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stringlengths 6
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stringlengths 6
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int64 1
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| size
int64 137
1.04M
| content
stringlengths 137
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stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
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float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
KimSJ/HDLC_chip
|
arduinointerface_tb.vhd
| 1 | 3,083 |
-- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming strb is left high between accesses)
-- set port low bits to input
-- set RmW, strb to 1, 0 (10 = command "read low-nibble")
-- read the value
-- set strb 1 (11 = command "read high-nibble)
-- read the value
-- for multi-byte reads, repeat last four steps
-- to write this peripheral:
-- (assuming strb is left high between accesses)
-- set RnW to 0 (strb no change, so no write yet; output buffers now disabled)
-- set port low bits to output
-- write the lo-nibble value, with b5, b4 = 00
-- write the hi-nibble value, with b5, b4 = 01
-- for multi-byte writes, repeat last two steps
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity arduinointerface_tb is
end entity arduinointerface_tb;
architecture behavioural of arduinointerface_tb is
signal RnW : Std_Logic := '1';
signal strb : Std_Logic := '1';
signal clock: Std_Logic;
signal rst: Std_Logic :='1';
signal bidir : Std_Logic_Vector (3 downto 0) := "ZZZZ"; -- the databus
signal rd, wr: Std_Logic;
signal q, i : Std_Logic_Vector (7 downto 0) := x"A5"; -- i is the values read on input, q is values output by write
signal cycle : integer :=0;
component arduinointerface is
port (
-- arduino pins
data: inout Std_Logic_Vector (3 downto 0);
strb: in Std_Logic;
RnW: in Std_Logic;
clk: in Std_Logic;
rst: in Std_Logic;
-- io pins
rd, wr: out Std_Logic;
q: out Std_Logic_Vector (7 downto 0);
i: in Std_Logic_Vector (7 downto 0)
);
end component arduinointerface;
subtype nibble is Std_Logic_Vector(3 downto 0);
type tDataItem is record
d: nibble;
RnW, strb: Std_Logic;
end record tDataItem;
type tDataList is array (0 to 5) of tDataItem;
constant dataList : tDataList := (
-- d, RnW, strb
-- read cycle
("ZZZZ", '1', '1'),
("ZZZZ", '1', '0'),
("ZZZZ", '1', '1'),
-- write cycle
("ZZZZ", '0', '1'),
("0001", '0', '0'),
("0010", '0', '1')
);
begin
iface : arduinointerface
port map (
data => bidir,
strb => strb,
RnW => RnW,
clk => clock,
rst => rst,
rd => rd,
wr => wr,
q => q,
i => i
);
rst <= '1' after 0 ns, '0' after 100 ns;
process
-- drive the txClock
begin
clock <= '0';
wait for 62 ns;
clock <= '1';
wait for 63 ns;
end process;
process (clock)
begin
if rising_edge(clock) then
cycle <= (cycle + 1) mod (10 * dataList'length);
if cycle = 0 then
i <= (i(0) & i(7 downto 1)) xor "0" & i(0) & "00" & i(0) & "0" & i(0) & "0";
end if;
if (cycle mod 10) = 0 then
bidir <= dataList(cycle/10).d;
RnW <= dataList(cycle/10).RnW;
strb <= dataList(cycle/10).strb;
end if;
end if;
end process;
end behavioural;
|
gpl-3.0
|
165b624b1054740473a7e1c207dcbdde
| 0.626338 | 2.911237 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE1-SoC/DE1_SoC_LT24_top_level.vhd
| 1 | 6,585 |
-- #############################################################################
-- DE1_SoC_LT24_top_level.vhd
-- ==========================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_LT24_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
GPIO_1_LT24_ADC_BUSY : in std_logic;
GPIO_1_LT24_ADC_CS_N : out std_logic;
GPIO_1_LT24_ADC_DCLK : out std_logic;
GPIO_1_LT24_ADC_DIN : out std_logic;
GPIO_1_LT24_ADC_DOUT : in std_logic;
GPIO_1_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_1_LT24_CS_N : out std_logic;
GPIO_1_LT24_D : out std_logic_vector(15 downto 0);
GPIO_1_LT24_LCD_ON : out std_logic;
GPIO_1_LT24_RD_N : out std_logic;
GPIO_1_LT24_RESET_N : out std_logic;
GPIO_1_LT24_RS : out std_logic;
GPIO_1_LT24_WR_N : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_LT24_top_level;
architecture rtl of DE1_SoC_LT24_top_level is
begin
end;
|
unlicense
|
d1b6ad8a9d5e034ab12db8c8cbe45a43
| 0.50858 | 3.137208 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/CHAR_ROM/example_design/CHAR_ROM_exdes.vhd
| 1 | 4,330 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: CHAR_ROM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY CHAR_ROM_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END CHAR_ROM_exdes;
ARCHITECTURE xilinx OF CHAR_ROM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT CHAR_ROM IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : CHAR_ROM
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
b4b0aaa3014e32aa47ee03a10af59420
| 0.574134 | 4.795127 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_test/fp23_complex_tst_m1.vhd
| 1 | 7,680 |
-------------------------------------------------------------------------------
--
-- Title : fp23_complex_tst_m1
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : floating point multiplier
--
-------------------------------------------------------------------------------
--
-- Version 1.0 19.12.2015
-- Description: Complex floating point multiplier for tests only
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.fp_m1_pkg.all;
entity fp23_complex_tst_m1 is
generic (
td : time:=1ns --! Time delay for simulation
);
port(
ARE : in STD_LOGIC_VECTOR(15 downto 0); --! Real part of A
AIM : in STD_LOGIC_VECTOR(15 downto 0); --! Imag part of A
BRE : in STD_LOGIC_VECTOR(15 downto 0); --! Real part of B
BIM : in STD_LOGIC_VECTOR(15 downto 0); --! Imag part of B
ENA : in STD_LOGIC; --! Input data enable
CRE : out STD_LOGIC_VECTOR(15 downto 0); --! Real part of C
CIM : out STD_LOGIC_VECTOR(15 downto 0); --! Imag part of C
VAL : out STD_LOGIC; --! Output data valid
SCALE : in STD_LOGIC_VECTOR(05 downto 0); --! SCALE for FP converter
RESET : in STD_LOGIC; --! Reset
CLK : in STD_LOGIC --! Clock
);
end fp23_complex_tst_m1;
architecture test_fp23_cm_m1 of fp23_complex_tst_m1 is
signal are_z : std_logic_vector(15 downto 0);
signal aim_z : std_logic_vector(15 downto 0);
signal bre_z : std_logic_vector(15 downto 0);
signal bim_z : std_logic_vector(15 downto 0);
signal ena_z : std_logic_vector(03 downto 0);
signal rst : std_logic_vector(11 downto 0);
signal fp23_aa : fp23_complex;
signal fp23_bb : fp23_complex;
signal fp23_val : std_logic;
signal fp23_are_bre : fp23_data;
signal fp23_are_bim : fp23_data;
signal fp23_aim_bre : fp23_data;
signal fp23_aim_bim : fp23_data;
signal fp23_mult : std_logic;
signal fp23_cc : fp23_complex;
signal fp23_add : std_logic;
signal fix_cc_re : std_logic_vector(15 downto 0);
signal fix_cc_im : std_logic_vector(15 downto 0);
signal fix_val : std_logic;
signal scale_z : std_logic_vector(5 downto 0);
begin
are_z <= ARE after td when rising_edge(clk);
aim_z <= AIM after td when rising_edge(clk);
bre_z <= BRE after td when rising_edge(clk);
bim_z <= BIM after td when rising_edge(clk);
---------------- FIX2FLOAT CONVERTER ----------------
ARE_CONV : entity work.fp23_fix2float
generic map( td => td)
port map (
din => are_z,
ena => ena_z(0),
dout => fp23_aa.re,
vld => fp23_val,
reset => rst(0),
clk => clk
);
AIM_CONV : entity work.fp23_fix2float
generic map( td => td)
port map (
din => aim_z,
ena => ena_z(1),
dout => fp23_aa.im,
vld => open,
reset => rst(1),
clk => clk
);
BRE_CONV : entity work.fp23_fix2float
generic map( td => td)
port map (
din => bre_z,
ena => ena_z(2),
dout => fp23_bb.re,
vld => open,
reset => rst(2),
clk => clk
);
BIM_CONV : entity work.fp23_fix2float
port map (
din => bim_z,
ena => ena_z(3),
dout => fp23_bb.im,
vld => open,
reset => rst(3),
clk => clk
);
---------------- FlOAT MULTIPLY A*B ----------------
ARExBRE : entity work.fp23_mult
generic map( td => td)
port map (
aa => fp23_aa.re,
bb => fp23_bb.re,
cc => fp23_are_bre,
enable => fp23_val,
valid => fp23_mult,
reset => rst(4),
clk => clk
);
AIMxBIM : entity work.fp23_mult
port map(
aa => fp23_aa.im,
bb => fp23_bb.im,
cc => fp23_aim_bim,
enable => fp23_val,
valid => open,
reset => rst(5),
clk => clk
);
ARExBIM : entity work.fp23_mult
generic map( td => td)
port map (
aa => fp23_aa.re,
bb => fp23_bb.im,
cc => fp23_are_bim,
enable => fp23_val,
valid => open,
reset => rst(6),
clk => clk
);
AIMxBRE : entity work.fp23_mult
generic map( td => td)
port map (
aa => fp23_aa.im,
bb => fp23_bb.re,
cc => fp23_aim_bre,
enable => fp23_val,
valid => open,
reset => rst(7),
clk => clk
);
---------------- FlOAT ADD/SUB +/- ----------------
AB_ADD : entity work.fp23_addsub
generic map( td => td)
port map (
aa => fp23_are_bim,
bb => fp23_aim_bre,
cc => fp23_cc.im,
addsub => '0',
enable => fp23_mult,
valid => fp23_add,
reset => rst(8),
clk => clk
);
AB_SUB : entity work.fp23_addsub
generic map( td => td)
port map (
aa => fp23_are_bre,
bb => fp23_aim_bim,
cc => fp23_cc.re,
addsub => '1',
enable => fp23_mult,
valid => open,
reset => rst(9),
clk => clk
);
---------------- FLOAT TO FIX ----------------
scale_z <= scale after td when rising_edge(clk);
FIX_RE : entity work.fp23_float2fix
generic map( td => td)
port map (
din => fp23_cc.re,
ena => fp23_add,
dout => fix_cc_re,
vld => fix_val,
scale => scale_z,
reset => rst(10),
clk => clk,
overflow => open
);
FIX_IM : entity work.fp23_float2fix
generic map( td => td)
port map (
din => fp23_cc.im,
ena => fp23_add,
dout => fix_cc_im,
vld => open,
scale => scale_z,
reset => rst(11),
clk => clk,
overflow => open
);
CRE <= fix_cc_re after td when rising_edge(clk);
CIM <= fix_cc_im after td when rising_edge(clk);
VAL <= fix_val after td when rising_edge(clk);
G_ENA: for ii in 0 to 3 generate
ena_z(ii) <= ENA after td when rising_edge(clk);
end generate;
G_RST: for ii in 0 to 11 generate
rst(ii) <= RESET after td when rising_edge(clk);
end generate;
end test_fp23_cm_m1;
|
mit
|
594562c8ed5f177ee898572f09b0c61b
| 0.523698 | 2.973287 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano-SoC/DE0_Nano_SoC_TRDB_D5M_top_level.vhd
| 1 | 4,319 |
-- #############################################################################
-- DE0_Nano_SoC_TRDB_D5M_top_level.vhd
-- ===================================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_TRDB_D5M_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
GPIO_1_D5M_FVAL : in std_logic;
GPIO_1_D5M_LVAL : in std_logic;
GPIO_1_D5M_PIXCLK : in std_logic;
GPIO_1_D5M_RESET_N : out std_logic;
GPIO_1_D5M_SCLK : inout std_logic;
GPIO_1_D5M_SDATA : inout std_logic;
GPIO_1_D5M_STROBE : in std_logic;
GPIO_1_D5M_TRIGGER : out std_logic;
GPIO_1_D5M_XCLKIN : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_TRDB_D5M_top_level;
architecture rtl of DE0_Nano_SoC_TRDB_D5M_top_level is
begin
end;
|
unlicense
|
6cedd0660d5d5ccfed304d35ef31c78f
| 0.511693 | 3.109431 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
DE10/pll73728.vhd
| 1 | 17,865 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll73728.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll73728 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
);
END pll73728;
ARCHITECTURE SYN OF pll73728 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 3125,
clk0_duty_cycle => 50,
clk0_multiply_by => 2304,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 3125,
clk2_duty_cycle => 50,
clk2_multiply_by => 768,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "MAX 10",
lpm_hint => "CBX_MODULE_PREFIX=pll73728",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.863998"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.288000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.86400000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.28800000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll73728.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3125"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2304"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3125"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "768"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll73728.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll73728.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll73728.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll73728.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll73728.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll73728_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-2.0
|
e1a1c0c44ea6fa217d1df203918c2f5c
| 0.701707 | 3.307721 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/reduce_pack.vhd
| 1 | 13,790 |
-- --------------------------------------------------------------------
--
-- Copyright 2002 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE [Draft] Standard 1076.3
-- reduce_pkg
-- This source file may not be copied, sold, or included
-- with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this
-- [draft] standard and may be distributed in compiled form in any manner so
-- long as the compiled form does not allow direct decompilation of the
-- original source file. This source file may be copied for individaul use
-- between licensed users.
--
-- The IEEE disclaims any responsibility or liability for damages resulting
-- from misinterpretation or misue of said information by the user.
--
-- [This source file represents a portion of the IEEE Draft Standard and is
-- unapproved and subject to change.]
--
-- < statement about permission to modify >
--
-- Title : REDUCE_PKG < IEEE std # 1076.3 >
--
-- Library : This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL/Synthesis, PAR 1076.3
--
-- Purpose : Reduction operations. This allows a vector to
-- be collapsed into a signle bit. Similar to the built
-- in functions in Verilog.
--
-- Limitation:
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 1.3
-- Date : 8 July 2002
-- Added "to_x01" on all inputs.
-- Made "and_reduce" return a "1" in the NULL case.
-- -------------------------------------------------------------------------
-- Version: 1.2
-- Date : 21 June 2002
-- Fixed some basic logic errors.
-- -------------------------------------------------------------------------
-- Version: 1.1
-- Date : 13 May 2002
-- Modified to deal with null arrays, added IEEE header.
-- -------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
-- Package definition
package reduce_pack is
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- bit_vector versions
FUNCTION and_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
end reduce_pack;
-- Package body.
package body reduce_pack is
-- done in a recursively called function.
function and_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '1'; -- Change for version 1.3
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) and BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper and Lower;
end if;
end if;
return Result;
end;
function nand_reduce (arg : std_logic_vector )
return std_logic is
begin
return not and_reduce (arg);
end;
function or_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) or BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper or Lower;
end if;
end if;
return Result;
end;
function nor_reduce (arg : std_logic_vector )
return std_logic is
begin
return not or_reduce ( arg );
end;
function xor_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper xor Lower;
end if;
end if;
return Result;
end;
function xnor_reduce (arg : std_logic_vector )
return std_logic is
begin
return not xor_reduce ( arg );
end;
function and_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : SIGNED )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : UNSIGNED )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : SIGNED )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : UNSIGNED )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : SIGNED )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : UNSIGNED )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : SIGNED )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : UNSIGNED )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : SIGNED )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : UNSIGNED )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : SIGNED )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : UNSIGNED )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : bit_vector )
return bit is
begin
return to_bit (and_reduce (to_stdlogicvector ( arg )));
end;
function nand_reduce (arg : bit_vector )
return bit is
begin
return to_bit (nand_reduce (to_stdlogicvector ( arg )));
end;
function or_reduce (arg : bit_vector )
return bit is
begin
return to_bit (or_reduce (to_stdlogicvector ( arg )));
end;
function nor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (nor_reduce (to_stdlogicvector ( arg )));
end;
function xor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (xor_reduce (to_stdlogicvector ( arg )));
end;
function xnor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (xnor_reduce (to_stdlogicvector ( arg )));
end;
end reduce_pack;
|
mit
|
525e2a51cae77742298630e19df00721
| 0.605439 | 3.818887 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/controllers/ram_io.vhd
| 1 | 1,410 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ram_io IS
PORT(
in_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_push_buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
in_switches : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
in_we : IN STD_LOGIC;
in_en : IN STD_LOGIC;
in_clk : IN STD_LOGIC;
-------------------------------------------
out_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_hex : BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ram_io;
ARCHITECTURE behavioral OF ram_io IS
SIGNAL s_ram_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_io_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
ram: ENTITY WORK.ram(behavioral)
GENERIC MAP
(
g_addr_width => 10
)
PORT MAP
(
in_data,
in_addr(9 DOWNTO 0),
in_we,
(in_en AND NOT(in_addr(31))),
in_clk,
-----------------------------
s_ram_data_out
);
io: ENTITY WORK.io_controller(behavioral)
PORT MAP
(
in_data,
in_addr,
in_we,
(in_en AND in_addr(31)),
in_clk,
in_push_buttons,
in_switches,
-------------------------------------------
s_io_data_out,
out_hex
);
data_control_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 1
)
PORT MAP
(
in_i(0) => s_ram_data_out,
in_i(1) => s_io_data_out,
in_sel => in_addr(31 DOWNTO 31),
out_o => out_data
);
END behavioral;
|
mit
|
a8d3c2c60b68bd2d04b1bec59cb8ff15
| 0.560993 | 2.701149 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano/DE0_Nano_TRDB_D5M_top_level.vhd
| 1 | 2,809 |
-- #############################################################################
-- DE0_Nano_TRDB_D5M_top_level.vhd
-- ===============================
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_TRDB_D5M_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
LED : out std_logic_vector(7 downto 0);
-- KEY_N
KEY_N : in std_logic_vector(1 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
EPCS_ASDO : out std_logic;
EPCS_DATA0 : in std_logic;
EPCS_DCLK : out std_logic;
EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
G_SENSOR_CS_N : out std_logic;
G_SENSOR_INT : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
GPIO_2 : inout std_logic_vector(12 downto 0);
GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic;
-- GPIO_1
GPIO_1 : inout std_logic_vector(33 downto 0);
GPIO_1_IN : in std_logic_vector(1 downto 0)
);
end entity DE0_Nano_TRDB_D5M_top_level;
architecture rtl of DE0_Nano_TRDB_D5M_top_level is
begin
end;
|
unlicense
|
d09654d911b71a2e631c1aa0f282619c
| 0.507654 | 3.206621 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/util/HexDisplay.vhd
| 1 | 1,294 |
-------------------------------------
-- Hex display controller --
-- PORT MAPPING --
-- Value : 4 bit input value --
-------------------------------------
-- OUT : 7 bit output value --
-------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY hex_display IS
PORT
(
in_value : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out_display : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END hex_display;
ARCHITECTURE behavioral OF hex_display IS
BEGIN
PROCESS(in_value)
BEGIN
CASE in_value IS
WHEN "0000" => out_display <= "0000001";
WHEN "0001" => out_display <= "1001111";
WHEN "0010" => out_display <= "0010010";
WHEN "0011" => out_display <= "0000110";
WHEN "0100" => out_display <= "1001100";
WHEN "0101" => out_display <= "0100100";
WHEN "0110" => out_display <= "0100000";
WHEN "0111" => out_display <= "0001111";
WHEN "1000" => out_display <= "0000000";
WHEN "1001" => out_display <= "0000100";
WHEN "1010" => out_display <= "0001000";
WHEN "1011" => out_display <= "1100000";
WHEN "1100" => out_display <= "0110001";
WHEN "1101" => out_display <= "1000010";
WHEN "1110" => out_display <= "0110000";
WHEN "1111" => out_display <= "0111000";
END CASE;
END PROCESS;
END behavioral;
|
mit
|
eb90839e81fc74d978f8e76bf7873cb0
| 0.544822 | 3.37859 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab9_new/lab9_new_lib/hdl/mini_alu_struct.vhd
| 1 | 10,180 |
-- VHDL Entity lab9_new_lib.mini_ALU.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 03:34:23 04/26/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mini_ALU IS
PORT(
ALU_cin : IN std_logic;
ALU_mode : IN std_logic;
Left : IN std_logic_vector (15 DOWNTO 0);
Right : IN std_logic_vector (15 DOWNTO 0);
operation : IN std_logic_vector (3 DOWNTO 0);
pcval : IN std_logic_vector (15 DOWNTO 0);
ALU_Result : OUT std_logic_vector (15 DOWNTO 0);
ALU_cout : OUT std_logic;
Is_negative : OUT std_logic;
Is_ovfl : OUT std_logic;
Is_zero : OUT std_logic;
next_pc_val : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END mini_ALU ;
--
-- VHDL Architecture lab9_new_lib.mini_ALU.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 03:34:23 04/26/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF mini_ALU IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout1 : std_logic_vector(15 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL ALU_Result_internal : std_logic_vector (15 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'custom_ALU' of 'alu181'
SIGNAL mw_custom_ALUa_in : std_logic_vector(15 DOWNTO 0);
SIGNAL mw_custom_ALUb_in : std_logic_vector(15 DOWNTO 0);
SIGNAL mw_custom_ALUaout : unsigned(15 DOWNTO 0);
SIGNAL mw_custom_ALUlout : std_logic_vector(15 DOWNTO 0);
SIGNAL mw_custom_ALUcarryout : std_logic;
BEGIN
-- ModuleWare code(v1.12) for instance 'custom_Adder' of 'add'
custom_addercombo_proc: PROCESS (pcval, dout1)
VARIABLE temp_din0 : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_sum : unsigned(16 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & pcval;
temp_din1 := '0' & dout1;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
next_pc_val <= conv_std_logic_vector(temp_sum(15 DOWNTO 0),16);
END PROCESS custom_addercombo_proc;
-- ModuleWare code(v1.12) for instance 'custom_ALU' of 'alu181'
ALU_cout <= mw_custom_ALUcarryout AND (NOT(ALU_mode));
Is_ovfl <= (mw_custom_ALUcarryout) AND (NOT(ALU_mode));
custom_aluarith_proc: PROCESS (mw_custom_ALUa_in, mw_custom_ALUb_in, ALU_cin)
VARIABLE temp_atemp : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_btemp : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_otemp : unsigned(16 DOWNTO 0);
VARIABLE temp_carryin : std_logic;
BEGIN
temp_atemp := '0' & mw_custom_ALUa_in;
temp_btemp := '0' & mw_custom_ALUb_in;
temp_carryin := ALU_cin;
temp_otemp := (unsigned(temp_atemp) + unsigned(temp_btemp) + temp_carryin);
mw_custom_ALUaout <= temp_otemp(15 DOWNTO 0);
mw_custom_ALUcarryout <= temp_otemp(16) ;
END PROCESS custom_aluarith_proc;
custom_alufdrive_proc: PROCESS (mw_custom_ALUaout, mw_custom_ALUlout, ALU_mode)
BEGIN
IF (ALU_mode = '1') THEN
ALU_Result_internal <= mw_custom_ALUlout;
ELSIF (ALU_mode = '0') THEN
ALU_Result_internal <= std_logic_vector(mw_custom_ALUaout);
ELSE
ALU_Result_internal <= (OTHERS => 'X');
END IF;
END PROCESS custom_alufdrive_proc;
custom_alumux_proc: PROCESS (operation, Left, Right)
VARIABLE temp_or0 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_and0 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_not_a : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_tain0 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_or1 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_and1 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_not_b : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_tain1 : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_orout : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_andout : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_xorout : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_ltemp : std_logic_vector(15 DOWNTO 0);
VARIABLE temp_s3_0 : std_logic_vector (3 DOWNTO 0);
CONSTANT S0 :std_logic_vector(3 DOWNTO 0 ) := "0000";
CONSTANT S1 :std_logic_vector(3 DOWNTO 0 ) := "0001";
CONSTANT S2 :std_logic_vector(3 DOWNTO 0 ) := "0010";
CONSTANT S3 :std_logic_vector(3 DOWNTO 0 ) := "0011";
CONSTANT S4 :std_logic_vector(3 DOWNTO 0 ) := "0100";
CONSTANT S5 :std_logic_vector(3 DOWNTO 0 ) := "0101";
CONSTANT S6 :std_logic_vector(3 DOWNTO 0 ) := "0110";
CONSTANT S7 :std_logic_vector(3 DOWNTO 0 ) := "0111";
CONSTANT S8 :std_logic_vector(3 DOWNTO 0 ) := "1000";
CONSTANT S9 :std_logic_vector(3 DOWNTO 0 ) := "1001";
CONSTANT S10 :std_logic_vector(3 DOWNTO 0 ) := "1010";
CONSTANT S11 :std_logic_vector(3 DOWNTO 0 ) := "1011";
CONSTANT S12 :std_logic_vector(3 DOWNTO 0 ) := "1100";
CONSTANT S13 :std_logic_vector(3 DOWNTO 0 ) := "1101";
CONSTANT S14 :std_logic_vector(3 DOWNTO 0 ) := "1110";
CONSTANT S15 :std_logic_vector(3 DOWNTO 0 ) := "1111";
BEGIN
temp_s3_0 := operation;
temp_or1 := (OTHERS => '0');
temp_or0 := (OTHERS => '0');
temp_and1 := (OTHERS => '1');
temp_and0 := (OTHERS => '1');
temp_not_a := NOT(Left);
temp_not_b := NOT(Right);
CASE temp_s3_0 IS
WHEN S1 =>
temp_or0 := temp_not_a;
temp_or1 := temp_not_b;
temp_and0 := Left;
temp_and1 := Right;
WHEN S2 =>
temp_or0 := temp_not_a;
temp_or1 := Right;
temp_and0 := Left;
temp_and1 := temp_not_b;
WHEN S4 =>
temp_and0 := temp_not_a;
temp_and1 := temp_not_b;
temp_or0 := Left;
temp_or1 := temp_not_b;
WHEN S5 =>
temp_and0 := Left;
temp_and1 := Right;
temp_or0 := Left;
temp_or1 := temp_not_b;
WHEN S6 =>
temp_and0 := temp_not_a;
temp_and1 := temp_not_b;
WHEN S7 =>
temp_or0 := Left;
temp_or1 := temp_not_b;
WHEN S8 =>
temp_and0 := temp_not_a;
temp_and1 := Right;
temp_or0 := Left;
temp_or1 := Right;
WHEN S9 =>
temp_or0 := Left;
temp_or1 := Right;
WHEN S10 =>
temp_and0 := Left;
temp_and1 := temp_not_b;
temp_or0 := Left;
temp_or1 := Right;
WHEN S11 =>
temp_or0 := Left;
temp_or1 := Right;
WHEN S13 | S14 =>
temp_and0 := Left;
temp_and1 := Right;
temp_or0 := temp_not_a;
temp_or1 := Right;
WHEN OTHERS =>
temp_and0 := (OTHERS => 'X');
temp_and1 := (OTHERS => 'X');
temp_or0 := (OTHERS => 'X');
temp_or1 := (OTHERS => 'X');
END CASE;
temp_xorout := Left XOR Right;
temp_andout := temp_and0 AND temp_and1;
temp_orout := temp_or0 OR temp_or1;
temp_tain0 := (OTHERS => '0');
temp_tain1 := (OTHERS => '1'); -- minus 1
temp_ltemp := (OTHERS => '0');
CASE temp_s3_0 IS
WHEN S0 =>
temp_ltemp := temp_not_a;
temp_tain0 := Left;
WHEN S1 | S2 =>
temp_ltemp := temp_orout;
temp_tain0 := temp_andout;
WHEN S3 =>
temp_ltemp := (OTHERS => '0');
temp_ltemp(0) := '1';
WHEN S4 =>
temp_ltemp := temp_andout;
temp_tain0 := Left;
temp_tain1 := temp_orout;
WHEN S5 =>
temp_ltemp := temp_not_b;
temp_tain0 := temp_andout;
temp_tain1 := temp_orout;
WHEN S6 =>
temp_ltemp := NOT(temp_xorout);
temp_tain0 := Left;
temp_tain1 := temp_not_b;
WHEN S7 =>
temp_ltemp := temp_orout;
temp_tain1 := temp_orout;
WHEN S8 =>
temp_ltemp := temp_andout;
temp_tain0 := Left;
temp_tain1 := temp_orout;
WHEN S9 =>
temp_ltemp := temp_xorout;
temp_tain0 := Left;
temp_tain1 := Right;
WHEN S10 =>
temp_ltemp := Right;
temp_tain0 := temp_andout;
temp_tain1 := temp_orout;
WHEN S11 =>
temp_ltemp := temp_orout;
temp_tain1 := temp_orout;
WHEN S12 =>
temp_ltemp := (OTHERS => '0');
temp_tain0 := Left;
temp_tain1 := Left;
WHEN S13 =>
temp_ltemp := NOT(temp_orout);
temp_tain0 := temp_andout;
temp_tain1 := Left;
WHEN S14 =>
temp_ltemp := temp_andout;
temp_tain0 := NOT(temp_orout);
temp_tain1 := Left;
WHEN S15 =>
temp_ltemp := Left;
temp_tain1 := Left;
WHEN OTHERS =>
temp_ltemp := (OTHERS => 'X');
temp_tain0 := (OTHERS => 'X');
temp_tain1 := (OTHERS => 'X');
END CASE;
mw_custom_ALUlout <= temp_ltemp;
mw_custom_ALUa_in <= temp_tain0;
mw_custom_ALUb_in <= temp_tain1;
END PROCESS custom_alumux_proc;
-- ModuleWare code(v1.12) for instance 'Comparator' of 'cmp'
comparatorcombo_proc : PROCESS (ALU_Result_internal, dout)
VARIABLE temp_lgt : std_logic;
VARIABLE temp_leq : std_logic;
BEGIN
temp_lgt := '0';
temp_leq := '0';
IF (signed(ALU_Result_internal) > signed(dout)) THEN
temp_lgt := '1';
ELSIF (signed(ALU_Result_internal) = signed(dout)) THEN
temp_leq := '1';
END IF;
Is_zero <= temp_leq;
Is_negative <= NOT(temp_lgt OR temp_leq);
END PROCESS comparatorcombo_proc;
-- ModuleWare code(v1.12) for instance 'ZERO' of 'constval'
dout <= "0000000000000000";
-- ModuleWare code(v1.12) for instance 'pc_increment_Amount' of 'constval'
dout1 <= "0000000000000001";
-- Instance port mappings.
-- Implicit buffered output assignments
ALU_Result <= ALU_Result_internal;
END struct;
|
gpl-2.0
|
768c75fe9b1a2eade4c533174fd58ee1
| 0.5722 | 3.259686 | false | false | false | false |
a4a881d4/ringbus
|
simio/ademulator.vhd
| 1 | 1,716 |
-- This unit will simulate a DSP
-- It will read form a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity ADemulator is
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' ));
end ADemulator;
architecture behavior of ADemulator is
signal state: integer:=0;
constant StrLength : integer :=(DATA_WIDTH+1)/4;
begin
process( clk )
variable buf: line ;
variable lineno:integer:=0;
FILE data_file: TEXT IS IN AD_FILE;
variable dataTemp: std_logic_vector(15 downto 0):="0000000000000000";
variable booval: boolean :=false;
variable strData : string(StrLength downto 1);
begin
if(AD_FILE = "UNUSED") then
ASSERT FALSE
REPORT "file not found!"
SEVERITY WARNING;
end if;
if clk'event and clk='1' then
if ce='1' then
if NOT ENDFILE(data_file) then
booval := true;
READLINE(data_file, buf);
lineno:=lineno+1;
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
dataTemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),16);
data<=dataTemp(DATA_WIDTH-1 downto 0 );
else
data <= ( others => '0' );
end if;
end if;
end if;
end process;
end behavior;
|
lgpl-3.0
|
20e04e130cfb526e915be57534eba401
| 0.583333 | 3.384615 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab9_new/lab9_new_lib/hdl/mini_Shifter_Behavior.vhd
| 1 | 4,073 |
--
-- VHDL Architecture lab9_new_lib.mini_Shifter.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 10:59:42 04/21/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mini_Shifter IS
PORT(
shifter_In: IN std_logic_vector(15 downto 0); -- input
shift_operation: IN std_logic_vector(3 downto 0); -- shift operation
shifter_Out: OUT std_logic_vector(15 downto 0); -- Output
from_Carry_CCR: IN std_logic; -- value from the Carry CCR (Condition Code Register)
to_Carry_CCR: OUT std_logic -- value to be stored in the Carry CCR
);
END ENTITY mini_Shifter;
--
ARCHITECTURE Behavior OF mini_Shifter IS
BEGIN
PROCESS(all)
variable bit_Copy : std_logic; -- 1 bit variable
variable vector_Copy : std_logic_vector(14 downto 0); -- 1 bit shorter than the shifter input
variable shifter_Out_var : std_logic_vector(15 downto 0);
variable to_Carry_CCR_var : std_logic := '0';
BEGIN
CASE shift_operation IS
-- SL
when "1000" =>
bit_Copy := '0';
vector_Copy := shifter_In(14 downto 0);
shifter_Out_var := vector_Copy & bit_Copy; -- left shift
to_Carry_CCR_var := from_Carry_CCR; -- condition code not changed
-- SRL
when "1001" =>
bit_Copy := '0';
vector_Copy := shifter_In(15 downto 1);
shifter_Out_var := bit_Copy & vector_Copy; -- right shift (logical)
to_Carry_CCR_var := from_Carry_CCR; -- condition code not changed
-- SRA
when "1010" =>
bit_Copy := shifter_In(15);
vector_Copy := shifter_In(15 downto 1);
shifter_Out_var := bit_Copy & vector_Copy; -- right shift (arithmetic)
to_Carry_CCR_var := from_Carry_CCR; -- condition code not changed
-- RRA
when "1110" =>
to_Carry_CCR_var := shifter_In(0); -- * copy the least significant bit
bit_Copy := shifter_In(15); -- * copy the most significant bit
vector_Copy := shifter_In(15 downto 1);
shifter_Out_var := bit_Copy & vector_Copy;
-- RR
when "1101" =>
to_Carry_CCR_var := shifter_In(0); -- * copy the least significant bit
bit_Copy := from_Carry_CCR; -- * copy the carry condition bit
vector_Copy := shifter_In(15 downto 1);
shifter_Out_var := bit_Copy & vector_Copy; -- right shift
-- RL
when "1100" =>
bit_Copy := from_Carry_CCR; -- * copy the carry condition bit
to_Carry_CCR_var := shifter_In(15); -- * copy the most significant bit
vector_Copy := shifter_In(14 downto 0);
shifter_Out_var := vector_Copy & bit_Copy;
-- others
when others => shifter_Out_var := shifter_In; -- do nothing
to_Carry_CCR_var := from_Carry_CCR; -- condition code not changed
END CASE;
shifter_Out <= shifter_Out_var;
to_Carry_CCR <= to_Carry_CCR_var;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
03f512cc5ba791fc16365f376d994617
| 0.448809 | 4.500552 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab11_RegisterTracker/lab11_RegisterTracker_lib/hdl/Processor_Behavior.vhd
| 1 | 7,337 |
--
-- VHDL Architecture lab11_RegisterTracker_lib.Processor.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 15:43:22 04/19/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
ENTITY Processor IS
GENERIC( addr_size: positive := 4);
PORT( operand1_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
operand2_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
reserve_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
clear_Addr: IN std_logic_vector(addr_size-1 downto 0) := (others=>'0');
dependsOn_op1: In std_logic := '0'; -- whether the current instruction depends on Register value corresponding to operand 1
dependsOn_op2: In std_logic := '0'; -- whether the current instruction depends on Register value corresponding to operand 2
RegWrite_current: IN std_logic := '0'; -- Register writeback enable signal from the previous instruction (from WriteBack stage)
RegWrite_previous: IN std_logic := '0'; -- Register writeback enable signal from the current instruction (from Decode stage)
Register_Out: IN std_logic_vector(15 downto 0) := (others=>'0') ; -- values coming out of the Register
reset: IN std_logic := '0';
decode_pcval_out: IN std_logic_vector(15 DOWNTO 0);
-- *************** OUTPUTS **************************************************************
decode_pcval_out_TrackerOut: OUT std_logic_vector(15 DOWNTO 0);
can_move_on: OUT std_logic;
Register_In: OUT std_logic_vector(15 downto 0) -- input to be fed to the Register
);
END ENTITY Processor;
--
ARCHITECTURE Behavior OF Processor IS
BEGIN
p1: PROCESS(all)
CONSTANT ALL_ZERO: std_logic_vector(15 downto 0) := (others=>'0');
CONSTANT ALL_ONE: std_logic_vector(15 downto 0) := (others=>'1');
VARIABLE result_op1: std_logic_vector(15 downto 0); -- one-hot representation of operand 1's Register
VARIABLE result_op2: std_logic_vector(15 downto 0); -- one-hot representation of operand 2's Register
VARIABLE result_clear: std_logic_vector(15 downto 0); -- one-hot representation of the Register to clean (coming out from the Write Back stage)
VARIABLE result_reserve: std_logic_vector(15 downto 0); -- one-hot representation of the Register to reserve (for the Destination Register)
VARIABLE selection_op1: natural; -- integer representations, likewise
VARIABLE selection_op2: natural;
VARIABLE selection_clear: natural;
VARIABLE selection_reserve: natural;
VARIABLE upcoming_op1: std_logic; -- upcoming reservation status bit for operand 1's Register
VARIABLE upcoming_op2: std_logic; -- upcoming reservation status bit for operand 2's Register
VARIABLE can_move_on_var: std_logic := '1';
VARIABLE Register_Out_var: std_logic_vector(15 downto 0);
VARIABLE Register_In_var: std_logic_vector(15 downto 0);
VARIABLE decode_pcval_out_TrackerOut_var : std_logic_vector(15 downto 0); -- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
BEGIN
Register_Out_var := Register_Out; -- *** currently saved Register values
Register_In_var := Register_Out; -- *** currently saved Register values
decode_pcval_out_TrackerOut_var := decode_pcval_out;
selection_op1 := to_integer( ieee.numeric_std.unsigned(operand1_Addr) );
selection_op2 := to_integer( ieee.numeric_std.unsigned(operand2_Addr) );
-- If the Register for operand 1 is the same as Register to be cleared from Write-Back signal
IF( (selection_op1 = selection_clear) and (RegWrite_previous = '1') ) THEN
upcoming_op1 := '1';
ELSE
upcoming_op1 := Register_Out(selection_op1); -- upcoming status value for operand 1's Register
END IF;
-- If the Register for operand 2 is the same as Register to be cleared from Write-Back signal
IF( (selection_op2 = selection_clear) and (RegWrite_previous = '1') ) THEN
upcoming_op2 := '1';
ELSE
upcoming_op2 := Register_Out(selection_op2); -- upcoming status value for operand 2's Register
END IF;
-- Preprare bit masking for the clear Address
result_clear := ALL_ONE; -- pre-set all bits to 1
selection_clear := to_integer( ieee.numeric_std.unsigned(clear_Addr) );
IF( RegWrite_previous = '1') THEN
result_clear(selection_clear) := '0'; -- clear the reserved bit for previous instruction's destination
END IF;
-- Prepare bit masking for the reserve Address
result_reserve := ALL_ZERO; -- pre-set all bits to 0
selection_reserve := to_integer( ieee.numeric_std.unsigned(reserve_Addr) );
IF( RegWrite_current = '1') THEN
result_reserve(selection_reserve) := '1'; -- set a reserved bit for current instuction's destination
END IF;
-- Override the upcoming reservation status to 0 if the Register values are not needed in the instruction
IF( dependsOn_op1 /= '1') THEN
upcoming_op1 := '0';
END IF;
IF( dependsOn_op2 /= '1') THEN
upcoming_op2 := '0';
END IF;
-- If the Registers for both of the operands have not been reserved
IF( (upcoming_op1 = '0') and (upcoming_op2 = '0') ) THEN
can_move_on_var := '1'; -- can proceed with the next instruction
Register_In_var := Register_Out_var AND result_clear; -- *** clear the status bit corresponding to the clear Address (FIRST)
Register_In_var := Register_In_var OR result_reserve; -- *** reserve the status bit for the Destination Address (SECOND)
ELSE
can_move_on_var := '0'; -- stall
Register_In_var := Register_Out_var AND result_clear; -- *** clear the status bit corresponding to the clear Address
END IF;
-- If reset is enabled
IF( reset = '1') THEN
can_move_on_var := '1';
Register_In_var := (others=>'0');
END IF;
-- Finalize outputs
decode_pcval_out_TrackerOut <= decode_pcval_out_TrackerOut_var;
can_move_on <= can_move_on_var;
Register_In <= Register_In_var;
END PROCESS p1;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
edfe1db8c29f54670bb671563e80dda5
| 0.556086 | 4.411906 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/Uart.vhd
| 1 | 1,998 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UART is
port (
Clkin :in std_logic;
READin :in std_logic;
RXDin :in std_logic;
ASCIIin :in std_logic_vector (7 downto 0);
ASCII_out:out std_logic_vector (7 downto 0);
TXD_out :out std_logic;
READ_out : out std_logic);
end UART;
architecture Behavioral of UART is
signal TEST : std_logic;
signal CLKTXD : std_logic;
signal CLKRXD : std_logic;
signal X : std_logic_vector(1 downto 0);
-----------------------------------------------
component UartClkDiv
port(
CLKin : in std_logic;
CLKTXD_out : inout std_logic;
CLKRXD_out : inout std_logic);
end component;
-----------------------------------------------
component UartLogic is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
tx_out :out std_logic;
tx_empty :out std_logic;
---------------
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic);
end component;
-----------------------------------------------
begin
UART_CLK_DIV : UartClkDiv port map( CLKin => CLKin,
CLKTXD_out => CLKTXD,
CLKRXD_out => CLKRXD);
UART_LOGIC : UartLogic port map( reset => '0',
-------------------------
txclk => CLKTXD,
ld_tx_data => READin,
tx_data => ASCIIin,
tx_enable => '1',
tx_out => TXD_out,
tx_empty => X(0),
------------------------
rxclk => CLKRXD,
uld_rx_data => '1',
rx_data => ASCII_out,
rx_enable => '1',
rx_in => RXDin,
rx_empty => READ_out);
end Behavioral;
|
mit
|
0d0b112c7c0e199b0de8db4b8e90c7ae
| 0.471972 | 3.15142 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/controllers/io/IoBusController.vhd
| 1 | 1,887 |
----------------------------------------
-- IO controller --
-- PORT MAPPING --
-- data_in : 32 bit data input --
-- addr_in : 32 bit address input --
-- enable : 1 bit enable --
-- clk : 1 bit clock --
----------------------------------------
-- data_out : 32 bit data output --
----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY io_controller IS
PORT
(
in_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_we : IN STD_LOGIC;
in_en : IN STD_LOGIC;
in_clk : IN STD_LOGIC;
in_push_buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
in_switches : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
-------------------------------------------
out_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_hex : BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END io_controller;
ARCHITECTURE behavioral OF io_controller IS
BEGIN
-- DE2-115
-- HEX DISPLAYS
PROCESS(in_we, in_addr, in_en, in_clk)
BEGIN
IF(RISING_EDGE(in_clk) AND in_we = '1' AND in_en = '1') THEN
CASE(in_addr) IS
WHEN "10000000000000000000000000000000" =>
out_hex <= in_data;
WHEN OTHERS =>
END CASE;
END IF;
IF(RISING_EDGE(in_clk) AND in_we = '0' AND in_en = '1') THEN
CASE(in_addr) IS
WHEN "10000000000000000000000000000000" =>
out_data <= out_hex;
WHEN "11000000000000000000000000000000" =>
out_data <= "00000000000000000000000000000000";
out_data(3 DOWNTO 0) <= in_push_buttons;
WHEN "11000000000000000000000000000001" =>
out_data <= "00000000000000000000000000000000";
out_data(17 DOWNTO 0) <= in_switches;
WHEN OTHERS =>
out_data <= "10101010101010101010010101010101";
END CASE;
END IF;
END PROCESS;
END behavioral;
|
mit
|
f383922c4738c1c8ce9a38b9ed6750e0
| 0.54531 | 3.553672 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/dpram2k.vhd
| 1 | 2,050 |
-- A dual-port 2KiB RAM described as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram2k is
port(clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
addra : in std_logic_vector(10 downto 0);
addrb : in std_logic_vector(10 downto 0);
dia : in std_logic_vector(7 downto 0);
dib : in std_logic_vector(7 downto 0);
doa : out std_logic_vector(7 downto 0);
dob : out std_logic_vector(7 downto 0));
end dpram2k;
architecture syn of dpram2k is
type ram_type is array (0 to 2047) of std_logic_vector(7 downto 0);
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if CLKA'event and CLKA = '1' then
if ENA = '1' then
if WEA = '1' then
RAM(conv_integer(ADDRA)) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA));
end if;
end if;
end process;
process (CLKB)
begin
if CLKB'event and CLKB = '1' then
if ENB = '1' then
if WEB = '1' then
RAM(conv_integer(ADDRB)) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB));
end if;
end if;
end process;
end syn;
|
gpl-2.0
|
9937563a9de9525c1a00748c4b7518d9
| 0.646829 | 3.61552 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd
| 1 | 9,957 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 7
-- C_READ_WIDTH_A : 7
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 7
-- C_READ_WIDTH_B : 7
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
a50ef7e22998f859c526af2e5c4e3719
| 0.494727 | 3.771591 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano/DE0_Nano_LT24_top_level.vhd
| 1 | 2,979 |
-- #############################################################################
-- DE0_Nano_LT24_top_level.vhd
-- ===========================
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_LT24_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
LED : out std_logic_vector(7 downto 0);
-- KEY_N
KEY_N : in std_logic_vector(1 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
EPCS_ASDO : out std_logic;
EPCS_DATA0 : in std_logic;
EPCS_DCLK : out std_logic;
EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
G_SENSOR_CS_N : out std_logic;
G_SENSOR_INT : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
GPIO_2 : inout std_logic_vector(12 downto 0);
GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(33 downto 0);
GPIO_0_IN : in std_logic_vector(1 downto 0);
-- GPIO_1
GPIO_1_LT24_ADC_BUSY : in std_logic;
GPIO_1_LT24_ADC_CS_N : out std_logic;
GPIO_1_LT24_ADC_DCLK : out std_logic;
GPIO_1_LT24_ADC_DIN : out std_logic;
GPIO_1_LT24_ADC_DOUT : in std_logic;
GPIO_1_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_1_LT24_CS_N : out std_logic;
GPIO_1_LT24_D : out std_logic_vector(15 downto 0);
GPIO_1_LT24_LCD_ON : out std_logic;
GPIO_1_LT24_RD_N : out std_logic;
GPIO_1_LT24_RESET_N : out std_logic;
GPIO_1_LT24_RS : out std_logic;
GPIO_1_LT24_WR_N : out std_logic
);
end entity DE0_Nano_LT24_top_level;
architecture rtl of DE0_Nano_LT24_top_level is
begin
end;
|
unlicense
|
bb394b1f77cb34b88919f148b275ed13
| 0.503189 | 3.23102 | false | false | false | false |
fkmclane/AutoPidact
|
vhdl/AutoPidact.vhd
| 1 | 1,393 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AutoPidact is
port(
CLOCK_50_B5B : in std_logic;
GPIO : inout std_logic_vector(35 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end entity AutoPidact;
architecture RTL of AutoPidact is
signal mtr0_pwm : unsigned(2 downto 0);
signal mtr0 : std_logic;
signal mtr1_pwm : unsigned(2 downto 0);
signal mtr1 : std_logic;
signal mtr2_pwm : unsigned(2 downto 0);
signal mtr2 : std_logic;
signal mtr3_pwm : unsigned(0 downto 0);
signal mtr3 : std_logic;
begin
mtr0_pwm <= unsigned(GPIO(9 downto 7));
mtr1_pwm <= unsigned(GPIO(12 downto 10));
mtr2_pwm <= unsigned(GPIO(15 downto 13));
mtr3_pwm <= unsigned(GPIO(16 downto 16));
pwm0: entity work.PWM
generic map(cycle => 500000, width => 7)
port map(clk => CLOCK_50_B5B, pwm => mtr0_pwm, q => mtr0);
pwm1: entity work.PWM
generic map(cycle => 500000, width => 7)
port map(clk => CLOCK_50_B5B, pwm => mtr1_pwm, q => mtr1);
pwm2: entity work.PWM
generic map(cycle => 500000, width => 7)
port map(clk => CLOCK_50_B5B, pwm => mtr2_pwm, q => mtr2);
pwm3: entity work.PWM
generic map(cycle => 500000, width => 1)
port map(clk => CLOCK_50_B5B, pwm => mtr3_pwm, q => mtr3);
GPIO(3) <= mtr0;
GPIO(4) <= mtr1;
GPIO(5) <= mtr2;
GPIO(6) <= mtr3;
end RTL;
|
mit
|
025798c4c94fc65f541feae56abd1419
| 0.623833 | 2.797189 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab10_memory_stage/lab10_memory_stage_lib/hdl/memory_stage_struct.vhd
| 1 | 5,376 |
-- VHDL Entity lab10_memory_stage_lib.memory_stage.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 10:08:30 04/18/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY memory_stage IS
PORT(
Control : IN std_logic_vector (2 DOWNTO 0);
Data_In : IN std_logic_vector (15 DOWNTO 0);
Dest : IN std_logic_vector (3 DOWNTO 0);
Extra : IN std_logic_vector (15 DOWNTO 0);
Result : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
mdelay : IN std_logic;
Addr : OUT std_logic_vector (15 DOWNTO 0);
Control_toWB : OUT std_logic;
Data_Store : OUT std_logic_vector (15 DOWNTO 0);
Dest_toWB : OUT std_logic_vector (3 DOWNTO 0);
R : OUT std_logic;
Value_toWB : OUT std_logic_vector (15 DOWNTO 0);
W : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
END memory_stage ;
--
-- VHDL Architecture lab10_memory_stage_lib.memory_stage.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 01:11:45 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF memory_stage IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL RegWrite : std_logic;
SIGNAL dout : std_logic;
SIGNAL not_mdelay : std_logic;
SIGNAL q : std_logic_vector(2 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL Addr_internal : std_logic_vector (15 DOWNTO 0);
SIGNAL R_internal : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'Control_Reg' of 'adff'
SIGNAL mw_Control_Regreg_cval : std_logic_vector(2 DOWNTO 0) := "000";
-- ModuleWare signal declarations(v1.12) for instance 'Data_Reg' of 'adff'
SIGNAL mw_Data_Regreg_cval : std_logic_vector(3 DOWNTO 0) := "0000";
-- ModuleWare signal declarations(v1.12) for instance 'Extra_Reg' of 'adff'
SIGNAL mw_Extra_Regreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'Result_Reg' of 'adff'
SIGNAL mw_Result_Regreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'split'
SIGNAL mw_U_4temp_din : std_logic_vector(2 DOWNTO 0);
BEGIN
-- ModuleWare code(v1.12) for instance 'Control_Reg' of 'adff'
q <= mw_Control_Regreg_cval;
control_regseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (not_mdelay = '1') THEN
mw_Control_Regreg_cval <= Control;
END IF;
END IF;
END PROCESS control_regseq_proc;
-- ModuleWare code(v1.12) for instance 'Data_Reg' of 'adff'
Dest_toWB <= mw_Data_Regreg_cval;
data_regseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (not_mdelay = '1') THEN
mw_Data_Regreg_cval <= Dest;
END IF;
END IF;
END PROCESS data_regseq_proc;
-- ModuleWare code(v1.12) for instance 'Extra_Reg' of 'adff'
Data_Store <= mw_Extra_Regreg_cval;
extra_regseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (not_mdelay = '1') THEN
mw_Extra_Regreg_cval <= Extra;
END IF;
END IF;
END PROCESS extra_regseq_proc;
-- ModuleWare code(v1.12) for instance 'Result_Reg' of 'adff'
Addr_internal <= mw_Result_Regreg_cval;
result_regseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (not_mdelay = '1') THEN
mw_Result_Regreg_cval <= Result;
END IF;
END IF;
END PROCESS result_regseq_proc;
-- ModuleWare code(v1.12) for instance 'buf' of 'buff'
stall <= mdelay;
-- ModuleWare code(v1.12) for instance 'Stall_Equiv' of 'constval'
dout <= '0';
-- ModuleWare code(v1.12) for instance 'mdelay_inverter' of 'inv'
not_mdelay <= NOT(mdelay);
-- ModuleWare code(v1.12) for instance 'Control_MUX' of 'mux'
control_muxcombo_proc: PROCESS(RegWrite, dout, mdelay)
BEGIN
CASE mdelay IS
WHEN '0' => Control_toWB <= RegWrite;
WHEN '1' => Control_toWB <= dout;
WHEN OTHERS => Control_toWB <= 'X';
END CASE;
END PROCESS control_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'Value_MUX' of 'mux'
value_muxcombo_proc: PROCESS(Addr_internal, Data_In, R_internal)
BEGIN
CASE R_internal IS
WHEN '0' => Value_toWB <= Addr_internal;
WHEN '1' => Value_toWB <= Data_In;
WHEN OTHERS => Value_toWB <= (OTHERS => 'X');
END CASE;
END PROCESS value_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'U_4' of 'split'
mw_U_4temp_din <= q;
u_4combo_proc: PROCESS (mw_U_4temp_din)
VARIABLE temp_din: std_logic_vector(2 DOWNTO 0);
BEGIN
temp_din := mw_U_4temp_din(2 DOWNTO 0);
W <= temp_din(0);
R_internal <= temp_din(1);
RegWrite <= temp_din(2);
END PROCESS u_4combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
Addr <= Addr_internal;
R <= R_internal;
END struct;
|
gpl-2.0
|
adcf4a44545c5c78c90223986eff3eaa
| 0.612165 | 3.38966 | false | false | false | false |
a4a881d4/ringbus
|
V3.0/ringbus/CSlave.vhd
| 1 | 2,958 |
---------------------------------------------------------------------------------------------------
--
-- Title : Control Bus Slave
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : CSlave.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Control bus Slave
--
-- Rev: 3.1
-- rd signal ahead data one clock
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
use work.contr_config.all;
entity CSlave is
generic(
Bwidth : natural := 16
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- send to bus
tx: out std_logic_vector( Bwidth-1 downto 0 );
Req : out std_logic;
tx_sop : in std_logic;
en : in std_logic;
-- read from bus
rx_sop : in std_logic;
rx: in std_logic_vector( Bwidth-1 downto 0 );
-- Local Bus
addr : out std_logic_vector( Bwidth-1 downto 0 );
Din : in STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
Dout : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 ) := (others => '0');
wr : out std_logic;
rd : out std_logic := '0'
--
);
end CSlave;
architecture behave of CSlave is
signal req_i : std_logic := '0';
signal command : std_logic_vector( command_end downto command_start ) := (others => '0');
signal state : natural := 0;
signal tx_i : std_logic_vector( Bwidth-1 downto 0 ) := (others => '0');
begin
req<=req_i;
tx<=tx_i;
FSM:process(clk,rst)
begin
if rst='1' then
state<=state_IDLE;
command<=(others=>'0');
addr<=(others=>'0');
dout<=(others=>'0');
req_i<='0';
wr<='0';
tx_i<=(others=>'0');
elsif rising_edge(clk) then
case state is
when state_IDLE =>
if rx_sop='1' then
command<=rx( command_end downto command_start );
state<=state_ADDR;
end if;
wr<='0';
when state_ADDR =>
addr<=rx;
state<=state_DATA;
when state_DATA =>
if command=command_read then
state<=state_pending;
req_i<='1';
tx_i<=rx;
elsif command=command_write then
wr<='1';
dout<=rx;
state<=state_idle;
else
state<=state_idle;
end if;
when state_pending =>
if en='1' and tx_sop='1' then
req_i<='0';
state<=state_SENDING;
end if;
when state_SENDING =>
tx_i<=din;
state<=state_IDLE;
when others =>
state<=state_IDLE;
end case;
end if;
end process;
rd<= '1' when state=state_pending and en='1' and tx_sop='1' else '0';
end behave;
|
lgpl-3.0
|
ab69491dd316f3e21236e5b4d41c5b11
| 0.481406 | 3.246981 | false | false | false | false |
fkmclane/AutoPidact
|
vhdl/ClockGenerator.vhd
| 1 | 596 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ClockGenerator is
generic(
count : natural := 50000000
);
port(
clk : in std_logic;
rst : in std_logic;
q : out std_logic
);
end entity ClockGenerator;
architecture RTL of ClockGenerator is
begin
process(clk, rst)
variable value : integer range 0 to count := 0;
begin
if (rst = '0') then
value := 0;
elsif (clk'event) and (clk = '1') then
value := value + 1;
end if;
if (value = count) then
value := 0;
q <= '1';
else
q <= '0';
end if;
end process;
end architecture RTL;
|
mit
|
12d6c1d249d0ffc8efa210ac3dd2a723
| 0.630872 | 2.851675 | false | false | false | false |
NESHomebrew/cs207-NES-Guitar-Synth
|
DesignLab Libraries/A138/Chip_Designer/Simulate_Your_Chip_Design.vhd
| 1 | 1,502 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library DesignLab;
--use DesignLab.ALL;
entity Simulate_Your_CCL_Design is
end entity;
architecture sim of Simulate_Your_CCL_Design is
constant period: time := 10 ns;
signal clk: std_logic := '1';
signal rst: std_logic := '0';
COMPONENT A138
PORT(
--Put your custom external connections here
buttons : IN std_logic_vector(3 downto 0);
leds : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Define your external connections here
signal buttons: std_logic_vector(3 downto 0) := "1010";
signal leds: std_logic_vector(3 downto 0);
begin
clk <= not clk after period/2;
-- Reset
process
begin
wait for 5 ns;
rst <= '1';
wait for 20 ns;
rst <= '0';
wait;
end process;
uut: A138 PORT MAP(
--Define your external connections here
buttons => buttons,
leds => leds
);
process
begin
wait until rst='1';
wait until rst='0';
wait until rising_edge(clk);
-- This is where you should start providing your stimulus to test your design.
-- Provide stimulus on the buttons
buttons <= "0000";
wait for 100 ns;
-- Check that the leds match
assert( leds = "0000");
-- Provide stimulus on the buttons
buttons <= "1111";
wait for 100 ns;
-- Check that the leds match
assert( leds = "1111");
wait for 200 ns;
report "Finsihed" severity failure;
end process;
end sim;
|
mit
|
c9f8ce6a050b44b5025ee04a1d2c035a
| 0.651798 | 3.429224 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab9_new/lab9_new_lib/hdl/execute_stage_struct.vhd
| 1 | 20,387 |
-- VHDL Entity lab9_new_lib.execute_stage.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 21:34:28 04/27/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY execute_stage IS
PORT(
Control : IN std_logic_vector (15 DOWNTO 0);
Dest : IN std_logic_vector (3 DOWNTO 0);
Extra : IN std_logic_vector (15 DOWNTO 0);
L : IN std_logic_vector (15 DOWNTO 0);
R : IN std_logic_vector (15 DOWNTO 0);
can_move_on : IN std_logic;
clk : IN std_logic;
pcval : IN std_logic_vector (15 DOWNTO 0);
rst : IN std_logic;
stall : IN std_logic;
Control_Out : OUT std_logic_vector (2 DOWNTO 0);
Dest_Execute_Out : OUT std_logic_vector (3 DOWNTO 0);
Extra_Execute_Out : OUT std_logic_vector (15 DOWNTO 0);
Result : OUT std_logic_vector (15 DOWNTO 0);
jaddress : OUT std_logic_vector (15 DOWNTO 0);
jump : OUT std_logic
);
-- Declarations
END execute_stage ;
--
-- VHDL Architecture lab9_new_lib.execute_stage.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 08:49:57 04/29/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY lab9_new_lib;
ARCHITECTURE struct OF execute_stage IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL ALU_Result : std_logic_vector(15 DOWNTO 0);
SIGNAL ALU_cin_Control : std_logic_vector(1 DOWNTO 0);
SIGNAL ALU_cout : std_logic;
SIGNAL ALU_mode_Control : std_logic;
SIGNAL Additional_Execute_Control : std_logic_vector(3 DOWNTO 0);
SIGNAL Carry_CCR_In : std_logic;
SIGNAL Carry_CCR_Out : std_logic;
SIGNAL Carry_CCR_enable : std_logic;
SIGNAL Control_Register_Out : std_logic_vector(15 DOWNTO 0);
SIGNAL Dest_Register_Out : std_logic_vector(3 DOWNTO 0);
SIGNAL Dest_bit10 : std_logic;
SIGNAL Dest_bit11 : std_logic;
SIGNAL Dest_bit12 : std_logic;
SIGNAL Dest_bit9 : std_logic;
SIGNAL Enable_Carry_CCR : std_logic;
SIGNAL Enable_VNZ_CCR : std_logic;
SIGNAL Execute_Control : std_logic_vector(8 DOWNTO 0);
SIGNAL Is_Branch : std_logic;
SIGNAL Is_JAL : std_logic;
SIGNAL Is_Unconditional_Jumps : std_logic;
SIGNAL Is_negative : std_logic;
SIGNAL Is_ovfl : std_logic;
SIGNAL Is_zero : std_logic;
SIGNAL L_Register_Out : std_logic_vector(15 DOWNTO 0);
SIGNAL Negative_CCR_Out : std_logic;
SIGNAL Overflow_CCR_Out : std_logic;
SIGNAL R_Register_Out : std_logic_vector(15 DOWNTO 0);
SIGNAL Result_Intermediate : std_logic_vector(15 DOWNTO 0);
SIGNAL VNZ_CCR_enable : std_logic;
SIGNAL Zero_CCR_Out : std_logic;
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL dout10 : std_logic;
SIGNAL dout11 : std_logic;
SIGNAL dout12 : std_logic;
SIGNAL dout13 : std_logic;
SIGNAL dout14 : std_logic;
SIGNAL dout15 : std_logic_vector(15 DOWNTO 0);
SIGNAL dout16 : std_logic_vector(15 DOWNTO 0);
SIGNAL dout2 : std_logic;
SIGNAL dout3 : std_logic;
SIGNAL dout4 : std_logic;
SIGNAL dout5 : std_logic;
SIGNAL dout6 : std_logic;
SIGNAL dout7 : std_logic;
SIGNAL dout8 : std_logic;
SIGNAL dout9 : std_logic_vector(3 DOWNTO 0);
SIGNAL from_Shifter_Control : std_logic;
SIGNAL load_enable : std_logic;
SIGNAL next_pc_val : std_logic_vector(15 DOWNTO 0);
SIGNAL operation : std_logic_vector(3 DOWNTO 0);
SIGNAL pcval_Register_Out : std_logic_vector(15 DOWNTO 0);
SIGNAL shifter_Out : std_logic_vector(15 DOWNTO 0);
SIGNAL to_Carry_CCR : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'Carry_CCR_Register' of 'adff'
SIGNAL mw_Carry_CCR_Registerreg_cval : std_logic := '0';
-- ModuleWare signal declarations(v1.12) for instance 'Control_Register' of 'adff'
SIGNAL mw_Control_Registerreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'Dest_Register' of 'adff'
SIGNAL mw_Dest_Registerreg_cval : std_logic_vector(3 DOWNTO 0) := "0000";
-- ModuleWare signal declarations(v1.12) for instance 'Extra_Register' of 'adff'
SIGNAL mw_Extra_Registerreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'L_Register' of 'adff'
SIGNAL mw_L_Registerreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'Negative_CCR_Register' of 'adff'
SIGNAL mw_Negative_CCR_Registerreg_cval : std_logic := '0';
-- ModuleWare signal declarations(v1.12) for instance 'Overflow_CCR_Register' of 'adff'
SIGNAL mw_Overflow_CCR_Registerreg_cval : std_logic := '0';
-- ModuleWare signal declarations(v1.12) for instance 'R_Register' of 'adff'
SIGNAL mw_R_Registerreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'Zero_CCR_Register' of 'adff'
SIGNAL mw_Zero_CCR_Registerreg_cval : std_logic := '0';
-- ModuleWare signal declarations(v1.12) for instance 'pcval_Register' of 'adff'
SIGNAL mw_pcval_Registerreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'Additional_Execute_Control_Splitter' of 'split'
SIGNAL mw_Additional_Execute_Control_Splittertemp_din : std_logic_vector(3 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'Control_Splitter' of 'split'
SIGNAL mw_Control_Splittertemp_din : std_logic_vector(15 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'Dest_Splitter' of 'split'
SIGNAL mw_Dest_Splittertemp_din : std_logic_vector(3 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'Execute_Control_Splitter' of 'split'
SIGNAL mw_Execute_Control_Splittertemp_din : std_logic_vector(8 DOWNTO 0);
-- Component Declarations
COMPONENT mini_ALU
PORT (
ALU_cin : IN std_logic ;
ALU_mode : IN std_logic ;
Left : IN std_logic_vector (15 DOWNTO 0);
Right : IN std_logic_vector (15 DOWNTO 0);
operation : IN std_logic_vector (3 DOWNTO 0);
pcval : IN std_logic_vector (15 DOWNTO 0);
ALU_Result : OUT std_logic_vector (15 DOWNTO 0);
ALU_cout : OUT std_logic ;
Is_negative : OUT std_logic ;
Is_ovfl : OUT std_logic ;
Is_zero : OUT std_logic ;
next_pc_val : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT mini_Shifter
PORT (
from_Carry_CCR : IN std_logic;
shift_operation : IN std_logic_vector (3 DOWNTO 0);
shifter_In : IN std_logic_vector (15 DOWNTO 0);
shifter_Out : OUT std_logic_vector (15 DOWNTO 0);
to_Carry_CCR : OUT std_logic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : mini_ALU USE ENTITY lab9_new_lib.mini_ALU;
FOR ALL : mini_Shifter USE ENTITY lab9_new_lib.mini_Shifter;
-- pragma synthesis_on
BEGIN
-- ModuleWare code(v1.12) for instance 'Carry_CCR_Register' of 'adff'
Carry_CCR_Out <= mw_Carry_CCR_Registerreg_cval;
carry_ccr_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (rst = '1') THEN
mw_Carry_CCR_Registerreg_cval <= '0';
ELSIF (Carry_CCR_enable = '1') THEN
mw_Carry_CCR_Registerreg_cval <= Carry_CCR_In;
END IF;
END IF;
END PROCESS carry_ccr_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'Control_Register' of 'adff'
Control_Register_Out <= mw_Control_Registerreg_cval;
control_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_Control_Registerreg_cval <= dout16;
END IF;
END IF;
END PROCESS control_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'Dest_Register' of 'adff'
Dest_Register_Out <= mw_Dest_Registerreg_cval;
dest_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_Dest_Registerreg_cval <= Dest;
END IF;
END IF;
END PROCESS dest_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'Extra_Register' of 'adff'
Extra_Execute_Out <= mw_Extra_Registerreg_cval;
extra_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_Extra_Registerreg_cval <= Extra;
END IF;
END IF;
END PROCESS extra_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'L_Register' of 'adff'
L_Register_Out <= mw_L_Registerreg_cval;
l_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_L_Registerreg_cval <= L;
END IF;
END IF;
END PROCESS l_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'Negative_CCR_Register' of 'adff'
Negative_CCR_Out <= mw_Negative_CCR_Registerreg_cval;
negative_ccr_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (rst = '1') THEN
mw_Negative_CCR_Registerreg_cval <= '0';
ELSIF (VNZ_CCR_enable = '1') THEN
mw_Negative_CCR_Registerreg_cval <= Is_negative;
END IF;
END IF;
END PROCESS negative_ccr_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'Overflow_CCR_Register' of 'adff'
Overflow_CCR_Out <= mw_Overflow_CCR_Registerreg_cval;
overflow_ccr_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (rst = '1') THEN
mw_Overflow_CCR_Registerreg_cval <= '0';
ELSIF (VNZ_CCR_enable = '1') THEN
mw_Overflow_CCR_Registerreg_cval <= Is_ovfl;
END IF;
END IF;
END PROCESS overflow_ccr_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'R_Register' of 'adff'
R_Register_Out <= mw_R_Registerreg_cval;
r_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_R_Registerreg_cval <= R;
END IF;
END IF;
END PROCESS r_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'Zero_CCR_Register' of 'adff'
Zero_CCR_Out <= mw_Zero_CCR_Registerreg_cval;
zero_ccr_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (rst = '1') THEN
mw_Zero_CCR_Registerreg_cval <= '0';
ELSIF (VNZ_CCR_enable = '1') THEN
mw_Zero_CCR_Registerreg_cval <= Is_zero;
END IF;
END IF;
END PROCESS zero_ccr_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'pcval_Register' of 'adff'
pcval_Register_Out <= mw_pcval_Registerreg_cval;
pcval_registerseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_pcval_Registerreg_cval <= pcval;
END IF;
END IF;
END PROCESS pcval_registerseq_proc;
-- ModuleWare code(v1.12) for instance 'CCR_bitmask' of 'and'
dout13 <= Is_Branch AND dout6;
-- ModuleWare code(v1.12) for instance 'Carry_CCR_load_AND' of 'and'
Carry_CCR_enable <= Enable_Carry_CCR AND load_enable;
-- ModuleWare code(v1.12) for instance 'Carry_bitmask_AND' of 'and'
dout10 <= Carry_CCR_Out AND Dest_bit12;
-- ModuleWare code(v1.12) for instance 'Negative_bitmaskt_AND' of 'and'
dout12 <= Negative_CCR_Out AND Dest_bit10;
-- ModuleWare code(v1.12) for instance 'Overflow_bitmask_AND' of 'and'
dout11 <= Overflow_CCR_Out AND Dest_bit11;
-- ModuleWare code(v1.12) for instance 'VNZ_CCR_load_AND' of 'and'
VNZ_CCR_enable <= Enable_VNZ_CCR AND load_enable;
-- ModuleWare code(v1.12) for instance 'Zero_bitmask_AND' of 'and'
dout5 <= Zero_CCR_Out AND Dest_bit9;
-- ModuleWare code(v1.12) for instance 'jaddress_Buff' of 'buff'
jaddress <= Result_Intermediate;
-- ModuleWare code(v1.12) for instance 'ALU_MODE_ONE' of 'constval'
dout1 <= '1';
-- ModuleWare code(v1.12) for instance 'ALU_MODE_ZERO' of 'constval'
dout <= '0';
-- ModuleWare code(v1.12) for instance 'ALU_cin_ONE' of 'constval'
dout3 <= '1';
-- ModuleWare code(v1.12) for instance 'ALU_cin_ZERO' of 'constval'
dout2 <= '0';
-- ModuleWare code(v1.12) for instance 'Control_ZERO' of 'constval'
dout15 <= "0000000000000000";
-- ModuleWare code(v1.12) for instance 'FOURTEEN' of 'constval'
dout9 <= "1110";
-- ModuleWare code(v1.12) for instance 'jump_ONE' of 'constval'
dout4 <= '1';
-- ModuleWare code(v1.12) for instance 'Carry_CCR_inverter' of 'inv'
dout7 <= NOT(Carry_CCR_Out);
-- ModuleWare code(v1.12) for instance 'stall_inverter' of 'inv'
load_enable <= NOT(stall);
-- ModuleWare code(v1.12) for instance 'ALU_cin_MUX' of 'mux'
alu_cin_muxcombo_proc: PROCESS(dout2, Carry_CCR_Out, dout3, dout7,
ALU_cin_Control)
BEGIN
CASE ALU_cin_Control IS
WHEN "00" => dout8 <= dout2;
WHEN "01" => dout8 <= Carry_CCR_Out;
WHEN "10" => dout8 <= dout3;
WHEN "11" => dout8 <= dout7;
WHEN OTHERS => dout8 <= 'X';
END CASE;
END PROCESS alu_cin_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'ALU_mode_MUX' of 'mux'
alu_mode_muxcombo_proc: PROCESS(dout, dout1, ALU_mode_Control)
BEGIN
CASE ALU_mode_Control IS
WHEN '0' => dout14 <= dout;
WHEN '1' => dout14 <= dout1;
WHEN OTHERS => dout14 <= 'X';
END CASE;
END PROCESS alu_mode_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'Carry_CCR_MUX' of 'mux'
carry_ccr_muxcombo_proc: PROCESS(ALU_cout, to_Carry_CCR,
from_Shifter_Control)
BEGIN
CASE from_Shifter_Control IS
WHEN '0' => Carry_CCR_In <= ALU_cout;
WHEN '1' => Carry_CCR_In <= to_Carry_CCR;
WHEN OTHERS => Carry_CCR_In <= 'X';
END CASE;
END PROCESS carry_ccr_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'Control_Input_MUX' of 'mux'
control_input_muxcombo_proc: PROCESS(dout15, Control, can_move_on)
BEGIN
CASE can_move_on IS
WHEN '0' => dout16 <= dout15;
WHEN '1' => dout16 <= Control;
WHEN OTHERS => dout16 <= (OTHERS => 'X');
END CASE;
END PROCESS control_input_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'Dest_Execute_Out_MUX' of 'mux'
dest_execute_out_muxcombo_proc: PROCESS(Dest_Register_Out, dout9,
Is_JAL)
BEGIN
CASE Is_JAL IS
WHEN '0' => Dest_Execute_Out <= Dest_Register_Out;
WHEN '1' => Dest_Execute_Out <= dout9;
WHEN OTHERS => Dest_Execute_Out <= (OTHERS => 'X');
END CASE;
END PROCESS dest_execute_out_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'Result_Intermediate' of 'mux'
result_intermediatecombo_proc: PROCESS(ALU_Result, shifter_Out,
from_Shifter_Control)
BEGIN
CASE from_Shifter_Control IS
WHEN '0' => Result_Intermediate <= ALU_Result;
WHEN '1' => Result_Intermediate <= shifter_Out;
WHEN OTHERS => Result_Intermediate <= (OTHERS => 'X');
END CASE;
END PROCESS result_intermediatecombo_proc;
-- ModuleWare code(v1.12) for instance 'Result_MUX' of 'mux'
result_muxcombo_proc: PROCESS(Result_Intermediate, next_pc_val,
Is_JAL)
BEGIN
CASE Is_JAL IS
WHEN '0' => Result <= Result_Intermediate;
WHEN '1' => Result <= next_pc_val;
WHEN OTHERS => Result <= (OTHERS => 'X');
END CASE;
END PROCESS result_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'jump_MUX' of 'mux'
jump_muxcombo_proc: PROCESS(dout13, dout4, Is_Unconditional_Jumps)
BEGIN
CASE Is_Unconditional_Jumps IS
WHEN '0' => jump <= dout13;
WHEN '1' => jump <= dout4;
WHEN OTHERS => jump <= 'X';
END CASE;
END PROCESS jump_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'CCR_bitmask_OR' of 'or'
dout6 <= dout5 OR dout12 OR dout11 OR dout10;
-- ModuleWare code(v1.12) for instance 'Additional_Execute_Control_Splitter' of 'split'
mw_Additional_Execute_Control_Splittertemp_din <= Additional_Execute_Control;
additional_execute_control_splittercombo_proc: PROCESS (mw_Additional_Execute_Control_Splittertemp_din)
VARIABLE temp_din: std_logic_vector(3 DOWNTO 0);
BEGIN
temp_din := mw_Additional_Execute_Control_Splittertemp_din(3 DOWNTO 0);
Enable_VNZ_CCR <= temp_din(0);
Enable_Carry_CCR <= temp_din(1);
Is_JAL <= temp_din(2);
Is_Unconditional_Jumps <= temp_din(3);
END PROCESS additional_execute_control_splittercombo_proc;
-- ModuleWare code(v1.12) for instance 'Control_Splitter' of 'split'
mw_Control_Splittertemp_din <= Control_Register_Out;
control_splittercombo_proc: PROCESS (mw_Control_Splittertemp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_Control_Splittertemp_din(15 DOWNTO 0);
Execute_Control <= temp_din(8 DOWNTO 0);
Additional_Execute_Control <= temp_din(12 DOWNTO 9);
Control_Out <= temp_din(15 DOWNTO 13);
END PROCESS control_splittercombo_proc;
-- ModuleWare code(v1.12) for instance 'Dest_Splitter' of 'split'
mw_Dest_Splittertemp_din <= Dest_Register_Out;
dest_splittercombo_proc: PROCESS (mw_Dest_Splittertemp_din)
VARIABLE temp_din: std_logic_vector(3 DOWNTO 0);
BEGIN
temp_din := mw_Dest_Splittertemp_din(3 DOWNTO 0);
Dest_bit9 <= temp_din(0);
Dest_bit10 <= temp_din(1);
Dest_bit11 <= temp_din(2);
Dest_bit12 <= temp_din(3);
END PROCESS dest_splittercombo_proc;
-- ModuleWare code(v1.12) for instance 'Execute_Control_Splitter' of 'split'
mw_Execute_Control_Splittertemp_din <= Execute_Control;
execute_control_splittercombo_proc: PROCESS (mw_Execute_Control_Splittertemp_din)
VARIABLE temp_din: std_logic_vector(8 DOWNTO 0);
BEGIN
temp_din := mw_Execute_Control_Splittertemp_din(8 DOWNTO 0);
Is_Branch <= temp_din(0);
from_Shifter_Control <= temp_din(1);
ALU_cin_Control <= temp_din(3 DOWNTO 2);
operation <= temp_din(7 DOWNTO 4);
ALU_mode_Control <= temp_din(8);
END PROCESS execute_control_splittercombo_proc;
-- Instance port mappings.
U_0 : mini_ALU
PORT MAP (
ALU_cin => dout8,
ALU_mode => dout14,
Left => L_Register_Out,
Right => R_Register_Out,
operation => operation,
pcval => pcval_Register_Out,
ALU_Result => ALU_Result,
ALU_cout => ALU_cout,
Is_negative => Is_negative,
Is_ovfl => Is_ovfl,
Is_zero => Is_zero,
next_pc_val => next_pc_val
);
U_1 : mini_Shifter
PORT MAP (
shifter_In => L_Register_Out,
shift_operation => operation,
shifter_Out => shifter_Out,
from_Carry_CCR => Carry_CCR_Out,
to_Carry_CCR => to_Carry_CCR
);
END struct;
|
gpl-2.0
|
b3410f3b600a5f5b71ef63faf9948eff
| 0.60568 | 3.581694 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/UartClkDiv.vhd
| 1 | 896 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UartClkDiv is
port(
CLKin : in std_logic;
CLKTXD_out : inout std_logic:='0';
CLKRXD_out : inout std_logic:='0');
end UartClkDiv;
architecture Behavioral of UartClkDiv is
signal count : integer :=1;
signal count2 : integer :=1;
----------------------------------------------------------------------
begin
-------------------------------------------------
process(CLKin)
begin
if(CLKin'event and CLKin='1') then
count <= count + 1;
if(count = 434) then --<FOR CLKIN 100MZ>--
CLKTXD_out <= not CLKTXD_out;
count <=1;
end if;
end if;
end process;
-------------------------------------------------
process(CLKin)
begin
if(CLKin'event and CLKin='1') then
count2 <= count2 + 1;
if(count2 = 27) then --<FOR CLKIN 100MZ>--
CLKRXD_out <= not CLKRXD_out;
count2 <=1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
ed0ab8408eef5819cce669a31ace6e99
| 0.534598 | 3.294118 | false | false | false | false |
hlamer/ktexteditor
|
autotests/input/syntax/vhdl/light52_muldiv.vhdl
| 3 | 9,064 |
--------------------------------------------------------------------------------
-- light52_muldiv.vhdl -- Simple multiplier/divider module.
--------------------------------------------------------------------------------
-- The 8051 mul and div instructions are both unsigned and operands are 8 bit.
--
-- This module implements the division as a sequential state machine which takes
-- 8 cycles to complete.
-- The multiplier can be implemented as sequential or as combinational, in which
-- case it will use a DSP block in those architectures that support it.
-- No attempt has been made to make this module generic or reusable.
--
-- If you want a combinational multiplier but don't want to waste a DSP block
-- in this module, you need to modify this file adding whatever synthesis
-- pragmas your tool of choice needs.
--
-- Note that unlike the division state machine, the combinational product logic
-- is always operating: when SEQUENTIAL_MULTIPLIER=true, prod_out equals
-- data_a * data_b with a latency of 1 clock cycle, and mul_ready is hardwired
-- to '1'.
--
-- FIXME explain division algorithm.
--------------------------------------------------------------------------------
-- GENERICS:
--
-- SEQUENTIAL_MULTIPLIER -- Sequential vs. combinational multiplier.
-- When true, a sequential implementation will be used for the multiplier,
-- which will usually save a lot of logic or a dedicated multiplier.
-- When false, a combinational registered multiplier will be used.
--
--------------------------------------------------------------------------------
-- INTERFACE SIGNALS:
--
-- clk : Clock, active rising edge.
-- reset : Synchronous reset. Clears only the control registers not
-- visible to the programmer -- not the output registers.
--
-- data_a : Numerator input, should be connected to the ACC register.
-- data_b : Denominator input, should be connected to the B register.
-- start : Assert for 1 cycle to start the division state machine
-- (and the product if SEQUENTIAL_MULTIPLIER=true);
--
-- prod_out : Product output, valid only when mul_ready='1'.
-- quot_out : Quotient output, valid only when div_ready='1'.
-- rem_out : Remainder output, valid only when div_ready='1'.
-- div_ov_out : Division overflow flag, valid only when div_ready='1'.
-- mul_ov_out : Product overflow flag, valid only when mul_ready='1'.
--
-- mul_ready : Asserted permanently if SEQUENTIAL_MULTIPLIER=false.
-- div_ready : Deasserted the cycle after start is asserted.
-- Asserted when the division has completed.
--
--------------------------------------------------------------------------------
-- Copyright (C) 2012 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.light52_pkg.all;
use work.light52_ucode_pkg.all;
entity light52_muldiv is
generic (
SEQUENTIAL_MULTIPLIER : boolean := false
);
port(
clk : in std_logic;
reset : in std_logic;
data_a : in t_byte;
data_b : in t_byte;
start : in std_logic;
prod_out : out t_word;
quot_out : out t_byte;
rem_out : out t_byte;
div_ov_out : out std_logic;
mul_ov_out : out std_logic;
mul_ready : out std_logic;
div_ready : out std_logic
);
end entity light52_muldiv;
architecture sequential of light52_muldiv is
signal bit_ctr : integer range 0 to 8;
signal b_shift_reg : t_word;
signal den_ge_256 : std_logic;
signal num_ge_den : std_logic;
signal sub_num : std_logic;
signal denominator : t_byte;
signal rem_reg : t_byte;
signal quot_reg : t_byte;
signal prod_reg : t_word;
signal ready : std_logic;
signal load_regs : std_logic;
begin
-- Control logic ---------------------------------------------------------------
control_counter: process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
bit_ctr <= 8;
else
if load_regs='1' then
bit_ctr <= 0;
elsif bit_ctr /= 8 then
bit_ctr <= bit_ctr + 1;
end if;
end if;
end if;
end process control_counter;
-- Internal signal ready is asserted after 8 cycles.
-- The sequential multiplier will use this signal too, IF it takes 8 cycles.
ready <= '1' when bit_ctr >= 8 else '0';
---- Divider logic -------------------------------------------------------------
-- What we do is a simple base-2 'shift-and-subtract' algorithm that takes
-- 8 cycles to complete. We can get away with this because we deal with unsigned
-- numbers only.
divider_registers: process(clk)
begin
if clk'event and clk='1' then
-- denominator shift register
if load_regs='1' then
b_shift_reg <= "0" & data_b & "0000000";
-- Division overflow can be determined upon loading B reg data.
-- OV will be raised only on div-by-zero.
if data_b=X"00" then
div_ov_out <= '1';
else
div_ov_out <= '0';
end if;
else
b_shift_reg <= "0" & b_shift_reg(b_shift_reg'high downto 1);
end if;
-- numerator register
if load_regs='1' then
rem_reg <= data_a;
elsif bit_ctr/=8 and sub_num='1' then
rem_reg <= rem_reg - denominator;
end if;
--- quotient register
if load_regs='1' then
quot_reg <= (others => '0');
elsif bit_ctr/=8 then
quot_reg <= quot_reg(quot_reg'high-1 downto 0) & sub_num;
end if;
load_regs <= start;
end if;
end process divider_registers;
denominator <= b_shift_reg(7 downto 0);
-- The 16-bit comparison between b_shift_reg (denominator) and the zero-extended
-- rem_reg (numerator) can be simplified by splitting it in 2:
-- If the shifted denominator high byte is not zero, it is >=256...
den_ge_256 <= '1' when b_shift_reg(15 downto 8) /= X"00" else '0';
-- ...otherwise we need to compare the low bytes.
num_ge_den <= '1' when rem_reg >= denominator else '0';
sub_num <= '1' when den_ge_256='0' and num_ge_den='1' else '0';
quot_out <= quot_reg;
prod_out <= prod_reg;
rem_out <= rem_reg;
div_ready <= ready;
---- Multiplier logic ----------------------------------------------------------
---- Combinational multiplier -----------------------------
multiplier_combinational: if not SEQUENTIAL_MULTIPLIER generate
registered_combinational_multiplier:process(clk)
begin
if clk'event and clk='1' then
prod_reg <= data_a * data_b; -- t_byte is unsigned
end if;
end process registered_combinational_multiplier;
-- The multiplier output is valid in the cycle after the operands are loaded,
-- so by the time MUL is executed it's already done.
mul_ready <= '1';
mul_ov_out <= '1' when prod_reg(15 downto 8)/=X"00" else '0';
prod_out <= prod_reg;
end generate multiplier_combinational;
---- Sequential multiplier --------------------------------
multiplier_sequential: if SEQUENTIAL_MULTIPLIER generate
assert false
report "Sequential multiplier implementation not done yet."&
" Use combinational implementation."
severity failure;
end generate multiplier_sequential;
end sequential;
|
gpl-2.0
|
547fe5d204412702f28bc4a3b8b6b45d
| 0.554943 | 4.38086 | false | false | false | false |
arcade-lab/uarch-phases
|
src/lib/tracing/detect_mem_access.vhd
| 1 | 2,121 |
------------------------------------------------------------------------------
-- This file is part of a signal tracing utility for the LEON3 processor
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Entity: detect_mem_access
-- File: detect_mem_access.vhd
-- Author: Van Bui - ARCADE @ Columbia University
-- Description: Detects a memory access over the bus
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library sld;
use sld.tracing.all;
entity detect_mem_access is
port (
ahbsi : in ahb_slv_in_type;
mem_selected : out std_logic_vector(AHB_BITS-1 downto 0));
end detect_mem_access;
architecture beh of detect_mem_access is
begin --beh
check_mem_access: process (ahbsi)
variable haddr : std_logic_vector(1 downto 0);
begin -- process detect_mem_access
haddr := ahbsi.haddr(31 downto 30);
if (haddr = "01" and (ahbsi.htrans = HTRANS_NONSEQ)) then
mem_selected <= "01";
elsif (haddr = "01" and (ahbsi.htrans = HTRANS_SEQ)) then
mem_selected <= "10";
elsif (haddr = "01" and (ahbsi.htrans = HTRANS_BUSY)) then
mem_selected <= "11";
else
mem_selected <= "00";
end if;
end process check_mem_access;
end beh;
|
gpl-3.0
|
4aa9bdea64b7a952b9b7b8c970890ebc
| 0.611033 | 3.964486 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_cmult.vhd
| 1 | 4,970 |
-------------------------------------------------------------------------------
--
-- Title : fp23_cmult
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-- Description : floating point complex multiplier
--
-------------------------------------------------------------------------------
--
-- Version 1.0 19.12.2015
-- Description: Complex floating point multiplier
--
-- DC_RE = DA_RE * DB_RE - DA_IM * DB_IM
-- DC_IM = DA_RE * DB_IM + DA_IM * DB_RE
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.fp_m1_pkg.fp23_complex;
use work.fp_m1_pkg.fp23_data;
entity fp23_cmult is
generic (
XSERIES : string:="7SERIES" --! Xilinx series
);
port(
DA : in fp23_complex; --! Data A (input)
DB : in fp23_complex; --! Data B (input)
ENA : in STD_LOGIC; --! Input data enable
DC : out fp23_complex; --! Data C (output)
VAL : out STD_LOGIC; --! Output data valid
RESET : in STD_LOGIC; --! Reset
CLK : in STD_LOGIC --! Clock
);
end fp23_cmult;
architecture fp23_cmult of fp23_cmult is
signal fp23_cc : fp23_complex;
signal fp23_val : std_logic;
signal fp23_mlt : std_logic;
signal fp23_are_bre : fp23_data;
signal fp23_are_bim : fp23_data;
signal fp23_aim_bre : fp23_data;
signal fp23_aim_bim : fp23_data;
constant CM_SCALE : std_logic_vector(5 downto 0):="011111";
begin
---------------- FlOAT MULTIPLY A*B ----------------
ARExBRE : entity work.fp23_mult
generic map(
XSERIES => XSERIES,
EXP_DIF => CM_SCALE
)
port map (
aa => DA.re,
bb => DB.re,
cc => fp23_are_bre,
enable => ENA,
valid => fp23_mlt,
reset => RESET,
clk => clk
);
AIMxBIM : entity work.fp23_mult
generic map(
XSERIES => XSERIES,
EXP_DIF => CM_SCALE
)
port map (
aa => DA.im,
bb => DB.im,
cc => fp23_aim_bim,
enable => ENA,
valid => open,
reset => RESET,
clk => clk
);
ARExBIM : entity work.fp23_mult
generic map(
XSERIES => XSERIES,
EXP_DIF => CM_SCALE
)
port map (
aa => DA.re,
bb => DB.im,
cc => fp23_are_bim,
enable => ENA,
valid => open,
reset => RESET,
clk => clk
);
AIMxBRE : entity work.fp23_mult
generic map(
XSERIES => XSERIES,
EXP_DIF => CM_SCALE
)
port map (
aa => DA.im,
bb => DB.re,
cc => fp23_aim_bre,
enable => ENA,
valid => open,
reset => RESET,
clk => clk
);
---------------- FlOAT ADD/SUB +/- ----------------
AB_ADD : entity work.fp23_addsub
generic map(
XSERIES => XSERIES
)
port map (
aa => fp23_are_bim,
bb => fp23_aim_bre,
cc => fp23_cc.im,
addsub => '0',
reset => RESET,
enable => fp23_mlt,
valid => fp23_val,
clk => clk
);
AB_SUB : entity work.fp23_addsub
generic map(
XSERIES => XSERIES
)
port map (
aa => fp23_are_bre,
bb => fp23_aim_bim,
cc => fp23_cc.re,
addsub => '1',
reset => RESET,
enable => fp23_mlt,
valid => open,
clk => clk
);
DC <= fp23_cc when rising_edge(clk);
VAL <= fp23_val when rising_edge(clk);
end fp23_cmult;
|
mit
|
0e13946f1a678fb513df38899a758afc
| 0.515493 | 3.208522 | false | false | false | false |
sdenel/An-N-bits-pipelined-addsub-using-VHDL
|
src/fullAdderWithRegisters.vhd
| 1 | 2,177 |
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity fullAdderWithRegisters is
-- fullAdderWithRegisters
-- Prend a, b, en entrée
-- Prend c NREGSBEFORE coups d'horloge après
-- Rend s au bout de NREGSBEFORE+NREGSAFTER+1 coups d'horloge
-- NREGSBEFORE+NREGSAFTER+1
generic (
NREGSBEFORE: natural := 0;
NREGSAFTER : natural := 0;
ISCREG : natural := 0;
ISRESET : std_logic := '0'
);
port (
clk, rst : in std_logic;
a, b, c : in std_logic;
r, s : out std_logic
);
end entity fullAdderWithRegisters;
architecture rtl of fullAdderWithRegisters is
--signal Ar, Br, S, C, Bc: bit_vector(NBITS-1 downto 0);
signal Ar_B, Br_B: std_logic_vector(NREGSBEFORE downto 0);
signal Cr : std_logic_vector(ISCREG downto 0);
signal Sr_A : std_logic_vector(NREGSAFTER downto 0);
signal st : std_logic;
component fullAdder
port(
a, b, c : in std_logic;
r, s : out std_logic
);
end component fullAdder;
begin
G0: if ISCREG = 1 generate
process (clk)
begin
if clk'event and clk = '1' then
Cr(0) <= Cr(1);
end if;
end process;
end generate G0;
G1: if NREGSBEFORE > 0 generate
process (clk, rst)
begin
if ISRESET= '1' and rst = '1' then
Ar_B(NREGSBEFORE-1 downto 0) <= (others => '0');
Br_B(NREGSBEFORE-1 downto 0) <= (others => '0');
elsif clk'event and clk = '1' then
Ar_B(NREGSBEFORE-1 downto 0) <= Ar_B(NREGSBEFORE downto 1);
Br_B(NREGSBEFORE-1 downto 0) <= Br_B(NREGSBEFORE downto 1);
end if;
end process;
end generate G1;
G2: if NREGSAFTER > 0 generate
process (clk, rst)
begin
if ISRESET= '1' and rst = '1' then
Sr_A(NREGSAFTER-1 downto 0) <= (others => '0');
elsif clk'event and clk = '1' then
for i in 0 to NREGSAFTER-1 loop
Sr_A(NREGSAFTER-1 downto 0) <= Sr_A(NREGSAFTER downto 1);
end loop;
end if;
end process;
Sr_A(NREGSAFTER) <= st;
s <= Sr_A(0);
end generate G2;
G3: if NREGSAFTER = 0 generate
s <= st;
end generate G3;
Cr(ISCREG) <= c;
Ar_B(NREGSBEFORE) <= a;
Br_B(NREGSBEFORE) <= b;
inst: fullAdder port map(a=>Ar_B(0), b=>Br_B(0), c=>Cr(0), r=>r, s=>st);
end rtl;
|
mit
|
bdfdcdcf41edfcf888e5818922c5b0e9
| 0.628506 | 2.732412 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/vid2vga.vhdl
| 1 | 7,126 |
-- Video-to-VGA translation
-- (C) Copyright 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
--
-- horizontal: 640 pixels display 0..639
-- 16 pixels front porch 640..655
-- 96 pixels sync pulse 656..751
-- 48 pixels back porch 752..799
-- ---
-- 800
--
-- vartical: 480 lines display 0..479
-- 10 lines front porch 480..489
-- 2 lines sync pulse 490..491
-- 33 lines back porch 492..524
-- ---
-- 525
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.all;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- ======================================================================
-- top-level entity for 60Hz video to VGA
entity Vid2Vga is
generic (
VLINES : integer := 256;
HPIXELS : integer := 256;
VBITS : integer := 8;
HBITS : integer := 8;
SRCBITS : integer := 8;
OUTBITS : integer := 4
);
port (
vreset : in std_logic;
vgaclk : in std_logic; -- pixel clock for VGA
-- inputs from video subsystem
red : in std_logic_vector((SRCBITS-1) downto 0);
grn : in std_logic_vector((SRCBITS-1) downto 0);
blu : in std_logic_vector((SRCBITS-1) downto 0);
hblank : in std_logic;
vblank : in std_logic;
xpixel : in std_logic_vector((HBITS-1) downto 0);
ypixel : in std_logic_vector((VBITS-1) downto 0);
pxclk : in std_logic;
-- outputs for VGA
vga_red : out std_logic_vector((OUTBITS-1) downto 0);
vga_grn : out std_logic_vector((OUTBITS-1) downto 0);
vga_blu : out std_logic_vector((OUTBITS-1) downto 0);
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
end entity Vid2Vga;
-- ======================================================================
architecture behaviour of Vid2Vga is
function msb_set_by_width(width: natural) return std_logic_vector is
variable return_vector: std_logic_vector(width-1 downto 0);
begin
for i in return_vector'range loop
if (i = 0) then
return_vector(i) := '1';
else
return_vector(i) := '1';
end if;
end loop;
return return_vector;
end;
-- derive VGA and display parameters from generics
constant pvinit : unsigned(9 downto 0) := conv_unsigned(480, 10);
constant pvgry2 : unsigned(9 downto 0) := conv_unsigned((480-VLINES)/2, 10);
constant pvgry1 : unsigned(9 downto 0) := pvgry2 - (VLINES / 16);
constant pvgry3 : unsigned(9 downto 0) := conv_unsigned((480+VLINES)/2, 10);
constant pvgry4 : unsigned(9 downto 0) := pvgry3 + (VLINES / 16);
constant phgry2 : unsigned(9 downto 0) := conv_unsigned((640-HPIXELS)/2, 10);
constant phgry1 : unsigned(9 downto 0) := phgry2 - (HPIXELS / 16);
constant phgry3 : unsigned(9 downto 0) := conv_unsigned((640+HPIXELS)/2, 10);
constant phgry4 : unsigned(9 downto 0) := phgry3 + (HPIXELS / 16);
constant vgahalf : std_logic_vector((OUTBITS-1) downto 0) := msb_set_by_width(OUTBITS);
-- signals tracking video and VGA scanning
signal pvpos : unsigned(9 downto 0); -- VGA picture vertical (800x525)
signal phpos : unsigned(9 downto 0); -- VGA picture horizontal (800x525)
signal fvposp : unsigned(9 downto 0); -- frame vertical within VGA
signal fhposp : unsigned(9 downto 0); -- frame horizontal within VGA
signal blackout : std_logic;
signal borderout : std_logic;
-- frame buffer signals
signal rgb_wdata : std_logic_vector((3*OUTBITS-1) downto 0);
signal rgb_waddr : std_logic_vector((VBITS+HBITS-1) downto 0);
signal rgb_we : std_logic;
signal rgb_rdata : std_logic_vector((3*OUTBITS-1) downto 0);
signal rgb_raddr : std_logic_vector((VBITS+HBITS-1) downto 0);
-- registered frame buffer pixel
signal rgb_pixel : std_logic_vector((3*OUTBITS-1) downto 0);
begin
-- frame buffer
frame_buffer : entity work.ram
generic map (
ADDRESS_WIDTH => VBITS+HBITS,
DATA_WIDTH => 3*OUTBITS
)
port map (
clock => vgaclk,
data => rgb_wdata,
write_address => rgb_waddr,
read_address => rgb_raddr,
we => rgb_we,
q => rgb_rdata
);
-- frame buffer writing
rgb_wdata <= red((SRCBITS-1) downto (SRCBITS-OUTBITS)) &
grn((SRCBITS-1) downto (SRCBITS-OUTBITS)) &
blu((SRCBITS-1) downto (SRCBITS-OUTBITS));
rgb_waddr <= ypixel & xpixel;
rgb_we <= not (vblank or hblank) and pxclk;
-- establish VGA picture positions
sync_gen : process(vgaclk, vreset) is
begin
if vreset = '1' then
pvpos <= (others => '0');
phpos <= (others => '0');
elsif vgaclk'event and vgaclk = '0' then
if phpos = 799 then
phpos <= (others => '0');
if pvpos = 524 then
pvpos <= (others => '0');
else
pvpos <= pvpos + 1;
end if;
else
phpos <= phpos + 1;
end if;
end if;
end process;
-- frame position within VGA picture
fvposp <= pvpos - pvgry2;
fhposp <= phpos - phgry2;
rgb_raddr <= std_logic_vector(fvposp((VBITS-1) downto 0)) &
std_logic_vector(fhposp((HBITS-1) downto 0));
-- black and gray region detect
blackout <= '1' when ((pvpos <= pvgry1) or (pvpos > pvgry4) or
(phpos <= phgry1) or (phpos > phgry4)) else '0';
borderout <= '1' when ((pvpos < pvgry2) or (pvpos >= pvgry3) or
(phpos < phgry2) or (phpos >= phgry3)) else '0';
-- pixel register
pixel : process(vgaclk, vreset) is
begin
if vreset = '1' then
rgb_pixel <= (others => '0');
elsif vgaclk'event and vgaclk = '1' then
if (blackout = '1') then
rgb_pixel <= (others => '0');
elsif (borderout = '1') then
rgb_pixel <= vgahalf & vgahalf & vgahalf;
else
rgb_pixel <= rgb_rdata;
end if;
end if;
end process;
-- output VGA colours
vga_red <= rgb_pixel((3*OUTBITS-1) downto (2*OUTBITS));
vga_grn <= rgb_pixel((2*OUTBITS-1) downto OUTBITS);
vga_blu <= rgb_pixel( (OUTBITS-1) downto 0);
-- VGA syncs
vga_hsync <= '0' when ((phpos >= 656) and (phpos < 752)) else '1';
vga_vsync <= '0' when ((pvpos >= 490) and (pvpos < 492)) else '1';
end behaviour;
|
gpl-2.0
|
a3f5b3281a21e87c6472577941edab89
| 0.58911 | 3.552343 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab7/lab7_lib/hdl/fetch_stage_struct.vhd
| 1 | 7,433 |
-- VHDL Entity lab7_lib.fetch_stage.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 21:19:13 04/22/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY fetch_stage IS
PORT(
can_move_on : IN std_logic;
clk : IN std_logic; -- input
interrupt : IN std_logic := '0'; -- input
jaddr : IN std_logic_vector (15 DOWNTO 0); -- input
jump : IN std_logic := '0'; -- input
mdata : IN std_logic_vector (15 DOWNTO 0); -- input
mdelay : IN std_logic := '0'; -- input
reset : IN std_logic := '0'; -- input
stall : IN std_logic;
inst : OUT std_logic_vector (15 DOWNTO 0);
maddr : OUT std_logic_vector (15 DOWNTO 0);
pcval : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END fetch_stage ;
--
-- VHDL Architecture lab7_lib.fetch_stage.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 07:43:59 04/27/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY lab7_lib;
ARCHITECTURE struct OF fetch_stage IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL PC_Load_Control : std_logic;
SIGNAL PC_MUX_Control : std_logic_vector(1 DOWNTO 0);
SIGNAL control_bus : std_logic_vector( 6 DOWNTO 0 );
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout1 : std_logic;
SIGNAL dout2 : std_logic;
SIGNAL inst_MUX_Control : std_logic_vector(1 DOWNTO 0);
SIGNAL maddr_MUX_Control : std_logic_vector(1 DOWNTO 0);
SIGNAL pcval_In : std_logic_vector(15 DOWNTO 0);
SIGNAL signal_NOP : std_logic_vector(15 DOWNTO 0);
SIGNAL signal_ONE : std_logic_vector(15 DOWNTO 0); -- on interrupt
SIGNAL signal_PC_incrementAmt : std_logic_vector(15 DOWNTO 0);
SIGNAL signal_SPECIAL_INST : std_logic_vector(15 DOWNTO 0);
SIGNAL signal_ZERO : std_logic_vector(15 DOWNTO 0); -- on startup
-- Implicit buffer signal declarations
SIGNAL pcval_internal : std_logic_vector (15 DOWNTO 0);
-- ModuleWare signal declarations(v1.12) for instance 'PC' of 'adff'
SIGNAL mw_PCreg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'control_splitter' of 'split'
SIGNAL mw_control_splittertemp_din : std_logic_vector(6 DOWNTO 0);
-- Component Declarations
COMPONENT Fetch_FSM
PORT (
clock : IN std_logic;
int : IN std_logic;
jump : IN std_logic;
mdelay : IN std_logic;
reset : IN std_logic;
stall : IN std_logic;
control_bus : OUT std_logic_vector ( 6 DOWNTO 0 )
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : Fetch_FSM USE ENTITY lab7_lib.Fetch_FSM;
-- pragma synthesis_on
BEGIN
-- ModuleWare code(v1.12) for instance 'PC_incrementer' of 'add'
pc_incrementercombo_proc: PROCESS (pcval_internal, signal_PC_incrementAmt)
VARIABLE temp_din0 : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(16 DOWNTO 0);
VARIABLE temp_sum : unsigned(16 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & pcval_internal;
temp_din1 := '0' & signal_PC_incrementAmt;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
dout <= conv_std_logic_vector(temp_sum(15 DOWNTO 0),16);
END PROCESS pc_incrementercombo_proc;
-- ModuleWare code(v1.12) for instance 'PC' of 'adff'
pcval_internal <= mw_PCreg_cval;
pcseq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (dout2 = '1') THEN
mw_PCreg_cval <= pcval_In;
END IF;
END IF;
END PROCESS pcseq_proc;
-- ModuleWare code(v1.12) for instance 'INTERRUPT_INST' of 'constval'
signal_SPECIAL_INST <= "0000000000000001";
-- ModuleWare code(v1.12) for instance 'NOP' of 'constval'
signal_NOP <= "0000000000000000";
-- ModuleWare code(v1.12) for instance 'ONE' of 'constval'
signal_ONE <= "0000000000000001";
-- ModuleWare code(v1.12) for instance 'PC_increment_ONE' of 'constval'
signal_PC_incrementAmt <= "0000000000000001";
-- ModuleWare code(v1.12) for instance 'PC_load_ZERO' of 'constval'
dout1 <= '0';
-- ModuleWare code(v1.12) for instance 'ZERO' of 'constval'
signal_ZERO <= "0000000000000000";
-- ModuleWare code(v1.12) for instance 'PC_Load_MUX' of 'mux'
pc_load_muxcombo_proc: PROCESS(dout1, PC_Load_Control, can_move_on)
BEGIN
CASE can_move_on IS
WHEN '0' => dout2 <= dout1;
WHEN '1' => dout2 <= PC_Load_Control;
WHEN OTHERS => dout2 <= 'X';
END CASE;
END PROCESS pc_load_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'PC_MUX' of 'mux'
pc_muxcombo_proc: PROCESS(mdata, jaddr, dout, PC_MUX_Control)
BEGIN
CASE PC_MUX_Control IS
WHEN "00" => pcval_In <= mdata;
WHEN "01" => pcval_In <= jaddr;
WHEN "10" => pcval_In <= dout;
WHEN OTHERS => pcval_In <= (OTHERS => 'X');
END CASE;
END PROCESS pc_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'inst_MUX' of 'mux'
inst_muxcombo_proc: PROCESS(mdata, signal_NOP, signal_SPECIAL_INST,
inst_MUX_Control)
BEGIN
CASE inst_MUX_Control IS
WHEN "00" => inst <= mdata;
WHEN "01" => inst <= signal_NOP;
WHEN "10" => inst <= signal_SPECIAL_INST;
WHEN OTHERS => inst <= (OTHERS => 'X');
END CASE;
END PROCESS inst_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'maddr_MUX' of 'mux'
maddr_muxcombo_proc: PROCESS(signal_ZERO, signal_ONE, pcval_internal,
maddr_MUX_Control)
BEGIN
CASE maddr_MUX_Control IS
WHEN "00" => maddr <= signal_ZERO;
WHEN "01" => maddr <= signal_ONE;
WHEN "10" => maddr <= pcval_internal;
WHEN OTHERS => maddr <= (OTHERS => 'X');
END CASE;
END PROCESS maddr_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'control_splitter' of 'split'
mw_control_splittertemp_din <= control_bus;
control_splittercombo_proc: PROCESS (mw_control_splittertemp_din)
VARIABLE temp_din: std_logic_vector(6 DOWNTO 0);
BEGIN
temp_din := mw_control_splittertemp_din(6 DOWNTO 0);
inst_MUX_Control <= temp_din(1 DOWNTO 0);
maddr_MUX_Control <= temp_din(3 DOWNTO 2);
PC_Load_Control <= temp_din(4);
PC_MUX_Control <= temp_din(6 DOWNTO 5);
END PROCESS control_splittercombo_proc;
-- Instance port mappings.
U_0 : Fetch_FSM
PORT MAP (
clock => clk,
reset => reset,
mdelay => mdelay,
stall => stall,
jump => jump,
int => interrupt,
control_bus => control_bus
);
-- Implicit buffered output assignments
pcval <= pcval_internal;
END struct;
|
gpl-2.0
|
88dd7668221154644779767674302b0c
| 0.592089 | 3.573558 | false | false | false | false |
a4a881d4/ringbus
|
V3.0/pcie/pcie_config.vhd
| 1 | 5,163 |
---------------------------------------------------------------------------------------------------
--
-- Title : pcie_config
-- Design : ring bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : pcie_config.vhd
-- Generated : 2013/9/15
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : some pcie constant
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package pcie_config is
constant TX_CPLD_FMT_TYPE : std_logic_vector(6 downto 0) := "1001010";
constant TX_CPL_FMT_TYPE : std_logic_vector(6 downto 0) := "0001010";
constant RX_MEM_RD32_FMT_TYPE : std_logic_vector(6 downto 0) := "0000000";
constant RX_MEM_WR32_FMT_TYPE : std_logic_vector(6 downto 0) := "1000000";
constant RX_MEM_RD64_FMT_TYPE : std_logic_vector(6 downto 0) := "0100000";
constant RX_MEM_WR64_FMT_TYPE : std_logic_vector(6 downto 0) := "1100000";
constant RX_IO_RD32_FMT_TYPE : std_logic_vector(6 downto 0) := "0000010";
constant RX_IO_WR32_FMT_TYPE : std_logic_vector(6 downto 0) := "1000010";
constant Device_TC : std_logic_vector(2 downto 0) := "000";
constant Device_TD : std_logic:='0';
constant Device_EP : std_logic:='0';
constant Device_ATTR : std_logic_vector(1 downto 0) := "00";
constant Device_WR_TAG : std_logic_vector(7 downto 0) := "00000000";
component endpoint_blk_plus_v1_15
port (
pci_exp_rxn : in std_logic_vector((1 - 1) downto 0);
pci_exp_rxp : in std_logic_vector((1 - 1) downto 0);
pci_exp_txn : out std_logic_vector((1 - 1) downto 0);
pci_exp_txp : out std_logic_vector((1 - 1) downto 0);
sys_clk : in STD_LOGIC;
sys_reset_n : in STD_LOGIC;
refclkout : out std_logic;
trn_clk : out STD_LOGIC;
trn_reset_n : out STD_LOGIC;
trn_lnk_up_n : out STD_LOGIC;
trn_td : in STD_LOGIC_VECTOR((64 - 1) downto 0);
trn_trem_n: in STD_LOGIC_VECTOR (7 downto 0);
trn_tsof_n : in STD_LOGIC;
trn_teof_n : in STD_LOGIC;
trn_tsrc_dsc_n : in STD_LOGIC;
trn_tsrc_rdy_n : in STD_LOGIC;
trn_tdst_dsc_n : out STD_LOGIC;
trn_tdst_rdy_n : out STD_LOGIC;
trn_terrfwd_n : in STD_LOGIC ;
trn_tbuf_av : out STD_LOGIC_VECTOR (( 4 -1 ) downto 0 );
trn_rd : out STD_LOGIC_VECTOR((64 - 1) downto 0);
trn_rrem_n: out STD_LOGIC_VECTOR (7 downto 0);
trn_rsof_n : out STD_LOGIC;
trn_reof_n : out STD_LOGIC;
trn_rsrc_dsc_n : out STD_LOGIC;
trn_rsrc_rdy_n : out STD_LOGIC;
trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 );
trn_rdst_rdy_n : in STD_LOGIC;
trn_rerrfwd_n : out STD_LOGIC;
trn_rnp_ok_n : in STD_LOGIC;
trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 );
trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 );
trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 );
trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 );
trn_rcpl_streaming_n : in STD_LOGIC;
cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
cfg_rd_wr_done_n : out STD_LOGIC;
cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
cfg_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
cfg_wr_en_n : in STD_LOGIC;
cfg_rd_en_n : in STD_LOGIC;
cfg_err_cor_n : in STD_LOGIC;
cfg_err_cpl_abort_n : in STD_LOGIC;
cfg_err_cpl_timeout_n : in STD_LOGIC;
cfg_err_cpl_unexpect_n : in STD_LOGIC;
cfg_err_ecrc_n : in STD_LOGIC;
cfg_err_posted_n : in STD_LOGIC;
cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
cfg_err_ur_n : in STD_LOGIC;
cfg_err_cpl_rdy_n : out STD_LOGIC;
cfg_err_locked_n : in STD_LOGIC;
cfg_interrupt_n : in STD_LOGIC;
cfg_interrupt_rdy_n : out STD_LOGIC;
cfg_pm_wake_n : in STD_LOGIC;
cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_to_turnoff_n : out STD_LOGIC;
cfg_interrupt_assert_n : in STD_LOGIC;
cfg_interrupt_di : in STD_LOGIC_VECTOR(7 downto 0);
cfg_interrupt_do : out STD_LOGIC_VECTOR(7 downto 0);
cfg_interrupt_mmenable : out STD_LOGIC_VECTOR(2 downto 0);
cfg_interrupt_msienable: out STD_LOGIC;
cfg_trn_pending_n : in STD_LOGIC;
cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dsn: in STD_LOGIC_VECTOR (63 downto 0 );
fast_train_simulation_only : in STD_LOGIC
);
end component;
end rb_config;
|
lgpl-3.0
|
8195328f3fa38cbf5f4b5739d549468f
| 0.56595 | 3.125303 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/t80/t80_alu.vhd
| 1 | 13,576 |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity t80_alu is
generic(
t80mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end t80_alu;
architecture rtl of t80_alu is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(t80mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));
else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if t80mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
gpl-2.0
|
4e350e911a6c2aaace2bdaf511daf27c
| 0.470978 | 3.230842 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_mult.vhd
| 1 | 10,377 |
--------------------------------------------------------------------------------
--
-- Title : fp23_mult
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : floating point multiplier
--
-------------------------------------------------------------------------------
--
-- Version 1.0 22.02.2013
-- Description:
-- Multiplier for FP - 2DSP48E1 slices
-- 4 clock cycles delay
--
--
-- Version 1.2 15.01.2014
-- Description:
-- 5 clock cycles delay, improved logic
--
-- Version 1.3 24.03.2015
-- Description:
-- Deleted din_en signal
-- This version is fully pipelined with 1 DSP48E1!
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.DSP48E1;
use unisim.vcomponents.DSP48E2;
library work;
use work.reduce_pack.all;
use work.fp_m1_pkg.fp23_data;
entity fp23_mult is
generic(
EXP_DIF : std_logic_vector(5 downto 0):="011111"; -- DIFF_EXP
XSERIES : string:="7SERIES" --! Xilinx series
);
port(
aa : in fp23_data; --! Multiplicand A
bb : in fp23_data; --! Multiplier B
cc : out fp23_data; --! Product C
enable : in std_logic; --! Input data enable
valid : out std_logic; --! Output data valid
reset : in std_logic; --! Reset
clk : in std_logic --! Clock
);
end fp23_mult;
architecture fp23_mult of fp23_mult is
type std_logic_array_4x6 is array(3 downto 0) of std_logic_vector(5 downto 0);
signal man_aa : std_logic_vector(29 downto 0);
signal man_bb : std_logic_vector(17 downto 0);
type std_logic_array_2x5 is array(1 downto 0) of std_logic_vector(5 downto 0);
signal exp_az : std_logic_array_2x5;
signal exp_bz : std_logic_array_2x5;
signal exp_cc : std_logic_vector(5 downto 0);
signal exp_df : std_logic_vector(6 downto 0);
signal sig_cc : std_logic;
signal man_cc : std_logic_vector(15 downto 0);
signal prod : std_logic_vector(47 downto 0);
signal sig_ccz : std_logic_vector(2 downto 0);
signal exp_underflow : std_logic;
signal exp_underflowz : std_logic;
---------------------------------------
signal expa_or : std_logic;
signal expb_or : std_logic;
signal exp_zero : std_logic;
signal exp_zeroz : std_logic;
signal enaz : std_logic_vector(3 downto 0);
begin
---- finding zero exponents for multipliers ----
expa_or <= or_reduce(aa.exp) when rising_edge(clk);
expb_or <= or_reduce(bb.exp) when rising_edge(clk);
exp_zero <= (expa_or and expb_or) when rising_edge(clk);
exp_zeroz <= exp_zero when rising_edge(clk);
-- forming fractions for mulptiplier
man_aa(29 downto 18) <= x"000";
man_aa(17 downto 0) <= "01" & aa.man;
man_bb <= "01" & bb.man;
x7SERIES: if (XSERIES = "7SERIES") generate
NORMALIZE: DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT",
B_INPUT => "DIRECT",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 1,
CARRYINSELREG => 1,
CREG => 1,
DREG => 1,
INMODEREG => 1,
MREG => 1,
OPMODEREG => 1,
PREG => 1
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
PCOUT => open,
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open,
P => prod,
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'),
BCIN => (others=>'0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
PCIN => (others=>'0'),
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => (others=>'0'),
CARRYINSEL => (others=>'0'),
CLK => clk,
INMODE => (others=>'0'),
OPMODE => "0000101",
-- Data: 30-bit (each) input: Data Ports
A => man_aa,
B => man_bb,
C => (others=>'0'),
CARRYIN => '0',
D => (others=>'0'),
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => enable,
CEA2 => '1',
CEAD => '0',
CEALUMODE => '1',
CEB1 => enable,
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => reset,
RSTP => reset
);
end generate;
xULTRA: if (XSERIES = "ULTRA") generate
NORMALIZE : DSP48E2
generic map (
-- Feature Control Attributes: Data Path Selection
AMULTSEL => "A",
A_INPUT => "DIRECT",
BMULTSEL => "B",
B_INPUT => "DIRECT",
PREADDINSEL => "A",
USE_MULT => "MULTIPLY",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 1,
CARRYINSELREG => 1,
CREG => 1,
DREG => 1,
INMODEREG => 1,
MREG => 1,
OPMODEREG => 1,
PREG => 1
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
PCOUT => open,
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open,
P => prod,
XOROUT => open,
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'),
BCIN => (others=>'0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
PCIN => (others=>'0'),
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => (others=>'0'),
CARRYINSEL => (others=>'0'),
CLK => clk,
INMODE => (others=>'0'),
OPMODE => "000000101",
-- Data inputs: Data Ports
A => man_aa,
B => man_bb,
C => (others=>'0'),
CARRYIN => '0',
D => (others=>'0'),
-- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
CEA1 => enable,
CEA2 => '1',
CEAD => '0',
CEALUMODE => '1',
CEB1 => enable,
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => reset,
RSTP => reset
);
end generate;
---- exp difference ----
pr_exp: process(clk) is
begin
if rising_edge(clk) then
exp_az <= exp_az(0) & aa.exp;
exp_bz <= exp_bz(0) & bb.exp;
exp_df <= ('0' & exp_az(1)) + ('0' & exp_bz(1)) - ('0' & EXP_DIF);
if (exp_df(exp_df'left) = '0') then
exp_cc <= exp_df(exp_df'left-1 downto 0) + prod(33);
else
exp_cc <= (others=>'0');
end if;
end if;
end process;
-- find sign as xor of signs --
pr_sign: process(clk) is
begin
if rising_edge(clk) then
sig_cc <= aa.sig xor bb.sig;
sig_ccz <= sig_ccz(1 downto 0) & sig_cc;
end if;
end process;
-- find fraction --
pr_frac: process(clk) is
begin
if rising_edge(clk) then
if (prod(33) = '0') then
man_cc <= prod(31 downto 16);
else
man_cc <= prod(32 downto 17);
end if;
end if;
end process;
-- data out and result --
--exp_underflowz <= (exp_underflow and exp_zeroz) when rising_edge(clk);
exp_underflowz <= (exp_zeroz) when rising_edge(clk);
pr_dout: process(clk) is
begin
if rising_edge(clk) then
if (exp_underflowz = '0') then
cc <= ("000000", '0', x"0000");
else
cc <= (exp_cc, sig_ccz(2), man_cc);
end if;
end if;
end process;
enaz <= enaz(2 downto 0) & enable when rising_edge(clk);
valid <= enaz(3) when rising_edge(clk);
end fp23_mult;
|
mit
|
b179991d5f39b3fc8bfce3898939ae7c
| 0.52732 | 3.061062 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano/DE0_Nano_top_level.vhd
| 1 | 2,397 |
-- #############################################################################
-- DE0_Nano_top_level.vhd
-- ======================
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
LED : out std_logic_vector(7 downto 0);
-- KEY_N
KEY_N : in std_logic_vector(1 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
EPCS_ASDO : out std_logic;
EPCS_DATA0 : in std_logic;
EPCS_DCLK : out std_logic;
EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
G_SENSOR_CS_N : out std_logic;
G_SENSOR_INT : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
GPIO_2 : inout std_logic_vector(12 downto 0);
GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(33 downto 0);
GPIO_0_IN : in std_logic_vector(1 downto 0);
-- GPIO_1
GPIO_1 : inout std_logic_vector(33 downto 0);
GPIO_1_IN : in std_logic_vector(1 downto 0)
);
end entity DE0_Nano_top_level;
architecture rtl of DE0_Nano_top_level is
begin
end;
|
unlicense
|
4535614781bd7cab42cf6e5ec4dde085
| 0.50438 | 3.409673 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_fix2float.vhd
| 1 | 7,928 |
-------------------------------------------------------------------------------
--
-- Title : fp23_fix2float
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : Signed fix 16 bit to float fp23 converter
--
-------------------------------------------------------------------------------
--
-- Version 1.0 25.05.2013
-- Description:
-- Bus width for:
-- din = 15
-- dout = 23
-- exp = 6
-- sign = 1
-- mant = 15 + 1
-- Math expression:
-- A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)
-- NB:
-- 1's complement
-- Converting from fixed to float takes only 9 clock cycles
--
-- MODES: Mode0 : normal fix2float (1's complement data)
-- Mode1 : +1 fix2float for negative data (uncomment and
-- change this code a little: add a component
-- sp_addsub_m1 and some signals): 2's complement data.
--
--
-- Version 1.1 15.01.2015
-- Description:
-- Based on fp27_fix2float_m3 (FP27 FORMAT)
-- New version of FP (Reduced fraction width)
--
-- Version 1.2 18.03.2015
-- Description:
-- Changed CE signal
-- This version has ena. See OR5+OR5 stages
--
-- Version 1.3 24.03.2015
-- Description:
-- Deleted ENABLE signal
-- This version is fully pipelined !!!
--
-- Version 1.4 04.10.2015
-- Description:
-- DSP48E1 has been removed. Barrel shift is used now.
-- Delay 9 clocks
--
-- Version 1.5 04.01.2016
-- Description:
-- New barrel shifter with minimum resources.
-- New FP format: FP24 -> FP23.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fp_m1_pkg.fp23_data;
use work.reduce_pack.nor_reduce;
entity fp23_fix2float is
port(
din : in std_logic_vector(15 downto 0); --! Fixed input data
ena : in std_logic; --! Data enable
dout : out fp23_data; --! Float output data
vld : out std_logic; --! Data out valid
clk : in std_logic; --! Clock
reset : in std_logic --! Negative Reset
);
end fp23_fix2float;
architecture fp23_fix2float of fp23_fix2float is
constant FP32_EXP : std_logic_vector(5 downto 0):="011111";
signal true_form : std_logic_vector(15 downto 0):=(others => '0');
signal norm : std_logic_vector(15 downto 0);
signal frac : std_logic_vector(15 downto 0);
signal set_zero : std_logic;
signal sum_man : std_logic_vector(15 downto 0);
signal msb_num : std_logic_vector(4 downto 0);
signal msb_numn : std_logic_vector(5 downto 0);
signal msb_numt : std_logic_vector(4 downto 0);
signal msb_numz : std_logic_vector(5 downto 0);
signal expc : std_logic_vector(5 downto 0); -- (E - 127) by (IEEE754)
signal sign : std_logic_vector(2 downto 0);
signal valid : std_logic_vector(4 downto 0);
--signal dinz : std_logic_vector(15 downto 0);
signal dinz : std_logic_vector(15 downto 0);
signal dinh : std_logic;
signal dinx : std_logic;
begin
-- x2S_COMPL: if (IS_CMPL = TRUE) generate
pr_sgn: process(clk) is
begin
if rising_edge(clk) then
dinz <= din - din(15);
dinh <= din(15);
end if;
end process;
---- make abs(data) by using XOR ----
pr_abs: process(clk) is
begin
if rising_edge(clk) then
true_form(15) <= dinz(15) or dinh;
for ii in 0 to 14 loop
true_form(ii) <= dinz(ii) xor (dinz(15) or dinh);
end loop;
end if;
end process;
sum_man <= true_form(14 downto 0) & '0' when rising_edge(clk);
---- find MSB (highest '1' position) ----
pr_lead: process(clk) is
begin
if rising_edge(clk) then
if (true_form(14-00)='1') then msb_num <= "00001";--"00010";--"00001";
elsif (true_form(14-01)='1') then msb_num <= "00010";--"00011";--"00010";
elsif (true_form(14-02)='1') then msb_num <= "00011";--"00100";--"00011";
elsif (true_form(14-03)='1') then msb_num <= "00100";--"00101";--"00100";
elsif (true_form(14-04)='1') then msb_num <= "00101";--"00110";--"00101";
elsif (true_form(14-05)='1') then msb_num <= "00110";--"00111";--"00110";
elsif (true_form(14-06)='1') then msb_num <= "00111";--"01000";--"00111";
elsif (true_form(14-07)='1') then msb_num <= "01000";--"01001";--"01000";
elsif (true_form(14-08)='1') then msb_num <= "01001";--"01010";--"01001";
elsif (true_form(14-09)='1') then msb_num <= "01010";--"01011";--"01010";
elsif (true_form(14-10)='1') then msb_num <= "01011";--"01100";--"01011";
elsif (true_form(14-11)='1') then msb_num <= "01100";--"01101";--"01100";
elsif (true_form(14-12)='1') then msb_num <= "01101";--"01110";--"01101";
elsif (true_form(14-13)='1') then msb_num <= "01110";--"01111";--"01110";
elsif (true_form(14-14)='1') then msb_num <= "01111";--"10000";--"01111";
else msb_num <= "00000";
end if;
end if;
end process;
dinx <= dinz(15) xor dinh when rising_edge(clk);
msb_numz(5) <= dinx when rising_edge(clk);
msb_numz(4 downto 0) <= msb_num;
msb_numt <= msb_num when rising_edge(clk);
---- barrel shifter by 0-15 ----
norm <= STD_LOGIC_VECTOR(SHL(UNSIGNED(sum_man), UNSIGNED(msb_num))) when rising_edge(clk);
frac <= norm when rising_edge(clk);
---- Check zero value for fraction and exponent ----
set_zero <= nor_reduce(msb_numz) when rising_edge(clk);
---- find exponent (inv msb - x"2E") ----
pr_sub: process(clk) is
begin
if rising_edge(clk) then
if (set_zero = '1') then
expc <= (others=>'0');
else
expc <= FP32_EXP - msb_numt;
end if;
end if;
end process;
---- sign delay ----
sign <= sign(sign'left-1 downto 0) & true_form(15) when rising_edge(clk);
---- output data ----
pr_out: process(clk) is
begin
if rising_edge(clk) then
if (reset = '1') then
dout <= ("000000", '0', x"0000");
elsif (valid(valid'left) = '1') then
dout <= (expc, sign(sign'left), frac);
end if;
end if;
end process;
valid <= valid(valid'left-1 downto 0) & ena when rising_edge(clk);
vld <= valid(valid'left) when rising_edge(clk);
end fp23_fix2float;
|
mit
|
828ab55c0e2f1e92f43972392297fe9b
| 0.558022 | 3.209717 | false | false | false | false |
andreasschuh/Multi-Eigenmode-Controller
|
Interface.vhd
| 1 | 5,945 |
----------------------------------------------------------------------------------
-- Company: MIT
-- Engineer: Andreas Schuh
-- Top level design
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED;
library UNISIM;
use UNISIM.VComponents.all;
entity interface is
port( --clocks: 100 MHz and 24 MHz for Spartan 3A DSP
cmos_clk : in std_logic;
cmos24_clk : in std_logic;
--DAC Interface
-- *removed*
--ADC interace:
-- *removed*
);
end interface;
architecture Behavioral of interface is
component ADC
port(
ADC1out : out std_logic_vector(15 downto 0):=(others=>'0');
ADC2out : out std_logic_vector(15 downto 0):=(others=>'0');
-- *rest removed*
);
END COMPONENT;
component DAC
port(
DAC1in : in std_logic_vector(15 downto 0):=(others=>'0');
DAC2in : in std_logic_vector(15 downto 0):=(others=>'0');
-- *rest removed*
);
end component;
COMPONENT FloatToFixed -- Floating point to fixed point conversion component, from XILINX IP Core library
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT FixedToFloat -- Fixed point to floating point conversion component, from XILINX IP Core library
PORT (
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clk : IN STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT compensator -- main component with compensator calculation, see separate file
Port (
ADC1in : in STD_LOGIC_VECTOR (31 downto 0);
ADC2in : in STD_LOGIC_VECTOR (31 downto 0);
DAC1out : out STD_LOGIC_VECTOR (31 downto 0);
DAC2out : out STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC
);
END COMPONENT;
COMPONENT clock -- DCM for slower clock rate generation
PORT (
U1_CLKIN_IN : IN std_logic;
U1_RST_IN : IN std_logic;
U1_CLKDV_OUT : OUT std_logic;
U1_CLKIN_IBUFG_OUT : OUT std_logic;
U1_CLK0_OUT : OUT std_logic;
U2_CLK0_OUT : OUT std_logic;
U2_LOCKED_OUT : OUT std_logic
);
END COMPONENT;
-- Some signals for ADCs and DACs removed
signal add1 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal add2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal resultfloat : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal resultfloat2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal da1_in : std_logic_vector(15 downto 0):="0000000000000000";
signal da2_in : std_logic_vector(15 downto 0):="0000000000000000";
signal adc1_out : std_logic_vector(15 downto 0);
signal adc2_out : std_logic_vector(15 downto 0);
-- DCM Signals
signal clock_divided : std_logic;
signal cmosbuff_clk : std_logic;
signal idac1ff : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal idac1ff2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal idac1 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal idac2ff : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal idac2ff2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal idac2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal iadc1ff : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal iadc1ff2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal iadc1 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal iadc2ff : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal iadc2ff2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal iadc2 : std_logic_vector(31 downto 0):="00000000000000000000000000000000";
begin
DAC1: DAC PORT MAP(
DAC1in => da1_in,
DAC2in => da2_in,
-- *rest removed*
);
ADC1: ADC
ADC1out => adc1_out,
ADC2out => adc2_out,
-- *rest removed*
);
Fixed1 : FixedToFloat
PORT MAP (
a => adc1_out,
clk => cmosbuff_clk,
result => iadc1
);
Fixed2 : FixedToFloat
PORT MAP (
a => adc2_out,
clk => cmosbuff_clk, -
result => iadc2
);
Float1 : FloatToFixed
PORT MAP (
a => idac1,
clk => cmosbuff_clk,
result => da1_in
);
Float2 : FloatToFixed
PORT MAP (
a => idac2,
clk => cmosbuff_clk,
result => da2_in
);
-- main Compensator component
compensator1 : compensator
PORT MAP (
ADC1in => add1,
ADC2in => add2,
DAC1out => resultfloat,
DAC2out => resultfloat2,
clock => clock_divided
);
Inst_clock: clock
PORT MAP(
U1_CLKIN_IN => cmos_clk,
U1_RST_IN => '0',
U1_CLKDV_OUT => clock_divided,
U1_CLKIN_IBUFG_OUT => open,
U1_CLK0_OUT => cmosbuff_clk,
U2_CLK0_OUT => open,
U2_LOCKED_OUT => open
);
-- FF Buffering result/output of compensator
process (cmosbuff_clk)
begin
if(cmosbuff_clk'event and cmosbuff_clk='1') then
idac1ff <= resultfloat;
idac1ff2 <= idac1ff;
idac1 <= idac1ff2;
idac2ff <= resultfloat2;
idac2ff2 <= idac2ff;
idac2 <= idac2ff2;
end if;
end process;
-- FF Buffering
process (clock_divided)
begin
if(clock_divided'event and clock_divided='1') then
iadc1ff <= iadc1;
iadc1ff2 <= iadc1ff;
add1 <= iadc1ff2;
iadc2ff <= iadc2;
iadc2ff2 <= iadc2ff;
add2 <= iadc2ff2;
end if;
end process;
end Behavioral;
|
mit
|
a5056dd582319a8c6111bd47fc6a68b9
| 0.619344 | 3.308292 | false | false | false | false |
a4a881d4/ringbus
|
V3.0/testbench/rcbus2_tb.vhd
| 1 | 2,265 |
---------------------------------------------------------------------------------------------------
--
-- Title : Testbench for Two End Point Example for Ring Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : rbus2_tb.vhd
-- Generated : 2013/9/10
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Testbench for Two End Point Example for Ring Bus
-- two end point
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.contr_config.all;
entity RCBUS2_TB is
end RCBUS2_TB;
library simio;
use simio.SIMIO_PACKAGE.all;
architecture sim of RCBUS2_TB is
component RCBUS2
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- CPU bus
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic
);
end component;
signal clk : STD_LOGIC :='0';
signal rst : STD_LOGIC :='0';
signal dspce,dspwr,wr,cs0 : std_logic :='0';
signal w_r,rd : std_logic :='0';
signal addr : std_logic_vector( 7 downto 0 );
signal Din : std_logic_vector( 7 downto 0 );
signal Dout : std_logic_vector( 7 downto 0 );
signal cpuClk : std_logic :='0';
begin
cpu:dspemulator
generic map(
DSP_INC_FILE => "rcbus2.inx",
ABUS_WIDTH => 8,
DBUS_WIDTH => 8 )
port map(
clk => clk,
dspce => dspce,
dspa => addr,
data => din,
wr => w_r,
IOstb => dspwr
);
cbus2:RCBUS2
port map(
-- system
clk =>clk,
rst => rst,
wr => wr,
rd => rd,
addr => addr,
Din => Din,
Dout=>Dout,
cpuClk => clk
);
wr<=(not dspwr) and (not w_r);
rd<=(not dspwr) and w_r;
rst <= '1', '0' after 10 ns;
clk <= not clk after 1 ns;
end sim;
|
lgpl-3.0
|
b051a34d47e51c4015823bf0f4187c6c
| 0.459603 | 3.273121 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd
| 1 | 12,579 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (6 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0):= hex_to_std_logic_vector("0",7);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(6 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
7,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
mit
|
13a31a93175fe24f0e0ce36a1c0e7da6
| 0.54742 | 3.67807 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/lib/ControllerConstants.vhd
| 1 | 4,820 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE controller_constants IS
-- STATE MACHINE SIGNAL TYPE
type t_state_type IS (fetch_0, fetch_1, fetch_2, execute_0, execute_1, execute_2, execute_3, execute_4);
-- CONTROLLER SIGNAL CONSTANTS
-- ENABLE
CONSTANT c_clock_registerbank : INTEGER := 00;
CONSTANT c_clock_registerbank_size : INTEGER := 32;
CONSTANT c_clock_register_a : INTEGER := 32;
CONSTANT c_clock_register_b : INTEGER := 33;
CONSTANT c_clock_program_counter : INTEGER := 34;
CONSTANT c_clock_instruction_register : INTEGER := 35;
CONSTANT c_clock_status_register : INTEGER := 36;
CONSTANT c_clock_mar : INTEGER := 37;
CONSTANT c_clock_mdr : INTEGER := 38;
CONSTANT c_clock_ram : INTEGER := 39;
-- SELECTION
CONSTANT c_select_mux_registerbank_a : INTEGER := 00;
CONSTANT c_select_mux_registerbank_b : INTEGER := 05;
CONSTANT c_select_mux_registerbank_width : INTEGER := 05;
CONSTANT c_select_mux_main : INTEGER := 09;
CONSTANT c_select_mux_main_width : INTEGER := 03;
CONSTANT c_select_mux_jump : INTEGER := 12;
CONSTANT c_select_mux_status_alu_shifter : INTEGER := 13;
CONSTANT c_select_mux_pc_incrementer : INTEGER := 14;
-- FUNCTION
CONSTANT c_function_alu : INTEGER := 00;
CONSTANT c_function_alu_width : INTEGER := 04;
CONSTANT c_function_alu_cin : INTEGER := 04;
CONSTANT c_function_shifter : INTEGER := 05;
CONSTANT c_function_shifter_width : INTEGER := 03;
CONSTANT c_function_ram_we : INTEGER := 08;
-- OPCODES
-- DIRECT
-- Loads value at memory addres of the 16 bottom bits to a register
CONSTANT c_opcode_loadDirect : POSITIVE := 02;
-- Stores value of source register at memory address on the 16 bottom bits
CONSTANT c_opcode_storeDirect : POSITIVE := 03;
-- Adds the value of source and destination registers and stores it at the destination
CONSTANT c_opcode_addDirect : POSITIVE := 04;
-- Moves the value from source to destination register
CONSTANT c_opcode_moveDirect : POSITIVE := 05;
-- Subtracts the value of source and destination registers and stores it at the destination
CONSTANT c_opcode_subDirect : POSITIVE := 06;
-- Ands the value of source and destination registers and stores it at the destination
CONSTANT c_opcode_andDirect : POSITIVE := 07;
-- Ors the value of source and destination registers and stores it at the destination
CONSTANT c_opcode_orDirect : POSITIVE := 08;
-- Xors the value of source and destination registers and stores it at the destination
CONSTANT c_opcode_xorDirect : POSITIVE := 09;
-- Xnors the value of source and destination registers and stores it at the destination
CONSTANT c_opcode_xnorDirect : POSITIVE := 10;
-- Logical shitfs the value of source register and overwrites it's value
CONSTANT c_opcode_shiftLogicalLeft : POSITIVE := 17;
CONSTANT c_opcode_shiftLogicalRight : POSITIVE := 18;
-- Arithmetic shitfs the value of source register and overwrites it's value
CONSTANT c_opcode_shiftArithmeticLeft : POSITIVE := 19;
CONSTANT c_opcode_shiftArithmeticRight : POSITIVE := 20;
-- Rotates the value of source register and overwrites it's value
CONSTANT c_opcode_shiftRotateLeft : POSITIVE := 21;
CONSTANT c_opcode_shiftRotateRight : POSITIVE := 22;
-- INDIRECT
-- Inconditional jump to address in the address register
CONSTANT c_opcode_jumpIndirect : POSITIVE := 11;
-- Conditional jump to address in the address register if source is equal to destination
CONSTANT c_opcode_jumpEqualsIndirect : POSITIVE := 12;
-- Conditional jump to address in the address register if source is not equal to destination
CONSTANT c_opcode_jumpNotEqualsIndirect : POSITIVE := 13;
-- Conditional jump to address in the address register if source is lesser then destination
CONSTANT c_opcode_jumpLesserThenIndirect : POSITIVE := 14;
-- Conditional jump to address in the address register if source is greater then destination
CONSTANT c_opcode_jumpGreaterThenIndirect : POSITIVE := 15;
-- Inconditional jump to address, saving the return value to return address register
CONSTANT c_opcode_jumpAndLink : POSITIVE := 16;
CONSTANT c_opcode_loadIndirect : POSITIVE := 23;
CONSTANT c_opcode_storeIndirect : POSITIVE := 24;
-- IMEDIATE
-- Loads bottom 16 bits of instruction word to a register
CONSTANT c_opcode_loadImediate : POSITIVE := 01;
-- REGISTERS
CONSTANT c_register_returnAddress : POSITIVE := 30;
END PACKAGE;
|
mit
|
8490f2f8d05a440555a9fac8fb6564aa
| 0.682158 | 4.009983 | false | false | false | false |
NESHomebrew/cs207-NES-Guitar-Synth
|
DesignLab Libraries/A595/Chip_Designer/Simulate_Your_Chip_Design.vhd
| 1 | 1,502 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library DesignLab;
--use DesignLab.ALL;
entity Simulate_Your_CCL_Design is
end entity;
architecture sim of Simulate_Your_CCL_Design is
constant period: time := 10 ns;
signal clk: std_logic := '1';
signal rst: std_logic := '0';
COMPONENT A595
PORT(
--Put your custom external connections here
buttons : IN std_logic_vector(3 downto 0);
leds : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Define your external connections here
signal buttons: std_logic_vector(3 downto 0) := "1010";
signal leds: std_logic_vector(3 downto 0);
begin
clk <= not clk after period/2;
-- Reset
process
begin
wait for 5 ns;
rst <= '1';
wait for 20 ns;
rst <= '0';
wait;
end process;
uut: A595 PORT MAP(
--Define your external connections here
buttons => buttons,
leds => leds
);
process
begin
wait until rst='1';
wait until rst='0';
wait until rising_edge(clk);
-- This is where you should start providing your stimulus to test your design.
-- Provide stimulus on the buttons
buttons <= "0000";
wait for 100 ns;
-- Check that the leds match
assert( leds = "0000");
-- Provide stimulus on the buttons
buttons <= "1111";
wait for 100 ns;
-- Check that the leds match
assert( leds = "1111");
wait for 200 ns;
report "Finsihed" severity failure;
end process;
end sim;
|
mit
|
c4cfcb1b111f1ea323f67eef35ad62d5
| 0.651798 | 3.429224 | false | false | false | false |
a4a881d4/ringbus
|
simio/simio.vhd
| 1 | 6,897 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
package SIMIO_PACKAGE is
component dspemulator
generic ( DSP_INC_FILE : string := "UNUSED";
ABUS_WIDTH : integer := 16;
DBUS_WIDTH : integer := 16 );
port (
clk : in std_logic;
dspce : out std_logic;
dspa : out std_logic_vector( ABUS_WIDTH-1 downto 0);
data : out std_logic_vector( DBUS_WIDTH-1 downto 0);
wr : out std_logic;
IOstb : out std_logic);
end component ;
component probe
generic ( PROBE_FILE : string := "UNUSED";
SIGNAL1_WIDTH : NATURAL:=6;
SIGNAL1_MASK : integer:=0;
SIGNAL1_TRG : integer:=0;
SIGNAL2_WIDTH : NATURAL:=6;
SIGNAL2_MASK : integer:=0;
SIGNAL2_TRG : integer:=0;
SIGNAL3_WIDTH : NATURAL:=6;
SIGNAL3_MASK : integer:=0;
SIGNAL3_TRG : integer:=0;
SIGNAL4_WIDTH : NATURAL:=6;
SIGNAL4_MASK : integer:=0;
SIGNAL4_TRG : integer:=0);
port (
clk : in std_logic;
signal1 : in std_logic_vector(SIGNAL1_WIDTH-1 downto 0);
signal2 : in std_logic_vector(SIGNAL2_WIDTH-1 downto 0);
signal3 : in std_logic_vector(SIGNAL3_WIDTH-1 downto 0);
signal4 : in std_logic_vector(SIGNAL4_WIDTH-1 downto 0));
end component;
component ADemulator
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component DAemulator
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component IQADemulator
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iout : out std_logic_vector(DATA_WIDTH-1 downto 0);
Qout : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component IQDAemulator
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iin : in std_logic_vector(DATA_WIDTH-1 downto 0);
Qin : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
function int_to_str( value : integer ) return string;
function hex_str_to_int( str : string ) return integer;
function hex_to_str( value : integer ) return string;
procedure Shrink_line(L : inout LINE; pos : in integer);
end SIMIO_PACKAGE;
package body SIMIO_PACKAGE is
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0 ) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 => line_no(index) := '0';
when 1 => line_no(index) := '1';
when 2 => line_no(index) := '2';
when 3 => line_no(index) := '3';
when 4 => line_no(index) := '4';
when 5 => line_no(index) := '5';
when 6 => line_no(index) := '6';
when 7 => line_no(index) := '7';
when 8 => line_no(index) := '8';
when 9 => line_no(index) := '9';
when others => ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'A' => digit := 10;
when 'a' => digit := 10;
when 'B' => digit := 11;
when 'b' => digit := 11;
when 'C' => digit := 12;
when 'c' => digit := 12;
when 'D' => digit := 13;
when 'd' => digit := 13;
when 'E' => digit := 14;
when 'e' => digit := 14;
when 'F' => digit := 15;
when 'f' => digit := 15;
when others=>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
function hex_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while ( index<=8 ) loop
digit := ivalue MOD 16;
ivalue := ivalue/16;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when 10 =>
line_no(index) := 'A';
when 11 =>
line_no(index) := 'B';
when 12 =>
line_no(index) := 'C';
when 13 =>
line_no(index) := 'D';
when 14 =>
line_no(index) := 'E';
when 15 =>
line_no(index) := 'F';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l,stmp);
end if;
end;
end SIMIO_PACKAGE;
|
lgpl-3.0
|
7ee1c8e7e7f94764e75d9f7f49701bfe
| 0.481079 | 3.553323 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano-SoC/DE0_Nano_SoC_top_level.vhd
| 1 | 3,848 |
-- #############################################################################
-- DE0_Nano_SoC_top_level.vhd
-- ==========================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_top_level;
architecture rtl of DE0_Nano_SoC_top_level is
begin
end;
|
unlicense
|
005fe371e62f42e02c66462422155132
| 0.509875 | 3.21202 | false | false | false | false |
ymahajan456/HighLevelSynthesis
|
Version_1.0/Testing/data_path.vhd
| 1 | 8,153 |
-- ============================================================
-- File Name: data_path.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2016-11-22
-- ************************************************************
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY data_path IS
GENERIC(
data_width: INTEGER := 16);
PORT(
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
T: IN STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0');
a: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
d: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
b: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
c: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_0: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_1: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_2: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0'));
END ENTITY;
ARCHITECTURE data OF data_path is
SIGNAL clr_REG10, ena_REG10, clk_REG10: STD_LOGIC := '0';
SIGNAL ena_REG8, clk_REG9, clr_REG9, ena_REG9, clr_REG8: STD_LOGIC := '0';
SIGNAL outp_REG9, inp_REG10, outp_REG10, inp_REG9: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL inp_REG7, outp_REG7, inp_REG8, outp_REG8, outp_REG6: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clk_REG7, clr_REG7, ena_REG7, clk_REG8, ena_REG6: STD_LOGIC := '0';
SIGNAL outp_REG4, inp_REG5, outp_REG5, inp_REG6, inp_REG4: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clr_REG5, ena_REG5, clk_REG6, clr_REG6, clk_REG5: STD_LOGIC := '0';
SIGNAL inp_REG2, outp_REG2, inp_REG3, outp_REG3, outp_REG1: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL ena_REG3, clk_REG4, clr_REG4, ena_REG4, clr_REG3: STD_LOGIC := '0';
SIGNAL outp_ALU3, inp_REG0, outp_REG0, inp_REG1, in_2_ALU3: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clk_REG2, clr_REG2, ena_REG2, clk_REG3, ena_REG1: STD_LOGIC := '0';
SIGNAL in_1_ALU2, in_2_ALU2, outp_ALU2, in_1_ALU3, outp_ALU1: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clr_REG0, ena_REG0, clk_REG1, clr_REG1, clk_REG0: STD_LOGIC := '0';
SIGNAL in_2_ALU0, outp_ALU0, in_1_ALU1, in_2_ALU1, in_1_ALU0: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL sel_ALU1, sel_ALU2, sel_ALU3, sel_ALU0: STD_LOGIC_VECTOR( 0 TO 2 ) := (others => '0');
COMPONENT ALU IS
GENERIC(
data_width: INTEGER := 16);
PORT(
in_1: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
in_2: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
sel: IN STD_LOGIC_VECTOR( 0 TO 2 ) := (others => '0'));
END COMPONENT;
COMPONENT REG IS
GENERIC(
data_width: INTEGER := 16);
PORT(
inp: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
clk: IN STD_LOGIC := '0';
clr: IN STD_LOGIC := '0';
ena: IN STD_LOGIC := '0');
END COMPONENT;
begin
ALU0: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU0,
in_2 => in_2_ALU0,
outp => outp_ALU0,
sel => sel_ALU0
);
ALU1: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU1,
in_2 => in_2_ALU1,
outp => outp_ALU1,
sel => sel_ALU1
);
ALU2: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU2,
in_2 => in_2_ALU2,
outp => outp_ALU2,
sel => sel_ALU2
);
ALU3: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU3,
in_2 => in_2_ALU3,
outp => outp_ALU3,
sel => sel_ALU3
);
REG0: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG0,
outp => outp_REG0,
clk => clk_REG0,
clr => clr_REG0,
ena => ena_REG0
);
REG1: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG1,
outp => outp_REG1,
clk => clk_REG1,
clr => clr_REG1,
ena => ena_REG1
);
REG2: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG2,
outp => outp_REG2,
clk => clk_REG2,
clr => clr_REG2,
ena => ena_REG2
);
REG3: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG3,
outp => outp_REG3,
clk => clk_REG3,
clr => clr_REG3,
ena => ena_REG3
);
REG4: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG4,
outp => outp_REG4,
clk => clk_REG4,
clr => clr_REG4,
ena => ena_REG4
);
REG5: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG5,
outp => outp_REG5,
clk => clk_REG5,
clr => clr_REG5,
ena => ena_REG5
);
REG6: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG6,
outp => outp_REG6,
clk => clk_REG6,
clr => clr_REG6,
ena => ena_REG6
);
REG7: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG7,
outp => outp_REG7,
clk => clk_REG7,
clr => clr_REG7,
ena => ena_REG7
);
REG8: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG8,
outp => outp_REG8,
clk => clk_REG8,
clr => clr_REG8,
ena => ena_REG8
);
REG9: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG9,
outp => outp_REG9,
clk => clk_REG9,
clr => clr_REG9,
ena => ena_REG9
);
REG10: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG10,
outp => outp_REG10,
clk => clk_REG10,
clr => clr_REG10,
ena => ena_REG10
);
sel_ALU0 <= T ( 0 TO 2 );
sel_ALU1 <= T ( 3 TO 5 );
sel_ALU2 <= T ( 6 TO 8 );
sel_ALU3 <= T ( 9 TO 11 );
clk_REG0 <= clk;
clr_REG0 <= reset;
ena_REG0 <= T(12);
clk_REG1 <= clk;
clr_REG1 <= reset;
ena_REG1 <= T(13);
clk_REG2 <= clk;
clr_REG2 <= reset;
ena_REG2 <= T(14);
clk_REG3 <= clk;
clr_REG3 <= reset;
ena_REG3 <= T(15);
clk_REG4 <= clk;
clr_REG4 <= reset;
ena_REG4 <= T(16);
clk_REG5 <= clk;
clr_REG5 <= reset;
ena_REG5 <= T(17);
clk_REG6 <= clk;
clr_REG6 <= reset;
ena_REG6 <= T(18);
clk_REG7 <= clk;
clr_REG7 <= reset;
ena_REG7 <= T(19);
clk_REG8 <= clk;
clr_REG8 <= reset;
ena_REG8 <= T(20);
clk_REG9 <= clk;
clr_REG9 <= reset;
ena_REG9 <= T(21);
clk_REG10 <= clk;
clr_REG10 <= reset;
ena_REG10 <= T(22);
in_1_ALU0 <= outp_REG8
when (T ( 23 TO 24 ) = "00") else outp_REG9
when (T ( 23 TO 24 ) = "01") else outp_REG2
when (T ( 23 TO 24 ) = "10") else outp_REG6;
in_2_ALU0 <= outp_REG0
when (T ( 25 TO 26 ) = "00") else outp_REG6
when (T ( 25 TO 26 ) = "01") else outp_REG7;
in_1_ALU1 <= outp_REG1
when (T ( 27 TO 28 ) = "00") else outp_REG10
when (T ( 27 TO 28 ) = "01") else outp_REG7;
in_2_ALU1 <= outp_REG9
when (T ( 29 TO 30 ) = "00") else outp_REG3
when (T ( 29 TO 30 ) = "01") else outp_REG6;
in_1_ALU2 <= outp_REG2
when (T ( 31 TO 31 ) = "0") else outp_REG5;
in_2_ALU2 <= outp_REG0
when (T ( 32 TO 32 ) = "0") else outp_REG4;
in_1_ALU3 <= outp_REG1
when (T ( 33 TO 33 ) = "0") else outp_REG7;
in_2_ALU3 <= outp_REG3
when (T ( 34 TO 34 ) = "0") else outp_REG6;
inp_REG0 <= a;
inp_REG1 <= d;
inp_REG2 <= b;
inp_REG3 <= c;
inp_REG4 <= outp_ALU1
when (T ( 35 TO 35 ) = "0") else outp_ALU2;
inp_REG5 <= outp_ALU3;
inp_REG6 <= outp_ALU0;
inp_REG7 <= outp_ALU1;
inp_REG8 <= outp_ALU0;
inp_REG9 <= outp_ALU0
when (T ( 36 TO 36 ) = "0") else outp_ALU1;
inp_REG10 <= outp_ALU2;
output_0 <= outp_REG5;
output_1 <= outp_REG8;
output_2 <= outp_REG4;
END ARCHITECTURE;
|
gpl-3.0
|
c7f3d2c6c5ab3513fda6e1d0adc5968b
| 0.533178 | 2.475106 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/pll/pll128.vhd
| 1 | 15,206 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll128.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll128 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll128;
ARCHITECTURE SYN OF pll128 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
locked <= sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 12,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll128",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "120.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll128.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll128.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll128.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll128.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll128.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll128.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll128_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
mit
|
34a0f8c0a735269dc0321e9e46ce4a7c
| 0.699658 | 3.358957 | false | false | false | false |
sdenel/An-N-bits-pipelined-addsub-using-VHDL
|
src/addsub.vhd
| 1 | 3,086 |
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity addsub is
generic (
NBITS: natural := 8;
NPIPELINE : natural := 0; -- 0 pour aucun registre interne, 1 pour 1 registre interne, 2 pour 1+2=3 registres internes, ... N pour 2**N-1 registres internes.
ISRESET: std_logic := '0'
);
port (
clk, rst, sub : in std_logic;
A, B : in std_logic_vector(NBITS-1 downto 0);
Sr : out std_logic_vector(NBITS-1 downto 0) -- output registered
);
function cNREGSBEFORE(constant i : natural)
return natural is
variable pas : natural;
variable r : natural:=0;
variable index : natural :=0;
begin
if NPIPELINE=0 then
return r;
else
pas:=NBITS/(2*NPIPELINE);
for j in 0 to i loop
if index = pas then
r := r + 1;
index := 0;
end if;
index := index + 1;
end loop;
return r;
end if;
end function cNREGSBEFORE;
function cNREGSAFTER(constant i : natural)
return natural is
begin
return 2**NPIPELINE-1-cNREGSBEFORE(i);
end function cNREGSAFTER;
function cISCREG(constant i : natural)
return natural is
variable pas : natural;
variable r : natural:=0;
variable index : natural :=0;
begin
if NPIPELINE=0 then
return r;
else
pas:=NBITS/(2*NPIPELINE);
for j in 0 to i loop
if index = pas then
r := 1;
index := 0;
else
r := 0;
end if;
index := index + 1;
end loop;
return r;
end if;
end function cISCREG;
end entity addsub;
architecture rtl of addsub is
signal Ar, Br, S, C, Bc: std_logic_vector(NBITS-1 downto 0);
signal subr : std_logic;
component fullAdderWithRegisters
generic (
NREGSBEFORE: natural := 0;
NREGSAFTER : natural := 0;
ISCREG : natural := 0;
ISRESET : std_logic := '0'
);
port (
clk, rst : in std_logic;
a, b, c : in std_logic;
r, s : out std_logic
);
end component fullAdderWithRegisters;
begin
process (rst, clk)
begin
if ISRESET= '1' and rst = '1' then
Ar <= (others => '0'); -- A and B are registered before calculus
Br <= (others => '0');
Sr <= (others => '0');
subr <= '0';
elsif clk'event and clk = '1' then
Ar <= a;
Br <= b;
Sr <= S;
subr <= sub;
end if;
end process;
C(0) <= subr;
G1: for i in 0 to NBITS-1 generate
Bc(i) <= Br(i) xor subr;
G2: if i < NBITS-1 generate
inst: fullAdderWithRegisters
generic map(NREGSBEFORE=>cNREGSBEFORE(i), NREGSAFTER=>cNREGSAFTER(i), ISCREG=>cISCREG(i), ISRESET=>ISRESET)
port map(clk=>clk, rst=>rst, a=>Ar(i), b=>Bc(i), c=>C(i), r=>C(i+1), s=>S(i));
end generate G2;
G3: if i = NBITS-1 generate
inst: fullAdderWithRegisters
generic map(NREGSBEFORE=>cNREGSBEFORE(i), NREGSAFTER=>cNREGSAFTER(i), ISCREG=>cISCREG(i), ISRESET=>ISRESET)
port map(clk=>clk, rst=>rst, a=>Ar(i), b=>Bc(i), c=>C(i), r=>open , s=>S(i));
end generate G3;
end generate G1;
end rtl;
|
mit
|
69c59d9d1b7fb58bffe7d859652cbf16
| 0.581011 | 2.955939 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ProjectMain.vhd
| 1 | 11,520 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ProjectMain is
port ( CLKin : in std_logic;
LED_out : out std_logic_vector (7 downto 0);
----LED-MATRIX--------------
REFRESH_out : out std_logic;
STEP_out : out std_logic;
COLOR_out : out std_logic_vector(5 downto 0);
YCONTROL_out: out std_logic_vector(3 downto 0);
----UART--------------------
RXDin : in std_logic;
TXD_out : out std_logic;
----SRAM--------------------
SRAMDATA_io : inout std_logic_vector(14 downto 0);
SRAMADDR_out : out std_logic_vector(22 downto 0);
OE_out : out std_logic;
WE_out : out std_logic;
CE1_out : out std_logic;
CE2_out : out std_logic;
UB1_out : out std_logic;
LB1_out : out std_logic
);
end ProjectMain;
-------------------------------------------------------------------------------
architecture Behavioral of ProjectMain is
-------------------------------------------------------------------------------
signal YVAR : std_logic_Vector(4 downto 0);
signal XVAR : std_logic_Vector(5 downto 0);
signal COLOR : std_logic_Vector(14 downto 0);
signal COLOR2 : std_logic_Vector(9 downto 0);
signal COLOR3 : std_logic_Vector(14 downto 0):=(others => '0');
signal COLOR4 : std_logic_Vector(14 downto 0):=(others => '0');
signal MODE : std_logic_vector(1 downto 0):=(others => '0');
signal HEXVEC : std_logic_vector(295 downto 0):=(others => '0');
signal PIXDISP : std_logic_vector(511 downto 0):=(others => '0');
signal HEXSEL1 : integer:= 0;
signal HEXSEL2 : integer:= 0;
signal PIXRAM : std_logic_vector(15 downto 0);
signal PIXRAM2 : std_logic_vector(22 downto 0);
signal PIXRAMX : std_logic_vector(22 downto 0);
signal READRAM : std_logic:='0';
signal ASCII2 : std_logic_vector(6 downto 0);
signal ASCII1 : std_logic_vector(7 downto 0);
signal UPDAFOR : std_logic;
signal RAMCON : std_logic:= '0';
signal PIXSEL : std_logic_vector(4 downto 0);
signal UARTFOR : std_logic_vector(7 downto 0);
signal CLICK : std_logic:= '0';
signal COUNT : integer:= 0;
signal COUNT2 : integer:= 0;
signal COUNT3 : integer:= 0;
signal COUNT4 : integer:= 0;
signal XVAR2 : std_logic_vector(5 downto 0);
signal NUM : integer:= 0;
signal NUM3 : integer:= 3;
signal CLK2 : std_logic:='0';
signal CSEL : std_logic_Vector(14 downto 0):="111110000100001";
------UART SIGS-------------------------------------
signal DATAI : std_logic_vector(7 downto 0);
signal DATAO : std_logic_vector(7 downto 0);
signal READI : std_logic;
signal READO : std_logic;
----------------------------------------------------
--------------------------------------------------------------------
component VideoCon is
port ( CLKin : in std_logic;
REFRESH_out : out std_logic;
STEP_out : out std_logic;
COLORin : in std_logic_vector(14 downto 0);
COLOR_out : out std_logic_vector(5 downto 0);
YCON_out : out std_logic_vector(3 downto 0);
XSEL_out : out std_logic_vector(5 downto 0);
XSEL2_out : out std_logic_vector(5 downto 0);
YSEL_out : out std_logic_vector(4 downto 0));
end component;
--------------------------------------------------------------------
component UART is
port (
Clkin :in std_logic;
READin :in std_logic;
RXDin :in std_logic;
ASCIIin :in std_logic_vector (7 downto 0);
ASCII_out:out std_logic_vector (7 downto 0);
TXD_out :out std_logic;
READ_out: out std_logic);
end component;
--------------------------------------------------------------------
component SRAM_Controller is
port(
CLKin : in std_logic;
WRITEADDRin : in std_logic_vector(22 downto 0);
READADDRin : in std_logic_vector(22 downto 0);
DATAin : in std_logic_vector(14 downto 0);
READin : in std_logic;
WRITEin : in std_logic;
------------------------
SRAMDATA_io : inout std_logic_vector(14 downto 0);
------------------------
SRAMADDR_out : out std_logic_vector(22 downto 0);
DATA_out : out std_logic_vector(14 downto 0);
OE_out : out std_logic;
WE_out : out std_logic;
CE1_out : out std_logic;
CE2_out : out std_logic;
UB1_out : out std_logic;
LB1_out : out std_logic);
end component;
--------------------------------------------------------------------
component CHAR_ROM is
PORT (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : out STD_LOGIC_VECTOR(6 DOWNTO 0)
);
end component;
--------------------------------------------------------------------
component ASCII_LUT is
port( ASCIIin : in std_logic_vector(7 downto 0);
SEL_out : out std_logic_vector(6 downto 0));
end component;
--------------------------------------------------------------------
component DATA_CONSTRUCT is
port ( CLKin : in std_logic; --system clock
UPDATEin : in std_logic; --uart update signal
UARTin : in std_logic_vector(7 downto 0); --uart data in
COLOR_out : out std_logic_vector(14 downto 0); --color data
PIXSEL_out : out std_logic_vector(4 downto 0); --super pixel select
PIXRAM_out : out std_logic_vector(15 downto 0); --ram location select
UARTFOR_out : out std_logic_vector(7 downto 0); --uart data forward
MODE_out : out std_logic_vector(1 downto 0); --mode output
RAMCON_out : out std_logic; --controls write to sram
UPDAFOR_out : out std_logic; --uart update forward
UARTUPD_out : out std_logic; --uart send control
UARTDAT_out : out std_logic_vector(7 downto 0) --uart send data
);
end component;
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
VGA : VideoCon port map( CLKin => CLKin,
XSEL_out => XVAR,
YSEL_out => YVAR,
XSEL2_out => XVAR2,
YCON_out => YCONTROL_out,
COLOR_out => COLOR_out,
COLORin => COLOR,
REFRESH_out => REFRESH_out,
STEP_out => STEP_out);
UART_CON : UART port map( CLKin => CLKin,
READin => READI,
RXDin => RXDin,
ASCIIin(7 downto 0) => DATAI(7 downto 0),
ASCII_out(7 downto 0)=> DATAO(7 downto 0),
TXD_out => TXD_out,
READ_out => READO);
MAKE_DATA : DATA_CONSTRUCT port map( CLKin => CLKin,
UPDATEin => READO,
UARTin => DATAO,
COLOR_out => COLOR3,
PIXSEL_out => PIXSEL,
PIXRAM_out => PIXRAM,
MODE_out => MODE,
UARTFOR_out => UARTFOR,
RAMCON_out => RAMCON,
UPDAFOR_out => UPDAFOR,
UARTUPD_out => READI,
UARTDAT_out => DATAI);
IMAGERAM : SRAM_Controller port map( CLKin => CLKin,
WRITEADDRin => PIXRAMX(22 downto 0),
READADDRin => PIXRAM2(22 downto 0),
DATAin => COLOR3,
READin => READRAM,
WRITEin => NOT READRAM,
SRAMDATA_io => SRAMDATA_io,
SRAMADDR_out => SRAMADDR_out,
DATA_out => COLOR4,
OE_out => OE_out,
WE_out => WE_out,
CE1_out => CE1_out,
CE2_out => CE2_out,
UB1_out => UB1_out,
LB1_out => LB1_out);
CHARACTERS : CHAR_ROM port map( clka => CLKin,
addra => COLOR2,
douta => ASCII2);
CHARSELECT : ASCII_LUT port map( ASCIIin => ASCII1,
SEL_out => COLOR2(9 downto 3));
COLORTEMP : process (CLKin)
begin
if rising_edge(CLK2) then
if COUNT4 < 179 then
COUNT4 <= COUNT4 + 1;
else
COUNT4 <= 0;
end if;
if COUNT4 >= 0 and COUNT4 <= 29 then
CSEL(4 downto 0) <= CSEL(4 downto 0) + 1;
elsif COUNT4 >= 30 and COUNT4 <= 59 then
CSEL(14 downto 10) <= CSEL(14 downto 10) - 1;
elsif COUNT4 >= 60 and COUNT4 <= 89 then
CSEL(9 downto 5) <= CSEL(9 downto 5) + 1;
elsif COUNT4 >= 90 and COUNT4 <= 119 then
CSEL(4 downto 0) <= CSEL(4 downto 0) - 1;
elsif COUNT4 >= 120 and COUNT4 <= 149 then
CSEL(14 downto 10) <= CSEL(14 downto 10) + 1;
elsif COUNT4 >= 150 and COUNT4 <= 179 then
CSEL(9 downto 5) <= CSEL(9 downto 5) - 1;
end if;
end if;
if rising_edge(CLKin) then
if COUNT3 = 15000000 then
COUNT3 <= 0;
CLK2 <= '1';
else
COUNT3 <= COUNT3 + 1;
CLK2 <= '0';
end if;
if MODE = "00" or MODE = "10" then --DISPLAY
HEXVEC <= (others => '0');
PIXRAM2 <= conv_std_logic_vector(conv_integer(PIXDISP((conv_integer(YVAR(4 downto 3) & XVAR2(5 downto 3)))*16+15 downto (conv_integer(YVAR(4 downto 3) & XVAR2(5 downto 3)))*16))*64,23) + conv_integer(YVAR(2 downto 0) & "000") + conv_integer(XVAR2(2 downto 0));
if PIXDISP((conv_integer(YVAR(4 downto 3) & XVAR(5 downto 3)))*16+15 downto (conv_integer(YVAR(4 downto 3) & XVAR(5 downto 3)))*16) = 0 then
COLOR <= "000000000000000";
else
COLOR <= COLOR4;
end if;
READRAM <= '1';
if mode = "10" then
if rising_edge(UPDAFOR) then
PIXDISP(conv_integer(PIXSEL)*16+15 downto conv_integer(PIXSEL)*16) <= PIXRAM;
end if;
end if;
elsif MODE = "01" then
if rising_edge(RAMCON) then
PIXRAMX <= conv_std_logic_vector(conv_integer(PIXRAM) * 64,23) + COUNT2;
READRAM <= '0';
if COUNT2 < 63 then
COUNT2 <= COUNT2 + 1;
else
COUNT2 <= 0;
end if;
end if;
COLOR <= "000000000000000";
elsif MODE = "11" then
------DIRECT ASCII CONTROL LOGIC--------------------
if HEXSEL1+HEXSEL2 = NUM3 then
if CLICK = '1' then
ASCII1 <= x"FF";
else
ASCII1 <= HEXVEC(8*(HEXSEL1+HEXSEL2)+7 downto (8*(HEXSEL1+HEXSEL2)));
end if;
else
ASCII1 <= HEXVEC(8*(HEXSEL1+HEXSEL2)+7 downto (8*(HEXSEL1+HEXSEL2)));
end if;
if COUNT = 120000000 then
COUNT <= 0;
elsif COUNT < 60000000 then
COUNT <= COUNT + 1;
CLICK <= '1';
else
COUNT <= COUNT + 1;
CLICK <= '0';
end if;
if falling_edge(READO) then
HEXVEC((NUM*8)+7 downto (NUM*8)) <= DATAO;
if NUM < 36 then
NUM <= NUM + 1;
else
NUM <= 0;
end if;
if NUM3 < 36 then
NUM3 <= NUM3 + 1;
else
NUM3 <= 0;
end if;
end if;
COLOR2(2 downto 0) <= YVAR(2 downto 0);
if ASCII2(6 - (conv_integer(XVAR) mod 7)) = '1' then
COLOR <= CSEL;
else
COLOR <= "000000000000000";
end if;
-- ------------------------------------------------------
end if;
if (XVAR = 0 or XVAR = 63 or YVAR = 0 or YVAR = 31) and MODE /= 3 then
COLOR <= CSEL;
end if;
end if;
LED_out <= conv_std_logic_vector(conv_integer(MODE),8);
-----ASCII CONTROL AXIS MANIP-------------------------------
-- if XVAR < 7 then
-- HEXSEL1 <= 0;
-- elsif XVAR < 15 then
-- HEXSEL1 <= 1;
-- elsif XVAR < 22 then
-- HEXSEL1 <= 2;
-- elsif XVAR < 29 then
-- HEXSEL1 <= 3;
-- elsif XVAR < 36 then
-- HEXSEL1 <= 4;
-- elsif XVAR < 43 then
-- HEXSEL1 <= 5;
-- elsif XVAR < 50 then
-- HEXSEL1 <= 6;
-- elsif XVAR < 57 then
-- HEXSEL1 <= 7;
-- else
-- HEXSEL1 <= 8;
-- end if;
-- if YVAR < 8 then
-- HEXSEL2 <= 0;
-- elsif YVAR < 16 then
-- HEXSEL2 <= 9;
-- elsif YVAR < 24 then
-- HEXSEL2 <= 18;
-- else
-- HEXSEL2 <= 27;
-- end if;
------------------------------------------------------
end process COLORTEMP;
end Behavioral;
|
mit
|
e03abd0558353f570544d1615261b78f
| 0.529688 | 3.033974 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab8_new/lab8_new_lib/hdl/Reg_Behavior.vhd
| 1 | 776 |
--
-- VHDL Architecture lab8_new_lib.Reg.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 12:18:44 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Reg IS
GENERIC(size: positive := 16);
PORT( d: IN std_logic_vector (size-1 downto 0); -- input
q: OUT std_logic_vector (size-1 downto 0) := (others=>'0'); -- output
clock, e: IN std_logic); -- clock, enable
END ENTITY Reg;
ARCHITECTURE Behavior OF Reg IS
BEGIN
PROCESS(clock)
BEGIN
IF(rising_edge(clock) and e='1') THEN
q <= d;
END IF;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
878a43e61c88dcb492dd9153aab604b5
| 0.569588 | 3.448889 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
stack_32_bit.vhd
| 1 | 2,255 |
-- 32-bit stack with a max depth of 8
-- allows for push and pop operations
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity stack_32_bit is
port (
-- top of stack input
stack_top_write : in std_logic_vector(31 downto 0);
-- push enable, clock_enable, clock and reset
push : in std_logic;
clk_enable : in std_logic;
clk : in std_logic;
rst : in std_logic;
-- top of stack output
stack_top_read : out std_logic_vector(31 downto 0)
);
end entity stack_32_bit;
architecture stack_32_bit_arch of stack_32_bit is
-- 8 stack registers
signal top : std_logic_vector(31 downto 0);
signal next_0 : std_logic_vector(31 downto 0);
signal next_1 : std_logic_vector(31 downto 0);
signal next_2 : std_logic_vector(31 downto 0);
signal next_3 : std_logic_vector(31 downto 0);
signal next_4 : std_logic_vector(31 downto 0);
signal next_5 : std_logic_vector(31 downto 0);
signal next_6 : std_logic_vector(31 downto 0);
begin
-- stack process
stack : process(rst, clk_enable, clk, top)
begin
-- on async reset high, set all stack registers to 0
if rst = '1' then
top <= (others => '0');
next_0 <= (others => '0');
next_1 <= (others => '0');
next_2 <= (others => '0');
next_3 <= (others => '0');
next_4 <= (others => '0');
next_5 <= (others => '0');
next_6 <= (others => '0');
else
if clk_enable = '1' then
if rising_edge(clk) then
if push = '1' then
-- copying registers down
next_6 <= next_5;
next_5 <= next_4;
next_4 <= next_3;
next_3 <= next_2;
next_2 <= next_1;
next_1 <= next_0;
next_0 <= top;
-- pushing new value to stack top
top <= stack_top_write;
else
-- copying next_0 to stack top
top <= next_0;
-- copying registers up
next_0 <= next_1;
next_1 <= next_2;
next_2 <= next_3;
next_3 <= next_4;
next_4 <= next_5;
next_5 <= next_6;
-- clearing next_6
next_6 <= (others => '0');
end if;
end if;
end if;
end if;
stack_top_read <= top;
end process stack;
end architecture stack_32_bit_arch;
|
mit
|
ffa90401c5356f82ecf23bdc2618d764
| 0.577827 | 2.760098 | false | false | false | false |
ziyan/altera-de2-ann
|
src/pr/pr.vhd
| 1 | 5,144 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE pr_types IS
type integer_vector is array( NATURAL range <> ) of integer;
END PACKAGE pr_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.pr_types.all;
USE work.float_types.all;
USE work.ann_types.all;
PACKAGE pr_components IS
COMPONENT pr IS
GENERIC (
N_I : INTEGER := 16; -- pattern input size
N_O : INTEGER := 16; -- number of classes to recognize
N_T : INTEGER := 16 -- number of traning data
);
PORT (
reset, clock, go : IN STD_LOGIC;
training_data : IN STD_LOGIC_VECTOR(N_T * N_I - 1 downto 0);
training_class : IN INTEGER_VECTOR(N_T - 1 downto 0);
training_mse : IN FLOAT;
inputs : IN STD_LOGIC_VECTOR(N_I - 1 downto 0);
output : OUT INTEGER;
ready : OUT STD_LOGIC;
ann_mode : INOUT ann_mode;
ann_alpha : OUT float;
ann_inputs : OUT float_vector(N_I - 1 downto 0);
ann_targets : OUT float_vector(N_O - 1 downto 0);
ann_outputs : IN float_vector(N_O - 1 downto 0);
ann_mse : IN float;
ann_ready : IN STD_LOGIC;
lfsr_output : IN STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT pr;
END PACKAGE pr_components;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE work.pr_types.all;
USE work.float_types.all;
USE work.float_constants.all;
USE work.float_components.all;
USE work.ann_types.all;
ENTITY pr IS
GENERIC (
N_I : INTEGER := 16; -- pattern input size
N_O : INTEGER := 16; -- number of classes to recognize
N_T : INTEGER := 16 -- number of traning data
);
PORT (
reset, clock, go : IN STD_LOGIC;
training_data : IN STD_LOGIC_VECTOR(N_T * N_I - 1 downto 0);
training_class : IN INTEGER_VECTOR(N_T - 1 downto 0);
training_mse : IN FLOAT;
inputs : IN STD_LOGIC_VECTOR(N_I - 1 downto 0);
output : OUT INTEGER;
ready : OUT STD_LOGIC;
ann_mode : INOUT ann_mode;
ann_alpha : OUT float;
ann_inputs : OUT float_vector(N_I - 1 downto 0);
ann_targets : OUT float_vector(N_O - 1 downto 0);
ann_outputs : IN float_vector(N_O - 1 downto 0);
ann_mse : IN float;
ann_ready : IN STD_LOGIC;
lfsr_output : IN STD_LOGIC_VECTOR(15 downto 0)
);
END ENTITY pr;
ARCHITECTURE pr OF pr IS
constant alpha : float := float_half;
subtype classes is integer range 0 to N_O - 1;
signal class, k : classes := 0;
type states is (init, train, train_validate, train_validate_wait, train_validate_complete, run, run_complete, run_validate, run_validate_wait, run_validate_complete, idle);
signal state : states := init;
signal fp_cmp_enable, fp_cmp_agb : std_logic := '0';
signal fp_cmp_a, fp_cmp_b : float := float_zero;
signal train_success_count, j : integer := 0;
BEGIN
ann_alpha <= alpha;
output <= class;
fp_cmp0 : fp_cmp port map (reset, fp_cmp_enable, clock, fp_cmp_a, fp_cmp_b, fp_cmp_agb);
fsm : PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
ELSIF (clock = '1' AND clock'event) THEN
IF (ann_mode /= idle) THEN
ann_mode <= idle;
ELSIF (ann_ready = '0') THEN
ELSE
CASE state IS
WHEN init =>
ready <= '0';
state <= train;
train_success_count <= 0;
j <= 0;
WHEN train =>
FOR I IN N_I - 1 downto 0 LOOP
IF training_data(j * N_I + I) = '1' THEN
ann_inputs(I) <= float_one;
ELSE
ann_inputs(I) <= float_zero;
END IF;
END LOOP;
ann_targets <= (others => float_zero);
ann_targets(training_class(j)) <= float_one;
ann_mode <= learn;
state <= train_validate;
WHEN train_validate =>
fp_cmp_a <= training_mse;
fp_cmp_b <= ann_mse;
fp_cmp_enable <= '1';
state <= train_validate_wait;
WHEN train_validate_wait =>
state <= train_validate_complete;
WHEN train_validate_complete =>
IF (j = N_T - 1) THEN
j <= 0;
ELSE
j <= j + 1;
END IF;
fp_cmp_enable <= '0';
IF (fp_cmp_agb = '0') THEN
state <= train;
train_success_count <= 0;
ELSE
train_success_count <= train_success_count + 1;
IF (train_success_count /= N_T) THEN
state <= train;
ELSE
ready <= '1';
state <= run;
END IF;
END IF;
WHEN run =>
FOR I IN N_I - 1 downto 0 LOOP
IF inputs(I) = '1' THEN
ann_inputs(I) <= float_one;
ELSE
ann_inputs(I) <= float_zero;
END IF;
END LOOP;
ann_mode <= run;
state <= run_complete;
WHEN run_complete =>
class <= 0;
k <= 0;
fp_cmp_enable <= '1';
state <= run_validate;
WHEN run_validate =>
fp_cmp_a <= ann_outputs(k);
fp_cmp_b <= ann_outputs(class);
state <= run_validate_wait;
WHEN run_validate_wait =>
state <= run_validate_complete;
WHEN run_validate_complete =>
IF (fp_cmp_agb = '1') THEN
class <= k;
END IF;
IF (k = N_O - 1) THEN
fp_cmp_enable <= '0';
state <= idle;
ELSE
k <= k + 1;
state <= run_validate;
END IF;
WHEN idle =>
IF (go = '1') THEN
state <= run;
ELSE
state <= idle;
END IF;
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE pr;
|
mit
|
62dc0a5adff88334f56a8e893b4bdcd1
| 0.608087 | 2.824822 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp_div.vhd
| 1 | 102,734 |
-- megafunction wizard: %ALTFP_DIV%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_div
-- ============================================================
-- File Name: fp_div.vhd
-- Megafunction Name(s):
-- altfp_div
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_div CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" OPTIMIZE="SPEED" PIPELINE=6 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_div 2010:03:24:20:34:20:SJ cbx_altsyncram 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_abs 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_lpm_decode 2010:03:24:20:34:20:SJ cbx_lpm_divide 2010:03:24:20:34:20:SJ cbx_lpm_mult 2010:03:24:20:34:20:SJ cbx_lpm_mux 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_padd 2010:03:24:20:34:20:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ cbx_stratixiii 2010:03:24:20:34:20:SJ cbx_util_mgl 2010:03:24:20:34:20:SJ VERSION_END
--altfp_div_pst CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" FILE_NAME="fp_div.vhd:a" PIPELINE=6 WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_div 2010:03:24:20:34:20:SJ cbx_altsyncram 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_abs 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_lpm_decode 2010:03:24:20:34:20:SJ cbx_lpm_divide 2010:03:24:20:34:20:SJ cbx_lpm_mult 2010:03:24:20:34:20:SJ cbx_lpm_mux 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_padd 2010:03:24:20:34:20:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ cbx_stratixiii 2010:03:24:20:34:20:SJ cbx_util_mgl 2010:03:24:20:34:20:SJ VERSION_END
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = altsyncram 1 lpm_add_sub 4 lpm_compare 1 lpm_mult 5 mux21 74 reg 339
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_div_altfp_div_pst_foe IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_altfp_div_pst_foe;
ARCHITECTURE RTL OF fp_div_altfp_div_pst_foe IS
SIGNAL wire_altsyncram3_q_a : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL a_is_infinity_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_is_infinity_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_a_is_infinity_dffe_1_w_lg_q318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL a_is_infinity_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_is_infinity_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_is_infinity_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_zero_b_not_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_zero_b_not_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_a_zero_b_not_dffe_1_w_lg_q326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL a_zero_b_not_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_zero_b_not_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL a_zero_b_not_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL b1_dffe_0 : STD_LOGIC_VECTOR(33 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL b_is_infinity_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL b_is_infinity_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_b_is_infinity_dffe_1_w_lg_q325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL b_is_infinity_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL b_is_infinity_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL b_is_infinity_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_exp_zeros_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL divbyzero_pipe_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL divbyzero_pipe_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_divbyzero_pipe_dffe_1_w_lg_q317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL divbyzero_pipe_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL divbyzero_pipe_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL divbyzero_pipe_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL e1_dffe_0 : STD_LOGIC_VECTOR(16 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL e1_dffe_1 : STD_LOGIC_VECTOR(16 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_dffe_0 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_dffe_1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_dffe_2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_dffe_3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL frac_a_smaller_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_a_dffe1_dffe1 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_b_dffe1_dffe1 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_result_dffe : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL nan_pipe_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nan_pipe_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_nan_pipe_dffe_1_w_lg_q308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nan_pipe_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nan_pipe_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL nan_pipe_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL over_under_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL over_under_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL over_under_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL quotient_j_dffe : STD_LOGIC_VECTOR(16 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL quotient_k_dffe_0 : STD_LOGIC_VECTOR(16 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL remainder_j_dffe_0 : STD_LOGIC_VECTOR(49 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL remainder_j_dffe_1 : STD_LOGIC_VECTOR(49 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_pipe_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_pipe_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_pipe_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_pipe_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_pipe_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_pipe_dffe_5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_bias_addition_overflow : STD_LOGIC;
SIGNAL wire_bias_addition_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_sub_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_quotient_process_dataa : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_quotient_process_datab : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_quotient_process_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_quotient_process_w_result_range425w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_remainder_sub_0_dataa : STD_LOGIC_VECTOR (49 DOWNTO 0);
SIGNAL wire_remainder_sub_0_result : STD_LOGIC_VECTOR (49 DOWNTO 0);
SIGNAL wire_cmpr2_alb : STD_LOGIC;
SIGNAL wire_a1_prod_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_a1_prod_result : STD_LOGIC_VECTOR (34 DOWNTO 0);
SIGNAL wire_b1_prod_w_lg_w_result_range358w359w : STD_LOGIC_VECTOR (16 DOWNTO 0);
SIGNAL wire_b1_prod_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_b1_prod_result : STD_LOGIC_VECTOR (33 DOWNTO 0);
SIGNAL wire_b1_prod_w_result_range358w : STD_LOGIC_VECTOR (16 DOWNTO 0);
SIGNAL wire_q_partial_0_result : STD_LOGIC_VECTOR (33 DOWNTO 0);
SIGNAL wire_q_partial_0_w_result_range373w : STD_LOGIC_VECTOR (16 DOWNTO 0);
SIGNAL wire_q_partial_1_w_lg_w_result_range407w408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_w_lg_w_result_range410w411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_w_lg_w_result_range413w414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_w_lg_w_result_range416w417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_result : STD_LOGIC_VECTOR (33 DOWNTO 0);
SIGNAL wire_q_partial_1_w_result_range407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_w_result_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_w_result_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_q_partial_1_w_result_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_remainder_mult_0_result : STD_LOGIC_VECTOR (50 DOWNTO 0);
SIGNAL wire_exp_result_muxa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_man_a_adjusteda_dataout : STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL wire_man_result_muxa_dataout : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL wire_select_bias_2a_dataout : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL wire_select_biasa_dataout : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_lg_w_lg_bias_addition_overf_w304w305w306w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w302w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range262w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range265w287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range268w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range271w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range274w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range277w295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range280w297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range11w17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range21w27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range31w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range41w47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range51w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range61w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range71w77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range14w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range24w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range34w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range44w49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range54w59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range64w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range74w79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_exp_a_all_one_w_range78w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_exp_add_output_all_one_range298w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_exp_b_all_one_w_range80w224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_exp_b_not_zero_w_range76w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_a_is_infinity_w233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_a_is_nan_w234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_exp_sign_w303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_exp_a_not_zero_w_range73w227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_man_a_not_zero_w_range215w221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_man_b_not_zero_w_range218w223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_lg_w_lg_bias_addition_overf_w299w300w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w299w300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_bias_addition_overf_w323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_bias_addition_overf_w299w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range262w263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range268w269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range271w272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range274w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range277w278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_bias_addition_w_range280w281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range11w12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range31w32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range41w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range71w72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range24w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range34w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range44w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range64w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range74w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL a_is_infinity_w : STD_LOGIC;
SIGNAL a_is_nan_w : STD_LOGIC;
SIGNAL a_zero_b_not : STD_LOGIC;
SIGNAL b1_dffe_w : STD_LOGIC_VECTOR (33 DOWNTO 0);
SIGNAL b_is_infinity_w : STD_LOGIC;
SIGNAL b_is_nan_w : STD_LOGIC;
SIGNAL bias_addition_overf_w : STD_LOGIC;
SIGNAL bias_addition_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL both_exp_zeros : STD_LOGIC;
SIGNAL e0_dffe1_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL e0_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL e1_w : STD_LOGIC_VECTOR (50 DOWNTO 0);
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_add_output_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_add_output_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_mux_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_mux_sel_w : STD_LOGIC;
SIGNAL exp_result_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_sign_w : STD_LOGIC;
SIGNAL exp_sub_a_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_sub_b_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL frac_a_smaller_dffe1_wi : STD_LOGIC;
SIGNAL frac_a_smaller_dffe1_wo : STD_LOGIC;
SIGNAL frac_a_smaller_w : STD_LOGIC;
SIGNAL guard_bit : STD_LOGIC;
SIGNAL man_a_adjusted_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_a_dffe1_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_a_dffe1_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_adjusted_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_b_dffe1_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_dffe1_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_result_dffe_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_result_dffe_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_result_mux_select : STD_LOGIC;
SIGNAL man_result_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL overflow_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL overflow_underflow : STD_LOGIC;
SIGNAL overflow_w : STD_LOGIC;
SIGNAL quotient_accumulate_w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL quotient_process_cin_w : STD_LOGIC;
SIGNAL remainder_j_w : STD_LOGIC_VECTOR (99 DOWNTO 0);
SIGNAL round_bit : STD_LOGIC;
SIGNAL select_bias_out_2_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL select_bias_out_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL sticky_bits : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL underflow_w : STD_LOGIC;
SIGNAL underflow_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL value_add_one_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL value_normal_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL value_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_bias_addition_w_range280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_e1_w_range360w : STD_LOGIC_VECTOR (16 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_e1_w_range368w : STD_LOGIC_VECTOR (16 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_all_one_w_range78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_a_not_zero_w_range73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_all_one_range298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_add_output_not_zero_range279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_all_one_w_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_exp_b_not_zero_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_remainder_j_w_range363w : STD_LOGIC_VECTOR (49 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_sticky_bits_range405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_sticky_bits_range409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_sticky_bits_range412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_sticky_bits_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_div_pst1_w_w_quotient_accumulate_w_range385w_range386w : STD_LOGIC_VECTOR (16 DOWNTO 0);
COMPONENT altsyncram
GENERIC
(
ADDRESS_ACLR_A : STRING := "UNUSED";
ADDRESS_ACLR_B : STRING := "NONE";
ADDRESS_REG_B : STRING := "CLOCK1";
BYTE_SIZE : NATURAL := 8;
BYTEENA_ACLR_A : STRING := "UNUSED";
BYTEENA_ACLR_B : STRING := "NONE";
BYTEENA_REG_B : STRING := "CLOCK1";
CLOCK_ENABLE_CORE_A : STRING := "USE_INPUT_CLKEN";
CLOCK_ENABLE_CORE_B : STRING := "USE_INPUT_CLKEN";
CLOCK_ENABLE_INPUT_A : STRING := "NORMAL";
CLOCK_ENABLE_INPUT_B : STRING := "NORMAL";
CLOCK_ENABLE_OUTPUT_A : STRING := "NORMAL";
CLOCK_ENABLE_OUTPUT_B : STRING := "NORMAL";
ENABLE_ECC : STRING := "FALSE";
IMPLEMENT_IN_LES : STRING := "OFF";
INDATA_ACLR_A : STRING := "UNUSED";
INDATA_ACLR_B : STRING := "NONE";
INDATA_REG_B : STRING := "CLOCK1";
INIT_FILE : STRING := "UNUSED";
INIT_FILE_LAYOUT : STRING := "PORT_A";
MAXIMUM_DEPTH : NATURAL := 0;
NUMWORDS_A : NATURAL := 0;
NUMWORDS_B : NATURAL := 0;
OPERATION_MODE : STRING := "BIDIR_DUAL_PORT";
OUTDATA_ACLR_A : STRING := "NONE";
OUTDATA_ACLR_B : STRING := "NONE";
OUTDATA_REG_A : STRING := "UNREGISTERED";
OUTDATA_REG_B : STRING := "UNREGISTERED";
POWER_UP_UNINITIALIZED : STRING := "FALSE";
RAM_BLOCK_TYPE : STRING := "AUTO";
RDCONTROL_ACLR_B : STRING := "NONE";
RDCONTROL_REG_B : STRING := "CLOCK1";
READ_DURING_WRITE_MODE_MIXED_PORTS : STRING := "DONT_CARE";
read_during_write_mode_port_a : STRING := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : STRING := "NEW_DATA_NO_NBE_READ";
WIDTH_A : NATURAL;
WIDTH_B : NATURAL := 1;
WIDTH_BYTEENA_A : NATURAL := 1;
WIDTH_BYTEENA_B : NATURAL := 1;
WIDTHAD_A : NATURAL;
WIDTHAD_B : NATURAL := 1;
WRCONTROL_ACLR_A : STRING := "UNUSED";
WRCONTROL_ACLR_B : STRING := "NONE";
WRCONTROL_WRADDRESS_REG_B : STRING := "CLOCK1";
INTENDED_DEVICE_FAMILY : STRING := "Cyclone II";
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "altsyncram"
);
PORT
(
aclr0 : IN STD_LOGIC := '0';
aclr1 : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR(WIDTHAD_A-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR(WIDTHAD_B-1 DOWNTO 0) := (OTHERS => '1');
addressstall_a : IN STD_LOGIC := '0';
addressstall_b : IN STD_LOGIC := '0';
byteena_a : IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_A-1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_B-1 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
clock1 : IN STD_LOGIC := '1';
clocken0 : IN STD_LOGIC := '1';
clocken1 : IN STD_LOGIC := '1';
clocken2 : IN STD_LOGIC := '1';
clocken3 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0) := (OTHERS => '1');
data_b : IN STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0) := (OTHERS => '1');
eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO 7 GENERATE
wire_altfp_div_pst1_w_lg_w_lg_w_lg_bias_addition_overf_w304w305w306w(i) <= wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w305w(0) AND bias_addition_w(i);
END GENERATE loop0;
wire_altfp_div_pst1_w322w(0) <= wire_altfp_div_pst1_w_lg_w_exp_add_output_all_one_range298w321w(0) AND wire_altfp_div_pst1_w_lg_exp_sign_w303w(0);
wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w305w(0) <= wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w(0) AND wire_altfp_div_pst1_w_lg_exp_sign_w303w(0);
wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w312w(0) <= wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w(0) AND exp_sign_w;
loop1 : FOR i IN 0 TO 7 GENERATE
wire_altfp_div_pst1_w302w(i) <= wire_altfp_div_pst1_w_lg_w_lg_w_lg_bias_addition_overf_w299w300w301w(0) AND overflow_ones_w(i);
END GENERATE loop1;
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range262w285w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range262w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range283w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range265w287w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range265w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range286w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range268w289w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range268w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range288w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range271w291w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range271w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range290w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range274w293w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range274w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range292w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range277w295w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range277w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range294w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range280w297w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range280w(0) AND wire_altfp_div_pst1_w_exp_add_output_all_one_range296w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range11w17w(0) <= wire_altfp_div_pst1_w_dataa_range11w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range7w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range21w27w(0) <= wire_altfp_div_pst1_w_dataa_range21w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range18w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range31w37w(0) <= wire_altfp_div_pst1_w_dataa_range31w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range28w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range41w47w(0) <= wire_altfp_div_pst1_w_dataa_range41w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range38w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range51w57w(0) <= wire_altfp_div_pst1_w_dataa_range51w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range48w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range61w67w(0) <= wire_altfp_div_pst1_w_dataa_range61w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range58w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range71w77w(0) <= wire_altfp_div_pst1_w_dataa_range71w(0) AND wire_altfp_div_pst1_w_exp_a_all_one_w_range68w(0);
wire_altfp_div_pst1_w_lg_w_datab_range14w19w(0) <= wire_altfp_div_pst1_w_datab_range14w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range9w(0);
wire_altfp_div_pst1_w_lg_w_datab_range24w29w(0) <= wire_altfp_div_pst1_w_datab_range24w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range20w(0);
wire_altfp_div_pst1_w_lg_w_datab_range34w39w(0) <= wire_altfp_div_pst1_w_datab_range34w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range30w(0);
wire_altfp_div_pst1_w_lg_w_datab_range44w49w(0) <= wire_altfp_div_pst1_w_datab_range44w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range40w(0);
wire_altfp_div_pst1_w_lg_w_datab_range54w59w(0) <= wire_altfp_div_pst1_w_datab_range54w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range50w(0);
wire_altfp_div_pst1_w_lg_w_datab_range64w69w(0) <= wire_altfp_div_pst1_w_datab_range64w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range60w(0);
wire_altfp_div_pst1_w_lg_w_datab_range74w79w(0) <= wire_altfp_div_pst1_w_datab_range74w(0) AND wire_altfp_div_pst1_w_exp_b_all_one_w_range70w(0);
wire_altfp_div_pst1_w_lg_w_exp_a_all_one_w_range78w222w(0) <= wire_altfp_div_pst1_w_exp_a_all_one_w_range78w(0) AND wire_altfp_div_pst1_w_lg_w_man_a_not_zero_w_range215w221w(0);
wire_altfp_div_pst1_w_lg_w_exp_add_output_all_one_range298w321w(0) <= wire_altfp_div_pst1_w_exp_add_output_all_one_range298w(0) AND wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w(0);
wire_altfp_div_pst1_w_lg_w_exp_b_all_one_w_range80w224w(0) <= wire_altfp_div_pst1_w_exp_b_all_one_w_range80w(0) AND wire_altfp_div_pst1_w_lg_w_man_b_not_zero_w_range218w223w(0);
wire_altfp_div_pst1_w_lg_w_exp_b_not_zero_w_range76w256w(0) <= wire_altfp_div_pst1_w_exp_b_not_zero_w_range76w(0) AND wire_altfp_div_pst1_w_lg_w_exp_a_not_zero_w_range73w227w(0);
wire_altfp_div_pst1_w_lg_a_is_infinity_w233w(0) <= NOT a_is_infinity_w;
wire_altfp_div_pst1_w_lg_a_is_nan_w234w(0) <= NOT a_is_nan_w;
wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w(0) <= NOT bias_addition_overf_w;
wire_altfp_div_pst1_w_lg_exp_sign_w303w(0) <= NOT exp_sign_w;
wire_altfp_div_pst1_w_lg_w_exp_a_not_zero_w_range73w227w(0) <= NOT wire_altfp_div_pst1_w_exp_a_not_zero_w_range73w(0);
wire_altfp_div_pst1_w_lg_w_man_a_not_zero_w_range215w221w(0) <= NOT wire_altfp_div_pst1_w_man_a_not_zero_w_range215w(0);
wire_altfp_div_pst1_w_lg_w_man_b_not_zero_w_range218w223w(0) <= NOT wire_altfp_div_pst1_w_man_b_not_zero_w_range218w(0);
wire_altfp_div_pst1_w_lg_w_lg_w_lg_bias_addition_overf_w299w300w301w(0) <= wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w299w300w(0) OR a_is_infinity_dffe_1;
wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w299w300w(0) <= wire_altfp_div_pst1_w_lg_bias_addition_overf_w299w(0) OR nan_pipe_dffe_1;
wire_altfp_div_pst1_w_lg_bias_addition_overf_w323w(0) <= bias_addition_overf_w OR wire_altfp_div_pst1_w322w(0);
wire_altfp_div_pst1_w_lg_bias_addition_overf_w299w(0) <= bias_addition_overf_w OR divbyzero_pipe_dffe_1;
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range262w263w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range262w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range260w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range265w266w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range265w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range264w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range268w269w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range268w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range267w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range271w272w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range271w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range270w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range274w275w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range274w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range273w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range277w278w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range277w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range276w(0);
wire_altfp_div_pst1_w_lg_w_bias_addition_w_range280w281w(0) <= wire_altfp_div_pst1_w_bias_addition_w_range280w(0) OR wire_altfp_div_pst1_w_exp_add_output_not_zero_range279w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range141w142w(0) <= wire_altfp_div_pst1_w_dataa_range141w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range137w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range147w148w(0) <= wire_altfp_div_pst1_w_dataa_range147w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range143w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range153w154w(0) <= wire_altfp_div_pst1_w_dataa_range153w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range149w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range159w160w(0) <= wire_altfp_div_pst1_w_dataa_range159w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range155w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range165w166w(0) <= wire_altfp_div_pst1_w_dataa_range165w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range161w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range171w172w(0) <= wire_altfp_div_pst1_w_dataa_range171w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range167w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range177w178w(0) <= wire_altfp_div_pst1_w_dataa_range177w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range173w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range183w184w(0) <= wire_altfp_div_pst1_w_dataa_range183w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range179w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range189w190w(0) <= wire_altfp_div_pst1_w_dataa_range189w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range185w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range195w196w(0) <= wire_altfp_div_pst1_w_dataa_range195w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range191w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range87w88w(0) <= wire_altfp_div_pst1_w_dataa_range87w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range82w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range201w202w(0) <= wire_altfp_div_pst1_w_dataa_range201w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range197w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range207w208w(0) <= wire_altfp_div_pst1_w_dataa_range207w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range203w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range213w214w(0) <= wire_altfp_div_pst1_w_dataa_range213w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range209w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range11w12w(0) <= wire_altfp_div_pst1_w_dataa_range11w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range2w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range21w22w(0) <= wire_altfp_div_pst1_w_dataa_range21w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range13w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range31w32w(0) <= wire_altfp_div_pst1_w_dataa_range31w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range23w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range41w42w(0) <= wire_altfp_div_pst1_w_dataa_range41w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range33w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range51w52w(0) <= wire_altfp_div_pst1_w_dataa_range51w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range43w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range61w62w(0) <= wire_altfp_div_pst1_w_dataa_range61w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range53w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range93w94w(0) <= wire_altfp_div_pst1_w_dataa_range93w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range89w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range71w72w(0) <= wire_altfp_div_pst1_w_dataa_range71w(0) OR wire_altfp_div_pst1_w_exp_a_not_zero_w_range63w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range99w100w(0) <= wire_altfp_div_pst1_w_dataa_range99w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range95w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range105w106w(0) <= wire_altfp_div_pst1_w_dataa_range105w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range101w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range111w112w(0) <= wire_altfp_div_pst1_w_dataa_range111w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range107w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range117w118w(0) <= wire_altfp_div_pst1_w_dataa_range117w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range113w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range123w124w(0) <= wire_altfp_div_pst1_w_dataa_range123w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range119w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range129w130w(0) <= wire_altfp_div_pst1_w_dataa_range129w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range125w(0);
wire_altfp_div_pst1_w_lg_w_dataa_range135w136w(0) <= wire_altfp_div_pst1_w_dataa_range135w(0) OR wire_altfp_div_pst1_w_man_a_not_zero_w_range131w(0);
wire_altfp_div_pst1_w_lg_w_datab_range144w145w(0) <= wire_altfp_div_pst1_w_datab_range144w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range140w(0);
wire_altfp_div_pst1_w_lg_w_datab_range150w151w(0) <= wire_altfp_div_pst1_w_datab_range150w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range146w(0);
wire_altfp_div_pst1_w_lg_w_datab_range156w157w(0) <= wire_altfp_div_pst1_w_datab_range156w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range152w(0);
wire_altfp_div_pst1_w_lg_w_datab_range162w163w(0) <= wire_altfp_div_pst1_w_datab_range162w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range158w(0);
wire_altfp_div_pst1_w_lg_w_datab_range168w169w(0) <= wire_altfp_div_pst1_w_datab_range168w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range164w(0);
wire_altfp_div_pst1_w_lg_w_datab_range174w175w(0) <= wire_altfp_div_pst1_w_datab_range174w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range170w(0);
wire_altfp_div_pst1_w_lg_w_datab_range180w181w(0) <= wire_altfp_div_pst1_w_datab_range180w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range176w(0);
wire_altfp_div_pst1_w_lg_w_datab_range186w187w(0) <= wire_altfp_div_pst1_w_datab_range186w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range182w(0);
wire_altfp_div_pst1_w_lg_w_datab_range192w193w(0) <= wire_altfp_div_pst1_w_datab_range192w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range188w(0);
wire_altfp_div_pst1_w_lg_w_datab_range198w199w(0) <= wire_altfp_div_pst1_w_datab_range198w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range194w(0);
wire_altfp_div_pst1_w_lg_w_datab_range90w91w(0) <= wire_altfp_div_pst1_w_datab_range90w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range85w(0);
wire_altfp_div_pst1_w_lg_w_datab_range204w205w(0) <= wire_altfp_div_pst1_w_datab_range204w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range200w(0);
wire_altfp_div_pst1_w_lg_w_datab_range210w211w(0) <= wire_altfp_div_pst1_w_datab_range210w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range206w(0);
wire_altfp_div_pst1_w_lg_w_datab_range216w217w(0) <= wire_altfp_div_pst1_w_datab_range216w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range212w(0);
wire_altfp_div_pst1_w_lg_w_datab_range14w15w(0) <= wire_altfp_div_pst1_w_datab_range14w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range5w(0);
wire_altfp_div_pst1_w_lg_w_datab_range24w25w(0) <= wire_altfp_div_pst1_w_datab_range24w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range16w(0);
wire_altfp_div_pst1_w_lg_w_datab_range34w35w(0) <= wire_altfp_div_pst1_w_datab_range34w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range26w(0);
wire_altfp_div_pst1_w_lg_w_datab_range44w45w(0) <= wire_altfp_div_pst1_w_datab_range44w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range36w(0);
wire_altfp_div_pst1_w_lg_w_datab_range54w55w(0) <= wire_altfp_div_pst1_w_datab_range54w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range46w(0);
wire_altfp_div_pst1_w_lg_w_datab_range64w65w(0) <= wire_altfp_div_pst1_w_datab_range64w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range56w(0);
wire_altfp_div_pst1_w_lg_w_datab_range96w97w(0) <= wire_altfp_div_pst1_w_datab_range96w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range92w(0);
wire_altfp_div_pst1_w_lg_w_datab_range74w75w(0) <= wire_altfp_div_pst1_w_datab_range74w(0) OR wire_altfp_div_pst1_w_exp_b_not_zero_w_range66w(0);
wire_altfp_div_pst1_w_lg_w_datab_range102w103w(0) <= wire_altfp_div_pst1_w_datab_range102w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range98w(0);
wire_altfp_div_pst1_w_lg_w_datab_range108w109w(0) <= wire_altfp_div_pst1_w_datab_range108w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range104w(0);
wire_altfp_div_pst1_w_lg_w_datab_range114w115w(0) <= wire_altfp_div_pst1_w_datab_range114w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range110w(0);
wire_altfp_div_pst1_w_lg_w_datab_range120w121w(0) <= wire_altfp_div_pst1_w_datab_range120w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range116w(0);
wire_altfp_div_pst1_w_lg_w_datab_range126w127w(0) <= wire_altfp_div_pst1_w_datab_range126w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range122w(0);
wire_altfp_div_pst1_w_lg_w_datab_range132w133w(0) <= wire_altfp_div_pst1_w_datab_range132w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range128w(0);
wire_altfp_div_pst1_w_lg_w_datab_range138w139w(0) <= wire_altfp_div_pst1_w_datab_range138w(0) OR wire_altfp_div_pst1_w_man_b_not_zero_w_range134w(0);
a_is_infinity_w <= wire_altfp_div_pst1_w_lg_w_exp_a_all_one_w_range78w222w(0);
a_is_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
a_zero_b_not <= wire_altfp_div_pst1_w_lg_w_exp_b_not_zero_w_range76w256w(0);
b1_dffe_w <= ( b1_dffe_0);
b_is_infinity_w <= wire_altfp_div_pst1_w_lg_w_exp_b_all_one_w_range80w224w(0);
b_is_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
bias_addition_overf_w <= wire_bias_addition_overflow;
bias_addition_w <= wire_bias_addition_result(7 DOWNTO 0);
both_exp_zeros <= both_exp_zeros_dffe;
e0_dffe1_wo <= e0_w;
e0_w <= wire_altsyncram3_q_a;
e1_w <= ( e1_dffe_1 & e1_dffe_0 & wire_b1_prod_w_lg_w_result_range358w359w);
exp_a_all_one_w <= ( wire_altfp_div_pst1_w_lg_w_dataa_range71w77w & wire_altfp_div_pst1_w_lg_w_dataa_range61w67w & wire_altfp_div_pst1_w_lg_w_dataa_range51w57w & wire_altfp_div_pst1_w_lg_w_dataa_range41w47w & wire_altfp_div_pst1_w_lg_w_dataa_range31w37w & wire_altfp_div_pst1_w_lg_w_dataa_range21w27w & wire_altfp_div_pst1_w_lg_w_dataa_range11w17w & dataa(23));
exp_a_not_zero_w <= ( wire_altfp_div_pst1_w_lg_w_dataa_range71w72w & wire_altfp_div_pst1_w_lg_w_dataa_range61w62w & wire_altfp_div_pst1_w_lg_w_dataa_range51w52w & wire_altfp_div_pst1_w_lg_w_dataa_range41w42w & wire_altfp_div_pst1_w_lg_w_dataa_range31w32w & wire_altfp_div_pst1_w_lg_w_dataa_range21w22w & wire_altfp_div_pst1_w_lg_w_dataa_range11w12w & dataa(23));
exp_add_output_all_one <= ( wire_altfp_div_pst1_w_lg_w_bias_addition_w_range280w297w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range277w295w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range274w293w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range271w291w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range268w289w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range265w287w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range262w285w & bias_addition_w(0));
exp_add_output_not_zero <= ( wire_altfp_div_pst1_w_lg_w_bias_addition_w_range280w281w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range277w278w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range274w275w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range271w272w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range268w269w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range265w266w & wire_altfp_div_pst1_w_lg_w_bias_addition_w_range262w263w & bias_addition_w(0));
exp_b_all_one_w <= ( wire_altfp_div_pst1_w_lg_w_datab_range74w79w & wire_altfp_div_pst1_w_lg_w_datab_range64w69w & wire_altfp_div_pst1_w_lg_w_datab_range54w59w & wire_altfp_div_pst1_w_lg_w_datab_range44w49w & wire_altfp_div_pst1_w_lg_w_datab_range34w39w & wire_altfp_div_pst1_w_lg_w_datab_range24w29w & wire_altfp_div_pst1_w_lg_w_datab_range14w19w & datab(23));
exp_b_not_zero_w <= ( wire_altfp_div_pst1_w_lg_w_datab_range74w75w & wire_altfp_div_pst1_w_lg_w_datab_range64w65w & wire_altfp_div_pst1_w_lg_w_datab_range54w55w & wire_altfp_div_pst1_w_lg_w_datab_range44w45w & wire_altfp_div_pst1_w_lg_w_datab_range34w35w & wire_altfp_div_pst1_w_lg_w_datab_range24w25w & wire_altfp_div_pst1_w_lg_w_datab_range14w15w & datab(23));
exp_result_mux_out <= wire_exp_result_muxa_dataout;
exp_result_mux_sel_w <= ((((a_zero_b_not_dffe_1 OR b_is_infinity_dffe_1) OR wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w312w(0)) OR (((NOT exp_add_output_not_zero(7)) AND wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w(0)) AND wire_altfp_div_pst1_w_lg_exp_sign_w303w(0))) AND wire_nan_pipe_dffe_1_w_lg_q308w(0));
exp_result_w <= (wire_altfp_div_pst1_w_lg_w_lg_w_lg_bias_addition_overf_w304w305w306w OR wire_altfp_div_pst1_w302w);
exp_sign_w <= wire_bias_addition_result(8);
exp_sub_a_w <= ( "0" & dataa(30 DOWNTO 23));
exp_sub_b_w <= ( "0" & datab(30 DOWNTO 23));
exp_sub_w <= wire_exp_sub_result;
frac_a_smaller_dffe1_wi <= frac_a_smaller_w;
frac_a_smaller_dffe1_wo <= frac_a_smaller_dffe1;
frac_a_smaller_w <= wire_cmpr2_alb;
guard_bit <= wire_q_partial_1_result(22);
man_a_adjusted_w <= wire_man_a_adjusteda_dataout;
man_a_dffe1_wi <= dataa(22 DOWNTO 0);
man_a_dffe1_wo <= man_a_dffe1_dffe1;
man_a_not_zero_w <= ( wire_altfp_div_pst1_w_lg_w_dataa_range213w214w & wire_altfp_div_pst1_w_lg_w_dataa_range207w208w & wire_altfp_div_pst1_w_lg_w_dataa_range201w202w & wire_altfp_div_pst1_w_lg_w_dataa_range195w196w & wire_altfp_div_pst1_w_lg_w_dataa_range189w190w & wire_altfp_div_pst1_w_lg_w_dataa_range183w184w & wire_altfp_div_pst1_w_lg_w_dataa_range177w178w & wire_altfp_div_pst1_w_lg_w_dataa_range171w172w & wire_altfp_div_pst1_w_lg_w_dataa_range165w166w & wire_altfp_div_pst1_w_lg_w_dataa_range159w160w & wire_altfp_div_pst1_w_lg_w_dataa_range153w154w & wire_altfp_div_pst1_w_lg_w_dataa_range147w148w & wire_altfp_div_pst1_w_lg_w_dataa_range141w142w & wire_altfp_div_pst1_w_lg_w_dataa_range135w136w & wire_altfp_div_pst1_w_lg_w_dataa_range129w130w & wire_altfp_div_pst1_w_lg_w_dataa_range123w124w & wire_altfp_div_pst1_w_lg_w_dataa_range117w118w & wire_altfp_div_pst1_w_lg_w_dataa_range111w112w & wire_altfp_div_pst1_w_lg_w_dataa_range105w106w & wire_altfp_div_pst1_w_lg_w_dataa_range99w100w & wire_altfp_div_pst1_w_lg_w_dataa_range93w94w & wire_altfp_div_pst1_w_lg_w_dataa_range87w88w & dataa(0));
man_b_adjusted_w <= ( "1" & man_b_dffe1_wo);
man_b_dffe1_wi <= datab(22 DOWNTO 0);
man_b_dffe1_wo <= man_b_dffe1_dffe1;
man_b_not_zero_w <= ( wire_altfp_div_pst1_w_lg_w_datab_range216w217w & wire_altfp_div_pst1_w_lg_w_datab_range210w211w & wire_altfp_div_pst1_w_lg_w_datab_range204w205w & wire_altfp_div_pst1_w_lg_w_datab_range198w199w & wire_altfp_div_pst1_w_lg_w_datab_range192w193w & wire_altfp_div_pst1_w_lg_w_datab_range186w187w & wire_altfp_div_pst1_w_lg_w_datab_range180w181w & wire_altfp_div_pst1_w_lg_w_datab_range174w175w & wire_altfp_div_pst1_w_lg_w_datab_range168w169w & wire_altfp_div_pst1_w_lg_w_datab_range162w163w & wire_altfp_div_pst1_w_lg_w_datab_range156w157w & wire_altfp_div_pst1_w_lg_w_datab_range150w151w & wire_altfp_div_pst1_w_lg_w_datab_range144w145w & wire_altfp_div_pst1_w_lg_w_datab_range138w139w & wire_altfp_div_pst1_w_lg_w_datab_range132w133w & wire_altfp_div_pst1_w_lg_w_datab_range126w127w & wire_altfp_div_pst1_w_lg_w_datab_range120w121w & wire_altfp_div_pst1_w_lg_w_datab_range114w115w & wire_altfp_div_pst1_w_lg_w_datab_range108w109w & wire_altfp_div_pst1_w_lg_w_datab_range102w103w & wire_altfp_div_pst1_w_lg_w_datab_range96w97w & wire_altfp_div_pst1_w_lg_w_datab_range90w91w & datab(0));
man_result_dffe_wi <= man_result_w;
man_result_dffe_wo <= man_result_dffe;
man_result_mux_select <= (((((over_under_dffe_2 OR a_zero_b_not_dffe_4) OR nan_pipe_dffe_4) OR b_is_infinity_dffe_4) OR a_is_infinity_dffe_4) OR divbyzero_pipe_dffe_4);
man_result_w <= wire_man_result_muxa_dataout;
man_zeros_w <= (OTHERS => '0');
overflow_ones_w <= (OTHERS => '1');
overflow_underflow <= (overflow_w OR underflow_w);
overflow_w <= (wire_altfp_div_pst1_w_lg_bias_addition_overf_w323w(0) AND ((wire_nan_pipe_dffe_1_w_lg_q308w(0) AND wire_a_is_infinity_dffe_1_w_lg_q318w(0)) AND wire_divbyzero_pipe_dffe_1_w_lg_q317w(0)));
quotient_accumulate_w <= ( quotient_k_dffe_0 & "00000000000000" & quotient_j_dffe & "00000000000000");
quotient_process_cin_w <= (round_bit AND (guard_bit OR sticky_bits(4)));
remainder_j_w <= ( wire_remainder_sub_0_result(35 DOWNTO 0) & "00000000000000" & wire_a1_prod_result(34 DOWNTO 0) & "000000000000000");
result <= ( sign_pipe_dffe_5 & exp_result_dffe_3 & man_result_dffe_wo);
round_bit <= wire_q_partial_1_result(21);
select_bias_out_2_w <= wire_select_bias_2a_dataout;
select_bias_out_w <= wire_select_biasa_dataout;
sticky_bits <= ( wire_q_partial_1_w_lg_w_result_range416w417w & wire_q_partial_1_w_lg_w_result_range413w414w & wire_q_partial_1_w_lg_w_result_range410w411w & wire_q_partial_1_w_lg_w_result_range407w408w & wire_q_partial_1_result(16));
underflow_w <= ((((wire_altfp_div_pst1_w_lg_w_lg_bias_addition_overf_w304w312w(0) OR (((NOT exp_add_output_not_zero(7)) AND wire_altfp_div_pst1_w_lg_bias_addition_overf_w304w(0)) AND wire_altfp_div_pst1_w_lg_exp_sign_w303w(0))) AND wire_nan_pipe_dffe_1_w_lg_q308w(0)) AND wire_a_zero_b_not_dffe_1_w_lg_q326w(0)) AND wire_b_is_infinity_dffe_1_w_lg_q325w(0));
underflow_zeros_w <= (OTHERS => '0');
value_add_one_w <= "001111111";
value_normal_w <= "001111110";
value_zero_w <= (OTHERS => '0');
wire_altfp_div_pst1_w_bias_addition_w_range262w(0) <= bias_addition_w(1);
wire_altfp_div_pst1_w_bias_addition_w_range265w(0) <= bias_addition_w(2);
wire_altfp_div_pst1_w_bias_addition_w_range268w(0) <= bias_addition_w(3);
wire_altfp_div_pst1_w_bias_addition_w_range271w(0) <= bias_addition_w(4);
wire_altfp_div_pst1_w_bias_addition_w_range274w(0) <= bias_addition_w(5);
wire_altfp_div_pst1_w_bias_addition_w_range277w(0) <= bias_addition_w(6);
wire_altfp_div_pst1_w_bias_addition_w_range280w(0) <= bias_addition_w(7);
wire_altfp_div_pst1_w_dataa_range141w(0) <= dataa(10);
wire_altfp_div_pst1_w_dataa_range147w(0) <= dataa(11);
wire_altfp_div_pst1_w_dataa_range153w(0) <= dataa(12);
wire_altfp_div_pst1_w_dataa_range159w(0) <= dataa(13);
wire_altfp_div_pst1_w_dataa_range165w(0) <= dataa(14);
wire_altfp_div_pst1_w_dataa_range171w(0) <= dataa(15);
wire_altfp_div_pst1_w_dataa_range177w(0) <= dataa(16);
wire_altfp_div_pst1_w_dataa_range183w(0) <= dataa(17);
wire_altfp_div_pst1_w_dataa_range189w(0) <= dataa(18);
wire_altfp_div_pst1_w_dataa_range195w(0) <= dataa(19);
wire_altfp_div_pst1_w_dataa_range87w(0) <= dataa(1);
wire_altfp_div_pst1_w_dataa_range201w(0) <= dataa(20);
wire_altfp_div_pst1_w_dataa_range207w(0) <= dataa(21);
wire_altfp_div_pst1_w_dataa_range213w(0) <= dataa(22);
wire_altfp_div_pst1_w_dataa_range11w(0) <= dataa(24);
wire_altfp_div_pst1_w_dataa_range21w(0) <= dataa(25);
wire_altfp_div_pst1_w_dataa_range31w(0) <= dataa(26);
wire_altfp_div_pst1_w_dataa_range41w(0) <= dataa(27);
wire_altfp_div_pst1_w_dataa_range51w(0) <= dataa(28);
wire_altfp_div_pst1_w_dataa_range61w(0) <= dataa(29);
wire_altfp_div_pst1_w_dataa_range93w(0) <= dataa(2);
wire_altfp_div_pst1_w_dataa_range71w(0) <= dataa(30);
wire_altfp_div_pst1_w_dataa_range99w(0) <= dataa(3);
wire_altfp_div_pst1_w_dataa_range105w(0) <= dataa(4);
wire_altfp_div_pst1_w_dataa_range111w(0) <= dataa(5);
wire_altfp_div_pst1_w_dataa_range117w(0) <= dataa(6);
wire_altfp_div_pst1_w_dataa_range123w(0) <= dataa(7);
wire_altfp_div_pst1_w_dataa_range129w(0) <= dataa(8);
wire_altfp_div_pst1_w_dataa_range135w(0) <= dataa(9);
wire_altfp_div_pst1_w_datab_range144w(0) <= datab(10);
wire_altfp_div_pst1_w_datab_range150w(0) <= datab(11);
wire_altfp_div_pst1_w_datab_range156w(0) <= datab(12);
wire_altfp_div_pst1_w_datab_range162w(0) <= datab(13);
wire_altfp_div_pst1_w_datab_range168w(0) <= datab(14);
wire_altfp_div_pst1_w_datab_range174w(0) <= datab(15);
wire_altfp_div_pst1_w_datab_range180w(0) <= datab(16);
wire_altfp_div_pst1_w_datab_range186w(0) <= datab(17);
wire_altfp_div_pst1_w_datab_range192w(0) <= datab(18);
wire_altfp_div_pst1_w_datab_range198w(0) <= datab(19);
wire_altfp_div_pst1_w_datab_range90w(0) <= datab(1);
wire_altfp_div_pst1_w_datab_range204w(0) <= datab(20);
wire_altfp_div_pst1_w_datab_range210w(0) <= datab(21);
wire_altfp_div_pst1_w_datab_range216w(0) <= datab(22);
wire_altfp_div_pst1_w_datab_range14w(0) <= datab(24);
wire_altfp_div_pst1_w_datab_range24w(0) <= datab(25);
wire_altfp_div_pst1_w_datab_range34w(0) <= datab(26);
wire_altfp_div_pst1_w_datab_range44w(0) <= datab(27);
wire_altfp_div_pst1_w_datab_range54w(0) <= datab(28);
wire_altfp_div_pst1_w_datab_range64w(0) <= datab(29);
wire_altfp_div_pst1_w_datab_range96w(0) <= datab(2);
wire_altfp_div_pst1_w_datab_range74w(0) <= datab(30);
wire_altfp_div_pst1_w_datab_range102w(0) <= datab(3);
wire_altfp_div_pst1_w_datab_range108w(0) <= datab(4);
wire_altfp_div_pst1_w_datab_range114w(0) <= datab(5);
wire_altfp_div_pst1_w_datab_range120w(0) <= datab(6);
wire_altfp_div_pst1_w_datab_range126w(0) <= datab(7);
wire_altfp_div_pst1_w_datab_range132w(0) <= datab(8);
wire_altfp_div_pst1_w_datab_range138w(0) <= datab(9);
wire_altfp_div_pst1_w_e1_w_range360w <= e1_w(16 DOWNTO 0);
wire_altfp_div_pst1_w_e1_w_range368w <= e1_w(33 DOWNTO 17);
wire_altfp_div_pst1_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_altfp_div_pst1_w_exp_a_all_one_w_range18w(0) <= exp_a_all_one_w(1);
wire_altfp_div_pst1_w_exp_a_all_one_w_range28w(0) <= exp_a_all_one_w(2);
wire_altfp_div_pst1_w_exp_a_all_one_w_range38w(0) <= exp_a_all_one_w(3);
wire_altfp_div_pst1_w_exp_a_all_one_w_range48w(0) <= exp_a_all_one_w(4);
wire_altfp_div_pst1_w_exp_a_all_one_w_range58w(0) <= exp_a_all_one_w(5);
wire_altfp_div_pst1_w_exp_a_all_one_w_range68w(0) <= exp_a_all_one_w(6);
wire_altfp_div_pst1_w_exp_a_all_one_w_range78w(0) <= exp_a_all_one_w(7);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range13w(0) <= exp_a_not_zero_w(1);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range23w(0) <= exp_a_not_zero_w(2);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range33w(0) <= exp_a_not_zero_w(3);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range43w(0) <= exp_a_not_zero_w(4);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range53w(0) <= exp_a_not_zero_w(5);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range63w(0) <= exp_a_not_zero_w(6);
wire_altfp_div_pst1_w_exp_a_not_zero_w_range73w(0) <= exp_a_not_zero_w(7);
wire_altfp_div_pst1_w_exp_add_output_all_one_range283w(0) <= exp_add_output_all_one(0);
wire_altfp_div_pst1_w_exp_add_output_all_one_range286w(0) <= exp_add_output_all_one(1);
wire_altfp_div_pst1_w_exp_add_output_all_one_range288w(0) <= exp_add_output_all_one(2);
wire_altfp_div_pst1_w_exp_add_output_all_one_range290w(0) <= exp_add_output_all_one(3);
wire_altfp_div_pst1_w_exp_add_output_all_one_range292w(0) <= exp_add_output_all_one(4);
wire_altfp_div_pst1_w_exp_add_output_all_one_range294w(0) <= exp_add_output_all_one(5);
wire_altfp_div_pst1_w_exp_add_output_all_one_range296w(0) <= exp_add_output_all_one(6);
wire_altfp_div_pst1_w_exp_add_output_all_one_range298w(0) <= exp_add_output_all_one(7);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range260w(0) <= exp_add_output_not_zero(0);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range264w(0) <= exp_add_output_not_zero(1);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range267w(0) <= exp_add_output_not_zero(2);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range270w(0) <= exp_add_output_not_zero(3);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range273w(0) <= exp_add_output_not_zero(4);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range276w(0) <= exp_add_output_not_zero(5);
wire_altfp_div_pst1_w_exp_add_output_not_zero_range279w(0) <= exp_add_output_not_zero(6);
wire_altfp_div_pst1_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_altfp_div_pst1_w_exp_b_all_one_w_range20w(0) <= exp_b_all_one_w(1);
wire_altfp_div_pst1_w_exp_b_all_one_w_range30w(0) <= exp_b_all_one_w(2);
wire_altfp_div_pst1_w_exp_b_all_one_w_range40w(0) <= exp_b_all_one_w(3);
wire_altfp_div_pst1_w_exp_b_all_one_w_range50w(0) <= exp_b_all_one_w(4);
wire_altfp_div_pst1_w_exp_b_all_one_w_range60w(0) <= exp_b_all_one_w(5);
wire_altfp_div_pst1_w_exp_b_all_one_w_range70w(0) <= exp_b_all_one_w(6);
wire_altfp_div_pst1_w_exp_b_all_one_w_range80w(0) <= exp_b_all_one_w(7);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range16w(0) <= exp_b_not_zero_w(1);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range26w(0) <= exp_b_not_zero_w(2);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range36w(0) <= exp_b_not_zero_w(3);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range46w(0) <= exp_b_not_zero_w(4);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range56w(0) <= exp_b_not_zero_w(5);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range66w(0) <= exp_b_not_zero_w(6);
wire_altfp_div_pst1_w_exp_b_not_zero_w_range76w(0) <= exp_b_not_zero_w(7);
wire_altfp_div_pst1_w_man_a_not_zero_w_range82w(0) <= man_a_not_zero_w(0);
wire_altfp_div_pst1_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_altfp_div_pst1_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_altfp_div_pst1_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_altfp_div_pst1_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_altfp_div_pst1_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_altfp_div_pst1_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_altfp_div_pst1_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_altfp_div_pst1_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_altfp_div_pst1_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_altfp_div_pst1_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_altfp_div_pst1_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_altfp_div_pst1_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_altfp_div_pst1_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_altfp_div_pst1_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_altfp_div_pst1_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_altfp_div_pst1_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_altfp_div_pst1_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_altfp_div_pst1_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_altfp_div_pst1_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_altfp_div_pst1_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_altfp_div_pst1_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_altfp_div_pst1_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_altfp_div_pst1_w_man_b_not_zero_w_range85w(0) <= man_b_not_zero_w(0);
wire_altfp_div_pst1_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_altfp_div_pst1_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_altfp_div_pst1_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_altfp_div_pst1_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_altfp_div_pst1_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_altfp_div_pst1_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_altfp_div_pst1_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_altfp_div_pst1_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_altfp_div_pst1_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_altfp_div_pst1_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_altfp_div_pst1_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_altfp_div_pst1_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_altfp_div_pst1_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_altfp_div_pst1_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_altfp_div_pst1_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_altfp_div_pst1_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_altfp_div_pst1_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_altfp_div_pst1_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_altfp_div_pst1_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_altfp_div_pst1_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_altfp_div_pst1_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_altfp_div_pst1_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_altfp_div_pst1_w_remainder_j_w_range363w <= remainder_j_w(49 DOWNTO 0);
wire_altfp_div_pst1_w_sticky_bits_range405w(0) <= sticky_bits(0);
wire_altfp_div_pst1_w_sticky_bits_range409w(0) <= sticky_bits(1);
wire_altfp_div_pst1_w_sticky_bits_range412w(0) <= sticky_bits(2);
wire_altfp_div_pst1_w_sticky_bits_range415w(0) <= sticky_bits(3);
wire_altfp_div_pst1_w_w_quotient_accumulate_w_range385w_range386w <= quotient_accumulate_w(30 DOWNTO 14);
altsyncram3 : altsyncram
GENERIC MAP (
INIT_FILE => "fp_div.hex",
OPERATION_MODE => "ROM",
WIDTH_A => 9,
WIDTHAD_A => 9,
INTENDED_DEVICE_FAMILY => "Cyclone II"
)
PORT MAP (
address_a => datab(22 DOWNTO 14),
clock0 => clock,
clocken0 => clk_en,
q_a => wire_altsyncram3_q_a
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_is_infinity_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_is_infinity_dffe_0 <= a_is_infinity_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_is_infinity_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
END IF;
END IF;
END PROCESS;
wire_a_is_infinity_dffe_1_w_lg_q318w(0) <= NOT a_is_infinity_dffe_1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_is_infinity_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_is_infinity_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_is_infinity_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_zero_b_not_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_zero_b_not_dffe_0 <= a_zero_b_not;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_zero_b_not_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
END IF;
END IF;
END PROCESS;
wire_a_zero_b_not_dffe_1_w_lg_q326w(0) <= NOT a_zero_b_not_dffe_1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_zero_b_not_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_zero_b_not_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN a_zero_b_not_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b1_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN b1_dffe_0 <= wire_b1_prod_result;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_is_infinity_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN b_is_infinity_dffe_0 <= b_is_infinity_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_is_infinity_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
END IF;
END IF;
END PROCESS;
wire_b_is_infinity_dffe_1_w_lg_q325w(0) <= NOT b_is_infinity_dffe_1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_is_infinity_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_is_infinity_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_is_infinity_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_exp_zeros_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_exp_zeros_dffe <= ((NOT exp_b_not_zero_w(7)) AND wire_altfp_div_pst1_w_lg_w_exp_a_not_zero_w_range73w227w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divbyzero_pipe_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN divbyzero_pipe_dffe_0 <= ((((NOT exp_b_not_zero_w(7)) AND wire_altfp_div_pst1_w_lg_a_is_nan_w234w(0)) AND exp_a_not_zero_w(7)) AND wire_altfp_div_pst1_w_lg_a_is_infinity_w233w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divbyzero_pipe_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
END IF;
END IF;
END PROCESS;
wire_divbyzero_pipe_dffe_1_w_lg_q317w(0) <= NOT divbyzero_pipe_dffe_1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divbyzero_pipe_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divbyzero_pipe_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN divbyzero_pipe_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN e1_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN e1_dffe_0 <= wire_altfp_div_pst1_w_e1_w_range360w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN e1_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN e1_dffe_1 <= wire_altfp_div_pst1_w_e1_w_range368w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_dffe_0 <= exp_result_mux_out;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_dffe_1 <= exp_result_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_dffe_2 <= exp_result_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_dffe_3 <= exp_result_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN frac_a_smaller_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN frac_a_smaller_dffe1 <= frac_a_smaller_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_a_dffe1_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_a_dffe1_dffe1 <= man_a_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_b_dffe1_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_b_dffe1_dffe1 <= man_b_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_result_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_result_dffe <= man_result_dffe_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_pipe_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_pipe_dffe_0 <= (((a_is_nan_w OR b_is_nan_w) OR (a_is_infinity_w AND b_is_infinity_w)) OR (wire_altfp_div_pst1_w_lg_w_exp_a_not_zero_w_range73w227w(0) AND (NOT exp_b_not_zero_w(7))));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_pipe_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_pipe_dffe_1 <= nan_pipe_dffe_0;
END IF;
END IF;
END PROCESS;
wire_nan_pipe_dffe_1_w_lg_q308w(0) <= NOT nan_pipe_dffe_1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_pipe_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_pipe_dffe_2 <= nan_pipe_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_pipe_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_pipe_dffe_3 <= nan_pipe_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_pipe_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_pipe_dffe_4 <= nan_pipe_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN over_under_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN over_under_dffe_0 <= overflow_underflow;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN over_under_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN over_under_dffe_1 <= over_under_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN over_under_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN over_under_dffe_2 <= over_under_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN quotient_j_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN quotient_j_dffe <= wire_q_partial_0_w_result_range373w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN quotient_k_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN quotient_k_dffe_0 <= wire_altfp_div_pst1_w_w_quotient_accumulate_w_range385w_range386w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN remainder_j_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN remainder_j_dffe_0 <= wire_altfp_div_pst1_w_remainder_j_w_range363w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN remainder_j_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN remainder_j_dffe_1 <= remainder_j_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_pipe_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_pipe_dffe_0 <= (dataa(31) XOR datab(31));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_pipe_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_pipe_dffe_1 <= sign_pipe_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_pipe_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_pipe_dffe_2 <= sign_pipe_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_pipe_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_pipe_dffe_3 <= sign_pipe_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_pipe_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_pipe_dffe_4 <= sign_pipe_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_pipe_dffe_5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_pipe_dffe_5 <= sign_pipe_dffe_4;
END IF;
END IF;
END PROCESS;
bias_addition : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_sub_w,
datab => select_bias_out_2_w,
overflow => wire_bias_addition_overflow,
result => wire_bias_addition_result
);
exp_sub : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_sub_a_w,
datab => exp_sub_b_w,
result => wire_exp_sub_result
);
wire_quotient_process_dataa <= ( quotient_accumulate_w(61 DOWNTO 45) & "00000000000000");
wire_quotient_process_datab <= ( "00000000000000" & wire_q_partial_1_result(32 DOWNTO 22) & "111111");
wire_quotient_process_w_result_range425w <= wire_quotient_process_result(28 DOWNTO 6);
quotient_process : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 31
)
PORT MAP (
cin => quotient_process_cin_w,
dataa => wire_quotient_process_dataa,
datab => wire_quotient_process_datab,
result => wire_quotient_process_result
);
wire_remainder_sub_0_dataa <= ( remainder_j_dffe_1(49 DOWNTO 15) & "000000000000000");
remainder_sub_0 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 50
)
PORT MAP (
dataa => wire_remainder_sub_0_dataa,
datab => wire_remainder_mult_0_result(49 DOWNTO 0),
result => wire_remainder_sub_0_result
);
cmpr2 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 23
)
PORT MAP (
alb => wire_cmpr2_alb,
dataa => dataa(22 DOWNTO 0),
datab => datab(22 DOWNTO 0)
);
wire_a1_prod_datab <= ( "1" & e0_dffe1_wo);
a1_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 25,
LPM_WIDTHB => 10,
LPM_WIDTHP => 35,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => man_a_adjusted_w,
datab => wire_a1_prod_datab,
result => wire_a1_prod_result
);
loop2 : FOR i IN 0 TO 16 GENERATE
wire_b1_prod_w_lg_w_result_range358w359w(i) <= NOT wire_b1_prod_w_result_range358w(i);
END GENERATE loop2;
wire_b1_prod_datab <= ( "1" & e0_dffe1_wo);
wire_b1_prod_w_result_range358w <= wire_b1_prod_result(33 DOWNTO 17);
b1_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 24,
LPM_WIDTHB => 10,
LPM_WIDTHP => 34,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => man_b_adjusted_w,
datab => wire_b1_prod_datab,
result => wire_b1_prod_result
);
wire_q_partial_0_w_result_range373w <= wire_q_partial_0_result(32 DOWNTO 16);
q_partial_0 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 17,
LPM_WIDTHB => 17,
LPM_WIDTHP => 34,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => remainder_j_w(49 DOWNTO 33),
datab => e1_w(16 DOWNTO 0),
result => wire_q_partial_0_result
);
wire_q_partial_1_w_lg_w_result_range407w408w(0) <= wire_q_partial_1_w_result_range407w(0) OR wire_altfp_div_pst1_w_sticky_bits_range405w(0);
wire_q_partial_1_w_lg_w_result_range410w411w(0) <= wire_q_partial_1_w_result_range410w(0) OR wire_altfp_div_pst1_w_sticky_bits_range409w(0);
wire_q_partial_1_w_lg_w_result_range413w414w(0) <= wire_q_partial_1_w_result_range413w(0) OR wire_altfp_div_pst1_w_sticky_bits_range412w(0);
wire_q_partial_1_w_lg_w_result_range416w417w(0) <= wire_q_partial_1_w_result_range416w(0) OR wire_altfp_div_pst1_w_sticky_bits_range415w(0);
wire_q_partial_1_w_result_range407w(0) <= wire_q_partial_1_result(17);
wire_q_partial_1_w_result_range410w(0) <= wire_q_partial_1_result(18);
wire_q_partial_1_w_result_range413w(0) <= wire_q_partial_1_result(19);
wire_q_partial_1_w_result_range416w(0) <= wire_q_partial_1_result(20);
q_partial_1 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 17,
LPM_WIDTHB => 17,
LPM_WIDTHP => 34,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => remainder_j_w(99 DOWNTO 83),
datab => e1_w(50 DOWNTO 34),
result => wire_q_partial_1_result
);
remainder_mult_0 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 34,
LPM_WIDTHB => 17,
LPM_WIDTHP => 51,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => b1_dffe_w(33 DOWNTO 0),
datab => wire_q_partial_0_result(32 DOWNTO 16),
result => wire_remainder_mult_0_result
);
wire_exp_result_muxa_dataout <= underflow_zeros_w WHEN exp_result_mux_sel_w = '1' ELSE exp_result_w;
wire_man_a_adjusteda_dataout <= ( "1" & man_a_dffe1_wo & "0") WHEN frac_a_smaller_dffe1_wo = '1' ELSE ( "0" & "1" & man_a_dffe1_wo);
wire_man_result_muxa_dataout <= ( nan_pipe_dffe_4 & man_zeros_w(21 DOWNTO 0)) WHEN man_result_mux_select = '1' ELSE wire_quotient_process_result(28 DOWNTO 6);
wire_select_bias_2a_dataout <= value_zero_w WHEN both_exp_zeros = '1' ELSE select_bias_out_w;
wire_select_biasa_dataout <= value_normal_w WHEN frac_a_smaller_dffe1_wo = '1' ELSE value_add_one_w;
END RTL; --fp_div_altfp_div_pst_foe
--synthesis_resources = altsyncram 1 lpm_add_sub 4 lpm_compare 1 lpm_mult 5 mux21 74 reg 339
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_div_altfp_div_6ai IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_altfp_div_6ai;
ARCHITECTURE RTL OF fp_div_altfp_div_6ai IS
SIGNAL wire_altfp_div_pst1_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_div_altfp_div_pst_foe
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= wire_altfp_div_pst1_result;
altfp_div_pst1 : fp_div_altfp_div_pst_foe
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
dataa => dataa,
datab => datab,
result => wire_altfp_div_pst1_result
);
END RTL; --fp_div_altfp_div_6ai
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_div IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div;
ARCHITECTURE RTL OF fp_div IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_div_altfp_div_6ai
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_div_altfp_div_6ai_component : fp_div_altfp_div_6ai
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "6"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_div.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_div.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_div.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_div.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_div_inst.vhd FALSE
|
mit
|
e8c6131dec48a965dd5072ae259343c3
| 0.687523 | 2.340662 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_buffer.vhd
| 1 | 5,057 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_buffer
---- Version: 1.0.0
---- Description:
---- FIFO circular buffer
---- Input: 1 clk / [STORE: dat_val_i <= '1' / dat_i <= "STOREDDATA" ] / [READ: nxt_i <= '1']
---- Timing requirements: 1 clock cycle
---- Output: [READ: dat_val_o <= "1" / dat_o <= "STOREDDATA"]
---- Ressources requirements: CCSDS_RXTX_BUFFER_DATA_BUS_SIZE*(CCSDS_RXTX_BUFFER_SIZE+1) + 2*|log(CCSDS_RXTX_BUFFER_SIZE-1)/log(2)| + 2 + 3 + CCSDS_RXTX_BUFFER_DATA_BUS_SIZE registers
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
---- 2016/10/20: major corrections and optimizations
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary rxtx buffer inputs and outputs
--=============================================================================
entity ccsds_rxtx_buffer is
generic(
constant CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer; -- in bits
constant CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_nxt_i: in std_logic;
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
buf_emp_o: out std_logic;
buf_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_rxtx_buffer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_rxtx_buffer is
-- interconnection signals
type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
signal buffer_data: buffer_array := (others => (others => '0'));
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
-- components instanciation and mapping
begin
-- internal processing
--=============================================================================
-- Begin of bufferpullp
-- Read data from buffer
--=============================================================================
-- read: nxt_dat_i, rst_i, buffer_write_pos, buffer_data
-- write: dat_o, dat_val_o, buf_emp_o
-- r/w: buffer_read_pos
BUFFERPULLP : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
buf_emp_o <= '1';
buffer_read_pos <= 0;
dat_o <= (others => '0');
dat_val_o <= '0';
else
if (buffer_read_pos = buffer_write_pos) then
buf_emp_o <= '1';
dat_val_o <= '0';
else
buf_emp_o <= '0';
if (dat_nxt_i = '1') then
dat_val_o <= '1';
dat_o <= buffer_data(buffer_read_pos);
if (buffer_read_pos < CCSDS_RXTX_BUFFER_SIZE) then
buffer_read_pos <= (buffer_read_pos + 1);
else
buffer_read_pos <= 0;
end if;
else
dat_val_o <= '0';
end if;
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of bufferpushp
-- Store valid input data in buffer
--=============================================================================
-- read: dat_i, dat_val_i, buffer_read_pos, rst_i
-- write: buffer_data, buf_ful_o
-- r/w: buffer_write_pos
BUFFERPUSH : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
-- buffer_data <= (others => (others => '0'));
buf_ful_o <= '0';
buffer_write_pos <= 0;
else
if (buffer_write_pos < CCSDS_RXTX_BUFFER_SIZE) then
if (buffer_read_pos = (buffer_write_pos+1)) then
buf_ful_o <= '1';
else
buf_ful_o <= '0';
if (dat_val_i = '1') then
buffer_data(buffer_write_pos) <= dat_i;
buffer_write_pos <= (buffer_write_pos + 1);
end if;
end if;
else
if (buffer_read_pos = 0) then
buf_ful_o <= '1';
else
buf_ful_o <= '0';
if (dat_val_i = '1') then
buffer_data(buffer_write_pos) <= dat_i;
buffer_write_pos <= 0;
end if;
end if;
end if;
end if;
end if;
end process;
end rtl;
|
mit
|
6c75166730d7d1c928d638004b252c6d
| 0.462725 | 3.941543 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_footer.vhd
| 1 | 3,118 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_footer
---- Version: 1.0.0
---- Description:
---- TBD
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/28: initial release
---- 2016/10/21: rework
-------------------------------
--TODO: operationnal control field
--TODO: security trailer
--[OPT] SECURITY TRAILER
--[OPT] TRANSFER FRAME TRAILER (2 to 6 octets)
-- \ [OPT] OPERATIONAL CONTROL FIELD => 4 octets
-- \ [OPT] Frame error control field => 2 octets
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx footer inputs and outputs
--=============================================================================
entity ccsds_tx_footer is
generic(
constant CCSDS_TX_FOOTER_DATA_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FOOTER_LENGTH: integer -- in Bytes
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FOOTER_DATA_LENGTH*8-1 downto 0);
nxt_i: in std_logic;
rst_i: in std_logic;
-- outputs
bus_o: out std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FOOTER_DATA_LENGTH+CCSDS_TX_FOOTER_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_footer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_footer is
component ccsds_rxtx_crc is
generic(
constant CCSDS_RXTX_CRC_LENGTH: integer;
constant CCSDS_RXTX_CRC_DATA_LENGTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
nxt_i: in std_logic;
pad_dat_i: in std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
pad_dat_val_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
bus_o: out std_logic;
crc_o: out std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal variable signals
-- components instanciation and mapping
begin
tx_footer_crc_0: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_TX_FOOTER_DATA_LENGTH,
CCSDS_RXTX_CRC_LENGTH => CCSDS_TX_FOOTER_LENGTH
)
port map(
clk_i => clk_i,
rst_i => rst_i,
nxt_i => nxt_i,
pad_dat_i => (others => '0'),
pad_dat_val_i => '0',
bus_o => bus_o,
dat_i => dat_i,
crc_o => dat_o(CCSDS_TX_FOOTER_LENGTH*8-1 downto 0),
dat_o => dat_o((CCSDS_TX_FOOTER_DATA_LENGTH+CCSDS_TX_FOOTER_LENGTH)*8-1 downto CCSDS_TX_FOOTER_LENGTH*8),
dat_val_o => dat_val_o
);
-- internal processing
end structure;
|
mit
|
57dd0d54d1e9cd699d2b7b28b1540e26
| 0.54458 | 3.672556 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp_exp.vhd
| 1 | 124,362 |
-- megafunction wizard: %ALTFP_EXP%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_EXP
-- ============================================================
-- File Name: fp_exp.vhd
-- Megafunction Name(s):
-- ALTFP_EXP
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_exp CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=17 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock data result
--VERSION_BEGIN 9.1SP2 cbx_altfp_exp 2010:03:24:20:34:20:SJ cbx_altmult_opt 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_clshift 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_lpm_mult 2010:03:24:20:34:20:SJ cbx_lpm_mux 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_padd 2010:03:24:20:34:20:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ cbx_util_mgl 2010:03:24:20:34:20:SJ VERSION_END
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_add_sub 9 lpm_clshift 1 lpm_compare 3 lpm_mult 5 lpm_mux 3 mux21 124 reg 745
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_exp_altfp_exp_fkd IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_altfp_exp_fkd;
ARCHITECTURE RTL OF fp_exp_altfp_exp_fkd IS
SIGNAL barrel_shifter_underflow_dffe2_15_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_0 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_10 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_6 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_7 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_8 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_9 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_dffe1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_extra_ln2_dffe_5_w_lg_q157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fraction_dffe1 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_overflow_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_prod_dffe14 : STD_LOGIC_VECTOR(61 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_dffe15 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL result_pipe_dffe16 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL round_up_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_sign_dffe_w_lg_q448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_sign_dffe_w_lg_q434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tbl1_compare_dffe11_4_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_tbl2_prod_dffe12 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tbl3_taylor_prod_dffe12 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_0 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_1 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_2 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_3 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_4 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xf_pre_2_dffe10 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xf_pre_dffe9 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_exp_value_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_ln2_prod_dffe7 : STD_LOGIC_VECTOR(45 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_prod_dffe3 : STD_LOGIC_VECTOR(20 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_exp_minus_bias_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_minus_bias_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_minus_bias_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_w_lg_w_result_range445w446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_w_result_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_lg_w_result_range435w436w437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_result_range435w436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range435w436w437w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_man_over_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_result_range435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_invert_exp_value_dataa : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_invert_exp_value_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_invert_exp_value_w_result_range130w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_man_round_datab : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_man_round_result : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_one_minus_xf_dataa : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_one_minus_xf_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_x_fixed_minus_xiln2_datab : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_x_fixed_minus_xiln2_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_xf_minus_ln2_datab : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_xf_minus_ln2_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_xi_add_one_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_xi_add_one_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_distance_overflow_comp_agb : STD_LOGIC;
SIGNAL wire_tbl1_compare_ageb : STD_LOGIC;
SIGNAL wire_underflow_compare_agb : STD_LOGIC;
SIGNAL wire_man_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_tbl1_tbl2_prod_result : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL wire_tbl3_taylor_prod_datab : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_tbl3_taylor_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_xi_ln2_prod_result : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL wire_xi_prod_result : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_table_one_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 31 DOWNTO 0);
SIGNAL wire_table_one_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_table_three_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 20 DOWNTO 0);
SIGNAL wire_table_three_result : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_table_two_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 25 DOWNTO 0);
SIGNAL wire_table_two_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_cin_to_bias_dataout : STD_LOGIC;
SIGNAL wire_exp_result_mux_prea_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_result_mux_prea_w_lg_dataout557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_value_b4_biasa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_value_selecta_dataout : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL wire_exp_value_to_compare_muxa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_value_to_ln2a_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_extra_ln2_muxa_dataout : STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL wire_man_result_muxa_dataout : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL wire_xf_muxa_dataout : STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL wire_w_lg_man_prod_shifted408w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_w_lg_man_prod_wire407w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_w_lg_underflow_w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range10w34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range13w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range16w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range19w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range22w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range25w44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range28w46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_data_all_one_w_range47w119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range563w564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range568w569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range573w574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range578w579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range583w584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range588w589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range593w594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range492w493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range495w496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range498w499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range501w502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range504w505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range507w508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range510w511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range513w514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range516w517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range519w520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range465w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range522w523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range525w526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range528w529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range468w469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range471w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range474w475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range477w478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range480w481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range483w484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range486w487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range489w490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_underflow_w554w555w556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_barrel_shifter_underflow553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_infinity_wo443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_nan_wo442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_zero_wo444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_underflow_w454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_data_not_zero_w_range116w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_wo_range402w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_underflow_w554w555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_overflow_w536w537w538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_barrel_shifter_underflow549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_overflow_w542w543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_overflow_w536w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_barrel_shifter_underflow549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_distance_overflow447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_distance_overflow456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_overflow_w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_overflow_w536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range78w79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range81w82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range10w11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range13w14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range16w17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range19w20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range22w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range25w26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range28w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range63w64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range66w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range69w70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range72w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range75w76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range563w566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range568w571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range573w576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range578w581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range583w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range588w591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range593w595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range424w425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range421w422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range418w419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range415w416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addr_val_more_than_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL barrel_shifter_data : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL barrel_shifter_distance : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL barrel_shifter_underflow : STD_LOGIC;
SIGNAL barrel_shifter_underflow_wi : STD_LOGIC;
SIGNAL distance_overflow : STD_LOGIC;
SIGNAL distance_overflow_val_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL distance_overflow_wi : STD_LOGIC;
SIGNAL exp_bias : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bias_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_data_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_data_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_invert : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL extra_ln2 : STD_LOGIC;
SIGNAL fraction : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL fraction_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL fraction_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL gnd_w : STD_LOGIC;
SIGNAL guard_bit : STD_LOGIC;
SIGNAL input_is_infinity_wi : STD_LOGIC;
SIGNAL input_is_infinity_wo : STD_LOGIC;
SIGNAL input_is_nan_wi : STD_LOGIC;
SIGNAL input_is_nan_wo : STD_LOGIC;
SIGNAL input_is_zero_wi : STD_LOGIC;
SIGNAL input_is_zero_wo : STD_LOGIC;
SIGNAL ln2_w : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL man_data_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_overflow : STD_LOGIC;
SIGNAL man_overflow_wi : STD_LOGIC;
SIGNAL man_overflow_wo : STD_LOGIC;
SIGNAL man_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_shifted : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wi : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wire : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wo : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_result_all_ones : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_result_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_round_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_round_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL nan_w : STD_LOGIC;
SIGNAL negative_infinity : STD_LOGIC;
SIGNAL one_over_ln2_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL overflow_w : STD_LOGIC;
SIGNAL positive_infinity : STD_LOGIC;
SIGNAL result_pipe_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL result_pipe_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL result_underflow_w : STD_LOGIC;
SIGNAL round_bit : STD_LOGIC;
SIGNAL round_up : STD_LOGIC;
SIGNAL round_up_wi : STD_LOGIC;
SIGNAL round_up_wo : STD_LOGIC;
SIGNAL shifted_value : STD_LOGIC;
SIGNAL sign_w : STD_LOGIC;
SIGNAL sticky_bits : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL table_one_data : STD_LOGIC_VECTOR (1023 DOWNTO 0);
SIGNAL table_one_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_three_data : STD_LOGIC_VECTOR (671 DOWNTO 0);
SIGNAL table_three_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_three_out_tmp : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL table_two_data : STD_LOGIC_VECTOR (831 DOWNTO 0);
SIGNAL table_two_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_two_out_tmp : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL tbl1_compare_wi : STD_LOGIC;
SIGNAL tbl1_compare_wo : STD_LOGIC;
SIGNAL tbl1_tbl2_prod_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl1_tbl2_prod_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl3_taylor_prod_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl3_taylor_prod_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL underflow_compare_val_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL underflow_w : STD_LOGIC;
SIGNAL x_fixed : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL xf_pre : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_2_wi : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_2_wo : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_wi : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_wo : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xi_exp_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_exp_value_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_exp_value_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_ln2_prod_wi : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL xi_ln2_prod_wo : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL xi_prod_wi : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL xi_prod_wo : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_w_data_range78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range8w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range129w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range132w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_wo_range402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_xf_pre_2_wo_range183w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_w_xf_pre_wo_range177w : STD_LOGIC_VECTOR (30 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_clshift
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_SHIFTTYPE : STRING := "LOGICAL";
LPM_WIDTH : NATURAL;
LPM_WIDTHDIST : NATURAL;
lpm_type : STRING := "lpm_clshift"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
direction : IN STD_LOGIC := '0';
distance : IN STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
underflow : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO 61 GENERATE
wire_w_lg_man_prod_shifted408w(i) <= man_prod_shifted(i) AND wire_w_man_prod_wo_range402w(0);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 61 GENERATE
wire_w_lg_man_prod_wire407w(i) <= man_prod_wire(i) AND wire_w_lg_w_man_prod_wo_range402w406w(0);
END GENERATE loop1;
wire_w_lg_underflow_w554w(0) <= underflow_w AND wire_w_lg_barrel_shifter_underflow553w(0);
wire_w_lg_w_data_range10w34w(0) <= wire_w_data_range10w(0) AND wire_w_exp_data_all_one_w_range32w(0);
wire_w_lg_w_data_range13w36w(0) <= wire_w_data_range13w(0) AND wire_w_exp_data_all_one_w_range35w(0);
wire_w_lg_w_data_range16w38w(0) <= wire_w_data_range16w(0) AND wire_w_exp_data_all_one_w_range37w(0);
wire_w_lg_w_data_range19w40w(0) <= wire_w_data_range19w(0) AND wire_w_exp_data_all_one_w_range39w(0);
wire_w_lg_w_data_range22w42w(0) <= wire_w_data_range22w(0) AND wire_w_exp_data_all_one_w_range41w(0);
wire_w_lg_w_data_range25w44w(0) <= wire_w_data_range25w(0) AND wire_w_exp_data_all_one_w_range43w(0);
wire_w_lg_w_data_range28w46w(0) <= wire_w_data_range28w(0) AND wire_w_exp_data_all_one_w_range45w(0);
wire_w_lg_w_exp_data_all_one_w_range47w119w(0) <= wire_w_exp_data_all_one_w_range47w(0) AND wire_w_lg_w_man_data_not_zero_w_range116w118w(0);
wire_w_lg_w_exp_result_w_range563w564w(0) <= wire_w_exp_result_w_range563w(0) AND wire_w_exp_out_all_one_w_range559w(0);
wire_w_lg_w_exp_result_w_range568w569w(0) <= wire_w_exp_result_w_range568w(0) AND wire_w_exp_out_all_one_w_range565w(0);
wire_w_lg_w_exp_result_w_range573w574w(0) <= wire_w_exp_result_w_range573w(0) AND wire_w_exp_out_all_one_w_range570w(0);
wire_w_lg_w_exp_result_w_range578w579w(0) <= wire_w_exp_result_w_range578w(0) AND wire_w_exp_out_all_one_w_range575w(0);
wire_w_lg_w_exp_result_w_range583w584w(0) <= wire_w_exp_result_w_range583w(0) AND wire_w_exp_out_all_one_w_range580w(0);
wire_w_lg_w_exp_result_w_range588w589w(0) <= wire_w_exp_result_w_range588w(0) AND wire_w_exp_out_all_one_w_range585w(0);
wire_w_lg_w_exp_result_w_range593w594w(0) <= wire_w_exp_result_w_range593w(0) AND wire_w_exp_out_all_one_w_range590w(0);
wire_w_lg_w_man_round_wi_range492w493w(0) <= wire_w_man_round_wi_range492w(0) AND wire_w_man_result_all_ones_range491w(0);
wire_w_lg_w_man_round_wi_range495w496w(0) <= wire_w_man_round_wi_range495w(0) AND wire_w_man_result_all_ones_range494w(0);
wire_w_lg_w_man_round_wi_range498w499w(0) <= wire_w_man_round_wi_range498w(0) AND wire_w_man_result_all_ones_range497w(0);
wire_w_lg_w_man_round_wi_range501w502w(0) <= wire_w_man_round_wi_range501w(0) AND wire_w_man_result_all_ones_range500w(0);
wire_w_lg_w_man_round_wi_range504w505w(0) <= wire_w_man_round_wi_range504w(0) AND wire_w_man_result_all_ones_range503w(0);
wire_w_lg_w_man_round_wi_range507w508w(0) <= wire_w_man_round_wi_range507w(0) AND wire_w_man_result_all_ones_range506w(0);
wire_w_lg_w_man_round_wi_range510w511w(0) <= wire_w_man_round_wi_range510w(0) AND wire_w_man_result_all_ones_range509w(0);
wire_w_lg_w_man_round_wi_range513w514w(0) <= wire_w_man_round_wi_range513w(0) AND wire_w_man_result_all_ones_range512w(0);
wire_w_lg_w_man_round_wi_range516w517w(0) <= wire_w_man_round_wi_range516w(0) AND wire_w_man_result_all_ones_range515w(0);
wire_w_lg_w_man_round_wi_range519w520w(0) <= wire_w_man_round_wi_range519w(0) AND wire_w_man_result_all_ones_range518w(0);
wire_w_lg_w_man_round_wi_range465w466w(0) <= wire_w_man_round_wi_range465w(0) AND wire_w_man_result_all_ones_range463w(0);
wire_w_lg_w_man_round_wi_range522w523w(0) <= wire_w_man_round_wi_range522w(0) AND wire_w_man_result_all_ones_range521w(0);
wire_w_lg_w_man_round_wi_range525w526w(0) <= wire_w_man_round_wi_range525w(0) AND wire_w_man_result_all_ones_range524w(0);
wire_w_lg_w_man_round_wi_range528w529w(0) <= wire_w_man_round_wi_range528w(0) AND wire_w_man_result_all_ones_range527w(0);
wire_w_lg_w_man_round_wi_range468w469w(0) <= wire_w_man_round_wi_range468w(0) AND wire_w_man_result_all_ones_range467w(0);
wire_w_lg_w_man_round_wi_range471w472w(0) <= wire_w_man_round_wi_range471w(0) AND wire_w_man_result_all_ones_range470w(0);
wire_w_lg_w_man_round_wi_range474w475w(0) <= wire_w_man_round_wi_range474w(0) AND wire_w_man_result_all_ones_range473w(0);
wire_w_lg_w_man_round_wi_range477w478w(0) <= wire_w_man_round_wi_range477w(0) AND wire_w_man_result_all_ones_range476w(0);
wire_w_lg_w_man_round_wi_range480w481w(0) <= wire_w_man_round_wi_range480w(0) AND wire_w_man_result_all_ones_range479w(0);
wire_w_lg_w_man_round_wi_range483w484w(0) <= wire_w_man_round_wi_range483w(0) AND wire_w_man_result_all_ones_range482w(0);
wire_w_lg_w_man_round_wi_range486w487w(0) <= wire_w_man_round_wi_range486w(0) AND wire_w_man_result_all_ones_range485w(0);
wire_w_lg_w_man_round_wi_range489w490w(0) <= wire_w_man_round_wi_range489w(0) AND wire_w_man_result_all_ones_range488w(0);
wire_w_lg_w_lg_w_lg_underflow_w554w555w556w(0) <= NOT wire_w_lg_w_lg_underflow_w554w555w(0);
wire_w_lg_barrel_shifter_underflow553w(0) <= NOT barrel_shifter_underflow;
wire_w_lg_input_is_infinity_wo443w(0) <= NOT input_is_infinity_wo;
wire_w_lg_input_is_nan_wo442w(0) <= NOT input_is_nan_wo;
wire_w_lg_input_is_zero_wo444w(0) <= NOT input_is_zero_wo;
wire_w_lg_underflow_w454w(0) <= NOT underflow_w;
wire_w_lg_w_man_data_not_zero_w_range116w118w(0) <= NOT wire_w_man_data_not_zero_w_range116w(0);
wire_w_lg_w_man_prod_wo_range402w406w(0) <= NOT wire_w_man_prod_wo_range402w(0);
wire_w_lg_w_lg_underflow_w554w555w(0) <= wire_w_lg_underflow_w554w(0) OR negative_infinity;
wire_w_lg_w551w552w(0) <= wire_w551w(0) OR positive_infinity;
wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w(0) <= wire_w_lg_w_lg_w_lg_overflow_w536w537w538w(0) OR input_is_infinity_wo;
wire_w551w(0) <= wire_w_lg_w_lg_barrel_shifter_underflow549w550w(0) OR nan_w;
wire_w_lg_w_lg_w_lg_overflow_w536w537w538w(0) <= wire_w_lg_w_lg_overflow_w536w537w(0) OR input_is_zero_wo;
wire_w_lg_w_lg_barrel_shifter_underflow549w550w(0) <= wire_w_lg_barrel_shifter_underflow549w(0) OR input_is_zero_wo;
wire_w_lg_w_lg_overflow_w542w543w(0) <= wire_w_lg_overflow_w542w(0) OR positive_infinity;
wire_w_lg_w_lg_overflow_w536w537w(0) <= wire_w_lg_overflow_w536w(0) OR nan_w;
wire_w_lg_barrel_shifter_underflow549w(0) <= barrel_shifter_underflow OR overflow_w;
wire_w_lg_distance_overflow447w(0) <= distance_overflow OR wire_exp_value_add_bias_w_lg_w_result_range445w446w(0);
wire_w_lg_distance_overflow456w(0) <= distance_overflow OR wire_exp_value_add_bias_w_result_range445w(0);
wire_w_lg_overflow_w542w(0) <= overflow_w OR nan_w;
wire_w_lg_overflow_w536w(0) <= overflow_w OR underflow_w;
wire_w_lg_w_data_range78w79w(0) <= wire_w_data_range78w(0) OR wire_w_man_data_not_zero_w_range77w(0);
wire_w_lg_w_data_range81w82w(0) <= wire_w_data_range81w(0) OR wire_w_man_data_not_zero_w_range80w(0);
wire_w_lg_w_data_range84w85w(0) <= wire_w_data_range84w(0) OR wire_w_man_data_not_zero_w_range83w(0);
wire_w_lg_w_data_range87w88w(0) <= wire_w_data_range87w(0) OR wire_w_man_data_not_zero_w_range86w(0);
wire_w_lg_w_data_range90w91w(0) <= wire_w_data_range90w(0) OR wire_w_man_data_not_zero_w_range89w(0);
wire_w_lg_w_data_range93w94w(0) <= wire_w_data_range93w(0) OR wire_w_man_data_not_zero_w_range92w(0);
wire_w_lg_w_data_range96w97w(0) <= wire_w_data_range96w(0) OR wire_w_man_data_not_zero_w_range95w(0);
wire_w_lg_w_data_range99w100w(0) <= wire_w_data_range99w(0) OR wire_w_man_data_not_zero_w_range98w(0);
wire_w_lg_w_data_range102w103w(0) <= wire_w_data_range102w(0) OR wire_w_man_data_not_zero_w_range101w(0);
wire_w_lg_w_data_range105w106w(0) <= wire_w_data_range105w(0) OR wire_w_man_data_not_zero_w_range104w(0);
wire_w_lg_w_data_range51w52w(0) <= wire_w_data_range51w(0) OR wire_w_man_data_not_zero_w_range49w(0);
wire_w_lg_w_data_range108w109w(0) <= wire_w_data_range108w(0) OR wire_w_man_data_not_zero_w_range107w(0);
wire_w_lg_w_data_range111w112w(0) <= wire_w_data_range111w(0) OR wire_w_man_data_not_zero_w_range110w(0);
wire_w_lg_w_data_range114w115w(0) <= wire_w_data_range114w(0) OR wire_w_man_data_not_zero_w_range113w(0);
wire_w_lg_w_data_range10w11w(0) <= wire_w_data_range10w(0) OR wire_w_exp_data_not_zero_w_range8w(0);
wire_w_lg_w_data_range13w14w(0) <= wire_w_data_range13w(0) OR wire_w_exp_data_not_zero_w_range12w(0);
wire_w_lg_w_data_range16w17w(0) <= wire_w_data_range16w(0) OR wire_w_exp_data_not_zero_w_range15w(0);
wire_w_lg_w_data_range19w20w(0) <= wire_w_data_range19w(0) OR wire_w_exp_data_not_zero_w_range18w(0);
wire_w_lg_w_data_range22w23w(0) <= wire_w_data_range22w(0) OR wire_w_exp_data_not_zero_w_range21w(0);
wire_w_lg_w_data_range25w26w(0) <= wire_w_data_range25w(0) OR wire_w_exp_data_not_zero_w_range24w(0);
wire_w_lg_w_data_range54w55w(0) <= wire_w_data_range54w(0) OR wire_w_man_data_not_zero_w_range53w(0);
wire_w_lg_w_data_range28w29w(0) <= wire_w_data_range28w(0) OR wire_w_exp_data_not_zero_w_range27w(0);
wire_w_lg_w_data_range57w58w(0) <= wire_w_data_range57w(0) OR wire_w_man_data_not_zero_w_range56w(0);
wire_w_lg_w_data_range60w61w(0) <= wire_w_data_range60w(0) OR wire_w_man_data_not_zero_w_range59w(0);
wire_w_lg_w_data_range63w64w(0) <= wire_w_data_range63w(0) OR wire_w_man_data_not_zero_w_range62w(0);
wire_w_lg_w_data_range66w67w(0) <= wire_w_data_range66w(0) OR wire_w_man_data_not_zero_w_range65w(0);
wire_w_lg_w_data_range69w70w(0) <= wire_w_data_range69w(0) OR wire_w_man_data_not_zero_w_range68w(0);
wire_w_lg_w_data_range72w73w(0) <= wire_w_data_range72w(0) OR wire_w_man_data_not_zero_w_range71w(0);
wire_w_lg_w_data_range75w76w(0) <= wire_w_data_range75w(0) OR wire_w_man_data_not_zero_w_range74w(0);
wire_w_lg_w_exp_result_w_range563w566w(0) <= wire_w_exp_result_w_range563w(0) OR wire_w_exp_out_not_zero_w_range561w(0);
wire_w_lg_w_exp_result_w_range568w571w(0) <= wire_w_exp_result_w_range568w(0) OR wire_w_exp_out_not_zero_w_range567w(0);
wire_w_lg_w_exp_result_w_range573w576w(0) <= wire_w_exp_result_w_range573w(0) OR wire_w_exp_out_not_zero_w_range572w(0);
wire_w_lg_w_exp_result_w_range578w581w(0) <= wire_w_exp_result_w_range578w(0) OR wire_w_exp_out_not_zero_w_range577w(0);
wire_w_lg_w_exp_result_w_range583w586w(0) <= wire_w_exp_result_w_range583w(0) OR wire_w_exp_out_not_zero_w_range582w(0);
wire_w_lg_w_exp_result_w_range588w591w(0) <= wire_w_exp_result_w_range588w(0) OR wire_w_exp_out_not_zero_w_range587w(0);
wire_w_lg_w_exp_result_w_range593w595w(0) <= wire_w_exp_result_w_range593w(0) OR wire_w_exp_out_not_zero_w_range592w(0);
wire_w_lg_w_man_prod_result_range424w425w(0) <= wire_w_man_prod_result_range424w(0) OR wire_w_sticky_bits_range423w(0);
wire_w_lg_w_man_prod_result_range421w422w(0) <= wire_w_man_prod_result_range421w(0) OR wire_w_sticky_bits_range420w(0);
wire_w_lg_w_man_prod_result_range418w419w(0) <= wire_w_man_prod_result_range418w(0) OR wire_w_sticky_bits_range417w(0);
wire_w_lg_w_man_prod_result_range415w416w(0) <= wire_w_man_prod_result_range415w(0) OR wire_w_sticky_bits_range413w(0);
addr_val_more_than_one <= "10111";
barrel_shifter_data <= ( "00000000" & "1" & fraction_wo & "000000");
barrel_shifter_distance <= wire_exp_value_selecta_dataout;
barrel_shifter_underflow <= barrel_shifter_underflow_dffe2_15_pipes14;
barrel_shifter_underflow_wi <= (wire_underflow_compare_agb AND exp_value_wo(8));
distance_overflow <= distance_overflow_dffe2_15_pipes14;
distance_overflow_val_w <= "00000110";
distance_overflow_wi <= (wire_distance_overflow_comp_agb AND (NOT exp_value_wo(8)));
exp_bias <= "01111111";
exp_bias_all_ones_w <= (OTHERS => '1');
exp_data_all_one_w <= ( wire_w_lg_w_data_range28w46w & wire_w_lg_w_data_range25w44w & wire_w_lg_w_data_range22w42w & wire_w_lg_w_data_range19w40w & wire_w_lg_w_data_range16w38w & wire_w_lg_w_data_range13w36w & wire_w_lg_w_data_range10w34w & data(23));
exp_data_not_zero_w <= ( wire_w_lg_w_data_range28w29w & wire_w_lg_w_data_range25w26w & wire_w_lg_w_data_range22w23w & wire_w_lg_w_data_range19w20w & wire_w_lg_w_data_range16w17w & wire_w_lg_w_data_range13w14w & wire_w_lg_w_data_range10w11w & data(23));
exp_invert <= (xi_exp_value XOR exp_bias_all_ones_w);
exp_one <= ( wire_w_lg_w_lg_overflow_w542w543w & "1111111");
exp_out_all_one_w <= ( wire_w_lg_w_exp_result_w_range593w594w & wire_w_lg_w_exp_result_w_range588w589w & wire_w_lg_w_exp_result_w_range583w584w & wire_w_lg_w_exp_result_w_range578w579w & wire_w_lg_w_exp_result_w_range573w574w & wire_w_lg_w_exp_result_w_range568w569w & wire_w_lg_w_exp_result_w_range563w564w & exp_result_w(0));
exp_out_not_zero_w <= ( wire_w_lg_w_exp_result_w_range593w595w & wire_w_lg_w_exp_result_w_range588w591w & wire_w_lg_w_exp_result_w_range583w586w & wire_w_lg_w_exp_result_w_range578w581w & wire_w_lg_w_exp_result_w_range573w576w & wire_w_lg_w_exp_result_w_range568w571w & wire_w_lg_w_exp_result_w_range563w566w & exp_result_w(0));
exp_result_out <= wire_exp_result_mux_prea_w_lg_dataout557w;
exp_result_w <= wire_exp_value_man_over_result(7 DOWNTO 0);
exp_value <= wire_exp_minus_bias_result;
exp_value_wi <= exp_value;
exp_value_wo <= exp_value_dffe1;
exp_w <= data(30 DOWNTO 23);
extra_ln2 <= ((NOT xf_pre(37)) AND sign_dffe8);
fraction <= ( data(22 DOWNTO 0));
fraction_wi <= fraction;
fraction_wo <= fraction_dffe1;
gnd_w <= '0';
guard_bit <= man_prod_result(35);
input_is_infinity_wi <= wire_w_lg_w_exp_data_all_one_w_range47w119w(0);
input_is_infinity_wo <= input_is_infinity_16_pipes15;
input_is_nan_wi <= (exp_data_all_one_w(7) AND man_data_not_zero_w(22));
input_is_nan_wo <= input_is_nan_16_pipes15;
input_is_zero_wi <= (NOT exp_data_not_zero_w(7));
input_is_zero_wo <= input_is_zero_16_pipes15;
ln2_w <= "10110001011100100001011111110111110100";
man_data_not_zero_w <= ( wire_w_lg_w_data_range114w115w & wire_w_lg_w_data_range111w112w & wire_w_lg_w_data_range108w109w & wire_w_lg_w_data_range105w106w & wire_w_lg_w_data_range102w103w & wire_w_lg_w_data_range99w100w & wire_w_lg_w_data_range96w97w & wire_w_lg_w_data_range93w94w & wire_w_lg_w_data_range90w91w & wire_w_lg_w_data_range87w88w & wire_w_lg_w_data_range84w85w & wire_w_lg_w_data_range81w82w & wire_w_lg_w_data_range78w79w & wire_w_lg_w_data_range75w76w & wire_w_lg_w_data_range72w73w & wire_w_lg_w_data_range69w70w & wire_w_lg_w_data_range66w67w & wire_w_lg_w_data_range63w64w & wire_w_lg_w_data_range60w61w & wire_w_lg_w_data_range57w58w & wire_w_lg_w_data_range54w55w & wire_w_lg_w_data_range51w52w & data(0));
man_overflow <= (round_up AND man_result_all_ones(22));
man_overflow_wi <= man_overflow;
man_overflow_wo <= man_overflow_dffe15;
man_prod_result <= (wire_w_lg_man_prod_shifted408w OR wire_w_lg_man_prod_wire407w);
man_prod_shifted <= ( gnd_w & man_prod_wo(61 DOWNTO 1));
man_prod_wi <= wire_man_prod_result;
man_prod_wire <= man_prod_wo;
man_prod_wo <= man_prod_dffe14;
man_result_all_ones <= ( wire_w_lg_w_man_round_wi_range528w529w & wire_w_lg_w_man_round_wi_range525w526w & wire_w_lg_w_man_round_wi_range522w523w & wire_w_lg_w_man_round_wi_range519w520w & wire_w_lg_w_man_round_wi_range516w517w & wire_w_lg_w_man_round_wi_range513w514w & wire_w_lg_w_man_round_wi_range510w511w & wire_w_lg_w_man_round_wi_range507w508w & wire_w_lg_w_man_round_wi_range504w505w & wire_w_lg_w_man_round_wi_range501w502w & wire_w_lg_w_man_round_wi_range498w499w & wire_w_lg_w_man_round_wi_range495w496w & wire_w_lg_w_man_round_wi_range492w493w & wire_w_lg_w_man_round_wi_range489w490w & wire_w_lg_w_man_round_wi_range486w487w & wire_w_lg_w_man_round_wi_range483w484w & wire_w_lg_w_man_round_wi_range480w481w & wire_w_lg_w_man_round_wi_range477w478w & wire_w_lg_w_man_round_wi_range474w475w & wire_w_lg_w_man_round_wi_range471w472w & wire_w_lg_w_man_round_wi_range468w469w & wire_w_lg_w_man_round_wi_range465w466w & man_round_wi(0));
man_result_w <= wire_man_result_muxa_dataout;
man_round_wi <= man_prod_result(57 DOWNTO 35);
man_round_wo <= man_round_dffe15;
nan_w <= input_is_nan_wo;
negative_infinity <= (sign_dffe15 AND input_is_infinity_wo);
one_over_ln2_w <= "101110001";
overflow_w <= (((wire_sign_dffe_w_lg_q434w(0) AND ((wire_w_lg_distance_overflow456w(0) OR exp_out_all_one_w(7)) OR wire_exp_value_man_over_result(8))) AND wire_w_lg_underflow_w454w(0)) AND wire_w_lg_input_is_nan_wo442w(0));
positive_infinity <= (wire_sign_dffe_w_lg_q434w(0) AND input_is_infinity_wo);
result <= ( "0" & result_pipe_wo);
result_pipe_wi <= ( exp_result_out & man_result_w);
result_pipe_wo <= result_pipe_dffe16;
result_underflow_w <= ((NOT exp_out_not_zero_w(7)) AND wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range435w436w437w438w(0));
round_bit <= man_prod_result(34);
round_up <= (round_bit AND (guard_bit OR sticky_bits(4)));
round_up_wi <= round_up;
round_up_wo <= round_up_dffe15;
shifted_value <= (tbl1_compare_wo OR man_prod_wo(59));
sign_w <= data(31);
sticky_bits <= ( wire_w_lg_w_man_prod_result_range424w425w & wire_w_lg_w_man_prod_result_range421w422w & wire_w_lg_w_man_prod_result_range418w419w & wire_w_lg_w_man_prod_result_range415w416w & man_prod_result(33));
table_one_data <= ( "10101000100111100001011100110110" & "10100011011011100000001001111010" & "10011110011001101100101000011001" & "10011001100001110010110000111101" & "10010100110011011111000011111001" & "10010000001110011110100111111000" & "10001011110010011111001000110010" & "10000111011111001110110110100011" & "10000011010100011100100100000011" & "11111110100011101111001100001100" & "11110110101110011111100100100000" & "11101111001000101010111011111100" & "11100111110001110010111011000010" & "11100000101001011010000110001001" & "11011001101111000011111011100100" & "11010011000010010100110001110000" & "11001100100010110001110101101010" & "11000110010000000001001000111011" & "11000000001001101001100000011010" & "10111010001111010010100010011110" & "10110100100000100100100101100101" & "10101110111101001000101110110000" & "10101001100100101000110000000110" & "10100100010110101111000111100001" & "10011111010011000110111101010101" & "10011010011001011100000010111000" & "10010101101001011010110001011001" & "10010001000010110000001000101101" & "10001100100101001001101110000011" & "10001000010000010101101010111011" & "10000100000100000010101100000000" & "10000000000000000000000000000000");
table_one_out <= wire_table_one_result;
table_three_data <= ( "111110000001111000001" & "111100000001110000100" & "111010000001101001001" & "111000000001100010000" & "110110000001011011001" & "110100000001010100100" & "110010000001001110001" & "110000000001001000000" & "101110000001000010001" & "101100000000111100100" & "101010000000110111001" & "101000000000110010000" & "100110000000101101001" & "100100000000101000100" & "100010000000100100001" & "100000000000100000000" & "011110000000011100001" & "011100000000011000100" & "011010000000010101001" & "011000000000010010000" & "010110000000001111001" & "010100000000001100100" & "010010000000001010001" & "010000000000001000000" & "001110000000000110001" & "001100000000000100100" & "001010000000000011001" & "001000000000000010000" & "000110000000000001001" & "000100000000000000100" & "000010000000000000001" & "000000000000000000000");
table_three_out <= ( "1" & "0000000000" & table_three_out_tmp);
table_three_out_tmp <= wire_table_three_result;
table_two_data <= ( "11111011110010101100010101" & "11110011100011001101101010" & "11101011010100001111111011" & "11100011000101110011000111" & "11011010110111110111001100" & "11010010101010011100001000" & "11001010011101100001111000" & "11000010010001001000011011" & "10111010000101001111101110" & "10110001111001110111110000" & "10101001101111000000011110" & "10100001100100101001110111" & "10011001011010110011111000" & "10010001010001011110100000" & "10001001001000101001101100" & "10000001000000010101011010" & "01111000111000100001101001" & "01110000110001001110010101" & "01101000101010011011011110" & "01100000100100001001000001" & "01011000011110010110111100" & "01010000011001000101001110" & "01001000010100010011110011" & "01000000010000000010101011" & "00111000001100010001110010" & "00110000001001000001001000" & "00101000000110010000101001" & "00100000000100000000010101" & "00011000000010010000001001" & "00010000000001000000000010" & "00001000000000010000000000" & "00000000000000000000000000");
table_two_out <= ( "1" & "00000" & table_two_out_tmp);
table_two_out_tmp <= wire_table_two_result;
tbl1_compare_wi <= wire_tbl1_compare_ageb;
tbl1_compare_wo <= tbl1_compare_dffe11_4_pipes3;
tbl1_tbl2_prod_wi <= wire_tbl1_tbl2_prod_result(63 DOWNTO 33);
tbl1_tbl2_prod_wo <= tbl1_tbl2_prod_dffe12;
tbl3_taylor_prod_wi <= wire_tbl3_taylor_prod_result(61 DOWNTO 31);
tbl3_taylor_prod_wo <= tbl3_taylor_prod_dffe12;
underflow_compare_val_w <= "00011101";
underflow_w <= (((((result_underflow_w OR barrel_shifter_underflow) OR wire_sign_dffe_w_lg_q448w(0)) AND wire_w_lg_input_is_zero_wo444w(0)) AND wire_w_lg_input_is_infinity_wo443w(0)) AND wire_w_lg_input_is_nan_wo442w(0));
x_fixed <= wire_rbarrel_shift_result;
xf <= wire_xf_muxa_dataout;
xf_pre <= wire_x_fixed_minus_xiln2_result;
xf_pre_2_wi <= xf_pre_wo;
xf_pre_2_wo <= xf_pre_2_dffe10;
xf_pre_wi <= xf_pre;
xf_pre_wo <= xf_pre_dffe9;
xi_exp_value <= xi_prod_wo(18 DOWNTO 11);
xi_exp_value_wi <= xi_exp_value;
xi_exp_value_wo <= xi_exp_value_dffe4;
xi_ln2_prod_wi <= wire_xi_ln2_prod_result;
xi_ln2_prod_wo <= xi_ln2_prod_dffe7;
xi_prod_wi <= wire_xi_prod_result;
xi_prod_wo <= xi_prod_dffe3;
wire_w_data_range78w(0) <= data(10);
wire_w_data_range81w(0) <= data(11);
wire_w_data_range84w(0) <= data(12);
wire_w_data_range87w(0) <= data(13);
wire_w_data_range90w(0) <= data(14);
wire_w_data_range93w(0) <= data(15);
wire_w_data_range96w(0) <= data(16);
wire_w_data_range99w(0) <= data(17);
wire_w_data_range102w(0) <= data(18);
wire_w_data_range105w(0) <= data(19);
wire_w_data_range51w(0) <= data(1);
wire_w_data_range108w(0) <= data(20);
wire_w_data_range111w(0) <= data(21);
wire_w_data_range114w(0) <= data(22);
wire_w_data_range10w(0) <= data(24);
wire_w_data_range13w(0) <= data(25);
wire_w_data_range16w(0) <= data(26);
wire_w_data_range19w(0) <= data(27);
wire_w_data_range22w(0) <= data(28);
wire_w_data_range25w(0) <= data(29);
wire_w_data_range54w(0) <= data(2);
wire_w_data_range28w(0) <= data(30);
wire_w_data_range57w(0) <= data(3);
wire_w_data_range60w(0) <= data(4);
wire_w_data_range63w(0) <= data(5);
wire_w_data_range66w(0) <= data(6);
wire_w_data_range69w(0) <= data(7);
wire_w_data_range72w(0) <= data(8);
wire_w_data_range75w(0) <= data(9);
wire_w_exp_data_all_one_w_range32w(0) <= exp_data_all_one_w(0);
wire_w_exp_data_all_one_w_range35w(0) <= exp_data_all_one_w(1);
wire_w_exp_data_all_one_w_range37w(0) <= exp_data_all_one_w(2);
wire_w_exp_data_all_one_w_range39w(0) <= exp_data_all_one_w(3);
wire_w_exp_data_all_one_w_range41w(0) <= exp_data_all_one_w(4);
wire_w_exp_data_all_one_w_range43w(0) <= exp_data_all_one_w(5);
wire_w_exp_data_all_one_w_range45w(0) <= exp_data_all_one_w(6);
wire_w_exp_data_all_one_w_range47w(0) <= exp_data_all_one_w(7);
wire_w_exp_data_not_zero_w_range8w(0) <= exp_data_not_zero_w(0);
wire_w_exp_data_not_zero_w_range12w(0) <= exp_data_not_zero_w(1);
wire_w_exp_data_not_zero_w_range15w(0) <= exp_data_not_zero_w(2);
wire_w_exp_data_not_zero_w_range18w(0) <= exp_data_not_zero_w(3);
wire_w_exp_data_not_zero_w_range21w(0) <= exp_data_not_zero_w(4);
wire_w_exp_data_not_zero_w_range24w(0) <= exp_data_not_zero_w(5);
wire_w_exp_data_not_zero_w_range27w(0) <= exp_data_not_zero_w(6);
wire_w_exp_out_all_one_w_range559w(0) <= exp_out_all_one_w(0);
wire_w_exp_out_all_one_w_range565w(0) <= exp_out_all_one_w(1);
wire_w_exp_out_all_one_w_range570w(0) <= exp_out_all_one_w(2);
wire_w_exp_out_all_one_w_range575w(0) <= exp_out_all_one_w(3);
wire_w_exp_out_all_one_w_range580w(0) <= exp_out_all_one_w(4);
wire_w_exp_out_all_one_w_range585w(0) <= exp_out_all_one_w(5);
wire_w_exp_out_all_one_w_range590w(0) <= exp_out_all_one_w(6);
wire_w_exp_out_not_zero_w_range561w(0) <= exp_out_not_zero_w(0);
wire_w_exp_out_not_zero_w_range567w(0) <= exp_out_not_zero_w(1);
wire_w_exp_out_not_zero_w_range572w(0) <= exp_out_not_zero_w(2);
wire_w_exp_out_not_zero_w_range577w(0) <= exp_out_not_zero_w(3);
wire_w_exp_out_not_zero_w_range582w(0) <= exp_out_not_zero_w(4);
wire_w_exp_out_not_zero_w_range587w(0) <= exp_out_not_zero_w(5);
wire_w_exp_out_not_zero_w_range592w(0) <= exp_out_not_zero_w(6);
wire_w_exp_result_w_range563w(0) <= exp_result_w(1);
wire_w_exp_result_w_range568w(0) <= exp_result_w(2);
wire_w_exp_result_w_range573w(0) <= exp_result_w(3);
wire_w_exp_result_w_range578w(0) <= exp_result_w(4);
wire_w_exp_result_w_range583w(0) <= exp_result_w(5);
wire_w_exp_result_w_range588w(0) <= exp_result_w(6);
wire_w_exp_result_w_range593w(0) <= exp_result_w(7);
wire_w_exp_value_wo_range129w <= exp_value_wo(5 DOWNTO 0);
wire_w_exp_value_wo_range132w <= exp_value_wo(7 DOWNTO 0);
wire_w_exp_value_wo_range131w(0) <= exp_value_wo(8);
wire_w_man_data_not_zero_w_range49w(0) <= man_data_not_zero_w(0);
wire_w_man_data_not_zero_w_range80w(0) <= man_data_not_zero_w(10);
wire_w_man_data_not_zero_w_range83w(0) <= man_data_not_zero_w(11);
wire_w_man_data_not_zero_w_range86w(0) <= man_data_not_zero_w(12);
wire_w_man_data_not_zero_w_range89w(0) <= man_data_not_zero_w(13);
wire_w_man_data_not_zero_w_range92w(0) <= man_data_not_zero_w(14);
wire_w_man_data_not_zero_w_range95w(0) <= man_data_not_zero_w(15);
wire_w_man_data_not_zero_w_range98w(0) <= man_data_not_zero_w(16);
wire_w_man_data_not_zero_w_range101w(0) <= man_data_not_zero_w(17);
wire_w_man_data_not_zero_w_range104w(0) <= man_data_not_zero_w(18);
wire_w_man_data_not_zero_w_range107w(0) <= man_data_not_zero_w(19);
wire_w_man_data_not_zero_w_range53w(0) <= man_data_not_zero_w(1);
wire_w_man_data_not_zero_w_range110w(0) <= man_data_not_zero_w(20);
wire_w_man_data_not_zero_w_range113w(0) <= man_data_not_zero_w(21);
wire_w_man_data_not_zero_w_range116w(0) <= man_data_not_zero_w(22);
wire_w_man_data_not_zero_w_range56w(0) <= man_data_not_zero_w(2);
wire_w_man_data_not_zero_w_range59w(0) <= man_data_not_zero_w(3);
wire_w_man_data_not_zero_w_range62w(0) <= man_data_not_zero_w(4);
wire_w_man_data_not_zero_w_range65w(0) <= man_data_not_zero_w(5);
wire_w_man_data_not_zero_w_range68w(0) <= man_data_not_zero_w(6);
wire_w_man_data_not_zero_w_range71w(0) <= man_data_not_zero_w(7);
wire_w_man_data_not_zero_w_range74w(0) <= man_data_not_zero_w(8);
wire_w_man_data_not_zero_w_range77w(0) <= man_data_not_zero_w(9);
wire_w_man_prod_result_range424w(0) <= man_prod_result(29);
wire_w_man_prod_result_range421w(0) <= man_prod_result(30);
wire_w_man_prod_result_range418w(0) <= man_prod_result(31);
wire_w_man_prod_result_range415w(0) <= man_prod_result(32);
wire_w_man_prod_wo_range402w(0) <= man_prod_wo(59);
wire_w_man_result_all_ones_range463w(0) <= man_result_all_ones(0);
wire_w_man_result_all_ones_range494w(0) <= man_result_all_ones(10);
wire_w_man_result_all_ones_range497w(0) <= man_result_all_ones(11);
wire_w_man_result_all_ones_range500w(0) <= man_result_all_ones(12);
wire_w_man_result_all_ones_range503w(0) <= man_result_all_ones(13);
wire_w_man_result_all_ones_range506w(0) <= man_result_all_ones(14);
wire_w_man_result_all_ones_range509w(0) <= man_result_all_ones(15);
wire_w_man_result_all_ones_range512w(0) <= man_result_all_ones(16);
wire_w_man_result_all_ones_range515w(0) <= man_result_all_ones(17);
wire_w_man_result_all_ones_range518w(0) <= man_result_all_ones(18);
wire_w_man_result_all_ones_range521w(0) <= man_result_all_ones(19);
wire_w_man_result_all_ones_range467w(0) <= man_result_all_ones(1);
wire_w_man_result_all_ones_range524w(0) <= man_result_all_ones(20);
wire_w_man_result_all_ones_range527w(0) <= man_result_all_ones(21);
wire_w_man_result_all_ones_range470w(0) <= man_result_all_ones(2);
wire_w_man_result_all_ones_range473w(0) <= man_result_all_ones(3);
wire_w_man_result_all_ones_range476w(0) <= man_result_all_ones(4);
wire_w_man_result_all_ones_range479w(0) <= man_result_all_ones(5);
wire_w_man_result_all_ones_range482w(0) <= man_result_all_ones(6);
wire_w_man_result_all_ones_range485w(0) <= man_result_all_ones(7);
wire_w_man_result_all_ones_range488w(0) <= man_result_all_ones(8);
wire_w_man_result_all_ones_range491w(0) <= man_result_all_ones(9);
wire_w_man_round_wi_range492w(0) <= man_round_wi(10);
wire_w_man_round_wi_range495w(0) <= man_round_wi(11);
wire_w_man_round_wi_range498w(0) <= man_round_wi(12);
wire_w_man_round_wi_range501w(0) <= man_round_wi(13);
wire_w_man_round_wi_range504w(0) <= man_round_wi(14);
wire_w_man_round_wi_range507w(0) <= man_round_wi(15);
wire_w_man_round_wi_range510w(0) <= man_round_wi(16);
wire_w_man_round_wi_range513w(0) <= man_round_wi(17);
wire_w_man_round_wi_range516w(0) <= man_round_wi(18);
wire_w_man_round_wi_range519w(0) <= man_round_wi(19);
wire_w_man_round_wi_range465w(0) <= man_round_wi(1);
wire_w_man_round_wi_range522w(0) <= man_round_wi(20);
wire_w_man_round_wi_range525w(0) <= man_round_wi(21);
wire_w_man_round_wi_range528w(0) <= man_round_wi(22);
wire_w_man_round_wi_range468w(0) <= man_round_wi(2);
wire_w_man_round_wi_range471w(0) <= man_round_wi(3);
wire_w_man_round_wi_range474w(0) <= man_round_wi(4);
wire_w_man_round_wi_range477w(0) <= man_round_wi(5);
wire_w_man_round_wi_range480w(0) <= man_round_wi(6);
wire_w_man_round_wi_range483w(0) <= man_round_wi(7);
wire_w_man_round_wi_range486w(0) <= man_round_wi(8);
wire_w_man_round_wi_range489w(0) <= man_round_wi(9);
wire_w_sticky_bits_range413w(0) <= sticky_bits(0);
wire_w_sticky_bits_range417w(0) <= sticky_bits(1);
wire_w_sticky_bits_range420w(0) <= sticky_bits(2);
wire_w_sticky_bits_range423w(0) <= sticky_bits(3);
wire_w_xf_pre_2_wo_range183w <= xf_pre_2_wo(30 DOWNTO 0);
wire_w_xf_pre_wo_range177w <= xf_pre_wo(30 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes0 <= barrel_shifter_underflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes1 <= barrel_shifter_underflow_dffe2_15_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes2 <= barrel_shifter_underflow_dffe2_15_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes3 <= barrel_shifter_underflow_dffe2_15_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes4 <= barrel_shifter_underflow_dffe2_15_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes5 <= barrel_shifter_underflow_dffe2_15_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes6 <= barrel_shifter_underflow_dffe2_15_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes7 <= barrel_shifter_underflow_dffe2_15_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes8 <= barrel_shifter_underflow_dffe2_15_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes9 <= barrel_shifter_underflow_dffe2_15_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes10 <= barrel_shifter_underflow_dffe2_15_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes11 <= barrel_shifter_underflow_dffe2_15_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes12 <= barrel_shifter_underflow_dffe2_15_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes13 <= barrel_shifter_underflow_dffe2_15_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes14 <= barrel_shifter_underflow_dffe2_15_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes0 <= distance_overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes1 <= distance_overflow_dffe2_15_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes2 <= distance_overflow_dffe2_15_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes3 <= distance_overflow_dffe2_15_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes4 <= distance_overflow_dffe2_15_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes5 <= distance_overflow_dffe2_15_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes6 <= distance_overflow_dffe2_15_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes7 <= distance_overflow_dffe2_15_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes8 <= distance_overflow_dffe2_15_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes9 <= distance_overflow_dffe2_15_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes10 <= distance_overflow_dffe2_15_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes11 <= distance_overflow_dffe2_15_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes12 <= distance_overflow_dffe2_15_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes13 <= distance_overflow_dffe2_15_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes14 <= distance_overflow_dffe2_15_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_0 <= wire_exp_value_b4_biasa_dataout;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_1 <= exp_value_b4_bias_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_10 <= exp_value_b4_bias_dffe_9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_2 <= exp_value_b4_bias_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_3 <= exp_value_b4_bias_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_4 <= exp_value_b4_bias_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_5 <= exp_value_b4_bias_dffe_4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_6 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_6 <= exp_value_b4_bias_dffe_5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_7 <= exp_value_b4_bias_dffe_6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_8 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_8 <= exp_value_b4_bias_dffe_7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_9 <= exp_value_b4_bias_dffe_8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_dffe1 <= exp_value_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_0 <= extra_ln2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_1 <= extra_ln2_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_2 <= extra_ln2_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_3 <= extra_ln2_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_4 <= extra_ln2_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_5 <= extra_ln2_dffe_4;
END IF;
END IF;
END PROCESS;
wire_extra_ln2_dffe_5_w_lg_q157w(0) <= NOT extra_ln2_dffe_5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN fraction_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN fraction_dffe1 <= fraction_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes0 <= input_is_infinity_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes1 <= input_is_infinity_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes2 <= input_is_infinity_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes3 <= input_is_infinity_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes4 <= input_is_infinity_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes5 <= input_is_infinity_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes6 <= input_is_infinity_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes7 <= input_is_infinity_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes8 <= input_is_infinity_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes9 <= input_is_infinity_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes10 <= input_is_infinity_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes11 <= input_is_infinity_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes12 <= input_is_infinity_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes13 <= input_is_infinity_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes14 <= input_is_infinity_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes15 <= input_is_infinity_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes0 <= input_is_nan_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes1 <= input_is_nan_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes2 <= input_is_nan_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes3 <= input_is_nan_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes4 <= input_is_nan_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes5 <= input_is_nan_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes6 <= input_is_nan_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes7 <= input_is_nan_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes8 <= input_is_nan_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes9 <= input_is_nan_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes10 <= input_is_nan_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes11 <= input_is_nan_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes12 <= input_is_nan_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes13 <= input_is_nan_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes14 <= input_is_nan_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes15 <= input_is_nan_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes0 <= input_is_zero_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes1 <= input_is_zero_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes2 <= input_is_zero_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes3 <= input_is_zero_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes4 <= input_is_zero_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes5 <= input_is_zero_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes6 <= input_is_zero_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes7 <= input_is_zero_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes8 <= input_is_zero_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes9 <= input_is_zero_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes10 <= input_is_zero_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes11 <= input_is_zero_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes12 <= input_is_zero_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes13 <= input_is_zero_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes14 <= input_is_zero_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes15 <= input_is_zero_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_overflow_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_overflow_dffe15 <= man_overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_prod_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_prod_dffe14 <= man_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_dffe15 <= man_round_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN result_pipe_dffe16 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN result_pipe_dffe16 <= result_pipe_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_up_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_up_dffe15 <= round_up_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe0 <= sign_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe1 <= sign_dffe0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe2 <= sign_dffe1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe3 <= sign_dffe2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe4 <= sign_dffe3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe5 <= sign_dffe4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe6 <= sign_dffe5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe7 <= sign_dffe6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe8 <= sign_dffe7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe9 <= sign_dffe8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe10 <= sign_dffe9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe11 <= sign_dffe10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe12 <= sign_dffe11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe13 <= sign_dffe12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe14 <= sign_dffe13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe15 <= sign_dffe14;
END IF;
END IF;
END PROCESS;
wire_sign_dffe_w_lg_q448w(0) <= sign_dffe15 AND wire_w_lg_distance_overflow447w(0);
wire_sign_dffe_w_lg_q434w(0) <= NOT sign_dffe15;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes0 <= tbl1_compare_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes1 <= tbl1_compare_dffe11_4_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes2 <= tbl1_compare_dffe11_4_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes3 <= tbl1_compare_dffe11_4_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_tbl2_prod_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_tbl2_prod_dffe12 <= tbl1_tbl2_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl3_taylor_prod_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl3_taylor_prod_dffe12 <= tbl3_taylor_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_0 <= x_fixed;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_1 <= x_fixed_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_2 <= x_fixed_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_3 <= x_fixed_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_4 <= x_fixed_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xf_pre_2_dffe10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xf_pre_2_dffe10 <= xf_pre_2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xf_pre_dffe9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xf_pre_dffe9 <= xf_pre_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_exp_value_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_exp_value_dffe4 <= xi_exp_value_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_ln2_prod_dffe7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_ln2_prod_dffe7 <= xi_ln2_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_prod_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_prod_dffe3 <= xi_prod_wi;
END IF;
END IF;
END PROCESS;
wire_exp_minus_bias_dataa <= ( "0" & exp_w);
wire_exp_minus_bias_datab <= ( "0" & exp_bias);
exp_minus_bias : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => wire_exp_minus_bias_dataa,
datab => wire_exp_minus_bias_datab,
result => wire_exp_minus_bias_result
);
wire_exp_value_add_bias_w_lg_w_result_range445w446w(0) <= NOT wire_exp_value_add_bias_w_result_range445w(0);
wire_exp_value_add_bias_dataa <= ( "0" & exp_value_b4_bias_dffe_10);
wire_exp_value_add_bias_datab <= ( "0" & exp_bias(7 DOWNTO 1) & wire_extra_ln2_dffe_5_w_lg_q157w);
wire_exp_value_add_bias_w_result_range445w(0) <= wire_exp_value_add_bias_result(8);
exp_value_add_bias : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
cin => wire_cin_to_bias_dataout,
clken => clk_en,
clock => clock,
dataa => wire_exp_value_add_bias_dataa,
datab => wire_exp_value_add_bias_datab,
result => wire_exp_value_add_bias_result
);
wire_exp_value_man_over_w_lg_w_lg_w_result_range435w436w437w(0) <= wire_exp_value_man_over_w_lg_w_result_range435w436w(0) AND wire_sign_dffe_w_lg_q434w(0);
wire_exp_value_man_over_w_lg_w_result_range435w436w(0) <= NOT wire_exp_value_man_over_w_result_range435w(0);
wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range435w436w437w438w(0) <= wire_exp_value_man_over_w_lg_w_lg_w_result_range435w436w437w(0) OR sign_dffe15;
wire_exp_value_man_over_datab <= ( "00000000" & man_overflow_wo);
wire_exp_value_man_over_w_result_range435w(0) <= wire_exp_value_man_over_result(8);
exp_value_man_over : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => wire_exp_value_add_bias_result,
datab => wire_exp_value_man_over_datab,
result => wire_exp_value_man_over_result
);
wire_invert_exp_value_dataa <= (OTHERS => '0');
wire_invert_exp_value_w_result_range130w <= wire_invert_exp_value_result(5 DOWNTO 0);
invert_exp_value : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_invert_exp_value_dataa,
datab => exp_value(7 DOWNTO 0),
result => wire_invert_exp_value_result
);
wire_man_round_datab <= ( "0000000000000000000000" & round_up_wo);
man_round : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 23
)
PORT MAP (
dataa => man_round_wo,
datab => wire_man_round_datab,
result => wire_man_round_result
);
wire_one_minus_xf_dataa <= ( "1" & "000000000000000000000000000000");
one_minus_xf : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 31
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_one_minus_xf_dataa,
datab => wire_extra_ln2_muxa_dataout,
result => wire_one_minus_xf_result
);
wire_x_fixed_minus_xiln2_datab <= ( "0" & xi_ln2_prod_wo(45 DOWNTO 9));
x_fixed_minus_xiln2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 38
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => x_fixed_dffe_4,
datab => wire_x_fixed_minus_xiln2_datab,
result => wire_x_fixed_minus_xiln2_result
);
wire_xf_minus_ln2_datab <= ( "00" & ln2_w(37 DOWNTO 9));
xf_minus_ln2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 31
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => xf_pre(30 DOWNTO 0),
datab => wire_xf_minus_ln2_datab,
result => wire_xf_minus_ln2_result
);
wire_xi_add_one_datab <= "00000001";
xi_add_one : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => xi_exp_value,
datab => wire_xi_add_one_datab,
result => wire_xi_add_one_result
);
rbarrel_shift : lpm_clshift
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_SHIFTTYPE => "LOGICAL",
LPM_WIDTH => 38,
LPM_WIDTHDIST => 6
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => barrel_shifter_data,
direction => exp_value_wo(8),
distance => barrel_shifter_distance,
result => wire_rbarrel_shift_result
);
distance_overflow_comp : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
agb => wire_distance_overflow_comp_agb,
dataa => wire_exp_value_to_compare_muxa_dataout,
datab => distance_overflow_val_w
);
tbl1_compare : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 5
)
PORT MAP (
ageb => wire_tbl1_compare_ageb,
dataa => xf(28 DOWNTO 24),
datab => addr_val_more_than_one
);
underflow_compare : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
agb => wire_underflow_compare_agb,
dataa => wire_exp_value_to_compare_muxa_dataout,
datab => underflow_compare_val_w
);
man_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 31,
LPM_WIDTHB => 31,
LPM_WIDTHP => 62,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => tbl1_tbl2_prod_wo,
datab => tbl3_taylor_prod_wo,
result => wire_man_prod_result
);
tbl1_tbl2_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 32,
LPM_WIDTHB => 32,
LPM_WIDTHP => 64,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => table_one_out,
datab => table_two_out,
result => wire_tbl1_tbl2_prod_result
);
wire_tbl3_taylor_prod_datab <= ( "1" & "000000000000000" & xf(13 DOWNTO 0));
tbl3_taylor_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 32,
LPM_WIDTHB => 30,
LPM_WIDTHP => 62,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => table_three_out,
datab => wire_tbl3_taylor_prod_datab,
result => wire_tbl3_taylor_prod_result
);
xi_ln2_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 8,
LPM_WIDTHB => 38,
LPM_WIDTHP => 46,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_exp_value_to_ln2a_dataout,
datab => ln2_w,
result => wire_xi_ln2_prod_result
);
xi_prod : lpm_mult
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 12,
LPM_WIDTHB => 9,
LPM_WIDTHP => 21,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
dataa => x_fixed(37 DOWNTO 26),
datab => one_over_ln2_w,
result => wire_xi_prod_result
);
loop2 : FOR i IN 0 TO 31 GENERATE
loop3 : FOR j IN 0 TO 31 GENERATE
wire_table_one_data_2d(i, j) <= table_one_data(i*32+j);
END GENERATE loop3;
END GENERATE loop2;
table_one : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 32,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_one_data_2d,
result => wire_table_one_result,
sel => xf(28 DOWNTO 24)
);
loop4 : FOR i IN 0 TO 31 GENERATE
loop5 : FOR j IN 0 TO 20 GENERATE
wire_table_three_data_2d(i, j) <= table_three_data(i*21+j);
END GENERATE loop5;
END GENERATE loop4;
table_three : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 21,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_three_data_2d,
result => wire_table_three_result,
sel => xf(18 DOWNTO 14)
);
loop6 : FOR i IN 0 TO 31 GENERATE
loop7 : FOR j IN 0 TO 25 GENERATE
wire_table_two_data_2d(i, j) <= table_two_data(i*26+j);
END GENERATE loop7;
END GENERATE loop6;
table_two : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 26,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_two_data_2d,
result => wire_table_two_result,
sel => xf(23 DOWNTO 19)
);
wire_cin_to_bias_dataout <= shifted_value;
wire_exp_result_mux_prea_dataout <= exp_one WHEN wire_w_lg_w551w552w(0) = '1' ELSE exp_result_w;
loop8 : FOR i IN 0 TO 7 GENERATE
wire_exp_result_mux_prea_w_lg_dataout557w(i) <= wire_exp_result_mux_prea_dataout(i) AND wire_w_lg_w_lg_w_lg_underflow_w554w555w556w(0);
END GENERATE loop8;
wire_exp_value_b4_biasa_dataout <= exp_invert WHEN sign_dffe3 = '1' ELSE xi_exp_value;
wire_exp_value_selecta_dataout <= wire_invert_exp_value_result(5 DOWNTO 0) WHEN exp_value_wo(8) = '1' ELSE exp_value_wo(5 DOWNTO 0);
wire_exp_value_to_compare_muxa_dataout <= wire_invert_exp_value_result WHEN exp_value_wo(8) = '1' ELSE exp_value_wo(7 DOWNTO 0);
wire_exp_value_to_ln2a_dataout <= wire_xi_add_one_result WHEN sign_dffe4 = '1' ELSE xi_exp_value_wo;
wire_extra_ln2_muxa_dataout <= wire_xf_minus_ln2_result WHEN extra_ln2_dffe_0 = '1' ELSE xf_pre_wo(30 DOWNTO 0);
wire_man_result_muxa_dataout <= ( nan_w & "0000000000000000000000") WHEN wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w(0) = '1' ELSE wire_man_round_result;
wire_xf_muxa_dataout <= wire_one_minus_xf_result WHEN sign_dffe10 = '1' ELSE xf_pre_2_wo(30 DOWNTO 0);
END RTL; --fp_exp_altfp_exp_fkd
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_exp IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp;
ARCHITECTURE RTL OF fp_exp IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_exp_altfp_exp_fkd
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_exp_altfp_exp_fkd_component : fp_exp_altfp_exp_fkd
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_exp"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "17"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.cmp TRUE TRUE
|
mit
|
7c34244fb9de0abb587306c0b7093614
| 0.67055 | 2.534173 | false | false | false | false |
xuefei1/ElectronicEngineControl
|
electronic_engine_control.vhd
| 1 | 8,513 |
-- This file is modified from lab1 top level vhdl file provided in eclass
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE0_CONSTANTS.all;
entity electronic_engine_control is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (3 downto 0);
CLOCK_50 : in std_logic;
-- Green leds on board
LED : out DE0_LED_GREEN;
-- SDRAM on board
DRAM_ADDR : out DE0_SDRAM_ADDR_BUS;
DRAM_BA : out DE0_DRAM_BA;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout DE0_SDRAM_DATA_BUS;
DRAM_DQM : out DE0_SDRAM_DQM;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
GPIO_0 : out std_logic_vector (35 downto 0);
GPIO_2 : in std_logic_vector (7 downto 0);
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic
);
end electronic_engine_control;
architecture structure of electronic_engine_control is
-- Declarations (optional)
component niosII_system is
port (
clk_0 : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE0_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE0_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_out : out std_logic; -- clk
out_port_from_the_green_leds : out DE0_LED_GREEN; -- led out
in_port_to_the_switch : in std_logic_vector(3 downto 0) := (others => 'X'); -- export switch
adc_sclk_from_the_de0_nano_adc_0 : out std_logic; -- adc_sclk
adc_cs_n_from_the_de0_nano_adc_0 : out std_logic; -- adc_cs_n
adc_dout_to_the_de0_nano_adc_0 : in std_logic := 'X'; -- adc_dout
adc_din_from_the_de0_nano_adc_0 : out std_logic; -- adc_din
pwm_generator_tps_out_pwm_out_export : out std_logic := '0'; -- pwm_out_tps_val
rs232_0_external_interface_RXD : in std_logic := 'X'; -- RXD
rs232_0_external_interface_TXD : out std_logic; -- TXD
solenoid_out_external_connection_export : out std_logic_vector(7 downto 0) := "00000000"; -- export solenid drivin pins
pwm_generator_throttle_close_pwm_out_export : out std_logic; -- export pwm throttle close
pwm_generator_throttle_open_pwm_out_export : out std_logic; -- export pwm throttle open
buttons_external_connection_export : in std_logic_vector(7 downto 0) := "00000000"; -- export buttons
pwm_generator_test_pwm_out_export : out std_logic; -- export pwm test
curr_gear_out_external_connection_export : out std_logic_vector(1 downto 0); -- export current gear info
pwm_generator_engine_sound_out_pwm_out_export : out std_logic := '0'; -- export pwm engine sound
rpm_pwm_decoder_conduit_end_export : in std_logic := '0' -- export rpm pwm in
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA(1) <= BA(1);
DRAM_BA(0) <= BA(0);
DRAM_DQM(1) <= DQM(1);
DRAM_DQM(0) <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_0 => CLOCK_50,
reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_out => DRAM_CLK,
out_port_from_the_green_leds => LED,
in_port_to_the_switch => SW,
adc_sclk_from_the_de0_nano_adc_0 => ADC_SCLK,
adc_cs_n_from_the_de0_nano_adc_0 => ADC_CS_N,
adc_dout_to_the_de0_nano_adc_0 => ADC_SDAT,
adc_din_from_the_de0_nano_adc_0 => ADC_SADDR,
pwm_generator_test_pwm_out_export => GPIO_0(0),
pwm_generator_throttle_open_pwm_out_export => GPIO_0(8),
pwm_generator_throttle_close_pwm_out_export => GPIO_0(9),
pwm_generator_tps_out_pwm_out_export => GPIO_0(1),
solenoid_out_external_connection_export(2) => GPIO_0(2),
solenoid_out_external_connection_export(3) => GPIO_0(3),
buttons_external_connection_export(2) => GPIO_2(2),
buttons_external_connection_export(3) => GPIO_2(3),
rs232_0_external_interface_TXD => GPIO_0(7),
curr_gear_out_external_connection_export(0) => GPIO_0(10),
curr_gear_out_external_connection_export(1) => GPIO_0(11),
rs232_0_external_interface_RXD => GPIO_2(4),
pwm_generator_engine_sound_out_pwm_out_export => GPIO_0(12),
rpm_pwm_decoder_conduit_end_export => GPIO_2(7)
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE0_CONSTANTS is
type DE0_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE0_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE0_SDRAM_DQM is array(1 downto 0) of std_logic;
type DE0_LED_GREEN is array(7 downto 0) of std_logic;
type DE0_DRAM_BA is array(1 downto 0) of std_logic;
end DE0_CONSTANTS;
|
apache-2.0
|
08a6a34c119b23ab645807f5053bc18c
| 0.462234 | 3.587442 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_framer.vhd
| 1 | 16,155 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_framer
---- Version: 1.0.0
---- Description:
---- Implementation of standard CCSDS 132.0-B-2
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
---- 2016/10/20: rework
---- 2016/10/24: multiple footers generation to ensure higher speed than input max data rate (CCSDS_TX_FRAMER_DATA_BUS_SIZE*CLK_FREQ bits/sec)
---- 2016/10/31: ressources optimization
---- 2016/11/03: add only idle data insertion
-------------------------------
--TODO: trailer as option
--HEADER (6 up to 70 bytes) / before data / f(idle)
--TRANSFER FRAME DATA FIELD => Variable
--TRAILER (2 up to 6 bytes) / after data / f(data, header)
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx framer inputs and outputs
--=============================================================================
entity ccsds_tx_framer is
generic(
constant CCSDS_TX_FRAMER_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_FRAMER_DATA_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_FOOTER_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_HEADER_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO: integer := 16 -- activated max framer parallelism speed ratio / 1 = full speed / 2 = wishbone bus non-pipelined write max speed / ... / CCSDS_TX_FRAMER_DATA_BUS_SIZE = external serial data
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
dat_nxt_o: out std_logic;
dat_val_o: out std_logic;
idl_o: out std_logic
);
end ccsds_tx_framer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_framer is
component ccsds_tx_header is
generic(
constant CCSDS_TX_HEADER_LENGTH: integer
);
port(
clk_i: in std_logic;
idl_i: in std_logic;
nxt_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_HEADER_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_footer is
generic(
constant CCSDS_TX_FOOTER_DATA_LENGTH : integer;
constant CCSDS_TX_FOOTER_LENGTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
nxt_i: in std_logic;
bus_o: out std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FOOTER_DATA_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector((CCSDS_TX_FOOTER_LENGTH+CCSDS_TX_FOOTER_DATA_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
constant CCSDS_TX_FRAMER_FOOTER_NUMBER : integer := CCSDS_TX_FRAMER_DATA_BUS_SIZE*((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8+1)/(CCSDS_TX_FRAMER_DATA_LENGTH*8*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO)+1; -- 8*(HEAD+DATA+FOOT+1) clks / crc ; BUS bits / parallelism * clk ; DATA*8 bits / footer
constant CCSDS_TX_FRAMER_OID_PATTERN: std_logic_vector(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) := (others => '1'); -- Only Idle Data Pattern transmitted (jam payload for frame stuffing)
-- internal variable signals
type frame_array is array (CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0) of std_logic_vector((CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH)*8-1 downto 0);
signal wire_header_data: std_logic_vector(CCSDS_TX_FRAMER_HEADER_LENGTH*8-1 downto 0);
signal wire_footer_data_o: frame_array;
signal wire_header_data_valid: std_logic;
signal wire_footer_data_valid: std_logic_vector(CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0);
signal wire_header_next: std_logic := '0';
signal wire_header_idle: std_logic := '0';
signal wire_footer_next: std_logic_vector(CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0) := (others => '0');
signal wire_footer_busy: std_logic_vector(CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0);
signal reg_next_frame: std_logic_vector(CCSDS_TX_FRAMER_DATA_LENGTH*8-CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
signal reg_current_frame: std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
signal reg_processing_frame: std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH)*8-1 downto 0);
signal next_processing_frame_pointer : integer range 0 to CCSDS_TX_FRAMER_FOOTER_NUMBER-1 := 0;
-- components instanciation and mapping
begin
tx_header_0: ccsds_tx_header
generic map(
CCSDS_TX_HEADER_LENGTH => CCSDS_TX_FRAMER_HEADER_LENGTH
)
port map(
clk_i => clk_i,
idl_i => wire_header_idle,
nxt_i => wire_header_next,
rst_i => rst_i,
dat_o => wire_header_data,
dat_val_o => wire_header_data_valid
);
FOOTERGEN:
for i in 0 to CCSDS_TX_FRAMER_FOOTER_NUMBER-1 generate
tx_footer_x : ccsds_tx_footer
generic map(
CCSDS_TX_FOOTER_DATA_LENGTH => CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH,
CCSDS_TX_FOOTER_LENGTH => CCSDS_TX_FRAMER_FOOTER_LENGTH
)
port map(
clk_i => clk_i,
rst_i => rst_i,
nxt_i => wire_footer_next(i),
bus_o => wire_footer_busy(i),
dat_i => reg_processing_frame,
dat_o => wire_footer_data_o(i),
dat_val_o => wire_footer_data_valid(i)
);
end generate FOOTERGEN;
-- presynthesis checks
CHKFRAMERP0 : if ((CCSDS_TX_FRAMER_DATA_LENGTH*8) mod CCSDS_TX_FRAMER_DATA_BUS_SIZE /= 0) generate
process
begin
report "ERROR: FRAMER DATA LENGTH SHOULD BE A MULTIPLE OF FRAMER DATA BUS SIZE" severity failure;
wait;
end process;
end generate CHKFRAMERP0;
CHKFRAMERP1 : if ((CCSDS_TX_FRAMER_DATA_LENGTH) = 0) generate
process
begin
report "ERROR: FRAMER DATA LENGTH CANNOT BE 0" severity failure;
wait;
end process;
end generate CHKFRAMERP1;
CHKFRAMERP2 : if ((CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO) = 0) generate
process
begin
report "ERROR: PARALLELISM MAX RATIO CANNOT BE 0" severity failure;
wait;
end process;
end generate CHKFRAMERP2;
-- internal processing
--=============================================================================
-- Begin of frameroutputp
-- Generate valid frame output on footer data_valid signal
--=============================================================================
-- read: rst_i, wire_footer_data, wire_footer_data_valid
-- write: dat_o, dat_val_o
-- r/w: next_valid_frame_pointer
FRAMEROUTPUTP: process (clk_i)
variable next_valid_frame_pointer : integer range 0 to CCSDS_TX_FRAMER_FOOTER_NUMBER-1 := 0;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
next_valid_frame_pointer := 0;
dat_o <= (others => '0');
dat_val_o <= '0';
-- generating valid frames output
else
dat_o <= wire_footer_data_o(next_valid_frame_pointer);
if (wire_footer_data_valid(next_valid_frame_pointer) = '1') then
dat_val_o <= '1';
if (next_valid_frame_pointer < (CCSDS_TX_FRAMER_FOOTER_NUMBER-1)) then
next_valid_frame_pointer := (next_valid_frame_pointer + 1);
else
next_valid_frame_pointer := 0;
end if;
else
dat_o <= (others => '0');
dat_val_o <= '0';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of framerprocessp
-- Start footer computation on valid header signal
--=============================================================================
-- read: wire_header_data, wire_header_data_valid
-- write: next_processing_frame_pointer, reg_processing_frame, wire_footer_next
-- r/w:
FRAMERPROCESSP: process (clk_i)
variable reg_next_processing_frame: std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
next_processing_frame_pointer <= 0;
wire_footer_next <= (others => '0');
else
if(wire_header_data_valid = '1') then
reg_processing_frame((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH)*8-1 downto CCSDS_TX_FRAMER_DATA_LENGTH*8) <= wire_header_data;
-- idle data to be used
if (wire_header_data(10 downto 0) = "11111111110") then
reg_processing_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) <= CCSDS_TX_FRAMER_OID_PATTERN;
reg_next_processing_frame := reg_current_frame;
-- current data to be used
else
-- continuous data flow header is one clk in advance
if (CCSDS_TX_FRAMER_DATA_LENGTH*8 = CCSDS_TX_FRAMER_DATA_BUS_SIZE) and (CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO = 1) then
reg_processing_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) <= reg_next_processing_frame;
reg_next_processing_frame := reg_current_frame;
-- header is synchronous with data
else
reg_processing_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) <= reg_current_frame;
end if;
end if;
wire_footer_next(next_processing_frame_pointer) <= '1';
if (next_processing_frame_pointer = CCSDS_TX_FRAMER_FOOTER_NUMBER-1) then
next_processing_frame_pointer <= 0;
else
next_processing_frame_pointer <= (next_processing_frame_pointer + 1);
end if;
end if;
if (next_processing_frame_pointer = 0) then
wire_footer_next(CCSDS_TX_FRAMER_FOOTER_NUMBER-1) <= '0';
else
wire_footer_next(next_processing_frame_pointer-1) <= '0';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of framergeneratep
-- Generate next_frame, start next header generation
--=============================================================================
-- read: dat_val_i, rst_i
-- write: wire_header_next, reg_current_frame, reg_next_frame, dat_nxt_o, idl_o
-- r/w:
FRAMERGENERATEP: process (clk_i)
variable next_frame_write_pos: integer range 0 to (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1 := (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
variable frame_output_counter: integer range 0 to (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1 := 0;
variable current_frame_ready: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
current_frame_ready := '0';
wire_header_next <= '0';
next_frame_write_pos := (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
frame_output_counter := 0;
idl_o <= '0';
dat_nxt_o <= '0';
else
-- valid data is presented
if (dat_val_i = '1') then
-- next frame is full
if (next_frame_write_pos = 0) then
reg_current_frame(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0) <= dat_i;
reg_current_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto CCSDS_TX_FRAMER_DATA_BUS_SIZE) <= reg_next_frame;
-- time to start frame computation
if (frame_output_counter = 0) then
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*8*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
wire_header_next <= '1';
wire_header_idle <= '0';
idl_o <= '0';
-- source data rate overflow / stop buffer output
else
dat_nxt_o <= '0';
end if;
else
frame_output_counter := frame_output_counter - 1;
-- signal a frame ready for computation
if (current_frame_ready = '0') then
wire_header_next <= '0';
current_frame_ready := '1';
-- source data rate overflow
else
dat_nxt_o <= '0';
end if;
end if;
next_frame_write_pos := CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE-1;
else
-- filling next frame
reg_next_frame(next_frame_write_pos*CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto (next_frame_write_pos-1)*CCSDS_TX_FRAMER_DATA_BUS_SIZE) <= dat_i;
next_frame_write_pos := next_frame_write_pos-1;
-- time to start frame computation
if (frame_output_counter = 0) then
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
dat_nxt_o <= '1';
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
-- no frame is ready / inserting idle data
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
idl_o <= '1';
-- a frame is ready
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
idl_o <= '0';
end if;
else
dat_nxt_o <= '0';
end if;
else
-- stop data before overflow
if (next_frame_write_pos = 1) and (current_frame_ready = '1') then
dat_nxt_o <= '0';
end if;
frame_output_counter := frame_output_counter - 1;
wire_header_next <= '0';
end if;
end if;
-- no valid data
else
-- time to start frame computation
if (frame_output_counter = 0) then
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
dat_nxt_o <= '1';
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
idl_o <= '1';
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
idl_o <= '0';
end if;
end if;
else
wire_header_next <= '0';
frame_output_counter := frame_output_counter - 1;
end if;
end if;
end if;
end if;
end process;
end structure;
|
mit
|
68172bf290641ca594bfa328e0b41c1c
| 0.554998 | 3.799389 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp_add.vhd
| 1 | 253,628 |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: fp_add.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=7 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_add_sub 2010:03:24:20:34:20:SJ cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_add_altbarrel_shift_h0e;
ARCHITECTURE RTL OF fp_add_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) AND wire_lbarrel_shift_w678w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) AND wire_lbarrel_shift_w674w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) AND wire_lbarrel_shift_w699w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) AND wire_lbarrel_shift_w695w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) AND wire_lbarrel_shift_w721w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) AND wire_lbarrel_shift_w717w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) AND wire_lbarrel_shift_w743w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) AND wire_lbarrel_shift_w739w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) AND wire_lbarrel_shift_w765w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) AND wire_lbarrel_shift_w761w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w770w & wire_lbarrel_shift_w748w & wire_lbarrel_shift_w726w & wire_lbarrel_shift_w704w & wire_lbarrel_shift_w683w);
wire_lbarrel_shift_w674w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w678w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w695w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w699w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w717w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w721w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w739w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w743w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w761w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w765w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range771w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range771w;
END IF;
END IF;
END PROCESS;
END RTL; --fp_add_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altbarrel_shift_6hb IS
PORT
(
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_add_altbarrel_shift_6hb;
ARCHITECTURE RTL OF fp_add_altbarrel_shift_6hb IS
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range779w793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range801w814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range822w836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w884w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w788w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w792w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w809w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w813w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w831w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w835w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w857w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w879w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range777w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range800w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) AND wire_rbarrel_shift_w792w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) AND wire_rbarrel_shift_w788w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) AND wire_rbarrel_shift_w813w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) AND wire_rbarrel_shift_w809w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) AND wire_rbarrel_shift_w835w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) AND wire_rbarrel_shift_w831w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) AND wire_rbarrel_shift_w857w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) AND wire_rbarrel_shift_w853w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) AND wire_rbarrel_shift_w879w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) AND wire_rbarrel_shift_w_sbit_w_range777w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) AND wire_rbarrel_shift_w_sbit_w_range800w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) AND wire_rbarrel_shift_w_sbit_w_range820w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) AND wire_rbarrel_shift_w_sbit_w_range842w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) AND wire_rbarrel_shift_w_sbit_w_range864w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0) <= NOT wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0) <= NOT wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0) <= NOT wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) <= NOT wire_rbarrel_shift_w_sel_w_range782w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) <= NOT wire_rbarrel_shift_w_sel_w_range803w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) <= NOT wire_rbarrel_shift_w_sel_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) <= NOT wire_rbarrel_shift_w_sel_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) <= NOT wire_rbarrel_shift_w_sel_w_range869w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w797w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w818w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w840w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w862w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w884w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w884w & wire_rbarrel_shift_w862w & wire_rbarrel_shift_w840w & wire_rbarrel_shift_w818w & wire_rbarrel_shift_w797w);
wire_rbarrel_shift_w788w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w792w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w809w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w813w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w831w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w835w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w853w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w857w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w879w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range779w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range801w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range822w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range842w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range864w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range777w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range800w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range820w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range782w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range803w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range825w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range847w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range869w(0) <= sel_w(4);
END RTL; --fp_add_altbarrel_shift_6hb
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_3e8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --fp_add_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_6e8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero920w921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero922w923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero920w & wire_altpriority_encoder14_w_lg_w_lg_zero922w923w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : fp_add_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0) <= wire_altpriority_encoder14_w_lg_zero920w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero922w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero920w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero922w923w(0) <= wire_altpriority_encoder14_w_lg_zero922w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0);
altpriority_encoder14 : fp_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --fp_add_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_be8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero910w911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero912w913w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero910w & wire_altpriority_encoder12_w_lg_w_lg_zero912w913w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : fp_add_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i) <= wire_altpriority_encoder12_w_lg_zero910w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero912w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero910w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero912w913w(i) <= wire_altpriority_encoder12_w_lg_zero912w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i);
END GENERATE loop52;
altpriority_encoder12 : fp_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --fp_add_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_add_altpriority_encoder_3v7;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --fp_add_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_add_altpriority_encoder_6v7;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero945w946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero947w948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero945w & wire_altpriority_encoder18_w_lg_w_lg_zero947w948w);
altpriority_encoder17 : fp_add_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0) <= wire_altpriority_encoder18_w_lg_zero945w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero947w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero945w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero947w948w(0) <= wire_altpriority_encoder18_w_lg_zero947w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0);
altpriority_encoder18 : fp_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --fp_add_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_add_altpriority_encoder_bv7;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero936w937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero938w939w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero936w & wire_altpriority_encoder16_w_lg_w_lg_zero938w939w);
altpriority_encoder15 : fp_add_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i) <= wire_altpriority_encoder16_w_lg_zero936w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero938w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero936w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero938w939w(i) <= wire_altpriority_encoder16_w_lg_zero938w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i);
END GENERATE loop55;
altpriority_encoder16 : fp_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --fp_add_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_r08 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_add_altpriority_encoder_r08;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_r08 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero901w902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero903w904w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero901w & wire_altpriority_encoder10_w_lg_w_lg_zero903w904w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i) <= wire_altpriority_encoder10_w_lg_zero901w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero903w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero901w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero903w904w(i) <= wire_altpriority_encoder10_w_lg_zero903w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i);
END GENERATE loop58;
altpriority_encoder10 : fp_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : fp_add_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --fp_add_altpriority_encoder_r08
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_rf8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_rf8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_rf8 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero957w958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero959w960w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero957w & wire_altpriority_encoder20_w_lg_w_lg_zero959w960w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : fp_add_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i) <= wire_altpriority_encoder20_w_lg_zero957w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero959w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero957w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero959w960w(i) <= wire_altpriority_encoder20_w_lg_zero959w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i);
END GENERATE loop61;
altpriority_encoder20 : fp_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --fp_add_altpriority_encoder_rf8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_qb6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_add_altpriority_encoder_qb6;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_qb6 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero894w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero894w895w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_r08
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_rf8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder8_w_lg_zero892w & wire_altpriority_encoder8_w_lg_w_lg_zero894w895w);
altpriority_encoder7 : fp_add_altpriority_encoder_r08
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero894w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero892w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero894w895w(i) <= wire_altpriority_encoder8_w_lg_zero894w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i);
END GENERATE loop64;
altpriority_encoder8 : fp_add_altpriority_encoder_rf8
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
END RTL; --fp_add_altpriority_encoder_qb6
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_nh8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1004w1005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1004w1005w(0) <= NOT wire_altpriority_encoder27_w_data_range1004w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1004w1005w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1004w(0) <= data(0);
END RTL; --fp_add_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_qh8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero996w997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero998w999w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0) <= wire_altpriority_encoder27_w_lg_zero996w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero996w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0);
altpriority_encoder27 : fp_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : fp_add_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --fp_add_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_vh8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero986w987w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero988w989w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i) <= wire_altpriority_encoder25_w_lg_zero986w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero988w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero986w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i);
END GENERATE loop67;
altpriority_encoder25 : fp_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : fp_add_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --fp_add_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_fj8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_add_altpriority_encoder_fj8;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_fj8 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero976w977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT fp_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero978w979w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i) <= wire_altpriority_encoder23_w_lg_zero976w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero978w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero976w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i);
END GENERATE loop70;
altpriority_encoder23 : fp_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : fp_add_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --fp_add_altpriority_encoder_fj8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_add_altpriority_encoder_n28;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1038w1039w(0) <= NOT wire_altpriority_encoder34_w_data_range1038w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1038w1039w);
wire_altpriority_encoder34_w_data_range1038w(0) <= data(0);
END RTL; --fp_add_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_add_altpriority_encoder_q28;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w);
wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0) <= wire_altpriority_encoder33_w_lg_zero1031w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1031w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0);
altpriority_encoder33 : fp_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : fp_add_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --fp_add_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_add_altpriority_encoder_v28;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT fp_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i) <= wire_altpriority_encoder31_w_lg_zero1022w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1024w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1022w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i);
END GENERATE loop73;
altpriority_encoder31 : fp_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : fp_add_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --fp_add_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_f48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_add_altpriority_encoder_f48;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_f48 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i) <= wire_altpriority_encoder29_w_lg_zero1013w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1015w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1013w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i);
END GENERATE loop76;
altpriority_encoder29 : fp_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : fp_add_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --fp_add_altpriority_encoder_f48
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altpriority_encoder_e48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_add_altpriority_encoder_e48;
ARCHITECTURE RTL OF fp_add_altpriority_encoder_e48 IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero967w968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero969w970w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT fp_add_altpriority_encoder_fj8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_f48
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero969w970w);
loop77 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i) <= wire_altpriority_encoder21_w_lg_zero967w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop77;
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero969w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop78;
wire_altpriority_encoder21_w_lg_zero967w(0) <= NOT wire_altpriority_encoder21_zero;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero969w970w(i) <= wire_altpriority_encoder21_w_lg_zero969w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i);
END GENERATE loop79;
altpriority_encoder21 : fp_add_altpriority_encoder_fj8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : fp_add_altpriority_encoder_f48
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
END RTL; --fp_add_altpriority_encoder_e48
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 282
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add_altfp_add_sub_13k IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_add_altfp_add_sub_13k;
ARCHITECTURE RTL OF fp_add_altfp_add_sub_13k IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w278w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w276w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w292w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range272w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range290w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_add_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_add_altbarrel_shift_6hb
PORT
(
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_qb6
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_add_altpriority_encoder_e48
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop80 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w278w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w276w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND wire_w_exp_amb_w_range274w(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop89;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop93;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop95;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop96 : FOR i IN 0 TO 4 GENERATE
wire_w292w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) AND wire_w_exp_diff_abs_w_range290w(i);
END GENERATE loop96;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop97 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w279w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w273w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range272w(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop111;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop112 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w(i) <= wire_w_exp_diff_abs_exceed_max_w_range289w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop112;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop113 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop116;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w275w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range289w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop117 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop120;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w(0) <= wire_w_exp_diff_abs_exceed_max_w_range282w(0) OR wire_w_exp_diff_abs_w_range284w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w(0) <= wire_w_exp_diff_abs_exceed_max_w_range286w(0) OR wire_w_exp_diff_abs_w_range287w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12_wi;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13_wi;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14_wi;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12_wi;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13_wi;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14_wi;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12_wi;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13_wi;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14_wi;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12_wi;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13_wi;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14_wi;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12_wi;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13_wi;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14_wi;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12_wi;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13_wi;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14_wi;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41_wi;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23_wi;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13_wi;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14_wi;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w275w276w OR wire_w_lg_exp_amb_mux_w273w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41_wi;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23_wi;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27_wi;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23_wi;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27_wi;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41_wi;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41_wi;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23_wi;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27_wi;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41_wi;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12_wi;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13_wi;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14_wi;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12_wi;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12_wi;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13_wi;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14_wi;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12_wi;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23_wi;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27_wi;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41_wi;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13_wi;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14_wi;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23_wi;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27_wi;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41_wi;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23_wi;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27_wi;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23_wi;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27_wi;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41_wi;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23_wi;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13_wi;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w279w OR wire_w_lg_w_lg_exp_amb_mux_w275w278w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23_wi;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13_wi;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14_wi;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w OR wire_w292w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41_wi;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23_wi;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27_wi;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23_wi;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27_wi;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range274w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range272w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range282w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range286w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range289w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range290w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range284w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range287w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : fp_add_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : fp_add_altbarrel_shift_6hb
PORT MAP (
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : fp_add_altpriority_encoder_qb6
PORT MAP (
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : fp_add_altpriority_encoder_e48
PORT MAP (
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop121 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop122;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop123;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop125;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop126;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop127 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop129;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --fp_add_altfp_add_sub_13k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_add IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_add;
ARCHITECTURE RTL OF fp_add IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_add_altfp_add_sub_13k
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_add_altfp_add_sub_13k_component : fp_add_altfp_add_sub_13k
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_add_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
cc36e6f2c968bd7581557a76474d9a36
| 0.704457 | 2.425948 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/Data_Count.vhd
| 1 | 1,713 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:29:16 10/20/2016
-- Design Name:
-- Module Name: Data_Count - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Data_Count is
generic(DataEndOfCount : NATURAL := 8);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end Data_Count;
architecture Behavioral of Data_Count is
signal cuenta : std_logic_vector(3 downto 0) := (others =>'0') ;
begin
count <= cuenta;
p_counter: process(clk)
begin
if clk'event and clk = '1' then
if reset = '0' then
cuenta <= (others => '0');
-- cuenta <= to_unsigned(0, 8);
else
if enable = '1' then
cuenta <= cuenta + 1;
end if;
end if;
if cuenta = DataEndOfCount then
cuenta <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
mit
|
a8d4b518b2372f3be2056d3413418f4d
| 0.55108 | 3.660256 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
shifter_32_bit.vhd
| 1 | 2,673 |
-- 32-bit shifter circuit
-- this circuit performs shifts (both logical and arithmetic) on inputs
-- all code (c) copyright 2016 Jay valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity shifter_32_bit is
port (
-- inputs
a_32 : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(1 downto 0);
enable : in std_logic;
-- outputs
result_32 : out std_logic_vector(31 downto 0);
carry_out : out std_logic
);
end entity shifter_32_bit;
architecture shifter_32_bit_arch of shifter_32_bit is
-- defining signals
signal a_unsigned : unsigned(31 downto 0);
signal a_signed : signed(31 downto 0);
signal result_unsigned : unsigned(31 downto 0);
signal result_signed : signed(31 downto 0);
begin
-- design implementation
shift : process(opcode, enable, a_32, a_unsigned, a_signed, result_unsigned, result_signed)
begin
-- shifter enabled, perform specified shift function
if enable = '1' then
-- if performing logical shift then a needs to be unsigned
a_unsigned <= unsigned(a_32);
-- if performing arithmetic shift then a needs to be signed
a_signed <= signed(a_32);
-- opcode 00 is shift left logical
if opcode = "00" then
carry_out <= a_unsigned(31);
result_unsigned <= shift_left(a_unsigned, 1);
result_signed <= (others => '0');
-- opcode 01 is shift right logical
elsif opcode = "01" then
carry_out <= a_unsigned(0);
result_unsigned <= shift_right(a_unsigned, 1);
result_signed <= (others => '0');
-- opcode 10 is shift left arithmetic (copy lsb)
elsif opcode = "10" then
carry_out <= a_signed(31);
result_signed <= shift_left(a_signed, 1);
result_unsigned <= (others => '0');
-- opcode 11 is shift right arithmetic (copy msb)
elsif opcode = "11" then
carry_out <= a_signed(0);
result_signed <= shift_right(a_signed, 1);
result_unsigned <= (others => '0');
-- any other opcode gives result 0
else
carry_out <= '0';
result_signed <= (others => '0');
result_unsigned <= (others => '0');
end if;
if opcode(1) = '0' then
result_32 <= std_logic_vector(result_unsigned);
elsif opcode(1) = '1' then
result_32 <= std_logic_vector(result_signed);
else
result_32 <= (others => '0');
end if;
-- shifter disabled, all outputs and signals 0
else
result_32 <= (others => '0');
a_unsigned <= (others => '0');
a_signed <= (others => '0');
result_unsigned <= (others => '0');
result_signed <= (others => '0');
carry_out <= '0';
end if;
end process shift;
end architecture shifter_32_bit_arch;
|
mit
|
3c875b91a2311bee263b9add08ef16ef
| 0.638608 | 3.115385 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/Pulse_width.vhd
| 1 | 1,812 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:42:51 10/20/2016
-- Design Name:
-- Module Name: Pulse_width - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Pulse_width is
generic(PulseEndOfCount : NATURAL := 174);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
send : out STD_LOGIC);
end Pulse_width;
architecture Behavioral of Pulse_width is
signal cuenta : std_logic_vector(7 downto 0) := (others =>'0') ;
signal salida : std_logic := '0';
begin
send <= salida;
p_counter: process(clk)
begin
if clk'event and clk = '1' then
if reset = '0' then
cuenta <= (others => '0');
else
if enable = '1' then
cuenta <= cuenta + 1;
elsif enable = '0' then
cuenta <= (others => '0');
end if;
end if;
if cuenta = PulseEndOfCount then
salida <= '1';
cuenta <= (others => '0');
else
salida <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
9b015e58ec3d9bd203946b52cc5d7dd9
| 0.54415 | 3.660606 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/simulation/fifo_pkg.vhd
| 1 | 11,644 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fifo_pkg;
PACKAGE BODY fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fifo_pkg;
|
mit
|
4aeb9c0961ed7243ec4cc394eea17c20
| 0.489437 | 3.998626 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_coder_differential.vhd
| 1 | 3,620 |
---- Design Name: ccsds_tx_coder_differential
---- Version: 1.0.0
---- Description:
---- Word by word differential coder
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx differential coder inputs and outputs
--=============================================================================
entity ccsds_tx_coder_differential is
generic(
constant CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
constant CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_coder_differential;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_coder_differential is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKCODERP0 : if (CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE mod (CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) /= 0) generate
process
begin
report "ERROR: DATA BUS SIZE HAS TO BE A MULTIPLE OF BITS PER CODE WORD" severity failure;
wait;
end process;
end generate CHKCODERP0;
-- internal processing
--=============================================================================
-- Begin of coderdiffp
-- Differential encode words
--=============================================================================
-- read: rst_i, dat_i, dat_val_i
-- write: dat_o, dat_val_o
-- r/w:
CODERDIFFP: process (clk_i)
variable prev_sym: std_logic_vector(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
dat_val_o <= '0';
prev_sym := (others => '0');
else
if (dat_val_i = '1') then
dat_val_o <= '1';
dat_o(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) <= prev_sym xor dat_i(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD);
for i in CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE/(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD)-1 downto 1 loop
dat_o(i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto (i-1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) <= dat_i(i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto (i-1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) xor dat_i((i+1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD);
end loop;
prev_sym := dat_i(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto 0);
else
dat_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
mit
|
28d2b9b375985abbe0079a3b7e671a1f
| 0.536464 | 3.838812 | false | false | false | false |
plorefice/freon
|
src/hdl/core/alu.vhdl
| 1 | 1,521 |
-- Design:
-- Arithmetic Logic unit for the Freon core.
--
-- Authors:
-- Pietro Lorefice <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic (
XLEN : integer := 32 -- # data bits
);
port (
opsel : in std_logic_vector(2 downto 0);
ctrl : in std_logic;
op1, op2 : in std_logic_vector(XLEN-1 downto 0);
res : out std_logic_vector(XLEN-1 downto 0)
);
end entity ; -- alu
architecture beh of alu is
signal op1_s, op2_s : signed(XLEN-1 downto 0) := (others => '0');
signal op1_u, op2_u : unsigned(XLEN-1 downto 0) := (others => '0');
begin
-- Connecting internal signals
op1_s <= signed(op1);
op2_s <= signed(op2);
op1_u <= unsigned(op1);
op2_u <= unsigned(op2);
-- ALU arithmetic operators
process (op1_s, op2_s, op1_u, op2_u, op1, op2, opsel, ctrl)
begin
res <= (others => '0');
case opsel(2 downto 0) is
when "000" => -- ADD/SUB
if (ctrl = '0') then
res <= std_logic_vector(op1_s + op2_s);
else
res <= std_logic_vector(op1_s - op2_s);
end if;
when "010" => -- SLT
if (op1_s < op2_s) then
res(0) <= '1';
end if;
when "011" => -- SLTU
if (op1_u < op2_u) then
res(0) <= '1';
end if;
when "100" => -- XOR
res <= op1 xor op2;
when "110" => -- OR
res <= op1 or op2;
when "111" => -- AND
res <= op1 and op2;
when others => -- irrelevant, not managed by ALU
res <= (others => '0');
end case;
end process;
end architecture ; -- beh
|
mit
|
fcd6ca45d4a6cde0deadf03d8cab09b6
| 0.577252 | 2.535 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_physical_layer.vhd
| 1 | 4,059 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_physical_layer
---- Version: 1.0.0
---- Description:
---- Implementation of standard CCSDS 401.0-B
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
--TODO: Gray coder
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary tx physical layer
entity ccsds_tx_physical_layer is
generic (
constant CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL: integer;
constant CCSDS_TX_PHYSICAL_MODULATION_TYPE: integer;
constant CCSDS_TX_PHYSICAL_DATA_BUS_SIZE: integer;
constant CCSDS_TX_PHYSICAL_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH : integer
);
port(
-- inputs
clk_sam_i: in std_logic;
clk_sym_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_PHYSICAL_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
sam_i_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0)
);
end ccsds_tx_physical_layer;
-- internal processing
architecture structure of ccsds_tx_physical_layer is
component ccsds_tx_mapper_bits_symbols is
generic(
CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer;
CCSDS_TX_MAPPER_MODULATION_TYPE: integer;
CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_MAPPER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
sym_val_o: out std_logic;
sym_i_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_q_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0)
);
end component;
component ccsds_tx_filter is
generic(
CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
CCSDS_TX_FILTER_MODULATION_TYPE: integer;
CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer
);
port(
clk_i: in std_logic;
sym_val_i: in std_logic;
sym_i_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_q_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
rst_i: in std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
signal wire_sym_i: std_logic_vector(CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL-1 downto 0);
signal wire_sym_q: std_logic_vector(CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL-1 downto 0);
signal wire_sym_val: std_logic;
begin
tx_mapper_bits_symbols_0: ccsds_tx_mapper_bits_symbols
generic map(
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL,
CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_TX_PHYSICAL_MODULATION_TYPE,
CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_TX_PHYSICAL_DATA_BUS_SIZE
)
port map(
clk_i => clk_sym_i,
dat_i => dat_i,
dat_val_i => dat_val_i,
rst_i => rst_i,
sym_i_o => wire_sym_i,
sym_q_o => wire_sym_q,
sym_val_o => wire_sym_val
);
tx_filter_0: ccsds_tx_filter
generic map(
CCSDS_TX_FILTER_OVERSAMPLING_RATIO => CCSDS_TX_PHYSICAL_OVERSAMPLING_RATIO,
CCSDS_TX_FILTER_MODULATION_TYPE => CCSDS_TX_PHYSICAL_MODULATION_TYPE,
CCSDS_TX_FILTER_SIG_QUANT_DEPTH => CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH,
CCSDS_TX_FILTER_BITS_PER_SYMBOL => CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL
)
port map(
clk_i => clk_sam_i,
sym_i_i => wire_sym_i,
sym_q_i => wire_sym_q,
sym_val_i => wire_sym_val,
rst_i => rst_i,
-- sam_val_o => ,
sam_i_o => sam_i_o,
sam_q_o => sam_q_o
);
end structure;
|
mit
|
496110dc81e767d6867baedaa31deca7
| 0.627987 | 3.134363 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/data_counter.vhd
| 1 | 1,482 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:43 11/24/2016
-- Design Name:
-- Module Name: data_counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity data_counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (2 downto 0));
end data_counter;
architecture Behavioral of data_counter is
signal cuenta : std_logic_vector(2 downto 0) := (others =>'0') ;
begin
count <= cuenta;
process(clk, reset, enable, cuenta)
begin
if clk'event and clk = '1' then
if reset = '1' then
cuenta <= "000";
elsif enable <= '1' then
cuenta <= cuenta + 1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
7c2d5b34f51f12fbbbca90d20cde27b2
| 0.566802 | 3.686567 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
mux_2_single_bit.vhd
| 1 | 1,016 |
-- 2-input single-bit multiplexer
-- this circuit takes two single-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2_single_bit is
port (
-- inputs
in_signal_0 : in std_logic;
in_signal_1 : in std_logic;
-- select signal
input_select : in std_logic;
-- output
out_signal : out std_logic
);
end entity mux_2_single_bit;
architecture mux_2_single_bit_arch of mux_2_single_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(in_signal_0, in_signal_1, input_select)
begin
-- select 0 is input 0
if input_select = '0' then
out_signal <= in_signal_0;
-- select 1 is input 1
elsif input_select = '1' then
out_signal <= in_signal_1;
-- otherwise invalid select signal, output 0
else
out_signal <= '0';
end if;
end process mux;
end architecture mux_2_single_bit_arch;
|
mit
|
53268483cd1556fbb28bed798d174178
| 0.687008 | 2.944928 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/inputFIFO.vhd
| 1 | 9,387 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/7/22 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Implements a 4 byte input, 1 byte output FIFO buffer. Note: so far only writes where all 4 bytes contain
--* data are supported.
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity InputFIFO is
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DInxDI : in std_logic_vector(31 downto 0);
-- SelInxSI : in std_logic_vector(3 downto 0); -- not supported
WExSI : in std_logic;
StopOutputxSI : in std_logic;
BusyxSO : out std_logic;
DOutxDO : out std_logic_vector(7 downto 0);
OutStrobexSO : out std_logic;
LengthxDO : out integer range 0 to 2048);
end InputFIFO;
architecture Behavioral of InputFIFO is
constant ADR_BIT_LEN : integer := 11; -- addresses are in _bytes_
constant DEPTH : integer := 2048; -- max length of the fifo in _bytes_
signal LengthxDN, LengthxDP : integer range 0 to DEPTH := 0; -- number of _bytes_ in fifo
signal WrPtrxDN, WrPtrxDP : integer range 0 to DEPTH-1 := 0; -- write pointer in _bytes_
signal RdPtrxDN, RdPtrxDP : integer range 0 to DEPTH-1 := 0; -- read pointer in _bytes_
signal DoWritexS, DoReadxS : std_logic;
signal OutStrobexSN, OutStrobexSP : std_logic := '0';
signal BusyxSN, BusyxSP : std_logic := '0';
signal BRamDOutxD : std_logic_vector(31 downto 0);
signal BRamDInxD : std_logic_vector(31 downto 0);
signal BRamWrAdrxD : std_logic_vector(13 downto 0);
signal BRamRdAdrxD : std_logic_vector(13 downto 0);
begin -- Behavorial
-- implement write port logic
process (LengthxDP, WExSI, WrPtrxDP)
begin
WrPtrxDN <= WrPtrxDP;
BusyxSN <= '0';
BRamWrAdrxD <= std_logic_vector(to_unsigned(WrPtrxDP, ADR_BIT_LEN)) & "000";
DoWritexS <= '0';
if WExSI = '1' and LengthxDP <= (DEPTH-4) then
DoWritexS <= '1';
if WrPtrxDP < DEPTH-4 then
WrPtrxDN <= WrPtrxDP + 4;
else
WrPtrxDN <= 0;
end if;
end if;
-- use busy signal as an almost full indicator
if LengthxDP >= DEPTH-8 then -- indicate it when we have room for two or less writes
BusyxSN <= '1';
end if;
end process;
-- purpose: implement data output port logic
process (DInxDI, LengthxDP, RdPtrxDP, StopOutputxSI)
begin
RdPtrxDN <= RdPtrxDP;
DoReadxS <= '0';
OutStrobexSN <= '0';
BRamDInxD <= DInxDI;
BRamRdAdrxD <= std_logic_vector(to_unsigned(RdPtrxDP, ADR_BIT_LEN)) & "000";
if LengthxDP > 0 and StopOutputxSI = '0' then
DoReadxS <= '1';
OutStrobexSN <= '1'; -- bram delays data output by one clock cycle, do same for strobe
if RdPtrxDP < DEPTH-1 then
RdPtrxDN <= RdPtrxDP + 1;
else
RdPtrxDN <= 0;
end if;
end if;
end process;
-- purpose: implement a length counter
lenCntPrcs : process (DoReadxS, DoWritexS, LengthxDP)
begin
LengthxDN <= LengthxDP;
if DoWritexS = '1' and DoReadxS = '0' then
if LengthxDP <= (DEPTH-4) then
LengthxDN <= LengthxDP + 4;
else
assert false report "Input FIFO overrun" severity error;
end if;
end if;
if DoWritexS = '0' and DoReadxS = '1' then
assert LengthxDP > 0 report "input FIFO underrun" severity error;
LengthxDN <= LengthxDP - 1;
end if;
if DoWritexS = '1' and DoReadxS = '1' then
assert LengthxDP < DEPTH-3 report "Input FIFO underrun at simultaneous read and write" severity error;
LengthxDN <= LengthxDP + 4 - 1;
end if;
end process lenCntPrcs;
DOutxDO <= BRamDOutxD(7 downto 0);
LengthxDO <= LengthxDP;
OutStrobexSO <= OutStrobexSP;
BusyxSO <= BusyxSP;
-- purpose: implement registers
process (ClkxCI, RstxRI)
begin
if ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if RstxRI = '1' then
LengthxDP <= 0;
WrPtrxDP <= 0;
RdPtrxDP <= 0;
OutStrobexSP <= '0';
BusyxSP <= '0';
else
LengthxDP <= LengthxDN;
WrPtrxDP <= WrPtrxDN;
RdPtrxDP <= RdPtrxDN;
OutStrobexSP <= OutStrobexSN;
BusyxSP <= BusyxSN;
end if;
end if;
end process;
FifoBRam : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => open, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => BRamDOutxD, -- 32-bit B port data output
DOPB => open, -- 4-bit B port parity output
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => BRamWrAdrxD, -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => DoWritexS, -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => "1111", -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => DInxDI, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => BRamRdAdrxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => DoReadxS, -- 1-bit B port enable input
REGCEB => '1', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => "0000", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => "0000" -- 4-bit B port parity input
);
end Behavioral;
|
gpl-2.0
|
6d1ad139be107e7c63b2d3489901c0f7
| 0.541174 | 4.081304 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/history.vhd
| 1 | 13,435 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/21 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--*
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity historyBuffer is
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
WriteInxDI : in std_logic_vector(7 downto 0);
WExSI : in std_logic;
NextWrAdrxDO : out std_logic_vector(11 downto 0); -- memory address at which the next byte will be written
RExSI : in std_logic; -- initiate a memory read back
ReadBackAdrxDI : in std_logic_vector(11 downto 2); -- for speed up read back is only word adressable
ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
ReadBackDonexSO : out std_logic); -- indicates that requested read back data is available
end historyBuffer;
architecture Behavioral of historyBuffer is
signal WrPtrxDN, WrPtrxDP : std_logic_vector(11 downto 0) := (others => '0');
signal Ram0RdAdrAxD, Ram0RdAdrBxD : std_logic_vector(13 downto 0);
signal Ram1RdAdrAxD, Ram1RdAdrBxD : std_logic_vector(13 downto 0);
signal Ram0AdrAxD, Ram1AdrAxD : std_logic_vector(13 downto 0);
signal RamWrDataxD : std_logic_vector(31 downto 0);
signal Ram0OutAxD, Ram0OutBxD : std_logic_vector(31 downto 0);
signal Ram1OutAxD, Ram1OutBxD : std_logic_vector(31 downto 0);
signal Ram0WExS, Ram1WExS : std_logic_vector(3 downto 0);
signal Ram0EnAxS, Ram1EnAxS : std_logic;
signal RdAdrIntxD : integer; -- to split up long expressions (type casts)
signal Ram0RdAdrBasexD, Ram1RdAdrBasexD : integer;
signal DataReadyxSN, DataReadyxSP : std_logic;
signal LastReadBackAdrxDN, LastReadBackAdrxDP : std_logic_vector(11 downto 2);
begin
-- Note: If the requested address is not a multiple of 8 (ie bit 2 is 1) the
-- first word (4 bytes) we read is in ram 1. Therefore the adress for ram 0 has
-- to be incremented by 1.
RdAdrIntxD <= to_integer(unsigned(ReadBackAdrxDI(11 downto 3)));
Ram0RdAdrBasexD <= RdAdrIntxD when ReadBackAdrxDI(2) = '0' else (RdAdrIntxD+1);
Ram1RdAdrBasexD <= RdAdrIntxD;
Ram0RdAdrAxD <= std_logic_vector(to_unsigned(Ram0RdAdrBasexD, 9)) & "00000";
Ram0RdAdrBxD <= std_logic_vector(to_unsigned(Ram0RdAdrBasexD+1, 9)) & "00000";
Ram1RdAdrAxD <= std_logic_vector(to_unsigned(Ram1RdAdrBasexD, 9)) & "00000";
Ram1RdAdrBxD <= std_logic_vector(to_unsigned(Ram1RdAdrBasexD+1, 9)) & "00000";
-- select port A address based on read/write mode
Ram0AdrAxD <= Ram0RdAdrAxD when WExSI = '0' else (WrPtrxDP(11 downto 3)& "00000");
Ram1AdrAxD <= Ram1RdAdrAxD when WExSI = '0' else (WrPtrxDP(11 downto 3) & "00000");
-- Ram0AdrAxD <= Ram0RdAdrAxD when WExSI = '0' else (WrAdrxDI(11 downto 3)& "00000");
-- Ram1AdrAxD <= Ram1RdAdrAxD when WExSI = '0' else (WrAdrxDI(11 downto 3) & "00000");
RamWrDataxD <= WriteInxDI & WriteInxDI & WriteInxDI & WriteInxDI;
-- The memory behaves like a register -> save requested adress for output decoder
LastReadBackAdrxDN <= ReadBackAdrxDI;
-- the read back value is reordered depending on wether the requested address
-- is a multiple of 8 or not. See comment above.
ReadBackxDO <= (Ram1OutBxD & Ram0OutBxD & Ram1OutAxD & Ram0OutAxD) when LastReadBackAdrxDP(2) = '0' else (Ram0OutBxD & Ram1OutBxD & Ram0OutAxD & Ram1OutAxD);
Ram0EnAxS <= WExSI or RExSI;
Ram1EnAxS <= WExSI or RExSI;
-- implement a write address counter
wrCntPrcs : process (WExSI, WrPtrxDP)
begin
WrPtrxDN <= WrPtrxDP;
Ram0WExS <= "0000";
Ram1WExS <= "0000";
if WExSI = '1' then
if WrPtrxDP = x"fff" then
WrPtrxDN <= x"000";
else
WrPtrxDN <= std_logic_vector(to_unsigned(to_integer(unsigned(WrPtrxDP))+1, 12));
end if;
-- decode lower 3 bits to the 8 write enable lines
if WrPtrxDP(2) = '0' then
-- write to ram 0
Ram0WExS(to_integer(unsigned(WrPtrxDP(1 downto 0)))) <= '1';
else
Ram1WExS(to_integer(unsigned(WrPtrxDP(1 downto 0)))) <= '1';
end if;
-- if WrAdrxDI(2) = '0' then
-- -- write to ram 0
-- Ram0WExS(to_integer(unsigned(WrAdrxDI(1 downto 0)))) <= '1';
-- else
-- Ram1WExS(to_integer(unsigned(WrAdrxDI(1 downto 0)))) <= '1';
-- end if;
end if;
end process wrCntPrcs;
DataReadyxSN <= RExSI; -- it takes one clock cycle to read the
-- data, delay read enable for one cycle to create a output valid signal
NextWrAdrxDO <= WrPtrxDP;
ReadBackDonexSO <= DataReadyxSP;
process (ClkxCI, RstxRI)
begin -- process
if RstxRI = '1' then
LastReadBackAdrxDP <= (others => '0');
WrPtrxDP <= (others => '0');
DataReadyxSP <= '0';
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
LastReadBackAdrxDP <= LastReadBackAdrxDN;
WrPtrxDP <= WrPtrxDN;
DataReadyxSP <= DataReadyxSN;
end if;
end process;
-- port A is used to write and read (lower bytes) data, port B is for read only
HistMem0Inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36,
DATA_WIDTH_B => 36,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => Ram0OutAxD, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => Ram0OutBxD,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => Ram0AdrAxD, -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => Ram0EnAxS, -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => Ram0WExS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => RamWrDataxD, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => Ram0RdAdrBxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => RExSI, -- 1-bit B port enable input
REGCEB => '1', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
-- RAM 1
-- port A is used to write and read (lower bytes) data, port B is for read only
HistMem1Inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36,
DATA_WIDTH_B => 36,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => Ram1OutAxD, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => Ram1OutBxD,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => Ram1AdrAxD, -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => Ram1EnAxS, -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => Ram1WExS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => RamWrDataxD, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => Ram1RdAdrBxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => RExSI, -- 1-bit B port enable input
REGCEB => '1', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
end Behavioral;
|
gpl-2.0
|
f7767d54f7215786b03e8ec9a70a90ee
| 0.551842 | 3.935267 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/example_design/fifo_exdes.vhd
| 1 | 5,097 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_exdes;
architecture xilinx of fifo_exdes is
signal clk_i : std_logic;
component fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : fifo
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
mit
|
2ad4a37bffd853234c05bf86805af1cf
| 0.508142 | 4.803959 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
mux_4_single_bit.vhd
| 1 | 1,310 |
-- 4-input single-bit multiplexer
-- this circuit takes four single-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_4_single_bit is
port (
-- inputs
in_signal_0 : in std_logic;
in_signal_1 : in std_logic;
in_signal_2 : in std_logic;
in_signal_3 : in std_logic;
-- select signal
input_select : in std_logic_vector(1 downto 0);
-- output
out_signal : out std_logic
);
end entity mux_4_single_bit;
architecture mux_4_single_bit_arch of mux_4_single_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(in_signal_0, in_signal_1, in_signal_2, in_signal_3, input_select)
begin
-- select 00 is input 0
if input_select = "00" then
out_signal <= in_signal_0;
-- select 01 is input 1
elsif input_select = "01" then
out_signal <= in_signal_1;
-- select 10 is input 2
elsif input_select = "10" then
out_signal <= in_signal_2;
-- select 11 is input 3
elsif input_select = "11" then
out_signal <= in_signal_3;
-- otherwise invalid select signal, output 0
else
out_signal <= '0';
end if;
end process mux;
end architecture mux_4_single_bit_arch;
|
mit
|
099dcc395407d7087e927a238a78e207
| 0.675573 | 2.841649 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp_sub.vhd
| 1 | 253,996 |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: fp_sub.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="SUB" OPTIMIZE="SPEED" PIPELINE=7 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_add_sub 2010:03:24:20:34:20:SJ cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_sub_altbarrel_shift_h0e;
ARCHITECTURE RTL OF fp_sub_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) AND wire_lbarrel_shift_w678w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) AND wire_lbarrel_shift_w674w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) AND wire_lbarrel_shift_w699w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) AND wire_lbarrel_shift_w695w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) AND wire_lbarrel_shift_w721w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) AND wire_lbarrel_shift_w717w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) AND wire_lbarrel_shift_w743w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) AND wire_lbarrel_shift_w739w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) AND wire_lbarrel_shift_w765w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) AND wire_lbarrel_shift_w761w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w770w & wire_lbarrel_shift_w748w & wire_lbarrel_shift_w726w & wire_lbarrel_shift_w704w & wire_lbarrel_shift_w683w);
wire_lbarrel_shift_w674w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w678w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w695w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w699w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w717w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w721w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w739w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w743w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w761w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w765w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range771w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range771w;
END IF;
END IF;
END PROCESS;
END RTL; --fp_sub_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altbarrel_shift_6hb IS
PORT
(
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_sub_altbarrel_shift_6hb;
ARCHITECTURE RTL OF fp_sub_altbarrel_shift_6hb IS
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range779w793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range801w814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range822w836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w884w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w788w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w792w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w809w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w813w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w831w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w835w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w857w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w879w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range777w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range800w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) AND wire_rbarrel_shift_w792w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) AND wire_rbarrel_shift_w788w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) AND wire_rbarrel_shift_w813w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) AND wire_rbarrel_shift_w809w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) AND wire_rbarrel_shift_w835w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) AND wire_rbarrel_shift_w831w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) AND wire_rbarrel_shift_w857w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) AND wire_rbarrel_shift_w853w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) AND wire_rbarrel_shift_w879w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) AND wire_rbarrel_shift_w_sbit_w_range777w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) AND wire_rbarrel_shift_w_sbit_w_range800w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) AND wire_rbarrel_shift_w_sbit_w_range820w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) AND wire_rbarrel_shift_w_sbit_w_range842w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) AND wire_rbarrel_shift_w_sbit_w_range864w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0) <= NOT wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0) <= NOT wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0) <= NOT wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) <= NOT wire_rbarrel_shift_w_sel_w_range782w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) <= NOT wire_rbarrel_shift_w_sel_w_range803w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) <= NOT wire_rbarrel_shift_w_sel_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) <= NOT wire_rbarrel_shift_w_sel_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) <= NOT wire_rbarrel_shift_w_sel_w_range869w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w797w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w818w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w840w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w862w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w884w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w884w & wire_rbarrel_shift_w862w & wire_rbarrel_shift_w840w & wire_rbarrel_shift_w818w & wire_rbarrel_shift_w797w);
wire_rbarrel_shift_w788w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w792w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w809w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w813w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w831w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w835w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w853w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w857w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w879w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range779w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range801w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range822w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range842w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range864w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range777w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range800w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range820w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range782w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range803w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range825w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range847w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range869w(0) <= sel_w(4);
END RTL; --fp_sub_altbarrel_shift_6hb
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_3e8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --fp_sub_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_6e8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero920w921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero922w923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero920w & wire_altpriority_encoder14_w_lg_w_lg_zero922w923w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0) <= wire_altpriority_encoder14_w_lg_zero920w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero922w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero920w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero922w923w(0) <= wire_altpriority_encoder14_w_lg_zero922w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0);
altpriority_encoder14 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --fp_sub_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_be8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero910w911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero912w913w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero910w & wire_altpriority_encoder12_w_lg_w_lg_zero912w913w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i) <= wire_altpriority_encoder12_w_lg_zero910w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero912w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero910w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero912w913w(i) <= wire_altpriority_encoder12_w_lg_zero912w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i);
END GENERATE loop52;
altpriority_encoder12 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --fp_sub_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_sub_altpriority_encoder_3v7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --fp_sub_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_sub_altpriority_encoder_6v7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero945w946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero947w948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero945w & wire_altpriority_encoder18_w_lg_w_lg_zero947w948w);
altpriority_encoder17 : fp_sub_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0) <= wire_altpriority_encoder18_w_lg_zero945w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero947w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero945w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero947w948w(0) <= wire_altpriority_encoder18_w_lg_zero947w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0);
altpriority_encoder18 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --fp_sub_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_sub_altpriority_encoder_bv7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero936w937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero938w939w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero936w & wire_altpriority_encoder16_w_lg_w_lg_zero938w939w);
altpriority_encoder15 : fp_sub_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i) <= wire_altpriority_encoder16_w_lg_zero936w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero938w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero936w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero938w939w(i) <= wire_altpriority_encoder16_w_lg_zero938w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i);
END GENERATE loop55;
altpriority_encoder16 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --fp_sub_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_r08 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_sub_altpriority_encoder_r08;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_r08 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero901w902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero903w904w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero901w & wire_altpriority_encoder10_w_lg_w_lg_zero903w904w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i) <= wire_altpriority_encoder10_w_lg_zero901w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero903w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero901w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero903w904w(i) <= wire_altpriority_encoder10_w_lg_zero903w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i);
END GENERATE loop58;
altpriority_encoder10 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : fp_sub_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --fp_sub_altpriority_encoder_r08
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_rf8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_rf8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_rf8 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero957w958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero959w960w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero957w & wire_altpriority_encoder20_w_lg_w_lg_zero959w960w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i) <= wire_altpriority_encoder20_w_lg_zero957w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero959w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero957w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero959w960w(i) <= wire_altpriority_encoder20_w_lg_zero959w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i);
END GENERATE loop61;
altpriority_encoder20 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --fp_sub_altpriority_encoder_rf8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_qb6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_sub_altpriority_encoder_qb6;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_qb6 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero894w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero894w895w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_r08
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_rf8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder8_w_lg_zero892w & wire_altpriority_encoder8_w_lg_w_lg_zero894w895w);
altpriority_encoder7 : fp_sub_altpriority_encoder_r08
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero894w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero892w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero894w895w(i) <= wire_altpriority_encoder8_w_lg_zero894w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i);
END GENERATE loop64;
altpriority_encoder8 : fp_sub_altpriority_encoder_rf8
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
END RTL; --fp_sub_altpriority_encoder_qb6
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_nh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1004w1005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1004w1005w(0) <= NOT wire_altpriority_encoder27_w_data_range1004w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1004w1005w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1004w(0) <= data(0);
END RTL; --fp_sub_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_qh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero996w997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero998w999w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0) <= wire_altpriority_encoder27_w_lg_zero996w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero996w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0);
altpriority_encoder27 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --fp_sub_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_vh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero986w987w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero988w989w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i) <= wire_altpriority_encoder25_w_lg_zero986w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero988w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero986w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i);
END GENERATE loop67;
altpriority_encoder25 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --fp_sub_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_fj8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_fj8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_fj8 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero976w977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero978w979w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i) <= wire_altpriority_encoder23_w_lg_zero976w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero978w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero976w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i);
END GENERATE loop70;
altpriority_encoder23 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --fp_sub_altpriority_encoder_fj8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_sub_altpriority_encoder_n28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1038w1039w(0) <= NOT wire_altpriority_encoder34_w_data_range1038w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1038w1039w);
wire_altpriority_encoder34_w_data_range1038w(0) <= data(0);
END RTL; --fp_sub_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_sub_altpriority_encoder_q28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w);
wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0) <= wire_altpriority_encoder33_w_lg_zero1031w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1031w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0);
altpriority_encoder33 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : fp_sub_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --fp_sub_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_sub_altpriority_encoder_v28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i) <= wire_altpriority_encoder31_w_lg_zero1022w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1024w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1022w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i);
END GENERATE loop73;
altpriority_encoder31 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : fp_sub_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --fp_sub_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_f48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_sub_altpriority_encoder_f48;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_f48 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i) <= wire_altpriority_encoder29_w_lg_zero1013w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1015w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1013w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i);
END GENERATE loop76;
altpriority_encoder29 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : fp_sub_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --fp_sub_altpriority_encoder_f48
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_e48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_sub_altpriority_encoder_e48;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_e48 IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero967w968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero969w970w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_fj8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_f48
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero969w970w);
loop77 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i) <= wire_altpriority_encoder21_w_lg_zero967w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop77;
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero969w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop78;
wire_altpriority_encoder21_w_lg_zero967w(0) <= NOT wire_altpriority_encoder21_zero;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero969w970w(i) <= wire_altpriority_encoder21_w_lg_zero969w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i);
END GENERATE loop79;
altpriority_encoder21 : fp_sub_altpriority_encoder_fj8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : fp_sub_altpriority_encoder_f48
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
END RTL; --fp_sub_altpriority_encoder_e48
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 282
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altfp_add_sub_24k IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sub_altfp_add_sub_24k;
ARCHITECTURE RTL OF fp_sub_altfp_add_sub_24k IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w278w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w276w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w292w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_datab_sign_dffe15_wo336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range272w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range290w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_sub_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altbarrel_shift_6hb
PORT
(
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_qb6
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_e48
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop80 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w278w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w276w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND wire_w_exp_amb_w_range274w(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop89;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop93;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop95;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo338w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop96 : FOR i IN 0 TO 4 GENERATE
wire_w292w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) AND wire_w_exp_diff_abs_w_range290w(i);
END GENERATE loop96;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop97 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w279w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w273w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range272w(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop111;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= input_datab_infinite_dffe15_wo AND wire_w_lg_aligned_datab_sign_dffe15_wo336w(0);
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop112 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w(i) <= wire_w_exp_diff_abs_exceed_max_w_range289w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop112;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop113 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop116;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_aligned_datab_sign_dffe15_wo336w(0) <= NOT aligned_datab_sign_dffe15_wo;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w275w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo338w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range289w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop117 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop120;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w(0) <= wire_w_exp_diff_abs_exceed_max_w_range282w(0) OR wire_w_exp_diff_abs_w_range284w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w(0) <= wire_w_exp_diff_abs_exceed_max_w_range286w(0) OR wire_w_exp_diff_abs_w_range287w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo);
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12_wi;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13_wi;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14_wi;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12_wi;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13_wi;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14_wi;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12_wi;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13_wi;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14_wi;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12_wi;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13_wi;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14_wi;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12_wi;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13_wi;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14_wi;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12_wi;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13_wi;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14_wi;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41_wi;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23_wi;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13_wi;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14_wi;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w275w276w OR wire_w_lg_exp_amb_mux_w273w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41_wi;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23_wi;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27_wi;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) OR wire_w_lg_input_datab_infinite_dffe15_wo337w(0));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23_wi;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27_wi;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41_wi;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41_wi;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23_wi;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27_wi;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41_wi;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12_wi;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13_wi;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14_wi;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12_wi;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12_wi;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13_wi;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14_wi;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12_wi;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23_wi;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27_wi;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41_wi;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13_wi;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14_wi;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23_wi;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27_wi;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41_wi;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23_wi;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27_wi;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23_wi;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27_wi;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41_wi;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23_wi;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13_wi;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w279w OR wire_w_lg_w_lg_exp_amb_mux_w275w278w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23_wi;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13_wi;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14_wi;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w OR wire_w292w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41_wi;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23_wi;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27_wi;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23_wi;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27_wi;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range274w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range272w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range282w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range286w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range289w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range290w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range284w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range287w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : fp_sub_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : fp_sub_altbarrel_shift_6hb
PORT MAP (
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : fp_sub_altpriority_encoder_qb6
PORT MAP (
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : fp_sub_altpriority_encoder_e48
PORT MAP (
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop121 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop122;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop123;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop125;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop126;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop127 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop129;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --fp_sub_altfp_add_sub_24k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sub;
ARCHITECTURE RTL OF fp_sub IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_sub_altfp_add_sub_24k
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_sub_altfp_add_sub_24k_component : fp_sub_altfp_add_sub_24k
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
59e29feb9ffbb1dc14b7d2c59ad9faf1
| 0.704523 | 2.425848 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/outputFIFOTb.vhd
| 1 | 7,323 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/8/12 - LS
--* started file
--*
--* Version 1.0 - 2013/4/5 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Test bench for outputFIFO.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity outputFIFO_tb is
end outputFIFO_tb;
architecture tb of outputFIFO_tb is
component outputFIFO
generic (
frameSize : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
BodyDataxDI : in std_logic_vector(7 downto 0);
BodyStrobexSI : in std_logic;
HeaderDataxDI : in std_logic_vector(frameSize-1 downto 0);
HeaderStrobexSI : in std_logic;
BuffersEmptyxSO : out std_logic;
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024);
end component;
-- component generics
constant frameSize : integer := 8;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal BodyDataxDI : std_logic_vector(7 downto 0) := (others => '0');
signal BodyStrobexSI : std_logic := '0';
signal HeaderDataxDI : std_logic_vector(frameSize-1 downto 0) := (others => '0');
signal HeaderStrobexSI : std_logic := '0';
signal BuffersEmptyxSO : std_logic;
signal BufOutxDO : std_logic_vector(7 downto 0);
signal OutputValidxSO : std_logic;
signal RdStrobexSI : std_logic := '0';
signal LengthxDO : integer range 0 to 1024;
-- clock
signal Clk : std_logic := '1';
constant PERIOD : time := 20ns;
begin -- tb
-- component instantiation
DUT : outputFIFO
generic map (
frameSize => frameSize)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
BodyDataxDI => BodyDataxDI,
BodyStrobexSI => BodyStrobexSI,
HeaderDataxDI => HeaderDataxDI,
HeaderStrobexSI => HeaderStrobexSI,
BuffersEmptyxSO => BuffersEmptyxSO,
BufOutxDO => BufOutxDO,
OutputValidxSO => OutputValidxSO,
RdStrobexSI => RdStrobexSI,
LengthxDO => LengthxDO);
-- clock generation
Clk <= not Clk after PERIOD/2;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
begin
wait for 20 ns;
wait until ClkxCI'event and ClkxCI = '1';
RstxRI <= '0';
-- send a data frame with an odd number of bytes (header and body)
BodyDataxDI <= x"00";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"01";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"00";
BodyStrobexSI <= '0';
HeaderDataxDI <= x"0f";
HeaderStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"00";
BodyStrobexSI <= '0';
HeaderDataxDI <= x"00";
HeaderStrobexSI <= '0';
-- send a data frame to the input buffer
BodyDataxDI <= x"10";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"11";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"12";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"13";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"14";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"15";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"16";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"17";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"18";
HeaderDataxDI <= x"1f";
HeaderStrobexSI <= '1';
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
HeaderStrobexSI <= '0';
HeaderDataxDI <= x"00";
BodyDataxDI <= x"00";
-- send a short frame (this is allowed for the last frame only)
BodyDataxDI <= x"ff";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '1';
HeaderStrobexSI <= '1';
HeaderDataxDI <= x"ff";
BodyDataxDI <= x"ff";
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
HeaderStrobexSI <= '0';
HeaderDataxDI <= x"00";
BodyDataxDI <= x"00";
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '1';
wait for 15 * PERIOD;
RdStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
-- try illegal read
RdStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '0';
wait;
end process WaveGen_Proc;
end tb;
configuration outputFIFO_tb_tb_cfg of outputFIFO_tb is
for tb
end for;
end outputFIFO_tb_tb_cfg;
|
gpl-2.0
|
9af60da776167e3a23a3c743842645e7
| 0.546497 | 4.348575 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
data_bus.vhd
| 1 | 3,081 |
-- data bus, connects internal memory interface to i/o ports and internal/external memory
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- declaring array for i/o port
package io_port_type is
type io_port is array(15 downto 0) of std_logic_vector(7 downto 0);
end package io_port_type;
use work.io_port_type.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity data_bus is
port (
-- address in
addr : in std_logic_vector(31 downto 0);
-- data from/to interface
interface_data : inout std_logic_vector(7 downto 0);
-- clk and w/r
clk : in std_logic;
wr : in std_logic;
-- data from/to i/o
io_data : inout io_port;
-- internal memory addr, data, clk
int_mem_addr : out std_logic_vector(9 downto 0);
int_mem_data : inout std_logic_vector(7 downto 0);
int_mem_clk : out std_logic;
-- external memory addr, data, clk
ext_mem_addr : out std_logic_vector(31 downto 0);
ext_mem_data : inout std_logic_vector(7 downto 0);
ext_mem_clk : out std_logic
);
end entity data_bus;
architecture data_bus_arch of data_bus is
-- internal bank selection
signal bank : integer;
begin
-- design implementation
data_bus_process : process(clk, addr)
begin
if to_integer(unsigned(addr)) > 1040 then
-- select external memory
bank <= 2;
-- set external memory address
ext_mem_addr <= std_logic_vector(unsigned(addr) - to_unsigned(1041, 32));
-- if writing, set data
if wr = '1' then
ext_mem_data <= interface_data;
end if;
-- reset internal mem signals
int_mem_addr <= (others => '0');
int_mem_data <= (others => '0');
elsif to_integer(unsigned(addr)) > 15 then
-- select internal memory
bank <= 1;
-- set internal memory address
int_mem_addr <= std_logic_vector(unsigned(addr) - to_unsigned(15, 32))(9 downto 0);
-- if writing, set data
if wr = '1' then
int_mem_data <= interface_data;
end if;
-- reset external mem signals
ext_mem_addr <= (others => '0');
ext_mem_data <= (others => '0');
else
-- select i/o ports
bank <= 0;
end if;
-- on clock rising edge, read or write from selected bank
if rising_edge(clk) then
-- read or write i/o
if bank <= 0 then
if wr = '1' then
io_data(to_integer(unsigned(addr))) <= interface_data;
else
interface_data <= io_data(to_integer(unsigned(addr)));
end if;
-- read or write internal memory
elsif bank <= 1 then
if wr = '1' then
int_mem_clk <= '1';
else
interface_data <= int_mem_data;
end if;
-- read or write external memory
elsif bank <= 2 then
if wr = '1' then
ext_mem_clk <= '1';
else
interface_data <= ext_mem_data;
end if;
end if;
end if;
-- on clock falling edge, reset secondary clocks
if falling_edge(clk) then
ext_mem_clk <= '0';
int_mem_clk <= '0';
end if;
end process data_bus_process;
end architecture data_bus_arch;
|
mit
|
4cda769472a62a2bd25f3aa38c2339bf
| 0.627718 | 2.942693 | false | false | false | false |
jpendlum/crash
|
fpga/src/toplevel_testbench/toplevel_testbench.vhd
| 2 | 89,085 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: toplevel_testbench.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Testbench for toplevel file for the Zedboard, ZC702, and ZC706.
-- Does not simulate the processor system, but it does simulate
-- the AXI ACP and AXI GP ports used for DMA transfers and
-- control / status register access.
--
-- The testbench does the following:
-- - Simulates the modified USRP firmware and simulates it
-- receiving a sinusoid. This is used to trigger the
-- threshold detection portion of the Spectrum Sensing block.
-- - Reads and writes 256 words over AXI ACP to test the interface.
-- - Sets up a transmission by reading 4096 words over AXI ACP and
-- buffering them. These words will be sent to the transmit
-- path of the USRP DDR Interface block when TX is enabled via
-- a control register.
-- - Sets up the Spectrum Sense block to trigger the USRP DDR
-- Interface block when the threshold is exceeded.
-- - Sets up the USRP DDR Interface block to receive sample and
-- filter sample data.
--
-- All of these steps together simulate the code detecting a
-- sinusoid and triggering a tranmission due to that signal.
-- It is also possible to configure the system to transmit when
-- the threshold is not exceeded in the Spectrum Sensing block,
-- i.e. transmit when detecting the absence of the sinusoid signal.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity toplevel_testbench is
end entity;
architecture Testbench of toplevel_testbench is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component ps_pl_interface is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
-- AXIS Stream Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- AXI-Lite Slave bus for access to control & status registers
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI ACP Bus to interface with processor system
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Interrupt on successfully completed AXI ACP writes
irq : out std_logic;
-- Global reset for all accelerators
rst_glb_n : out std_logic;
-- Accelerator interfaces
-- Note: Master & Slave 0 are not listed as the Datamover componeent
-- uses both.
-- Accelerator 1
axis_master_1_tvalid : in std_logic;
axis_master_1_tready : out std_logic;
axis_master_1_tdata : in std_logic_vector(63 downto 0);
axis_master_1_tdest : in std_logic_vector(2 downto 0);
axis_master_1_tlast : in std_logic;
axis_master_1_irq : in std_logic;
axis_slave_1_tvalid : out std_logic;
axis_slave_1_tready : in std_logic;
axis_slave_1_tdata : out std_logic_vector(63 downto 0);
axis_slave_1_tid : out std_logic_vector(2 downto 0);
axis_slave_1_tlast : out std_logic;
axis_slave_1_irq : in std_logic;
status_1_addr : out std_logic_vector(7 downto 0);
status_1_data : in std_logic_vector(31 downto 0);
status_1_stb : out std_logic;
ctrl_1_addr : out std_logic_vector(7 downto 0);
ctrl_1_data : out std_logic_vector(31 downto 0);
ctrl_1_stb : out std_logic;
-- Accelerator 2
axis_master_2_tvalid : in std_logic;
axis_master_2_tready : out std_logic;
axis_master_2_tdata : in std_logic_vector(63 downto 0);
axis_master_2_tdest : in std_logic_vector(2 downto 0);
axis_master_2_tlast : in std_logic;
axis_master_2_irq : in std_logic;
axis_slave_2_tvalid : out std_logic;
axis_slave_2_tready : in std_logic;
axis_slave_2_tdata : out std_logic_vector(63 downto 0);
axis_slave_2_tid : out std_logic_vector(2 downto 0);
axis_slave_2_tlast : out std_logic;
axis_slave_2_irq : in std_logic;
status_2_addr : out std_logic_vector(7 downto 0);
status_2_data : in std_logic_vector(31 downto 0);
status_2_stb : out std_logic;
ctrl_2_addr : out std_logic_vector(7 downto 0);
ctrl_2_data : out std_logic_vector(31 downto 0);
ctrl_2_stb : out std_logic;
-- Accelerator 3
axis_master_3_tvalid : in std_logic;
axis_master_3_tready : out std_logic;
axis_master_3_tdata : in std_logic_vector(63 downto 0);
axis_master_3_tdest : in std_logic_vector(2 downto 0);
axis_master_3_tlast : in std_logic;
axis_master_3_irq : in std_logic;
axis_slave_3_tvalid : out std_logic;
axis_slave_3_tready : in std_logic;
axis_slave_3_tdata : out std_logic_vector(63 downto 0);
axis_slave_3_tid : out std_logic_vector(2 downto 0);
axis_slave_3_tlast : out std_logic;
axis_slave_3_irq : in std_logic;
status_3_addr : out std_logic_vector(7 downto 0);
status_3_data : in std_logic_vector(31 downto 0);
status_3_stb : out std_logic;
ctrl_3_addr : out std_logic_vector(7 downto 0);
ctrl_3_data : out std_logic_vector(31 downto 0);
ctrl_3_stb : out std_logic;
-- Accelerator 4
axis_master_4_tvalid : in std_logic;
axis_master_4_tready : out std_logic;
axis_master_4_tdata : in std_logic_vector(63 downto 0);
axis_master_4_tdest : in std_logic_vector(2 downto 0);
axis_master_4_tlast : in std_logic;
axis_master_4_irq : in std_logic;
axis_slave_4_tvalid : out std_logic;
axis_slave_4_tready : in std_logic;
axis_slave_4_tdata : out std_logic_vector(63 downto 0);
axis_slave_4_tid : out std_logic_vector(2 downto 0);
axis_slave_4_tlast : out std_logic;
axis_slave_4_irq : in std_logic;
status_4_addr : out std_logic_vector(7 downto 0);
status_4_data : in std_logic_vector(31 downto 0);
status_4_stb : out std_logic;
ctrl_4_addr : out std_logic_vector(7 downto 0);
ctrl_4_data : out std_logic_vector(31 downto 0);
ctrl_4_stb : out std_logic;
-- Accelerator 5
axis_master_5_tvalid : in std_logic;
axis_master_5_tready : out std_logic;
axis_master_5_tdata : in std_logic_vector(63 downto 0);
axis_master_5_tdest : in std_logic_vector(2 downto 0);
axis_master_5_tlast : in std_logic;
axis_master_5_irq : in std_logic;
axis_slave_5_tvalid : out std_logic;
axis_slave_5_tready : in std_logic;
axis_slave_5_tdata : out std_logic_vector(63 downto 0);
axis_slave_5_tid : out std_logic_vector(2 downto 0);
axis_slave_5_tlast : out std_logic;
axis_slave_5_irq : in std_logic;
status_5_addr : out std_logic_vector(7 downto 0);
status_5_data : in std_logic_vector(31 downto 0);
status_5_stb : out std_logic;
ctrl_5_addr : out std_logic_vector(7 downto 0);
ctrl_5_data : out std_logic_vector(31 downto 0);
ctrl_5_stb : out std_logic;
-- Accelerator 6
axis_master_6_tvalid : in std_logic;
axis_master_6_tready : out std_logic;
axis_master_6_tdata : in std_logic_vector(63 downto 0);
axis_master_6_tdest : in std_logic_vector(2 downto 0);
axis_master_6_tlast : in std_logic;
axis_master_6_irq : in std_logic;
axis_slave_6_tvalid : out std_logic;
axis_slave_6_tready : in std_logic;
axis_slave_6_tdata : out std_logic_vector(63 downto 0);
axis_slave_6_tid : out std_logic_vector(2 downto 0);
axis_slave_6_tlast : out std_logic;
axis_slave_6_irq : in std_logic;
status_6_addr : out std_logic_vector(7 downto 0);
status_6_data : in std_logic_vector(31 downto 0);
status_6_stb : out std_logic;
ctrl_6_addr : out std_logic_vector(7 downto 0);
ctrl_6_data : out std_logic_vector(31 downto 0);
ctrl_6_stb : out std_logic;
-- Accelerator 7
axis_master_7_tvalid : in std_logic;
axis_master_7_tready : out std_logic;
axis_master_7_tdata : in std_logic_vector(63 downto 0);
axis_master_7_tdest : in std_logic_vector(2 downto 0);
axis_master_7_tlast : in std_logic;
axis_master_7_irq : in std_logic;
axis_slave_7_tvalid : out std_logic;
axis_slave_7_tready : in std_logic;
axis_slave_7_tdata : out std_logic_vector(63 downto 0);
axis_slave_7_tid : out std_logic_vector(2 downto 0);
axis_slave_7_tlast : out std_logic;
axis_slave_7_irq : in std_logic;
status_7_addr : out std_logic_vector(7 downto 0);
status_7_data : in std_logic_vector(31 downto 0);
status_7_stb : out std_logic;
ctrl_7_addr : out std_logic_vector(7 downto 0);
ctrl_7_data : out std_logic_vector(31 downto 0);
ctrl_7_stb : out std_logic);
end component;
component usrp_ddr_intf_axis is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 1e6); -- UART baud rate
port (
-- USRP Interface
UART_TX : out std_logic; -- UART
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(4 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(4 downto 0); -- Receive data (P)
RX_DATA_STB_N : in std_logic; -- Receive data strobe (N)
RX_DATA_STB_P : in std_logic; -- Receive data strobe (P)
TX_DATA_N : out std_logic_vector(5 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(5 downto 0); -- Transmit data (P)
TX_DATA_STB_N : out std_logic; -- Transmit data strobe (N)
TX_DATA_STB_P : out std_logic; -- Transmit data strobe (P)
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (DAC / TX Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (ADC / RX Data)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
rx_enable_aux : in std_logic;
tx_enable_aux : in std_logic);
end component;
component spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end component;
component bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end component;
component crash_ddr_intf is
generic (
CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 1e6); -- UART baud rate
port (
clk : in std_logic; -- Clock (from ADC)
reset : in std_logic; -- Active high reset
RX_DATA_CLK_N : out std_logic; -- RX data clock (P)
RX_DATA_CLK_P : out std_logic; -- RX data clock (N)
RX_DATA_N : out std_logic_vector(4 downto 0); -- RX data (P)
RX_DATA_P : out std_logic_vector(4 downto 0); -- RX data (N)
RX_DATA_STB_N : out std_logic; -- RX data strobe (N)
RX_DATA_STB_P : out std_logic; -- RX data strobe (N)
TX_DATA_N : in std_logic_vector(5 downto 0); -- TX data (P)
TX_DATA_P : in std_logic_vector(5 downto 0); -- TX data (N)
TX_DATA_STB_N : in std_logic; -- TX data strobe (N)
TX_DATA_STB_P : in std_logic; -- TX data strobe (N)
UART_RX : in std_logic; -- Control interface from CRUSH (RX)
-- CRASH RX data signals
adc_i : in std_logic_vector(13 downto 0); -- ADC data I, raw sample data
adc_q : in std_logic_vector(13 downto 0); -- ADC data Q, raw sample data
adc_dc_off_i : in std_logic_vector(23 downto 0); -- ADC data I, with DC offset correction & IQ balance
adc_dc_off_q : in std_logic_vector(23 downto 0); -- ADC data Q, with DC offset correction & IQ balance
-- Following signals come from USRP firmware and are used when bypassing CRASH functionality
dac_usrp_i : in std_logic_vector(15 downto 0); -- DAC data I from USRP, raw sample data
dac_usrp_q : in std_logic_vector(15 downto 0); -- DAC data Q from USRP, raw sample data
dac_usrp_dc_off_i : in std_logic_vector(23 downto 0); -- DAC data I from USRP, before DC offset correction & IQ balance
dac_usrp_dc_off_q : in std_logic_vector(23 downto 0); -- DAC data Q from USRP, before DC offset correction & IQ balance
-- CRASH TX data signals
dac_i : out std_logic_vector(15 downto 0); -- DAC data I, raw sample data
dac_q : out std_logic_vector(15 downto 0); -- DAC data Q, raw sample data
dac_dc_off_i : out std_logic_vector(23 downto 0); -- DAC data I, before DC offset correction & IQ balance
dac_dc_off_q : out std_logic_vector(23 downto 0)); -- DAC data Q, before DC offset correction & IQ balance
end component;
-----------------------------------------------------------------------------
-- Constants Declaration
-----------------------------------------------------------------------------
constant AXIS_CLOCK_RATE : real := 150.0e6;
constant AXIS_CLOCK_PERIOD : time := (1.0e12/AXIS_CLOCK_RATE)*(1 ps);
constant CLOCK_RATE_100MHz : real := 100.0e6;
constant CLOCK_PERIOD_100MHz : time := (1.0e12/CLOCK_RATE_100MHz)*(1 ps);
constant TIMEOUT : time := 5 sec;
-- Control registers
constant REG_USRP_MODE : std_logic_vector(31 downto 0) := x"00000001";
constant REG_RX_PKT_SIZE : std_logic_vector(31 downto 0) := x"00000002";
constant REG_RX_DECIM : std_logic_vector(31 downto 0) := x"00000003";
constant REG_RX_GAIN : std_logic_vector(31 downto 0) := x"00000004";
constant REG_TXRX_RESET : std_logic_vector(31 downto 0) := x"00000005";
constant REG_TX_INTERP : std_logic_vector(31 downto 0) := x"00000006";
constant REG_TX_GAIN : std_logic_vector(31 downto 0) := x"00000007";
constant REG_TXRX_MMCM_PHASE_INIT : std_logic_vector(31 downto 0) := x"00000008";
constant REG_TXRX_MMCM_PHASE_ADJ : std_logic_vector(31 downto 0) := x"00000009";
constant REG_MISC : std_logic_vector(31 downto 0) := x"0000000A";
-- Crash commands
constant CMD_TX_MODE : std_logic_vector(3 downto 0) := x"1";
constant CMD_RX_MODE : std_logic_vector(3 downto 0) := x"2";
-- RX modes (lower nibble)
constant RX_ADC_RAW_MODE : std_logic_vector(3 downto 0) := x"0";
constant RX_ADC_DC_OFF_MODE : std_logic_vector(3 downto 0) := x"1";
constant RX_SINE_TEST_MODE : std_logic_vector(3 downto 0) := x"2";
constant RX_TEST_PATTERN_MODE : std_logic_vector(3 downto 0) := x"3";
constant RX_ALL_1s_MODE : std_logic_vector(3 downto 0) := x"4";
constant RX_ALL_0s_MODE : std_logic_vector(3 downto 0) := x"5";
constant RX_I_1s_Q_0s_MODE : std_logic_vector(3 downto 0) := x"6";
constant RX_I_0s_Q_1s_MODE : std_logic_vector(3 downto 0) := x"7";
constant RX_CHECK_ALIGN_MODE : std_logic_vector(3 downto 0) := x"8";
constant RX_TX_LOOPBACK_MODE : std_logic_vector(3 downto 0) := x"9";
-- TX modes (upper nibble)
constant TX_PASSTHRU_MODE : std_logic_vector(3 downto 0) := x"0";
constant TX_DAC_RAW_MODE : std_logic_vector(3 downto 0) := x"1";
constant TX_DAC_DC_OFF_MODE : std_logic_vector(3 downto 0) := x"2";
constant TX_SINE_TEST_MODE : std_logic_vector(3 downto 0) := x"3";
-----------------------------------------------------------------------------
-- Signal Declaration
-----------------------------------------------------------------------------
signal axis_clk : std_logic;
signal axis_rst_n : std_logic;
signal clk_100MHz : std_logic;
signal reset : std_logic;
signal S_AXI_AWADDR : std_logic_vector(31 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(31 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
signal M_AXI_AWADDR : std_logic_vector(31 downto 0);
signal M_AXI_AWPROT : std_logic_vector(2 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_AWREADY : std_logic;
signal M_AXI_WDATA : std_logic_vector(63 downto 0);
signal M_AXI_WSTRB : std_logic_vector(7 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_WREADY : std_logic;
signal M_AXI_BRESP : std_logic_vector(1 downto 0);
signal M_AXI_BVALID : std_logic;
signal M_AXI_BREADY : std_logic;
signal M_AXI_AWLEN : std_logic_vector(7 downto 0);
signal M_AXI_AWSIZE : std_logic_vector(2 downto 0);
signal M_AXI_AWBURST : std_logic_vector(1 downto 0);
signal M_AXI_AWCACHE : std_logic_vector(3 downto 0);
signal M_AXI_AWUSER : std_logic_vector(4 downto 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_ARADDR : std_logic_vector(31 downto 0);
signal M_AXI_ARPROT : std_logic_vector(2 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_ARREADY : std_logic;
signal M_AXI_RDATA : std_logic_vector(63 downto 0);
signal M_AXI_RRESP : std_logic_vector(1 downto 0);
signal M_AXI_RVALID : std_logic;
signal M_AXI_RREADY : std_logic;
signal M_AXI_RLAST : std_logic;
signal M_AXI_ARCACHE : std_logic_vector(3 downto 0);
signal M_AXI_ARUSER : std_logic_vector(4 downto 0);
signal M_AXI_ARLEN : std_logic_vector(7 downto 0);
signal M_AXI_ARBURST : std_logic_vector(1 downto 0);
signal M_AXI_ARSIZE : std_logic_vector(2 downto 0);
signal irq : std_logic;
signal rst_glb_n : std_logic;
signal axis_master_1_tvalid : std_logic;
signal axis_master_1_tready : std_logic;
signal axis_master_1_tdata : std_logic_vector(63 downto 0);
signal axis_master_1_tdest : std_logic_vector(2 downto 0);
signal axis_master_1_tlast : std_logic;
signal axis_master_1_irq : std_logic;
signal axis_slave_1_tvalid : std_logic;
signal axis_slave_1_tready : std_logic;
signal axis_slave_1_tdata : std_logic_vector(63 downto 0);
signal axis_slave_1_tid : std_logic_vector(2 downto 0);
signal axis_slave_1_tlast : std_logic;
signal axis_slave_1_irq : std_logic;
signal status_1_addr : std_logic_vector(7 downto 0);
signal status_1_data : std_logic_vector(31 downto 0);
signal status_1_stb : std_logic;
signal ctrl_1_addr : std_logic_vector(7 downto 0);
signal ctrl_1_data : std_logic_vector(31 downto 0);
signal ctrl_1_stb : std_logic;
signal axis_master_2_tvalid : std_logic;
signal axis_master_2_tready : std_logic;
signal axis_master_2_tdata : std_logic_vector(63 downto 0);
signal axis_master_2_tdest : std_logic_vector(2 downto 0);
signal axis_master_2_tlast : std_logic;
signal axis_master_2_irq : std_logic;
signal axis_slave_2_tvalid : std_logic;
signal axis_slave_2_tready : std_logic;
signal axis_slave_2_tdata : std_logic_vector(63 downto 0);
signal axis_slave_2_tid : std_logic_vector(2 downto 0);
signal axis_slave_2_tlast : std_logic;
signal axis_slave_2_irq : std_logic;
signal status_2_addr : std_logic_vector(7 downto 0);
signal status_2_data : std_logic_vector(31 downto 0);
signal status_2_stb : std_logic;
signal ctrl_2_addr : std_logic_vector(7 downto 0);
signal ctrl_2_data : std_logic_vector(31 downto 0);
signal ctrl_2_stb : std_logic;
signal axis_master_3_tvalid : std_logic;
signal axis_master_3_tready : std_logic;
signal axis_master_3_tdata : std_logic_vector(63 downto 0);
signal axis_master_3_tdest : std_logic_vector(2 downto 0);
signal axis_master_3_tlast : std_logic;
signal axis_master_3_irq : std_logic;
signal axis_slave_3_tvalid : std_logic;
signal axis_slave_3_tready : std_logic;
signal axis_slave_3_tdata : std_logic_vector(63 downto 0);
signal axis_slave_3_tid : std_logic_vector(2 downto 0);
signal axis_slave_3_tlast : std_logic;
signal axis_slave_3_irq : std_logic;
signal status_3_addr : std_logic_vector(7 downto 0);
signal status_3_data : std_logic_vector(31 downto 0);
signal status_3_stb : std_logic;
signal ctrl_3_addr : std_logic_vector(7 downto 0);
signal ctrl_3_data : std_logic_vector(31 downto 0);
signal ctrl_3_stb : std_logic;
signal axis_master_4_tvalid : std_logic;
signal axis_master_4_tready : std_logic;
signal axis_master_4_tdata : std_logic_vector(63 downto 0);
signal axis_master_4_tdest : std_logic_vector(2 downto 0);
signal axis_master_4_tlast : std_logic;
signal axis_master_4_irq : std_logic;
signal axis_slave_4_tvalid : std_logic;
signal axis_slave_4_tready : std_logic;
signal axis_slave_4_tdata : std_logic_vector(63 downto 0);
signal axis_slave_4_tid : std_logic_vector(2 downto 0);
signal axis_slave_4_tlast : std_logic;
signal axis_slave_4_irq : std_logic;
signal status_4_addr : std_logic_vector(7 downto 0);
signal status_4_data : std_logic_vector(31 downto 0);
signal status_4_stb : std_logic;
signal ctrl_4_addr : std_logic_vector(7 downto 0);
signal ctrl_4_data : std_logic_vector(31 downto 0);
signal ctrl_4_stb : std_logic;
signal axis_master_5_tvalid : std_logic;
signal axis_master_5_tready : std_logic;
signal axis_master_5_tdata : std_logic_vector(63 downto 0);
signal axis_master_5_tdest : std_logic_vector(2 downto 0);
signal axis_master_5_tlast : std_logic;
signal axis_master_5_irq : std_logic;
signal axis_slave_5_tvalid : std_logic;
signal axis_slave_5_tready : std_logic;
signal axis_slave_5_tdata : std_logic_vector(63 downto 0);
signal axis_slave_5_tid : std_logic_vector(2 downto 0);
signal axis_slave_5_tlast : std_logic;
signal axis_slave_5_irq : std_logic;
signal status_5_addr : std_logic_vector(7 downto 0);
signal status_5_data : std_logic_vector(31 downto 0);
signal status_5_stb : std_logic;
signal ctrl_5_addr : std_logic_vector(7 downto 0);
signal ctrl_5_data : std_logic_vector(31 downto 0);
signal ctrl_5_stb : std_logic;
signal axis_master_6_tvalid : std_logic;
signal axis_master_6_tready : std_logic;
signal axis_master_6_tdata : std_logic_vector(63 downto 0);
signal axis_master_6_tdest : std_logic_vector(2 downto 0);
signal axis_master_6_tlast : std_logic;
signal axis_master_6_irq : std_logic;
signal axis_slave_6_tvalid : std_logic;
signal axis_slave_6_tready : std_logic;
signal axis_slave_6_tdata : std_logic_vector(63 downto 0);
signal axis_slave_6_tid : std_logic_vector(2 downto 0);
signal axis_slave_6_tlast : std_logic;
signal axis_slave_6_irq : std_logic;
signal status_6_addr : std_logic_vector(7 downto 0);
signal status_6_data : std_logic_vector(31 downto 0);
signal status_6_stb : std_logic;
signal ctrl_6_addr : std_logic_vector(7 downto 0);
signal ctrl_6_data : std_logic_vector(31 downto 0);
signal ctrl_6_stb : std_logic;
signal axis_master_7_tvalid : std_logic;
signal axis_master_7_tready : std_logic;
signal axis_master_7_tdata : std_logic_vector(63 downto 0);
signal axis_master_7_tdest : std_logic_vector(2 downto 0);
signal axis_master_7_tlast : std_logic;
signal axis_master_7_irq : std_logic;
signal axis_slave_7_tvalid : std_logic;
signal axis_slave_7_tready : std_logic;
signal axis_slave_7_tdata : std_logic_vector(63 downto 0);
signal axis_slave_7_tid : std_logic_vector(2 downto 0);
signal axis_slave_7_tlast : std_logic;
signal axis_slave_7_irq : std_logic;
signal status_7_addr : std_logic_vector(7 downto 0);
signal status_7_data : std_logic_vector(31 downto 0);
signal status_7_stb : std_logic;
signal ctrl_7_addr : std_logic_vector(7 downto 0);
signal ctrl_7_data : std_logic_vector(31 downto 0);
signal ctrl_7_stb : std_logic;
signal UART_TX : std_logic;
signal RX_DATA_CLK_N : std_logic;
signal RX_DATA_CLK_P : std_logic;
signal RX_DATA_N : std_logic_vector(4 downto 0);
signal RX_DATA_P : std_logic_vector(4 downto 0);
signal RX_DATA_STB_N : std_logic;
signal RX_DATA_STB_P : std_logic;
signal TX_DATA_N : std_logic_vector(5 downto 0);
signal TX_DATA_P : std_logic_vector(5 downto 0);
signal TX_DATA_STB_N : std_logic;
signal TX_DATA_STB_P : std_logic;
signal rx_enable_aux : std_logic;
signal tx_enable_aux : std_logic;
signal threshold_not_exceeded : std_logic;
signal threshold_not_exceeded_stb : std_logic;
signal threshold_exceeded : std_logic;
signal threshold_exceeded_stb : std_logic;
signal trigger_stb : std_logic;
signal adc_i : std_logic_vector(13 downto 0);
signal adc_q : std_logic_vector(13 downto 0);
signal adc_dc_off_i : std_logic_vector(23 downto 0);
signal adc_dc_off_q : std_logic_vector(23 downto 0);
signal dac_usrp_i : std_logic_vector(15 downto 0);
signal dac_usrp_q : std_logic_vector(15 downto 0);
signal dac_usrp_dc_off_i : std_logic_vector(23 downto 0);
signal dac_usrp_dc_off_q : std_logic_vector(23 downto 0);
signal dac_i : std_logic_vector(15 downto 0);
signal dac_q : std_logic_vector(15 downto 0);
signal dac_dc_off_i : std_logic_vector(23 downto 0);
signal dac_dc_off_q : std_logic_vector(23 downto 0);
signal RX_DATA_CLK_N_wire_dly : std_logic;
signal RX_DATA_CLK_P_wire_dly : std_logic;
signal RX_DATA_N_wire_dly : std_logic_vector(4 downto 0);
signal RX_DATA_P_wire_dly : std_logic_vector(4 downto 0);
signal RX_DATA_STB_N_wire_dly : std_logic;
signal RX_DATA_STB_P_wire_dly : std_logic;
signal TX_DATA_N_wire_dly : std_logic_vector(5 downto 0);
signal TX_DATA_P_wire_dly : std_logic_vector(5 downto 0);
signal TX_DATA_STB_N_wire_dly : std_logic;
signal TX_DATA_STB_P_wire_dly : std_logic;
type slv_8192x64 is array(0 to 8192) of std_logic_vector(63 downto 0);
signal ram : slv_8192x64 := (others=>(others=>'0'));
signal addr_inc : integer;
signal set_ctrl : std_logic;
signal set_ctrl_busy : std_logic;
signal set_ctrl_addr : std_logic_vector(15 downto 0);
signal set_ctrl_data : std_logic_vector(31 downto 0);
signal set_status : std_logic;
signal set_status_busy : std_logic;
signal set_status_addr : std_logic_vector(15 downto 0);
signal set_status_data : std_logic_vector(31 downto 0);
signal set_ram : std_logic;
signal set_ram_addr : integer;
signal set_ram_data : std_logic_vector(63 downto 0);
begin
-------------------------------------------------------------------------------
-- Create Clock Process
-------------------------------------------------------------------------------
proc_create_axis_clk : process
begin
axis_clk <= '1';
wait for AXIS_CLOCK_PERIOD/2;
axis_clk <= '0';
wait for AXIS_CLOCK_PERIOD/2;
end process;
proc_create_clock_100MHz : process
begin
clk_100MHz <= '0';
wait for CLOCK_PERIOD_100MHz/2;
clk_100MHz <= '1';
wait for CLOCK_PERIOD_100MHz/2;
end process;
-------------------------------------------------------------------------------
-- Reset Process
-------------------------------------------------------------------------------
proc_reset : process
begin
reset <= '1';
wait for 20*CLOCK_PERIOD_100MHz;
reset <= '0';
wait;
end process;
proc_axis_rst_n : process
begin
axis_rst_n <= '0';
wait for 20*AXIS_CLOCK_PERIOD;
axis_rst_n <= '1';
wait;
end process;
-------------------------------------------------------------------------------
-- Timeout Process
-------------------------------------------------------------------------------
proc_timeout : process
begin
wait for TIMEOUT;
assert(FALSE)
report "ERROR: Simulation timed out."
severity FAILURE;
wait;
end process;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
inst_ps_pl_interface : ps_pl_interface
generic map (
C_BASEADDR => x"40000000",
C_HIGHADDR => x"4001ffff")
port map (
clk => axis_clk,
rst_n => axis_rst_n,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARSIZE => M_AXI_ARSIZE,
irq => irq,
rst_glb_n => rst_glb_n,
-- Note: Master 0 & Slave 0 interfaces are occupied by the
-- datamover component internally.
axis_master_1_tvalid => axis_master_1_tvalid,
axis_master_1_tready => axis_master_1_tready,
axis_master_1_tdata => axis_master_1_tdata,
axis_master_1_tdest => axis_master_1_tdest,
axis_master_1_tlast => axis_master_1_tlast,
axis_master_1_irq => axis_master_1_irq,
axis_slave_1_tvalid => axis_slave_1_tvalid,
axis_slave_1_tready => axis_slave_1_tready,
axis_slave_1_tdata => axis_slave_1_tdata,
axis_slave_1_tid => axis_slave_1_tid,
axis_slave_1_tlast => axis_slave_1_tlast,
axis_slave_1_irq => axis_slave_1_irq,
status_1_addr => status_1_addr,
status_1_data => status_1_data,
status_1_stb => status_1_stb,
ctrl_1_addr => ctrl_1_addr,
ctrl_1_data => ctrl_1_data,
ctrl_1_stb => ctrl_1_stb,
axis_master_2_tvalid => axis_master_2_tvalid,
axis_master_2_tready => axis_master_2_tready,
axis_master_2_tdata => axis_master_2_tdata,
axis_master_2_tdest => axis_master_2_tdest,
axis_master_2_tlast => axis_master_2_tlast,
axis_master_2_irq => axis_master_2_irq,
axis_slave_2_tvalid => axis_slave_2_tvalid,
axis_slave_2_tready => axis_slave_2_tready,
axis_slave_2_tdata => axis_slave_2_tdata,
axis_slave_2_tid => axis_slave_2_tid,
axis_slave_2_tlast => axis_slave_2_tlast,
axis_slave_2_irq => axis_slave_2_irq,
status_2_addr => status_2_addr,
status_2_data => status_2_data,
status_2_stb => status_2_stb,
ctrl_2_addr => ctrl_2_addr,
ctrl_2_data => ctrl_2_data,
ctrl_2_stb => ctrl_2_stb,
axis_master_3_tvalid => axis_master_3_tvalid,
axis_master_3_tready => axis_master_3_tready,
axis_master_3_tdata => axis_master_3_tdata,
axis_master_3_tdest => axis_master_3_tdest,
axis_master_3_tlast => axis_master_3_tlast,
axis_master_3_irq => axis_master_3_irq,
axis_slave_3_tvalid => axis_slave_3_tvalid,
axis_slave_3_tready => axis_slave_3_tready,
axis_slave_3_tdata => axis_slave_3_tdata,
axis_slave_3_tid => axis_slave_3_tid,
axis_slave_3_tlast => axis_slave_3_tlast,
axis_slave_3_irq => axis_slave_3_irq,
status_3_addr => status_3_addr,
status_3_data => status_3_data,
status_3_stb => status_3_stb,
ctrl_3_addr => ctrl_3_addr,
ctrl_3_data => ctrl_3_data,
ctrl_3_stb => ctrl_3_stb,
axis_master_4_tvalid => axis_master_4_tvalid,
axis_master_4_tready => axis_master_4_tready,
axis_master_4_tdata => axis_master_4_tdata,
axis_master_4_tdest => axis_master_4_tdest,
axis_master_4_tlast => axis_master_4_tlast,
axis_master_4_irq => axis_master_4_irq,
axis_slave_4_tvalid => axis_slave_4_tvalid,
axis_slave_4_tready => axis_slave_4_tready,
axis_slave_4_tdata => axis_slave_4_tdata,
axis_slave_4_tid => axis_slave_4_tid,
axis_slave_4_tlast => axis_slave_4_tlast,
axis_slave_4_irq => axis_slave_4_irq,
status_4_addr => status_4_addr,
status_4_data => status_4_data,
status_4_stb => status_4_stb,
ctrl_4_addr => ctrl_4_addr,
ctrl_4_data => ctrl_4_data,
ctrl_4_stb => ctrl_4_stb,
axis_master_5_tvalid => axis_master_5_tvalid,
axis_master_5_tready => axis_master_5_tready,
axis_master_5_tdata => axis_master_5_tdata,
axis_master_5_tdest => axis_master_5_tdest,
axis_master_5_tlast => axis_master_5_tlast,
axis_master_5_irq => axis_master_5_irq,
axis_slave_5_tvalid => axis_slave_5_tvalid,
axis_slave_5_tready => axis_slave_5_tready,
axis_slave_5_tdata => axis_slave_5_tdata,
axis_slave_5_tid => axis_slave_5_tid,
axis_slave_5_tlast => axis_slave_5_tlast,
axis_slave_5_irq => axis_slave_5_irq,
status_5_addr => status_5_addr,
status_5_data => status_5_data,
status_5_stb => status_5_stb,
ctrl_5_addr => ctrl_5_addr,
ctrl_5_data => ctrl_5_data,
ctrl_5_stb => ctrl_5_stb,
axis_master_6_tvalid => axis_master_6_tvalid,
axis_master_6_tready => axis_master_6_tready,
axis_master_6_tdata => axis_master_6_tdata,
axis_master_6_tdest => axis_master_6_tdest,
axis_master_6_tlast => axis_master_6_tlast,
axis_master_6_irq => axis_master_6_irq,
axis_slave_6_tvalid => axis_slave_6_tvalid,
axis_slave_6_tready => axis_slave_6_tready,
axis_slave_6_tdata => axis_slave_6_tdata,
axis_slave_6_tid => axis_slave_6_tid,
axis_slave_6_tlast => axis_slave_6_tlast,
axis_slave_6_irq => axis_slave_6_irq,
status_6_addr => status_6_addr,
status_6_data => status_6_data,
status_6_stb => status_6_stb,
ctrl_6_addr => ctrl_6_addr,
ctrl_6_data => ctrl_6_data,
ctrl_6_stb => ctrl_6_stb,
axis_master_7_tvalid => axis_master_7_tvalid,
axis_master_7_tready => axis_master_7_tready,
axis_master_7_tdata => axis_master_7_tdata,
axis_master_7_tdest => axis_master_7_tdest,
axis_master_7_tlast => axis_master_7_tlast,
axis_master_7_irq => axis_master_7_irq,
axis_slave_7_tvalid => axis_slave_7_tvalid,
axis_slave_7_tready => axis_slave_7_tready,
axis_slave_7_tdata => axis_slave_7_tdata,
axis_slave_7_tid => axis_slave_7_tid,
axis_slave_7_tlast => axis_slave_7_tlast,
axis_slave_7_irq => axis_slave_7_irq,
status_7_addr => status_7_addr,
status_7_data => status_7_data,
status_7_stb => status_7_stb,
ctrl_7_addr => ctrl_7_addr,
ctrl_7_data => ctrl_7_data,
ctrl_7_stb => ctrl_7_stb);
-- Accelerator 1
inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis
generic map (
DDR_CLOCK_FREQ => 100e6,
BAUD => 10e6)
port map (
UART_TX => UART_TX,
RX_DATA_CLK_N => RX_DATA_CLK_N_wire_dly,
RX_DATA_CLK_P => RX_DATA_CLK_P_wire_dly,
RX_DATA_N => RX_DATA_N_wire_dly,
RX_DATA_P => RX_DATA_P_wire_dly,
RX_DATA_STB_N => RX_DATA_STB_N_wire_dly,
RX_DATA_STB_P => RX_DATA_STB_P_wire_dly,
TX_DATA_N => TX_DATA_N,
TX_DATA_P => TX_DATA_P,
TX_DATA_STB_N => TX_DATA_STB_N,
TX_DATA_STB_P => TX_DATA_STB_P,
clk => axis_clk,
rst_n => rst_glb_n,
status_addr => status_1_addr,
status_data => status_1_data,
status_stb => status_1_stb,
ctrl_addr => ctrl_1_addr,
ctrl_data => ctrl_1_data,
ctrl_stb => ctrl_1_stb,
axis_slave_tvalid => axis_slave_1_tvalid,
axis_slave_tready => axis_slave_1_tready,
axis_slave_tdata => axis_slave_1_tdata,
axis_slave_tid => axis_slave_1_tid,
axis_slave_tlast => axis_slave_1_tlast,
axis_slave_irq => axis_slave_1_irq,
axis_master_tvalid => axis_master_1_tvalid,
axis_master_tready => axis_master_1_tready,
axis_master_tdata => axis_master_1_tdata,
axis_master_tdest => axis_master_1_tdest,
axis_master_tlast => axis_master_1_tlast,
axis_master_irq => axis_master_1_irq,
rx_enable_aux => rx_enable_aux,
tx_enable_aux => tx_enable_aux);
rx_enable_aux <= '0';
tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded;
-- Accelerator 2
inst_spectrum_sense : spectrum_sense
port map (
clk => axis_clk,
rst_n => rst_glb_n,
status_addr => status_2_addr,
status_data => status_2_data,
status_stb => status_2_stb,
ctrl_addr => ctrl_2_addr,
ctrl_data => ctrl_2_data,
ctrl_stb => ctrl_2_stb,
axis_slave_tvalid => axis_slave_2_tvalid,
axis_slave_tready => axis_slave_2_tready,
axis_slave_tdata => axis_slave_2_tdata,
axis_slave_tid => axis_slave_2_tid,
axis_slave_tlast => axis_slave_2_tlast,
axis_slave_irq => axis_slave_2_irq,
axis_master_tvalid => axis_master_2_tvalid,
axis_master_tready => axis_master_2_tready,
axis_master_tdata => axis_master_2_tdata,
axis_master_tdest => axis_master_2_tdest,
axis_master_tlast => axis_master_2_tlast,
axis_master_irq => axis_master_2_irq,
threshold_not_exceeded => threshold_not_exceeded,
threshold_not_exceeded_stb => threshold_not_exceeded_stb,
threshold_exceeded => threshold_exceeded,
threshold_exceeded_stb => threshold_exceeded_stb);
-- Accelerator 3
inst_bpsk_mod : bpsk_mod
port map (
clk => axis_clk,
rst_n => rst_glb_n,
status_addr => status_3_addr,
status_data => status_3_data,
status_stb => status_3_stb,
ctrl_addr => ctrl_3_addr,
ctrl_data => ctrl_3_data,
ctrl_stb => ctrl_3_stb,
axis_slave_tvalid => axis_slave_3_tvalid,
axis_slave_tready => axis_slave_3_tready,
axis_slave_tdata => axis_slave_3_tdata,
axis_slave_tid => axis_slave_3_tid,
axis_slave_tlast => axis_slave_3_tlast,
axis_slave_irq => axis_slave_3_irq,
axis_master_tvalid => axis_master_3_tvalid,
axis_master_tready => axis_master_3_tready,
axis_master_tdata => axis_master_3_tdata,
axis_master_tdest => axis_master_3_tdest,
axis_master_tlast => axis_master_3_tlast,
axis_master_irq => axis_master_3_irq,
trigger_stb => trigger_stb);
trigger_stb <= threshold_exceeded_stb;
-- Unused Accelerators
axis_slave_4_tready <= '0';
axis_slave_4_irq <= '0';
axis_master_4_tvalid <= '0';
axis_master_4_tdata <= x"0000000000000000";
axis_master_4_tdest <= "000";
axis_master_4_tlast <= '0';
axis_master_4_irq <= '0';
status_4_data <= x"00000000";
axis_slave_5_tready <= '0';
axis_slave_5_irq <= '0';
axis_master_5_tvalid <= '0';
axis_master_5_tdata <= x"0000000000000000";
axis_master_5_tdest <= "000";
axis_master_5_tlast <= '0';
axis_master_5_irq <= '0';
status_5_data <= x"00000000";
axis_slave_6_tready <= '0';
axis_slave_6_irq <= '0';
axis_master_6_tvalid <= '0';
axis_master_6_tdata <= x"0000000000000000";
axis_master_6_tdest <= "000";
axis_master_6_tlast <= '0';
axis_master_6_irq <= '0';
status_6_data <= x"00000000";
axis_slave_7_tready <= '0';
axis_slave_7_irq <= '0';
axis_master_7_tvalid <= '0';
axis_master_7_tdata <= x"0000000000000000";
axis_master_7_tdest <= "000";
axis_master_7_tlast <= '0';
axis_master_7_irq <= '0';
status_7_data <= x"00000000";
-----------------------------------------------------------------------------
-- CRASH DDR Interface (on USRP)
-----------------------------------------------------------------------------
inst_crash_ddr_intf : crash_ddr_intf
generic map (
CLOCK_FREQ => 100e6,
BAUD => 10e6)
port map (
clk => clk_100MHz,
reset => reset,
RX_DATA_CLK_N => RX_DATA_CLK_N,
RX_DATA_CLK_P => RX_DATA_CLK_P,
RX_DATA_N => RX_DATA_N,
RX_DATA_P => RX_DATA_P,
RX_DATA_STB_N => RX_DATA_STB_N,
RX_DATA_STB_P => RX_DATA_STB_P,
TX_DATA_N => TX_DATA_N_wire_dly,
TX_DATA_P => TX_DATA_P_wire_dly,
TX_DATA_STB_N => TX_DATA_STB_N_wire_dly,
TX_DATA_STB_P => TX_DATA_STB_P_wire_dly,
UART_RX => UART_TX,
adc_i => adc_i,
adc_q => adc_q,
adc_dc_off_i => adc_dc_off_i,
adc_dc_off_q => adc_dc_off_q,
dac_usrp_i => dac_usrp_i,
dac_usrp_q => dac_usrp_q,
dac_usrp_dc_off_i => dac_usrp_dc_off_i,
dac_usrp_dc_off_q => dac_usrp_dc_off_q,
dac_i => dac_i,
dac_q => dac_q,
dac_dc_off_i => dac_dc_off_i,
dac_dc_off_q => dac_dc_off_q);
-- Simulate delay due to MICTOR cable
RX_DATA_CLK_N_wire_dly <= transport RX_DATA_CLK_N after 13 ns;
RX_DATA_CLK_P_wire_dly <= transport RX_DATA_CLK_P after 13 ns;
RX_DATA_N_wire_dly <= transport RX_DATA_N after 11 ns;
RX_DATA_P_wire_dly <= transport RX_DATA_P after 11 ns;
RX_DATA_STB_N_wire_dly <= transport RX_DATA_STB_N after 11 ns;
RX_DATA_STB_P_wire_dly <= transport RX_DATA_STB_P after 11 ns;
TX_DATA_N_wire_dly <= transport TX_DATA_N after 11 ns;
TX_DATA_P_wire_dly <= transport TX_DATA_P after 11 ns;
TX_DATA_STB_N_wire_dly <= transport TX_DATA_STB_N after 11 ns;
TX_DATA_STB_P_wire_dly <= transport TX_DATA_STB_P after 11 ns;
-------------------------------------------------------------------------------
-- Create ADC Data
-------------------------------------------------------------------------------
proc_create_adc_data : process
variable PHASE_ACCUM : real := 0.0;
begin
adc_i <= (others=>'0');
adc_q <= (others=>'0');
adc_dc_off_i <= (others=>'0');
adc_dc_off_q <= (others=>'0');
wait until reset = '1';
loop
PHASE_ACCUM := PHASE_ACCUM + 2.0*MATH_PI*0.5/100.0; -- 500 KHz off center freq
if (PHASE_ACCUM > 2.0*MATH_PI) then
PHASE_ACCUM := PHASE_ACCUM - 2.0*MATH_PI;
end if;
adc_i <= std_logic_vector(to_signed(integer(round((2.0**13.0-1.0)*cos(PHASE_ACCUM))),14));
adc_q <= std_logic_vector(to_signed(integer(round((2.0**13.0-1.0)*sin(PHASE_ACCUM))),14));
adc_dc_off_i <= std_logic_vector(to_signed(integer(round((2.0**13.0-1.0)*cos(PHASE_ACCUM))),24));
adc_dc_off_q <= std_logic_vector(to_signed(integer(round((2.0**13.0-1.0)*sin(PHASE_ACCUM))),24));
wait until clk_100MHz = '1';
end loop;
end process;
-------------------------------------------------------------------------------
-- Create DAC Data
-------------------------------------------------------------------------------
proc_create_dac_data : process
variable PHASE_ACCUM : real := 0.0;
begin
dac_usrp_i <= (others=>'0');
dac_usrp_q <= (others=>'0');
dac_usrp_dc_off_i <= (others=>'0');
dac_usrp_dc_off_q <= (others=>'0');
wait until reset = '1';
loop
PHASE_ACCUM := PHASE_ACCUM + 2.0*MATH_PI*0.5/100.0;
if (PHASE_ACCUM > 2.0*MATH_PI) then
PHASE_ACCUM := PHASE_ACCUM - 2.0*MATH_PI;
end if;
dac_usrp_i <= std_logic_vector(to_signed(integer(round((2.0**15.0-1.0)*cos(PHASE_ACCUM))),16));
dac_usrp_q <= std_logic_vector(to_signed(integer(round((2.0**15.0-1.0)*sin(PHASE_ACCUM))),16));
dac_usrp_dc_off_i <= std_logic_vector(to_signed(integer(round((2.0**15.0-1.0)*cos(PHASE_ACCUM))),24));
dac_usrp_dc_off_q <= std_logic_vector(to_signed(integer(round((2.0**15.0-1.0)*sin(PHASE_ACCUM))),24));
wait until axis_clk = '1';
end loop;
end process;
-------------------------------------------------------------------------------
-- AXI ACP Write & Read // Simulated memory accessed by AXI ACP interface
-------------------------------------------------------------------------------
proc_axi_acp_write : process(axis_clk,axis_rst_n)
variable m_axi_awaddr_base : integer := 0;
variable m_axi_awlen_cnt : integer := 0;
variable addr_inc : integer := 0;
begin
if (axis_rst_n = '0') then
M_AXI_AWREADY <= '0';
M_AXI_WREADY <= '0';
m_axi_awaddr_base := 0;
m_axi_awlen_cnt := 0;
addr_inc := 0;
ram <= (others=>(others=>'0'));
else
if rising_edge(axis_clk) then
if (M_AXI_AWVALID = '1') then
M_AXI_AWREADY <= '1';
if (m_axi_awlen_cnt = 0) then
m_axi_awaddr_base := to_integer(unsigned(M_AXI_AWADDR(12 downto 0)));
end if;
m_axi_awlen_cnt := m_axi_awlen_cnt + to_integer(unsigned(M_AXI_AWLEN));
else
M_AXI_AWREADY <= '0';
end if;
if (M_AXI_WVALID = '1') then
M_AXI_WREADY <= '1';
ram(m_axi_awaddr_base + addr_inc) <= M_AXI_WDATA;
addr_inc := addr_inc + 1;
m_axi_awlen_cnt := m_axi_awlen_cnt - 1;
else
M_AXI_WREADY <= '0';
end if;
if (m_axi_awlen_cnt = 1) then
addr_inc := 0;
end if;
-- Manually fill RAM
if (set_ram = '1') then
ram(set_ram_addr) <= set_ram_data;
end if;
end if;
end if;
end process;
M_AXI_BRESP <= "00";
M_AXI_BVALID <= M_AXI_BREADY;
proc_axi_acp_read : process(axis_clk)
variable m_axi_arlen_cnt : integer := 0;
variable m_axi_araddr_base : integer := 0;
variable addr_inc : integer := 0;
begin
if (axis_rst_n = '0') then
M_AXI_ARREADY <= '0';
M_AXI_RVALID <= '0';
M_AXI_RLAST <= '0';
M_AXI_RDATA <= (others=>'0');
m_axi_arlen_cnt := 0;
m_axi_araddr_base := 0;
addr_inc := 0;
else
if rising_edge(axis_clk) then
if (m_axi_arlen_cnt > 0) then
M_AXI_RVALID <= '1';
if (M_AXI_RREADY = '1') then
M_AXI_RDATA <= ram(m_axi_araddr_base + addr_inc);
-- On last beat, set rlast
if (m_axi_arlen_cnt = 1) then
M_AXI_RLAST <= '1';
end if;
if (addr_inc = 4096) then
addr_inc := 0;
else
addr_inc := addr_inc + 1;
end if;
m_axi_arlen_cnt := m_axi_arlen_cnt - 1;
end if;
else
addr_inc := 0;
M_AXI_RVALID <= '0';
M_AXI_RLAST <= '0';
end if;
if (M_AXI_ARVALID = '1' AND M_AXI_ARREADY = '0') then
M_AXI_ARREADY <= '1';
if (m_axi_arlen_cnt = 0) then
m_axi_araddr_base := to_integer(unsigned(M_AXI_ARADDR(15 downto 3)));
end if;
m_axi_arlen_cnt := m_axi_arlen_cnt + to_integer(unsigned(M_AXI_ARLEN)) + 1;
else
M_AXI_ARREADY <= '0';
end if;
end if;
end if;
end process;
M_AXI_RRESP <= "00";
-------------------------------------------------------------------------------
-- AXI-Lite // interface to access control & status registers
-------------------------------------------------------------------------------
proc_axi_lite_ctrl_reg : process(axis_clk,axis_rst_n)
begin
if (axis_rst_n = '0') then
S_AXI_AWADDR <= (others=>'0');
S_AXI_AWVALID <= '0';
S_AXI_WDATA <= (others=>'0');
S_AXI_WSTRB <= (others=>'0');
S_AXI_WVALID <= '0';
S_AXI_BREADY <= '0';
set_ctrl_busy <= '0';
else
if rising_edge(axis_clk) then
if (set_ctrl = '1') then
-- Address left shifted by 2 due to access on word boundaries
S_AXI_AWADDR <= x"40000000" + (set_ctrl_addr & "00");
S_AXI_AWVALID <= '1';
S_AXI_WDATA <= set_ctrl_data;
S_AXI_WVALID <= '1';
set_ctrl_busy <= '1';
end if;
if (set_ctrl_busy = '1' AND S_AXI_WREADY = '1') then
S_AXI_AWVALID <= '0';
S_AXI_WVALID <= '0';
set_ctrl_busy <= '0';
end if;
end if;
end if;
end process;
proc_axi_lite_status_reg : process(axis_clk,axis_rst_n)
begin
if (axis_rst_n = '0') then
S_AXI_ARADDR <= (others=>'0');
S_AXI_ARVALID <= '0';
S_AXI_RREADY <= '0';
set_status_busy <= '0';
set_status_data <= (others=>'0');
else
if rising_edge(axis_clk) then
if (set_status = '1') then
-- Address left shifted by 2 due to access on word boundaries
S_AXI_ARADDR <= x"40000000" + (set_status_addr & "00");
S_AXI_ARVALID <= '1';
set_status_busy <= '1';
S_AXI_RREADY <= '1';
end if;
if (S_AXI_ARREADY = '1') then
S_AXI_ARVALID <= '0';
end if;
if (S_AXI_RVALID = '1') then
S_AXI_RREADY <= '0';
set_status_data <= S_AXI_RDATA;
set_status_busy <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Test Bench
-------------------------------------------------------------------------------
proc_test_bench : process
begin
set_ctrl <= '0';
set_ctrl_addr <= (others=>'0');
set_ctrl_data <= (others=>'0');
set_status <= '0';
set_status_addr <= (others=>'0');
set_ram <= '0';
set_ram_addr <= 0;
set_ram_data <= (others=>'0');
wait until axis_rst_n = '1';
wait until axis_clk = '1';
-----------------------------------------------------------------------------
-- Set the first 4096 words of memory to a sine wave
-----------------------------------------------------------------------------
for i in 0 to 4095 loop
set_ram <= '1';
set_ram_addr <= i;
-- Useful counter: set_ram_data <= std_logic_vector(to_unsigned(i,32)) & std_logic_vector(to_unsigned(i+128,32));
set_ram_data <= (63 downto 48 => dac_usrp_i(15)) & dac_usrp_i & (31 downto 16 => dac_usrp_q(15)) & dac_usrp_q;
wait until axis_clk = '1';
end loop;
set_ram <= '0';
wait until axis_clk = '1';
-----------------------------------------------------------------------------
-- Test AXI ACP interface with a loopback. Set ps_pl_interface to
-- read the first 256 words from memory and immediately write them back.
-----------------------------------------------------------------------------
-- Enable MM2S and S2MM xfers
set_ctrl_addr <= x"00" & x"00";
set_ctrl_data(0) <= '1';
set_ctrl_data(1) <= '1';
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set ps_pl_interface Control Register Bank 2: MM2S Command Address
set_ctrl_addr <= x"00" & x"02";
set_ctrl_data <= (others=>'0'); -- Address
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set ps_pl_interface Control Register Bank 3: MM2S Command Size, Cache, tdest
set_ctrl_addr <= x"00" & x"03";
---- Send 64 words (64*8 bytes) and set the enable to push the command into the command FIFO
set_ctrl_data <= (others=>'0');
set_ctrl_data(22 downto 0) <= std_logic_vector(to_unsigned(256*8,23)); -- Number of bytes to transfer
set_ctrl_data(25 downto 23) <= "000"; -- Tdest
set_ctrl_data(31) <= '1'; -- Push command to FIFO
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set ps_pl_interface Control Register Bank 4: S2MM Command Address
set_ctrl_addr <= x"00" & x"04";
set_ctrl_data <= std_logic_vector(to_unsigned(0,32)); -- Address
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set ps_pl_interface Control Register Bank 5: S2MM Command Size, Cache, tdest
set_ctrl_addr <= x"00" & x"05";
set_ctrl_data <= (others=>'0');
set_ctrl_data(22 downto 0) <= std_logic_vector(to_unsigned(256*8,23)); -- Number of bytes to transfer
set_ctrl_data(25 downto 23) <= "000"; -- Tdest
set_ctrl_data(31) <= '1'; -- Push command to FIFO
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Wait for transfer to complete by checking if S2MM STS FIFO is empty
set_status_addr <= x"00" & x"08";
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
---- While S2MM STS FIFO is empty
while (set_status_data(2) = '1') loop
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
end loop;
-- Read M2SS STS FIFO
set_status_addr <= x"00" & x"06";
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
-- Read S2MM STS FIFO
set_status_addr <= x"00" & x"07";
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
-----------------------------------------------------------------------------
-- Test spectrum sensing. Setup spectrum_sense to enable FFT, discard
-- output (i.e. do not route the FFT output to anywhere meaningful so it
-- can constantly run), and trigger on threshold exceeded
-----------------------------------------------------------------------------
-- Set spectrum_sense Control Register Bank 1
set_ctrl_addr <= x"02" & x"01";
set_ctrl_data <= (others=>'0');
set_ctrl_data(4 downto 0) <= "00111"; -- FFT Size ("00111" = 128)
set_ctrl_data(5) <= '1'; -- Set FFT Size
set_ctrl_data(9 downto 8) <= "11"; -- FFT Mode "11", discard FFT output
set_ctrl_data(10) <= '1'; -- Enable IRQ
set_ctrl_data(11) <= '1'; -- Enable threshold exceeded sideband signal
set_ctrl_data(13) <= '1'; -- Enable clear threshold latched
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set spectrum_sense Control Register Bank 0
set_ctrl_addr <= x"02" & x"00";
set_ctrl_data <= (others=>'0');
set_ctrl_data(0) <= '1'; -- Enable FFT
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set spectrum_sense Control Register Bank 2
set_ctrl_addr <= x"02" & x"02";
set_ctrl_data <= x"40A00000"; -- Threshold level (floating point, value = 5.0)
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-----------------------------------------------------------------------------
-- Setup usrp_ddr_interface_axis to enable RX, bypass TX floating to fixed
-- point, set interp/decim rates, RX & TX gain, and MICTOR cable calibration.
-----------------------------------------------------------------------------
-- Set usrp_ddr_interface_axis Control Register Bank 0
-- Note: Tdest can only be set when a transfer is not in progress (i.e.
-- usrp_ddr_interface_axis rx_enable = 0). This prevents switching destinations
-- in the middle of a transfer, which may cause problems with the AXI interconnect
set_ctrl_addr <= x"01" & x"00";
set_ctrl_data <= (others=>'0');
set_ctrl_data(31 downto 29) <= "010"; -- Master Tdest
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set usrp_ddr_interface_axis Control Register Bank 2
set_ctrl_addr <= x"01" & x"02";
set_ctrl_data <= (others=>'0');
set_ctrl_data(23 downto 0) <= std_logic_vector(to_unsigned(128,24)); -- RX packet size
set_ctrl_data(24) <= '0'; -- RX fix2float bypass
set_ctrl_data(25) <= '1'; -- RX CIC bypass
set_ctrl_data(26) <= '1'; -- RX Halfband bypass
set_ctrl_data(27) <= '1'; -- TX float2fix bypass
set_ctrl_data(28) <= '1'; -- TX CIC bypass
set_ctrl_data(29) <= '1'; -- TX Halfband bypass
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set usrp_ddr_interface_axis Control Register Bank 3
set_ctrl_addr <= x"01" & x"03";
set_ctrl_data <= (others=>'0');
set_ctrl_data(10 downto 0) <= std_logic_vector(to_unsigned(1,11)); -- RX decimation
set_ctrl_data(26 downto 16) <= std_logic_vector(to_unsigned(1,11)); -- TX interpolation
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set usrp_ddr_interface_axis Control Register Bank 4, RX gain
-- NOTE: If the CIC filter is bypassed, then gain can be safely set to 1 as our test sinusoid
-- already uses the full dynamic range.
set_ctrl_addr <= x"01" & x"04";
set_ctrl_data <= std_logic_vector(to_unsigned(1,32)); -- RX gain
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set usrp_ddr_interface_axis Control Register Bank 5, TX gain
-- NOTE: If the CIC filter is bypassed, then gain can be safely set to 1 as our test sinusoid
-- already uses the full dynamic range.
set_ctrl_addr <= x"01" & x"05";
set_ctrl_data <= std_logic_vector(to_unsigned(1,32)); -- TX gain
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set usrp_ddr_interface_axis Control Register Bank 1, USRP Mode
--set_ctrl_addr <= x"01" & x"01";
--set_ctrl_data <= x"000000" & CMD_RX_MODE & RX_TX_LOOPBACK_MODE; -- USRP Mode
--set_ctrl <= '1';
--wait until set_ctrl_busy = '1';
--set_ctrl <= '0';
--wait until set_ctrl_busy = '0';
--wait until axis_clk = '1';
-- Set MMCM phase values to calibrate MICTOR cable
set_ctrl_addr <= x"01" & x"06";
set_ctrl_data <= (others=>'0');
set_ctrl_data(0) <= '1'; -- RX restart calibration
set_ctrl_data(10 downto 1) <= std_logic_vector(to_unsigned(200,10)); -- RX phase
set_ctrl_data(16) <= '1'; -- TX restart calibration
set_ctrl_data(26 downto 17) <= std_logic_vector(to_unsigned(450,10)); -- TX phase
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Read usrp_ddr_interface_axis Status Register 7 and wait until the link is re-calibrated
set_status_addr <= x"01" & x"07";
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
---- Wait for calibration busy
while (set_status_data(3) = '1' OR set_status_data(4) = '1') loop
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
end loop;
wait until axis_clk = '1';
set_status_addr <= x"01" & x"07";
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
---- Wait for calibration to complete
while (set_status_data(3) = '0' OR set_status_data(4) = '0') loop
set_status <= '1';
wait until set_status_busy = '1';
set_status <= '0';
wait until set_status_busy = '0';
wait until axis_clk = '1';
end loop;
wait until axis_clk = '1';
-- Enable RX to kickoff spectrum sensing. Route RX data to spectrum_sense
set_ctrl_addr <= x"01" & x"00";
set_ctrl_data <= (others=>'0');
set_ctrl_data(0) <= '1'; -- RX Enable
set_ctrl_data(3) <= '0'; -- TX Enable Aux
set_ctrl_data(6) <= '1'; -- RX FIFO Bypass
set_ctrl_data(31 downto 29) <= "010"; -- Master Tdest
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-----------------------------------------------------------------------------
-- Setup ps_pl_interface to transfer TX data from RAM to usrp_ddr_intf_axis
-- which is AXI-Stream slave interface "001"
-----------------------------------------------------------------------------
-- Set ps_pl_interface Control Register Bank 2: MM2S Command Address
set_ctrl_addr <= x"00" & x"02";
set_ctrl_data <= (others=>'0'); -- Address
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-- Set ps_pl_interface Control Register Bank 3: MM2S Command Size, Cache, tdest
set_ctrl_addr <= x"00" & x"03";
set_ctrl_data <= (others=>'0');
set_ctrl_data(22 downto 0) <= std_logic_vector(to_unsigned(4096*8,23)); -- Number of bytes to transfer
set_ctrl_data(25 downto 23) <= "001"; -- Tdest
set_ctrl_data(31) <= '1'; -- Push command to FIFO
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
-----------------------------------------------------------------------------
-- Setup usrp_ddr_interface_axis control registers to enable TX to trigger
-- if the spectrum sensing threshold is exceeded.
-----------------------------------------------------------------------------
-- Enable TX Enable Aux to kickoff the entire simulation
-- Set usrp_ddr_interface_axis Control Register Bank 0
set_ctrl_addr <= x"01" & x"00";
set_ctrl_data <= (others=>'0');
set_ctrl_data(0) <= '1'; -- RX Enable
--set_ctrl_data(1) <= '1'; -- TX Enable
set_ctrl_data(3) <= '1'; -- TX Enable Aux
set_ctrl_data(6) <= '1'; -- RX FIFO Bypass
set_ctrl_data(31 downto 29) <= "010"; -- Master Tdest
set_ctrl <= '1';
wait until set_ctrl_busy = '1';
set_ctrl <= '0';
wait until set_ctrl_busy = '0';
wait until axis_clk = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
d31a3b2813b335a8fe91b7711ee3df4e
| 0.456508 | 3.877982 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp_mul.vhd
| 1 | 85,444 |
-- megafunction wizard: %ALTFP_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_MULT
-- ============================================================
-- File Name: fp_mul.vhd
-- Megafunction Name(s):
-- ALTFP_MULT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" EXCEPTION_HANDLING="NO" PIPELINE=5 REDUCED_FUNCTIONALITY="NO" ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_alt_ded_mult_y 2010:03:24:20:34:20:SJ cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_mult 2010:03:24:20:34:20:SJ cbx_altmult_add 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_lpm_mult 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_padd 2010:03:24:20:34:20:SJ cbx_parallel_add 2010:03:24:20:34:20:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ cbx_util_mgl 2010:03:24:20:34:20:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 136
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_mul_altfp_mult_ppo IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mul_altfp_mult_ppo;
ARCHITECTURE RTL OF fp_mul_altfp_mult_ppo IS
SIGNAL dataa_exp_all_one_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dataa_exp_all_one_ff_p1_w_lg_q296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dataa_exp_all_one_ff_p1_w_lg_q291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dataa_exp_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_man_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dataa_man_not_zero_ff_p1_w_lg_q290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dataa_man_not_zero_ff_p2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_exp_all_one_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_datab_exp_all_one_ff_p1_w_lg_q294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_datab_exp_all_one_ff_p1_w_lg_q289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL datab_exp_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_datab_man_not_zero_ff_p1_w_lg_q288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL datab_man_not_zero_ff_p2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_exp2_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_exp_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_man_product_msb : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_delay_man_product_msb_w_lg_q392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_man_product_msb_w_lg_q394w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL delay_man_product_msb_p0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_add_p1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_ff : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_is_infinity_ff1_w_lg_q462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_input_is_infinity_ff1_w_lg_q464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL input_is_nan_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_is_nan_ff1_w_lg_q474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL input_not_zero_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_not_zero_ff1_w_lg_q461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL lsb_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_result_ff : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p2 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_man_round_p2_w_lg_w_q_range399w400w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_q_range396w397w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_q_range391w398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range399w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range396w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL round_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_exp_add_adder_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_add_adder_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_add_adder_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_lg_w_lg_w_result_range454w455w456w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_lg_w_result_range454w455w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_lg_w_result_range429w452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_result : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range454w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_adder_w_result_range429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_dataa : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_result : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_man_round_adder_dataa : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_round_adder_datab : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_round_adder_result : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range302w303w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range299w300w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range298w372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range298w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_dataa : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_product2_mult_datab : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_product2_mult_result : STD_LOGIC_VECTOR (47 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range302w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range299w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w478w479w480w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_w_lg_w478w479w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_w_lg_w468w469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w478w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_result_round_range475w476w477w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_result_round_range465w466w467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_inf_num459w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range81w87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range91w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range101w107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range121w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range131w137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range84w89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range94w99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range104w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range124w129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range134w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_result_round_range475w476w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_w_lg_w_man_result_round_range465w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range403w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range407w409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range410w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range413w415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range416w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range419w421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range422w424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_inf463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_zero453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range450w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w468w469w470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_inf_num459w460w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w468w469w470w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_is_inf457w458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_inf457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range211w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range221w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range227w228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range233w234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range239w240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range245w246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range251w252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range257w258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range263w264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range157w158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range269w270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range275w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range281w282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range81w82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range91w92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range101w102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range121w122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range131w132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range163w164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range169w170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range175w176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range181w182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range187w188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range193w194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range199w200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range205w206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range224w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range230w231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range236w237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range242w243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range248w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range254w255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range260w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range266w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range160w161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range272w273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range278w279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range284w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range94w95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range104w105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range124w125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range134w135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range166w167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range172w173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range178w179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range184w185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range190w191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range196w197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range202w203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range208w209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range436w437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range438w439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range440w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range442w443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range444w445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range446w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range448w449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range306w309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range337w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range340w342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range343w345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range346w348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range349w351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range352w354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range355w357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range358w360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range361w363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range364w366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range310w312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range367w369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range370w373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range313w315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range316w318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range319w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range322w324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range325w327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range328w330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range331w333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range334w336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL bias : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL dataa_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_exp_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_man_not_zero : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL datab_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL datab_exp_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL datab_man_not_zero : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL exp_is_inf : STD_LOGIC;
SIGNAL exp_is_zero : STD_LOGIC;
SIGNAL expmod : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL inf_num : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL lsb_bit : STD_LOGIC;
SIGNAL man_result_round : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_shift_full : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL result_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL result_exp_not_zero : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL round_bit : STD_LOGIC;
SIGNAL round_carry : STD_LOGIC;
SIGNAL sticky_bit : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_round_range475w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_w_man_result_round_range465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_shift_full_range379w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
loop0 : FOR i IN 0 TO 21 GENERATE
wire_w_lg_w_lg_w478w479w480w(i) <= wire_w_lg_w478w479w(i) AND wire_input_is_nan_ff1_w_lg_q474w(0);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 21 GENERATE
wire_w_lg_w478w479w(i) <= wire_w478w(i) AND wire_w_lg_exp_is_zero453w(0);
END GENERATE loop1;
wire_w_lg_w468w469w(0) <= wire_w468w(0) AND wire_w_lg_exp_is_zero453w(0);
loop2 : FOR i IN 0 TO 21 GENERATE
wire_w478w(i) <= wire_w_lg_w_lg_w_man_result_round_range475w476w477w(i) AND wire_w_lg_exp_is_inf463w(0);
END GENERATE loop2;
wire_w468w(0) <= wire_w_lg_w_lg_w_man_result_round_range465w466w467w(0) AND wire_w_lg_exp_is_inf463w(0);
loop3 : FOR i IN 0 TO 21 GENERATE
wire_w_lg_w_lg_w_man_result_round_range475w476w477w(i) <= wire_w_lg_w_man_result_round_range475w476w(i) AND wire_input_is_infinity_ff1_w_lg_q464w(0);
END GENERATE loop3;
wire_w_lg_w_lg_w_man_result_round_range465w466w467w(0) <= wire_w_lg_w_man_result_round_range465w466w(0) AND wire_input_is_infinity_ff1_w_lg_q464w(0);
loop4 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_inf_num459w(i) <= inf_num(i) AND wire_w_lg_w_lg_exp_is_inf457w458w(0);
END GENERATE loop4;
wire_w_lg_w_dataa_range81w87w(0) <= wire_w_dataa_range81w(0) AND wire_w_dataa_exp_all_one_range77w(0);
wire_w_lg_w_dataa_range91w97w(0) <= wire_w_dataa_range91w(0) AND wire_w_dataa_exp_all_one_range88w(0);
wire_w_lg_w_dataa_range101w107w(0) <= wire_w_dataa_range101w(0) AND wire_w_dataa_exp_all_one_range98w(0);
wire_w_lg_w_dataa_range111w117w(0) <= wire_w_dataa_range111w(0) AND wire_w_dataa_exp_all_one_range108w(0);
wire_w_lg_w_dataa_range121w127w(0) <= wire_w_dataa_range121w(0) AND wire_w_dataa_exp_all_one_range118w(0);
wire_w_lg_w_dataa_range131w137w(0) <= wire_w_dataa_range131w(0) AND wire_w_dataa_exp_all_one_range128w(0);
wire_w_lg_w_dataa_range141w147w(0) <= wire_w_dataa_range141w(0) AND wire_w_dataa_exp_all_one_range138w(0);
wire_w_lg_w_datab_range84w89w(0) <= wire_w_datab_range84w(0) AND wire_w_datab_exp_all_one_range79w(0);
wire_w_lg_w_datab_range94w99w(0) <= wire_w_datab_range94w(0) AND wire_w_datab_exp_all_one_range90w(0);
wire_w_lg_w_datab_range104w109w(0) <= wire_w_datab_range104w(0) AND wire_w_datab_exp_all_one_range100w(0);
wire_w_lg_w_datab_range114w119w(0) <= wire_w_datab_range114w(0) AND wire_w_datab_exp_all_one_range110w(0);
wire_w_lg_w_datab_range124w129w(0) <= wire_w_datab_range124w(0) AND wire_w_datab_exp_all_one_range120w(0);
wire_w_lg_w_datab_range134w139w(0) <= wire_w_datab_range134w(0) AND wire_w_datab_exp_all_one_range130w(0);
wire_w_lg_w_datab_range144w149w(0) <= wire_w_datab_range144w(0) AND wire_w_datab_exp_all_one_range140w(0);
loop5 : FOR i IN 0 TO 21 GENERATE
wire_w_lg_w_man_result_round_range475w476w(i) <= wire_w_man_result_round_range475w(i) AND input_not_zero_ff1;
END GENERATE loop5;
wire_w_lg_w_man_result_round_range465w466w(0) <= wire_w_man_result_round_range465w(0) AND input_not_zero_ff1;
wire_w_lg_w_result_exp_all_one_range403w406w(0) <= wire_w_result_exp_all_one_range403w(0) AND wire_exp_adj_adder_w_result_range405w(0);
wire_w_lg_w_result_exp_all_one_range407w409w(0) <= wire_w_result_exp_all_one_range407w(0) AND wire_exp_adj_adder_w_result_range408w(0);
wire_w_lg_w_result_exp_all_one_range410w412w(0) <= wire_w_result_exp_all_one_range410w(0) AND wire_exp_adj_adder_w_result_range411w(0);
wire_w_lg_w_result_exp_all_one_range413w415w(0) <= wire_w_result_exp_all_one_range413w(0) AND wire_exp_adj_adder_w_result_range414w(0);
wire_w_lg_w_result_exp_all_one_range416w418w(0) <= wire_w_result_exp_all_one_range416w(0) AND wire_exp_adj_adder_w_result_range417w(0);
wire_w_lg_w_result_exp_all_one_range419w421w(0) <= wire_w_result_exp_all_one_range419w(0) AND wire_exp_adj_adder_w_result_range420w(0);
wire_w_lg_w_result_exp_all_one_range422w424w(0) <= wire_w_result_exp_all_one_range422w(0) AND wire_exp_adj_adder_w_result_range423w(0);
wire_w_lg_exp_is_inf463w(0) <= NOT exp_is_inf;
wire_w_lg_exp_is_zero453w(0) <= NOT exp_is_zero;
wire_w_lg_w_result_exp_not_zero_range450w451w(0) <= NOT wire_w_result_exp_not_zero_range450w(0);
wire_w_lg_w_lg_w468w469w470w(0) <= wire_w_lg_w468w469w(0) OR wire_input_is_infinity_ff1_w_lg_q462w(0);
loop6 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_inf_num459w460w(i) <= wire_w_lg_inf_num459w(i) OR wire_exp_adj_adder_w_lg_w_lg_w_result_range454w455w456w(i);
END GENERATE loop6;
wire_w_lg_w_lg_w_lg_w468w469w470w471w(0) <= wire_w_lg_w_lg_w468w469w470w(0) OR input_is_nan_ff1;
wire_w_lg_w_lg_exp_is_inf457w458w(0) <= wire_w_lg_exp_is_inf457w(0) OR input_is_nan_ff1;
wire_w_lg_exp_is_inf457w(0) <= exp_is_inf OR input_is_infinity_ff1;
wire_w_lg_w_dataa_range211w212w(0) <= wire_w_dataa_range211w(0) OR wire_w_dataa_man_not_zero_range207w(0);
wire_w_lg_w_dataa_range221w222w(0) <= wire_w_dataa_range221w(0) OR wire_w_dataa_man_not_zero_range218w(0);
wire_w_lg_w_dataa_range227w228w(0) <= wire_w_dataa_range227w(0) OR wire_w_dataa_man_not_zero_range223w(0);
wire_w_lg_w_dataa_range233w234w(0) <= wire_w_dataa_range233w(0) OR wire_w_dataa_man_not_zero_range229w(0);
wire_w_lg_w_dataa_range239w240w(0) <= wire_w_dataa_range239w(0) OR wire_w_dataa_man_not_zero_range235w(0);
wire_w_lg_w_dataa_range245w246w(0) <= wire_w_dataa_range245w(0) OR wire_w_dataa_man_not_zero_range241w(0);
wire_w_lg_w_dataa_range251w252w(0) <= wire_w_dataa_range251w(0) OR wire_w_dataa_man_not_zero_range247w(0);
wire_w_lg_w_dataa_range257w258w(0) <= wire_w_dataa_range257w(0) OR wire_w_dataa_man_not_zero_range253w(0);
wire_w_lg_w_dataa_range263w264w(0) <= wire_w_dataa_range263w(0) OR wire_w_dataa_man_not_zero_range259w(0);
wire_w_lg_w_dataa_range157w158w(0) <= wire_w_dataa_range157w(0) OR wire_w_dataa_man_not_zero_range152w(0);
wire_w_lg_w_dataa_range269w270w(0) <= wire_w_dataa_range269w(0) OR wire_w_dataa_man_not_zero_range265w(0);
wire_w_lg_w_dataa_range275w276w(0) <= wire_w_dataa_range275w(0) OR wire_w_dataa_man_not_zero_range271w(0);
wire_w_lg_w_dataa_range281w282w(0) <= wire_w_dataa_range281w(0) OR wire_w_dataa_man_not_zero_range277w(0);
wire_w_lg_w_dataa_range81w82w(0) <= wire_w_dataa_range81w(0) OR wire_w_dataa_exp_not_zero_range72w(0);
wire_w_lg_w_dataa_range91w92w(0) <= wire_w_dataa_range91w(0) OR wire_w_dataa_exp_not_zero_range83w(0);
wire_w_lg_w_dataa_range101w102w(0) <= wire_w_dataa_range101w(0) OR wire_w_dataa_exp_not_zero_range93w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_dataa_exp_not_zero_range103w(0);
wire_w_lg_w_dataa_range121w122w(0) <= wire_w_dataa_range121w(0) OR wire_w_dataa_exp_not_zero_range113w(0);
wire_w_lg_w_dataa_range131w132w(0) <= wire_w_dataa_range131w(0) OR wire_w_dataa_exp_not_zero_range123w(0);
wire_w_lg_w_dataa_range163w164w(0) <= wire_w_dataa_range163w(0) OR wire_w_dataa_man_not_zero_range159w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_dataa_exp_not_zero_range133w(0);
wire_w_lg_w_dataa_range169w170w(0) <= wire_w_dataa_range169w(0) OR wire_w_dataa_man_not_zero_range165w(0);
wire_w_lg_w_dataa_range175w176w(0) <= wire_w_dataa_range175w(0) OR wire_w_dataa_man_not_zero_range171w(0);
wire_w_lg_w_dataa_range181w182w(0) <= wire_w_dataa_range181w(0) OR wire_w_dataa_man_not_zero_range177w(0);
wire_w_lg_w_dataa_range187w188w(0) <= wire_w_dataa_range187w(0) OR wire_w_dataa_man_not_zero_range183w(0);
wire_w_lg_w_dataa_range193w194w(0) <= wire_w_dataa_range193w(0) OR wire_w_dataa_man_not_zero_range189w(0);
wire_w_lg_w_dataa_range199w200w(0) <= wire_w_dataa_range199w(0) OR wire_w_dataa_man_not_zero_range195w(0);
wire_w_lg_w_dataa_range205w206w(0) <= wire_w_dataa_range205w(0) OR wire_w_dataa_man_not_zero_range201w(0);
wire_w_lg_w_datab_range214w215w(0) <= wire_w_datab_range214w(0) OR wire_w_datab_man_not_zero_range210w(0);
wire_w_lg_w_datab_range224w225w(0) <= wire_w_datab_range224w(0) OR wire_w_datab_man_not_zero_range220w(0);
wire_w_lg_w_datab_range230w231w(0) <= wire_w_datab_range230w(0) OR wire_w_datab_man_not_zero_range226w(0);
wire_w_lg_w_datab_range236w237w(0) <= wire_w_datab_range236w(0) OR wire_w_datab_man_not_zero_range232w(0);
wire_w_lg_w_datab_range242w243w(0) <= wire_w_datab_range242w(0) OR wire_w_datab_man_not_zero_range238w(0);
wire_w_lg_w_datab_range248w249w(0) <= wire_w_datab_range248w(0) OR wire_w_datab_man_not_zero_range244w(0);
wire_w_lg_w_datab_range254w255w(0) <= wire_w_datab_range254w(0) OR wire_w_datab_man_not_zero_range250w(0);
wire_w_lg_w_datab_range260w261w(0) <= wire_w_datab_range260w(0) OR wire_w_datab_man_not_zero_range256w(0);
wire_w_lg_w_datab_range266w267w(0) <= wire_w_datab_range266w(0) OR wire_w_datab_man_not_zero_range262w(0);
wire_w_lg_w_datab_range160w161w(0) <= wire_w_datab_range160w(0) OR wire_w_datab_man_not_zero_range155w(0);
wire_w_lg_w_datab_range272w273w(0) <= wire_w_datab_range272w(0) OR wire_w_datab_man_not_zero_range268w(0);
wire_w_lg_w_datab_range278w279w(0) <= wire_w_datab_range278w(0) OR wire_w_datab_man_not_zero_range274w(0);
wire_w_lg_w_datab_range284w285w(0) <= wire_w_datab_range284w(0) OR wire_w_datab_man_not_zero_range280w(0);
wire_w_lg_w_datab_range84w85w(0) <= wire_w_datab_range84w(0) OR wire_w_datab_exp_not_zero_range75w(0);
wire_w_lg_w_datab_range94w95w(0) <= wire_w_datab_range94w(0) OR wire_w_datab_exp_not_zero_range86w(0);
wire_w_lg_w_datab_range104w105w(0) <= wire_w_datab_range104w(0) OR wire_w_datab_exp_not_zero_range96w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_datab_exp_not_zero_range106w(0);
wire_w_lg_w_datab_range124w125w(0) <= wire_w_datab_range124w(0) OR wire_w_datab_exp_not_zero_range116w(0);
wire_w_lg_w_datab_range134w135w(0) <= wire_w_datab_range134w(0) OR wire_w_datab_exp_not_zero_range126w(0);
wire_w_lg_w_datab_range166w167w(0) <= wire_w_datab_range166w(0) OR wire_w_datab_man_not_zero_range162w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_datab_exp_not_zero_range136w(0);
wire_w_lg_w_datab_range172w173w(0) <= wire_w_datab_range172w(0) OR wire_w_datab_man_not_zero_range168w(0);
wire_w_lg_w_datab_range178w179w(0) <= wire_w_datab_range178w(0) OR wire_w_datab_man_not_zero_range174w(0);
wire_w_lg_w_datab_range184w185w(0) <= wire_w_datab_range184w(0) OR wire_w_datab_man_not_zero_range180w(0);
wire_w_lg_w_datab_range190w191w(0) <= wire_w_datab_range190w(0) OR wire_w_datab_man_not_zero_range186w(0);
wire_w_lg_w_datab_range196w197w(0) <= wire_w_datab_range196w(0) OR wire_w_datab_man_not_zero_range192w(0);
wire_w_lg_w_datab_range202w203w(0) <= wire_w_datab_range202w(0) OR wire_w_datab_man_not_zero_range198w(0);
wire_w_lg_w_datab_range208w209w(0) <= wire_w_datab_range208w(0) OR wire_w_datab_man_not_zero_range204w(0);
wire_w_lg_w_result_exp_not_zero_range433w435w(0) <= wire_w_result_exp_not_zero_range433w(0) OR wire_exp_adj_adder_w_result_range405w(0);
wire_w_lg_w_result_exp_not_zero_range436w437w(0) <= wire_w_result_exp_not_zero_range436w(0) OR wire_exp_adj_adder_w_result_range408w(0);
wire_w_lg_w_result_exp_not_zero_range438w439w(0) <= wire_w_result_exp_not_zero_range438w(0) OR wire_exp_adj_adder_w_result_range411w(0);
wire_w_lg_w_result_exp_not_zero_range440w441w(0) <= wire_w_result_exp_not_zero_range440w(0) OR wire_exp_adj_adder_w_result_range414w(0);
wire_w_lg_w_result_exp_not_zero_range442w443w(0) <= wire_w_result_exp_not_zero_range442w(0) OR wire_exp_adj_adder_w_result_range417w(0);
wire_w_lg_w_result_exp_not_zero_range444w445w(0) <= wire_w_result_exp_not_zero_range444w(0) OR wire_exp_adj_adder_w_result_range420w(0);
wire_w_lg_w_result_exp_not_zero_range446w447w(0) <= wire_w_result_exp_not_zero_range446w(0) OR wire_exp_adj_adder_w_result_range423w(0);
wire_w_lg_w_result_exp_not_zero_range448w449w(0) <= wire_w_result_exp_not_zero_range448w(0) OR wire_exp_adj_adder_w_result_range426w(0);
wire_w_lg_w_sticky_bit_range306w309w(0) <= wire_w_sticky_bit_range306w(0) OR wire_man_product2_mult_w_result_range308w(0);
wire_w_lg_w_sticky_bit_range337w339w(0) <= wire_w_sticky_bit_range337w(0) OR wire_man_product2_mult_w_result_range338w(0);
wire_w_lg_w_sticky_bit_range340w342w(0) <= wire_w_sticky_bit_range340w(0) OR wire_man_product2_mult_w_result_range341w(0);
wire_w_lg_w_sticky_bit_range343w345w(0) <= wire_w_sticky_bit_range343w(0) OR wire_man_product2_mult_w_result_range344w(0);
wire_w_lg_w_sticky_bit_range346w348w(0) <= wire_w_sticky_bit_range346w(0) OR wire_man_product2_mult_w_result_range347w(0);
wire_w_lg_w_sticky_bit_range349w351w(0) <= wire_w_sticky_bit_range349w(0) OR wire_man_product2_mult_w_result_range350w(0);
wire_w_lg_w_sticky_bit_range352w354w(0) <= wire_w_sticky_bit_range352w(0) OR wire_man_product2_mult_w_result_range353w(0);
wire_w_lg_w_sticky_bit_range355w357w(0) <= wire_w_sticky_bit_range355w(0) OR wire_man_product2_mult_w_result_range356w(0);
wire_w_lg_w_sticky_bit_range358w360w(0) <= wire_w_sticky_bit_range358w(0) OR wire_man_product2_mult_w_result_range359w(0);
wire_w_lg_w_sticky_bit_range361w363w(0) <= wire_w_sticky_bit_range361w(0) OR wire_man_product2_mult_w_result_range362w(0);
wire_w_lg_w_sticky_bit_range364w366w(0) <= wire_w_sticky_bit_range364w(0) OR wire_man_product2_mult_w_result_range365w(0);
wire_w_lg_w_sticky_bit_range310w312w(0) <= wire_w_sticky_bit_range310w(0) OR wire_man_product2_mult_w_result_range311w(0);
wire_w_lg_w_sticky_bit_range367w369w(0) <= wire_w_sticky_bit_range367w(0) OR wire_man_product2_mult_w_result_range368w(0);
wire_w_lg_w_sticky_bit_range370w373w(0) <= wire_w_sticky_bit_range370w(0) OR wire_man_product2_mult_w_lg_w_result_range298w372w(0);
wire_w_lg_w_sticky_bit_range313w315w(0) <= wire_w_sticky_bit_range313w(0) OR wire_man_product2_mult_w_result_range314w(0);
wire_w_lg_w_sticky_bit_range316w318w(0) <= wire_w_sticky_bit_range316w(0) OR wire_man_product2_mult_w_result_range317w(0);
wire_w_lg_w_sticky_bit_range319w321w(0) <= wire_w_sticky_bit_range319w(0) OR wire_man_product2_mult_w_result_range320w(0);
wire_w_lg_w_sticky_bit_range322w324w(0) <= wire_w_sticky_bit_range322w(0) OR wire_man_product2_mult_w_result_range323w(0);
wire_w_lg_w_sticky_bit_range325w327w(0) <= wire_w_sticky_bit_range325w(0) OR wire_man_product2_mult_w_result_range326w(0);
wire_w_lg_w_sticky_bit_range328w330w(0) <= wire_w_sticky_bit_range328w(0) OR wire_man_product2_mult_w_result_range329w(0);
wire_w_lg_w_sticky_bit_range331w333w(0) <= wire_w_sticky_bit_range331w(0) OR wire_man_product2_mult_w_result_range332w(0);
wire_w_lg_w_sticky_bit_range334w336w(0) <= wire_w_sticky_bit_range334w(0) OR wire_man_product2_mult_w_result_range335w(0);
bias <= ( "0" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
dataa_exp_all_one <= ( wire_w_lg_w_dataa_range141w147w & wire_w_lg_w_dataa_range131w137w & wire_w_lg_w_dataa_range121w127w & wire_w_lg_w_dataa_range111w117w & wire_w_lg_w_dataa_range101w107w & wire_w_lg_w_dataa_range91w97w & wire_w_lg_w_dataa_range81w87w & dataa(23));
dataa_exp_not_zero <= ( wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range131w132w & wire_w_lg_w_dataa_range121w122w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range101w102w & wire_w_lg_w_dataa_range91w92w & wire_w_lg_w_dataa_range81w82w & dataa(23));
dataa_man_not_zero <= ( wire_w_lg_w_dataa_range281w282w & wire_w_lg_w_dataa_range275w276w & wire_w_lg_w_dataa_range269w270w & wire_w_lg_w_dataa_range263w264w & wire_w_lg_w_dataa_range257w258w & wire_w_lg_w_dataa_range251w252w & wire_w_lg_w_dataa_range245w246w & wire_w_lg_w_dataa_range239w240w & wire_w_lg_w_dataa_range233w234w & wire_w_lg_w_dataa_range227w228w & wire_w_lg_w_dataa_range221w222w & dataa(11) & wire_w_lg_w_dataa_range211w212w & wire_w_lg_w_dataa_range205w206w & wire_w_lg_w_dataa_range199w200w & wire_w_lg_w_dataa_range193w194w & wire_w_lg_w_dataa_range187w188w & wire_w_lg_w_dataa_range181w182w & wire_w_lg_w_dataa_range175w176w & wire_w_lg_w_dataa_range169w170w & wire_w_lg_w_dataa_range163w164w & wire_w_lg_w_dataa_range157w158w & dataa(0));
datab_exp_all_one <= ( wire_w_lg_w_datab_range144w149w & wire_w_lg_w_datab_range134w139w & wire_w_lg_w_datab_range124w129w & wire_w_lg_w_datab_range114w119w & wire_w_lg_w_datab_range104w109w & wire_w_lg_w_datab_range94w99w & wire_w_lg_w_datab_range84w89w & datab(23));
datab_exp_not_zero <= ( wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range134w135w & wire_w_lg_w_datab_range124w125w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range104w105w & wire_w_lg_w_datab_range94w95w & wire_w_lg_w_datab_range84w85w & datab(23));
datab_man_not_zero <= ( wire_w_lg_w_datab_range284w285w & wire_w_lg_w_datab_range278w279w & wire_w_lg_w_datab_range272w273w & wire_w_lg_w_datab_range266w267w & wire_w_lg_w_datab_range260w261w & wire_w_lg_w_datab_range254w255w & wire_w_lg_w_datab_range248w249w & wire_w_lg_w_datab_range242w243w & wire_w_lg_w_datab_range236w237w & wire_w_lg_w_datab_range230w231w & wire_w_lg_w_datab_range224w225w & datab(11) & wire_w_lg_w_datab_range214w215w & wire_w_lg_w_datab_range208w209w & wire_w_lg_w_datab_range202w203w & wire_w_lg_w_datab_range196w197w & wire_w_lg_w_datab_range190w191w & wire_w_lg_w_datab_range184w185w & wire_w_lg_w_datab_range178w179w & wire_w_lg_w_datab_range172w173w & wire_w_lg_w_datab_range166w167w & wire_w_lg_w_datab_range160w161w & datab(0));
exp_is_inf <= (((NOT wire_exp_adj_adder_result(9)) AND wire_exp_adj_adder_result(8)) OR ((NOT wire_exp_adj_adder_result(8)) AND result_exp_all_one(7)));
exp_is_zero <= wire_exp_adj_adder_w_lg_w_result_range429w452w(0);
expmod <= ( "00000000" & wire_delay_man_product_msb_w_lg_q392w & wire_delay_man_product_msb_w_lg_q394w);
inf_num <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
lsb_bit <= man_shift_full(1);
man_result_round <= (wire_man_round_p2_w_lg_w_q_range399w400w OR wire_man_round_p2_w_lg_w_q_range396w397w);
man_shift_full <= (wire_man_product2_mult_w_lg_w_result_range302w303w OR wire_man_product2_mult_w_lg_w_result_range299w300w);
result <= ( sign_node_ff4 & exp_result_ff(7 DOWNTO 0) & man_result_ff(22 DOWNTO 0));
result_exp_all_one <= ( wire_w_lg_w_result_exp_all_one_range422w424w & wire_w_lg_w_result_exp_all_one_range419w421w & wire_w_lg_w_result_exp_all_one_range416w418w & wire_w_lg_w_result_exp_all_one_range413w415w & wire_w_lg_w_result_exp_all_one_range410w412w & wire_w_lg_w_result_exp_all_one_range407w409w & wire_w_lg_w_result_exp_all_one_range403w406w & wire_exp_adj_adder_result(0));
result_exp_not_zero <= ( wire_w_lg_w_result_exp_not_zero_range448w449w & wire_w_lg_w_result_exp_not_zero_range446w447w & wire_w_lg_w_result_exp_not_zero_range444w445w & wire_w_lg_w_result_exp_not_zero_range442w443w & wire_w_lg_w_result_exp_not_zero_range440w441w & wire_w_lg_w_result_exp_not_zero_range438w439w & wire_w_lg_w_result_exp_not_zero_range436w437w & wire_w_lg_w_result_exp_not_zero_range433w435w & wire_exp_adj_adder_result(0));
round_bit <= man_shift_full(0);
round_carry <= (round_dffe AND (lsb_dffe OR sticky_dffe));
sticky_bit <= ( wire_w_lg_w_sticky_bit_range370w373w & wire_w_lg_w_sticky_bit_range367w369w & wire_w_lg_w_sticky_bit_range364w366w & wire_w_lg_w_sticky_bit_range361w363w & wire_w_lg_w_sticky_bit_range358w360w & wire_w_lg_w_sticky_bit_range355w357w & wire_w_lg_w_sticky_bit_range352w354w & wire_w_lg_w_sticky_bit_range349w351w & wire_w_lg_w_sticky_bit_range346w348w & wire_w_lg_w_sticky_bit_range343w345w & wire_w_lg_w_sticky_bit_range340w342w & wire_w_lg_w_sticky_bit_range337w339w & wire_w_lg_w_sticky_bit_range334w336w & wire_w_lg_w_sticky_bit_range331w333w & wire_w_lg_w_sticky_bit_range328w330w & wire_w_lg_w_sticky_bit_range325w327w & wire_w_lg_w_sticky_bit_range322w324w & wire_w_lg_w_sticky_bit_range319w321w & wire_w_lg_w_sticky_bit_range316w318w & wire_w_lg_w_sticky_bit_range313w315w & wire_w_lg_w_sticky_bit_range310w312w & wire_w_lg_w_sticky_bit_range306w309w & wire_man_product2_mult_result(0));
wire_w_dataa_range211w(0) <= dataa(10);
wire_w_dataa_range221w(0) <= dataa(12);
wire_w_dataa_range227w(0) <= dataa(13);
wire_w_dataa_range233w(0) <= dataa(14);
wire_w_dataa_range239w(0) <= dataa(15);
wire_w_dataa_range245w(0) <= dataa(16);
wire_w_dataa_range251w(0) <= dataa(17);
wire_w_dataa_range257w(0) <= dataa(18);
wire_w_dataa_range263w(0) <= dataa(19);
wire_w_dataa_range157w(0) <= dataa(1);
wire_w_dataa_range269w(0) <= dataa(20);
wire_w_dataa_range275w(0) <= dataa(21);
wire_w_dataa_range281w(0) <= dataa(22);
wire_w_dataa_range81w(0) <= dataa(24);
wire_w_dataa_range91w(0) <= dataa(25);
wire_w_dataa_range101w(0) <= dataa(26);
wire_w_dataa_range111w(0) <= dataa(27);
wire_w_dataa_range121w(0) <= dataa(28);
wire_w_dataa_range131w(0) <= dataa(29);
wire_w_dataa_range163w(0) <= dataa(2);
wire_w_dataa_range141w(0) <= dataa(30);
wire_w_dataa_range169w(0) <= dataa(3);
wire_w_dataa_range175w(0) <= dataa(4);
wire_w_dataa_range181w(0) <= dataa(5);
wire_w_dataa_range187w(0) <= dataa(6);
wire_w_dataa_range193w(0) <= dataa(7);
wire_w_dataa_range199w(0) <= dataa(8);
wire_w_dataa_range205w(0) <= dataa(9);
wire_w_dataa_exp_all_one_range77w(0) <= dataa_exp_all_one(0);
wire_w_dataa_exp_all_one_range88w(0) <= dataa_exp_all_one(1);
wire_w_dataa_exp_all_one_range98w(0) <= dataa_exp_all_one(2);
wire_w_dataa_exp_all_one_range108w(0) <= dataa_exp_all_one(3);
wire_w_dataa_exp_all_one_range118w(0) <= dataa_exp_all_one(4);
wire_w_dataa_exp_all_one_range128w(0) <= dataa_exp_all_one(5);
wire_w_dataa_exp_all_one_range138w(0) <= dataa_exp_all_one(6);
wire_w_dataa_exp_not_zero_range72w(0) <= dataa_exp_not_zero(0);
wire_w_dataa_exp_not_zero_range83w(0) <= dataa_exp_not_zero(1);
wire_w_dataa_exp_not_zero_range93w(0) <= dataa_exp_not_zero(2);
wire_w_dataa_exp_not_zero_range103w(0) <= dataa_exp_not_zero(3);
wire_w_dataa_exp_not_zero_range113w(0) <= dataa_exp_not_zero(4);
wire_w_dataa_exp_not_zero_range123w(0) <= dataa_exp_not_zero(5);
wire_w_dataa_exp_not_zero_range133w(0) <= dataa_exp_not_zero(6);
wire_w_dataa_man_not_zero_range152w(0) <= dataa_man_not_zero(0);
wire_w_dataa_man_not_zero_range218w(0) <= dataa_man_not_zero(11);
wire_w_dataa_man_not_zero_range223w(0) <= dataa_man_not_zero(12);
wire_w_dataa_man_not_zero_range229w(0) <= dataa_man_not_zero(13);
wire_w_dataa_man_not_zero_range235w(0) <= dataa_man_not_zero(14);
wire_w_dataa_man_not_zero_range241w(0) <= dataa_man_not_zero(15);
wire_w_dataa_man_not_zero_range247w(0) <= dataa_man_not_zero(16);
wire_w_dataa_man_not_zero_range253w(0) <= dataa_man_not_zero(17);
wire_w_dataa_man_not_zero_range259w(0) <= dataa_man_not_zero(18);
wire_w_dataa_man_not_zero_range265w(0) <= dataa_man_not_zero(19);
wire_w_dataa_man_not_zero_range159w(0) <= dataa_man_not_zero(1);
wire_w_dataa_man_not_zero_range271w(0) <= dataa_man_not_zero(20);
wire_w_dataa_man_not_zero_range277w(0) <= dataa_man_not_zero(21);
wire_w_dataa_man_not_zero_range165w(0) <= dataa_man_not_zero(2);
wire_w_dataa_man_not_zero_range171w(0) <= dataa_man_not_zero(3);
wire_w_dataa_man_not_zero_range177w(0) <= dataa_man_not_zero(4);
wire_w_dataa_man_not_zero_range183w(0) <= dataa_man_not_zero(5);
wire_w_dataa_man_not_zero_range189w(0) <= dataa_man_not_zero(6);
wire_w_dataa_man_not_zero_range195w(0) <= dataa_man_not_zero(7);
wire_w_dataa_man_not_zero_range201w(0) <= dataa_man_not_zero(8);
wire_w_dataa_man_not_zero_range207w(0) <= dataa_man_not_zero(9);
wire_w_datab_range214w(0) <= datab(10);
wire_w_datab_range224w(0) <= datab(12);
wire_w_datab_range230w(0) <= datab(13);
wire_w_datab_range236w(0) <= datab(14);
wire_w_datab_range242w(0) <= datab(15);
wire_w_datab_range248w(0) <= datab(16);
wire_w_datab_range254w(0) <= datab(17);
wire_w_datab_range260w(0) <= datab(18);
wire_w_datab_range266w(0) <= datab(19);
wire_w_datab_range160w(0) <= datab(1);
wire_w_datab_range272w(0) <= datab(20);
wire_w_datab_range278w(0) <= datab(21);
wire_w_datab_range284w(0) <= datab(22);
wire_w_datab_range84w(0) <= datab(24);
wire_w_datab_range94w(0) <= datab(25);
wire_w_datab_range104w(0) <= datab(26);
wire_w_datab_range114w(0) <= datab(27);
wire_w_datab_range124w(0) <= datab(28);
wire_w_datab_range134w(0) <= datab(29);
wire_w_datab_range166w(0) <= datab(2);
wire_w_datab_range144w(0) <= datab(30);
wire_w_datab_range172w(0) <= datab(3);
wire_w_datab_range178w(0) <= datab(4);
wire_w_datab_range184w(0) <= datab(5);
wire_w_datab_range190w(0) <= datab(6);
wire_w_datab_range196w(0) <= datab(7);
wire_w_datab_range202w(0) <= datab(8);
wire_w_datab_range208w(0) <= datab(9);
wire_w_datab_exp_all_one_range79w(0) <= datab_exp_all_one(0);
wire_w_datab_exp_all_one_range90w(0) <= datab_exp_all_one(1);
wire_w_datab_exp_all_one_range100w(0) <= datab_exp_all_one(2);
wire_w_datab_exp_all_one_range110w(0) <= datab_exp_all_one(3);
wire_w_datab_exp_all_one_range120w(0) <= datab_exp_all_one(4);
wire_w_datab_exp_all_one_range130w(0) <= datab_exp_all_one(5);
wire_w_datab_exp_all_one_range140w(0) <= datab_exp_all_one(6);
wire_w_datab_exp_not_zero_range75w(0) <= datab_exp_not_zero(0);
wire_w_datab_exp_not_zero_range86w(0) <= datab_exp_not_zero(1);
wire_w_datab_exp_not_zero_range96w(0) <= datab_exp_not_zero(2);
wire_w_datab_exp_not_zero_range106w(0) <= datab_exp_not_zero(3);
wire_w_datab_exp_not_zero_range116w(0) <= datab_exp_not_zero(4);
wire_w_datab_exp_not_zero_range126w(0) <= datab_exp_not_zero(5);
wire_w_datab_exp_not_zero_range136w(0) <= datab_exp_not_zero(6);
wire_w_datab_man_not_zero_range155w(0) <= datab_man_not_zero(0);
wire_w_datab_man_not_zero_range220w(0) <= datab_man_not_zero(11);
wire_w_datab_man_not_zero_range226w(0) <= datab_man_not_zero(12);
wire_w_datab_man_not_zero_range232w(0) <= datab_man_not_zero(13);
wire_w_datab_man_not_zero_range238w(0) <= datab_man_not_zero(14);
wire_w_datab_man_not_zero_range244w(0) <= datab_man_not_zero(15);
wire_w_datab_man_not_zero_range250w(0) <= datab_man_not_zero(16);
wire_w_datab_man_not_zero_range256w(0) <= datab_man_not_zero(17);
wire_w_datab_man_not_zero_range262w(0) <= datab_man_not_zero(18);
wire_w_datab_man_not_zero_range268w(0) <= datab_man_not_zero(19);
wire_w_datab_man_not_zero_range162w(0) <= datab_man_not_zero(1);
wire_w_datab_man_not_zero_range274w(0) <= datab_man_not_zero(20);
wire_w_datab_man_not_zero_range280w(0) <= datab_man_not_zero(21);
wire_w_datab_man_not_zero_range168w(0) <= datab_man_not_zero(2);
wire_w_datab_man_not_zero_range174w(0) <= datab_man_not_zero(3);
wire_w_datab_man_not_zero_range180w(0) <= datab_man_not_zero(4);
wire_w_datab_man_not_zero_range186w(0) <= datab_man_not_zero(5);
wire_w_datab_man_not_zero_range192w(0) <= datab_man_not_zero(6);
wire_w_datab_man_not_zero_range198w(0) <= datab_man_not_zero(7);
wire_w_datab_man_not_zero_range204w(0) <= datab_man_not_zero(8);
wire_w_datab_man_not_zero_range210w(0) <= datab_man_not_zero(9);
wire_w_man_result_round_range475w <= man_result_round(21 DOWNTO 0);
wire_w_man_result_round_range465w(0) <= man_result_round(22);
wire_w_man_shift_full_range379w <= man_shift_full(24 DOWNTO 1);
wire_w_result_exp_all_one_range403w(0) <= result_exp_all_one(0);
wire_w_result_exp_all_one_range407w(0) <= result_exp_all_one(1);
wire_w_result_exp_all_one_range410w(0) <= result_exp_all_one(2);
wire_w_result_exp_all_one_range413w(0) <= result_exp_all_one(3);
wire_w_result_exp_all_one_range416w(0) <= result_exp_all_one(4);
wire_w_result_exp_all_one_range419w(0) <= result_exp_all_one(5);
wire_w_result_exp_all_one_range422w(0) <= result_exp_all_one(6);
wire_w_result_exp_not_zero_range433w(0) <= result_exp_not_zero(0);
wire_w_result_exp_not_zero_range436w(0) <= result_exp_not_zero(1);
wire_w_result_exp_not_zero_range438w(0) <= result_exp_not_zero(2);
wire_w_result_exp_not_zero_range440w(0) <= result_exp_not_zero(3);
wire_w_result_exp_not_zero_range442w(0) <= result_exp_not_zero(4);
wire_w_result_exp_not_zero_range444w(0) <= result_exp_not_zero(5);
wire_w_result_exp_not_zero_range446w(0) <= result_exp_not_zero(6);
wire_w_result_exp_not_zero_range448w(0) <= result_exp_not_zero(7);
wire_w_result_exp_not_zero_range450w(0) <= result_exp_not_zero(8);
wire_w_sticky_bit_range306w(0) <= sticky_bit(0);
wire_w_sticky_bit_range337w(0) <= sticky_bit(10);
wire_w_sticky_bit_range340w(0) <= sticky_bit(11);
wire_w_sticky_bit_range343w(0) <= sticky_bit(12);
wire_w_sticky_bit_range346w(0) <= sticky_bit(13);
wire_w_sticky_bit_range349w(0) <= sticky_bit(14);
wire_w_sticky_bit_range352w(0) <= sticky_bit(15);
wire_w_sticky_bit_range355w(0) <= sticky_bit(16);
wire_w_sticky_bit_range358w(0) <= sticky_bit(17);
wire_w_sticky_bit_range361w(0) <= sticky_bit(18);
wire_w_sticky_bit_range364w(0) <= sticky_bit(19);
wire_w_sticky_bit_range310w(0) <= sticky_bit(1);
wire_w_sticky_bit_range367w(0) <= sticky_bit(20);
wire_w_sticky_bit_range370w(0) <= sticky_bit(21);
wire_w_sticky_bit_range313w(0) <= sticky_bit(2);
wire_w_sticky_bit_range316w(0) <= sticky_bit(3);
wire_w_sticky_bit_range319w(0) <= sticky_bit(4);
wire_w_sticky_bit_range322w(0) <= sticky_bit(5);
wire_w_sticky_bit_range325w(0) <= sticky_bit(6);
wire_w_sticky_bit_range328w(0) <= sticky_bit(7);
wire_w_sticky_bit_range331w(0) <= sticky_bit(8);
wire_w_sticky_bit_range334w(0) <= sticky_bit(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_exp_all_one_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_exp_all_one_ff_p1 <= dataa_exp_all_one(7);
END IF;
END IF;
END PROCESS;
wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0);
wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_exp_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero(7);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_not_zero_ff_p1 <= dataa_man_not_zero(10);
END IF;
END IF;
END PROCESS;
wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0) <= NOT wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0) <= dataa_man_not_zero_ff_p1 OR dataa_man_not_zero_ff_p2;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_not_zero_ff_p2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_not_zero_ff_p2 <= dataa_man_not_zero(22);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_exp_all_one_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_exp_all_one_ff_p1 <= datab_exp_all_one(7);
END IF;
END IF;
END PROCESS;
wire_datab_exp_all_one_ff_p1_w_lg_q294w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0);
wire_datab_exp_all_one_ff_p1_w_lg_q289w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_exp_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_exp_not_zero_ff_p1 <= datab_exp_not_zero(7);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_not_zero_ff_p1 <= datab_man_not_zero(10);
END IF;
END IF;
END PROCESS;
wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0) <= NOT wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
wire_datab_man_not_zero_ff_p1_w_lg_q288w(0) <= datab_man_not_zero_ff_p1 OR datab_man_not_zero_ff_p2;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_not_zero_ff_p2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_not_zero_ff_p2 <= datab_man_not_zero(22);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp2_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp2_bias <= delay_exp_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp_bias <= wire_exp_bias_subtr_result;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb <= delay_man_product_msb_p0;
END IF;
END IF;
END PROCESS;
wire_delay_man_product_msb_w_lg_q392w(0) <= delay_man_product_msb AND wire_man_round_p2_w_q_range391w(0);
wire_delay_man_product_msb_w_lg_q394w(0) <= delay_man_product_msb XOR wire_man_round_p2_w_q_range391w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb_p0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb_p0 <= wire_man_product2_mult_w_result_range298w(0);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_add_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_add_p1 <= wire_exp_add_adder_result;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_ff <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_ff <= wire_w_lg_w_lg_inf_num459w460w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q294w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff1 <= input_is_infinity_dffe_1;
END IF;
END IF;
END PROCESS;
wire_input_is_infinity_ff1_w_lg_q462w(0) <= input_is_infinity_ff1 AND wire_input_not_zero_ff1_w_lg_q461w(0);
wire_input_is_infinity_ff1_w_lg_q464w(0) <= NOT input_is_infinity_ff1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q289w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_1 <= input_is_nan_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff1 <= input_is_nan_dffe_1;
END IF;
END IF;
END PROCESS;
wire_input_is_nan_ff1_w_lg_q474w(0) <= NOT input_is_nan_ff1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 AND datab_exp_not_zero_ff_p1);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_1 <= input_not_zero_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff1 <= input_not_zero_dffe_1;
END IF;
END IF;
END PROCESS;
wire_input_not_zero_ff1_w_lg_q461w(0) <= NOT input_not_zero_ff1;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN lsb_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN lsb_dffe <= lsb_bit;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_result_ff <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_result_ff <= ( wire_w_lg_w_lg_w_lg_w468w469w470w471w & wire_w_lg_w_lg_w478w479w480w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p <= wire_w_man_shift_full_range379w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p2 <= wire_man_round_adder_result;
END IF;
END IF;
END PROCESS;
loop7 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_q_range399w400w(i) <= wire_man_round_p2_w_q_range399w(i) AND wire_man_round_p2_w_lg_w_q_range391w398w(0);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_q_range396w397w(i) <= wire_man_round_p2_w_q_range396w(i) AND wire_man_round_p2_w_q_range391w(0);
END GENERATE loop8;
wire_man_round_p2_w_lg_w_q_range391w398w(0) <= NOT wire_man_round_p2_w_q_range391w(0);
wire_man_round_p2_w_q_range399w <= man_round_p2(23 DOWNTO 0);
wire_man_round_p2_w_q_range396w <= man_round_p2(24 DOWNTO 1);
wire_man_round_p2_w_q_range391w(0) <= man_round_p2(24);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_dffe <= round_bit;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff0 <= (dataa(31) XOR datab(31));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff1 <= sign_node_ff0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff2 <= sign_node_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff3 <= sign_node_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff4 <= sign_node_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_dffe <= sticky_bit(22);
END IF;
END IF;
END PROCESS;
wire_exp_add_adder_dataa <= ( "0" & dataa(30 DOWNTO 23));
wire_exp_add_adder_datab <= ( "0" & datab(30 DOWNTO 23));
exp_add_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => wire_exp_add_adder_dataa,
datab => wire_exp_add_adder_datab,
result => wire_exp_add_adder_result
);
loop9 : FOR i IN 0 TO 7 GENERATE
wire_exp_adj_adder_w_lg_w_lg_w_result_range454w455w456w(i) <= wire_exp_adj_adder_w_lg_w_result_range454w455w(i) AND input_not_zero_ff1;
END GENERATE loop9;
loop10 : FOR i IN 0 TO 7 GENERATE
wire_exp_adj_adder_w_lg_w_result_range454w455w(i) <= wire_exp_adj_adder_w_result_range454w(i) AND wire_w_lg_exp_is_zero453w(0);
END GENERATE loop10;
wire_exp_adj_adder_w_lg_w_result_range429w452w(0) <= wire_exp_adj_adder_w_result_range429w(0) OR wire_w_lg_w_result_exp_not_zero_range450w451w(0);
wire_exp_adj_adder_w_result_range405w(0) <= wire_exp_adj_adder_result(1);
wire_exp_adj_adder_w_result_range408w(0) <= wire_exp_adj_adder_result(2);
wire_exp_adj_adder_w_result_range411w(0) <= wire_exp_adj_adder_result(3);
wire_exp_adj_adder_w_result_range414w(0) <= wire_exp_adj_adder_result(4);
wire_exp_adj_adder_w_result_range417w(0) <= wire_exp_adj_adder_result(5);
wire_exp_adj_adder_w_result_range420w(0) <= wire_exp_adj_adder_result(6);
wire_exp_adj_adder_w_result_range454w <= wire_exp_adj_adder_result(7 DOWNTO 0);
wire_exp_adj_adder_w_result_range423w(0) <= wire_exp_adj_adder_result(7);
wire_exp_adj_adder_w_result_range426w(0) <= wire_exp_adj_adder_result(8);
wire_exp_adj_adder_w_result_range429w(0) <= wire_exp_adj_adder_result(9);
exp_adj_adder : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 10
)
PORT MAP (
cin => wire_gnd,
dataa => delay_exp2_bias,
datab => expmod,
result => wire_exp_adj_adder_result
);
wire_exp_bias_subtr_dataa <= ( "0" & exp_add_p1(8 DOWNTO 0));
wire_exp_bias_subtr_datab <= ( bias(9 DOWNTO 0));
exp_bias_subtr : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 0,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 10
)
PORT MAP (
dataa => wire_exp_bias_subtr_dataa,
datab => wire_exp_bias_subtr_datab,
result => wire_exp_bias_subtr_result
);
wire_man_round_adder_dataa <= ( "0" & man_round_p);
wire_man_round_adder_datab <= ( "000000000000000000000000" & round_carry);
man_round_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 0,
LPM_WIDTH => 25
)
PORT MAP (
dataa => wire_man_round_adder_dataa,
datab => wire_man_round_adder_datab,
result => wire_man_round_adder_result
);
loop11 : FOR i IN 0 TO 24 GENERATE
wire_man_product2_mult_w_lg_w_result_range302w303w(i) <= wire_man_product2_mult_w_result_range302w(i) AND wire_man_product2_mult_w_lg_w_result_range298w301w(0);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 24 GENERATE
wire_man_product2_mult_w_lg_w_result_range299w300w(i) <= wire_man_product2_mult_w_result_range299w(i) AND wire_man_product2_mult_w_result_range298w(0);
END GENERATE loop12;
wire_man_product2_mult_w_lg_w_result_range298w372w(0) <= wire_man_product2_mult_w_result_range298w(0) AND wire_man_product2_mult_w_result_range371w(0);
wire_man_product2_mult_w_lg_w_result_range298w301w(0) <= NOT wire_man_product2_mult_w_result_range298w(0);
wire_man_product2_mult_dataa <= ( "1" & dataa(22 DOWNTO 0));
wire_man_product2_mult_datab <= ( "1" & datab(22 DOWNTO 0));
wire_man_product2_mult_w_result_range335w(0) <= wire_man_product2_mult_result(10);
wire_man_product2_mult_w_result_range338w(0) <= wire_man_product2_mult_result(11);
wire_man_product2_mult_w_result_range341w(0) <= wire_man_product2_mult_result(12);
wire_man_product2_mult_w_result_range344w(0) <= wire_man_product2_mult_result(13);
wire_man_product2_mult_w_result_range347w(0) <= wire_man_product2_mult_result(14);
wire_man_product2_mult_w_result_range350w(0) <= wire_man_product2_mult_result(15);
wire_man_product2_mult_w_result_range353w(0) <= wire_man_product2_mult_result(16);
wire_man_product2_mult_w_result_range356w(0) <= wire_man_product2_mult_result(17);
wire_man_product2_mult_w_result_range359w(0) <= wire_man_product2_mult_result(18);
wire_man_product2_mult_w_result_range362w(0) <= wire_man_product2_mult_result(19);
wire_man_product2_mult_w_result_range308w(0) <= wire_man_product2_mult_result(1);
wire_man_product2_mult_w_result_range365w(0) <= wire_man_product2_mult_result(20);
wire_man_product2_mult_w_result_range368w(0) <= wire_man_product2_mult_result(21);
wire_man_product2_mult_w_result_range371w(0) <= wire_man_product2_mult_result(22);
wire_man_product2_mult_w_result_range311w(0) <= wire_man_product2_mult_result(2);
wire_man_product2_mult_w_result_range314w(0) <= wire_man_product2_mult_result(3);
wire_man_product2_mult_w_result_range302w <= wire_man_product2_mult_result(46 DOWNTO 22);
wire_man_product2_mult_w_result_range299w <= wire_man_product2_mult_result(47 DOWNTO 23);
wire_man_product2_mult_w_result_range298w(0) <= wire_man_product2_mult_result(47);
wire_man_product2_mult_w_result_range317w(0) <= wire_man_product2_mult_result(4);
wire_man_product2_mult_w_result_range320w(0) <= wire_man_product2_mult_result(5);
wire_man_product2_mult_w_result_range323w(0) <= wire_man_product2_mult_result(6);
wire_man_product2_mult_w_result_range326w(0) <= wire_man_product2_mult_result(7);
wire_man_product2_mult_w_result_range329w(0) <= wire_man_product2_mult_result(8);
wire_man_product2_mult_w_result_range332w(0) <= wire_man_product2_mult_result(9);
man_product2_mult : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 24,
LPM_WIDTHB => 24,
LPM_WIDTHP => 48,
LPM_WIDTHS => 1,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_man_product2_mult_dataa,
datab => wire_man_product2_mult_datab,
result => wire_man_product2_mult_result
);
END RTL; --fp_mul_altfp_mult_ppo
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_mul IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mul;
ARCHITECTURE RTL OF fp_mul IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_mul_altfp_mult_ppo
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_mul_altfp_mult_ppo_component : fp_mul_altfp_mult_ppo
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: FPM_FORMAT STRING "Single"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "5"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_mul.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_mul.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_mul.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_mul_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_mul.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_mul.cmp TRUE TRUE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
b345c1472a62dc3faa56f608a15d601e
| 0.696842 | 2.396544 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_clock_divider.vhd
| 1 | 2,946 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_clock_divider
---- Version: 1.0.0
---- Description:
---- Generate output clock = input clock / divider
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx clock generator inputs and outputs
--=============================================================================
entity ccsds_rxtx_clock_divider is
generic(
constant CCSDS_RXTX_CLOCK_DIVIDER: integer range 1 to 4096
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
-- outputs
clk_o: out std_logic
);
end ccsds_rxtx_clock_divider;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_rxtx_clock_divider is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKCLKDIV0: if (CCSDS_RXTX_CLOCK_DIVIDER mod 2 /= 0) and (CCSDS_RXTX_CLOCK_DIVIDER /= 1) generate
process
begin
report "ERROR: CLOCK DIVIDER MUST BE A MULTIPLE OF 2 OR 1" severity failure;
wait;
end process;
end generate CHKCLKDIV0;
-- internal processing
CLOCKDIVIDER1P: if (CCSDS_RXTX_CLOCK_DIVIDER = 1) generate
clk_o <= clk_i and (not rst_i);
end generate CLOCKDIVIDER1P;
CLOCKDIVIDERNP: if (CCSDS_RXTX_CLOCK_DIVIDER /= 1) generate
--=============================================================================
-- Begin of clockdividerp
-- Clock divider
--=============================================================================
-- read: rst_i
-- write: clk_o
-- r/w:
CLOCKDIVIDERP : process (clk_i, rst_i)
-- variables instantiation
variable counter: integer range 0 to CCSDS_RXTX_CLOCK_DIVIDER/2-1 := CCSDS_RXTX_CLOCK_DIVIDER/2-1;
variable clock_state: std_logic := '1';
begin
if (rst_i = '1') then
clk_o <= '0';
clock_state := '1';
counter := CCSDS_RXTX_CLOCK_DIVIDER/2-1;
else
-- on each clock rising edge
if rising_edge(clk_i) then
clk_o <= clock_state;
if (counter = 0) then
clock_state := clock_state xor '1';
counter := CCSDS_RXTX_CLOCK_DIVIDER/2-1;
else
counter := counter-1;
end if;
end if;
end if;
end process;
end generate CLOCKDIVIDERNP;
end structure;
|
mit
|
7616a30e6cd2012b8c1de1093a70f3e0
| 0.502716 | 4.63937 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/hash.vhd
| 1 | 11,681 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/17 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Implements a hash table. The number of entries is fixed to 2048. The entries length is configurable
--* (up to 18 bits)
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity HashTable is
generic (
entryBitWidth : integer := 12);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
NewEntryxDI : in std_logic_vector(entryBitWidth-1 downto 0); -- new entry
-- to be stored in the table
EnWrxSI : in std_logic; -- initiate a write access to hash table
-- the three bytes that serve as a key
Key0xDI : in std_logic_vector(7 downto 0);
Key1xDI : in std_logic_vector(7 downto 0);
Key2xDI : in std_logic_vector(7 downto 0);
-- the old entry which was stored under the given keys hash
OldEntryxDO : out std_logic_vector(entryBitWidth-1 downto 0));
end HashTable;
architecture Behavioral of HashTable is
constant HASH_BIT_LEN : integer := 11; -- number of address bits of the hash table
constant SEED : integer := 40543; -- seed value for hash algorithm as specified by Ross Williamson
constant ZERO : std_logic_vector(17 downto 0) := (others => '0');
signal Stage0xS : std_logic_vector(11 downto 0);
signal Stage1xS : std_logic_vector(15 downto 0);
signal ProductxS : integer;
signal RawHashxS : std_logic_vector(31 downto 0); -- This is the full output which is then truncated
signal BRamAddrxD : std_logic_vector(13 downto 0);
signal TblInxD, TblOutxD : std_logic_vector(17 downto 0); -- data input and out of table memory
signal BRamWexS : std_logic_vector(3 downto 0);
signal BRamLDInxD, BRamHDInxD : std_logic_vector(31 downto 0);
signal BRamLPInxD, BRamHPInxD : std_logic_vector(3 downto 0);
signal BRamLDOutxD, BRamHDOutxD : std_logic_vector(31 downto 0);
signal BRamLPOutxD, BRamHPOutxD : std_logic_vector(3 downto 0);
begin
-- first stage is: ((k0<<4)^k1)
Stage0xS <= Key0xDI(7 downto 4) & (Key0xDI(3 downto 0) xor Key1xDI(7 downto 4)) & Key1xDI(3 downto 0);
-- second stage: (stage0<<4) ^ k2
Stage1xS <= Stage0xS(11 downto 4) & (Stage0xS(3 downto 0) xor Key2xDI(7 downto 4)) & Key2xDI(3 downto 0);
ProductxS <= SEED * to_integer(unsigned(Stage1xS));
RawHashxS <= std_logic_vector(to_unsigned(ProductxS, 32));
-- note: The hash algorithm used by Ross Williamson does not use the last 4
-- bits, I don't know why. However we keep this
--HashxD <= RawHashxS(HASH_BIT_LEN+4-1 downto 4);
BRamAddrxD <= RawHashxS(HASH_BIT_LEN+4-1 downto 4) & ZERO(13-HASH_BIT_LEN downto 0);
-- reformat signals to adapt buswidth for memory blocks
BRamWexS <= EnWrxSI & EnWrxSI & EnWrxSI & EnWrxSI;
TblInxD <= ZERO(17 downto entryBitWidth) & NewEntryxDI;
BRamLDInxD <= x"000000" & TblInxD(7 downto 0);
BRamHDInxD <= x"000000" & TblInxD(16 downto 9);
BRamLPInxD <= "000" & TblInxD(8);
BRamHPInxD <= "000" & TblInxD(17);
TblOutxD <= BRamHPOutxD(0) & BRamHDOutxD(7 downto 0) & BRamLPOutxD(0) & BRamLDOutxD(7 downto 0);
OldEntryxDO <= TblOutxD(entryBitWidth-1 downto 0);
-- lower byte of hash table. Only port A is used
hashTableMemLowInst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => BRamLDOutxD, -- 8-bit A port data output
DOPA => BRamLPOutxD, -- 1-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => open,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => BRamAddrxD, -- 11-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => '1', -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => '0', -- 1-bit A port register set/reset input
WEA => BRamWexS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => BRamLDInxD, -- 32-bit A port data input
DIPA => BRamLPInxD, -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => "00000000000000", -- 14-bit B port address input
CLKB => '0', -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => '0', -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
-- higher byte of hash table. Only port A is used
hashTableMemHighInst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => BRamHDOutxD, -- 8-bit A port data output
DOPA => BRamHPOutxD, -- 1-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => open,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => BRamAddrxD, -- 11-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => '1', -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => '0', -- 1-bit A port register set/reset input
WEA => BRamWexS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => BRamHDInxD, -- 32-bit A port data input
DIPA => BRamHPInxD, -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => "00000000000000", -- 14-bit B port address input
CLKB => '0', -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => '0', -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
end Behavioral;
|
gpl-2.0
|
244a4f997dcf00805d55c1f76d563125
| 0.533345 | 3.823568 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/RS232_TX.vhd
| 1 | 4,734 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:21:19 10/20/2016
-- Design Name:
-- Module Name: RS232_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RS232_TX is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Start : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
EOT : out STD_LOGIC;
TX : out STD_LOGIC);
end RS232_TX;
architecture Behavioral of RS232_TX is
component Pulse_Width
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
send : out STD_LOGIC);
end component;
component Data_Count
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end component;
type State is (Idle,
StartBit,
SendData,
StopBit);
signal PresentState, NextState : State;
signal send : STD_LOGIC;
signal count : STD_LOGIC_VECTOR(3 downto 0);
signal reset_data : STD_LOGIC;
signal reset_control : STD_LOGIC;
signal byte1 : STD_LOGIC_VECTOR(7 downto 0);
signal eleccion : STD_LOGIC;
begin
reset_control <= reset_data and Reset;
Pulse_Control: Pulse_Width
port map (
clk => Clk,
reset => Reset,
enable => '1',
send => send);
Data_Control: Data_Count
port map (
clk => Clk,
reset => reset_control,
enable => send,
count => count);
FFs : process(Clk, Reset)
begin
if Reset ='0' then
PresentState <= Idle;
eleccion <= '0';
byte1 <= (others => '0');
elsif Clk'event and Clk = '1' then
if PresentState = Idle then
byte1 <= data;
elsif PresentState = SendData and count = "1000" then
eleccion <= not eleccion;
end if;
PresentState <= NextState;
end if;
end process;
Siguiente : process(PresentState, Start, send, count, eleccion, data)
begin
case PresentState is
when Idle =>
if Start = '1' or eleccion = '1' then
NextState <= StartBit;
else
NextState <= Idle;
end if;
when StartBit =>
if send ='1' then
NextState <= SendData;
else
NextState <= StartBit;
end if;
when SendData =>
if count = "1000" then
NextState <= StopBit;
else
NextState <= SendData;
end if;
when StopBit =>
if send ='1' then
NextState <= Idle;
else
NextState <= StopBit;
end if;
when others =>
NextState <= Idle;
end case;
end process;
Salidas : process(PresentState, count, data, byte1, eleccion)
begin
case PresentState is
when Idle =>
EOT <= '1';
TX <= '1';
reset_data <= '0';
when StartBit =>
EOT <= '0';
TX <= '0';
reset_data <= '0';
when SendData =>
EOT <= '0';
reset_data <= '1';
if eleccion = '0' then
case count is
when "0000" => TX <= byte1(0);
when "0001" => TX <= byte1(1);
when "0010" => TX <= byte1(2);
when "0011" => TX <= byte1(3);
when "0100" => TX <= byte1(4);
when "0101" => TX <= byte1(5);
when "0110" => TX <= byte1(6);
when "0111" => TX <= byte1(7);
when others => TX <= '1';
end case;
elsif eleccion = '1' then
case count is
when "0000" => TX <= data(0);
when "0001" => TX <= data(1);
when "0010" => TX <= data(2);
when "0011" => TX <= data(3);
when "0100" => TX <= data(4);
when "0101" => TX <= data(5);
when "0110" => TX <= data(6);
when "0111" => TX <= data(7);
when others => TX <= '1';
end case;
end if;
when StopBit =>
reset_data <= '0';
EOT <= '0';
TX <= '1';
when others =>
reset_data <= '0';
EOT <= '1';
TX <= '1';
end case;
end process;
end Behavioral;
|
mit
|
1b832db182a3acba1957d1c52cce202a
| 0.519645 | 3.403307 | false | false | false | false |
xuefei1/ElectronicEngineControl
|
vhd/pwm_decoder.vhd
| 3 | 1,506 |
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic := '0';
duty_count_out : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
reset : in std_logic := '0' -- reset
);
end entity pwm_decoder;
architecture decode of pwm_decoder is
begin
inc: process(clock, reset)
variable period : std_logic_vector(31 downto 0) := "00000000000000011000111010011000";
variable duty_count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
if(reset = '1') then
duty_count := "00000000000000000000000000000000";
count := "00000000000000000000000000000000";
elsif(rising_edge(clock)) then
if(unsigned(count) = unsigned(period) - 1) then
duty_count_out <= duty_count;
count := "00000000000000000000000000000000";
duty_count := "00000000000000000000000000000000";
else
if(pwm_in = '1') then
duty_count := std_logic_vector(unsigned(duty_count) + 1);
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
end architecture decode; -- of pwm_decoder
|
apache-2.0
|
17dd9ebdb43c9af5a5f143ded3f0f33e
| 0.634794 | 3.518692 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_crc.vhd
| 1 | 13,720 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_crc
---- Version: 1.0.0
---- Description:
---- CRC computation core
---- Input: 1 clk / nxt_dat_i <= '1' / dat_i <= "CRCCOMPUTEDDATA" / [pad_dat_val_i <= '1' / pad_dat_i <= "PADDINGDATA"]
---- Timing requirements: (CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8+1 clock cycles for valid output CRC
---- Output: dat_val_o <= "1" / dat_o <= "CRCCOMPUTEDDATA" / crc_o <= "CRCCOMPUTED"
---- Ressources requirements: data computed registers + crc registers + padding data registers + busy state registers + data_valid state registers + crc data pointer registers = (CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH*2)*8 + 2 + |log(CCSDS_RXTX_CRC_DATA_LENGTH-1)/log(2)| + 1 registers
--TODO: ressources with inversions
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/10/18: initial release
---- 2016/10/25: external padding data mode
---- 2016/10/30: ressources usage optimization
-------------------------------
--TODO: Implement DIRECT computation?
--TODO: CRC LENGTH not being multiple of Byte
-- CRC reference and explanations:
-- http://www.ross.net/crc/download/crc_v3.txt
-- Online data converters:
-- http://www.asciitohex.com/
-- Online CRC computers:
-- http://www.sunshine2k.de/coding/javascript/crc/crc_js.html
-- http://www.zorc.breitbandkatze.de/crc.html
-- NB: use nondirect configuration
-- COMMON STANDARDS CONFIGURATIONS:
-- http://reveng.sourceforge.net/crc-catalogue/
-- WARNING: some check values found there are linked to direct computation / cf: http://srecord.sourceforge.net/crc16-ccitt.html
--------------------
-- Check value: x"313233343536373839" <=> 123456789/ASCII
--------------------
-- CRC-8/DVB-S2
-- Width = 8 bits
-- Truncated polynomial = 0xd5
-- Initial value = 0x00
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x00
-- Check = 0xbc
--------------------
-- CRC-8/ITU/ATM
-- Width = 8 bits
-- Truncated polynomial = 0x07
-- Initial value = 0x00
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x55
-- Check = 0xa1
--------------------
-- CRC-8/LTE
-- Width = 8 bits
-- Truncated polynomial = 0x9b
-- Initial value = 0x00
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x00
-- Check = 0xea
--------------------
-- CRC-16/CCSDS/CCITT-FALSE
-- Width = 16 bits
-- Truncated polynomial = 0x1021
-- Initial value = 0xffff
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x0000
-- Check = 0xe5cc
--------------------
-- CRC-16/LTE
-- Width = 16 bits
-- Truncated polynomial = 0x1021
-- Initial value = 0x0000
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x0000
-- Check = 0x31c3
--------------------
-- CRC-16/CCITT-TRUE/KERMIT
-- Width = 16 bits
-- Truncated polynomial = 0x1021
-- Initial value = 0x0000
-- Input data reflected: true
-- Output CRC reflected: true
-- XOR final = 0x0000
-- Check = 0x2189
--------------------
-- CRC-16/UMTS
-- Width = 16 bits
-- Truncated polynomial = 0x8005
-- Initial value = 0x0000
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x0000
-- Check = 0xfee8
--------------------
-- CRC-16/X-25
-- Width = 16 bits
-- Truncated polynomial = 0x1021
-- Initial value = 0xffff
-- Input data reflected: true
-- Output CRC reflected: true
-- XOR final = 0xffff
-- Check = 0x2e5d
--------------------
-- CRC-32/ADCCP
-- Width = 32 bits
-- Truncated polynomial = 0x04c11db7
-- Initial value = 0xffffffff
-- Input data reflected: true
-- Output CRC reflected: true
-- XOR final = 0xffffffff
-- Check = 0x22896b0a
----------------
-- CRC-32/BZIP2
-- Width = 32 bits
-- Truncated polynomial = 0x04c11db7
-- Initial value = 0xffffffff
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0xffffffff
-- Check = 0xfc891918
----------------
-- CRC-32/MPEG-2
-- Width = 32 bits
-- Truncated polynomial = 0x04c11db7
-- Initial value = 0xffffffff
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0x00000000
-- Check = 0x373C5870
----------------
-- CRC-32/POSIX
-- Width = 32 bits
-- Truncated polynomial = 0x04c11db7
-- Initial value = 0x00000000
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0xffffffff
-- Check = 0x765e7680
----------------
-- CRC-64/WE
-- Width = 64 bits
-- Truncated polynomial = 0x42f0e1eba9ea3693
-- Initial value = 0xffffffffffffffff
-- Input data reflected: false
-- Output CRC reflected: false
-- XOR final = 0xffffffffffffffff
-- Check = 0xd2c7a4d6f38185a4
----------------
-- CRC-64/XZ
-- Width = 64 bits
-- Truncated polynomial = 0x42f0e1eba9ea3693
-- Initial value = 0xffffffffffffffff
-- Input data reflected: true
-- Output CRC reflected: true
-- XOR final = 0xffffffffffffffff
-- Check = 0xecf36dfb73a6edf7
----------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ccsds_rxtx_functions.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary rxtx crc inputs and outputs
--=============================================================================
entity ccsds_rxtx_crc is
generic(
constant CCSDS_RXTX_CRC_DATA_LENGTH: integer := 2; -- Data length - in Bytes
constant CCSDS_RXTX_CRC_FINAL_XOR: std_logic_vector := x"0000"; -- Final XOR mask (0x0000 <=> No XOR)
constant CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED: boolean := false; -- Reflect input byte by byte (used by standards)
constant CCSDS_RXTX_CRC_INPUT_REFLECTED: boolean := false; -- Reflect input on overall data (not currently used by standards) / WARNING - take over input bytes reflected parameter if activated
constant CCSDS_RXTX_CRC_LENGTH: integer := 2; -- CRC value depth - in Bytes
constant CCSDS_RXTX_CRC_OUTPUT_REFLECTED: boolean := false; -- Reflect output
constant CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector := x"1021"; -- Truncated polynomial / MSB <=> lower polynome (needs to be '1')
constant CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED: boolean := false; -- Reflect polynomial
constant CCSDS_RXTX_CRC_SEED: std_logic_vector := x"FFFF" -- Initial value from register
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
nxt_i: in std_logic;
pad_dat_i: in std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
pad_dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
bus_o: out std_logic;
crc_o: out std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_rxtx_crc;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_rxtx_crc is
-- internal variable signals
signal crc_busy: std_logic := '0';
signal crc_data: std_logic_vector((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1 downto 0) := (others => '0');
signal crc_memory: std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0) := CCSDS_RXTX_CRC_SEED;
-- components instanciation and mapping
begin
bus_o <= crc_busy;
crc_o <= crc_memory;
dat_o <= crc_data((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1 downto CCSDS_RXTX_CRC_LENGTH*8);
-- presynthesis checks
CHKCRCP0 : if CCSDS_RXTX_CRC_SEED'length /= CCSDS_RXTX_CRC_LENGTH*8 generate
process
begin
report "ERROR: CRC SEED VALUE LENGTH MUST BE EQUAL TO CRC LENGTH" severity failure;
wait;
end process;
end generate CHKCRCP0;
CHKCRCP1 : if CCSDS_RXTX_CRC_POLYNOMIAL'length /= CCSDS_RXTX_CRC_LENGTH*8 generate
process
begin
report "ERROR: CRC POLYNOMIAL LENGTH MUST BE EQUAL TO CRC LENGTH (SHORTENED VERSION / DON'T PUT MANDATORY HIGHER POLYNOME '1')" severity failure;
wait;
end process;
end generate CHKCRCP1;
CHKCRCP2 : if CCSDS_RXTX_CRC_POLYNOMIAL(CCSDS_RXTX_CRC_LENGTH*8-1) = '0' generate
process
begin
report "ERROR: CRC POLYNOMIAL MSB MUST BE EQUAL TO '1': " & std_logic'image(CCSDS_RXTX_CRC_POLYNOMIAL(CCSDS_RXTX_CRC_LENGTH*8-1)) severity failure;
wait;
end process;
end generate CHKCRCP2;
CHKCRCP3 : if CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED = true and CCSDS_RXTX_CRC_INPUT_REFLECTED = true generate
process
begin
report "ERROR: CRC INPUT DATA REFLECTION CANNOT BE DONE SIMULTANEOUSLY ON OVERALL DATA AND BYTE BY BYTE" severity failure;
wait;
end process;
end generate CHKCRCP3;
-- internal processing
--=============================================================================
-- Begin of crcp
-- Compute CRC based on input data
--=============================================================================
-- read: rst_i, nxt_i, pad_dat_i, pad_dat_val_i
-- write: dat_val_o, crc_busy, crc_memory
-- r/w: crc_data
CRCP: process (clk_i)
variable crc_data_pointer: integer range -2 to ((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1) := -2;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
crc_busy <= '0';
dat_val_o <= '0';
-- crc_memory <= CCSDS_RXTX_CRC_SEED;
-- crc_data <= (others => '0');
crc_data_pointer := -2;
else
case crc_data_pointer is
-- no current crc under computation
when -2 =>
dat_val_o <= '0';
-- CRC computation required and
if (nxt_i = '1') then
crc_busy <= '1';
crc_memory <= CCSDS_RXTX_CRC_SEED;
crc_data_pointer := (CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1;
if (CCSDS_RXTX_CRC_INPUT_REFLECTED) then
crc_data((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1 downto CCSDS_RXTX_CRC_LENGTH*8) <= reverse_std_logic_vector(dat_i);
elsif (CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED) then
for data_pointer in CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH-1 downto CCSDS_RXTX_CRC_LENGTH loop
crc_data((data_pointer+1)*8-1 downto data_pointer*8) <= reverse_std_logic_vector(dat_i(((data_pointer+1-CCSDS_RXTX_CRC_LENGTH)*8-1) downto (data_pointer-CCSDS_RXTX_CRC_LENGTH)*8));
end loop;
else
crc_data((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1 downto CCSDS_RXTX_CRC_LENGTH*8) <= dat_i;
end if;
if (pad_dat_val_i = '1') then
if (CCSDS_RXTX_CRC_OUTPUT_REFLECTED) then
crc_data(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0) <= reverse_std_logic_vector(pad_dat_i);
else
crc_data(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0) <= pad_dat_i;
end if;
else
crc_data(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0) <= (others => '0');
end if;
else
-- nothing to be done
crc_busy <= '0';
end if;
-- CRC is computed
when -1 =>
crc_busy <= '0';
dat_val_o <= '1';
crc_data_pointer := -2;
if (CCSDS_RXTX_CRC_OUTPUT_REFLECTED) then
crc_memory <= reverse_std_logic_vector(crc_memory xor CCSDS_RXTX_CRC_FINAL_XOR);
else
crc_memory <= (crc_memory xor CCSDS_RXTX_CRC_FINAL_XOR);
end if;
if (CCSDS_RXTX_CRC_INPUT_REFLECTED) then
crc_data((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1 downto CCSDS_RXTX_CRC_LENGTH*8) <= reverse_std_logic_vector(crc_data((CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH)*8-1 downto CCSDS_RXTX_CRC_LENGTH*8));
elsif (CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED) then
for data_pointer in CCSDS_RXTX_CRC_DATA_LENGTH+CCSDS_RXTX_CRC_LENGTH-1 downto CCSDS_RXTX_CRC_LENGTH loop
crc_data(((data_pointer+1)*8-1) downto data_pointer*8) <= reverse_std_logic_vector(crc_data(((data_pointer+1)*8-1) downto data_pointer*8));
end loop;
end if;
-- Computing CRC
when others =>
crc_busy <= '1';
dat_val_o <= '0';
-- MSB = 1 / register shifted output bit will be '1'
if (crc_memory(CCSDS_RXTX_CRC_LENGTH*8-1) = '1') then
if (CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED) then
crc_memory <= (std_logic_vector(resize(unsigned(crc_memory),CCSDS_RXTX_CRC_LENGTH*8-1)) & crc_data(crc_data_pointer)) xor reverse_std_logic_vector(CCSDS_RXTX_CRC_POLYNOMIAL);
else
crc_memory <= (std_logic_vector(resize(unsigned(crc_memory),CCSDS_RXTX_CRC_LENGTH*8-1)) & crc_data(crc_data_pointer)) xor CCSDS_RXTX_CRC_POLYNOMIAL;
end if;
else
crc_memory <= (std_logic_vector(resize(unsigned(crc_memory),CCSDS_RXTX_CRC_LENGTH*8-1)) & crc_data(crc_data_pointer));
end if;
crc_data_pointer := crc_data_pointer - 1;
end case;
end if;
end if;
end process;
end rtl;
|
mit
|
a0c98b9bdd233ad0649bfe5820ebcf64
| 0.596793 | 3.625793 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/CPU.vhd
| 1 | 7,507 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PIC_pkg.ALL;
entity CPU is
port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
ROM_Data : in STD_LOGIC_VECTOR (11 downto 0);
ROM_Addr : out STD_LOGIC_VECTOR (11 downto 0);
RAM_Addr : out STD_LOGIC_VECTOR (7 downto 0);
RAM_Write : out STD_LOGIC;
RAM_OE : out STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
DMA_RQ : in STD_LOGIC;
DMA_ACK : out STD_LOGIC;
SEND_comm : out STD_LOGIC;
DMA_READY : in STD_LOGIC;
Alu_op : out alu_op;
Index_Reg : in STD_LOGIC_VECTOR (7 downto 0);
FlagZ : in STD_LOGIC);
-- FlagC : in STD_LOGIC;
-- FlagN : in STD_LOGIC;
-- FlagE : in STD_LOGIC);
end CPU;
architecture Behavioral of CPU is
type State is (Idle, Fetch, Op_Fetch, Decode, Execute, Receive, Transmit);
signal current_state, next_state: State;
signal PC_reg, INS_reg, TMP_reg: std_logic_vector(7 downto 0);
signal PC_reg_tmp, INS_reg_tmp, TMP_reg_tmp: std_logic_vector(7 downto 0);
begin
ROM_Addr <= "0000" & PC_reg;
process(current_state, FlagZ, Index_Reg, DMA_RQ, DMA_READY, ROM_Data, PC_reg, INS_reg, TMP_reg)
begin
-- Valores por defecto
Databus <= "ZZZZZZZZ";
RAM_Addr <= "ZZZZZZZZ";
RAM_Write <= 'Z';
RAM_OE <= 'Z';
DMA_Ack <= '0';
Send_comm <= '0';
ALU_op <= nop;
next_state <= current_state;
INS_reg_tmp <= INS_reg;
PC_reg_tmp <= PC_reg;
TMP_reg_tmp <= TMP_reg;
case current_state is
when Idle =>
if DMA_RQ='1' then
next_state <= Receive;
else
next_state <= Fetch;
end if;
when Receive =>
DMA_ACK<='1';
if DMA_RQ='0' then
next_state <= Fetch;
end if;
when Fetch =>
INS_reg_tmp <= ROM_Data(7 downto 0);
PC_reg_tmp <= PC_reg+1;
next_state <= Decode;
when Decode =>
case INS_reg(7 downto 6) is
when TYPE_1 =>
next_state <= Execute;
when TYPE_2 =>
next_state <= Op_Fetch;
when TYPE_3 =>
if INS_reg(5 downto 3)=(LD & SRC_ACC) then
next_state <= Execute;
else
next_state <= Op_Fetch;
end if;
when TYPE_4 =>
next_state <= Transmit;
when others =>
end case;
when Op_Fetch =>
TMP_reg_tmp <= ROM_Data(7 downto 0);
PC_reg_tmp <= PC_reg+1;
next_state <= Execute;
when Execute =>
case INS_reg(7 downto 6) is
when TYPE_1 =>
case INS_reg(5 downto 0) is
when ALU_ADD =>
Alu_op <= op_add;
when ALU_SUB =>
Alu_op <= op_sub;
when ALU_SHIFTL =>
Alu_op <= op_shiftl;
when ALU_SHIFTR =>
Alu_op <= op_shiftr;
when ALU_AND =>
Alu_op <= op_and;
when ALU_OR =>
Alu_op <= op_or;
when ALU_XOR =>
Alu_op <= op_xor;
when ALU_CMPE =>
Alu_op <= op_cmpe;
when ALU_CMPL =>
Alu_op <= op_cmpl;
when ALU_CMPG =>
Alu_op <= op_cmpg;
when ALU_ASCII2BIN =>
Alu_op <= op_ascii2bin;
when ALU_BIN2ASCII =>
Alu_op <= op_bin2ascii;
when others =>
end case;
next_state <= Idle;
when TYPE_2 =>
case INS_reg(5 downto 0) is
when JMP_UNCOND =>
PC_reg_tmp <= TMP_reg;
when JMP_COND =>
if FlagZ='1' then
PC_reg_tmp <= TMP_reg;
end if;
when others =>
end case;
next_state <= Idle;
when TYPE_3 =>
if INS_reg(5)='0' then -- Registros o lectura de memoria
case INS_reg(4 downto 0) is
-- Transferencias entre registros
when SRC_ACC & DST_A =>
Alu_op <= op_mvacc2a;
next_state <= Idle;
when SRC_ACC & DST_B =>
Alu_op <= op_mvacc2b;
next_state <= Idle;
when SRC_ACC & DST_INDX =>
Alu_op <= op_mvacc2id;
next_state <= Idle;
-- Carga de registros con constantes
when SRC_CONSTANT & DST_A =>
Alu_op <= op_lda;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_CONSTANT & DST_B =>
Alu_op <= op_ldb;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_CONSTANT & DST_INDX =>
Alu_op <= op_ldid;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_CONSTANT & DST_ACC =>
Alu_op <= op_ldacc;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
-- Carga de registros desde memoria
when SRC_MEM & DST_A =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_lda;
next_state <= Idle;
when SRC_MEM & DST_B =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_ldb;
next_state <= Idle;
when SRC_MEM & DST_ACC =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_ldacc;
next_state <= Idle;
when SRC_MEM & DST_INDX =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_ldid;
next_state <= Idle;
-- Carga de registros desde memoria indexada
when SRC_INDXD_MEM & DST_A =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_lda;
next_state <= Idle;
when SRC_INDXD_MEM & DST_B =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_ldb;
next_state <= Idle;
when SRC_INDXD_MEM & DST_ACC =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_ldacc;
next_state <= Idle;
when SRC_INDXD_MEM & DST_INDX =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_ldid;
next_state <= Idle;
when others =>
end case;
else -- Escritura en memoria
Alu_op <= op_oeacc;
case INS_reg(4 downto 0) is
when SRC_ACC & DST_MEM =>
RAM_Write <= '1';
RAM_OE <= '1';
RAM_Addr <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_ACC & DST_INDXD_MEM =>
RAM_Write <= '1';
RAM_OE <= '1';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
next_state <= Idle;
when others =>
end case;
end if;
when TYPE_4 =>
when others =>
end case;
when Transmit =>
SEND_comm <= '1';
if DMA_READY='1' then
next_state <= Idle;
end if;
end case;
end process;
PROCESS (reset, clk)
BEGIN
if reset='0' then
current_state <= Idle;
PC_reg <= (others=>'0');
elsif clk'event and clk='1' then
current_state <= next_state;
PC_reg <= PC_reg_tmp;
INS_reg <= INS_reg_tmp;
TMP_reg <= TMP_reg_tmp;
end if;
END PROCESS;
end Behavioral;
|
mit
|
33c898595f84b818b5a2a8e212540d8f
| 0.484481 | 3.131831 | false | false | false | false |
xuefei1/ElectronicEngineControl
|
vhd/pwm_generator.vhd
| 3 | 2,521 |
-- pwm_generator.vhd
-- Author: Fred
-- Status: Tested and passed
-- This module was based on the pwm module included here:
-- http://www.alteraforum.com/forum/showthread.php?t=45531
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_generator is
port (
clock : in std_logic := '0'; -- clock
write_en_period : in std_logic := '0'; -- write_enable_period
write_en_duty : in std_logic := '0'; -- write_enable_duty
write_en_control : in std_logic := '0'; -- write_enable_control
period_in : in std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; -- period in clock ticks
duty_in : in std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; -- duty must be less than or equal to period
control_in : in std_logic_vector(7 downto 0) := "00000000"; -- control input(bit 0: output enable)
pwm_out : out std_logic := '0'; -- output pwm signal
reset : in std_logic := '0' -- reset
);
end entity pwm_generator;
architecture pwm of pwm_generator is
begin
inc: process(clock, reset)
variable period : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable duty_count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable control : std_logic_vector(7 downto 0) := "00000000";
begin
if(reset = '1') then
period := "00000000000000000000000000000000";
duty_count := "00000000000000000000000000000000";
control := "00000000";
elsif(rising_edge(clock)) then
if(write_en_period = '1') then
period := period_in;
end if;
if(write_en_duty = '1') then
duty_count := duty_in;
if(duty_count > period) then
duty_count := period;
end if;
end if;
if(write_en_control = '1') then
control := control_in;
end if;
if(unsigned(count) = unsigned(period) - 1) then
count := "00000000000000000000000000000000";
else
count := std_logic_vector(unsigned(count) + 1);
end if;
if(unsigned(count) < unsigned(duty_count)) then
pwm_out <= '1';
else
pwm_out <= '0';
end if;
end if;
end process;
end architecture pwm; -- of pwm_generator
|
apache-2.0
|
bc70a689469d0d41f9c6864392db1f6f
| 0.595399 | 3.383893 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_mapper_symbols_samples.vhd
| 1 | 4,348 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_mapper_symbols_samples
---- Version: 1.0.0
---- Description:
---- Map symbols to their sample value depending on quantization depth
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx bits to symbols mapper inputs and outputs
--=============================================================================
entity ccsds_tx_mapper_symbols_samples is
generic(
constant CCSDS_TX_MAPPER_TARGET_SNR: real; -- in dB
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer; -- in bits
constant CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
-- outputs
sam_val_o: out std_logic;
sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
);
end ccsds_tx_mapper_symbols_samples;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_mapper_symbols_samples is
-- internal constants
constant QUANTIZATION_SNR: real := 6.02*real(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH);
constant REQUIRED_SNR: real := real(2 + 2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL) + CCSDS_TX_MAPPER_TARGET_SNR;
constant SYMBOL_STEP: real := 2.0**(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH) / real(CCSDS_TX_MAPPER_BITS_PER_SYMBOL+1);
-- internal variable signals
type samples_array is array(2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL)-1 downto 0) of std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0);
signal symbols_values: samples_array;
-- components instanciation and mapping
begin
SYMBOLS_VALUES_GENERATOR: for symbol_counter in 0 to 2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1)-1 generate
symbols_values(2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1)+symbol_counter) <= std_logic_vector(to_signed(integer(2.0**(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1) - 1.0 - real(symbol_counter) * SYMBOL_STEP),CCSDS_TX_MAPPER_QUANTIZATION_DEPTH));
symbols_values(2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1)-symbol_counter-1) <= std_logic_vector(to_signed(integer(-(2.0**(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1)) + 1.0 + real(symbol_counter) * SYMBOL_STEP),CCSDS_TX_MAPPER_QUANTIZATION_DEPTH));
end generate SYMBOLS_VALUES_GENERATOR;
-- presynthesis checks
-- Check SNR level requested is respected
-- Signal SNR > crest factor modulated signal + SNR requested from configuration
-- QAMCrestFactor, dB # 2 + 2 * NumberOfBitsPerSymbol
-- QuantizedSignal SNR, dB # 6.02 * QuantizationDepth
CHKMAPPERP0 : if (QUANTIZATION_SNR < REQUIRED_SNR) generate
process
begin
report "ERROR: INCREASE QUANTIZATION DEPTH - QUANTIZATION SNR = " & real'image(QUANTIZATION_SNR) & " dB - REQUIRED SNR = " & real'image(REQUIRED_SNR) severity failure;
wait;
end process;
end generate CHKMAPPERP0;
-- internal processing
--=============================================================================
-- Begin of mapperp
-- Map symbols to samples
--=============================================================================
-- read: rst_i, sym_i, sym_val_i
-- write: sam_val_o, sam_o
-- r/w:
MAPPERP: process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sam_o <= (others => '0');
sam_val_o <= '0';
else
if (sym_val_i = '1') then
sam_o <= symbols_values(to_integer(unsigned(sym_i)));
sam_val_o <= '1';
else
sam_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
mit
|
99b25d485402624d1508afea007488a3
| 0.574057 | 4.003683 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/simulation/fifo_dverif.vhd
| 1 | 5,957 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
0a203f5ed263baa82db7aa61fe69f36c
| 0.55162 | 3.947647 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/simulation/fifo_pctrl.vhd
| 1 | 15,812 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
mit
|
1ffe84bc63d1375ace5831aa041cb297
| 0.504048 | 3.427704 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/outputFIFO.vhd
| 1 | 18,289 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/7/22 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Descrambles encoded data output into proper data stream and buffers data in an FIFO.
--* Note: This unit can accept simulatinous input of body and header data.
--* However there must not be too much data input. The minimum is 16 cycles between
--* two assertions of HeaderStrobexSI. This is due to internal bandwidth
--* limitations. The only exception to this rule is the very last frame. However
--* no additional data is permitted after it until the reset signal was applied
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity outputFIFO is
generic (
frameSize : integer := 8); -- must be a multiple of 8
port (
ClkxCI : in std_logic;
RstxRI : in std_logic; -- active high
BodyDataxDI : in std_logic_vector(7 downto 0);
BodyStrobexSI : in std_logic; -- strobe signal for data
HeaderDataxDI : in std_logic_vector(frameSize-1 downto 0);
HeaderStrobexSI : in std_logic;
BuffersEmptyxSO : out std_logic; -- indicates that the internal data buffers are empty
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic; -- read next word
LengthxDO : out integer range 0 to 1024); -- number of bytes in the FIFO
end outputFIFO;
architecture Behavorial of outputFIFO is
constant ADR_BIT_LEN : integer := 10; -- fifo memory address bus width in bits (for byte addressing)
constant DEPTH : integer := 2**ADR_BIT_LEN; -- Has to match value for range in LengthxDO and the BRam!
constant TRANS_BUF_LEN : integer := (frameSize*2)+(frameSize/8); -- we need frameSize/8 bytes for the
-- header, plus frameSize*2 for the body
type inBufType is array (0 to (frameSize*2)-1) of std_logic_vector(7 downto 0); -- *2 because we can have two bytes per entry
signal InputBufxDN, InputBufxDP : inBufType := (others => (others => '0'));
type transBufType is array (0 to TRANS_BUF_LEN-1) of std_logic_vector(7 downto 0);
signal TransBufxDN, TransBufxDP : transBufType := (others => (others => '0'));
signal InBufCntxDN, InBufCntxDP : integer range 0 to (frameSize*2)+1 := 0; -- number of _bytes_ in buffer
signal TransBufLenxDN, TransBufLenxDP : integer range 0 to (frameSize*2)+1 := 0;
signal TransBufBusyxS : std_logic;
signal CopyReqxSN, CopyReqxSP : std_logic := '0';
signal HeaderInBufxDN, HeaderInBufxDP : std_logic_vector(7 downto 0) := x"00";
signal BuffersEmptyxSN, BuffersEmptyxSP : std_logic := '0';
signal BRamWexS : std_logic_vector(3 downto 0);
signal BRamWrInxD : std_logic_vector(31 downto 0);
signal BRamWrAdrxD : std_logic_vector(13 downto 0);
signal BRamRdAdrxD : std_logic_vector(13 downto 0);
signal BRamDOutxD : std_logic_vector(31 downto 0);
signal DoReadxS, DoWritexS : std_logic;
signal ReadLenxS, WriteLenxS : integer range 0 to 3; -- 0 -> 1 byte, 1 -> 2 bytes, ...
signal LengthxDN, LengthxDP : integer range 0 to DEPTH := 0; -- count the number of bytes in the FIFO
signal ReadPtrxDN, ReadPtrxDP : integer range 0 to DEPTH := 0;
signal WrPtrxDN, WrPtrxDP : integer range 0 to DEPTH := 0;
signal FifoInxD : std_logic_vector(15 downto 0); -- data input to fifo
signal FifoInSelxD : std_logic_vector(1 downto 0); -- byte select for fifo data input
signal OutputValidxSN, OutputValidxSP : std_logic := '0';
type transferFSMType is (ST_IDLE, ST_FIRST_SINGLE_BYTE, ST_COPY, ST_LAST_SINGLE_BYTE);
signal StatexSN, StatexSP : transferFSMType := ST_IDLE;
begin -- Behavorial
-- implement data input buffer
inBufPrcs : process (BodyDataxDI, BodyStrobexSI, CopyReqxSP, HeaderDataxDI,
HeaderInBufxDP, HeaderStrobexSI, InBufCntxDP,
InputBufxDP, StatexSP, TransBufBusyxS)
begin
InBufCntxDN <= InBufCntxDP;
InputBufxDN <= InputBufxDP;
CopyReqxSN <= CopyReqxSP and TransBufBusyxS;
HeaderInBufxDN <= HeaderInBufxDP;
if BodyStrobexSI = '1' then
if InBufCntxDP < (frameSize*2) then
InBufCntxDN <= InBufCntxDP + 1;
InputBufxDN(InBufCntxDP) <= BodyDataxDI;
else
assert false report "Buffer overflow in data input buffer of output FIFO" severity error;
end if;
end if;
if HeaderStrobexSI = '1' then
if TransBufBusyxS = '0' then
InBufCntxDN <= 0; -- reset for next frame
else
CopyReqxSN <= '1'; -- can't copy right now, remember to do that
HeaderInBufxDN <= HeaderDataxDI;
end if;
end if;
if StatexSP = ST_IDLE and CopyReqxSP = '1' then
-- the requested copy operation starts now, reset counter
InBufCntxDN <= 0;
end if;
end process inBufPrcs;
-- purpose: implement transfer buffer (shift reg) and the state machine which copies the
-- data into the fifo.
transBufPrcs : process (BodyStrobexSI, CopyReqxSP, HeaderDataxDI,
HeaderInBufxDP, HeaderStrobexSI, InBufCntxDP,
InputBufxDP, LengthxDP, StatexSP, TransBufLenxDP,
TransBufxDP, WrPtrxDP)
begin
TransBufxDN <= TransBufxDP;
TransBufLenxDN <= TransBufLenxDP;
StatexSN <= StatexSP; -- default: keep current state
DoWritexS <= '0'; -- default: do nothing
FifoInxD <= (others => '-');
FifoInSelxD <= "00";
WriteLenxS <= 0;
TransBufBusyxS <= '0';
case StatexSP is
when ST_IDLE =>
if (HeaderStrobexSI = '1' or CopyReqxSP = '1') and InBufCntxDP > 1 then
-- we must have at least one data byte in the frame
-- assert InBufCntxDN > 0 report "Transfer FSM: Atempted illegal transfer of frame without data" severity warning;
-- copy data from the input buffer into transfer buffer
for i in 1 to TRANS_BUF_LEN-1 loop
TransBufxDN(i) <= InputBufxDP(i-1);
end loop; -- i
if HeaderStrobexSI = '1' then
-- the header is coming in right now -> copy from input signal
TransBufxDN(0) <= HeaderDataxDI;
else
-- this must be an transfer requested earlier -> copy header from buffer
TransBufxDN(0) <= HeaderInBufxDP;
end if;
if BodyStrobexSI = '0' then
TransBufLenxDN <= InBufCntxDP + (frameSize/8); -- frameSize / 8 is the header length
else
TransBufLenxDN <= InBufCntxDP + (frameSize/8) + 1; -- frameSize / 8 is the header length
end if;
-- Note: we know we have at least two bytes (header + data) therefore
-- it is save to move to ST_COPY
if WrPtrxDP mod 2 = 1 then
-- we have an odd byte location -> transfer single byte first
StatexSN <= ST_FIRST_SINGLE_BYTE;
else
StatexSN <= ST_COPY;
end if;
end if;
when ST_FIRST_SINGLE_BYTE =>
TransBufBusyxS <= '1';
if LengthxDP < DEPTH-1 then -- make sure we have enough space for 2 bytes in fifo
-- copy one byte from the transfer buffer to the fifo
FifoInxD <= TransBufxDP(0) & x"00";
FifoInSelxD <= "10";
DoWritexS <= '1';
WriteLenxS <= 1;
if TransBufLenxDP > 2 then
StatexSN <= ST_COPY; -- we have more than one byte left, do dual byte copy
else
StatexSN <= ST_LAST_SINGLE_BYTE; -- only one byte left in frame
end if;
-- shift the transfer buffer one byte
for i in 0 to TRANS_BUF_LEN-2 loop
TransBufxDN(i) <= TransBufxDP(i+1);
end loop; -- i
TransBufxDN(TRANS_BUF_LEN-1) <= x"00"; -- to make simulation look nice :)
TransBufLenxDN <= TransBufLenxDP - 1;
end if;
when ST_COPY =>
TransBufBusyxS <= '1';
if LengthxDP < DEPTH-1 then -- make sure we have enough space for 2 bytes in fifo
assert TransBufLenxDP >= 2 report "ST_COPY: not enough data in transfer buffer to perform copy operation" severity error;
FifoInxD <= TransBufxDP(1) & TransBufxDP(0);
FifoInSelxD <= "11";
DoWritexS <= '1';
WriteLenxS <= 2;
TransBufLenxDN <= TransBufLenxDP - 2; -- we copy two bytes here
for i in 0 to TRANS_BUF_LEN-3 loop
-- shift buffer two bytes
TransBufxDN(i) <= TransBufxDP(i+2);
end loop; -- i
if TransBufLenxDP = 2 then
StatexSN <= ST_IDLE; -- this were the last two bytes -> we are done
elsif TransBufLenxDP = 3 then
StatexSN <= ST_LAST_SINGLE_BYTE; -- handle last byte as special case
end if;
end if;
when ST_LAST_SINGLE_BYTE =>
TransBufBusyxS <= '1';
if LengthxDP < DEPTH-1 then -- make sure we have enough space for 2 bytes in fifo
assert TransBufLenxDP = 1 report "ST_LAST_SINGLE_BYTE: TransBufLenxDP is not 1" severity error;
FifoInxD <= x"00" & TransBufxDP(0); -- copy last byte
FifoInSelxD <= "01";
TransBufLenxDN <= 0;
DoWritexS <= '1';
WriteLenxS <= 1;
StatexSN <= ST_IDLE; -- transfer is done
end if;
when others => null;
end case;
end process transBufPrcs;
BuffersEmptyxSN <= '1' when InBufCntxDP = 0 and TransBufLenxDP = 0 else '0';
BuffersEmptyxSO <= BuffersEmptyxSP;
-- implement write pointer counter
wrPortDemuxPrcs : process (DoWritexS, FifoInSelxD, FifoInxD, WrPtrxDP,
WriteLenxS)
begin
WrPtrxDN <= WrPtrxDP;
BRamWrInxD <= x"0000" & FifoInxD;
BRamWrAdrxD <= "0" & std_logic_vector(to_unsigned(WrPtrxDP/2, ADR_BIT_LEN-1)) & "0000";
BRamWexS <= "00" & FifoInSelxD;
-- implement a write pointer that overflows when we reach the end of the fifo memory
if DoWritexS = '1' then
if (WrPtrxDP + WriteLenxS) < DEPTH then
WrPtrxDN <= WrPtrxDP + WriteLenxS;
else
WrPtrxDN <= WrPtrxDP + WriteLenxS - DEPTH;
end if;
end if;
end process wrPortDemuxPrcs;
-- purpose: implement read port related logic
readPrcs : process (LengthxDP, RdStrobexSI, ReadPtrxDP)
begin
ReadPtrxDN <= ReadPtrxDP;
DoReadxS <= '0';
ReadLenxS <= 0;
OutputValidxSN <= '0';
BRamRdAdrxD <= "0" & std_logic_vector(to_unsigned(ReadPtrxDP, ADR_BIT_LEN)) & "000";
-- suppress illeagal read attempts (when the fifo is empty)
if RdStrobexSI = '1' and LengthxDP > 0 then
DoReadxS <= '1';
ReadLenxS <= 1;
OutputValidxSN <= '1'; -- read takes one cycle
-- implement read pointer
if ReadPtrxDP < DEPTH-1 then
ReadPtrxDN <= ReadPtrxDP + 1;
else
ReadPtrxDN <= 0;
end if;
end if;
end process readPrcs;
-- purpose: Count the number of _bytes_ currently stored in the FIFO
lenCntPrcs : process (DoReadxS, DoWritexS, LengthxDP, ReadLenxS, WriteLenxS)
begin -- process LenCntPrcs
LengthxDN <= LengthxDP; -- default: do nothing
if DoReadxS = '1' and DoWritexS = '0' and LengthxDP > 0 then
LengthxDN <= LengthxDP - ReadLenxS;
-- byte -> different encoding for ReadLen, see signal definition
end if;
if DoReadxS = '0' and DoWritexS = '1' and LengthxDP < DEPTH then
LengthxDN <= LengthxDP + WriteLenxS;
end if;
if DoReadxS = '1' and DoWritexS = '1' then
LengthxDN <= LengthxDP + WriteLenxS - ReadLenxS;
end if;
end process LenCntPrcs;
BufOutxDO <= BRamDOutxD(7 downto 0);
LengthxDO <= LengthxDP;
OutputValidxSO <= OutputValidxSP;
--SelxSO <= ReadSelxS;
-- purpose: implement the registers
-- type : sequential
process (ClkxCI, RstxRI)
begin -- process
if ClkxCI'event and ClkxCI = '1' then -- rising clock edge then
if RstxRI = '1' then
InBufCntxDP <= 0;
LengthxDP <= 0;
TransBufLenxDP <= 0;
CopyReqxSP <= '0';
LengthxDP <= 0;
WrPtrxDP <= 0;
ReadPtrxDP <= 0;
OutputValidxSP <= '0';
BuffersEmptyxSP <= '0';
StatexSP <= ST_IDLE;
else
InputBufxDP <= InputBufxDN;
InBufCntxDP <= InBufCntxDN;
TransBufxDP <= TransBufxDN;
TransBufLenxDP <= TransBufLenxDN;
CopyReqxSP <= CopyReqxSN;
HeaderInBufxDP <= HeaderInBufxDN;
LengthxDP <= LengthxDN;
WrPtrxDP <= WrPtrxDN;
ReadPtrxDP <= ReadPtrxDN;
OutputValidxSP <= OutputValidxSN;
BuffersEmptyxSP <= BuffersEmptyxSN;
StatexSP <= StatexSN;
end if;
end if;
end process;
FifoBRam : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => open, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => BRamDOutxD, -- 32-bit B port data output
DOPB => open, -- 4-bit B port parity output
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => BRamWrAdrxD, -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => DoWritexS, -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => BRamWexS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => BRamWrInxD, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => BRamRdAdrxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => DoReadxS, -- 1-bit B port enable input
REGCEB => '1', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => "0000", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => "0000" -- 4-bit B port parity input
);
end Behavorial;
|
gpl-2.0
|
09f2e1f91ad347fe02e25922e5c934ad
| 0.566625 | 4.351416 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/HastTb.vhd
| 1 | 5,253 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/17 - LS
--* started file
--*
--* Version 1.0 - 2013/4/5 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Test bench for entity hashTable
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity HashTable_tb is
end HashTable_tb;
-------------------------------------------------------------------------------
architecture tb of HashTable_tb is
component HashTable
generic (
entryBitWidth : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
NewEntryxDI : in std_logic_vector(entryBitWidth-1 downto 0);
EnWrxSI : in std_logic;
Key0xDI : in std_logic_vector(7 downto 0);
Key1xDI : in std_logic_vector(7 downto 0);
Key2xDI : in std_logic_vector(7 downto 0);
OldEntryxDO : out std_logic_vector(entryBitWidth-1 downto 0));
end component;
-- component generics
constant entryBitWidth : integer := 12;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal NewEntryxDI : std_logic_vector(entryBitWidth-1 downto 0) := (others => '0');
signal EnWrxSI : std_logic := '0';
signal Key0xDI : std_logic_vector(7 downto 0) := (others => '0');
signal Key1xDI : std_logic_vector(7 downto 0) := (others => '0');
signal Key2xDI : std_logic_vector(7 downto 0) := (others => '0');
signal OldEntryxDO : std_logic_vector(entryBitWidth-1 downto 0);
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : HashTable
generic map (
entryBitWidth => entryBitWidth)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
NewEntryxDI => NewEntryxDI,
EnWrxSI => EnWrxSI,
Key0xDI => Key0xDI,
Key1xDI => Key1xDI,
Key2xDI => Key2xDI,
OldEntryxDO => OldEntryxDO);
-- clock generation
Clk <= not Clk after 10 ns;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"210";
EnWrxSI <= '1';
wait until Clk'event and Clk = '1';
Key0xDI <= x"00";
Key1xDI <= x"00";
Key2xDI <= x"00";
NewEntryxDI <= x"000";
EnWrxSI <= '1';
wait until Clk'event and Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"fff";
EnWrxSI <= '0';
wait until Clk'event and Clk = '1';
Key0xDI <= x"00";
Key1xDI <= x"00";
Key2xDI <= x"00";
NewEntryxDI <= x"111";
EnWrxSI <= '0';
wait until Clk'event and Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"fff";
EnWrxSI <= '1';
wait until Clk'event and Clk = '1';
Key0xDI <= x"10";
Key1xDI <= x"32";
Key2xDI <= x"54";
NewEntryxDI <= x"000";
EnWrxSI <= '0';
wait until Clk'event and Clk = '1';
wait;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration HashTable_tb_tb_cfg of HashTable_tb is
for tb
end for;
end HashTable_tb_tb_cfg;
-------------------------------------------------------------------------------
|
gpl-2.0
|
67c4acfaa00a46d75ea72b66dad43f21
| 0.47668 | 4.219277 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_coder_convolutional.vhd
| 1 | 7,383 |
---- Design Name: ccsds_tx_coder_convolutional
---- Version: 1.0.0
---- Description:
---- Convolutional coder
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2017/01/15: initial release
-------------------------------
-- TODO: puncturation + input rate /= 1
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use work.ccsds_rxtx_functions.all;
use work.ccsds_rxtx_types.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx convolutional coder inputs and outputs
--=============================================================================
entity ccsds_tx_coder_convolutional is
generic(
constant CCSDS_TX_CODER_CONV_CONNEXION_VECTORS: std_logic_vector_array := ("1111001", "1011011");
constant CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE: integer := 7; -- in bits
constant CCSDS_TX_CODER_CONV_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_CODER_CONV_OPERATING_MODE: integer := 1; -- 0=streaming / 1=truncated (reset state when new frame) //TODO: terminated trellis + tailbiting
constant CCSDS_TX_CODER_CONV_OUTPUT_INVERSION: boolean_array := (false, true);
constant CCSDS_TX_CODER_CONV_RATE_OUTPUT: integer := 2; -- in bits/operation
constant CCSDS_TX_CODER_CONV_SEED: std_logic_vector := "000000"
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
bus_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE*CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_coder_convolutional;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_coder_convolutional is
-- internal constants
type connexion_vectors_array is array(CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 downto 0) of std_logic_vector(CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-1 downto 0);
signal connexion_vectors: connexion_vectors_array;
constant connexion_vectors_array_size: integer := CCSDS_TX_CODER_CONV_CONNEXION_VECTORS'length;
constant output_inversion_array_size: integer := CCSDS_TX_CODER_CONV_OUTPUT_INVERSION'length;
-- internal variable signals
signal coder_busy: std_logic := '0';
signal coder_memory: std_logic_vector(CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-2 downto 0) := CCSDS_TX_CODER_CONV_SEED;
-- components instanciation and mapping
begin
bus_o <= coder_busy;
CONNEXION_VECTORS_GENERATOR: for vector_counter in 0 to CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 generate
connexion_vectors(CCSDS_TX_CODER_CONV_RATE_OUTPUT-1-vector_counter) <= convert_std_logic_vector_array_to_std_logic_vector(CCSDS_TX_CODER_CONV_CONNEXION_VECTORS, vector_counter);
end generate CONNEXION_VECTORS_GENERATOR;
-- presynthesis checks
CHKCODERP0 : if (CCSDS_TX_CODER_CONV_SEED'length /= CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-1) generate
process
begin
report "ERROR: SEED SIZE HAS TO BE EQUAL TO CONSTRAINT SIZE - 1" severity failure;
wait;
end process;
end generate CHKCODERP0;
CHKCODERP1 : if (connexion_vectors_array_size /= CCSDS_TX_CODER_CONV_RATE_OUTPUT) generate
process
begin
report "ERROR: CONNEXION VECTORS ARRAY SIZE HAS TO BE EQUAL TO OUTPUT RATE : " & integer'image(connexion_vectors_array_size) severity failure;
wait;
end process;
end generate CHKCODERP1;
CHKCODERP2 : if (output_inversion_array_size /= CCSDS_TX_CODER_CONV_RATE_OUTPUT) generate
process
begin
report "ERROR: OUTPUT INVERSION ARRAY HAS TO BE EQUAL TO OUTPUT RATE" severity failure;
wait;
end process;
end generate CHKCODERP2;
-- internal processing
--=============================================================================
-- Begin of coderp
-- Convolutional encode bits based on connexion vectors
--=============================================================================
-- read: rst_i, dat_i, dat_val_i
-- write: dat_o, dat_val_o, coder_busy
-- r/w:
CODERP: process (clk_i)
variable coder_data_pointer: integer range -1 to (CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1) := -1;
variable coder_data: std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1 downto 0) := (others => '0');
variable coder_atomic_result: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- dat_o <= (others => '0');
dat_val_o <= '0';
coder_memory <= CCSDS_TX_CODER_CONV_SEED;
coder_data_pointer := -1;
coder_atomic_result := '0';
coder_busy <= '0';
else
case coder_data_pointer is
-- no current computation
when -1 =>
dat_val_o <= '0';
-- reset on new frame behaviour
if (CCSDS_TX_CODER_CONV_OPERATING_MODE = 1) then
coder_memory <= CCSDS_TX_CODER_CONV_SEED;
end if;
-- store data
if (dat_val_i = '1') then
coder_data := dat_i;
coder_busy <= '1';
coder_data_pointer := CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1;
else
-- nothing to be done
coder_busy <= '0';
end if;
-- processing
when others =>
coder_busy <= '1';
dat_val_o <= '0';
-- shift memory
coder_memory <= coder_memory(CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-3 downto 0) & coder_data(coder_data_pointer);
-- compute output
for i in CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 downto 0 loop
if (connexion_vectors(i)(CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-1) = '1') then
coder_atomic_result := coder_data(coder_data_pointer);
else
coder_atomic_result := '0';
end if;
for j in CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-2 downto 0 loop
if (connexion_vectors(i)(j) = '1') then
coder_atomic_result := coder_atomic_result xor coder_memory(CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE-2-j);
end if;
end loop;
if (CCSDS_TX_CODER_CONV_OUTPUT_INVERSION(CCSDS_TX_CODER_CONV_RATE_OUTPUT-1-i) = true) then
dat_o(coder_data_pointer*CCSDS_TX_CODER_CONV_RATE_OUTPUT+i) <= not(coder_atomic_result);
else
dat_o(coder_data_pointer*CCSDS_TX_CODER_CONV_RATE_OUTPUT+i) <= coder_atomic_result;
end if;
end loop;
-- output is computed
if (coder_data_pointer = 0) then
coder_busy <= '0';
dat_val_o <= '1';
end if;
coder_data_pointer := coder_data_pointer - 1;
end case;
end if;
end if;
end process;
end rtl;
|
mit
|
ccb9bfa67d4831d855ba67aa2ee98f62
| 0.566301 | 3.950241 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rx_datalink_layer.vhd
| 1 | 1,296 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rx_datalink_layer
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary rx datalink layer
entity ccsds_rx_datalink_layer is
generic (
CCSDS_RX_DATALINK_DATA_BUS_SIZE: integer := 32
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
rst_i: in std_logic;
-- outputs
buf_bit_ful_o: out std_logic;
buf_dat_ful_o: out std_logic;
buf_fra_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0)
);
end ccsds_rx_datalink_layer;
-- internal processing
architecture rtl of ccsds_rx_datalink_layer is
-- TEMPORARY NO CHANGE / DUMMY LINKLAYER
begin
dat_o <= dat_i;
buf_dat_ful_o <= '0';
buf_fra_ful_o <= '0';
buf_bit_ful_o <= '0';
DATALINKP : process (clk_i, dat_i)
begin
end process;
end rtl;
|
mit
|
5da9b76521ce0408c2633ff01b0646c7
| 0.561728 | 3.39267 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/CompressorTopTb.vhd
| 1 | 11,628 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/10/16 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Simple testebench for manual signal inspection of the Wishbone interfaces
--* and the DMA unit of CompressorTop.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity CompressorTop_tb is
end CompressorTop_tb;
architecture TB of CompressorTop_tb is
component CompressorTop
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
SlCycxSI : in std_logic;
SlStbxSI : in std_logic;
SlWexSI : in std_logic;
SlSelxDI : in std_logic_vector(3 downto 0);
SlAdrxDI : in std_logic_vector(4 downto 2);
SlDatxDI : in std_logic_vector(31 downto 0);
SlDatxDO : out std_logic_vector(31 downto 0);
SlAckxSO : out std_logic;
SlErrxSO : out std_logic;
IntxSO : out std_logic;
MaCycxSO : out std_logic;
MaStbxSO : out std_logic;
MaWexSO : out std_logic;
MaSelxDO : out std_logic_vector(3 downto 0);
MaAdrxDO : out std_logic_vector(31 downto 0);
MaDatxDO : out std_logic_vector(31 downto 0);
MaDatxDI : in std_logic_vector(31 downto 0);
MaAckxSI : in std_logic;
MaErrxSI : in std_logic);
end component;
constant PERIOD : time := 25 ns;
signal ClkxCI : std_logic := '0';
signal RstxRI : std_logic := '1';
signal SlCycxSI : std_logic := '0';
signal SlStbxSI : std_logic := '0';
signal SlWexSI : std_logic := '0';
signal SlSelxDI : std_logic_vector(3 downto 0) := "0000";
signal SlAdrxDI : std_logic_vector(4 downto 2) := (others => '0');
signal SlDatxDI : std_logic_vector(31 downto 0) := (others => '0');
signal SlDatxDO : std_logic_vector(31 downto 0) := (others => '0');
signal SlAckxSO : std_logic;
signal SlErrxSO : std_logic;
signal IntxSO : std_logic;
signal MaCycxSO : std_logic;
signal MaStbxSO : std_logic;
signal MaWexSO : std_logic;
signal MaSelxDO : std_logic_vector(3 downto 0) := (others => '0');
signal MaAdrxDO : std_logic_vector(31 downto 0) := (others => '0');
signal MaDatxDO : std_logic_vector(31 downto 0) := (others => '0');
signal MaDatxDI : std_logic_vector(31 downto 0) := (others => '0');
signal MaAckxSI : std_logic := '0';
signal MaErrxSI : std_logic := '0';
begin
ClkxCI <= not ClkxCI after PERIOD/2;
process
begin
RstxRI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RstxRI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
-- reset core
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "111";
SlWexSI <= '1';
SlSelxDI <= "1111";
SlDatxDI <= x"00000001";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- set inc dest addr flag and IE for in fifo full and for core done
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '1';
SlDatxDI <= x"00020100";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- read flags
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
-- setup dma destination
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "100";
SlWexSI <= '1';
SlDatxDI <= x"12345670";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- setup dma length
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "101";
SlWexSI <= '1';
SlDatxDI <= x"00000030";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- read dma destination
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "100";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- setup in fifo thresholds
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "010";
SlWexSI <= '1';
SlDatxDI <= x"000f0004";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"03020100";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"07060504";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0b0a0908";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0f0e0d0c";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"05030201";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"0b0a0706";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"1413120c";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
-- write data
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "000";
SlWexSI <= '1';
SlDatxDI <= x"08070605";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
--wait for PERIOD*2*20;
-- enable done interrupt
-- wait until ClkxCI'event and ClkxCI = '1';
-- SlCycxSI <= '1';
-- SlStbxSI <= '1';
-- SlAdrxDI <= "001";
-- SlWexSI <= '1';
-- SlDatxDI <= x"00200102";
-- wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
-- SlCycxSI <= '0';
-- SlStbxSI <= '0';
-- SlAdrxDI <= "000";
-- SlWexSI <= '0';
-- SlDatxDI <= x"00000000";
-- flush core
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "111";
SlWexSI <= '1';
SlDatxDI <= x"00000002";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait for PERIOD*200;
-- read flags
wait until ClkxCI'event and ClkxCI = '1';
SlCycxSI <= '1';
SlStbxSI <= '1';
SlAdrxDI <= "001";
SlWexSI <= '0';
SlDatxDI <= x"00000000";
wait until ClkxCI'event and ClkxCI = '1' and SlAckxSO = '1';
SlCycxSI <= '0';
SlStbxSI <= '0';
SlAdrxDI <= "000";
wait;
end process;
MaAckxSI <= MaCycxSO and MaStbxSO;
--MaErrxSI <= MaCycxSO and MaStbxSO;
DUT : CompressorTop
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
SlCycxSI => SlCycxSI,
SlStbxSI => SlStbxSI,
SlWexSI => SlWexSI,
SlSelxDI => SlSelxDI,
SlAdrxDI => SlAdrxDI,
SlDatxDI => SlDatxDI,
SlDatxDO => SlDatxDO,
SlAckxSO => SlAckxSO,
SlErrxSO => SlErrxSO,
IntxSO => IntxSO,
MaCycxSO => MaCycxSO,
MaStbxSO => MaStbxSO,
MaWexSO => MaWexSO,
MaSelxDO => MaSelxDO,
MaAdrxDO => MaAdrxDO,
MaDatxDO => MaDatxDO,
MaDatxDI => MaDatxDI,
MaAckxSI => MaAckxSI,
MaErrxSI => MaErrxSI);
end TB;
|
gpl-2.0
|
53840a418fe9f5457f9610f3dbc7975c
| 0.533368 | 3.803729 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_manager.vhd
| 1 | 7,155 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_manager
---- Version: 1.0.0
---- Description:
---- In charge of internal clocks generation + forwarding to reduce power draw + select TX input data
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/10/16: initial release
---- 2016/10/31: add serdes sub-component
---- 2016/11/05: add clock generator sub-component
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx manager inputs and outputs
--=============================================================================
entity ccsds_tx_manager is
generic(
constant CCSDS_TX_MANAGER_BITS_PER_SYMBOL: integer;
constant CCSDS_TX_MANAGER_MODULATION_TYPE: integer;
constant CCSDS_TX_MANAGER_DATALINK_OVERHEAD_RATIO: integer := 2;
constant CCSDS_TX_MANAGER_PARALLELISM_MAX_RATIO: integer := 16;
constant CCSDS_TX_MANAGER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_MANAGER_DATA_BUS_SIZE : integer
);
port(
-- inputs
clk_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
dat_ser_i: in std_logic;
dat_val_i: in std_logic;
ena_i: in std_logic;
in_sel_i: in std_logic; -- 0 = parallel data / 1 = external serial data
rst_i: in std_logic;
-- outputs
clk_bit_o: out std_logic;
clk_dat_o: out std_logic;
clk_sam_o: out std_logic;
clk_sym_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic;
ena_o: out std_logic
);
end ccsds_tx_manager;
--=============================================================================
-- architecture declaration / internal connections
--=============================================================================
architecture structure of ccsds_tx_manager is
component ccsds_rxtx_serdes is
generic (
constant CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
clk_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_i: in std_logic;
dat_ser_i: in std_logic;
dat_ser_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_o: out std_logic;
dat_ser_o: out std_logic;
dat_ser_val_o: out std_logic
);
end component;
component ccsds_rxtx_clock_divider is
generic(
CCSDS_RXTX_CLOCK_DIVIDER: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
clk_o: out std_logic
);
end component;
-- internal constants
-- for simulation only / cannot be used when synthesizing
constant CCSDS_TX_MANAGER_DEBUG: std_logic := '0';
--------------------------------
-- Clocks ratios computations --
--------------------------------
-- clk_dat
---- clk_bit = clk_dat / parallelism * data_link_overhead_ratio
------ clk_sym = clk_bit * data_bus_size / (2 * bits_per_symbol)
-------- clk_sam = clk_sym * oversampling_ratio
constant CCSDS_TX_MANAGER_SAMPLES_TO_SYMBOLS_RATIO: integer := CCSDS_TX_MANAGER_OVERSAMPLING_RATIO;
constant CCSDS_TX_MANAGER_SAMPLES_TO_BITS_RATIO: integer := CCSDS_TX_MANAGER_MODULATION_TYPE*CCSDS_TX_MANAGER_SAMPLES_TO_SYMBOLS_RATIO*CCSDS_TX_MANAGER_DATA_BUS_SIZE/(CCSDS_TX_MANAGER_BITS_PER_SYMBOL*2);
constant CCSDS_TX_MANAGER_SAMPLES_TO_DATA_RATIO: integer := CCSDS_TX_MANAGER_SAMPLES_TO_BITS_RATIO*CCSDS_TX_MANAGER_DATALINK_OVERHEAD_RATIO/CCSDS_TX_MANAGER_PARALLELISM_MAX_RATIO;
-- interconnection signals
signal wire_serdes_dat_par_o: std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
signal wire_serdes_dat_par_val_o: std_logic;
signal wire_serdes_dat_ser_val_i: std_logic;
signal wire_clk_dat: std_logic;
signal wire_rst_clk: std_logic;
begin
-- presynthesis checks
CHKMANAGERP0: if (CCSDS_TX_MANAGER_DEBUG = '1') generate
process
begin
report "INFO: TX CLOCK FREQUENCY HAS TO BE " & integer'image(CCSDS_TX_MANAGER_SAMPLES_TO_DATA_RATIO) & " x WB DATA CLOCK" severity note;
wait;
end process;
end generate CHKMANAGERP0;
-- components instanciation and mapping
clock_divider_bits_001: ccsds_rxtx_clock_divider
generic map(
CCSDS_RXTX_CLOCK_DIVIDER => CCSDS_TX_MANAGER_SAMPLES_TO_BITS_RATIO
)
port map(
clk_i => clk_i,
rst_i => wire_rst_clk,
clk_o => clk_bit_o
);
clock_divider_dat_001: ccsds_rxtx_clock_divider
generic map(
CCSDS_RXTX_CLOCK_DIVIDER => CCSDS_TX_MANAGER_SAMPLES_TO_DATA_RATIO
)
port map(
clk_i => clk_i,
rst_i => wire_rst_clk,
clk_o => wire_clk_dat
);
clock_divider_sam_001: ccsds_rxtx_clock_divider
generic map(
CCSDS_RXTX_CLOCK_DIVIDER => 1
)
port map(
clk_i => clk_i,
rst_i => wire_rst_clk,
clk_o => clk_sam_o
);
clock_divider_sym_001: ccsds_rxtx_clock_divider
generic map(
CCSDS_RXTX_CLOCK_DIVIDER => CCSDS_TX_MANAGER_SAMPLES_TO_SYMBOLS_RATIO
)
port map(
clk_i => clk_i,
rst_i => wire_rst_clk,
clk_o => clk_sym_o
);
serdes_001: ccsds_rxtx_serdes
generic map(
CCSDS_RXTX_SERDES_DEPTH => CCSDS_TX_MANAGER_DATA_BUS_SIZE
)
port map(
clk_i => wire_clk_dat,
dat_par_i => (others => '0'),
dat_par_val_i => '0',
dat_ser_i => dat_ser_i,
dat_ser_val_i => wire_serdes_dat_ser_val_i,
rst_i => rst_i,
dat_par_o => wire_serdes_dat_par_o,
dat_par_val_o => wire_serdes_dat_par_val_o
);
ena_o <= ena_i;
wire_rst_clk <= not(ena_i);
clk_dat_o <= wire_clk_dat;
--=============================================================================
-- Begin of selectp
-- Input selection
--=============================================================================
-- read: rst_i, ena_i, in_sel_i, dat_val_i
-- write: dat_o, dat_val_o, wire_serdes_dat_ser_val_i
-- r/w:
SELECTP : process (wire_clk_dat, ena_i)
-- variables instantiation
begin
-- on each clock rising edge
if rising_edge(wire_clk_dat) and (ena_i = '1') then
if (rst_i = '1') then
dat_o <= (others => '0');
dat_val_o <= '0';
wire_serdes_dat_ser_val_i <= '0';
else
if (in_sel_i = '1') then
wire_serdes_dat_ser_val_i <= '1';
dat_o <= wire_serdes_dat_par_o;
dat_val_o <= wire_serdes_dat_par_val_o;
else
wire_serdes_dat_ser_val_i <= '0';
dat_val_o <= dat_val_i;
dat_o <= dat_par_i;
end if;
end if;
end if;
end process;
end structure;
|
mit
|
71f1a95cc773bc0547c259d427b05a90
| 0.553599 | 3.543834 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_functions.vhd
| 1 | 5,241 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_functions
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/12/28: initial release
---- 2016/10/20: added reverse_std_logic_vector function + rework sim_generate_random_std_logic_vector for > 32 bits vectors
---- 2016/11/17: added convert_boolean_to_std_logic function
---- 2017/01/15: added convert_std_logic_vector_array_to_std_logic_vector
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.ccsds_rxtx_types.all;
package ccsds_rxtx_functions is
-- synthetizable functions
function convert_boolean_to_std_logic(input: in boolean) return std_logic;
function convert_std_logic_vector_array_to_std_logic_vector(std_logic_vector_array_in: in std_logic_vector_array; current_row: in integer) return std_logic_vector;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector;
-- simulation / testbench only functions
function convert_std_logic_vector_to_hexa_ascii(input: in std_logic_vector) return string;
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
end ccsds_rxtx_functions;
package body ccsds_rxtx_functions is
function convert_boolean_to_std_logic(input: in boolean) return std_logic is
begin
if (input = true) then
return '1';
else
return '0';
end if;
end convert_boolean_to_std_logic;
function convert_std_logic_vector_array_to_std_logic_vector(std_logic_vector_array_in: in std_logic_vector_array; current_row: in integer) return std_logic_vector is
variable result: std_logic_vector(std_logic_vector_array_in'range(2));
begin
for i in std_logic_vector_array_in'range(2) loop
result(i) := std_logic_vector_array_in(current_row, i);
-- report "Read: " & std_logic'image(std_logic_vector_array_in(current_row, i)) severity note;
end loop;
return result;
end;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(input'range);
alias output: std_logic_vector(input'REVERSE_RANGE) is input;
begin
for vector_pointer in output'range loop
result(vector_pointer) := output(vector_pointer);
end loop;
return result;
end;
function convert_std_logic_vector_to_hexa_ascii(input: in std_logic_vector) return string is
constant words_number: integer := input'length/4;
variable result: string(words_number-1 downto 0);
variable word: std_logic_vector(3 downto 0);
begin
for vector_word_pointer in words_number-1 downto 0 loop
word := input((vector_word_pointer+1)*4-1 downto vector_word_pointer*4);
case word is
when "0000" =>
result(vector_word_pointer) := '0';
when "0001" =>
result(vector_word_pointer) := '1';
when "0010" =>
result(vector_word_pointer) := '2';
when "0011" =>
result(vector_word_pointer) := '3';
when "0100" =>
result(vector_word_pointer) := '4';
when "0101" =>
result(vector_word_pointer) := '5';
when "0110" =>
result(vector_word_pointer) := '6';
when "0111" =>
result(vector_word_pointer) := '7';
when "1000" =>
result(vector_word_pointer) := '8';
when "1001" =>
result(vector_word_pointer) := '9';
when "1010" =>
result(vector_word_pointer) := 'a';
when "1011" =>
result(vector_word_pointer) := 'b';
when "1100" =>
result(vector_word_pointer) := 'c';
when "1101" =>
result(vector_word_pointer) := 'd';
when "1110" =>
result(vector_word_pointer) := 'e';
when "1111" =>
result(vector_word_pointer) := 'f';
when others =>
result(vector_word_pointer) := '?';
end case;
-- report "Converted " & integer'image(to_integer(resize(unsigned(word),16))) & " to " & result(vector_word_pointer) severity note;
end loop;
return result;
end;
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector) is
variable rand: real := 0.0;
variable temp: std_logic_vector(31 downto 0);
begin
if (vector_size < 32) then
uniform(seed1, seed2, rand);
rand := rand*(2**(real(vector_size))-1.0);
result := std_logic_vector(to_unsigned(integer(rand),vector_size));
else
uniform(seed1, seed2, rand);
for vector_pointer in 0 to vector_size-1 loop
uniform(seed1, seed2, rand);
rand := rand*(2**(real(31))-1.0);
temp := std_logic_vector(to_unsigned(integer(rand),32));
result(vector_pointer) := temp(0);
end loop;
end if;
end sim_generate_random_std_logic_vector;
end ccsds_rxtx_functions;
|
mit
|
5ced8e2dd6aeb6b59ab6daa74ca96d76
| 0.628506 | 3.536437 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_datalink_layer.vhd
| 1 | 7,952 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_datalink_layer
---- Version: 1.0.0
---- Description:
---- TM (TeleMetry) Space Data Link Protocol
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/21: rework based on TX final architecture
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx datalink layer inputs and outputs
--=============================================================================
entity ccsds_tx_datalink_layer is
generic (
constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
);
port(
-- inputs
clk_bit_i: in std_logic;
clk_dat_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_nxt_o: out std_logic;
dat_val_o: out std_logic;
idl_o: out std_logic
);
end ccsds_tx_datalink_layer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_datalink_layer is
component ccsds_tx_framer is
generic(
CCSDS_TX_FRAMER_DATA_BUS_SIZE : integer;
CCSDS_TX_FRAMER_DATA_LENGTH : integer;
CCSDS_TX_FRAMER_FOOTER_LENGTH : integer;
CCSDS_TX_FRAMER_HEADER_LENGTH : integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic;
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_tx_coder is
generic(
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
CCSDS_TX_CODER_ASM_LENGTH: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8;
constant FRAME_OUTPUT_WORDS: integer := FRAME_OUTPUT_SIZE/CCSDS_TX_DATALINK_DATA_BUS_SIZE;
-- interconnection signals
signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
signal wire_framer_data_valid: std_logic;
signal wire_coder_data: std_logic_vector(FRAME_OUTPUT_SIZE-1 downto 0);
signal wire_coder_data_valid: std_logic;
-- components instanciation and mapping
begin
tx_datalink_framer_0: ccsds_tx_framer
generic map(
CCSDS_TX_FRAMER_HEADER_LENGTH => CCSDS_TX_DATALINK_HEADER_LENGTH,
CCSDS_TX_FRAMER_DATA_LENGTH => CCSDS_TX_DATALINK_DATA_LENGTH,
CCSDS_TX_FRAMER_FOOTER_LENGTH => CCSDS_TX_DATALINK_FOOTER_LENGTH,
CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_TX_DATALINK_DATA_BUS_SIZE
)
port map(
clk_i => clk_dat_i,
rst_i => rst_i,
dat_val_i => dat_val_i,
dat_i => dat_i,
dat_val_o => wire_framer_data_valid,
dat_nxt_o => dat_nxt_o,
dat_o => wire_framer_data,
idl_o => idl_o
);
tx_datalink_coder_0: ccsds_tx_coder
generic map(
CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
)
port map(
clk_i => clk_dat_i,
dat_i => wire_framer_data,
dat_val_i => wire_framer_data_valid,
rst_i => rst_i,
dat_val_o => wire_coder_data_valid,
dat_o => wire_coder_data
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
--=============================================================================
-- read: rst_i, wire_coder_data_valid
-- write: dat_val_o
-- r/w:
BITSVALIDP: process (clk_dat_i)
begin
-- on each clock rising edge
if rising_edge(clk_dat_i) then
-- reset signal received
if (rst_i = '1') then
dat_val_o <= '0';
else
if (wire_coder_data_valid = '1') then
dat_val_o <= '1';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of bitsoutputp
-- Generate bits output word by word based on coder output
--=============================================================================
-- read: rst_i, wire_coder_data
-- write: dat_o
-- r/w:
BITSOUTPUTP: process (clk_bit_i)
variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
variable current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_bit_i) then
-- reset signal received
if (rst_i = '1') then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
dat_o <= (others => '0');
else
-- generating valid bits output words
if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
next_word_pointer := FRAME_OUTPUT_WORDS - 2;
else
dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
if (next_word_pointer = 0) then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
else
next_word_pointer := next_word_pointer - 1;
end if;
end if;
end if;
end if;
end process;
end structure;
|
mit
|
4fe7b5bdf99d79350d9e3a3b85491649
| 0.586771 | 3.703773 | false | false | false | false |
plorefice/freon
|
tests/hdl/core/reg_file_tb.vhdl
| 1 | 1,988 |
-- Design:
-- Testbench for the register file of the Freon core.
--
-- Authors:
-- Pietro Lorefice <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg_file_tb is
end entity; -- reg_file_tb
architecture tb of reg_file_tb is
constant T : time := 1 ns; -- arbitrary test time
signal clk, arst, w_en : std_logic := '0';
signal r_addr_1, r_addr_2, w_addr : std_logic_vector(4 downto 0) := (others => '0');
signal r_data_1, r_data_2, w_data : std_logic_vector(31 downto 0) := (others => '0');
signal tb_over : std_logic := '0';
begin
-- unit under test
uut : entity work.reg_file
generic map (XLEN => 32, ALEN => 5)
port map (
clk => clk,
arst => arst,
w_en => w_en,
r_addr_1 => r_addr_1,
r_addr_2 => r_addr_2,
w_addr => w_addr,
r_data_1 => r_data_1,
r_data_2 => r_data_2,
w_data => w_data
);
-- testbench clock
clk <= not clk after T/2 when tb_over /='1' else '0';
-- asynchronous reset
arst <= '1', '0' after T;
-- testbench
tb_proc : process
begin
-- Make sure register r0 always contains zero
r_addr_1 <= "00000"; wait for T;
assert r_data_1 = X"00000000" report "R0 != 0" severity failure;
-- Try to set R0
wait until falling_edge(clk);
w_addr <= "00000"; w_data <= X"ffffffff"; w_en <= '1';
wait for T; w_en <= '0';
assert r_data_1 = X"00000000" report "R0 != 0" severity failure;
-- Set two random registers
wait until falling_edge(clk);
w_addr <= "01010"; w_data <= X"aabbccdd"; w_en <= '1';
wait for T; w_en <= '0';
wait until falling_edge(clk);
w_addr <= "10101"; w_data <= X"11223344"; w_en <= '1';
wait for T; w_en <= '0';
-- Read back those registers
r_addr_1 <= "01010"; r_addr_2 <= "10101"; wait for T;
assert r_data_1 = X"aabbccdd" and r_data_2 = X"11223344"
report "Wrong data read" severity failure;
tb_over <= '1'; -- Terminate testbench
end process; -- tb_proc
end architecture; -- reg_file_tb
|
mit
|
77e8f47b30aedbd37bbb985ed13802d6
| 0.603622 | 2.661312 | false | true | false | false |
jayvalentine/vhdl-risc-processor
|
mux_4_32_bit.vhd
| 1 | 1,325 |
-- 4-input 32-bit multiplexer
-- this circuit takes 4 32-bit inputs and selects one to output based on a 2-bit control signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_4_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
in_32_2 : in std_logic_vector(31 downto 0);
in_32_3 : in std_logic_vector(31 downto 0);
-- input select
input_select : in std_logic_vector(1 downto 0);
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end entity mux_4_32_bit;
architecture mux_4_32_bit_arch of mux_4_32_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(input_select, in_32_0, in_32_1, in_32_2, in_32_3)
begin
-- select 00 is input 0
if input_select = "00" then
out_32 <= in_32_0;
-- select 01 is input 1
elsif input_select = "01" then
out_32 <= in_32_1;
-- select 10 is input 2
elsif input_select = "10" then
out_32 <= in_32_2;
-- select 11 is input 3
elsif input_select = "11" then
out_32 <= in_32_3;
-- otherwise invalid select signal, output 0
else
out_32 <= (others => '0');
end if;
end process mux;
end architecture mux_4_32_bit_arch;
|
mit
|
4e67d4738381b0d5409ee0492a5769d4
| 0.65434 | 2.665996 | false | false | false | false |
daveshah1/openMixR
|
fpga/vivado/openmixr_base/openmixr_base.srcs/sources_1/ip/init_config_rom/misc/blk_mem_gen_v8_3.vhd
| 1 | 8,325 |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_4 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_4;
architecture xilinx of blk_mem_gen_v8_3_4 is
begin
end
architecture xilinx;
|
mit
|
8644aa1ebac49782167a009a593e965e
| 0.42967 | 3.611714 | false | false | false | false |
jpendlum/crash
|
fpga/src/usrp_ddr_intf/usrp_ddr_intf.vhd
| 2 | 76,094 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: usrp_ddr_intf.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Interfaces transmit and receive data between the FPGA
-- development board and the USRP N2xx and includes
-- RX decimation and TX interpolation filters with rate changes
-- from 1 to 8188. Includes fixed point to floating point
-- converts (bypassable) and multipliers for gain correction.
-- Most components are based on Xilinx IP.
--
-- Converts DDR input data (data transitions on both rising and
-- falling edges) to SDR data (data transition only on rising
-- edge). To conserve pins at the physical interface, the DDR
-- data runs at twice the SDR data rate. This means the SDR
-- data is split across two clocks, i.e. for 16-bit data the
-- upper byte is sent first, then the lower byte second.
--
-- The interface has independent RX and TX PLLs for calibration/
-- The calibration procedure requires putting the custom
-- firmware running on the USRP into RX_TEST_PATTERN_MODE. The
-- RX PLL is shifted until the RX data matches the pattern
-- without error. Then, the custom USRP firmware is set into
-- RX_TX_LOOPBACK_MODE and a unique pattern sent to the USRP
-- through this block. The TX PLL can be adjusted until the same
-- pattern is received back with errors. This entire process is
-- automated in a software program called calibrate provided
-- with the framework code.
--
-- A UART is used to control the custom firmware running on
-- the USRP that receives RX/ADC data and injects our TX/DAC data.
--
-- The RX and TX filter paths use two FIR and one CIC filter
-- per path per I & Q. This results in 8 FIR filters and 4
-- CIC filters. The FIR filters are half-band 23 tap filters
-- with +60 dB out of band attenuation.
--
-- Note: The USRP operates at 100 MHz.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity usrp_ddr_intf is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 1e6); -- UART baud rate
port (
reset : in std_logic; -- Asynchronous reset
-- Control registers (internally synchronized to clk_rx clock domain)
usrp_mode_ctrl : in std_logic_vector(7 downto 0); -- USRP Mode
usrp_mode_ctrl_en : in std_logic; -- USRP Mode data valid, hold until acknowledge
usrp_mode_ctrl_ack : out std_logic; -- USRP Mode register acknowledge
rx_enable : in std_logic; -- Enable RX processing chain (clears resets)
rx_gain : in std_logic_vector(31 downto 0); -- Scales decimating CIC filter output
rx_cic_decim : in std_logic_vector(10 downto 0); -- Receive CIC decimation rate
rx_cic_decim_en : in std_logic; -- Set receive CIC decimation rate
rx_cic_decim_ack : out std_logic; -- Set receive CIC decimation rate acknowledge
rx_fix2float_bypass : in std_logic; -- Bypass RX fixed to floating point conversion
rx_cic_bypass : in std_logic; -- Bypass RX CIC filter
rx_hb_bypass : in std_logic; -- Bypass RX half band filter
tx_enable : in std_logic; -- Enable TX processing chain (clears resets)
tx_gain : in std_logic_vector(31 downto 0); -- Scales interpolating CIC filter output
tx_cic_interp : in std_logic_vector(10 downto 0); -- Transmit CIC interpolation rate
tx_cic_interp_en : in std_logic; -- Set transmit CIC interpolation rate
tx_cic_interp_ack : out std_logic; -- Set transmit CIC interpolation rate acknowledge
tx_float2fix_bypass : in std_logic; -- Bypass TX floating to fixed point conversion
tx_cic_bypass : in std_logic; -- Bypass TX CIC filter
tx_hb_bypass : in std_logic; -- Bypass TX half band filter
-- UART output signals
uart_busy : out std_logic; -- UART busy
UART_TX : out std_logic; -- UART
-- Physical Transmit / Receive data interface
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(4 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(4 downto 0); -- Receive data (P)
RX_DATA_STB_N : in std_logic; -- Receive data strobe (N)
RX_DATA_STB_P : in std_logic; -- Receive data strobe (P)
TX_DATA_N : out std_logic_vector(5 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(5 downto 0); -- Transmit data (P)
TX_DATA_STB_N : out std_logic; -- Transmit data strobe (N)
TX_DATA_STB_P : out std_logic; -- Transmit data strobe (P)
clk_rx_locked : out std_logic; -- RX data MMCM clock locked
clk_rx_phase : out std_logic_vector(9 downto 0); -- RX data MMCM phase offset, 0 - 559
rx_phase_init : in std_logic_vector(9 downto 0); -- RX data MMCM phase offset initialization, 0 - 559
rx_phase_incdec : in std_logic; -- '1' = Increment, '0' = Decrement
rx_phase_en : in std_logic; -- Increment / decrements RX data MMCM phase (Rising edge)
rx_phase_busy : out std_logic; -- RX data MMCM phase adjustment in process
rx_restart_cal : in std_logic; -- Restart RX data MMCM phase calibration
rx_cal_complete : out std_logic; -- RX data MMCM phase calibration complete
clk_tx_locked : out std_logic; -- TX data MMCM clock locked
clk_tx_phase : out std_logic_vector(9 downto 0); -- TX data MMCM phase offset, 0 - 559
tx_phase_init : in std_logic_vector(9 downto 0); -- TX data MMCM phase offset initialization, 0 - 559
tx_phase_incdec : in std_logic; -- '1' = Increment, '0' = Decrement
tx_phase_en : in std_logic; -- Increment / decrements TX data MMCM phase (Rising edge)
tx_phase_busy : out std_logic; -- TX data MMCM phase adjustment in process
tx_restart_cal : in std_logic; -- Restart TX data MMCM phase calibration
tx_cal_complete : out std_logic; -- TX data MMCM phase calibration complete
-- Receive data FIFO interface (all signals on clk_rx_fifo clock domain)
clk_rx_fifo : in std_logic; -- Receive data FIFO clock
rx_fifo_reset : in std_logic; -- Receive data FIFO reset
rx_fifo_data_i : out std_logic_vector(31 downto 0); -- Receive data FIFO output
rx_fifo_data_q : out std_logic_vector(31 downto 0); -- Receive data FIFO output
rx_fifo_rd_en : in std_logic; -- Receive data FIFO read enable
rx_fifo_underflow : out std_logic; -- Receive data FIFO underflow
rx_fifo_empty : out std_logic; -- Receive data FIFO empty
rx_fifo_almost_empty : out std_logic; -- Receive data FIFO almost empty
rx_fifo_overflow_latch : out std_logic; -- Receive data FIFO overflow (clears on reset)
rx_fifo_overflow_clr : in std_logic; -- Receive data FIFO clears overflow latch
-- Receive data FIFO interface (all signals on clk_tx_fifo clock domain)
clk_tx_fifo : in std_logic; -- Transmit data FIFO clock
tx_fifo_reset : in std_logic; -- Transmit data FIFO reset
tx_fifo_data_i : in std_logic_vector(31 downto 0); -- Transmit data FIFO output
tx_fifo_data_q : in std_logic_vector(31 downto 0); -- Transmit data FIFO output
tx_fifo_wr_en : in std_logic; -- Transmit data FIFO write enable
tx_fifo_overflow : out std_logic; -- Transmit data FIFO overflow
tx_fifo_full : out std_logic; -- Transmit data FIFO full
tx_fifo_almost_full : out std_logic; -- Transmit data FIFO almost full
tx_fifo_underflow_latch : out std_logic; -- Transmit data FIFO underflow (clears on reset)
tx_fifo_underflow_clr : in std_logic); -- Transmit data FIFO clears underflow latch
end entity;
architecture RTL of usrp_ddr_intf is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component BUFG is
port (
O : out std_logic; -- Clock buffer output
I : in std_logic); -- Clock buffer input
end component;
component synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end component;
component synchronizer_slv is
generic (
STROBE_EDGE : string := "NONE"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic_vector := "0");
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic_vector; -- Asynchronous input
sync : out std_logic_vector); -- Synchronized output
end component;
component mmcm_ddr_to_sdr is
port (
CLKIN_300MHz : in std_logic;
CLKOUT_100MHz : out std_logic;
CLKOUT_300MHz : out std_logic;
-- Dynamic phase shift ports
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic);
end component;
component fifo_64x8192 is
port (
wr_rst : in std_logic;
wr_clk : in std_logic;
rd_rst : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic;
overflow : out std_logic;
underflow : out std_logic);
end component;
component uart is
generic (
CLOCK_FREQ : integer := 100e6; -- Input clock frequency (Hz)
BAUD : integer := 1e6; -- Baud rate (bits/sec)
DATA_BITS : integer := 8; -- Number of data bits
PARITY : string := "MARK"; -- EVEN, ODD, MARK (always = '1'), SPACE (always = '0'), NONE
NO_STROBE_ON_ERR : string := "TRUE"); -- No rx_data_stb if error in received data.
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
tx_busy : out std_logic; -- Transmitting data
tx_data_stb : in std_logic; -- Transmit buffer load and begin transmission strobe
tx_data : in std_logic_vector(DATA_BITS-1 downto 0);
rx_busy : out std_logic; -- Receiving data
rx_data_stb : out std_logic; -- Receive buffer data valid strobe
rx_data : out std_logic_vector(DATA_BITS-1 downto 0);
rx_error : out std_logic; -- '1' = Invalid parity bit, start bit, or stop bit(s)
tx : out std_logic; -- TX output
rx : in std_logic); -- RX input
end component;
component fifo_16x15
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(14 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(14 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic);
end component;
component fifo_16x18
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(17 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(17 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic);
end component;
component cic_decimator is
port (
din : in std_logic_vector(13 downto 0);
rate : in std_logic_vector(10 downto 0);
rate_we : in std_logic;
sclr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(46 downto 0);
nd : in std_logic;
rdy : out std_logic;
rfd : out std_logic);
end component;
component mult_rx_gain_adjust is
port (
clk : in std_logic;
a : in std_logic_vector(46 downto 0);
b : in std_logic_vector(31 downto 0);
sclr : in std_logic;
p : out std_logic_vector(35 downto 0));
end component;
component fir_halfband_decimator is
port (
sclr : in std_logic;
clk : in std_logic;
nd : in std_logic;
rfd : out std_logic;
rdy : out std_logic;
data_valid : out std_logic;
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fix1_31_to_float32 is
port (
a : in std_logic_vector(31 downto 0);
clk : in std_logic;
sclr : in std_logic;
operation_nd : in std_logic;
operation_rfd : out std_logic;
rdy : out std_logic;
result : out std_logic_vector(31 downto 0));
end component;
component cic_interpolator is
port (
din : in std_logic_vector(19 downto 0);
rate : in std_logic_vector(10 downto 0);
rate_we : in std_logic;
sclr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(41 downto 0);
nd : in std_logic;
rdy : out std_logic;
rfd : out std_logic);
end component;
component mult_tx_gain_adjust is
port (
clk : in std_logic;
a : in std_logic_vector(41 downto 0);
b : in std_logic_vector(31 downto 0);
sclr : in std_logic;
p : out std_logic_vector(19 downto 0));
end component;
component fir_halfband_interpolator is
port (
sclr : in std_logic;
clk : in std_logic;
nd : in std_logic;
ce : in std_logic;
rfd : out std_logic;
rdy : out std_logic;
data_valid : out std_logic;
din : in std_logic_vector(19 downto 0);
dout : out std_logic_vector(19 downto 0));
end component;
component float32_to_fix1_19 is
port (
a : in std_logic_vector(31 downto 0);
clk : in std_logic;
sclr : in std_logic;
operation_nd : in std_logic;
operation_rfd : out std_logic;
rdy : out std_logic;
result : out std_logic_vector(19 downto 0));
end component;
component trunc_unbiased is
generic (
WIDTH_IN : integer;
TRUNCATE : integer);
port (
i : in std_logic_vector(WIDTH_IN-1 downto 0);
o : out std_logic_vector(WIDTH_IN-TRUNCATE-1 downto 0));
end component;
-----------------------------------------------------------------------------
-- Constants Declaration
-----------------------------------------------------------------------------
-- RX modes (lower nibble)
constant RX_ADC_RAW_MODE : std_logic_vector(3 downto 0) := x"0";
constant RX_ADC_DSP_MODE : std_logic_vector(3 downto 0) := x"1";
constant RX_SINE_TEST_MODE : std_logic_vector(3 downto 0) := x"2";
constant RX_TEST_PATTERN_MODE : std_logic_vector(3 downto 0) := x"3";
constant RX_ALL_1s_MODE : std_logic_vector(3 downto 0) := x"4";
constant RX_ALL_0s_MODE : std_logic_vector(3 downto 0) := x"5";
constant RX_CHA_1s_CHB_0s_MODE : std_logic_vector(3 downto 0) := x"6";
constant RX_CHA_0s_CHB_1s_MODE : std_logic_vector(3 downto 0) := x"7";
constant RX_CHECK_ALIGN_MODE : std_logic_vector(3 downto 0) := x"8";
constant RX_TX_LOOPBACK_MODE : std_logic_vector(3 downto 0) := x"9";
-- TX modes (upper nibble)
constant TX_PASSTHRU_MODE : std_logic_vector(3 downto 0) := x"0";
constant TX_DAC_RAW_MODE : std_logic_vector(3 downto 0) := x"1";
constant TX_DAC_DSP_MODE : std_logic_vector(3 downto 0) := x"2";
constant TX_SINE_TEST_MODE : std_logic_vector(3 downto 0) := x"3";
constant TX_RX_LOOPBACK_MODE : std_logic_vector(3 downto 0) := x"4";
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
type rx_state_type is (SET_RX_PHASE,WAIT_RX_PHASE,RX_CALIBRATION_COMPLETE);
type tx_state_type is (SET_TX_PHASE,WAIT_TX_PHASE,TX_CALIBRATION_COMPLETE);
signal rx_state : rx_state_type;
signal tx_state : tx_state_type;
signal clk_rx : std_logic;
signal clk_rx_3x : std_logic;
signal clk_tx : std_logic;
signal clk_tx_3x : std_logic;
signal ddr_data_clk : std_logic;
signal ddr_data_clk_bufg : std_logic;
signal clk_rx_locked_int : std_logic;
signal clk_tx_locked_int : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal rx_psen : std_logic;
signal rx_psincdec : std_logic;
signal rx_psdone : std_logic;
signal rx_phase_busy_int : std_logic;
signal tx_psen : std_logic;
signal tx_psincdec : std_logic;
signal tx_psdone : std_logic;
signal tx_phase_busy_int : std_logic;
signal tx_busy : std_logic;
signal tx_test_pattern_en : std_logic;
signal rx_mmcm_phase : integer range 0 to 559;
signal tx_mmcm_phase : integer range 0 to 559;
signal rx_async : std_logic_vector(67 downto 0);
signal rx_sync : std_logic_vector(67 downto 0);
signal rx_async_rising : std_logic_vector(4 downto 0);
signal rx_sync_rising : std_logic_vector(4 downto 0);
signal tx_async : std_logic_vector(58 downto 0);
signal tx_sync : std_logic_vector(58 downto 0);
signal tx_async_rising : std_logic_vector(3 downto 0);
signal tx_sync_rising : std_logic_vector(3 downto 0);
signal rx_phase_init_sync : std_logic_vector(9 downto 0);
signal rx_phase_incdec_sync : std_logic;
signal rx_phase_en_sync : std_logic;
signal tx_phase_init_sync : std_logic_vector(9 downto 0);
signal tx_phase_incdec_sync : std_logic;
signal tx_phase_en_sync : std_logic;
signal usrp_mode_ctrl_sync : std_logic_vector(7 downto 0);
signal usrp_mode_ctrl_en_sync : std_logic;
signal usrp_mode_ctrl_stb : std_logic;
signal rx_fix2float_bypass_sync : std_logic;
signal rx_cic_bypass_sync : std_logic;
signal rx_hb_bypass_sync : std_logic;
signal rx_cic_decim_sync : std_logic_vector(10 downto 0);
signal rx_cic_decim_en_sync : std_logic;
signal rx_cic_decim_stb : std_logic;
signal rx_gain_sync : std_logic_vector(31 downto 0);
signal tx_float2fix_bypass_sync : std_logic;
signal tx_cic_bypass_sync : std_logic;
signal tx_hb_bypass_sync : std_logic;
signal tx_cic_interp_sync : std_logic_vector(10 downto 0);
signal tx_cic_interp_en_sync : std_logic;
signal tx_cic_interp_stb : std_logic;
signal tx_gain_sync : std_logic_vector(31 downto 0);
signal rx_enable_sync : std_logic;
signal rx_enable_stb : std_logic;
signal rx_enable_n : std_logic;
signal tx_enable_sync : std_logic;
signal tx_enable_stb : std_logic;
signal tx_enable_n : std_logic;
signal usrp_mode_ctrl_ack_int : std_logic;
signal rx_restart_cal_sync : std_logic;
signal tx_restart_cal_sync : std_logic;
signal rx_cic_decim_ack_int : std_logic;
signal tx_cic_interp_ack_int : std_logic;
-- CRASH-USRP interface signals
signal tx_data_3x_i : std_logic_vector(5 downto 0);
signal tx_data_3x_q : std_logic_vector(5 downto 0);
signal tx_data_3x_stb : std_logic;
signal tx_data_3x_ddr : std_logic_vector(5 downto 0);
signal tx_data_3x_stb_ddr : std_logic;
signal tx_fifo_3x_din_i : std_logic_vector(17 downto 0);
signal tx_fifo_3x_din_q : std_logic_vector(17 downto 0);
signal tx_fifo_3x_dout_i : std_logic_vector(17 downto 0);
signal tx_fifo_3x_dout_q : std_logic_vector(17 downto 0);
signal tx_fifo_3x_rd_en : std_logic;
signal tx_fifo_3x_wr_en : std_logic;
signal tx_fifo_3x_full : std_logic;
signal tx_fifo_3x_empty : std_logic;
signal tx_cnt : integer range 0 to 2;
signal rx_data_i : std_logic_vector(13 downto 0);
signal rx_data_q : std_logic_vector(13 downto 0);
signal rx_data_3x_i : std_logic_vector(4 downto 0);
signal rx_data_3x_q : std_logic_vector(4 downto 0);
signal rx_data_3x_stb : std_logic;
signal rx_data_3x_ddr : std_logic_vector(4 downto 0);
signal rx_data_3x_stb_ddr : std_logic;
signal rx_fifo_3x_din_i : std_logic_vector(14 downto 0);
signal rx_fifo_3x_din_q : std_logic_vector(14 downto 0);
signal rx_fifo_3x_dout_i : std_logic_vector(14 downto 0);
signal rx_fifo_3x_dout_q : std_logic_vector(14 downto 0);
signal rx_fifo_3x_rd_en : std_logic;
signal rx_fifo_3x_wr_en : std_logic;
signal rx_fifo_3x_full : std_logic;
signal rx_fifo_3x_empty : std_logic;
-- RX signals
signal rx_cic_rate : std_logic_vector(10 downto 0);
signal rx_cic_rate_we : std_logic;
signal rx_cic_nd : std_logic;
signal rx_cic_din_i : std_logic_vector(13 downto 0);
signal rx_cic_din_q : std_logic_vector(13 downto 0);
signal rx_cic_dout_i : std_logic_vector(46 downto 0);
signal rx_cic_dout_q : std_logic_vector(46 downto 0);
signal rx_cic_rdy_i : std_logic;
signal rx_cic_rfd_i : std_logic;
signal rx_gain_din_i : std_logic_vector(46 downto 0);
signal rx_gain_din_q : std_logic_vector(46 downto 0);
signal rx_gain_dout_i : std_logic_vector(35 downto 0);
signal rx_gain_dout_q : std_logic_vector(35 downto 0);
signal rx_gain_dout_trunc_i : std_logic_vector(31 downto 0);
signal rx_gain_dout_trunc_q : std_logic_vector(31 downto 0);
signal rx_halfband_nd : std_logic;
signal rx_halfband_rfd_i : std_logic;
signal rx_halfband_dout_valid_i : std_logic;
signal rx_halfband_din_i : std_logic_vector(31 downto 0);
signal rx_halfband_dout_i : std_logic_vector(31 downto 0);
signal rx_halfband_din_q : std_logic_vector(31 downto 0);
signal rx_halfband_dout_q : std_logic_vector(31 downto 0);
signal rx_fix2float_nd : std_logic;
signal rx_fix2float_rfd_i : std_logic;
signal rx_fix2float_rdy_i : std_logic;
signal rx_fix2float_din_i : std_logic_vector(31 downto 0);
signal rx_fix2float_dout_i : std_logic_vector(31 downto 0);
signal rx_fix2float_din_q : std_logic_vector(31 downto 0);
signal rx_fix2float_dout_q : std_logic_vector(31 downto 0);
signal rx_fifo_wr_en : std_logic;
signal rx_fifo_wr_en_int : std_logic;
signal rx_fifo_rd_en_int : std_logic;
signal rx_fifo_empty_int : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_overflow : std_logic;
signal rx_fifo_overflow_latch_int : std_logic;
signal rx_fifo_overflow_clr_sync : std_logic;
signal rx_fifo_din : std_logic_vector(63 downto 0);
signal rx_fifo_dout : std_logic_vector(63 downto 0);
-- TX signals
signal tx_cic_rate : std_logic_vector(10 downto 0);
signal tx_cic_rate_we : std_logic;
signal tx_data_i : std_logic_vector(31 downto 0);
signal tx_data_q : std_logic_vector(31 downto 0);
signal tx_cic_nd : std_logic;
signal tx_cic_nd_int : std_logic;
signal tx_cic_din_i : std_logic_vector(19 downto 0);
signal tx_cic_din_q : std_logic_vector(19 downto 0);
signal tx_cic_dout_i : std_logic_vector(41 downto 0);
signal tx_cic_dout_q : std_logic_vector(41 downto 0);
signal tx_cic_rdy_i : std_logic;
signal tx_cic_rfd_i : std_logic;
signal tx_gain_din_i : std_logic_vector(41 downto 0);
signal tx_gain_din_q : std_logic_vector(41 downto 0);
signal tx_gain_dout_i : std_logic_vector(19 downto 0);
signal tx_gain_dout_q : std_logic_vector(19 downto 0);
signal tx_halfband_ce : std_logic;
signal tx_halfband_nd : std_logic;
signal tx_halfband_nd_int : std_logic;
signal tx_halfband_rfd_i : std_logic;
signal tx_halfband_dout_valid_i : std_logic;
signal tx_halfband_din_i : std_logic_vector(19 downto 0);
signal tx_halfband_dout_i : std_logic_vector(19 downto 0);
signal tx_halfband_din_q : std_logic_vector(19 downto 0);
signal tx_halfband_dout_q : std_logic_vector(19 downto 0);
signal tx_float2fix_nd : std_logic;
signal tx_float2fix_rfd_i : std_logic;
signal tx_float2fix_rdy_i : std_logic;
signal tx_float2fix_dout_i : std_logic_vector(19 downto 0);
signal tx_float2fix_dout_q : std_logic_vector(19 downto 0);
signal tx_trunc_din_i : std_logic_vector(19 downto 0);
signal tx_trunc_din_q : std_logic_vector(19 downto 0);
signal tx_trunc_dout_i : std_logic_vector(15 downto 0);
signal tx_trunc_dout_q : std_logic_vector(15 downto 0);
signal tx_fifo_wr_en_int : std_logic;
signal tx_fifo_rd_en : std_logic;
signal tx_fifo_rd_en_int : std_logic;
signal tx_fifo_full_int : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_underflow : std_logic;
signal tx_fifo_underflow_latch_int : std_logic;
signal tx_fifo_underflow_clr_sync : std_logic;
signal tx_fifo_din : std_logic_vector(63 downto 0);
signal tx_fifo_dout : std_logic_vector(63 downto 0);
begin
inst_rx_clk_IBUFDS : IBUFDS
generic map (
DIFF_TERM => TRUE,
IOSTANDARD => "DEFAULT")
port map (
I => RX_DATA_CLK_P,
IB => RX_DATA_CLK_N,
O => ddr_data_clk);
-- Use a BUFG to buffer the DDR data clk
inst_BUFG : BUFG
port map (
I => ddr_data_clk,
O => ddr_data_clk_bufg);
-----------------------------------------------------------------------------
-- State machine to adjust the RX and TX data MMCM phase
-----------------------------------------------------------------------------
proc_calibrate_rx_mmcm : process(clk_rx,rx_reset)
begin
if (rx_reset = '1') then
rx_mmcm_phase <= 0;
rx_psincdec <= '0';
rx_psen <= '0';
rx_phase_busy_int <= '0';
rx_cal_complete <= '0';
rx_state <= SET_RX_PHASE;
else
if rising_edge(clk_rx) then
case rx_state is
when SET_RX_PHASE =>
if (rx_mmcm_phase /= rx_phase_init_sync) then
rx_psincdec <= '1';
rx_psen <= '1';
if (rx_mmcm_phase = 559) then
rx_mmcm_phase <= 0;
else
rx_mmcm_phase <= rx_mmcm_phase + 1;
end if;
rx_state <= WAIT_RX_PHASE;
else
rx_state <= RX_CALIBRATION_COMPLETE;
end if;
when WAIT_RX_PHASE =>
rx_psen <= '0';
if (rx_psdone = '1') then
rx_state <= SET_RX_PHASE;
end if;
when RX_CALIBRATION_COMPLETE =>
-- Only forward USRP DDR interface mode changes when
-- we are not calibrating the interface.
rx_cal_complete <= '1';
rx_psen <= '0';
if (rx_restart_cal_sync = '1') then
rx_cal_complete <= '0';
rx_state <= SET_RX_PHASE;
end if;
-- Allow manual manipulation of MMCM phase
if (rx_phase_en_sync = '1' AND rx_phase_busy_int = '0') then
rx_psincdec <= rx_phase_incdec_sync;
rx_psen <= '1';
rx_phase_busy_int <= '1';
-- Adjust mmcm phase counter based on whether we are incrementing
-- or decrementing
if (rx_phase_incdec_sync = '1') then
if (rx_mmcm_phase = 559) then
rx_mmcm_phase <= 0;
else
rx_mmcm_phase <= rx_mmcm_phase + 1;
end if;
else
if (rx_mmcm_phase = 0) then
rx_mmcm_phase <= 559;
else
rx_mmcm_phase <= rx_mmcm_phase - 1;
end if;
end if;
end if;
if (rx_psdone = '1') then
rx_phase_busy_int <= '0';
end if;
when others =>
rx_state <= SET_RX_PHASE;
end case;
end if;
end if;
end process;
proc_calibrate_tx_mmcm : process(clk_tx,tx_reset)
begin
if (tx_reset = '1') then
tx_mmcm_phase <= 0;
tx_psincdec <= '0';
tx_psen <= '0';
tx_phase_busy_int <= '0';
tx_cal_complete <= '0';
tx_state <= SET_TX_PHASE;
else
if rising_edge(clk_tx) then
case tx_state is
when SET_TX_PHASE =>
if (tx_mmcm_phase /= tx_phase_init_sync) then
tx_psincdec <= '1';
tx_psen <= '1';
if (tx_mmcm_phase = 559) then
tx_mmcm_phase <= 0;
else
tx_mmcm_phase <= tx_mmcm_phase + 1;
end if;
tx_state <= WAIT_TX_PHASE;
else
tx_state <= TX_CALIBRATION_COMPLETE;
end if;
when WAIT_TX_PHASE =>
tx_psen <= '0';
if (tx_psdone = '1') then
tx_state <= SET_TX_PHASE;
end if;
when TX_CALIBRATION_COMPLETE =>
tx_cal_complete <= '1';
tx_psen <= '0';
if (tx_restart_cal_sync = '1') then
tx_cal_complete <= '0';
tx_state <= SET_TX_PHASE;
end if;
-- Allow manual manipulation of MMCM phase
if (tx_phase_en_sync = '1' AND tx_phase_busy_int = '0') then
tx_psincdec <= tx_phase_incdec_sync;
tx_psen <= '1';
tx_phase_busy_int <= '1';
-- Adjust mmcm phase counter based on whether we are incrementing
-- or decrementing
if (tx_phase_incdec_sync = '1') then
if (tx_mmcm_phase = 559) then
tx_mmcm_phase <= 0;
else
tx_mmcm_phase <= tx_mmcm_phase + 1;
end if;
else
if (tx_mmcm_phase = 0) then
tx_mmcm_phase <= 559;
else
tx_mmcm_phase <= tx_mmcm_phase - 1;
end if;
end if;
end if;
if (tx_psdone = '1') then
tx_phase_busy_int <= '0';
end if;
when others =>
tx_state <= SET_TX_PHASE;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- RX Path
-----------------------------------------------------------------------------
-- Route BUFG DDR data clock to MMCM to generate a phase shifted
-- global clock whose rising edge is ideally in the middle of
-- the DDR data bit
inst_rx_mmcm_ddr_to_sdr : mmcm_ddr_to_sdr
port map (
CLKIN_300MHz => ddr_data_clk_bufg,
CLKOUT_100MHz => clk_rx,
CLKOUT_300MHz => clk_rx_3x,
PSCLK => clk_rx,
PSEN => rx_psen,
PSINCDEC => rx_psincdec,
PSDONE => rx_psdone,
RESET => reset,
LOCKED => clk_rx_locked_int);
rx_reset <= NOT(clk_rx_locked_int);
-- DDR LVDS Data Input
gen_rx_ddr_lvds : for i in 0 to 4 generate
inst_IDDR : IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
SRTYPE => "ASYNC")
port map (
Q1 => rx_data_3x_i(i),
Q2 => rx_data_3x_q(i),
C => clk_rx_3x,
CE => '1',
D => rx_data_3x_ddr(i),
R => rx_reset,
S => '0');
inst_IBUFDS : IBUFDS
generic map (
DIFF_TERM => TRUE,
IOSTANDARD => "DEFAULT")
port map (
I => RX_DATA_P(i),
IB => RX_DATA_N(i),
O => rx_data_3x_ddr(i));
end generate;
inst_rx_stb_IDDR : IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
SRTYPE => "ASYNC")
port map (
Q1 => open,
Q2 => rx_data_3x_stb,
C => clk_rx_3x,
CE => '1',
D => rx_data_3x_stb_ddr,
R => rx_reset,
S => '0');
inst_rx_stb_IBUFDS : IBUFDS
generic map (
DIFF_TERM => TRUE,
IOSTANDARD => "DEFAULT")
port map (
I => RX_DATA_STB_P,
IB => RX_DATA_STB_N,
O => rx_data_3x_stb_ddr);
proc_rx_data_assemble : process(clk_rx_3x,rx_reset)
begin
if (rx_reset = '1') then
rx_fifo_3x_din_i <= (others=>'0');
rx_fifo_3x_din_q <= (others=>'0');
rx_fifo_3x_wr_en <= '0';
else
if rising_edge(clk_rx_3x) then
rx_fifo_3x_wr_en <= rx_data_3x_stb;
rx_fifo_3x_din_i(4 downto 0) <= rx_data_3x_i;
rx_fifo_3x_din_i(9 downto 5) <= rx_fifo_3x_din_i(4 downto 0);
rx_fifo_3x_din_i(14 downto 10) <= rx_fifo_3x_din_i(9 downto 5);
rx_fifo_3x_din_q(4 downto 0) <= rx_data_3x_q;
rx_fifo_3x_din_q(9 downto 5) <= rx_fifo_3x_din_q(4 downto 0);
rx_fifo_3x_din_q(14 downto 10) <= rx_fifo_3x_din_q(9 downto 5);
end if;
end if;
end process;
inst_rx_fifo_i : fifo_16x15
port map (
rst => rx_reset,
wr_clk => clk_rx_3x,
rd_clk => clk_rx,
din => rx_fifo_3x_din_i,
wr_en => rx_fifo_3x_wr_en,
rd_en => rx_fifo_3x_rd_en,
dout => rx_fifo_3x_dout_i,
full => rx_fifo_3x_full,
almost_full => open,
empty => rx_fifo_3x_empty,
almost_empty => open);
inst_rx_fifo_q : fifo_16x15
port map (
rst => rx_reset,
wr_clk => clk_rx_3x,
rd_clk => clk_rx,
din => rx_fifo_3x_din_q,
wr_en => rx_fifo_3x_wr_en,
rd_en => rx_fifo_3x_rd_en,
dout => rx_fifo_3x_dout_q,
full => open,
almost_full => open,
empty => open,
almost_empty => open);
rx_fifo_3x_rd_en <= NOT(rx_fifo_3x_empty);
rx_data_i <= rx_fifo_3x_dout_i(14 downto 1); -- Sample data is only 14-bit wide
rx_data_q <= rx_fifo_3x_dout_q(14 downto 1);
-- RX chain filtering
rx_cic_rate <= rx_cic_decim_sync;
rx_cic_rate_we <= rx_cic_decim_stb OR rx_enable_stb;
i_cic_decimator : cic_decimator
port map (
clk => clk_rx,
sclr => rx_enable_n,
din => rx_cic_din_i,
rate => rx_cic_rate,
rate_we => rx_cic_rate_we,
dout => rx_cic_dout_i,
nd => rx_cic_nd,
rdy => rx_cic_rdy_i,
rfd => rx_cic_rfd_i);
q_cic_decimator : cic_decimator
port map (
clk => clk_rx,
sclr => rx_enable_n,
din => rx_cic_din_q,
rate => rx_cic_rate,
rate_we => rx_cic_rate_we,
dout => rx_cic_dout_q,
nd => rx_cic_nd,
rdy => open,
rfd => open);
-- The halfband FIR filters use 32 bit wide inputs. To ensure we use the
-- maximum dynamic range, we apply gain to CIC filter's output based on the
-- decimation rate.
-- WARNING: Input a is 47 bits, input b is 32 bits, so the resulting output
-- p internally is 72 bits wide. However, the output is the
-- bit slice p(47 down 16).
i_mult_rx_gain_adjust : mult_rx_gain_adjust
port map (
clk => clk_rx,
sclr => rx_enable_n,
a => rx_gain_din_i,
b => rx_gain_sync,
p => rx_gain_dout_i);
q_mult_rx_gain_adjust : mult_rx_gain_adjust
port map (
clk => clk_rx,
sclr => rx_enable_n,
a => rx_gain_din_q,
b => rx_gain_sync,
p => rx_gain_dout_q);
-- Truncation causes a -0.5 bias. This performs unbiased truncation of multiplier output to 32 bits.
-- We only use 4 bits as rounding more bits yields diminishing returns.
i_rx_gain_trunc_unbiased : trunc_unbiased
generic map (
WIDTH_IN => 36,
TRUNCATE => 4)
port map (
i => rx_gain_dout_i,
o => rx_gain_dout_trunc_i);
q_rx_gain_trunc_unbiased : trunc_unbiased
generic map (
WIDTH_IN => 36,
TRUNCATE => 4)
port map (
i => rx_gain_dout_q,
o => rx_gain_dout_trunc_q);
-- FIR Halfband Decimation
-- Input is fixed1_31, output is fixed2_30 due to the very small filter gain
i_fir_halfband_decimator : fir_halfband_decimator
port map (
clk => clk_rx,
sclr => rx_enable_n,
nd => rx_halfband_nd,
rfd => rx_halfband_rfd_i,
rdy => open,
data_valid => rx_halfband_dout_valid_i,
din => rx_halfband_din_i,
dout => rx_halfband_dout_i);
q_fir_halfband_decimator : fir_halfband_decimator
port map (
clk => clk_rx,
sclr => rx_enable_n,
nd => rx_halfband_nd,
rfd => open,
rdy => open,
data_valid => open,
din => rx_halfband_din_q,
dout => rx_halfband_dout_q);
-- Convert 32 bit fixed point to 32 bit floating point
i_fix1_31_to_float32 : fix1_31_to_float32
port map (
clk => clk_rx,
sclr => rx_enable_n,
operation_nd => rx_fix2float_nd,
operation_rfd => rx_fix2float_rfd_i,
rdy => rx_fix2float_rdy_i,
a => rx_fix2float_din_i,
result => rx_fix2float_dout_i);
q_fix1_31_to_float32 : fix1_31_to_float32
port map (
clk => clk_rx,
sclr => rx_enable_n,
operation_nd => rx_fix2float_nd,
operation_rfd => open,
rdy => open,
a => rx_fix2float_din_q,
result => rx_fix2float_dout_q);
-- Implement flow control signals and bypass logic
rx_cic_din_i <= rx_data_i;
rx_cic_din_q <= rx_data_q;
rx_cic_nd <= '1' when rx_cic_bypass_sync = '1' else rx_cic_rfd_i;
rx_gain_din_i <= rx_data_i & (32 downto 0 => '0') when rx_cic_bypass_sync = '1' else rx_cic_dout_i;
rx_gain_din_q <= rx_data_q & (32 downto 0 => '0') when rx_cic_bypass_sync = '1' else rx_cic_dout_q;
rx_halfband_din_i <= rx_gain_dout_trunc_i;
rx_halfband_din_q <= rx_gain_dout_trunc_q;
rx_halfband_nd <= rx_cic_nd when rx_cic_bypass_sync = '1' else rx_cic_rdy_i;
rx_fix2float_din_i <= rx_halfband_din_i when rx_hb_bypass_sync = '1' else rx_halfband_dout_i;
rx_fix2float_din_q <= rx_halfband_din_q when rx_hb_bypass_sync = '1' else rx_halfband_dout_q;
rx_fix2float_nd <= rx_halfband_nd when rx_hb_bypass_sync = '1' else rx_halfband_dout_valid_i;
-- FIFO for clock crossing and buffering (Receive)
-- Bypass fixed to float conversion and output raw data when decimation is set to 0
rx_fifo_din <= rx_fix2float_din_i & rx_fix2float_din_q when rx_fix2float_bypass_sync = '1' else
rx_fix2float_dout_i & rx_fix2float_dout_q;
rx_fifo_wr_en <= rx_fifo_wr_en_int AND NOT(rx_fifo_full);
rx_fifo_wr_en_int <= rx_fix2float_nd when rx_fix2float_bypass_sync = '1' else
rx_fix2float_rdy_i;
rx_fifo_rd_en_int <= rx_fifo_rd_en AND NOT(rx_fifo_empty_int);
rx_fifo_data_i <= rx_fifo_dout(63 downto 32);
rx_fifo_data_q <= rx_fifo_dout(31 downto 0);
inst_rx_data_fifo_64x8192 : fifo_64x8192
port map (
wr_rst => '0',
wr_clk => clk_rx,
rd_rst => rx_fifo_reset,
rd_clk => clk_rx_fifo,
din => rx_fifo_din,
wr_en => rx_fifo_wr_en,
rd_en => rx_fifo_rd_en_int,
dout => rx_fifo_dout,
full => rx_fifo_full,
almost_full => rx_fifo_almost_full,
empty => rx_fifo_empty_int,
almost_empty => rx_fifo_almost_empty,
overflow => rx_fifo_overflow,
underflow => rx_fifo_underflow);
-- Latch overflow to indicate that the FIFO needs to be reset
proc_rx_overflow_latch : process(clk_rx,rx_enable_sync)
begin
if (rx_enable_sync = '0') then
rx_fifo_overflow_latch_int <= '0';
else
if rising_edge(clk_rx) then
if (rx_fifo_wr_en_int = '1' AND rx_fifo_full = '1') then
rx_fifo_overflow_latch_int <= '1';
end if;
if (rx_fifo_overflow_clr_sync = '1') then
rx_fifo_overflow_latch_int <= '0';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- TX Path
-----------------------------------------------------------------------------
-- This MMCM is used to phase shift the TX data clock independently of the
-- RX data clock.
inst_tx_mmcm_ddr_to_sdr : mmcm_ddr_to_sdr
port map (
CLKIN_300MHz => ddr_data_clk_bufg,
CLKOUT_100MHz => clk_tx,
CLKOUT_300MHz => clk_tx_3x,
PSCLK => clk_tx,
PSEN => tx_psen,
PSINCDEC => tx_psincdec,
PSDONE => tx_psdone,
RESET => reset,
LOCKED => clk_tx_locked_int);
tx_reset <= NOT(clk_tx_locked_int);
-- LVDS DDR Data Interface, 3x Clock Domain (300 MHz)
-- Transmit 16-bit TX I/Q data at 300 MHz DDR.
inst_tx_fifo_i : fifo_16x18
port map (
rst => tx_reset,
wr_clk => clk_tx,
rd_clk => clk_tx_3x,
din => tx_fifo_3x_din_i,
wr_en => tx_fifo_3x_wr_en,
rd_en => tx_fifo_3x_rd_en,
dout => tx_fifo_3x_dout_i,
full => tx_fifo_3x_full,
almost_full => open,
empty => tx_fifo_3x_empty,
almost_empty => open);
inst_tx_fifo_q : fifo_16x18
port map (
rst => tx_reset,
wr_clk => clk_tx,
rd_clk => clk_tx_3x,
din => tx_fifo_3x_din_q,
wr_en => tx_fifo_3x_wr_en,
rd_en => tx_fifo_3x_rd_en,
dout => tx_fifo_3x_dout_q,
full => open,
almost_full => open,
empty => open,
almost_empty => open);
tx_fifo_3x_wr_en <= NOT(tx_fifo_3x_full);
tx_fifo_3x_rd_en <= tx_data_3x_stb;
tx_fifo_3x_din_i <= tx_trunc_dout_i & "00";
tx_fifo_3x_din_q <= tx_trunc_dout_q & "00";
proc_gen_tx_data : process(clk_tx_3x,tx_reset)
begin
if (tx_reset = '1') then
tx_cnt <= 0;
tx_data_3x_stb <= '0';
tx_data_3x_i <= (others=>'0');
tx_data_3x_q <= (others=>'0');
else
if rising_edge(clk_tx_3x) then
case tx_cnt is
when 0 =>
tx_cnt <= tx_cnt + 1;
tx_data_3x_stb <= '0';
tx_data_3x_i <= tx_fifo_3x_dout_i(17 downto 12);
tx_data_3x_q <= tx_fifo_3x_dout_q(17 downto 12);
when 1 =>
tx_cnt <= tx_cnt + 1;
tx_data_3x_stb <= '0';
tx_data_3x_i <= tx_fifo_3x_dout_i(11 downto 6);
tx_data_3x_q <= tx_fifo_3x_dout_q(11 downto 6);
when 2 =>
tx_cnt <= 0;
tx_data_3x_stb <= NOT(tx_fifo_empty);
tx_data_3x_i <= tx_fifo_3x_dout_i(5 downto 0);
tx_data_3x_q <= tx_fifo_3x_dout_q(5 downto 0);
when others =>
end case;
end if;
end if;
end process;
-- DDR LVDS Data Output
gen_tx_ddr_lvds : for i in 0 to 5 generate
inst_ODDR : ODDR
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE",
SRTYPE => "ASYNC")
port map (
Q => tx_data_3x_ddr(i),
C => clk_tx_3x,
CE => '1',
D1 => tx_data_3x_i(i),
D2 => tx_data_3x_q(i),
R => tx_reset,
S => '0');
inst_OBUFDS : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
I => tx_data_3x_ddr(i),
O => TX_DATA_P(i),
OB => TX_DATA_N(i));
end generate;
inst_tx_stb_ODDR : ODDR
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE",
SRTYPE => "ASYNC")
port map (
Q => tx_data_3x_stb_ddr,
C => clk_tx_3x,
CE => '1',
D1 => '0',
D2 => tx_data_3x_stb,
R => tx_reset,
S => '0');
inst_tx_stb_OBUFDS : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
I => tx_data_3x_stb_ddr,
O => TX_DATA_STB_P,
OB => TX_DATA_STB_N);
-- TX Interpolation Chain
-- Convert 32 bit floating point to 20 bit fixed point (fix1_19)
i_float32_to_fix1_19 : float32_to_fix1_19
port map (
clk => clk_tx,
sclr => tx_enable_n,
operation_nd => tx_float2fix_nd,
operation_rfd => tx_float2fix_rfd_i,
rdy => tx_float2fix_rdy_i,
a => tx_data_i,
result => tx_float2fix_dout_i);
q_float32_to_fix1_19 : float32_to_fix1_19
port map (
clk => clk_tx,
sclr => tx_enable_n,
operation_nd => tx_float2fix_nd,
operation_rfd => open,
rdy => open,
a => tx_data_q,
result => tx_float2fix_dout_q);
-- FIR Halfband Interpolator
-- Input is fixed1_31, output is fixed2_30 due to the very small filter gain
i_fir_halfband_interpolator : fir_halfband_interpolator
port map (
clk => clk_tx,
sclr => tx_enable_n,
nd => tx_halfband_nd,
ce => tx_halfband_ce,
rfd => tx_halfband_rfd_i,
rdy => open,
data_valid => tx_halfband_dout_valid_i,
din => tx_halfband_din_i,
dout => tx_halfband_dout_i);
q_fir_halfband_interpolator : fir_halfband_interpolator
port map (
clk => clk_tx,
sclr => tx_enable_n,
nd => tx_halfband_nd,
ce => tx_halfband_ce,
rfd => open,
rdy => open,
data_valid => open,
din => tx_halfband_din_q,
dout => tx_halfband_dout_q);
-- CIC Filter with programmabled decimation rate of 4 - 2047.
tx_cic_rate <= tx_cic_interp;
tx_cic_rate_we <= tx_cic_interp_stb OR tx_enable_stb;
i_cic_interpolator : cic_interpolator
port map (
clk => clk_tx,
sclr => tx_enable_n,
din => tx_cic_din_i,
rate => tx_cic_rate,
rate_we => tx_cic_rate_we,
dout => tx_cic_dout_i,
nd => tx_cic_nd,
rdy => tx_cic_rdy_i,
rfd => tx_cic_rfd_i);
q_cic_interpolator : cic_interpolator
port map (
clk => clk_tx,
sclr => tx_enable_n,
din => tx_cic_din_q,
rate => tx_cic_rate,
rate_we => tx_cic_rate_we,
dout => tx_cic_dout_q,
nd => tx_cic_nd,
rdy => open,
rfd => open);
-- To ensure we use the maximum dynamic range, we apply gain to CIC filter's
-- output based on the interpolation rate.
-- WARNING: Input a is 42 bits, input b is 32 bits, so the resulting output
-- p internally is 74 bits wide. However, the output is the
-- bit slice p(41 downto 22).
i_mult_tx_gain_adjust : mult_tx_gain_adjust
port map (
clk => clk_tx,
sclr => tx_enable_n,
a => tx_gain_din_i,
b => tx_gain_sync,
p => tx_gain_dout_i);
q_mult_tx_gain_adjust : mult_tx_gain_adjust
port map (
clk => clk_tx,
sclr => tx_enable_n,
a => tx_gain_din_q,
b => tx_gain_sync,
p => tx_gain_dout_q);
i_tx_trunc_unbiased : trunc_unbiased
generic map (
WIDTH_IN => 20,
TRUNCATE => 4)
port map (
i => tx_trunc_din_i,
o => tx_trunc_dout_i);
q_tx_trunc_unbiased : trunc_unbiased
generic map (
WIDTH_IN => 20,
TRUNCATE => 4)
port map (
i => tx_trunc_din_q,
o => tx_trunc_dout_q);
-- TX data flow control and bypassing
tx_float2fix_nd <= '1' when tx_hb_bypass_sync = '1' AND tx_cic_bypass_sync = '1' else
tx_cic_rfd_i when tx_hb_bypass_sync = '1' AND tx_cic_bypass_sync = '0' else
tx_halfband_rfd_i;
tx_halfband_din_i <= tx_data_i(15 downto 0) & x"0" when tx_float2fix_bypass_sync = '1' else tx_float2fix_dout_i;
tx_halfband_din_q <= tx_data_q(15 downto 0) & x"0" when tx_float2fix_bypass_sync = '1' else tx_float2fix_dout_q;
tx_halfband_ce <= '1' when tx_cic_bypass_sync = '1' else tx_cic_rfd_i;
tx_halfband_nd <= tx_halfband_rfd_i AND tx_halfband_nd_int;
tx_halfband_nd_int <= tx_float2fix_nd when tx_float2fix_bypass_sync = '1' else tx_float2fix_rdy_i;
tx_cic_din_i <= tx_halfband_din_i when tx_hb_bypass_sync = '1' else tx_halfband_dout_i;
tx_cic_din_q <= tx_halfband_din_q when tx_hb_bypass_sync = '1' else tx_halfband_dout_q;
tx_cic_nd <= tx_cic_rfd_i AND tx_cic_nd_int;
tx_cic_nd_int <= tx_halfband_nd_int when tx_hb_bypass_sync = '1' else tx_halfband_dout_valid_i;
tx_gain_din_i <= tx_cic_din_i & (21 downto 0 => '0') when tx_cic_bypass_sync = '1' else tx_cic_dout_i;
tx_gain_din_q <= tx_cic_din_q & (21 downto 0 => '0') when tx_cic_bypass_sync = '1' else tx_cic_dout_q;
tx_trunc_din_i <= tx_gain_dout_i;
tx_trunc_din_q <= tx_gain_dout_q;
-- FIFOs for clock crossing and buffering (Transmit)
tx_fifo_rd_en <= tx_fifo_rd_en_int AND NOT(tx_fifo_empty);
tx_fifo_rd_en_int <= tx_float2fix_nd AND tx_enable_sync;
tx_fifo_wr_en_int <= tx_fifo_wr_en AND NOT(tx_fifo_full_int);
tx_fifo_din <= tx_fifo_data_i & tx_fifo_data_q;
tx_data_i <= tx_fifo_dout(63 downto 32);
tx_data_q <= tx_fifo_dout(31 downto 0);
inst_tx_data_fifo_64x8192 : fifo_64x8192
port map (
wr_rst => tx_fifo_reset,
wr_clk => clk_tx_fifo,
rd_rst => '0',
rd_clk => clk_tx,
din => tx_fifo_din,
wr_en => tx_fifo_wr_en_int,
rd_en => tx_fifo_rd_en,
dout => tx_fifo_dout,
full => tx_fifo_full_int,
almost_full => tx_fifo_almost_full,
empty => tx_fifo_empty,
almost_empty => tx_fifo_almost_empty,
overflow => tx_fifo_overflow,
underflow => tx_fifo_underflow);
-- Latch underflow to indicate that the FIFO needs to be reset
proc_tx_underflow_latch : process(clk_tx,tx_enable_sync)
begin
if (tx_enable_sync = '0') then
tx_fifo_underflow_latch_int <= '0';
else
if rising_edge(clk_tx) then
if (tx_fifo_rd_en_int = '1' AND tx_fifo_empty = '1') then
tx_fifo_underflow_latch_int <= '1';
end if;
if (tx_fifo_underflow_clr_sync = '1') then
tx_fifo_underflow_latch_int <= '0';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- UART to set USRP receive and transmit modes
-----------------------------------------------------------------------------
inst_uart : uart
generic map (
CLOCK_FREQ => DDR_CLOCK_FREQ,
BAUD => BAUD,
DATA_BITS => 8,
PARITY => "EVEN",
NO_STROBE_ON_ERR => "TRUE")
port map (
clk => clk_rx,
reset => rx_reset,
tx_busy => tx_busy,
tx_data_stb => usrp_mode_ctrl_stb,
tx_data => usrp_mode_ctrl_sync,
rx_busy => open,
rx_data_stb => open,
rx_data => open,
rx_error => open,
tx => UART_TX,
rx => '1');
uart_busy <= tx_busy;
-----------------------------------------------------------------------------
-- Acknowledgement Logic
-----------------------------------------------------------------------------
proc_acknowledgements : process(clk_rx,rx_reset)
begin
if (rx_reset = '1') then
usrp_mode_ctrl_ack_int <= '0';
rx_cic_decim_ack_int <= '0';
tx_cic_interp_ack_int <= '0';
else
if rising_edge(clk_rx) then
-- Acknowledgement for UART control interface
if (usrp_mode_ctrl_en_sync = '1' AND usrp_mode_ctrl_ack_int = '0') then
usrp_mode_ctrl_ack_int <= '1';
end if;
if (usrp_mode_ctrl_en_sync = '0') then
usrp_mode_ctrl_ack_int <= '0';
end if;
-- Acknowledgement for RX CIC
if (rx_cic_decim_en_sync = '1' AND rx_cic_decim_ack_int = '0') then
rx_cic_decim_ack_int <= '1';
end if;
if (rx_cic_decim_en_sync = '0') then
rx_cic_decim_ack_int <= '0';
end if;
-- Acknowledgement for TX CIC
if (tx_cic_interp_en_sync = '1' AND tx_cic_interp_ack_int = '0') then
tx_cic_interp_ack_int <= '1';
end if;
if (tx_cic_interp_en_sync = '0') then
tx_cic_interp_ack_int <= '0';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Synchronizers
-----------------------------------------------------------------------------
-- RX Synchronizers
inst_rx_synchronizer : synchronizer_slv
generic map (
STROBE_EDGE => "N", -- None, Output is input
-- Note: RESET_OUTPUT sets the reset state of the sync output. There is
-- some special handling in this module with regards to the value.
-- It can be a single value, such as "0", which will set all the
-- reset values to "0". Or you can enter the individual reset values
-- of each bit in the sync output signal.
-- See the source code for more details.
RESET_OUTPUT => "0")
port map (
clk => clk_rx,
reset => rx_reset,
async => rx_async,
sync => rx_sync);
inst_rx_synchronizer_rising_edge_detect : synchronizer_slv
generic map (
STROBE_EDGE => "R", -- Risinge edge, strobe output on the rising edge
RESET_OUTPUT => "0")
port map (
clk => clk_rx,
reset => rx_reset,
async => rx_async_rising,
sync => rx_sync_rising);
rx_async_rising(0) <= usrp_mode_ctrl_en;
rx_async_rising(1) <= rx_phase_en;
rx_async_rising(2) <= rx_cic_decim_en;
rx_async_rising(3) <= rx_restart_cal;
rx_async_rising(4) <= rx_enable;
usrp_mode_ctrl_stb <= rx_sync_rising(0);
rx_phase_en_sync <= rx_sync_rising(1);
rx_cic_decim_stb <= rx_sync_rising(2);
rx_restart_cal_sync <= rx_sync_rising(3);
rx_enable_stb <= rx_sync_rising(4);
rx_async(7 downto 0) <= usrp_mode_ctrl;
rx_async(8) <= rx_phase_incdec;
rx_async(19 downto 9) <= rx_cic_decim;
rx_async(20) <= rx_fix2float_bypass;
rx_async(21) <= rx_cic_bypass;
rx_async(22) <= rx_hb_bypass;
rx_async(54 downto 23) <= rx_gain;
rx_async(64 downto 55) <= rx_phase_init;
rx_async(65) <= rx_enable;
rx_async(66) <= rx_cic_decim_en;
rx_async(67) <= usrp_mode_ctrl_en;
usrp_mode_ctrl_sync <= rx_sync(7 downto 0);
rx_phase_incdec_sync <= rx_sync(8);
rx_cic_decim_sync <= rx_sync(19 downto 9);
rx_fix2float_bypass_sync <= rx_sync(20);
rx_cic_bypass_sync <= rx_sync(21);
rx_hb_bypass_sync <= rx_sync(22);
rx_gain_sync <= rx_sync(54 downto 23);
rx_phase_init_sync <= rx_sync(64 downto 55);
rx_enable_sync <= rx_sync(65);
rx_cic_decim_en_sync <= rx_sync(66);
usrp_mode_ctrl_en_sync <= rx_sync(67);
rx_enable_n <= NOT(rx_enable_sync);
-- TX Synchronizers
inst_tx_synchronizer : synchronizer_slv
generic map (
STROBE_EDGE => "N",
RESET_OUTPUT => "0")
port map (
clk => clk_tx,
reset => tx_reset,
async => tx_async,
sync => tx_sync);
inst_tx_synchronizer_rising_edge_detect : synchronizer_slv
generic map (
STROBE_EDGE => "R",
RESET_OUTPUT => "0")
port map (
clk => clk_tx,
reset => tx_reset,
async => tx_async_rising,
sync => tx_sync_rising);
tx_async_rising(0) <= tx_phase_en;
tx_async_rising(1) <= tx_cic_interp_en;
tx_async_rising(2) <= tx_restart_cal;
tx_async_rising(3) <= tx_enable;
tx_phase_en_sync <= tx_sync_rising(0);
tx_cic_interp_stb <= tx_sync_rising(1);
tx_restart_cal_sync <= tx_sync_rising(2);
tx_enable_stb <= tx_sync_rising(3);
tx_async(0) <= tx_phase_incdec;
tx_async(11 downto 1) <= tx_cic_interp;
tx_async(12) <= tx_float2fix_bypass;
tx_async(13) <= tx_cic_bypass;
tx_async(14) <= tx_hb_bypass;
tx_async(46 downto 15) <= tx_gain;
tx_async(56 downto 47) <= tx_phase_init;
tx_async(57) <= tx_enable;
tx_async(58) <= tx_cic_interp_en;
tx_phase_incdec_sync <= tx_sync(0);
tx_cic_interp_sync <= tx_sync(11 downto 1);
tx_float2fix_bypass_sync <= tx_sync(12);
tx_cic_bypass_sync <= tx_sync(13);
tx_hb_bypass_sync <= tx_sync(14);
tx_gain_sync <= tx_sync(46 downto 15);
tx_phase_init_sync <= tx_sync(56 downto 47);
tx_enable_sync <= tx_sync(57);
tx_cic_interp_en_sync <= tx_sync(58);
tx_enable_n <= NOT(tx_enable_sync);
-- Sychronizer for rx overflow latch
inst_rx_overflow_latch_synchronizer : synchronizer
port map (
clk => clk_rx_fifo,
reset => rx_enable,
async => rx_fifo_overflow_latch_int,
sync => rx_fifo_overflow_latch);
-- Sychronizer for rx overflow latch clear
inst_rx_overflow_clr_synchronizer : synchronizer
port map (
clk => clk_rx,
reset => rx_reset,
async => rx_fifo_overflow_clr,
sync => rx_fifo_overflow_clr_sync);
-- Sychronizer for tx underflow latch
inst_tx_underflow_latch_synchronizer : synchronizer
port map (
clk => clk_tx_fifo,
reset => tx_fifo_reset,
async => tx_fifo_underflow_latch_int,
sync => tx_fifo_underflow_latch);
-- Sychronizer for tx underflow latch
inst_tx_underflow_clr_synchronizer : synchronizer
port map (
clk => clk_tx,
reset => tx_reset,
async => tx_fifo_underflow_clr,
sync => tx_fifo_underflow_clr_sync);
-----------------------------------------------------------------------------
-- Internal signals to output ports
-----------------------------------------------------------------------------
usrp_mode_ctrl_ack <= usrp_mode_ctrl_ack_int;
rx_cic_decim_ack <= rx_cic_decim_ack_int;
tx_cic_interp_ack <= tx_cic_interp_ack_int;
rx_phase_busy <= rx_phase_busy_int;
tx_phase_busy <= tx_phase_busy_int;
clk_rx_locked <= clk_rx_locked_int;
clk_tx_locked <= clk_tx_locked_int;
clk_rx_phase <= std_logic_vector(to_unsigned(rx_mmcm_phase,10));
clk_tx_phase <= std_logic_vector(to_unsigned(tx_mmcm_phase,10));
tx_fifo_full <= tx_fifo_full_int;
rx_fifo_empty <= rx_fifo_empty_int;
end RTL;
|
gpl-3.0
|
e20de755793d00d0a31678e66ae5c3ef
| 0.435212 | 4.034891 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/xst_14_2/historyTb.vhd
| 1 | 4,158 |
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity historyBuffer_tb is
end historyBuffer_tb;
-------------------------------------------------------------------------------
architecture tb of historyBuffer_tb is
component historyBuffer
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
WriteInxDI : in std_logic_vector(7 downto 0);
WExSI : in std_logic;
NextWrAdrxDO : out std_logic_vector(11 downto 0);
RExSI : in std_logic;
ReadBackAdrxDI : in std_logic_vector(11 downto 2);
ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
ReadBackDonexSO : out std_logic);
end component;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal WriteInxDI : std_logic_vector(7 downto 0) := (others => '0');
signal WExSI : std_logic := '0';
signal NextWrAdrxDO : std_logic_vector(11 downto 0);
signal RExSI : std_logic := '0';
signal ReadBackAdrxDI : std_logic_vector(11 downto 2);
signal ReadBackxDO : std_logic_vector(16*8-1 downto 0);
signal ReadBackDonexSO : std_logic;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT: historyBuffer
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
WriteInxDI => WriteInxDI,
WExSI => WExSI,
NextWrAdrxDO => NextWrAdrxDO,
RExSI => RExSI,
ReadBackAdrxDI => ReadBackAdrxDI,
ReadBackxDO => ReadBackxDO,
ReadBackDonexSO => ReadBackDonexSO);
-- clock generation
Clk <= not Clk after 10 ns;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc: process
begin
wait for 10 ns;
wait until Clk = '1';
RstxRI <= '0';
-- first: write some data to buffer
wait until Clk'event and Clk='1';
WriteInxDI <= x"00";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"01";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"02";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"03";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"04";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"05";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"06";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"07";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"08";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"09";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0a";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0b";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0c";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0d";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0e";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0f";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"10";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"11";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"12";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"13";
WExSI <= '1';
wait until Clk'event and Clk='1';
WExSI <= '0';
-- now read back
ReadBackAdrxDI <= "0000000000";
wait until Clk'event and Clk='1';
ReadBackAdrxDI <= "0000000001";
wait until Clk'event and Clk='1';
ReadBackAdrxDI <= "0000000002";
wait until Clk'event and Clk='1';
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration historyBuffer_tb_tb_cfg of historyBuffer_tb is
for tb
end for;
end historyBuffer_tb_tb_cfg;
-------------------------------------------------------------------------------
|
gpl-2.0
|
96d7eee47bdb36847748e3aeb5e2eac5
| 0.53343 | 3.948718 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp_cmp.vhd
| 1 | 52,964 |
-- megafunction wizard: %ALTFP_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_compare
-- ============================================================
-- File Name: fp_cmp.vhd
-- Megafunction Name(s):
-- altfp_compare
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 WIDTH_EXP=8 WIDTH_MAN=23 aclr agb clk_en clock dataa datab
--VERSION_BEGIN 9.1SP2 cbx_altfp_compare 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 4 reg 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_cmp_altfp_compare_v5c IS
PORT
(
aclr : IN STD_LOGIC := '0';
agb : OUT STD_LOGIC;
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cmp_altfp_compare_v5c;
ARCHITECTURE RTL OF fp_cmp_altfp_compare_v5c IS
SIGNAL out_agb_w_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_cmpr1_aeb : STD_LOGIC;
SIGNAL wire_cmpr1_agb : STD_LOGIC;
SIGNAL wire_cmpr2_aeb : STD_LOGIC;
SIGNAL wire_cmpr2_agb : STD_LOGIC;
SIGNAL wire_cmpr3_aeb : STD_LOGIC;
SIGNAL wire_cmpr3_agb : STD_LOGIC;
SIGNAL wire_cmpr4_aeb : STD_LOGIC;
SIGNAL wire_cmpr4_agb : STD_LOGIC;
SIGNAL wire_w_lg_w304w305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_agb_w_dffe2_wo314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_flip_outputs_dffe2_wo310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range11w17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range21w27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range31w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range41w47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range51w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range61w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range71w77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range14w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range24w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range34w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range44w49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range54w59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range64w69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range74w79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_aeb_range233w245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_aeb_range237w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_aeb_range241w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range251w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range251w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range254w255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range254w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_eq_grp_range256w263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w304w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_both_inputs_zero_dffe2_wo312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_a_not_zero_dffe1_wo293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_agb_w_dffe2_wo309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_b_not_zero_dffe1_wo294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_w296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_out_aeb_w308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_out_unordered_w302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w304w305w306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range157w158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range163w164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range169w170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range175w176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range181w182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range187w188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range193w194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range199w200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range205w206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range211w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range11w12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range31w32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range41w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range71w72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range160w161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range166w167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range172w173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range178w179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range184w185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range190w191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range196w197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range202w203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range208w209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range24w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range34w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range44w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range64w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range74w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_agb_tmp_w_range265w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_agb_tmp_w_range268w269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_agb_tmp_w_range270w271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_dffe1_wo_range285w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_dffe1_wo_range288w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aligned_dataa_sign_adjusted_dffe2_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_adjusted_dffe2_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_adjusted_w : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_dataa_w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL aligned_datab_sign_adjusted_dffe2_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_adjusted_dffe2_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_adjusted_w : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL aligned_datab_w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL both_inputs_zero : STD_LOGIC;
SIGNAL both_inputs_zero_dffe2_wi : STD_LOGIC;
SIGNAL both_inputs_zero_dffe2_wo : STD_LOGIC;
SIGNAL exp_a_all_one_dffe1_wi : STD_LOGIC;
SIGNAL exp_a_all_one_dffe1_wo : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_dffe1_wi : STD_LOGIC;
SIGNAL exp_a_not_zero_dffe1_wo : STD_LOGIC;
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_aeb : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_aeb_tmp_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_aeb_w : STD_LOGIC;
SIGNAL exp_aeb_w_dffe2_wi : STD_LOGIC;
SIGNAL exp_aeb_w_dffe2_wo : STD_LOGIC;
SIGNAL exp_agb : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_agb_tmp_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL exp_agb_w : STD_LOGIC;
SIGNAL exp_agb_w_dffe2_wi : STD_LOGIC;
SIGNAL exp_agb_w_dffe2_wo : STD_LOGIC;
SIGNAL exp_b_all_one_dffe1_wi : STD_LOGIC;
SIGNAL exp_b_all_one_dffe1_wo : STD_LOGIC;
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_dffe1_wi : STD_LOGIC;
SIGNAL exp_b_not_zero_dffe1_wo : STD_LOGIC;
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_eq_grp : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_eq_gt_grp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL flip_outputs_dffe2_wi : STD_LOGIC;
SIGNAL flip_outputs_dffe2_wo : STD_LOGIC;
SIGNAL flip_outputs_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL man_a_not_zero_dffe1_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_a_not_zero_dffe1_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_a_not_zero_merge_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_dffe1_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_b_not_zero_dffe1_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_b_not_zero_merge_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL out_aeb_w : STD_LOGIC;
SIGNAL out_agb_dffe3_wi : STD_LOGIC;
SIGNAL out_agb_dffe3_wo : STD_LOGIC;
SIGNAL out_agb_w : STD_LOGIC;
SIGNAL out_unordered_w : STD_LOGIC;
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_range237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_tmp_w_range243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_tmp_w_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_aeb_tmp_w_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_range234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_range238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_range242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_tmp_w_range265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_tmp_w_range268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_agb_tmp_w_range270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_grp_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_grp_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_grp_range256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_gt_grp_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_gt_grp_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_eq_gt_grp_range264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_dffe1_wo_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_merge_w_range280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_dffe1_wo_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_merge_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_w_lg_w304w305w(0) <= wire_w304w(0) AND exp_aeb_w_dffe2_wo;
wire_w316w(0) <= wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w(0) AND aligned_datab_sign_adjusted_dffe2_wo;
wire_w_lg_exp_agb_w_dffe2_wo314w(0) <= exp_agb_w_dffe2_wo AND wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w(0);
wire_w_lg_flip_outputs_dffe2_wo310w(0) <= flip_outputs_dffe2_wo AND wire_w_lg_exp_agb_w_dffe2_wo309w(0);
wire_w_lg_w_dataa_range11w17w(0) <= wire_w_dataa_range11w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range21w27w(0) <= wire_w_dataa_range21w(0) AND wire_w_exp_a_all_one_w_range18w(0);
wire_w_lg_w_dataa_range31w37w(0) <= wire_w_dataa_range31w(0) AND wire_w_exp_a_all_one_w_range28w(0);
wire_w_lg_w_dataa_range41w47w(0) <= wire_w_dataa_range41w(0) AND wire_w_exp_a_all_one_w_range38w(0);
wire_w_lg_w_dataa_range51w57w(0) <= wire_w_dataa_range51w(0) AND wire_w_exp_a_all_one_w_range48w(0);
wire_w_lg_w_dataa_range61w67w(0) <= wire_w_dataa_range61w(0) AND wire_w_exp_a_all_one_w_range58w(0);
wire_w_lg_w_dataa_range71w77w(0) <= wire_w_dataa_range71w(0) AND wire_w_exp_a_all_one_w_range68w(0);
wire_w_lg_w_datab_range14w19w(0) <= wire_w_datab_range14w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range24w29w(0) <= wire_w_datab_range24w(0) AND wire_w_exp_b_all_one_w_range20w(0);
wire_w_lg_w_datab_range34w39w(0) <= wire_w_datab_range34w(0) AND wire_w_exp_b_all_one_w_range30w(0);
wire_w_lg_w_datab_range44w49w(0) <= wire_w_datab_range44w(0) AND wire_w_exp_b_all_one_w_range40w(0);
wire_w_lg_w_datab_range54w59w(0) <= wire_w_datab_range54w(0) AND wire_w_exp_b_all_one_w_range50w(0);
wire_w_lg_w_datab_range64w69w(0) <= wire_w_datab_range64w(0) AND wire_w_exp_b_all_one_w_range60w(0);
wire_w_lg_w_datab_range74w79w(0) <= wire_w_datab_range74w(0) AND wire_w_exp_b_all_one_w_range70w(0);
wire_w_lg_w_exp_aeb_range233w245w(0) <= wire_w_exp_aeb_range233w(0) AND wire_w_exp_aeb_tmp_w_range243w(0);
wire_w_lg_w_exp_aeb_range237w247w(0) <= wire_w_exp_aeb_range237w(0) AND wire_w_exp_aeb_tmp_w_range246w(0);
wire_w_lg_w_exp_aeb_range241w249w(0) <= wire_w_exp_aeb_range241w(0) AND wire_w_exp_aeb_tmp_w_range248w(0);
wire_w_lg_w_exp_eq_grp_range251w253w(0) <= wire_w_exp_eq_grp_range251w(0) AND wire_w_exp_aeb_range233w(0);
wire_w_lg_w_exp_eq_grp_range251w259w(0) <= wire_w_exp_eq_grp_range251w(0) AND wire_w_exp_agb_range234w(0);
wire_w_lg_w_exp_eq_grp_range254w255w(0) <= wire_w_exp_eq_grp_range254w(0) AND wire_w_exp_aeb_range237w(0);
wire_w_lg_w_exp_eq_grp_range254w261w(0) <= wire_w_exp_eq_grp_range254w(0) AND wire_w_exp_agb_range238w(0);
wire_w_lg_w_exp_eq_grp_range256w263w(0) <= wire_w_exp_eq_grp_range256w(0) AND wire_w_exp_agb_range242w(0);
wire_w304w(0) <= NOT wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo303w(0);
wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo313w(0) <= NOT aligned_dataa_sign_adjusted_dffe2_wo;
wire_w_lg_both_inputs_zero_dffe2_wo312w(0) <= NOT both_inputs_zero_dffe2_wo;
wire_w_lg_exp_a_not_zero_dffe1_wo293w(0) <= NOT exp_a_not_zero_dffe1_wo;
wire_w_lg_exp_agb_w_dffe2_wo309w(0) <= NOT exp_agb_w_dffe2_wo;
wire_w_lg_exp_b_not_zero_dffe1_wo294w(0) <= NOT exp_b_not_zero_dffe1_wo;
wire_w_lg_input_dataa_zero_w296w(0) <= NOT input_dataa_zero_w;
wire_w_lg_input_datab_zero_w298w(0) <= NOT input_datab_zero_w;
wire_w_lg_out_aeb_w308w(0) <= NOT out_aeb_w;
wire_w_lg_out_unordered_w302w(0) <= NOT out_unordered_w;
wire_w_lg_w_lg_w304w305w306w(0) <= wire_w_lg_w304w305w(0) OR both_inputs_zero_dffe2_wo;
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range157w158w(0) <= wire_w_dataa_range157w(0) OR wire_w_man_a_not_zero_w_range154w(0);
wire_w_lg_w_dataa_range163w164w(0) <= wire_w_dataa_range163w(0) OR wire_w_man_a_not_zero_w_range159w(0);
wire_w_lg_w_dataa_range169w170w(0) <= wire_w_dataa_range169w(0) OR wire_w_man_a_not_zero_w_range165w(0);
wire_w_lg_w_dataa_range175w176w(0) <= wire_w_dataa_range175w(0) OR wire_w_man_a_not_zero_w_range171w(0);
wire_w_lg_w_dataa_range181w182w(0) <= wire_w_dataa_range181w(0) OR wire_w_man_a_not_zero_w_range177w(0);
wire_w_lg_w_dataa_range187w188w(0) <= wire_w_dataa_range187w(0) OR wire_w_man_a_not_zero_w_range183w(0);
wire_w_lg_w_dataa_range193w194w(0) <= wire_w_dataa_range193w(0) OR wire_w_man_a_not_zero_w_range189w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range82w(0);
wire_w_lg_w_dataa_range199w200w(0) <= wire_w_dataa_range199w(0) OR wire_w_man_a_not_zero_w_range195w(0);
wire_w_lg_w_dataa_range205w206w(0) <= wire_w_dataa_range205w(0) OR wire_w_man_a_not_zero_w_range201w(0);
wire_w_lg_w_dataa_range211w212w(0) <= wire_w_dataa_range211w(0) OR wire_w_man_a_not_zero_w_range207w(0);
wire_w_lg_w_dataa_range11w12w(0) <= wire_w_dataa_range11w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range21w22w(0) <= wire_w_dataa_range21w(0) OR wire_w_exp_a_not_zero_w_range13w(0);
wire_w_lg_w_dataa_range31w32w(0) <= wire_w_dataa_range31w(0) OR wire_w_exp_a_not_zero_w_range23w(0);
wire_w_lg_w_dataa_range41w42w(0) <= wire_w_dataa_range41w(0) OR wire_w_exp_a_not_zero_w_range33w(0);
wire_w_lg_w_dataa_range51w52w(0) <= wire_w_dataa_range51w(0) OR wire_w_exp_a_not_zero_w_range43w(0);
wire_w_lg_w_dataa_range61w62w(0) <= wire_w_dataa_range61w(0) OR wire_w_exp_a_not_zero_w_range53w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range71w72w(0) <= wire_w_dataa_range71w(0) OR wire_w_exp_a_not_zero_w_range63w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range160w161w(0) <= wire_w_datab_range160w(0) OR wire_w_man_b_not_zero_w_range156w(0);
wire_w_lg_w_datab_range166w167w(0) <= wire_w_datab_range166w(0) OR wire_w_man_b_not_zero_w_range162w(0);
wire_w_lg_w_datab_range172w173w(0) <= wire_w_datab_range172w(0) OR wire_w_man_b_not_zero_w_range168w(0);
wire_w_lg_w_datab_range178w179w(0) <= wire_w_datab_range178w(0) OR wire_w_man_b_not_zero_w_range174w(0);
wire_w_lg_w_datab_range184w185w(0) <= wire_w_datab_range184w(0) OR wire_w_man_b_not_zero_w_range180w(0);
wire_w_lg_w_datab_range190w191w(0) <= wire_w_datab_range190w(0) OR wire_w_man_b_not_zero_w_range186w(0);
wire_w_lg_w_datab_range196w197w(0) <= wire_w_datab_range196w(0) OR wire_w_man_b_not_zero_w_range192w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range85w(0);
wire_w_lg_w_datab_range202w203w(0) <= wire_w_datab_range202w(0) OR wire_w_man_b_not_zero_w_range198w(0);
wire_w_lg_w_datab_range208w209w(0) <= wire_w_datab_range208w(0) OR wire_w_man_b_not_zero_w_range204w(0);
wire_w_lg_w_datab_range214w215w(0) <= wire_w_datab_range214w(0) OR wire_w_man_b_not_zero_w_range210w(0);
wire_w_lg_w_datab_range14w15w(0) <= wire_w_datab_range14w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range24w25w(0) <= wire_w_datab_range24w(0) OR wire_w_exp_b_not_zero_w_range16w(0);
wire_w_lg_w_datab_range34w35w(0) <= wire_w_datab_range34w(0) OR wire_w_exp_b_not_zero_w_range26w(0);
wire_w_lg_w_datab_range44w45w(0) <= wire_w_datab_range44w(0) OR wire_w_exp_b_not_zero_w_range36w(0);
wire_w_lg_w_datab_range54w55w(0) <= wire_w_datab_range54w(0) OR wire_w_exp_b_not_zero_w_range46w(0);
wire_w_lg_w_datab_range64w65w(0) <= wire_w_datab_range64w(0) OR wire_w_exp_b_not_zero_w_range56w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range74w75w(0) <= wire_w_datab_range74w(0) OR wire_w_exp_b_not_zero_w_range66w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_agb_tmp_w_range265w267w(0) <= wire_w_exp_agb_tmp_w_range265w(0) OR wire_w_exp_eq_gt_grp_range260w(0);
wire_w_lg_w_exp_agb_tmp_w_range268w269w(0) <= wire_w_exp_agb_tmp_w_range268w(0) OR wire_w_exp_eq_gt_grp_range262w(0);
wire_w_lg_w_exp_agb_tmp_w_range270w271w(0) <= wire_w_exp_agb_tmp_w_range270w(0) OR wire_w_exp_eq_gt_grp_range264w(0);
wire_w_lg_w_man_a_not_zero_dffe1_wo_range285w286w(0) <= wire_w_man_a_not_zero_dffe1_wo_range285w(0) OR wire_w_man_a_not_zero_merge_w_range280w(0);
wire_w_lg_w_man_b_not_zero_dffe1_wo_range288w289w(0) <= wire_w_man_b_not_zero_dffe1_wo_range288w(0) OR wire_w_man_b_not_zero_merge_w_range283w(0);
wire_w_lg_aligned_dataa_sign_adjusted_dffe2_wo303w(0) <= aligned_dataa_sign_adjusted_dffe2_wo XOR aligned_datab_sign_adjusted_dffe2_wo;
agb <= out_agb_dffe3_wo;
aligned_dataa_sign_adjusted_dffe2_wi <= aligned_dataa_sign_adjusted_w;
aligned_dataa_sign_adjusted_dffe2_wo <= aligned_dataa_sign_adjusted_dffe2_wi;
aligned_dataa_sign_adjusted_w <= (aligned_dataa_sign_dffe1_wo AND wire_w_lg_input_dataa_zero_w296w(0));
aligned_dataa_sign_dffe1_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe1_wo <= aligned_dataa_sign_dffe1_wi;
aligned_dataa_sign_w <= dataa(31);
aligned_dataa_w <= ( dataa(30 DOWNTO 0));
aligned_datab_sign_adjusted_dffe2_wi <= aligned_datab_sign_adjusted_w;
aligned_datab_sign_adjusted_dffe2_wo <= aligned_datab_sign_adjusted_dffe2_wi;
aligned_datab_sign_adjusted_w <= (aligned_datab_sign_dffe1_wo AND wire_w_lg_input_datab_zero_w298w(0));
aligned_datab_sign_dffe1_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe1_wo <= aligned_datab_sign_dffe1_wi;
aligned_datab_sign_w <= datab(31);
aligned_datab_w <= ( datab(30 DOWNTO 0));
both_inputs_zero <= (input_dataa_zero_w AND input_datab_zero_w);
both_inputs_zero_dffe2_wi <= both_inputs_zero;
both_inputs_zero_dffe2_wo <= both_inputs_zero_dffe2_wi;
exp_a_all_one_dffe1_wi <= exp_a_all_one_w(7);
exp_a_all_one_dffe1_wo <= exp_a_all_one_dffe1_wi;
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range71w77w & wire_w_lg_w_dataa_range61w67w & wire_w_lg_w_dataa_range51w57w & wire_w_lg_w_dataa_range41w47w & wire_w_lg_w_dataa_range31w37w & wire_w_lg_w_dataa_range21w27w & wire_w_lg_w_dataa_range11w17w & dataa(23));
exp_a_not_zero_dffe1_wi <= exp_a_not_zero_w(7);
exp_a_not_zero_dffe1_wo <= exp_a_not_zero_dffe1_wi;
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range71w72w & wire_w_lg_w_dataa_range61w62w & wire_w_lg_w_dataa_range51w52w & wire_w_lg_w_dataa_range41w42w & wire_w_lg_w_dataa_range31w32w & wire_w_lg_w_dataa_range21w22w & wire_w_lg_w_dataa_range11w12w & dataa(23));
exp_aeb <= ( wire_cmpr4_aeb & wire_cmpr3_aeb & wire_cmpr2_aeb & wire_cmpr1_aeb);
exp_aeb_tmp_w <= ( wire_w_lg_w_exp_aeb_range241w249w & wire_w_lg_w_exp_aeb_range237w247w & wire_w_lg_w_exp_aeb_range233w245w & exp_aeb(0));
exp_aeb_w <= exp_aeb_tmp_w(3);
exp_aeb_w_dffe2_wi <= exp_aeb_w;
exp_aeb_w_dffe2_wo <= exp_aeb_w_dffe2_wi;
exp_agb <= ( wire_cmpr4_agb & wire_cmpr3_agb & wire_cmpr2_agb & wire_cmpr1_agb);
exp_agb_tmp_w <= ( wire_w_lg_w_exp_agb_tmp_w_range270w271w & wire_w_lg_w_exp_agb_tmp_w_range268w269w & wire_w_lg_w_exp_agb_tmp_w_range265w267w & exp_eq_gt_grp(0));
exp_agb_w <= exp_agb_tmp_w(3);
exp_agb_w_dffe2_wi <= exp_agb_w;
exp_agb_w_dffe2_wo <= exp_agb_w_dffe2_wi;
exp_b_all_one_dffe1_wi <= exp_b_all_one_w(7);
exp_b_all_one_dffe1_wo <= exp_b_all_one_dffe1_wi;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range74w79w & wire_w_lg_w_datab_range64w69w & wire_w_lg_w_datab_range54w59w & wire_w_lg_w_datab_range44w49w & wire_w_lg_w_datab_range34w39w & wire_w_lg_w_datab_range24w29w & wire_w_lg_w_datab_range14w19w & datab(23));
exp_b_not_zero_dffe1_wi <= exp_b_not_zero_w(7);
exp_b_not_zero_dffe1_wo <= exp_b_not_zero_dffe1_wi;
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range74w75w & wire_w_lg_w_datab_range64w65w & wire_w_lg_w_datab_range54w55w & wire_w_lg_w_datab_range44w45w & wire_w_lg_w_datab_range34w35w & wire_w_lg_w_datab_range24w25w & wire_w_lg_w_datab_range14w15w & datab(23));
exp_eq_grp <= ( wire_w_lg_w_exp_eq_grp_range254w255w & wire_w_lg_w_exp_eq_grp_range251w253w & exp_aeb(0));
exp_eq_gt_grp <= ( wire_w_lg_w_exp_eq_grp_range256w263w & wire_w_lg_w_exp_eq_grp_range254w261w & wire_w_lg_w_exp_eq_grp_range251w259w & exp_agb(0));
flip_outputs_dffe2_wi <= flip_outputs_w;
flip_outputs_dffe2_wo <= flip_outputs_dffe2_wi;
flip_outputs_w <= (aligned_dataa_sign_adjusted_w AND aligned_datab_sign_adjusted_w);
input_dataa_nan_dffe2_wi <= input_dataa_nan_w;
input_dataa_nan_dffe2_wo <= input_dataa_nan_dffe2_wi;
input_dataa_nan_w <= (exp_a_all_one_dffe1_wo AND man_a_not_zero_merge_w(1));
input_dataa_zero_w <= wire_w_lg_exp_a_not_zero_dffe1_wo293w(0);
input_datab_nan_dffe2_wi <= input_datab_nan_w;
input_datab_nan_dffe2_wo <= input_datab_nan_dffe2_wi;
input_datab_nan_w <= (exp_b_all_one_dffe1_wo AND man_b_not_zero_merge_w(1));
input_datab_zero_w <= wire_w_lg_exp_b_not_zero_dffe1_wo294w(0);
man_a_not_zero_dffe1_wi <= ( man_a_not_zero_w(22) & man_a_not_zero_w(11));
man_a_not_zero_dffe1_wo <= man_a_not_zero_dffe1_wi;
man_a_not_zero_merge_w <= ( wire_w_lg_w_man_a_not_zero_dffe1_wo_range285w286w & man_a_not_zero_dffe1_wo(0));
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range211w212w & wire_w_lg_w_dataa_range205w206w & wire_w_lg_w_dataa_range199w200w & wire_w_lg_w_dataa_range193w194w & wire_w_lg_w_dataa_range187w188w & wire_w_lg_w_dataa_range181w182w & wire_w_lg_w_dataa_range175w176w & wire_w_lg_w_dataa_range169w170w & wire_w_lg_w_dataa_range163w164w & wire_w_lg_w_dataa_range157w158w & dataa(12) & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_b_not_zero_dffe1_wi <= ( man_b_not_zero_w(22) & man_b_not_zero_w(11));
man_b_not_zero_dffe1_wo <= man_b_not_zero_dffe1_wi;
man_b_not_zero_merge_w <= ( wire_w_lg_w_man_b_not_zero_dffe1_wo_range288w289w & man_b_not_zero_dffe1_wo(0));
man_b_not_zero_w <= ( wire_w_lg_w_datab_range214w215w & wire_w_lg_w_datab_range208w209w & wire_w_lg_w_datab_range202w203w & wire_w_lg_w_datab_range196w197w & wire_w_lg_w_datab_range190w191w & wire_w_lg_w_datab_range184w185w & wire_w_lg_w_datab_range178w179w & wire_w_lg_w_datab_range172w173w & wire_w_lg_w_datab_range166w167w & wire_w_lg_w_datab_range160w161w & datab(12) & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
out_aeb_w <= (wire_w_lg_w_lg_w304w305w306w(0) AND wire_w_lg_out_unordered_w302w(0));
out_agb_dffe3_wi <= out_agb_w;
out_agb_dffe3_wo <= out_agb_w_dffe3;
out_agb_w <= (((wire_w316w(0) OR (wire_w_lg_exp_agb_w_dffe2_wo314w(0) AND wire_w_lg_both_inputs_zero_dffe2_wo312w(0))) OR (wire_w_lg_flip_outputs_dffe2_wo310w(0) AND wire_w_lg_out_aeb_w308w(0))) AND wire_w_lg_out_unordered_w302w(0));
out_unordered_w <= (input_dataa_nan_dffe2_wo OR input_datab_nan_dffe2_wo);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range157w(0) <= dataa(13);
wire_w_dataa_range163w(0) <= dataa(14);
wire_w_dataa_range169w(0) <= dataa(15);
wire_w_dataa_range175w(0) <= dataa(16);
wire_w_dataa_range181w(0) <= dataa(17);
wire_w_dataa_range187w(0) <= dataa(18);
wire_w_dataa_range193w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range199w(0) <= dataa(20);
wire_w_dataa_range205w(0) <= dataa(21);
wire_w_dataa_range211w(0) <= dataa(22);
wire_w_dataa_range11w(0) <= dataa(24);
wire_w_dataa_range21w(0) <= dataa(25);
wire_w_dataa_range31w(0) <= dataa(26);
wire_w_dataa_range41w(0) <= dataa(27);
wire_w_dataa_range51w(0) <= dataa(28);
wire_w_dataa_range61w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range71w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range160w(0) <= datab(13);
wire_w_datab_range166w(0) <= datab(14);
wire_w_datab_range172w(0) <= datab(15);
wire_w_datab_range178w(0) <= datab(16);
wire_w_datab_range184w(0) <= datab(17);
wire_w_datab_range190w(0) <= datab(18);
wire_w_datab_range196w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range202w(0) <= datab(20);
wire_w_datab_range208w(0) <= datab(21);
wire_w_datab_range214w(0) <= datab(22);
wire_w_datab_range14w(0) <= datab(24);
wire_w_datab_range24w(0) <= datab(25);
wire_w_datab_range34w(0) <= datab(26);
wire_w_datab_range44w(0) <= datab(27);
wire_w_datab_range54w(0) <= datab(28);
wire_w_datab_range64w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range74w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range18w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range28w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range38w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range48w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range58w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range68w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range13w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range23w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range33w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range43w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range53w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range63w(0) <= exp_a_not_zero_w(6);
wire_w_exp_aeb_range233w(0) <= exp_aeb(1);
wire_w_exp_aeb_range237w(0) <= exp_aeb(2);
wire_w_exp_aeb_range241w(0) <= exp_aeb(3);
wire_w_exp_aeb_tmp_w_range243w(0) <= exp_aeb_tmp_w(0);
wire_w_exp_aeb_tmp_w_range246w(0) <= exp_aeb_tmp_w(1);
wire_w_exp_aeb_tmp_w_range248w(0) <= exp_aeb_tmp_w(2);
wire_w_exp_agb_range234w(0) <= exp_agb(1);
wire_w_exp_agb_range238w(0) <= exp_agb(2);
wire_w_exp_agb_range242w(0) <= exp_agb(3);
wire_w_exp_agb_tmp_w_range265w(0) <= exp_agb_tmp_w(0);
wire_w_exp_agb_tmp_w_range268w(0) <= exp_agb_tmp_w(1);
wire_w_exp_agb_tmp_w_range270w(0) <= exp_agb_tmp_w(2);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range20w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range30w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range40w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range50w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range60w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range70w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range16w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range26w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range36w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range46w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range56w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range66w(0) <= exp_b_not_zero_w(6);
wire_w_exp_eq_grp_range251w(0) <= exp_eq_grp(0);
wire_w_exp_eq_grp_range254w(0) <= exp_eq_grp(1);
wire_w_exp_eq_grp_range256w(0) <= exp_eq_grp(2);
wire_w_exp_eq_gt_grp_range260w(0) <= exp_eq_gt_grp(1);
wire_w_exp_eq_gt_grp_range262w(0) <= exp_eq_gt_grp(2);
wire_w_exp_eq_gt_grp_range264w(0) <= exp_eq_gt_grp(3);
wire_w_man_a_not_zero_dffe1_wo_range285w(0) <= man_a_not_zero_dffe1_wo(1);
wire_w_man_a_not_zero_merge_w_range280w(0) <= man_a_not_zero_merge_w(0);
wire_w_man_a_not_zero_w_range82w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range154w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range159w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range165w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range171w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range177w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range183w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range189w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range195w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range201w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range207w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_b_not_zero_dffe1_wo_range288w(0) <= man_b_not_zero_dffe1_wo(1);
wire_w_man_b_not_zero_merge_w_range283w(0) <= man_b_not_zero_merge_w(0);
wire_w_man_b_not_zero_w_range85w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range156w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range162w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range168w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range174w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range180w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range186w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range192w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range198w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range204w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range210w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN out_agb_w_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN out_agb_w_dffe3 <= out_agb_dffe3_wi;
END IF;
END IF;
END PROCESS;
cmpr1 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr1_aeb,
agb => wire_cmpr1_agb,
dataa => aligned_dataa_w(30 DOWNTO 23),
datab => aligned_datab_w(30 DOWNTO 23)
);
cmpr2 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr2_aeb,
agb => wire_cmpr2_agb,
dataa => aligned_dataa_w(22 DOWNTO 15),
datab => aligned_datab_w(22 DOWNTO 15)
);
cmpr3 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_cmpr3_aeb,
agb => wire_cmpr3_agb,
dataa => aligned_dataa_w(14 DOWNTO 7),
datab => aligned_datab_w(14 DOWNTO 7)
);
cmpr4 : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 7
)
PORT MAP (
aeb => wire_cmpr4_aeb,
agb => wire_cmpr4_agb,
dataa => aligned_dataa_w(6 DOWNTO 0),
datab => aligned_datab_w(6 DOWNTO 0)
);
END RTL; --fp_cmp_altfp_compare_v5c
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_cmp IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
agb : OUT STD_LOGIC
);
END fp_cmp;
ARCHITECTURE RTL OF fp_cmp IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT fp_cmp_altfp_compare_v5c
PORT (
aclr : IN STD_LOGIC ;
agb : OUT STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
agb <= sub_wire0;
fp_cmp_altfp_compare_v5c_component : fp_cmp_altfp_compare_v5c
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
agb => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_cmp_inst.vhd FALSE
|
mit
|
a0bcdfe1e660601fbc6342e83e6bae6c
| 0.689563 | 2.241673 | false | false | false | false |
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