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fpga-logi/logi-hard
|
hdl/wishbone/peripherals/logi_wishbone_peripherals_pack.vhd
| 1 | 15,167 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.logi_utils_pack.all ;
package logi_wishbone_peripherals_pack is
type slv16_array is array(natural range <>) of std_logic_vector(15 downto 0);
type slv32_array is array(natural range <>) of std_logic_vector(31 downto 0);
component wishbone_register is
generic(
wb_addr_size : natural := 16; -- Address port size for wishbone
wb_size : natural := 16; -- Data port size for wishbone
nb_regs : natural := 1 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reg_out : out slv16_array(0 to nb_regs-1);
reg_in : in slv16_array(0 to nb_regs-1)
);
end component;
component wishbone_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth;
BURST_SIZE : positive := 4;
B_THRESHOLD : positive := 4;
A_THRESHOLD : positive := 4;
SYNC_LOGIC_INTERFACE : boolean := false
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
write_fifo, read_fifo : in std_logic ;
fifo_input: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
fifo_output : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
read_fifo_empty, read_fifo_full, read_fifo_threshold : out std_logic ;
write_fifo_empty, write_fifo_full, write_fifo_threshold : out std_logic ;
read_fifo_reset, write_fifo_reset : out std_logic
);
end component;
component wishbone_max7219 is
generic(NB_DEVICE : positive := 2;
CLK_DIV : positive := 1024;
wb_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- max7219 signals
DOUT : out std_logic ;
SCLK : out std_logic ;
LOAD : out std_logic
);
end component;
component wishbone_servo is
generic(NB_SERVOS : positive := 2;
wb_size : natural := 16 ; -- Data port size for wishbone
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
failsafe : in std_logic ;
servos : out std_logic_vector(NB_SERVOS-1 downto 0)
);
end component;
component wishbone_pwm is
generic( nb_chan : positive := 3;
wb_addr_size : natural := 16; -- Address port size for wishbone
wb_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
pwm_out : out std_logic_vector(nb_chan-1 downto 0)
);
end component;
component wishbone_interrupt_manager is
generic(NB_INTERRUPT_LINES : positive := 3;
NB_INTERRUPTS : positive := 1;
ADDR_WIDTH : positive := 16;
DATA_WIDTH : positive := 16);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( DATA_WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( DATA_WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
interrupt_lines : out std_logic_vector(0 to NB_INTERRUPT_LINES-1);
interrupts_req : in std_logic_vector(0 to NB_INTERRUPTS-1)
);
end component;
component wishbone_mem is
generic( mem_size : positive := 3;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 -- addr port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic
);
end component;
component wishbone_gpio is
generic(
wb_size : natural := 16
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
gpio: inout std_logic_vector(15 downto 0)
);
end component;
component wishbone_watchdog is
generic(
wb_size : natural := 16; -- Data port size for wishbone
watchdog_timeout_ms : positive := 160;
clock_period_ns : positive := 10
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reset_out : out std_logic
);
end component;
component wishbone_7seg4x is
generic(
wb_size : natural := 16; -- Data port size for wishbone
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end component;
component wishbone_shared_mem is
generic( mem_size : positive := 256;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 ; -- Data port size for wishbone
logic_addr_size : natural := 10 ;
logic_data_size : natural := 16
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Logic signals
write_in : in std_logic ;
addr_in : in std_logic_vector(logic_addr_size-1 downto 0);
data_in : in std_logic_vector(logic_data_size-1 downto 0);
data_out : out std_logic_vector(logic_data_size-1 downto 0)
);
end component;
component wishbone_gps is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
baudrate : positive := 115_200
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
rx_in : in std_logic
);
end component;
component wishbone_ping is
generic( nb_ping : positive := 2;
clock_period_ns : integer := 10
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( 15 downto 0);
wbs_readdata : out std_logic_vector( 15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
ping_io : inout std_logic_vector(nb_ping-1 downto 0 )
);
end component;
component wishbone_led_matrix_ctrl is
generic(wb_size : positive := 16;
clk_div : positive := 10;
nb_panels : positive := 1 ;
bits_per_color : INTEGER RANGE 1 TO 4 := 4 ;
expose_step_cycle : positive := 1910
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
SCLK_OUT : out std_logic ;
BLANK_OUT : out std_logic ;
LATCH_OUT : out std_logic ;
A_OUT : out std_logic_vector(3 downto 0);
R_out : out std_logic_vector(1 downto 0);
G_out : out std_logic_vector(1 downto 0);
B_out : out std_logic_vector(1 downto 0)
);
end component;
component wishbone_pmic is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
sample_rate : positive := 48_000;
sclk_period_ns : positive := 80
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
ss, sck : out std_logic ;
miso : in std_logic
);
end component;
component wishbone_i2c_master is
generic(
wb_size : natural := 16 -- data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
scl, sda : inout std_logic
);
end component;
component wishbone_to_xil_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
WR_FIFO_SIZE : natural := 128;
RD_FIFO_SIZE : natural := 128
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- fifo signals
fifo_rst : out std_logic;
-- write xil_fifo signals
wr_clk : out std_logic ;
dout : out std_logic_vector(15 downto 0);
wr_en : out std_logic ;
full : in std_logic ;
wr_data_count : in std_logic_vector(15 downto 0);
overflow : in std_logic;
-- read xil_fifo signals
rd_clk : out std_logic ;
din : in std_logic_vector(15 downto 0);
rd_en : out std_logic ;
empty : in std_logic ;
rd_data_count : in std_logic_vector(15 downto 0);
underflow : in std_logic
);
end component;
end logi_wishbone_peripherals_pack;
package body logi_wishbone_peripherals_pack is
end logi_wishbone_peripherals_pack;
|
lgpl-3.0
|
762c24a8962904f5884da25cd1242eee
| 0.616338 | 3.318092 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_fifo_dev.vhd
| 2 | 8,466 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth
B_BURST_SIZE : positive := 4;
A_BURST_SIZE : positive := 4;
SYNC_LOGIC_INTERFACE : boolean := false;
AUTO_INC : boolean := false
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
wrB, rdA : in std_logic ; --! logic side fifo control signal
inputB: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
outputA : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
emptyA, fullA, emptyB, fullB, burst_available_B, burst_available_A : out std_logic; --! fifo state signals
fifoA_reset, fifoB_reset : out std_logic
);
end wishbone_fifo;
architecture RTL of wishbone_fifo is
constant address_space_nbit : integer := MAX((nbit(B_BURST_SIZE)+1), 3);
signal fifoA_wr, fifoB_rd, srazA, srazB : std_logic ;
signal fifoA_in, fifoB_out : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_availableA, nb_availableB : unsigned((WIDTH - 1) downto 0 );
signal nb_availableA_latched, nb_availableB_latched : std_logic_vector((WIDTH - 1) downto 0 );
signal data_bus_out_t : std_logic_vector((WIDTH - 1) downto 0);
signal access_addr, access_addr_old : std_logic ;
signal addr_inc : std_logic ;
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
begin
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
fifo_A : dp_fifo -- write from bus, read from logic
generic map(N => SIZE , W => WIDTH, SYNC_RD => SYNC_LOGIC_INTERFACE, SYNC_WR => false)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => srazA ,
wr => fifoA_wr, rd => rdA,
empty => emptyA,
full => fullA ,
data_out => outputA ,
data_in => fifoA_in ,
nb_available => nb_availableA(nbit(SIZE) downto 0)
);
fifo_B : dp_fifo -- read from bus, write from logic
generic map(N => SIZE , W => WIDTH, SYNC_WR => SYNC_LOGIC_INTERFACE, SYNC_RD => AUTO_INC)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => srazB ,
wr => wrB, rd => fifoB_rd,
empty => emptyB,
full => fullB ,
data_out => fifoB_out ,
data_in => inputB ,
nb_available => nb_availableB(nbit(SIZE) downto 0)
);
nb_availableB_latched <= std_logic_vector(nb_availableB) ;
nb_availableA_latched <= std_logic_vector(nb_availableA) ;
nb_availableB((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
nb_availableA((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_availableA_latched) when wbs_address(1 downto 0)= "01" else
( nb_availableB_latched) when wbs_address(1 downto 0)= "10" else
fifoB_out when wbs_address((address_space_nbit-1)) = '1' and wbs_address(1 downto 0)= "11" else -- peek !
(others => '0');
fifo_data <= fifoB_out ;
--wbs_readdata <= control_latched when wbs_address((address_space_nbit-1)) = '1' else
-- fifo_data ;
--
--
--fifoB_rd <= addr_inc when wbs_address((address_space_nbit-1)) = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
-- '0' ;
wbs_readdata <= control_latched when wbs_address((address_space_nbit-1)) = '1' else --data_access = '0' else
fifo_data ;
gen_auto_inc : if AUTO_INC = true generate
fifoB_rd <= addr_inc when data_access = '1' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
end generate ;
gen_no_auto_inc : if AUTO_INC = false generate
fifoB_rd <= '1' when wbs_address((address_space_nbit-1)) = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
end generate ;
fifoA_wr <= '1' when wbs_address((address_space_nbit-1)) = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
srazA <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and wbs_address(address_space_nbit-1) = '1' and wbs_address(1 downto 0) = "01" else
'0' ;
srazB <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and wbs_address(address_space_nbit-1) = '1' and wbs_address(1 downto 0) = "10" else
'0' ;
fifoA_reset <= srazA ;
fifoB_reset <= srazB ;
fifoA_in <= wbs_writedata ;
burst_available_B <= '1' when nb_availableB_latched > B_BURST_SIZE else
'0' ;
burst_available_A <= '1' when nb_availableA_latched > A_BURST_SIZE else
'0' ;
-- Following block takes care of generating reads when the wishbone bus generates burst
access_addr <= wbs_address(0) ;
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
access_addr_old <= '0';
elsif gls_clk'event and gls_clk = '1' then
access_addr_old <= access_addr ;
end if ;
end process ;
addr_inc <= '1' when access_addr /= access_addr_old and read_ack = '1' else
'0' ;
-- Following block takes care of correctly addressing fifo in burst mode.
-- Address can be increase up to the control memory area without losing 2bytes on last read
-- Following block is a RS latch to latch current addressing mode control/data
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
data_access <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if( wbs_strobe = '1' and wbs_cycle = '1' and wbs_address((address_space_nbit-1)) = '0') then
data_access <= '1' ;
elsif (wbs_strobe = '0' or wbs_cycle = '0') then
data_access <= '0' ;
end if ;
end if ;
end process ;
end RTL;
|
lgpl-3.0
|
769bf22865d8127ef4d237db4fecd781
| 0.622254 | 3.151899 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/stratixgx_dpa_lvds_rx/_primary.vhd
| 1 | 1,374 |
library verilog;
use verilog.vl_types.all;
entity stratixgx_dpa_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_coreclock_input: string := "OFF";
enable_dpa_fifo : string := "ON";
registered_output: string := "ON";
REGISTER_WIDTH : vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_slowclk : in vl_logic;
rx_locked : in vl_logic;
rx_coreclk : in vl_logic_vector;
rx_reset : in vl_logic_vector;
rx_dpll_reset : in vl_logic_vector;
rx_channel_data_align: in vl_logic_vector;
rx_out : out vl_logic_vector;
rx_dpa_locked : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of use_coreclock_input : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_fifo : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
end stratixgx_dpa_lvds_rx;
|
bsd-2-clause
|
63264d95530dc2658fbc5a5a7178122a
| 0.605531 | 3.634921 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/ADCS7476_ctrl.vhd
| 2 | 4,818 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:09:59 09/30/2014
-- Design Name:
-- Module Name: ADCS7476_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end ADCS7476_ctrl;
architecture Behavioral of ADCS7476_ctrl is
constant divider_modulo : positive := ((sclk_period_ns/clk_period_ns)/2)-1 ;
constant tick_between_samples : positive := (time_between_sample_ns/sclk_period_ns);
type com_state is (WAIT_SAMPLE, ASSERT_SS, SCLK_LOW, SCLK_HIGH, DEASSERT_SS);
signal cur_state, next_state : com_state ;
signal bit_counter : std_logic_vector(15 downto 0);
signal bit_counter_en, bit_counter_reset : std_logic ;
signal clk_divider : std_logic_vector(15 downto 0);
signal end_divider : std_logic ;
signal shift_in : std_logic ;
signal data_reg : std_logic_vector(15 downto 0);
signal ss_comb, sclk_comb, miso_latched : std_logic ;
begin
process(clk, resetn)
begin
if resetn = '0' then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
elsif clk'event and clk = '1' then
if clk_divider = 0 then
clk_divider <= std_logic_vector(to_unsigned(divider_modulo, 16));
else
clk_divider <= clk_divider - 1 ;
end if ;
end if;
end process ;
end_divider <= '1' when clk_divider = 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
bit_counter <= (others => '0');
elsif clk'event and clk = '1' then
if bit_counter_reset = '1' then
bit_counter <= (others => '0');
elsif bit_counter_en = '1' then
bit_counter <= bit_counter + 1;
end if ;
end if;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
cur_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
cur_state <= next_state;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
data_reg <= (others => '0');
elsif clk'event and clk = '1' then
if shift_in = '1' then
data_reg(15 downto 1) <= data_reg(14 downto 0);
data_reg(0) <= miso_latched ;
end if ;
end if;
end process ;
process(cur_state, bit_counter, end_divider)
begin
next_state <= cur_state ;
case cur_state is
when WAIT_SAMPLE =>
if bit_counter = tick_between_samples and end_divider = '1' then
next_state <= ASSERT_SS ;
end if ;
when ASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when SCLK_LOW =>
if end_divider = '1' then
next_state <= SCLK_HIGH ;
end if ;
when SCLK_HIGH =>
if bit_counter = 15 and end_divider = '1' then
next_state <= DEASSERT_SS ;
elsif end_divider = '1' then
next_state <= SCLK_LOW ;
end if ;
when DEASSERT_SS =>
if bit_counter = 1 and end_divider = '1' then
next_state <= WAIT_SAMPLE ;
end if ;
when others => next_state <= WAIT_SAMPLE ;
end case;
end process ;
with cur_state select
bit_counter_en <= end_divider when SCLK_HIGH,
'0' when SCLK_LOW,
end_divider when others ;
bit_counter_reset <= '1' when cur_state = ASSERT_SS and next_state = SCLK_LOW else
'1' when cur_state = WAIT_SAMPLE and next_state = ASSERT_SS else
'1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'1' when cur_state = DEASSERT_SS and next_state = WAIT_SAMPLE else
'0';
shift_in <= '1' when cur_state = SCLK_LOW and next_state = SCLK_HIGH else
'0' ;
sample_valid <= '1' when cur_state = SCLK_HIGH and next_state = DEASSERT_SS else
'0' ;
sample_out <= data_reg(12 downto 1);
ss_comb <= '1' when cur_state = WAIT_SAMPLE else
'1' when cur_state = DEASSERT_SS else
'0' ;
with cur_state select
sclk_comb <= '0' when SCLK_LOW,
'1' when others ;
process(clk, resetn)
begin
if resetn = '0' then
ss <= '1' ;
sclk <= '1' ;
miso_latched <= '0' ;
elsif clk'event and clk = '1' then
ss <= ss_comb;
sclk <= sclk_comb ;
miso_latched <= miso ;
end if;
end process ;
end Behavioral;
|
lgpl-3.0
|
6cb710f47396ce4ceb010db2469481ca
| 0.636571 | 3.057107 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_32_s6_ste/example_design/afifo_32_s6_top.vhd
| 1 | 19,612 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_32_s6_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_32_s6_top;
architecture xilinx of afifo_32_s6_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_32_s6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_32_s6
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
gpl-3.0
|
1afd575cb0f388c6e757379ea64e14d9
| 0.475117 | 3.96042 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dverif.vhd
| 1 | 5,696 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
gpl-3.0
|
e00b515ef12d5b005c6d0434ea4d9e69
| 0.582338 | 3.99439 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/dcfifo_mixed_widths/_primary.vhd
| 1 | 3,945 |
library verilog;
use verilog.vl_types.all;
entity dcfifo_mixed_widths is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_width_r : vl_notype;
lpm_widthu_r : vl_notype;
lpm_numwords : integer := 2;
delay_rdusedw : integer := 1;
delay_wrusedw : integer := 1;
rdsync_delaypipe: integer := 0;
wrsync_delaypipe: integer := 0;
intended_device_family: string := "Stratix";
lpm_showahead : string := "OFF";
underflow_checking: string := "ON";
overflow_checking: string := "ON";
clocks_are_synchronized: string := "FALSE";
use_eab : string := "ON";
add_ram_output_register: string := "OFF";
lpm_hint : string := "USE_EAB=ON";
lpm_type : string := "dcfifo_mixed_widths";
add_usedw_msb_bit: string := "OFF";
read_aclr_synch : string := "OFF";
write_aclr_synch: string := "OFF";
add_width : integer := 1;
ram_block_type : string := "AUTO";
FAMILY_HAS_STRATIXII_STYLE_RAM: vl_notype;
FAMILY_HAS_STRATIXIII_STYLE_RAM: vl_notype;
WRITE_SIDE_SYNCHRONIZERS: vl_notype;
READ_SIDE_SYNCHRONIZERS: vl_notype
);
port(
data : in vl_logic_vector;
rdclk : in vl_logic;
wrclk : in vl_logic;
aclr : in vl_logic;
rdreq : in vl_logic;
wrreq : in vl_logic;
rdfull : out vl_logic;
wrfull : out vl_logic;
rdempty : out vl_logic;
wrempty : out vl_logic;
rdusedw : out vl_logic_vector;
wrusedw : out vl_logic_vector;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_width : constant is 1;
attribute mti_svvh_generic_type of lpm_widthu : constant is 1;
attribute mti_svvh_generic_type of lpm_width_r : constant is 3;
attribute mti_svvh_generic_type of lpm_widthu_r : constant is 3;
attribute mti_svvh_generic_type of lpm_numwords : constant is 1;
attribute mti_svvh_generic_type of delay_rdusedw : constant is 1;
attribute mti_svvh_generic_type of delay_wrusedw : constant is 1;
attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1;
attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_showahead : constant is 1;
attribute mti_svvh_generic_type of underflow_checking : constant is 1;
attribute mti_svvh_generic_type of overflow_checking : constant is 1;
attribute mti_svvh_generic_type of clocks_are_synchronized : constant is 1;
attribute mti_svvh_generic_type of use_eab : constant is 1;
attribute mti_svvh_generic_type of add_ram_output_register : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of add_usedw_msb_bit : constant is 1;
attribute mti_svvh_generic_type of read_aclr_synch : constant is 1;
attribute mti_svvh_generic_type of write_aclr_synch : constant is 1;
attribute mti_svvh_generic_type of add_width : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXII_STYLE_RAM : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXIII_STYLE_RAM : constant is 3;
attribute mti_svvh_generic_type of WRITE_SIDE_SYNCHRONIZERS : constant is 3;
attribute mti_svvh_generic_type of READ_SIDE_SYNCHRONIZERS : constant is 3;
end dcfifo_mixed_widths;
|
bsd-2-clause
|
af00a837aff4908a19a5f17a3f8bc077
| 0.618758 | 3.785988 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/heart_beat.vhd
| 2 | 2,693 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:36:55 02/19/2014
-- Design Name:
-- Module Name: heart_beat - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity heart_beat is
generic(clk_period_ns : positive := 10;
beat_period_ns : positive := 900_000_000;
beat_length_ns : positive := 100_000_000);
port ( gls_clk : in STD_LOGIC;
gls_reset : in STD_LOGIC;
beat_out : out STD_LOGIC);
end heart_beat;
architecture RTL of heart_beat is
constant period_count : positive := beat_period_ns/clk_period_ns ;
constant beat_count : positive := beat_length_ns/clk_period_ns ;
constant nb_beat : positive := 2 ;
signal cycle_counter : std_logic_vector(1 downto 0);
signal time_counter,load_value : std_logic_vector(nbit(period_count)-1 downto 0);
signal load_counter : std_logic ;
begin
time_count0 : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
time_counter <= std_logic_vector(to_unsigned(period_count, nbit(period_count)));
elsif gls_clk'event and gls_clk = '1' then
if load_counter = '1' then
time_counter <= load_value ;
else
time_counter <= time_counter - 1 ;
end if ;
end if ;
end process ;
load_counter <= '1' when time_counter = 0 else
'0' ;
cycle_count0 : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
cycle_counter <= (others => '0');
elsif gls_clk'event and gls_clk = '1' then
if time_counter = 0 then
cycle_counter <= cycle_counter + 1 ;
end if ;
end if ;
end process ;
with cycle_counter select
load_value <= std_logic_vector(to_unsigned(beat_count, nbit(period_count))) when "00",
std_logic_vector(to_unsigned(beat_count, nbit(period_count))) when "01",
std_logic_vector(to_unsigned(beat_count, nbit(period_count))) when "10",
std_logic_vector(to_unsigned(period_count, nbit(period_count))) when others ;
beat_out <= '1' when cycle_counter = 1 else
'1' when cycle_counter = 3 else
'0' ;
end RTL;
|
lgpl-3.0
|
6798540e3542da2a9fa59e6ab33ddc01
| 0.637208 | 3.296206 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/ID_TB.vhd
| 2 | 5,534 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:49:54 12/19/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/ID_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ID
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ID_TB IS
END ID_TB;
ARCHITECTURE behavior OF ID_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ID
PORT(
clock : IN std_logic;
reset : IN std_logic;
instruction_in : IN std_logic_vector(31 downto 0);
rfile_read_addr3 : IN std_logic_vector(4 downto 0);
rfile_write_addr : IN std_logic_vector(4 downto 0);
rfile_write_data : IN std_logic_vector(31 downto 0);
rfile_write_e : IN std_logic;
forward_data_EX : IN std_logic_vector(31 downto 0);
forward_data_MEMIO : IN std_logic_vector(31 downto 0);
forward_data_WB : IN std_logic_vector(31 downto 0);
forward_addr_EX : IN std_logic_vector(4 downto 0);
forward_addr_MEMIO : IN std_logic_vector(4 downto 0);
forward_addr_WB : IN std_logic_vector(4 downto 0);
ALU_A_to_ID : OUT std_logic_vector(31 downto 0);
ALU_B_to_ID : OUT std_logic_vector(31 downto 0);
EX_control : OUT std_logic_vector(11 downto 0);
load_store_reg_data : OUT std_logic_vector(31 downto 0);
MEMIO_control : OUT std_logic_vector(20 downto 0);
WB_control : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal instruction_in : std_logic_vector(31 downto 0) := (others => '0');
signal rfile_read_addr3 : std_logic_vector(4 downto 0) := (others => '0');
signal rfile_write_addr : std_logic_vector(4 downto 0) := (others => '0');
signal rfile_write_data : std_logic_vector(31 downto 0) := (others => '0');
signal rfile_write_e : std_logic := '0';
signal forward_data_EX : std_logic_vector(31 downto 0) := (others => '0');
signal forward_data_MEMIO : std_logic_vector(31 downto 0) := (others => '0');
signal forward_data_WB : std_logic_vector(31 downto 0) := (others => '0');
signal forward_addr_EX : std_logic_vector(4 downto 0) := (others => '0');
signal forward_addr_MEMIO : std_logic_vector(4 downto 0) := (others => '0');
signal forward_addr_WB : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal ALU_A_to_ID : std_logic_vector(31 downto 0);
signal ALU_B_to_ID : std_logic_vector(31 downto 0);
signal EX_control : std_logic_vector(11 downto 0);
signal load_store_reg_data : std_logic_vector(31 downto 0);
signal MEMIO_control : std_logic_vector(20 downto 0);
signal WB_control : std_logic_vector(5 downto 0);
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ID PORT MAP (
clock => clock,
reset => reset,
instruction_in => instruction_in,
rfile_read_addr3 => rfile_read_addr3,
rfile_write_addr => rfile_write_addr,
rfile_write_data => rfile_write_data,
rfile_write_e => rfile_write_e,
forward_data_EX => forward_data_EX,
forward_data_MEMIO => forward_data_MEMIO,
forward_data_WB => forward_data_WB,
forward_addr_EX => forward_addr_EX,
forward_addr_MEMIO => forward_addr_MEMIO,
forward_addr_WB => forward_addr_WB,
ALU_A_to_ID => ALU_A_to_ID,
ALU_B_to_ID => ALU_B_to_ID,
EX_control => EX_control,
load_store_reg_data => load_store_reg_data,
MEMIO_control => MEMIO_control,
WB_control => WB_control
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
instruction_in <= x"00000000";
rfile_write_e <= '1';
wait for 30 ns;
rfile_write_addr <= b"00001";
rfile_write_data <= x"00000001";
wait for 20 ns;
rfile_write_addr <= b"00010";
rfile_write_data <= x"00000002";
wait for 20 ns;
rfile_write_addr <= b"00011";
rfile_write_data <= x"00000003";
forward_addr_EX <= b"00010";
forward_data_EX <= x"0000000F";
forward_addr_MEMIO <= b"00010";
forward_data_MEMIO <= x"0000000E";
forward_addr_WB <= b"00011";
forward_data_WB <= x"0000000D";
wait for 20 ns;
instruction_in <= b"00100000001000110000000000000111";
wait;
end process;
END;
|
mit
|
4d152aa495217fc6cf0b7a81e9ab7e00
| 0.58764 | 3.452277 | false | false | false | false |
CprE488/Final
|
system/pcores/led_pwm_v1_00_a/hdl/vhdl/user_logic.vhd
| 1 | 37,651 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Nov 19 18:26:09 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic;
led8 : out std_logic;
led9 : out std_logic;
led10 : out std_logic;
led11 : out std_logic;
led12 : out std_logic;
led13 : out std_logic;
led14 : out std_logic;
led15 : out std_logic;
led16 : out std_logic;
led17 : out std_logic;
led18 : out std_logic;
led19 : out std_logic;
led20 : out std_logic;
led21 : out std_logic;
led22 : out std_logic;
led23 : out std_logic;
led24 : out std_logic;
led25 : out std_logic;
led26 : out std_logic;
led27 : out std_logic;
led28 : out std_logic;
led29 : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT clk_prescaler
PORT(
in_clk : IN std_logic;
rst : in STD_LOGIC;
prescaler_value : IN std_logic_vector(4 downto 0);
out_clk : OUT std_logic
);
END COMPONENT;
COMPONENT pwm
PORT(
clk : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
top : IN std_logic_vector(31 downto 0);
duty_cycle : IN std_logic_vector(31 downto 0);
output : OUT std_logic
);
END COMPONENT;
--USER signal declarations added here, as needed for user logic
signal clk_sig : std_logic;
signal rst_sig : std_logic;
signal enable_sig : std_logic;
signal prescaler_value_sig : std_logic_vector(4 downto 0);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal control_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal top_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal duty_cycle_reg_29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
-- Instantiate the Unit Under Test (UUT)
prescaler: clk_prescaler PORT MAP (
in_clk => Bus2IP_Clk,
rst => rst_sig,
prescaler_value => prescaler_value_sig,
out_clk => clk_sig
);
pwm0: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_0,
output => led0
);
pwm1: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_1,
output => led1
);
pwm2: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_2,
output => led2
);
pwm3: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_3,
output => led3
);
pwm4: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_4,
output => led4
);
pwm5: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_5,
output => led5
);
pwm6: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_6,
output => led6
);
pwm7: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_7,
output => led7
);
pwm8: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_8,
output => led8
);
pwm9: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_9,
output => led9
);
pwm10: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_10,
output => led10
);
pwm11: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_11,
output => led11
);
pwm12: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_12,
output => led12
);
pwm13: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_13,
output => led13
);
pwm14: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_14,
output => led14
);
pwm15: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_15,
output => led15
);
pwm16: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_16,
output => led16
);
pwm17: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_17,
output => led17
);
pwm18: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_18,
output => led18
);
pwm19: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_19,
output => led19
);
pwm20: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_20,
output => led20
);
pwm21: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_21,
output => led21
);
pwm22: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_22,
output => led22
);
pwm23: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_23,
output => led23
);
pwm24: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_24,
output => led24
);
pwm25: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_25,
output => led25
);
pwm26: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_26,
output => led26
);
pwm27: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_27,
output => led27
);
pwm28: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_28,
output => led28
);
pwm29: pwm PORT MAP (
clk => clk_sig,
rst => rst_sig,
enable => enable_sig,
top => top_reg,
duty_cycle => duty_cycle_reg_29,
output => led29
);
enable_sig <= control_reg(0);
rst_sig <= control_reg(1) or not Bus2IP_Resetn;
prescaler_value_sig <= control_reg(6 downto 2);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
control_reg <= (others => '0');
top_reg <= (others => '0');
duty_cycle_reg_0 <= (others => '0');
duty_cycle_reg_1 <= (others => '0');
duty_cycle_reg_2 <= (others => '0');
duty_cycle_reg_3 <= (others => '0');
duty_cycle_reg_4 <= (others => '0');
duty_cycle_reg_5 <= (others => '0');
duty_cycle_reg_6 <= (others => '0');
duty_cycle_reg_7 <= (others => '0');
duty_cycle_reg_8 <= (others => '0');
duty_cycle_reg_9 <= (others => '0');
duty_cycle_reg_10 <= (others => '0');
duty_cycle_reg_11 <= (others => '0');
duty_cycle_reg_12 <= (others => '0');
duty_cycle_reg_13 <= (others => '0');
duty_cycle_reg_14 <= (others => '0');
duty_cycle_reg_15 <= (others => '0');
duty_cycle_reg_16 <= (others => '0');
duty_cycle_reg_17 <= (others => '0');
duty_cycle_reg_18 <= (others => '0');
duty_cycle_reg_19 <= (others => '0');
duty_cycle_reg_20 <= (others => '0');
duty_cycle_reg_21 <= (others => '0');
duty_cycle_reg_22 <= (others => '0');
duty_cycle_reg_23 <= (others => '0');
duty_cycle_reg_24 <= (others => '0');
duty_cycle_reg_25 <= (others => '0');
duty_cycle_reg_26 <= (others => '0');
duty_cycle_reg_27 <= (others => '0');
duty_cycle_reg_28 <= (others => '0');
duty_cycle_reg_29 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
control_reg(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
top_reg(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
duty_cycle_reg_29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, control_reg, top_reg, duty_cycle_reg_0, duty_cycle_reg_1, duty_cycle_reg_2, duty_cycle_reg_3, duty_cycle_reg_4, duty_cycle_reg_5, duty_cycle_reg_6, duty_cycle_reg_7, duty_cycle_reg_8, duty_cycle_reg_9, duty_cycle_reg_10, duty_cycle_reg_11, duty_cycle_reg_12, duty_cycle_reg_13, duty_cycle_reg_14, duty_cycle_reg_15, duty_cycle_reg_16, duty_cycle_reg_17, duty_cycle_reg_18, duty_cycle_reg_19, duty_cycle_reg_20, duty_cycle_reg_21, duty_cycle_reg_22, duty_cycle_reg_23, duty_cycle_reg_24, duty_cycle_reg_25, duty_cycle_reg_26, duty_cycle_reg_27, duty_cycle_reg_28, duty_cycle_reg_29 ) is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= control_reg;
when "01000000000000000000000000000000" => slv_ip2bus_data <= top_reg;
when "00100000000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_0;
when "00010000000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_1;
when "00001000000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_2;
when "00000100000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_3;
when "00000010000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_4;
when "00000001000000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_5;
when "00000000100000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_6;
when "00000000010000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_7;
when "00000000001000000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_8;
when "00000000000100000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_9;
when "00000000000010000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_10;
when "00000000000001000000000000000000" => slv_ip2bus_data <= duty_cycle_reg_11;
when "00000000000000100000000000000000" => slv_ip2bus_data <= duty_cycle_reg_12;
when "00000000000000010000000000000000" => slv_ip2bus_data <= duty_cycle_reg_13;
when "00000000000000001000000000000000" => slv_ip2bus_data <= duty_cycle_reg_14;
when "00000000000000000100000000000000" => slv_ip2bus_data <= duty_cycle_reg_15;
when "00000000000000000010000000000000" => slv_ip2bus_data <= duty_cycle_reg_16;
when "00000000000000000001000000000000" => slv_ip2bus_data <= duty_cycle_reg_17;
when "00000000000000000000100000000000" => slv_ip2bus_data <= duty_cycle_reg_18;
when "00000000000000000000010000000000" => slv_ip2bus_data <= duty_cycle_reg_19;
when "00000000000000000000001000000000" => slv_ip2bus_data <= duty_cycle_reg_20;
when "00000000000000000000000100000000" => slv_ip2bus_data <= duty_cycle_reg_21;
when "00000000000000000000000010000000" => slv_ip2bus_data <= duty_cycle_reg_22;
when "00000000000000000000000001000000" => slv_ip2bus_data <= duty_cycle_reg_23;
when "00000000000000000000000000100000" => slv_ip2bus_data <= duty_cycle_reg_24;
when "00000000000000000000000000010000" => slv_ip2bus_data <= duty_cycle_reg_25;
when "00000000000000000000000000001000" => slv_ip2bus_data <= duty_cycle_reg_26;
when "00000000000000000000000000000100" => slv_ip2bus_data <= duty_cycle_reg_27;
when "00000000000000000000000000000010" => slv_ip2bus_data <= duty_cycle_reg_28;
when "00000000000000000000000000000001" => slv_ip2bus_data <= duty_cycle_reg_29;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
gpl-3.0
|
264ad8595bca169d306c943a7d7c4f7d
| 0.514727 | 3.639536 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/dram_fifo.vhd
| 2 | 15,305 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:12:13 10/16/2014
-- Design Name:
-- Module Name: dram_fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
use work.logi_primitive_pack.all ;
entity dram_fifo is
generic(CACHE_SIZE : positive := 2048;
FIFO_SIZE : positive := 16_777_216;
sdram_address_width : positive := 24;
SYNC_READ : boolean := true;
SYNC_WRITE : boolean := true;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- FIFO interface
reset_fifo : in std_logic ;
write_fifo, read_fifo : in std_logic ;
nb_available : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end dram_fifo;
architecture Behavioral of dram_fifo is
type cache_controller_state is (IDLE, REFRESH, FLUSH);
constant CACHE_END_ADDRESS : std_logic_vector(sdram_address_width-2 downto 0) := CACHE_ADDRESS(sdram_address_width-2 downto 0) + (FIFO_SIZE/2);
constant cache_byte_granularity : positive := 256 ;
constant cache_index_low_fifo_side : positive := nbit(cache_byte_granularity)-1;
constant cache_index_low_sdram_side : positive := nbit(cache_byte_granularity)-2;
signal cache_current_state, cache_next_state : cache_controller_state;
signal fifo_write_address, fifo_read_address : std_logic_vector(cache_index_low_fifo_side downto 0);
signal sdram_write_address, sdram_read_address : std_logic_vector(sdram_address_width-2 downto 0);
signal cache_write_address, cache_read_address : std_logic_vector(cache_index_low_sdram_side downto 0);
signal cache_out, cache_in : std_logic_vector(31 downto 0);
signal cache_require_refresh, cache_require_flush : std_logic ;
signal cache_counter : std_logic_vector(6 downto 0);
signal cache_ready : std_logic ;
signal write_fifo_index, read_fifo_index : std_logic ;
signal refresh_done, flush_done, cache_require_flush_reset, cache_require_refresh_reset : std_logic ;
signal old_write_line_index, old_read_line_index : std_logic ;
signal write_fifo_write, write_cache_write : std_logic ;
signal fifo_wr, fifo_rd : std_logic ;
signal rd_old, wr_old, wr_data, rd_data, one_turn, latch_data : std_logic ;
signal rd_rising_edge, wr_rising_edge : std_logic ;
signal rd_falling_edge, wr_falling_edge : std_logic ;
signal fifo_nb_available_t : std_logic_vector(31 downto 0);
signal fifo_ready : std_logic ;
signal flushed_line_count : std_logic_vector(15 downto 0);
signal read_cache_init : std_logic_vector(1 downto 0);
begin
refresh_active <= '1' when cache_current_state = REFRESH else
'0' ;
flush_active <= '1' when cache_current_state = FLUSH else
'0' ;
cmd_byte_enable <= (others => '1');
-- CACHE MANAGEMENT
process(clk, reset)
begin
if reset = '1' then
cache_current_state <= IDLE; -- CACHE init state is IDLE
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
cache_current_state <= IDLE;
else
cache_current_state <= cache_next_state;
end if ;
end if ;
end process ;
process(cache_ready, cache_require_refresh, cache_require_flush, refresh_done, flush_done, cache_current_state)
begin
cache_next_state <= cache_current_state ;
case cache_current_state is
when IDLE =>
if cache_require_refresh = '1' and cache_ready = '1' then
cache_next_state <= REFRESH ; -- CACHE can only be refreshed if already flushed onces
elsif cache_require_flush = '1' then
cache_next_state <= FLUSH ;
end if ;
when REFRESH =>
if refresh_done = '1' then
cache_next_state <= IDLE ;
end if ;
when FLUSH =>
if flush_done = '1' then
cache_next_state <= IDLE ;
end if ;
when others =>
cache_next_state <= IDLE ;
end case ;
end process ;
-- CACHE REFRESH/FLUSH STRATEGY
process(clk, reset)
begin
if reset = '1' then
cache_ready <= '0' ;
cache_require_refresh <= '0' ;
cache_require_flush <= '0';
write_fifo_index <= '0';
read_fifo_index <= '0';
fifo_ready <= '0' ;
read_cache_init <= "11";
elsif clk'event and clk = '1' then
-- CACHE IS FLUSHED WHENEVER THE FIFO_INDEX BIT CHANGES
if reset_fifo = '1' then
cache_require_flush <= '0';
elsif cache_require_flush_reset = '1' then
cache_require_flush <= '0';
elsif write_fifo_index /= fifo_write_address(fifo_write_address'high) then
cache_require_flush <= '1'; -- CACHE require flush when one line of cache was written
-- fifo write address highest byte indicate cache line address
end if ;
write_fifo_index <= fifo_write_address(fifo_write_address'high) ;
-- CACHE IS REFRESHED ONCE TWICE AND THEN
-- WHENEVER THE FIFO_INDEX BIT CHANGES
if reset_fifo = '1' then
read_cache_init <= "11"; -- at reset init indicates that cache can be refreshed twice
cache_require_refresh <= '0' ;
elsif cache_require_refresh_reset = '1' then -- a refresh was performed
cache_require_refresh <= '0';
read_cache_init(1) <= '0' ;
read_cache_init(0) <= read_cache_init(1) ;
elsif read_cache_init /= 0 and flushed_line_count > 0 then -- a refresh is required as init of cache was not performed
cache_require_refresh <= '1';
elsif read_cache_init = 0 and read_fifo_index /= fifo_read_address(fifo_read_address'high) and flushed_line_count > 0 then
cache_require_refresh <= '1'; -- normal case to trigger a refresh. One line of cache was fully consumed
end if ;
read_fifo_index <= fifo_read_address(fifo_read_address'high) ;
-- CACHE IS CONSIDERED READY WHEN IT WAS ONCE FLUSHED AND REFRESHED
-- THIS LIMIT GRANULARITY OF FIFO
if reset_fifo = '1' then
cache_ready <= '0' ;
elsif cache_current_state = FLUSH and cache_next_state = IDLE then
cache_ready <= '1' ;
end if ;
--TODO: decide when cache is not ready anymore ...
-- FIFO IS CONSIDERED READY WHEN IT WAS ONCE REFRESHED
-- THIS LIMIT GRANULARITY OF FIFO
if reset_fifo = '1' then
fifo_ready <= '0' ;
elsif cache_current_state = REFRESH and cache_next_state = IDLE then
fifo_ready <= '1' ;
elsif fifo_ready = '1' and fifo_nb_available_t = 0 then
fifo_ready <= '0' ;-- fifo is fully empty the cache is not ready anymore
end if ;
end if ;
end process ;
-- SDRAM WRITE ADDRESS IS INCREMENTED WHEN CACHE IS FLUSHED
-- END OF FLUSH IS REACHED WHEN THE CACHE_LINE_INDEX CHANGES
process(clk, reset)
begin
if reset = '1' then
sdram_write_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0);
old_write_line_index <= '0' ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
sdram_write_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0) ;
elsif cache_current_state = FLUSH and cmd_ready = '1' then --incrementing on falling edge of ready signal
if sdram_write_address = CACHE_END_ADDRESS then
sdram_write_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0) ;
else
sdram_write_address <= sdram_write_address + 1 ;
end if ;
end if ;
if reset_fifo = '1' then
old_write_line_index <= '0' ;
else
old_write_line_index <= sdram_write_address(cache_index_low_sdram_side);
end if ;
end if ;
end process ;
cache_read_address <= sdram_write_address(cache_read_address'high downto 0);
flush_done <= '1' when cache_current_state = FLUSH and old_write_line_index /= sdram_write_address(cache_index_low_sdram_side) else
'0' ;
cache_require_flush_reset <= '1' when cache_current_state = FLUSH and cache_next_state=IDLE else
'0' ;
-- SDRAM_READ_ADDRESS IS INCREMENTED ON REFRESH UNTIL THE CACHE_LINE_INDEX CHANGES
process(clk, reset)
begin
if reset = '1' then
sdram_read_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0);
cache_write_address <= (others => '0');
old_read_line_index <= '0' ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
sdram_read_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0);
elsif cache_current_state = REFRESH and refresh_done = '0' and cmd_ready = '1' and cache_write_address(cache_write_address'high) = sdram_read_address(cache_write_address'high) then
if sdram_read_address = CACHE_END_ADDRESS then
sdram_read_address <= CACHE_ADDRESS(sdram_address_width-2 downto 0) ;
else
sdram_read_address <= sdram_read_address + 1 ;
end if ;
end if ;
-- CACHE_WRITE_ADDRESS IS ONLY INCREMENT WHEN SDRAM PIPELINE IS INITIALIZED
if reset_fifo = '1' then
cache_write_address <= (others => '0');
elsif cache_current_state = REFRESH and sdram_data_ready = '1' then
cache_write_address <= cache_write_address + 1 ;
end if ;
if reset_fifo = '1' then
old_read_line_index <= '0' ;
else
old_read_line_index <= cache_write_address(cache_write_address'high);
end if ;
end if ;
end process ;
refresh_done <= '1' when cache_current_state = REFRESH and old_read_line_index /= cache_write_address(cache_write_address'high) else
'0';
write_cache_write <= '1' when cache_current_state = REFRESH and sdram_data_ready = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
flushed_line_count <= (others => '0');
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
flushed_line_count <= (others => '0');
elsif refresh_done = '1' and flushed_line_count > 0 then
flushed_line_count <= flushed_line_count - 1;
elsif flush_done = '1' then
flushed_line_count <= flushed_line_count + 1;
end if ;
end if ;
end process ;
cache_require_refresh_reset <= '1' when cache_current_state = REFRESH and cache_next_state=IDLE else
'0' ;
---- WRITE COMMAND IS ACTIVE ON FLUSH
--cmd_wr <= cmd_ready when cache_current_state = FLUSH else
cmd_wr <= '1' when cache_current_state = FLUSH else
'0' ;
---- CMD_ENABLE IS ACTIVE ON FLUSH AND ON REFRESH UNTIL THE SDRAM_READ_ADDRESS INDICATING CACHE_LINE_INDEX
---- CHANGES
---- THIS SEEMS TO AFFECT TIMING ...
cmd_enable <= '0' when cache_current_state = IDLE else
'1' when cache_current_state = REFRESH and cache_write_address(cache_write_address'high) = sdram_read_address(cache_write_address'high) else
'1' when cache_current_state = FLUSH else
'0';
----CMD_ADDRESS IS EITHER READ_ADDRESS OR WRITE_ADDRESS DEPENDING ON FLUSH OR REFRESH
---- THIS SEEMS TO AFFECT TIMING ...
with cache_current_state select
cmd_address <= sdram_write_address when FLUSH,
sdram_read_address when REFRESH,
(others => '0') when others ;
cache_in <= sdram_data_out ;
cmd_data_in <= cache_out ;
-- CACHE ARE INSTANTIATED IN NEXT SECTION
-- write cache is divided into two lines
-- one line is always available for write, and one line is always available
-- to be flushed to SDRAM
write_cache : tdp_bram
generic map(
DATA_A => 16,
ADDR_A => 8,
DATA_B => 32,
ADDR_B => 7
)
port map(
-- Port A
a_clk => clk,
a_wr => write_fifo_write,
a_addr => fifo_write_address,
a_din => data_in,
a_dout => open,
-- Port B
b_clk => clk,
b_wr => '0',
b_addr => cache_read_address,
b_din => (others => '0'),
b_dout => cache_out
);
-- read cache is divided into two lines
-- one line is always available for read, and one line is always available
--for refresh
read_cache : tdp_bram
generic map(
DATA_A => 16,
ADDR_A => 8,
DATA_B => 32,
ADDR_B => 7
)
port map(
-- Port A
a_clk => clk,
a_wr => '0',
a_addr => fifo_read_address,
a_din => (others => '0'),
a_dout => data_out,
-- Port B
b_clk => clk,
b_wr => write_cache_write,
b_addr => cache_write_address,
b_din => cache_in,
b_dout => open
);
-- HERE STARTS FIFO STRUCTURE
gen_async_rd : if NOT SYNC_READ generate
process(reset, clk)
begin
if reset = '1' then
rd_old <= '0' ;
elsif clk'event and clk = '1' then
rd_old <= read_fifo ;
end if ;
end process ;
rd_falling_edge <= ((NOT read_fifo) AND rd_old);
fifo_rd <= rd_falling_edge ;
end generate ;
gen_sync_rd : if SYNC_READ generate
fifo_rd <= read_fifo;
end generate ;
gen_async_wr : if NOT SYNC_WRITE generate
process(reset, clk)
begin
if reset = '1' then
wr_old <= '0' ;
elsif clk'event and clk = '1' then
wr_old <= write_fifo ;
end if ;
end process ;
wr_falling_edge <= ((NOT write_fifo) AND wr_old) ;
fifo_wr <= wr_falling_edge ;
end generate ;
gen_sync_wr : if SYNC_WRITE generate
fifo_wr <= write_fifo ;
end generate ;
write_fifo_write <= fifo_wr ;
--rd process
process(clk, reset)
begin
if reset = '1' then
fifo_read_address <= (others => '0') ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
fifo_read_address <= (others => '0') ;
elsif fifo_rd = '1' and fifo_nb_available_t /= 0 then
fifo_read_address <= fifo_read_address + 1;
end if ;
end if ;
end process ;
-- wr process
process(clk, reset)
begin
if reset = '1' then
fifo_write_address <= (others => '0') ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
fifo_write_address <= (others => '0') ;
elsif fifo_wr = '1' and fifo_nb_available_t /= FIFO_SIZE then
fifo_write_address <= fifo_write_address + 1;
end if ;
end if ;
end process ;
-- nb available process
process(clk, reset)
begin
if reset = '1' then
fifo_nb_available_t <= (others => '0') ;
elsif clk'event and clk = '1' then
if reset_fifo = '1' then
fifo_nb_available_t <= (others => '0') ;
elsif fifo_wr = '1' and fifo_rd = '0' and fifo_nb_available_t /= FIFO_SIZE then
fifo_nb_available_t <= fifo_nb_available_t + 1 ;
elsif fifo_rd = '1' and fifo_wr = '0' and fifo_nb_available_t /= 0 then
fifo_nb_available_t <= fifo_nb_available_t - 1 ;
end if ;
end if ;
end process ;
nb_available <= fifo_nb_available_t when fifo_ready = '1' else
(others => '0');
end Behavioral;
|
lgpl-3.0
|
2b5a0507d14176eb08904625405a6773
| 0.650506 | 3.149825 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/UartLogic.vhd
| 1 | 4,866 |
-------------------------------------------------------
-- Design Name : UartLogic
-- File Name : UartLogic.vhd
-- Function : Simple UART
-- Coder : Credit to Deepak Kumar Tala (Verilog)
-- Translator : and Alexander H Pham (VHDL)
-- Updated : Zachary Hitchcock(For Project 2 Application)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity UartLogic is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
tx_out :out std_logic;
tx_empty :out std_logic;
----------------------------------------------------
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic);
end UartLogic;
architecture rtl of UartLogic is
signal tx_reg :std_logic_vector (7 downto 0);
signal tx_is_empty :std_logic;
signal tx_over_run :std_logic;
signal tx_cnt :std_logic_vector (3 downto 0);
signal rx_reg :std_logic_vector (7 downto 0);
signal rx_sample_cnt :std_logic_vector (3 downto 0);
signal rx_cnt :std_logic_vector (3 downto 0);
signal rx_frame_err :std_logic;
signal rx_over_run :std_logic;
signal rx_d1 :std_logic;
signal rx_d2 :std_logic;
signal rx_busy :std_logic;
signal rx_is_empty :std_logic;
begin
rx_empty <= rx_is_empty;
tx_empty <= tx_is_empty;
-- UART RX Logic --------------------------------------------------------------
process (rxclk, reset) begin
if (reset = '1') then
rx_reg <= (others=>'0');
rx_data <= (others=>'0');
rx_sample_cnt <= (others=>'0');
rx_cnt <= (others=>'0');
rx_frame_err <= '0';
rx_over_run <= '0';
rx_is_empty <= '1';
rx_d1 <= '1';
rx_d2 <= '1';
rx_busy <= '0';
elsif (rising_edge(rxclk)) then
-- Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
-- Uload the rx data
if (uld_rx_data = '1') then
rx_data <= rx_reg;
rx_is_empty <= '1';
end if;
-- Receive data only when rx is enabled
if (rx_enable = '1') then
-- Check if just received start of frame
if (rx_busy = '0' and rx_d2 = '0') then
rx_busy <= '1';
rx_sample_cnt <= X"1";
rx_cnt <= X"0";
end if;
-- Start of frame detected, Proceed with rest of data
if (rx_busy = '1') then
rx_sample_cnt <= rx_sample_cnt + 1;
-- Logic to sample at middle of data
if (rx_sample_cnt = 7) then
if ((rx_d2 = '1') and (rx_cnt = 0)) then
rx_busy <= '0';
else
rx_cnt <= rx_cnt + 1;
-- Start storing the rx data
if (rx_cnt > 0 and rx_cnt < 9) then
rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
end if;
if (rx_cnt = 9) then
rx_busy <= '0';
-- Check if End of frame received correctly
if (rx_d2 = '0') then
rx_frame_err <= '1';
else
rx_is_empty <= '0';
rx_frame_err <= '0';
-- Check if last rx data was not unloaded,
if (rx_is_empty = '1') then
rx_over_run <= '0';
else
rx_over_run <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
if (rx_enable = '0') then
rx_busy <= '0';
end if;
end if;
end process;
-- UART TX Logic -----------------------------------------------------------------------
process (txclk, reset) begin
if (reset = '1') then
tx_reg <= (others=>'0');
tx_is_empty <= '1';
tx_over_run <= '0';
tx_out <= '1';
tx_cnt <= (others=>'0');
elsif (rising_edge(txclk)) then
if (ld_tx_data = '1') then
if (tx_is_empty = '0') then
tx_over_run <= '0';
else
tx_reg <= tx_data;
tx_is_empty <= '0';
end if;
end if;
if (tx_enable = '1' and tx_is_empty = '0') then
tx_cnt <= tx_cnt + 1;
if (tx_cnt = 0) then
tx_out <= '0';
end if;
if (tx_cnt > 0 and tx_cnt < 9) then
tx_out <= tx_reg(conv_integer(tx_cnt) -1);
end if;
if (tx_cnt = 9) then
tx_out <= '1';
tx_cnt <= X"0";
tx_is_empty <= '1';
end if;
end if;
if (tx_enable = '0') then
tx_cnt <= X"0";
end if;
end if;
end process;
end architecture;
|
mit
|
56e5bf6f10b051516bb538ef74b6218b
| 0.453966 | 3.19082 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE1-SoC/DE1_SoC_TRDB_D5M_LT24_top_level.vhd
| 1 | 7,056 |
-- #############################################################################
-- DE1_SoC_TRDB_D5M_LT24_top_level.vhd
-- ===================================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.8
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_TRDB_D5M_LT24_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic;
-- GPIO_1
GPIO_1_LT24_ADC_BUSY : in std_logic;
GPIO_1_LT24_ADC_CS_N : out std_logic;
GPIO_1_LT24_ADC_DCLK : out std_logic;
GPIO_1_LT24_ADC_DIN : out std_logic;
GPIO_1_LT24_ADC_DOUT : in std_logic;
GPIO_1_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_1_LT24_CS_N : out std_logic;
GPIO_1_LT24_D : out std_logic_vector(15 downto 0);
GPIO_1_LT24_LCD_ON : out std_logic;
GPIO_1_LT24_RD_N : out std_logic;
GPIO_1_LT24_RESET_N : out std_logic;
GPIO_1_LT24_RS : out std_logic;
GPIO_1_LT24_WR_N : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_TRDB_D5M_LT24_top_level;
architecture rtl of DE1_SoC_TRDB_D5M_LT24_top_level is
begin
end;
|
unlicense
|
0e1984f1911195cb2127c347b26acfbc
| 0.509779 | 3.081223 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/component/Shifter.vhd
| 1 | 3,766 |
----------------------------------------
-- ?g BIT SHIFTER --
-- PORT MAPPING --
-- A: ?g bit input value --
-- FUN: 3 bit input function selector --
-- 0 - PASS --
-- 1 - LEFT --
-- 2 - RIGHT --
-- 3 - ARITHMETIC LEFT --
-- 4 - ARITHMETIC RIGHT --
-- 5 - ROTATE LEFT --
-- 6 - ROTATE RIGHT --
-- 7 - --
-- 8 - --
----------------------------------------
-- C: ?g bit output value --
-- STATUS: 4 bit status output --
-- 0 - ZERO --
-- 1 - NOOP --
-- 2 - SIGN --
-- 3 - OVERFLOW --
----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY shifter IS
PORT
(
in_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_fun : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
---------------------------------------------------------------
out_c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END shifter;
ARCHITECTURE behavioral OF shifter IS
SIGNAL s_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_status : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(in_fun, in_a, s_out)
BEGIN
CASE(in_fun) IS
-- PASS
WHEN "000" =>
s_out <= in_a;
s_status <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, s_status'LENGTH));
-- LEFT
WHEN "001" =>
s_out <= STD_LOGIC_VECTOR(SHIFT_LEFT(UNSIGNED(in_a), 1));
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
IF(in_a(31) = '1') THEN
s_status(3) <= '1';
ELSE
s_status(3) <= '0';
END IF;
-- RIGHT
WHEN "010" =>
s_out <= STD_LOGIC_VECTOR(SHIFT_RIGHT(UNSIGNED(in_a), 1));
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- A LEFT
WHEN "011" =>
s_out <= STD_LOGIC_VECTOR(SHIFT_LEFT(SIGNED(in_a), 1));
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
IF(in_a(31) = '1') THEN
s_status(3) <= '1';
ELSE
s_status(3) <= '0';
END IF;
-- A RIGHT
WHEN "100" =>
s_out <= STD_LOGIC_VECTOR(SHIFT_RIGHT(SIGNED(in_a), 1));
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- R LEFT
WHEN "101" =>
s_out <= STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(in_a), 1));
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- R RIGHT
WHEN "110" =>
s_out <= STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(in_a), 1));
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
WHEN OTHERS =>
s_out <= in_a;
s_status <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, s_status'LENGTH));
END CASE;
END PROCESS;
out_c <= s_out;
out_status <= s_status;
END behavioral;
|
mit
|
1b170f5a682ed8ea3cd4c1aaf5b62eda
| 0.427775 | 2.903624 | false | false | false | false |
a4a881d4/ringbus
|
simio/daemulator.vhd
| 1 | 854 |
-- This unit is a DAemulator
-- The outout will be writen to a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity DAemulator is
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' ));
end DAemulator;
architecture simulation of DAemulator is
begin
process(clk)
variable idata:integer:=0;
FILE data_file: TEXT IS OUT DA_FILE;
variable buf:line;
begin
if clk'event and clk='1' then
if ce='1' then
idata:=CONV_INTEGER(unsigned(data));
WRITE(buf,hex_to_str(idata),right,8);
WRITELINE(data_file,buf);
end if;
end if;
end process;
end simulation;
|
lgpl-3.0
|
3e7f39e1f8565719f57bd7f17ccd8961
| 0.653396 | 2.904762 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab8_new/lab8_new_lib/hdl/SimpleMux4_Behavior.vhd
| 1 | 1,047 |
--
-- VHDL Architecture lab8_new_lib.SimpleMux4.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 15:40:39 04/ 1/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
--
-- VHDL Architecture lab8_new_lib.SimpleMux3.Behavior
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY SimpleMux4 IS
GENERIC(width: POSITIVE := 16);
PORT( Data_In_0, Data_In_1, Data_In_2, Data_In_3: IN std_logic_vector(width-1 downto 0);
Data_Out: OUT std_logic_vector(width-1 downto 0);
mux_control: IN std_logic_vector(1 downto 0) );
END ENTITY SimpleMux4;
--
ARCHITECTURE Behavior OF SimpleMux4 IS
BEGIN
PROCESS(all)
BEGIN
CASE mux_control IS
when "00" => Data_Out <= Data_In_0;
when "01" => Data_Out <= Data_In_1;
when "10" => Data_Out <= Data_In_2;
when "11" => Data_Out <= Data_In_3;
when others => Data_Out <= (others=>'X');
END CASE;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
47a415608fb07475de49101b88bda92e
| 0.601719 | 3.134731 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/t80/t80_pack.vhd
| 1 | 8,735 |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package t80_pack is
component t80
generic(
t80mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component t80_reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component t80_mcode
generic(
t80mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component t80_alu
generic(
t80mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
|
gpl-2.0
|
70dda5a4ad25a28de0fff7fcad6e01b1
| 0.510361 | 3.938233 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab8_new/lab8_new_lib/hdl/SimpleMux3_Behavior.vhd
| 1 | 918 |
--
-- VHDL Architecture lab8_new_lib.SimpleMux3.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 15:08:24 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY SimpleMux3 IS
GENERIC(width: POSITIVE := 16);
PORT( Data_In_0, Data_In_1, Data_In_2: IN std_logic_vector(width-1 downto 0);
Data_Out: OUT std_logic_vector(width-1 downto 0);
mux_control: IN std_logic_vector(1 downto 0) );
END ENTITY SimpleMux3;
--
ARCHITECTURE Behavior OF SimpleMux3 IS
BEGIN
PROCESS(all)
BEGIN
CASE mux_control IS
when "00" => Data_Out <= Data_In_0;
when "01" => Data_Out <= Data_In_1;
when "10" => Data_Out <= Data_In_2;
when others => Data_Out <= (others=>'X');
END CASE;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
a9f35b01f88e2bcc20c055da8e4880e5
| 0.610022 | 3.165517 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/pixel_ram.vhd
| 1 | 2,138 |
-- Pixel RAM for Konami Arcade Emulator
-- (C) Copyright 2011, 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
--
-- Adapted from Xilinx "XST User's Guide" 10.1, "Dual-Port RAM with
-- Synchronous Read"
-- ________
-- / \
-- DPRA --| |
-- WE --| |
-- DI --| |-- DPO
-- A --| |
-- CLK --|> |
-- \________/
--
-- DPRA = Dual Port Read Address
-- WE = Write Enable
-- DI = Data Input
-- A = Write Address
-- CLK = Positive-Edge (write) Clock
-- DPO = Dual Port Output
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pixel_ram is
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(8 downto 0);
dpra : in std_logic_vector(8 downto 0);
di : in std_logic_vector(4 downto 0);
dpo : out std_logic_vector(4 downto 0));
end entity pixel_ram;
architecture syn of pixel_ram is
type pixel_ram_type is array (511 downto 0) of std_logic_vector(4 downto 0);
signal RAM : pixel_ram_type;
signal reg_dpra : std_logic_vector(8 downto 0);
begin -- syn
process (clk)
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if (we = '1') then
RAM(to_integer(unsigned(a))) <= di;
end if;
reg_dpra <= dpra;
end if;
end process;
dpo <= RAM(to_integer(unsigned(reg_dpra)));
end syn;
|
gpl-2.0
|
4f5655124888351ac992e17ee10c147c
| 0.616464 | 3.516447 | false | false | false | false |
arcade-lab/uarch-phases
|
src/lib/tracing/ahb_rate_trace.vhd
| 1 | 8,016 |
------------------------------------------------------------------------------
-- This file is part of an extension to the GRLIB VHDL IP library.
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
-- Copyright (C) 2013, System Level Design (SLD) group @ Columbia University
--
-- GRLIP is a Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Entity: ahb_rate_trace
-- File: ahb_rate_trace.vhd
-- Authors: Paolo Mantovani - SLD @ Columbia University
-- Van Bui - ARCADE @ Columbia University
-- Description: Amba 2.0 AHB Slave to Network Interface wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
use STD.textio.all;
use ieee.std_logic_textio.all;
--pragma translate_on
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.genacc.all;
library sld;
use sld.tracing.all;
entity ahb_rate_trace is
generic (
tech : integer := virtex7;
hindex : integer range 0 to NAHBSLV-1 := 5;
hmask : integer := 16#ffc#;
haddr : integer := 16#b00#;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ipreg : in ipreg_out_type;
ahbso : out ahb_slv_out_type
);
end ahb_rate_trace;
architecture rtl of ahb_rate_trace is
-- We are interested in a period of time of roughly 2^30 cycles
-- and we try to compute the derivative of the # of DRAM accesses
-- every 2^14 cycles. We need a 2^16 words memory.
signal memout : std_logic_vector(MEM_BITS - 1 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal mem_selected : std_logic_vector(AHB_BITS-1 downto 0);
signal sram_input : std_logic_vector((MEM_BITS -1) downto 0);
signal rden : std_ulogic;
signal rdaddr : std_logic_vector((MEM_SIZE_LOG-1) downto 0);
signal sw : softsigs;
signal rate, rate_next : std_logic_vector(MEM_SIZE_LOG - 1 downto 0);
signal activity, activity_next : std_logic_vector(ACTIVITY_BITS-1 downto 0);
signal count, count_next : std_logic_vector(COUNT_BITS - 1 downto 0);
signal log : std_ulogic;
signal full_log : std_ulogic;
signal sample : std_ulogic;
signal irq : std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_SLD, SLD_RATE_TRACE, 0, 0, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
begin -- rtl
-----------------------------------------------------------------------------
-- SRAMS interface
-----------------------------------------------------------------------------
syncram_dp_1: syncram_dp_wrapper
generic map (
tech => tech,
pirq => pirq)
port map (
rst => rst,
clk => clk,
rdaddr => rdaddr,
rden => rden,
packsigs => sram_input,
sample => sample,
reset_log => sw.reset_stats,
stop_log => sw.dump_stats,
full_log => full_log,
memout => memout,
irq => irq);
-----------------------------------------------------------------------------
-- Pack pipeline signals
-----------------------------------------------------------------------------
packer_1 : packer
port map(
rst => rst,
clk => clk,
ipreg => ipreg,
mem_selected => mem_selected,
activity => activity,
packsigs => sram_input);
-----------------------------------------------------------------------------
-- Memory access detection
-----------------------------------------------------------------------------
detect_mem_access_1 : detect_mem_access
port map (
ahbsi => ahbsi,
mem_selected => mem_selected);
-----------------------------------------------------------------------------
-- AHB signal handler
-----------------------------------------------------------------------------
decode_address: process (ahbsi, rden, rate, activity)
variable haddr : std_logic_vector(31 downto 0);
begin -- process address_decoder
haddr := "00" & ahbsi.haddr(31 downto 2);
haddr := haddr_mask and haddr;
rdaddr <= haddr(MEM_SIZE_LOG - 1 downto 0);
rate_next <= rate;
activity_next <= activity;
sw.sample_rate <= '0';
sw.sample_event <= '0';
sw.reset_stats <= '0';
sw.dump_stats <= '0';
if rden = '1' and ahbsi.htrans = HTRANS_NONSEQ
and ahbsi.hwrite = '1' then
if haddr(MEM_SIZE_LOG - 1 downto 0) = zero_adx then -- 0
sw.reset_stats <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = one_adx then -- 1
sw.dump_stats <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = ahb_adx then -- 7
activity_next <= ahb_act;
sw.sample_event <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = pc_adx then -- 4
activity_next <= pc_act;
sw.sample_event <= '1';
elsif haddr(MEM_SIZE_LOG - 1 downto 0) = inst_adx then -- 6
activity_next <= inst_act;
sw.sample_event <= '1';
else
rate_next <= haddr(MEM_SIZE_LOG - 1 downto 0);
sw.sample_rate <= '1';
end if;
end if;
end process decode_address;
update_params: process (clk,rst)
begin
if rst = '0' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '0';
rate <= conv_std_logic_vector(2, COUNT_BITS);
activity <= conv_std_logic_vector(0, ACTIVITY_BITS);
elsif clk'event and clk='1' then
if sw.reset_stats = '1' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '1';
elsif sw.dump_stats = '1' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '0';
elsif sw.sample_rate = '1' then
rate <= rate_next;
elsif sw.sample_event = '1' then
activity <= activity_next;
elsif full_log = '1' then
count <= conv_std_logic_vector(1, COUNT_BITS);
log <= '0';
elsif log = '1' then
count <= count_next;
if count_next = rate then
count <= one_count;
end if;
end if;
end if;
end process update_params;
sample <= '1' when ((log = '1') and (count_next = rate)) else '0';
rden <= '1' when (ahbsi.hsel(hindex) = '1' and ahbsi.hready = '1') else '0';
count_next <= count + conv_std_logic_vector(1, COUNT_BITS);
-----------------------------------------------------------------------------
-- AHB output handling
-----------------------------------------------------------------------------
hrdata(MEM_BITS - 1 downto 0) <= memout;
ahbso.hready <= '1';
ahbso.hresp <= HRESP_OKAY;
ahbso.hrdata <= hrdata;
ahbso.hsplit <= (others => '0');
-- ahbso.hirq <= (others => '0');
ahbso.hirq <= irq;
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
end rtl;
|
gpl-3.0
|
4230f7705b2beefe3e6e9bc4fe606f3a
| 0.503743 | 4.038287 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab11_RegisterTracker/lab11_RegisterTracker_lib/hdl/Reg_Behavior.vhd
| 1 | 856 |
--
-- VHDL Architecture lab11_RegisterTracker_lib.Reg.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 12:27:15 04/18/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Reg IS
GENERIC(size: positive := 16);
PORT( d: IN std_logic_vector (size-1 downto 0);
q: OUT std_logic_vector (size-1 downto 0) := (others=>'0');
c,e, reset: IN std_logic);
END ENTITY Reg;
ARCHITECTURE Behavior OF Reg IS
BEGIN
PROCESS(c)
BEGIN
IF(rising_edge(c)) THEN
IF(reset = '1') THEN
q <= (others=>'0');
ELSIF(e = '1') THEN
q <= d;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
2cbaf1bcbdb3f96abe12b85b566a2420
| 0.533879 | 3.53719 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/t80/t80.vhd
| 1 | 35,043 |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.t80_pack.all;
entity t80 is
generic(
t80mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end t80;
architecture rtl of t80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : t80_mcode
generic map(
t80mode => t80mode
)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : t80_alu
generic map(
t80mode => t80mode
)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if t80mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if t80mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif t80mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if t80mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(5) <= not ACC(5);
F(4) <= '1';
F(3) <= not ACC(3);
F(1) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(0) <= not F(0);
F(5) <= ACC(5);
F(4) <= F(0);
F(3) <= ACC(3);
F(1) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(0) <= '1';
F(5) <= ACC(5);
F(4) <= '0';
F(3) <= ACC(3);
F(1) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(2) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(2) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if t80mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(0) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(4) <= '0';
F(1) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(6) <= '1';
else
F(6) <= '0';
end if;
F(7) <= DI_Reg(7);
F(2) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(3) <= ALU_Q(3);
F(5) <= ALU_Q(1);
F(4) <= '0';
F(1) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(2) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and t80mode < 2 then
IncDecZ <= F_Out(6);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : t80_reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(2))) or
(I_BC and (not IR(4) or F(6) or not F(2))) or
(I_BTR and (not IR(4) or F(6)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and t80mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and t80mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
gpl-2.0
|
4d1ab201530b280df0c8b65abc23d2f4
| 0.44668 | 3.767254 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/VideoCon.vhd
| 1 | 4,777 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VideoCon is
port ( CLKin : in std_logic;
REFRESH_out : out std_logic;
STEP_out : out std_logic;
COLORin : in std_logic_vector(14 downto 0);
COLOR_out : out std_logic_vector(5 downto 0);
-- READRAM_out : out std_logic;
-- WRITERAM_out: out std_logic;
YCON_out : out std_logic_vector(3 downto 0);
XSEL_out : out std_logic_vector(5 downto 0);
XSEL2_out : out std_logic_vector(5 downto 0);
YSEL_out : out std_logic_vector(4 downto 0));
end VideoCon;
architecture Behavioral of VideoCon is
---------------------------------------------------------------------------
signal CLK2 : std_logic := '1';
signal CLK : std_logic := '0';
signal CLK3 : std_logic := '0';
signal TAK : std_logic := '0';
signal COLOR : std_logic_vector(14 downto 0);
signal COUNT : integer:= 0;
signal COUNT2 : integer:= 0;
signal COUNT3 : integer:= 0;
signal COUNTER1 : integer:= 0;
signal COUNTER2 : integer:= 0;
signal COUNTER3 : integer:= 0;
signal HCOUNT: std_logic_vector(6 downto 0) := (others => '0');
signal VCOUNT: std_logic_vector(4 downto 0) := (others => '0');
signal VSIG: std_logic_vector(6 downto 0) := (others => '0');
----------------------------------------------------------------------------
begin
----------------------------------------------------------
VHSHIFTER : process (CLKin)
begin
-----CLOCK DIV (SPEED)-----------------------------
if rising_edge(CLKin) then
if COUNT < 1 then
COUNT <= COUNT + 1;
else
CLK <= not CLK;
COUNT <= 0;
end if;
end if;
-----CLOCK DIV (CONTROL)---------------------------
if rising_edge(CLK) then
CLK2 <= not CLK2;
if COUNT2 = 1 then
STEP_out <= '1';
CLK3 <= '1';
COUNT2 <= 0;
else
STEP_out <= '0';
CLK3 <= '0';
COUNT2 <= 1;
end if;
if COUNTER1 < 64 then --SET COLOR AND DEFINE X AXIS SELECT
XSEL_out(5 downto 0) <= 63 - conv_std_logic_vector(COUNTER1,6);
XSEL2_out(5 downto 0) <= 61 - conv_std_logic_vector(COUNTER1,6);
if VCOUNT <= 15 then
COLOR_out(0) <= COLOR(0);
COLOR_out(1) <= '0';
COLOR_out(2) <= COLOR(1);
COLOR_out(3) <= '0';
COLOR_out(4) <= COLOR(2);
COLOR_out(5) <= '0';
elsif VCOUNT <= 31 then
COLOR_out(0) <= '0';
COLOR_out(1) <= COLOR(0);
COLOR_out(2) <= '0';
COLOR_out(3) <= COLOR(1);
COLOR_out(4) <= '0';
COLOR_out(5) <= COLOR(2);
else
COLOR_out <= (others => '0');
end if;
else
COLOR_out <= (others => '0');
end if;
if COUNTER1 = 64 or COUNTER1 = 129 then --ENABLE THE SCREEN UPDATE
if COUNTER2 = 0 then
COUNTER2 <= COUNTER2 + 1;
REFRESH_out <= '1';
else
REFRESH_out <= '0';
end if;
else
COUNTER2 <= 0;
REFRESH_out <= '0';
end if;
end if;
-----V & H SHIFT----------------------------------
if rising_edge(CLK2) then
if COUNTER1 < 130 then --128+2
COUNTER1 <= COUNTER1 + 1;
if COUNTER1 = 128 then --128
if VCOUNT < 31 then --16 - 1
VCOUNT <= VCOUNT + 1;
else
VCOUNT <= (others => '0');
end if;
end if;
if COUNTER1 = 129 then --RENEW THE Y CONTROL AND AXIS OUTPUT VALUES
YCON_out(3 downto 0) <= VCOUNT(3 downto 0);
YSEL_out(4 downto 0) <= 31 - VCOUNT;
end if;
else
COUNTER1 <= 0;
end if;
end if;
--------------------------------------------------
-------PULSE WIDTH--------------------------------------------------
if rising_edge(CLK3) then
if COUNTER3 < 32 then --2 ^ N + 1 (0-16 = 17) FOR SHIFTING
COUNTER3 <= COUNTER3 + 1;
else
COUNTER3 <= 0;
end if;
end if;
------------------------------------------------- RED
if COUNTER3 <= COLORin(14 downto 10) then
if COLORin(14 downto 10) = 0 then
COLOR(0) <= '0';
else
COLOR(0) <= '1';
end if;
else
COLOR(0) <= '0';
end if;
------------------------------------------------- GREEN
if COUNTER3 <= COLORin(9 downto 5) then
if COLORin(9 downto 5) = 0 then
COLOR(1) <= '0';
else
COLOR(1) <= '1';
end if;
else
COLOR(1) <= '0';
end if;
------------------------------------------------- BLUE
if COUNTER3 <= COLORin(4 downto 0) then
if COLORin(4 downto 0) = 0 then
COLOR(2) <= '0';
else
COLOR(2) <= '1';
end if;
else
COLOR(2) <= '0';
end if;
---------------------------------------------
-----SRAM SIGNALS*------------------------------------------------
-- READRAM_out <= --MAKE RELEVANT CONTROL
-- WRITERAM_out <= --MAKE RELEVANT CONTROL
------------------------------------------------------------------
end process VHSHIFTER;
----------------------------------------------------------
end Behavioral;
|
mit
|
87edafe404e0c9f50d135711669b1f8a
| 0.479799 | 3.182545 | false | false | false | false |
vermaete/ipxact2systemverilog
|
example/tb/vhd_dut.vhd
| 2 | 1,414 |
-- VHDL 93
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.example_vhd_pkg.all;
entity vhd_dut is
generic (
width : integer := 8;
addressWidth : integer := 8
);
port (
address : in std_ulogic_vector(addressWidth-1 downto 0);
writeEnable : in std_ulogic;
writeData : in std_ulogic_vector(width-1 downto 0);
readEnable : in std_ulogic;
readData : out std_ulogic_vector(width-1 downto 0);
clk : in std_ulogic;
rstn : in std_ulogic;
registers_i : in example_in_record_type;
registers_o : out example_out_record_type);
end vhd_dut;
architecture rtl of vhd_dut is
signal registers_i_i : example_in_record_type;
signal registers_o_i : example_out_record_type;
begin
process(clk, rstn)
begin
if rstn = '0' then
registers_o_i <= reset_example;
readData <= (others => '0');
elsif (clk = '1' and clk'event) then
registers_i_i <= registers_i;
if readEnable = '1' then
readData <= read_example(registers_i_i, registers_o_i, address);
elsif writeEnable = '1' then
registers_o_i <= write_example(writeData, address, registers_o_i);
end if;
-- If the design, as oppose of the CPU, wants to change the register values,
-- add code for it here.
end if;
end process;
registers_o <= registers_o_i;
end rtl;
|
gpl-2.0
|
45f24083ce789d7f5ee109b49e4bdabb
| 0.621641 | 3.35867 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_addsub.vhd
| 1 | 13,401 |
-------------------------------------------------------------------------------
--
-- Title : fp23_addsub
-- Design : FFT
-- Author : Kapitanov Alexander
-- Company :
-- E-mail : [email protected]
--
-------------------------------------------------------------------------------
--
-- Description : floating point adder/subtractor
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.reduce_pack.or_reduce;
use work.fp_m1_pkg.fp23_data;
library unisim;
use unisim.vcomponents.DSP48E1;
use unisim.vcomponents.DSP48E2;
entity fp23_addsub is
generic (
USE_MLT : boolean:=FALSE; --! Use DSP48E1/2 blocks or not
XSERIES : string:="7SERIES" --! Xilinx series: ULTRA / 7SERIES
);
port (
aa : in fp23_data; --! Summand/Minuend A
bb : in fp23_data; --! Summand/Substrahend B
cc : out fp23_data; --! Sum/Dif C
addsub : in std_logic; --! '0' - Add, '1' - Sub
reset : in std_logic; --! '0' - Reset
enable : in std_logic; --! Input data enable
valid : out std_logic; --! Output data valid
clk : in std_logic --! Clock
);
end fp23_addsub;
architecture fp23_addsub of fp23_addsub is
type std_logic_array_5xn is array (5 downto 0) of std_logic_vector(5 downto 0);
signal aa_z : fp23_data;
signal bb_z : fp23_data;
signal comp : std_logic_vector(22 downto 0);
signal muxa : fp23_data;
signal muxb : fp23_data;
signal exp_dif : std_logic_vector(5 downto 0);
signal impl_a : std_logic;
signal impl_b : std_logic;
signal msb_dec : std_logic_vector(15 downto 0);
signal man_az : std_logic_vector(16 downto 0);
signal subtract : std_logic;
signal msb_num : std_logic_vector(4 downto 0);
signal expc : std_logic_vector(5 downto 0);
signal frac : std_logic_vector(15 downto 0);
signal set_zero : std_logic;
signal expaz : std_logic_array_5xn;
signal sign_c : std_logic_vector(5 downto 0);
signal dout_val_v : std_logic_vector(7 downto 0);
signal exp_a0 : std_logic;
signal exp_b0 : std_logic;
signal exp_ab : std_logic;
signal exp_zz : std_logic_vector(5 downto 0);
signal new_man : std_logic_vector(15 downto 0);
begin
-- add or sub operation --
aa_z <= aa when rising_edge(clk);
pr_addsub: process(clk) is
begin
if rising_edge(clk) then
if (addsub = '0') then
bb_z <= bb;
else
bb_z <= (bb.exp, not bb.sig, bb.man);
end if;
end if;
end process;
exp_a0 <= or_reduce(aa.exp) when rising_edge(clk);
exp_b0 <= or_reduce(bb.exp) when rising_edge(clk);
exp_ab <= not (exp_a0 or exp_b0) when rising_edge(clk);
exp_zz <= exp_zz(exp_zz'left-1 downto 0) & exp_ab when rising_edge(clk);
-- check difference (least/most attribute) --
pr_ex: process(clk) is
begin
if rising_edge(clk) then
comp <= ('0' & aa.exp & aa.man) - ('0' & bb.exp & bb.man);
end if;
end process;
---- data switch multiplexer --
pr_mux: process(clk) is
begin
if rising_edge(clk) then
if (comp(22) = '1') then
muxa <= bb_z;
muxb <= aa_z;
else
muxa <= aa_z;
muxb <= bb_z;
end if;
end if;
end process;
---- implied '1' for fraction --
pr_imp: process(clk) is
begin
if rising_edge(clk) then
if (comp(22) = '1') then
impl_a <= exp_b0;
impl_b <= exp_a0;
else
impl_a <= exp_a0;
impl_b <= exp_b0;
end if;
end if;
end process;
---- Find exponent ----
pr_dif: process(clk) is
begin
if rising_edge(clk) then
exp_dif <= muxa.exp - muxb.exp;
subtract <= muxa.sig xor muxb.sig;
end if;
end process;
man_az <= impl_a & muxa.man when rising_edge(clk);
xUSE_DSP48: if (USE_MLT = TRUE) generate
constant CONST_ONE : std_logic_vector(15 downto 0):=x"8000";
signal dsp_aa : std_logic_vector(29 downto 0);
signal dsp_bb : std_logic_vector(17 downto 0);
signal dsp_cc : std_logic_vector(47 downto 0);
signal sum_man : std_logic_vector(47 downto 0);
signal shift_man : std_logic_vector(15 downto 0);
signal alu_mode : std_logic_vector(3 downto 0):=x"0";
signal dsp_mlt : std_logic;
signal dsp_res : std_logic;
begin
pr_mlt: process(clk) is
begin
if rising_edge(clk) then
if (exp_dif(5 downto 4) = "00") then
dsp_res <= '0';
else
dsp_res <= '1';
end if;
end if;
end process;
---- Shift vector for fraction ----
shift_man <= STD_LOGIC_VECTOR(SHR(UNSIGNED(CONST_ONE), UNSIGNED(exp_dif(4 downto 0)))) when rising_edge(clk);
pr_manz: process(clk) is
begin
if rising_edge(clk) then
alu_mode <= "00" & subtract & subtract;
end if;
end process;
---- Find fraction by using DSP48 ----
dsp_aa(16 downto 00) <= impl_b & muxb.man;
dsp_aa(29 downto 17) <= (others=>'0');
dsp_bb <= "00" & shift_man;
dsp_cc(14 downto 00) <= (others =>'0');
dsp_cc(31 downto 15) <= man_az when rising_edge(clk);
dsp_cc(47 downto 32) <= (others =>'0');
xDSP48E1: if (XSERIES = "7SERIES") generate
align_add: DSP48E1
generic map (
ALUMODEREG => 1,
ADREG => 0,
AREG => 2,
BCASCREG => 0,
BREG => 0,
CREG => 1,
DREG => 0,
MREG => 1,
PREG => 1
)
port map (
P => sum_man,
A => dsp_aa,
ACIN => (others=>'0'),
ALUMODE => alu_mode,
B => dsp_bb,
BCIN => (others=>'0'),
C => dsp_cc,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others=>'0'),
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
CLK => clk,
D => (others=>'0'),
INMODE => "00000",
MULTSIGNIN => '0',
OPMODE => "0110101",
PCIN => (others=>'0'),
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => dsp_res,
RSTP => reset
);
end generate;
xDSP48E2: if (XSERIES = "ULTRA") generate
align_add: DSP48E2
generic map (
ALUMODEREG => 1,
ADREG => 0,
AREG => 2,
BCASCREG => 0,
BREG => 0,
CREG => 1,
DREG => 0,
MREG => 1,
PREG => 1
)
port map (
P => sum_man,
A => dsp_aa,
ACIN => (others=>'0'),
ALUMODE => alu_mode,
B => dsp_bb,
BCIN => (others=>'0'),
C => dsp_cc,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others=>'0'),
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
CLK => clk,
D => (others=>'0'),
INMODE => "00000",
MULTSIGNIN => '0',
OPMODE => "000110101",
PCIN => (others=>'0'),
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => dsp_res,
RSTP => reset
);
end generate;
msb_dec <= sum_man(32 downto 17);
new_man <= sum_man(31 downto 16) when rising_edge(clk);
end generate;
xUSE_LOGIC: if (USE_MLT = FALSE) generate
signal norm_man : std_logic_vector(16 downto 0);
signal diff_man : std_logic_vector(16 downto 0);
signal diff_exp : std_logic_vector(1 downto 0);
signal add1 : std_logic;
signal add2 : std_logic;
signal sum_mt : std_logic_vector(17 downto 0);
signal man_shift : std_logic_vector(16 downto 0);
signal man_az1 : std_logic_vector(16 downto 0);
signal man_az2 : std_logic_vector(16 downto 0);
begin
man_shift <= impl_b & muxb.man when rising_edge(clk);
norm_man <= STD_LOGIC_VECTOR(SHR(UNSIGNED(man_shift), UNSIGNED(exp_dif(3 downto 0)))) when rising_edge(clk);
diff_exp <= exp_dif(5 downto 4) when rising_edge(clk);
pr_norm_man: process(clk) is
begin
if rising_edge(clk) then
if (diff_exp = "00") then
diff_man <= norm_man;
else
diff_man <= (others => '0');
end if;
end if;
end process;
add1 <= not subtract when rising_edge(clk);
add2 <= add1 when rising_edge(clk);
-- sum of fractions --
pr_man: process(clk) is
begin
if rising_edge(clk) then
man_az1 <= man_az;
man_az2 <= man_az1;
if (add2 = '1') then
sum_mt <= ('0' & man_az2) + ('0' & diff_man);
else
sum_mt <= ('0' & man_az2) - ('0' & diff_man);
end if;
end if;
end process;
msb_dec <= sum_mt(17 downto 2);
new_man <= sum_mt(16 downto 1) when rising_edge(clk);
end generate;
---- find MSB (highest '1' position) ----
pr_align: process(clk) is
begin
if rising_edge(clk) then
if (msb_dec(15-00)='1') then msb_num <= "00000";
elsif (msb_dec(15-01)='1') then msb_num <= "00001";
elsif (msb_dec(15-02)='1') then msb_num <= "00010";
elsif (msb_dec(15-03)='1') then msb_num <= "00011";
elsif (msb_dec(15-04)='1') then msb_num <= "00100";
elsif (msb_dec(15-05)='1') then msb_num <= "00101";
elsif (msb_dec(15-06)='1') then msb_num <= "00110";
elsif (msb_dec(15-07)='1') then msb_num <= "00111";
elsif (msb_dec(15-08)='1') then msb_num <= "01000";
elsif (msb_dec(15-09)='1') then msb_num <= "01001";
elsif (msb_dec(15-10)='1') then msb_num <= "01010";
elsif (msb_dec(15-11)='1') then msb_num <= "01011";
elsif (msb_dec(15-12)='1') then msb_num <= "01100";
elsif (msb_dec(15-13)='1') then msb_num <= "01101";
elsif (msb_dec(15-14)='1') then msb_num <= "01110";
elsif (msb_dec(15-15)='1') then msb_num <= "01111";
else msb_num <= "11111";
end if;
end if;
end process;
frac <= STD_LOGIC_VECTOR(SHL(UNSIGNED(new_man), UNSIGNED(msb_num(4 downto 0)))) when rising_edge(clk);
set_zero <= msb_num(4);
---- exponent increment ----
pr_expx: process(clk) is
begin
if rising_edge(clk) then
---- Set ones (error of rounding fp data ----
if (set_zero = '0') then
if (expaz(4) < ('0' & msb_num)) then
expc <= "000000";
else
expc <= expaz(4) - msb_num + '1';
end if;
else
expc <= "000000";
end if;
end if;
end process;
---- exp & sign delay ----
pr_expz: process(clk) is
begin
if rising_edge(clk) then
expaz <= expaz(expaz'left-1 downto 0) & muxa.exp;
sign_c <= sign_c(sign_c'left-1 downto 0) & muxa.sig;
end if;
end process;
---- output product ----
pr_dout: process(clk) is
begin
if rising_edge(clk) then
if (exp_zz(exp_zz'left) = '1') then
cc <= ("000000", '0', x"0000");
else
cc <= (expc, sign_c(sign_c'left), frac);
end if;
end if;
end process;
dout_val_v <= dout_val_v(dout_val_v'left-1 downto 0) & enable when rising_edge(clk);
valid <= dout_val_v(dout_val_v'left) when rising_edge(clk);
end fp23_addsub;
|
mit
|
29175427cf16d213d10b4f154d728af3
| 0.521901 | 2.995976 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/t80/t80_reg.vhd
| 1 | 3,805 |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity t80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end t80_Reg;
architecture rtl of t80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;
|
gpl-2.0
|
07e6ad707b60553549675984613c0a55
| 0.684363 | 3.808809 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/CHAR_ROM/simulation/CHAR_ROM_synth.vhd
| 1 | 6,825 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: CHAR_ROM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY CHAR_ROM_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE CHAR_ROM_synth_ARCH OF CHAR_ROM_synth IS
COMPONENT CHAR_ROM_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: CHAR_ROM_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
e16d157db31eeb3cb18d57474b2f593f
| 0.57978 | 3.795884 | false | false | false | false |
arcade-lab/uarch-phases
|
src/lib/tracing/syncram_dp_wrapper.vhd
| 1 | 7,719 |
------------------------------------------------------------------------------
-- This file is part of a signal tracing utility for the LEON3 processor
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Entity: syncram_dp_wrapper
-- File: syncram_dp_wrapper
-- Author: Van Bui - ARCADE @ Columbia University
-- Description: wraps several 14 bit addressable dual port SRAMS
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
use STD.textio.all;
use ieee.std_logic_textio.all;
--pragma translate_on
library sld;
use sld.tracing.all;
library techmap;
use techmap.gencomp.all;
use techmap.genacc.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity syncram_dp_wrapper is
generic (
tech : integer := 0;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
rdaddr : in std_logic_vector((MEM_SIZE_LOG-1) downto 0);
rden : in std_ulogic;
packsigs : in std_logic_vector((MEM_BITS -1) downto 0);
sample : in std_ulogic;
reset_log : in std_ulogic;
stop_log : in std_ulogic;
full_log : out std_ulogic;
memout : out std_logic_vector(MEM_BITS-1 downto 0);
irq : out std_logic_vector(NAHBIRQ-1 downto 0));
end syncram_dp_wrapper;
architecture beh_wrapper of syncram_dp_wrapper is
signal wrenarray : uvector(0 to NUM_SRAMS-1);
signal read_sig : std_logic_vector(MEM_SIZE_LOG - 1 downto BANK_SIZE_LOG);
signal outarray : vectorarray(0 to (NUM_SRAMS - 1));
signal write_window : std_logic_vector((WIN_SIZE_LOG-1) downto 0);
signal write_window_next : std_logic_vector((WIN_SIZE_LOG-1) downto 0);
signal sram_input : std_logic_vector((MEM_BITS -1) downto 0);
signal max_samples : std_logic_vector((MEM_BITS-1) downto 0);
signal buffer_full : std_ulogic;
signal dump_stats : std_ulogic;
signal cycle_count : std_logic_vector((MEM_BITS-1) downto 0);
signal cycle_count_next : std_logic_vector((MEM_BITS-1) downto 0);
signal irqset : std_ulogic;
begin
GEN_SRAM:
for n in 0 to (NUM_SRAMS-1) generate
SRAMX : syncram_dp
generic map (
tech => tech,
abits => BANK_SIZE_LOG,
dbits => MEM_BITS)
port map (
clk1 => clk,
address1 => rdaddr(BANK_SIZE_LOG - 1 downto 0),
datain1 => (others => '0'),
dataout1 => outarray(n),
enable1 => rden,
write1 => '0',
clk2 => clk,
address2 => write_window(BANK_SIZE_LOG - 1 downto 0),
datain2 => sram_input,
dataout2 => open,
enable2 => wrenarray(n),
write2 => wrenarray(n));
end generate GEN_SRAM;
delay_selector: process (clk, rst)
begin -- process delay_selector
if rst = '0' then -- asynchronous reset (active low)
read_sig <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
read_sig <= rdaddr(MEM_SIZE_LOG - 1 downto BANK_SIZE_LOG);
end if;
end process delay_selector;
write_select : process(clk, rst)
variable baddr : std_logic_vector(MEM_SIZE_LOG-1 downto BANK_SIZE_LOG);
begin -- process set_wren
max_samples <= conv_std_logic_vector(NUM_SAMPLES, MEM_BITS);
if rst = '0' then
buffer_full <= '0';
write_window <= (others => '0');
for i in 0 to (NUM_SRAMS-1) loop
wrenarray(i) <= '0';
end loop;
sram_input <= packsigs;
-- sram_input <= (others => '0');
dump_stats <= '0';
cycle_count <= (others => '0');
irq <= (others => '0');
irqset <= '0';
elsif clk'event and clk='1' then
cycle_count <= cycle_count_next;
for j in 0 to (NUM_SRAMS-1) loop
wrenarray(j) <= '0';
end loop;
if reset_log = '1' then
sram_input <= packsigs;
-- sram_input <= (others => '0');
write_window <= (others => '0');
buffer_full <= '0';
dump_stats <= '0';
cycle_count <= (others => '0');
elsif dump_stats = '1' then
wrenarray(0) <= '0';
elsif (write_window_next = max_samples(WIN_SIZE_LOG-1 downto 0) and (dump_stats = '0')) then
buffer_full <= '1';
-- sram_input((MEM_BITS -1) downto WIN_SIZE_LOG) <= (others => '0');
-- sram_input(WIN_SIZE_LOG - 1 downto 0) <= cycle_count;
sram_input <= cycle_count;
write_window <= (others => '0');
wrenarray(0) <= '1';
elsif (stop_log = '1') and (buffer_full = '0') then
-- sram_input((MEM_BITS -1) downto WIN_SIZE_LOG) <= (others => '0');
-- sram_input(WIN_SIZE_LOG - 1 downto 0) <= cycle_count;
sram_input <= cycle_count;
write_window <= (others => '0');
wrenarray(0) <= '1';
dump_stats <= '1';
cycle_count <= (others => '0');
elsif (stop_log = '1') and (buffer_full = '1') then
cycle_count <= (others => '0');
sram_input <= cycle_count;
wrenarray(0) <= '1';
write_window <= (others => '0');
dump_stats <= '1';
elsif sample = '1' then
sram_input <= packsigs;
-- sram_input(31 downto WIN_SIZE_LOG) <= (others => '0');
-- sram_input((WIN_SIZE_LOG-1) downto 0) <= write_window_next;
write_window <= write_window_next;
for k in 0 to (NUM_SRAMS-1) loop
baddr := conv_std_logic_vector(k, MEM_SIZE_LOG-BANK_SIZE_LOG);
if write_window_next(MEM_SIZE_LOG - 1 downto BANK_SIZE_LOG) = baddr(MEM_SIZE_LOG-1 downto BANK_SIZE_LOG) then
wrenarray(k) <= '1';
end if;
end loop;
end if;
-- interrupt
if irqset = '1' then
irq(pirq) <= '0';
elsif ((stop_log = '1') and (buffer_full = '0')) or (write_window_next = max_samples(WIN_SIZE_LOG-1 downto 0) and (dump_stats = '0')) or ((stop_log = '1') and (buffer_full = '0')) then
irq(pirq) <= '1';
irqset <= '1';
end if;
if reset_log = '1' then
irqset <= '0';
end if;
end if;
end process write_select;
read_select: process (read_sig, outarray)
variable bankaddr : std_logic_vector(MEM_SIZE_LOG-1 downto BANK_SIZE_LOG);
begin -- process selector
memout <= (others => '0');
for m in 0 to (NUM_SRAMS-1) loop
bankaddr := conv_std_logic_vector(m, MEM_SIZE_LOG-BANK_SIZE_LOG);
if read_sig = bankaddr(MEM_SIZE_LOG-1 downto BANK_SIZE_LOG) then
memout <= outarray(m);
end if;
end loop;
end process read_select;
cycle_count_next <= cycle_count + conv_std_logic_vector(1, MEM_BITS);
write_window_next <= write_window + conv_std_logic_vector(1, WIN_SIZE_LOG);
full_log <= '1' when (write_window_next = max_samples(WIN_SIZE_LOG-1 downto 0)) else '0';
end beh_wrapper;
|
gpl-3.0
|
7fda88000f9722a58392d9f3d7229412
| 0.565358 | 3.442908 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/DATA_CONSTRUCT.vhd
| 1 | 3,617 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DATA_CONSTRUCT is
port ( CLKin : in std_logic; --system clock
UPDATEin : in std_logic; --uart update signal
UARTin : in std_logic_vector(7 downto 0); --uart data in
COLOR_out : out std_logic_vector(14 downto 0); --color data
PIXSEL_out : out std_logic_vector(4 downto 0); --super pixel select
PIXRAM_out : out std_logic_vector(15 downto 0); --ram location select
UARTFOR_out : out std_logic_vector(7 downto 0); --uart data forward
MODE_out : out std_logic_vector(1 downto 0); --mode output
RAMCON_out : out std_logic; --controls write to sram
UPDAFOR_out : out std_logic; --uart update forward
UARTUPD_out : out std_logic; --uart send control
UARTDAT_out : out std_logic_vector(7 downto 0) --uart send data
);
end DATA_CONSTRUCT;
architecture Behavioral of DATA_CONSTRUCT is
---------------------------------------------------------------------------
signal UARTDAT : std_logic_vector(7 downto 0);
signal COLOR1 : std_logic_vector(7 downto 0);
signal PIXSEL : std_logic_vector(4 downto 0);
signal ENABLE : std_logic:='0';
signal ENABLE2 : std_logic:='1';
signal CLK2 : std_logic:='0';
signal COUNT : integer:= 0;
signal COUNT2 : integer:= 0;
signal CLKCOUNT : integer:= 0;
signal STATE : integer:= 0;
signal MODE : std_logic_vector(1 downto 0):= "11";
signal REACH : integer:= 0;
signal COLOR : std_logic_vector(14 downto 0) := (others => '0');
signal PIXRAM : std_logic_vector(7 downto 0) := (others => '0');
----------------------------------------------------------------------------
begin
----------------------------------------------------------
UARTMANIP : process (CLKin)
begin
--COLOR_out <= COLOR;
--PIXRAM_out <= PIXRAM;
--MODE_out <= MODE;
--UARTDAT_out <= UARTDAT;
--PIXSEL_out <= PIXSEL;
if rising_edge(CLKin) then
if STATE = 3 or STATE = 134 or STATE = 137 then
if COUNT < 899 and ENABLE = '1' then
COUNT <= COUNT + 1;
UARTUPD_out <= '1';
else
UARTUPD_out <= '0';
COUNT <= 0;
ENABLE <= '0';
end if;
else
ENABLE <= '1';
UARTUPD_out <= '0';
end if;
if STATE = 0 then
UPDAFOR_out <= '1';
else
UPDAFOR_out <= '0';
end if;
if STATE >= 69 and STATE <= 132 then
RAMCON_out <= '1';
else
RAMCON_out <= '0';
end if;
end if;
if rising_edge(UPDATEin) then
case STATE is
when 0 =>
if UARTin = x"61" then
STATE <= 3;
MODE_out<="01";
UARTDAT_out <= x"41";
elsif UARTin = x"62" then
STATE <= 134;
MODE_out<="10";
UARTDAT_out <= x"42";
elsif UARTin = x"63" then
STATE <= 137;
MODE_out<="11";
UARTDAT_out <= x"43";
else
MODE_out<="00";
end if;
when 3 =>
PIXRAM <= UARTin;
STATE <= STATE + 1;
when 4 =>
PIXRAM_out <= UARTin & PIXRAM;
STATE <= STATE + 1;
when 5 to 68 =>
COLOR1 <= UARTin;
STATE <= STATE + 64;
when 69 to 131 =>
COLOR_out <= COLOR1(6 downto 0) & UARTin;
STATE <= STATE - 63;
when 132 =>
COLOR_out <= COLOR1(6 downto 0) & UARTin;
STATE <= 0;
when 134 =>
PIXRAM <= UARTin;
STATE <= STATE + 1;
when 135 =>
PIXRAM_out <= UARTin & PIXRAM;
STATE <= STATE + 1;
when 136 =>
PIXSEL_out <= UARTin(4 downto 0);
STATE <= 0;
when 137 to 171 =>
UARTFOR_out <= UARTin;
STATE <= STATE + 1;
when 172 =>
UARTFOR_out <= UARTin;
STATE <= 0;
when others =>
STATE <= 0;
end case;
end if;
end process UARTMANIP;
----------------------------------------------------------
end Behavioral;
|
mit
|
e9193a32768218f41220936da103c72a
| 0.55875 | 3.029313 | false | false | false | false |
a4a881d4/ringbus
|
simio/dspemulator.vhd
| 1 | 3,936 |
-- This unit will simulate a DSP
-- It will read form a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity dspemulator is
generic ( DSP_INC_FILE : string := "UNUSED" ;
ABUS_WIDTH : integer := 16;
DBUS_WIDTH : integer := 16 );
port ( clk : in std_logic;
dspce : out std_logic;
dspa : out std_logic_vector( ABUS_WIDTH-1 downto 0 ) := ( others => '0' );
data : out std_logic_vector( DBUS_WIDTH-1 downto 0 ) := ( others => '0' );
wr : out std_logic;
IOstb : out std_logic );
end dspemulator;
architecture behavior of dspemulator is
signal state: integer:=0;
begin
process( clk )
variable buf: line ;
variable lineno:integer:=0;
FILE data_file: TEXT IS IN DSP_INC_FILE;
variable counter : integer:=0;
variable itime : integer:=-1;
variable init: boolean := false;
variable onwork: boolean := false;
variable wrinc: boolean := false;
variable wrTemp: std_logic :='0';
variable dataBeRead : std_logic_vector(DBUS_WIDTH - 1 downto 0) := (others => '0');
variable dataTemp : std_logic_vector(DBUS_WIDTH - 1 downto 0) := (others => '0');
variable booval: boolean :=false;
-- variable strTime,strData,strAddress : string(4 downto 1);
variable strTime : string(4 downto 1);
variable strData : string((DBUS_WIDTH - 1)/4 + 1 downto 1);
variable strAddress : string((ABUS_WIDTH - 1)/4 + 1 downto 1);
variable dspaTemp : std_logic_vector(ABUS_WIDTH - 1 downto 0) := (others => '0');
variable dspceTemp: std_logic:='0';
begin
if NOT( init ) then
counter:=0;
init:=true;
onwork:=false;
state<=4;
IOstb<='1';
end if;
if(DSP_INC_FILE = "UNUSED") then
ASSERT FALSE
REPORT "file not found!"
SEVERITY WARNING;
end if;
if clk'event and clk='1' then
counter:=counter+1;
if itime = counter then
onwork:=true;
state<=0;
end if;
if itime < counter-5 then
state<=4;
end if;
case state is
when 0 =>
dspceTemp:='1';
dataTemp:=dataBeRead;
wrTemp:='0';
state<=state+1;
when 1 =>
if wrinc then
wrTemp:='1';
end if;
state<=state+1;
when 2 =>
IOstb<='0';
state<=state+1;
when 3 =>
IOstb<='1';
state<=state+1;
when 4 =>
wrTemp:='0';
wrinc:=false;
onwork:=false;
dspaTemp:=conv_std_logic_vector(0,ABUS_WIDTH);
if NOT ENDFILE(data_file) then
booval := true;
READLINE(data_file, buf);
lineno:=lineno+1;
if (buf(buf'LOW) = 'W') then
wrinc:=true;
end if;
shrink_line(buf, 1);
READ(L=>buf, VALUE=>strTime, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
itime:=itime+hex_str_to_int(strTime);
shrink_line(buf, 1);
READ(L=>buf, VALUE=>strAddress, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no write data domain"
SEVERITY ERROR;
end if;
dspatemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strAddress),ABUS_WIDTH);
if wrinc then
shrink_line(buf, 1);
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no write data domain"
SEVERITY ERROR;
end if;
dataBeRead:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),DBUS_WIDTH);
end if;
end if;
state <=state+1;
when others =>
null;
end case;
dspce<=dspceTemp;
dspa<=dspaTemp(ABUS_WIDTH-1 downto 0 );
wr<=not wrTemp;
data<=dataTemp(DBUS_WIDTH-1 downto 0 );
end if;
end process;
end behavior;
|
lgpl-3.0
|
f161fd34325aa91cd9f5cb167d964b97
| 0.593496 | 3.011477 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/CHAR_ROM/example_design/CHAR_ROM_prod.vhd
| 1 | 9,901 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: CHAR_ROM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : CHAR_ROM.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 7
-- C_READ_WIDTH_A : 7
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 7
-- C_READ_WIDTH_B : 7
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY CHAR_ROM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END CHAR_ROM_prod;
ARCHITECTURE xilinx OF CHAR_ROM_prod IS
COMPONENT CHAR_ROM_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : CHAR_ROM_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
be17388981815147e5323a306563d185
| 0.493991 | 3.821305 | false | false | false | false |
ymahajan456/HighLevelSynthesis
|
Version_1.0/Testing/REG.vhd
| 1 | 737 |
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
ENTITY REG IS
GENERIC(
data_width: INTEGER := 0);
PORT(
inp: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
clk: IN STD_LOGIC := '0';
clr: IN STD_LOGIC := '0';
ena: IN STD_LOGIC := '0');
END ENTITY;
architecture myReg of REG is
begin
process(clk,clr)
begin
if(clk'event and clk = '1') then
if(ena = '1') then
outp <= inp;
end if;
end if;
if(clr = '1') then
outp <= (others => '0');
end if;
end process;
end architecture;
|
gpl-3.0
|
d68cec0a1b3600c1db33c9b0f4f5a9cb
| 0.525102 | 3.045455 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/controllers/io/MatrixKeyboard.vhd
| 1 | 1,234 |
----------------------------------------
-- 4x4 matrix keyboard decoder --
-- PORT MAPPING --
-- SCAN_LINE : 4 bit scan input --
-- clk : 1 bit clock input --
----------------------------------------
-- SCAN_ROW : 4 bit scan output --
-- data : 4 bit data output --
----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY matrix_keyboard_decoder IS
PORT
(
in_scan_line : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
in_clk : IN STD_LOGIC;
-----------------------------------------------
out_scan_row : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
out_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END matrix_keyboard_decoder;
ARCHITECTURE behavioral OF matrix_keyboard_decoder IS
BEGIN
PROCESS(in_clk)
BEGIN
in_scan_line <= "1111";
FOR i IN 0 TO 3 LOOP
out_scan_row <= "0000";
out_scan_row(i) <= '1';
FOR j IN 0 TO 3 LOOP
IF(in_scan_line(j) = '0') THEN
out_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(i * 4 + j, out_data'LENGTH));
EXIT;
ELSE
out_data <= "0000";
EXIT;
END IF;
END LOOP;
END LOOP;
END PROCESS;
END behavioral;
|
mit
|
a833915b8ba2a21f52e2731e1e743173
| 0.492707 | 3.437326 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/ay_3_8910_psg.vhd
| 1 | 20,785 |
--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- (C) Copyright 2011 Christopher D. Kilgour
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- Modified by Christopher D. Kilgour for use in Konami Arcade Chassis
-- Emulator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ay_3_8910_psg is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
O_AUDIO_A : out std_logic_vector(7 downto 0);
O_AUDIO_B : out std_logic_vector(7 downto 0);
O_AUDIO_C : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher
-- speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of ay_3_8910_psg is
type regset is array (0 to 15) of std_logic_vector(7 downto 0);
type tonecnt is array (1 to 3) of unsigned(11 downto 0);
signal cnt_div : unsigned(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : regset;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : unsigned(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : tonecnt := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : unsigned(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : unsigned(4 downto 0);
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
if (addr(7 downto 4) = "0000") then
cs := '1';
else
cs := '0';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake
-- up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
--
-- CLOCKED
--
p_waddr : process( CLK, RESET_L ) is
begin
-- looks like registers are latches in real chip, but the
-- address is caught at the end of the address state.
if RESET_L = '0' then
addr <= (others => '0');
elsif CLK'event and CLK = '1' then
if (busctrl_addr = '1') then
addr <= I_DA;
end if;
end if;
end process;
p_wdata : process( CLK, RESET_L ) is
begin
-- looks like registers are latches in real chip, but the
-- address is caught at the end of the address state.
if RESET_L = '0' then
reg <= (others => (others => '0'));
env_reset <= '1';
elsif CLK'event and CLK = '1' then
if (busctrl_we = '1') then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA; env_reset <= '0';
when x"1" => reg(1) <= I_DA; env_reset <= '0';
when x"2" => reg(2) <= I_DA; env_reset <= '0';
when x"3" => reg(3) <= I_DA; env_reset <= '0';
when x"4" => reg(4) <= I_DA; env_reset <= '0';
when x"5" => reg(5) <= I_DA; env_reset <= '0';
when x"6" => reg(6) <= I_DA; env_reset <= '0';
when x"7" => reg(7) <= I_DA; env_reset <= '0';
when x"8" => reg(8) <= I_DA; env_reset <= '0';
when x"9" => reg(9) <= I_DA; env_reset <= '0';
when x"A" => reg(10) <= I_DA; env_reset <= '0';
when x"B" => reg(11) <= I_DA; env_reset <= '0';
when x"C" => reg(12) <= I_DA; env_reset <= '0';
when x"D" => reg(13) <= I_DA; env_reset <= '1';
when x"E" => reg(14) <= I_DA; env_reset <= '0';
when x"F" => reg(15) <= I_DA; env_reset <= '0';
when others => null;
end case;
else
env_reset <= '0';
end if;
end if;
end process;
--
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
--
-- p_waddr : process(reset_l, busctrl_addr)
-- begin
-- -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
-- if (RESET_L = '0') then
-- addr <= (others => '0');
-- elsif falling_edge(busctrl_addr) then -- yuk
-- addr <= I_DA;
-- end if;
-- end process;
-- p_wdata : process(reset_l, busctrl_we, addr)
-- begin
-- if (RESET_L = '0') then
-- reg <= (others => (others => '0'));
-- elsif falling_edge(busctrl_we) then
-- case addr(3 downto 0) is
-- when x"0" => reg(0) <= I_DA;
-- when x"1" => reg(1) <= I_DA;
-- when x"2" => reg(2) <= I_DA;
-- when x"3" => reg(3) <= I_DA;
-- when x"4" => reg(4) <= I_DA;
-- when x"5" => reg(5) <= I_DA;
-- when x"6" => reg(6) <= I_DA;
-- when x"7" => reg(7) <= I_DA;
-- when x"8" => reg(8) <= I_DA;
-- when x"9" => reg(9) <= I_DA;
-- when x"A" => reg(10) <= I_DA;
-- when x"B" => reg(11) <= I_DA;
-- when x"C" => reg(12) <= I_DA;
-- when x"D" => reg(13) <= I_DA;
-- when x"E" => reg(14) <= I_DA;
-- when x"F" => reg(15) <= I_DA;
-- when others => null;
-- end case;
-- end if;
--
-- env_reset <= '0';
-- if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
-- env_reset <= '1';
-- end if;
-- end process;
p_rdata : process(busctrl_re, addr, reg,
ioa_inreg, iob_inreg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for
-- putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process( CLK ) is
begin
if CLK'event and CLK = '1' then
-- / 8
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= "0111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end if;
end process;
p_noise_gen : process( CLK ) is
variable noise_gen_comp : unsigned(4 downto 0);
variable poly17_zero : std_logic;
begin
if CLK'event and CLK = '1' then
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := unsigned(reg(6)(4 downto 0)) - 1;
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process( CLK ) is
variable tone_gen_freq : tonecnt;
variable tone_gen_comp : tonecnt;
begin
if CLK'event and CLK = '1' then
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := unsigned(reg(1)(3 downto 0)) & unsigned(reg(0));
tone_gen_freq(2) := unsigned(reg(3)(3 downto 0)) & unsigned(reg(2));
tone_gen_freq(3) := unsigned(reg(5)(3 downto 0)) & unsigned(reg(4));
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end if;
end process;
p_envelope_freq : process( CLK ) is
variable env_gen_freq : unsigned(15 downto 0);
variable env_gen_comp : unsigned(15 downto 0);
begin
if CLK'event and CLK = '1' then
env_gen_freq := unsigned(reg(12)) & unsigned(reg(11));
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end if;
end process;
p_envelope_shape : process(CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if CLK'event and CLK = '1' then
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
else
env_hold <= '0';
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_output : process(CLK, RESET_L) is
variable volA, volB, volC : integer;
type rom32 is array(0 to 31) of std_logic_vector(7 downto 0);
constant dacrom : rom32 := (x"00", x"01", x"02", x"02",
x"03", x"03", x"04", x"05",
x"06", x"07", x"08", x"09",
x"0B", x"0D", x"10", x"13",
x"16", x"1A", x"1F", x"25",
x"2C", x"34", x"3D", x"48",
x"54", x"63", x"74", x"88",
x"9F", x"BA", x"D9", x"FF");
begin
if (RESET_L = '0') then
O_AUDIO_A <= (others => '0');
O_AUDIO_B <= (others => '0');
O_AUDIO_C <= (others => '0');
volA := 0; volB := 0; volC := 0;
elsif CLK'event and CLK = '0' then
if (ENA = '1') then
if ((reg(7)(0) = '0' and tone_gen_op(1) = '1') or
(reg(7)(3) = '0' and noise_gen_op = '1')) then
if reg(8)(4) = '0' then
if reg(8)(3 downto 0) = X"0" then
volA := 0;
else
volA := to_integer(unsigned(reg(8)(3 downto 0) & '1'));
end if;
else
volA := to_integer(env_vol);
end if;
else
volA := 0;
end if;
if ((reg(7)(1) = '0' and tone_gen_op(2) = '1') or
(reg(7)(4) = '0' and noise_gen_op = '1')) then
if reg(9)(4) = '0' then
if reg(9)(3 downto 0) = X"0" then
volB := 0;
else
volB := to_integer(unsigned(reg(9)(3 downto 0) & '1'));
end if;
else
volB := to_integer(env_vol);
end if;
else
volB := 0;
end if;
if ((reg(7)(2) = '0' and tone_gen_op(3) = '1') or
(reg(7)(5) = '0' and noise_gen_op = '1')) then
if reg(10)(4) = '0' then
if reg(10)(3 downto 0) = X"0" then
volC := 0;
else
volC := to_integer(unsigned(reg(10)(3 downto 0) & '1'));
end if;
else
volC := to_integer(env_vol);
end if;
else
volC := 0;
end if;
else
volA := 0; volB := 0; volC := 0;
end if;
O_AUDIO_A <= dacrom(volA);
O_AUDIO_B <= dacrom(volB);
O_AUDIO_C <= dacrom(volC);
end if;
end process;
p_io_ports : process(reg)
begin
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process( CLK ) is
begin
if CLK'event and CLK = '1' then
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end if;
end process;
end architecture RTL;
|
gpl-2.0
|
1c57f7de0db754b8d4ca70808018237d
| 0.460717 | 3.324004 | false | false | false | false |
juhasch/myhdl
|
example/manual/gray_inc_reg.vhd
| 6 | 1,216 |
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
lgpl-2.1
|
205184bf9b9ae67181e5b43fa83e3a8a
| 0.641447 | 2.958637 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab8_new/lab8_new_lib/hdl/SimpleMux2_Behavior.vhd
| 1 | 892 |
--
-- VHDL Architecture lab8_new_lib.SimpleMux2.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 15:07:21 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY SimpleMux2 IS
GENERIC(width: POSITIVE := 16);
PORT( Data_In_0, Data_In_1: IN std_logic_vector(width-1 downto 0);
Data_Out: OUT std_logic_vector(width-1 downto 0);
mux_control: IN std_logic);
END ENTITY SimpleMux2;
--
ARCHITECTURE Behavior OF SimpleMux2 IS
BEGIN
PROCESS(Data_In_0, Data_In_1, mux_control)
BEGIN
IF(mux_control = '0') THEN
Data_Out <= Data_In_0;
ELSIF(mux_control = '1') THEN
Data_Out <= Data_In_1;
ELSE
Data_Out <= (others=>'X');
END IF;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
51cf9e7016319b6b1d8ecfbcf72c31c4
| 0.606502 | 3.208633 | false | false | false | false |
a4a881d4/ringbus
|
simio/iqademulator.vhd
| 1 | 2,262 |
-- This unit will simulate a AD
-- It will read form a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity IQADemulator is
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iout : out std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' );
Qout : out std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' ));
end IQADemulator;
architecture behavior of IQADemulator is
signal state: integer:=0;
begin
process( clk )
variable buf: line ;
variable lineno:integer:=0;
FILE data_file: TEXT IS IN AD_FILE;
variable dataTemp: std_logic_vector(15 downto 0):="0000000000000000";
variable booval: boolean :=false;
variable strData : string(4 downto 1);
begin
if(AD_FILE = "UNUSED") then
ASSERT FALSE
REPORT "file not found!"
SEVERITY WARNING;
end if;
if clk'event and clk='1' then
if ce='1' then
if NOT ENDFILE(data_file) then
booval := true;
READLINE(data_file, buf);
lineno:=lineno+1;
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
dataTemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),16);
Iout<=dataTemp(DATA_WIDTH-1 downto 0 );
shrink_line(buf, 1);
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
dataTemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),16);
Qout<=dataTemp(DATA_WIDTH-1 downto 0 );
else
Iout <= ( others => '0' );
Qout <= ( others => '0' );
end if;
end if;
end if;
end process;
end behavior;
|
lgpl-3.0
|
0d6791097eb557511f0699b781d2da1b
| 0.545977 | 3.490741 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/blk_mem_gen_v7_3.vhd
| 1 | 5,472 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 10,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 1024,
c_read_depth_b => 1024,
c_read_width_a => 7,
c_read_width_b => 7,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 1024,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 7,
c_write_width_b => 7,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
|
mit
|
b9a12db62ffa3355460afd0884edf08e
| 0.529605 | 3.823899 | false | false | false | false |
a4a881d4/ringbus
|
V3.0/examples/rbus2.vhd
| 1 | 6,829 |
---------------------------------------------------------------------------------------------------
--
-- Title : Two End Point Example for Ring Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : rbus2.vhd
-- Generated : 2013/9/7
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring bus example
-- two end point
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.rb_config.all;
use work.dma_config.all;
entity RBUS2 is
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- CPU bus
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
-- out
viewAout : out std_logic_vector( 9 downto 0 );
viewDout : out std_logic_vector( 127 downto 0 );
viewenout : out std_logic
);
end RBUS2;
architecture behave of RBUS2 is
constant Num : natural := 2;
constant Bwidth : natural := 128;
component blockdram
generic(
depth: integer := 256;
Dwidth: integer := 8;
Awidth: integer := 8
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
reb: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component DUMMYSRC
generic(
Awidth : natural;
Bwidth : natural
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Addr : in std_logic_vector( Awidth-1 downto 0 );
Q : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
ren : in STD_LOGIC
);
end component;
signal tx_i : std_logic_vector( Num*Bwidth-1 downto 0 );
signal Req_i : std_logic_vector(Num-1 downto 0):= (others => '0');
signal tx_sop_i : std_logic_vector(Num-1 downto 0):= (others => '0');
signal rx_i : std_logic_vector( Num*Bwidth-1 downto 0 );
signal rx_sop_i : std_logic_vector(Num-1 downto 0):= (others => '0');
signal DMA0H, DMA1H : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' );
signal DMA0A, DMA1A : std_logic_vector( 9 downto 0 ) := ( others=>'0' );
signal DMA0_Req, DMA1_Req : std_logic := '0';
signal DMA0_Busy, DMA1_Busy : std_logic := '0';
signal viewA : std_logic_vector( 9 downto 0 ) := ( others=>'0' );
signal viewD : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' );
signal viewen : std_logic := '0';
signal CS0, CS1 : std_logic := '0';
signal Dout0, Dout1 : std_logic_vector( 7 downto 0 ) := ( others=>'Z' );
signal ramWA, ramRA, dummyA : std_logic_vector( 9 downto 0 ) := ( others=>'0' );
signal ramWD, ramRD, dummyD : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' );
signal ramWen, ramRen, dummyen : std_logic := '0';
begin
bus2:RBUS
generic map(
Bwidth=>128,
Num=>2
)
port map(
-- system
sync =>'0',
clk => clk,
rst => rst,
-- tx
tx => tx_i,
Req => Req_i,
tx_sop => tx_sop_i,
-- rx
rx_sop => rx_sop_i,
rx => rx_i
);
outEP0:EPMEMOUT
generic map (
Awidth => 10,
Bwidth => 128
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
tx_sop => tx_sop_i(0),
Req => req_i(0),
tx => tx_i((0+1)*Bwidth-1 downto 0*Bwidth),
-- Mem interface
mD => dummyD,
mAddr => dummyA,
mren => dummyen,
-- Local Bus interface
header => DMA0H,
laddr => DMA0A,
Req_in => DMA0_Req,
busy => DMA0_busy
);
outEP1:EPMEMOUT
generic map (
Awidth => 10,
Bwidth => 128
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
tx_sop => tx_sop_i(1),
Req => req_i(1),
tx => tx_i((1+1)*Bwidth-1 downto 1*Bwidth),
-- Mem interface
mD => ramRD,
mAddr => ramRA,
mren => ramRen,
-- Local Bus interface
header => DMA1H,
laddr => DMA1A,
Req_in => DMA1_Req,
busy => DMA1_busy
);
INEP0:EPMEMIN
generic map(
Awidth => 10,
Bwidth => 128,
CS => "00"
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
rx_sop => rx_sop_i(0),
rx => rx_i((0+1)*Bwidth-1 downto 0*Bwidth),
-- Mem interface
Addr => viewA,
D => viewD,
wen => viewen
--
);
INEP1:EPMEMIN
generic map(
Awidth => 10,
Bwidth => 128,
CS => "00"
)
port map(
-- system interface
clk => clk,
rst => rst,
-- bus interface
rx_sop => rx_sop_i(1),
rx => rx_i((1+1)*Bwidth-1 downto 1*Bwidth),
-- Mem interface
Addr => ramWA,
D => ramWD,
wen => ramWen
--
);
DMA0:DMANP
generic map(
Bwidth => 128,
SAwidth => 10,
DAwidth => 12,
Lwidth => 10
)
port map(
-- system signal
clk => clk,
rst => rst,
-- Tx interface
header => DMA0H,
Req => DMA0_Req,
laddr => DMA0A,
busy => DMA0_Busy,
tx_sop => tx_sop_i(0),
-- CPU bus
CS => CS0,
wr => wr,
rd => rd,
addr => addr( 3 downto 0 ),
Din => Din,
Dout => Dout0,
cpuClk => cpuClk,
-- Priority
en => '1'
);
DMA1:DMANP
generic map(
Bwidth => 128,
SAwidth => 10,
DAwidth => 12,
Lwidth => 10
)
port map(
-- system signal
clk => clk,
rst => rst,
-- Tx interface
header => DMA1H,
Req => DMA1_Req,
laddr => DMA1A,
busy => DMA0_Busy,
tx_sop => tx_sop_i(1),
-- CPU bus
CS => CS1,
wr => wr,
rd => rd,
addr => addr( 3 downto 0 ),
Din => Din,
Dout => Dout1,
cpuClk => cpuClk,
-- Priority
en => '1'
);
ep1ram : blockdram
generic map(
depth => 1024,
Dwidth => 128,
Awidth => 10
)
port map(
addra => ramWA,
clka => clk,
addrb => ramRA,
clkb => clk,
dia => ramWD,
wea => ramWen,
reb => ramRen,
dob => ramRD
);
ep0src:DUMMYSRC
generic map(
Awidth => 10,
Bwidth => 128
)
port map(
-- system
clk => clk,
rst => rst,
Addr => dummyA,
Q => dummyD,
ren => dummyen
);
viewAout<=viewA;
viewDout<=viewD;
viewenout <= viewen;
cs0<='1' when addr( 7 downto 4 )="0000" else '0';
cs1<='1' when addr( 7 downto 4 )="0001" else '0';
dout<=dout0 when cs0='1' else ( others=>'Z' );
end behave;
|
lgpl-3.0
|
c795aae346ab413be7cc9e2e339bf47f
| 0.507981 | 2.865715 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
DE10/altera_ram.vhd
| 1 | 924 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
GENERIC
(
ADDRESS_WIDTH : integer := 4;
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
write_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
read_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
);
END ram;
ARCHITECTURE rtl OF ram IS
TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL ram_block : RAM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(to_integer(unsigned(write_address))) <= data;
END IF;
q <= ram_block(to_integer(unsigned(read_address)));
END IF;
END PROCESS;
END rtl;
|
gpl-2.0
|
85393052d863f1ee14a23089a0858e45
| 0.622294 | 2.783133 | false | false | false | false |
andreasschuh/Multi-Eigenmode-Controller
|
compensator.vhd
| 1 | 22,214 |
----------------------------------------------------------------------------------
-- Company: Grad School
-- Engineer: Andreas Schuh
--
-- Create Date: 20:14:04 02/07/2013
-- Design Name:
-- Module Name: Statemachine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--ENTITY
entity SystemID is
Port ( ADC1in : in STD_LOGIC_VECTOR (31 downto 0);
ADC2in : in STD_LOGIC_VECTOR (31 downto 0);
DAC1out : out STD_LOGIC_VECTOR (31 downto 0);
DAC2out : out STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC);
end SystemID;
-- ARCHITECTURE
architecture Behavioral of SystemID is
------------------------------------------------------------------------------
-- DECLARE Compensator Parameters HERE - From MATLAB generated file
------------------------------------------------------------------------------
constant a11 : std_logic_vector := "00111111011111101000001010110010";
constant a12 : std_logic_vector := "00111101110110001001011101011111";
constant a21 : std_logic_vector := "10111101110110001001011101011111";
constant a22 : std_logic_vector := "00111111011111101000001010110010";
constant a33 : std_logic_vector := "00111111010011110100100101011111";
constant a34 : std_logic_vector := "00111111000101011100110100100011";
constant a43 : std_logic_vector := "10111111000101011100110100100011";
constant a44 : std_logic_vector := "00111111010011110100100101011111";
constant b1 : std_logic_vector := "10111011100101011111001010000110";
constant b2 : std_logic_vector := "00111100010101100110011000100000";
constant b3 : std_logic_vector := "10111011011001000111010100110001";
constant b4 : std_logic_vector := "10111100110010111000011111101011";
constant c1 : std_logic_vector := "00111100010101100010100101100000";
constant c2 : std_logic_vector := "10111011100101010110010010000101";
constant c3 : std_logic_vector := "10111100110010110101101110110001";
constant c4 : std_logic_vector := "10111011011001111000101100010100";
constant k1 : std_logic_vector := "10111101010100011110001110111000";
constant k2 : std_logic_vector := "00111101111000111001100001101000";
constant k3 : std_logic_vector := "00111101101000010100111110001011";
constant k4 : std_logic_vector := "10111110000110110101100011110011";
constant l1 : std_logic_vector := "00111111101000100100001001100101";
constant l2 : std_logic_vector := "10111110100100111111011000000000";
constant l3 : std_logic_vector := "11000000000100100001111011010000";
constant l4 : std_logic_vector := "10111110111111101110100111111000";
-- COMPONENTS
COMPONENT AddFloat
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
operation_nd : IN STD_LOGIC;
operation_rfd : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
underflow : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
invalid_op : OUT STD_LOGIC;
rdy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT MultFloat
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
operation_nd : IN STD_LOGIC;
operation_rfd : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
underflow : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
invalid_op : OUT STD_LOGIC;
rdy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT SubFloat
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
operation_nd : IN STD_LOGIC;
operation_rfd : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
underflow : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
invalid_op : OUT STD_LOGIC;
rdy : OUT STD_LOGIC
);
END COMPONENT;
-- for non Trimming
attribute KEEP : string;
attribute S : string;
-- SIGNALS
signal mult1a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult1b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult2a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult2b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult3a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult3b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult4a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult4b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add1a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add1b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add2a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add2b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add3a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add3b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add4a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add4b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sub1a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sub1b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_sub1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal vresult: std_logic_vector(31 downto 0);
signal vX1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vX2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vX3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vX4 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vKX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vCX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vRminusKX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vSensorMinusCX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add4 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_misc1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_misc2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal operation_nd1 : STD_LOGIC;
signal operation_nd2 : STD_LOGIC;
signal operation_nd3 : STD_LOGIC;
signal operation_nd4 : STD_LOGIC;
signal operation_nd5 : STD_LOGIC;
signal operation_nd6 : STD_LOGIC;
signal operation_nd7 : STD_LOGIC;
signal operation_nd8 : STD_LOGIC;
signal operation_nd9 : STD_LOGIC;
signal ADCbuff : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- STATE DEFINITIONS
type state_type is (Zero,One,Two,Three,Four,Five,Six,Seven,Eight,Nine);
signal state : state_type;
-- BEGIN
begin
-- INSTANTIATION OF COMPONENTS
AddFloat1 : AddFloat
PORT MAP (
a => add1a,
b => add1b,
operation_nd => operation_nd1,
operation_rfd => open,
result => result_add1,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
AddFloat2 : AddFloat
PORT MAP (
a => add2a,
b => add2b,
operation_nd => operation_nd2,
operation_rfd => open,
result => result_add2,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
AddFloat3 : AddFloat
PORT MAP (
a => add3a,
b => add3b,
operation_nd => operation_nd3,
operation_rfd => open,
result => result_add3,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
AddFloat4 : AddFloat
PORT MAP (
a => add4a,
b => add4b,
operation_nd => operation_nd4,
operation_rfd => open,
result => result_add4,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat1 : MultFloat
PORT MAP (
a => mult1a,
b => mult1b,
operation_nd => operation_nd5,
operation_rfd => open,
result => result_mult1,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat2 : MultFloat
PORT MAP (
a => mult2a,
b => mult2b,
operation_nd => operation_nd6,
operation_rfd => open,
result => result_mult2,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat3 : MultFloat
PORT MAP (
a => mult3a,
b => mult3b,
operation_nd => operation_nd7,
operation_rfd => open,
result => result_mult3,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat4 : MultFloat
PORT MAP (
a => mult4a,
b => mult4b,
operation_nd => operation_nd8,
operation_rfd => open,
result => result_mult4,
underflow => open,
overflow => open,
invalid_op => open,
rdy =>open
);
SubFloat1: SubFloat
PORT MAP (
a => sub1a,
b => sub1b,
operation_nd => operation_nd9,
operation_rfd => open,
result => result_sub1,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
-- SERIAL, SYNCHRONOUS PROCESS
-- All of the state machine is synchronous, no asyn. (combinatorial) code
process (clock)
begin
if(clock'event and clock='1') then
-- Default values for signal, to enforce full assigment.
mult1a <= (others => '0');
mult1b <= (others => '0');
mult2a <= (others => '0');
mult2b <= (others => '0');
mult3a <= (others => '0');
mult3b <= (others => '0');
mult4a <= (others => '0');
mult4b <= (others => '0');
add1a <= (others => '0');
add1b <= (others => '0');
add2a <= (others => '0');
add2b <= (others => '0');
add3a <= (others => '0');
add3b <= (others => '0');
add4a <= (others => '0');
add4b <= (others => '0');
sub1a <= (others => '0');
sub1b <= (others => '0');
vresult <= vresult;
vX1 <= vX1;
vX2 <= vX2;
vX3 <= vX3;
vX4 <= vX4;
vKX <= vKX;
vCX <= vCX;
vRminusKX <= vRminusKX;
vSensorMinusCX <= vSensorMinusCX;
vInter_add1 <= vInter_add1;
vInter_add2 <= vInter_add2;
vInter_add3 <= vInter_add3;
vInter_add4 <= vInter_add4;
vInter_misc1 <= vInter_misc1;
vInter_misc2 <= vInter_misc2;
operation_nd1 <= '0';
operation_nd2 <= '0';
operation_nd3 <= '0';
operation_nd4 <= '0';
operation_nd5 <= '0';
operation_nd6 <= '0';
operation_nd7 <= '0';
operation_nd8 <= '0';
operation_nd9 <= '0';
DAC1out <= vRminusKX;
DAC2out <= vCX;
state <= state;
-- START STATE MACHINE
case state is
when Zero =>
mult1a <= (others => '0');
mult1b <= (others => '0');
mult2a <= (others => '0');
mult2b <= (others => '0');
mult3a <= (others => '0');
mult3b <= (others => '0');
mult4a <= (others => '0');
mult4b <= (others => '0');
add1a <= (others => '0');
add1b <= (others => '0');
add2a <= (others => '0');
add2b <= (others => '0');
add3a <= (others => '0');
add3b <= (others => '0');
add4a <= (others => '0');
add4b <= (others => '0');
sub1a <= (others => '0');
sub1b <= (others => '0');
vresult <= (others => '0');
vX1 <= (others => '0');
vX2 <= (others => '0');
vX3 <= (others => '0');
vX4 <= (others => '0');
vKX <= (others => '0');
vCX <= (others => '0');
vRminusKX <= (others => '0');
vSensorMinusCX <= (others => '0');
vInter_add1 <= (others => '0');
vInter_add2 <= (others => '0');
vInter_add3 <= (others => '0');
vInter_add4 <= (others => '0');
vInter_misc1 <= (others => '0');
vInter_misc2 <= (others => '0');
DAC1out <= (others => '0');
DAC2out <= (others => '0');
operation_nd1 <= '0';
operation_nd2 <= '0';
operation_nd3 <= '0';
operation_nd4 <= '0';
operation_nd5 <= '0';
operation_nd6 <= '0';
operation_nd7 <= '0';
operation_nd8 <= '0';
operation_nd9 <= '0';
state <= One;
when One =>
add1a <= (others=>'0');
add1b <= (others=>'0');
operation_nd1 <= '0';
--vInter_misc1 := result_add1;
add2a <= (others=>'0');
add2b <= (others=>'0');
operation_nd2 <= '0';
--vInter_misc2 := result_add2;
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vX1;
mult1b <= c1;
operation_nd5 <= '1';
mult2a <= vX2;
mult2b <= c2;
operation_nd6 <= '1';
mult3a <= vX3;
mult3b <= c3;
operation_nd7 <= '1';
mult4a <= vX4;
mult4b <= c4;
operation_nd8 <= '1';
sub1a <= ADC1in;
sub1b <= result_add1;
vKX <= result_add1;
operation_nd9 <= '1';
state <= Two;
when Two =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vX1;
mult1b <= a11;
operation_nd5 <= '1';
mult2a <= vX2;
mult2b <= a12;
operation_nd6 <= '1';
mult3a <= vX1;
mult3b <= a21;
operation_nd7 <= '1';
mult4a <= vX2;
mult4b <= a22;
operation_nd8 <= '1';
vRminusKX <= result_sub1;
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Three;
when Three =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
add3a <= result_add1;
add3b <= result_add2;
operation_nd3 <= '1';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vX3;
mult1b <= a33;
operation_nd5 <= '1';
mult2a <= vX4;
mult2b <= a34;
operation_nd6 <= '1';
mult3a <= vX3;
mult3b <= a43;
operation_nd7 <= '1';
mult4a <= vX4;
mult4b <= a44;
operation_nd8 <= '1';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Four;
when Four =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
vX1 <= result_add1;
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
vX2 <= result_add2;
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vRminusKX;
mult1b <= b1;
operation_nd5 <= '1';
mult2a <= vRminusKX;
mult2b <= b2;
operation_nd6 <= '1';
mult3a <= vRminusKX;
mult3b <= b3;
operation_nd7 <= '1';
mult4a <= vRminusKX;
mult4b <= b4;
operation_nd8 <= '1';
sub1a <= ADC2in;
sub1b <= result_add3;
operation_nd9 <= '1';
vCX <= result_add3;
state <= Five;
when Five =>
add1a <= vX1;
add1b <= result_mult1;
operation_nd1 <= '1';
add2a <= vX2;
add2b <= result_mult2;
operation_nd2 <= '1';
add3a <= result_add1;
add3b <= result_mult3;
vX3 <= result_add1;
operation_nd3 <= '1';
add4a <= result_add2;
add4b <= result_mult4;
vX4 <= result_add2;
operation_nd4 <= '1';
vSensorMinusCX <= result_sub1;
mult1a <= result_sub1;
mult1b <= l1;
operation_nd5 <= '1';
mult2a <= result_sub1;
mult2b <= l2;
operation_nd6 <= '1';
mult3a <= result_sub1;
mult3b <= l3;
operation_nd7 <= '1';
mult4a <= result_sub1;
mult4b <= l4;
operation_nd8 <= '1';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Six;
when Six =>
add1a <= result_add1;
add1b <= result_mult1;
operation_nd1 <= '1';
vX1 <= result_add1;
add2a <= result_add2;
add2b <= result_mult2;
operation_nd2 <= '1';
vX2 <= result_add2;
add3a <= result_add3;
add3b <= result_mult3;
operation_nd3 <= '1';
vX3 <= result_add3;
add4a <= result_add4;
add4b <= result_mult4;
operation_nd4 <= '1';
vX4 <= result_add4;
mult1a <= (others => '0');
mult1b <= (others => '0');
operation_nd5 <= '0';
mult2a <= (others => '0');
mult2b <= (others => '0');
operation_nd6 <= '0';
mult3a <= (others => '0');
mult3b <= (others => '0');
operation_nd7 <= '0';
mult4a <= (others => '0');
mult4b <= (others => '0');
operation_nd8 <= '0';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Seven;
when Seven =>
vX1 <= result_add1;
vX2 <= result_add2;
vX3 <= result_add3;
vX4 <= result_add4;
add1a <= (others=>'0');
add1b <= (others=>'0');
operation_nd1 <= '0';
add2a <= (others=>'0');
add2b <= (others=>'0');
operation_nd2 <= '0';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= result_add1;
mult1b <= k1;
operation_nd5 <= '1';
mult2a <= result_add2;
mult2b <= k2;
operation_nd6 <= '1';
mult3a <= result_add3;
mult3b <= k3;
operation_nd7 <= '1';
mult4a <= result_add4;
mult4b <= k4;
operation_nd8 <= '1';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Eight;
when Eight =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= (others => '0');
mult1b <= (others => '0');
operation_nd5 <= '0';
mult2a <= (others => '0');
mult2b <= (others => '0');
operation_nd6 <= '0';
mult3a <= (others => '0');
mult3b <= (others => '0');
operation_nd7 <= '0';
mult4a <= (others => '0');
mult4b <= (others => '0');
operation_nd8 <= '0';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Nine;
when Nine =>
add1a <= result_add1;
add1b <= result_add2;
operation_nd1 <= '1';
add2a <= (others=>'0');
add2b <= (others=>'0');
operation_nd2 <= '0';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= (others => '0');
mult1b <= (others => '0');
operation_nd5 <= '0';
mult2a <= (others => '0');
mult2b <= (others => '0');
operation_nd6 <= '0';
mult3a <= (others => '0');
mult3b <= (others => '0');
operation_nd7 <= '0';
mult4a <= (others => '0');
mult4b <= (others => '0');
operation_nd8 <= '0';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= One;
when others =>
mult1a <= (others => '0');
mult1b <= (others => '0');
mult2a <= (others => '0');
mult2b <= (others => '0');
mult3a <= (others => '0');
mult3b <= (others => '0');
mult4a <= (others => '0');
mult4b <= (others => '0');
add1a <= (others => '0');
add1b <= (others => '0');
add2a <= (others => '0');
add2b <= (others => '0');
add3a <= (others => '0');
add3b <= (others => '0');
add4a <= (others => '0');
add4b <= (others => '0');
sub1a <= (others => '0');
sub1b <= (others => '0');
vresult <= (others => '0');
vX1 <= (others => '0');
vX2 <= (others => '0');
vX3 <= (others => '0');
vX4 <= (others => '0');
vKX <= (others => '0');
vCX <= (others => '0');
vRminusKX <= (others => '0');
vSensorMinusCX <= (others => '0');
vInter_add1 <= (others => '0');
vInter_add2 <= (others => '0');
vInter_add3 <= (others => '0');
vInter_add4 <= (others => '0');
vInter_misc1 <= (others => '0');
vInter_misc2 <= (others => '0');
DAC1out <= (others => '0');
DAC2out <= (others => '0');
operation_nd1 <= '0';
operation_nd2 <= '0';
operation_nd3 <= '0';
operation_nd4 <= '0';
operation_nd5 <= '0';
operation_nd6 <= '0';
operation_nd7 <= '0';
operation_nd8 <= '0';
operation_nd9 <= '0';
state <= One;
end case;
end if;
end process;
end Behavioral;
|
mit
|
f044a0b87c9d236bcd5ffd7c8d9079d8
| 0.51382 | 2.910258 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/component/Alu.vhd
| 1 | 6,021 |
----------------------------------------
-- 32 BIT ALU --
-- PORT MAPPING --
-- A: 32 bit input value --
-- B: 32 bit input value --
-- CIN: 1 bit input carry --
-- FUN: 4 bit input function selector --
-- 0 - ZERO --
-- 1 - ADD --
-- 2 - SUBTRACT --
-- 3 - PASS --
-- 4 - NOT --
-- 5 - AND --
-- 6 - OR --
-- 7 - XOR --
-- 8 - XNOR --
-- 9 - PASS B --
-- 10 - --
-- 11 - --
-- 12 - --
-- 13 - --
-- 14 - --
-- 15 - --
----------------------------------------
-- C: 32 bit output value --
-- STATUS: 4 bit status output --
-- 0 - ZERO --
-- 1 - CARRY --
-- 2 - SIGN --
-- 3 - OVERFLOW --
----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY alu IS
PORT
(
in_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_cin : IN STD_LOGIC;
in_fun : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
---------------------------------------------------------------
out_c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_status : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0)
);
END alu;
ARCHITECTURE behavioral OF alu IS
-- Adder result signals
SIGNAL s_add : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_cout : STD_LOGIC;
-- Subtractor result signals
SIGNAL s_sub : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_bout : STD_LOGIC;
-- Output signals
SIGNAL s_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_status : STD_LOGIC_VECTOR( 3 DOWNTO 0);
BEGIN
-- Instantiate adder
a: ENTITY WORK.adder(behavioral)
PORT MAP
(
in_a,
in_b,
in_cin,
s_add,
s_cout
);
-- Instantiate subtractor
s: ENTITY WORK.adder(behavioral)
PORT MAP
(
in_a,
NOT(in_b),
NOT(in_cin),
s_sub,
s_bout
);
out_c <= s_out;
out_status <= s_status;
-- Multiplexers set outputs using function code
PROCESS(in_a, in_b, in_cin, in_fun, s_out, s_status, s_add, s_cout, s_sub, s_bout)
BEGIN
CASE in_fun is
-- ZERO
WHEN "0000" =>
-- Set all outputs to 0
s_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, s_out'LENGTH));
s_status <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, s_status'LENGTH));
-- ADD
WHEN "0001" =>
-- Set output to result of adder
s_out <= s_add;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= s_cout;
s_status(2) <= s_out(31);
s_status(3) <= s_cout;
-- SUBTRACT
WHEN "0010" =>
-- Set output to result of subtractor
s_out <= s_sub;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= NOT(s_bout);
s_status(2) <= s_out(31);
s_status(3) <= NOT(s_bout);
-- PASS A
WHEN "0011" =>
-- Set output to input a
s_out <= in_a;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- NOT
WHEN "0100" =>
-- Set output to not a
s_out <= NOT(in_a);
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- AND --
WHEN "0101" =>
-- Set output to a and b
s_out <= in_a AND in_b;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- OR --
WHEN "0110" =>
-- Set output to a or b
s_out <= in_a OR in_b;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- XOR
WHEN "0111" =>
-- Set output to a xor b
s_out <= in_a XOR in_b;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- XNOR
WHEN "1000" =>
-- Set output to a xnor b
s_out <= NOT(in_a XOR in_b);
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
-- NOOP OPCODES for future expansion
-- PASS B
WHEN "1001" =>
-- Set output to input b
s_out <= in_b;
-- Set status values
IF(TO_INTEGER(UNSIGNED(s_out)) = 0) THEN
s_status(0) <= '1';
ELSE
s_status(0) <= '0';
END IF;
s_status(1) <= '0';
s_status(2) <= s_out(31);
s_status(3) <= '0';
WHEN OTHERS =>
-- Set all outputs to 0
s_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, s_out'LENGTH));
s_status <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, s_status'LENGTH));
END CASE;
END PROCESS;
END behavioral;
|
mit
|
ff9ad0e7fdf3aaeee230b67f41fdf76d
| 0.429829 | 2.989573 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/resampler.vhd
| 1 | 15,152 |
-- Audio Resampler And Filter for Konami Arcade Chassis Emulator
-- Copyright (C) 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
-- The main clock is 12288000 Hz, where an 18-bit output audio sample is
-- delivered every 256 clocks at 48000 Hz.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity resampler is
port (
clk: in std_logic;
reset: in std_logic;
psgclk: out std_logic;
psgnew: out std_logic; -- high when a new sample taken
sample_1: in std_logic_vector(7 downto 0);
select_1: out std_logic_vector(1 downto 0);
chan1_en: in std_logic_vector(2 downto 0); -- CBA enables
chan1_filt: in std_logic_vector(5 downto 0); -- 2-bits each for CBA
sample_2: in std_logic_vector(7 downto 0);
select_2: out std_logic_vector(1 downto 0);
chan2_en: in std_logic_vector(2 downto 0); -- CBA enables
chan2_filt: in std_logic_vector(5 downto 0); -- 2-bits each for CBA
audio: out std_logic_vector(17 downto 0);
audio_en: out std_logic -- high for one clock when the samples
-- are taken by the sink
);
attribute SIGIS : string;
attribute SIGIS of clk : signal is "CLK";
attribute SIGIS of reset : signal is "RST";
end entity resampler;
-------------------------------------------------------------------------------
architecture behaviour of resampler is
signal head : unsigned(4 downto 0);
signal local_sample_en, start_filt, output_en : std_logic;
type psgbuf is array (0 to 31) of signed(23 downto 0);
signal psg1a, psg1b, psg1c, psg2a, psg2b, psg2c : psgbuf;
signal clk3of5, clk18432 : std_logic;
signal clk96, clk48 : std_logic;
signal countB : unsigned(7 downto 0);
-- 32 bits in 9.23 format
signal filt1a, filt1b, filt1c,
filt2a, filt2b, filt2c : signed(31 downto 0);
-- indices into filters
signal fix1a, fix1b, fix1c, fix2a, fix2b, fix2c : integer;
begin
-- map filter indices
fix1a <= to_integer(unsigned(chan1_filt(1 downto 0)));
fix1b <= to_integer(unsigned(chan1_filt(3 downto 2)));
fix1c <= to_integer(unsigned(chan1_filt(5 downto 4)));
fix2a <= to_integer(unsigned(chan2_filt(1 downto 0)));
fix2b <= to_integer(unsigned(chan2_filt(3 downto 2)));
fix2c <= to_integer(unsigned(chan2_filt(5 downto 4)));
-- generate a 3-of-5, 96k and 48k
gen3of5 : process( clk, reset ) is
variable countA : unsigned(2 downto 0);
begin
if reset = '1' then
countA := "000";
countB <= X"00";
clk3of5 <= '0';
elsif clk'event and clk = '1' then
countB <= countB - 1;
if countA = 4 then
countA := "000";
else
countA := countA + 1;
end if;
if (countA = 0) or (countA = 2) or (countA = 4) then
clk3of5 <= not clk3of5;
end if;
end if;
end process;
clk96 <= std_logic(countB(6));
clk48 <= std_logic(countB(7));
-- generate clocks for the PSG chips
gen18432 : process( clk3of5, reset ) is
begin
if reset = '1' then
clk18432 <= '0';
elsif clk3of5'event and clk3of5 = '1' then
clk18432 <= not clk18432;
end if;
end process;
-- the PSG sampling runs once every 16 at 115200 kHz
psggen : process( clk18432, reset ) is
variable count : unsigned(3 downto 0);
begin
if reset = '1' then
count := "0000";
local_sample_en <= '0';
elsif clk18432'event and clk18432 = '1' then
if (count = 15) then
local_sample_en <= '1';
else
local_sample_en <= '0';
end if;
count := count + 1;
end if;
end process;
psgclk <= clk18432;
psgnew <= local_sample_en;
-- sample the PSG outputs at 115200 Hz, drop 1-of-6 for 96000 Hz
-- original samples are in 0.8 unsigned format, which are extended to 1.8 format,
-- then multiplied by gain in 1.14 format yielding 2.22 format
psggrab : process( clk, reset ) is
variable decount : unsigned(3 downto 0);
type TSTATE is (IDLE, CHANA, CHANB, CHANC, HALT);
variable state : TSTATE := IDLE;
-- constant gain in 1.14 format
type TGAIN is array(0 to 3) of signed(14 downto 0);
constant GAINS : TGAIN := ( "010" & X"023", -- 1/1.9913, 24kHz
"000" & X"35b", -- 1/19.070, 723Hz
"000" & X"45d", -- 1/14.656, 3386Hz
"000" & X"357" -- 1/19.144, 596Hz
);
begin
if reset = '1' then
head <= "00000";
decount := "0000";
state := IDLE;
select_1 <= "11";
select_2 <= "11";
elsif clk'event and clk = '1' then
case state is
when IDLE =>
if local_sample_en = '1' then
if decount /= 5 then
decount := decount + 1;
select_1 <= "00";
select_2 <= "00";
state := CHANA;
else
decount := "0000";
state := HALT;
end if;
end if;
when CHANA =>
if (chan1_en(0) = '1') then
psg1a(to_integer(head)) <= signed('0' & sample_1) * GAINS(fix1a);
else
psg1a(to_integer(head)) <= (others => '0');
end if;
if (chan2_en(0) = '1') then
psg2a(to_integer(head)) <= signed('0' & sample_2) * GAINS(fix2a);
else
psg2a(to_integer(head)) <= (others => '0');
end if;
select_1 <= "01";
select_2 <= "01";
state := CHANB;
when CHANB =>
if (chan1_en(1) = '1') then
psg1b(to_integer(head)) <= signed('0' & sample_1) * GAINS(fix1b);
else
psg1b(to_integer(head)) <= (others => '0');
end if;
if (chan2_en(1) = '1') then
psg2b(to_integer(head)) <= signed('0' & sample_2) * GAINS(fix2b);
else
psg2b(to_integer(head)) <= (others => '0');
end if;
select_1 <= "10";
select_2 <= "10";
state := CHANC;
when CHANC =>
if (chan1_en(2) = '1') then
psg1c(to_integer(head)) <= signed('0' & sample_1) * GAINS(fix1c);
else
psg1c(to_integer(head)) <= (others => '0');
end if;
if (chan2_en(2) = '1') then
psg2c(to_integer(head)) <= signed('0' & sample_2) * GAINS(fix2c);
else
psg2c(to_integer(head)) <= (others => '0');
end if;
head <= head + 1;
state := HALT;
when HALT =>
if local_sample_en = '0' then
state := IDLE;
end if;
when others => null;
end case;
end if;
end process;
start_filt <= '1' when countB(6 downto 0) = 121 -- selected so as to
-- avoid the sampling of
-- the PSGs
else '0';
-- At 96000 Hz, filter the oldest 17 samples for each channel
-- Scaled PSG audio is available in 2.22 format, here truncated to 2.14 bits
-- and MACed against 2.14 coefficients, each multiplication yields a 4.28
-- result.
filt : process( clk, reset )
-- 16 bits in 2.14 format
type TCOEFF is array(0 to 16) of signed(15 downto 0);
constant FILT24K : TCOEFF := (X"ff2e", -- -0.012820
X"00cb", -- 0.012419
X"004d", -- 0.004739
X"fe9f", -- -0.021598
X"0363", -- 0.052918
X"fb42", -- -0.074142
X"f69d", -- -0.146680
X"253d", -- 0.581888
X"4ca8", -- 1.197806
X"253d", -- 0.581888
X"f69d", -- -0.146680
X"fb42", -- -0.074142
X"0363", -- 0.052918
X"fe9f", -- -0.021598
X"004d", -- 0.004739
X"00cb", -- 0.012419
X"ff2e" -- -0.012820
);
constant FILT723 : TCOEFF := (X"463b", -- 1.097387
X"46d0", -- 1.106476
X"4752", -- 1.114392
X"47c0", -- 1.121121
X"481a", -- 1.126646
X"4861", -- 1.130956
X"4894", -- 1.134042
X"48b2", -- 1.135895
X"48bc", -- 1.136514
X"48b2", -- 1.135895
X"4894", -- 1.134042
X"4861", -- 1.130956
X"481a", -- 1.126646
X"47c0", -- 1.121121
X"4752", -- 1.114392
X"46d0", -- 1.106476
X"463b" -- 1.097387
);
constant FILT3K4 : TCOEFF := (X"1da9", -- 0.463487
X"25bf", -- 0.589803
X"2dae", -- 0.713773
X"3520", -- 0.830105
X"3bc0", -- 0.933647
X"4142", -- 1.019685
X"4563", -- 1.084222
X"47f3", -- 1.124215
X"48d1", -- 1.137762
X"47f3", -- 1.124215
X"4563", -- 1.084222
X"4142", -- 1.019685
X"3bc0", -- 0.933647
X"3520", -- 0.830105
X"2dae", -- 0.713773
X"25bf", -- 0.589803
X"1da9" -- 0.463487
);
constant FILT596 : TCOEFF := (X"4702", -- 1.109511
X"4767", -- 1.115719
X"47c0", -- 1.121119
X"480b", -- 1.125701
X"4849", -- 1.129460
X"4879", -- 1.132389
X"489b", -- 1.134485
X"48b0", -- 1.135743
X"48b6", -- 1.136163
X"48b0", -- 1.135743
X"489b", -- 1.134485
X"4879", -- 1.132389
X"4849", -- 1.129460
X"480b", -- 1.125701
X"47c0", -- 1.121119
X"4767", -- 1.115719
X"4702" -- 1.109511
);
type TFILTS is array(0 to 3) of TCOEFF;
variable FILTERS : TFILTS;
variable bindex, findex : unsigned(4 downto 0);
variable idle : std_logic;
begin
if reset = '1' then
bindex := "00000";
findex := "00000";
idle := '1';
FILTERS(0) := FILT24K;
FILTERS(1) := FILT723;
FILTERS(2) := FILT3K4;
FILTERS(3) := FILT596;
elsif clk'event and clk = '1' then
-- determine when to kick off
if (idle = '1') then
if (start_filt = '1') then
idle := '0';
findex := "00000";
bindex := head - 1;
filt1a <= (others => '0');
filt1b <= (others => '0');
filt1c <= (others => '0');
filt2a <= (others => '0');
filt2b <= (others => '0');
filt2c <= (others => '0');
end if;
else
-- FIR MACs
filt1a <= filt1a + (psg1a(to_integer(bindex))(23 downto 8) *
filters(fix1a)(to_integer(findex)));
filt1b <= filt1b + (psg1b(to_integer(bindex))(23 downto 8) *
filters(fix1b)(to_integer(findex)));
filt1c <= filt1c + (psg1c(to_integer(bindex))(23 downto 8) *
filters(fix1c)(to_integer(findex)));
filt2a <= filt2a + (psg2a(to_integer(bindex))(23 downto 8) *
filters(fix2a)(to_integer(findex)));
filt2b <= filt2b + (psg2b(to_integer(bindex))(23 downto 8) *
filters(fix2b)(to_integer(findex)));
filt2c <= filt2c + (psg2c(to_integer(bindex))(23 downto 8) *
filters(fix2c)(to_integer(findex)));
-- index update and termination
if (findex = "10000") then
idle := '1';
else
findex := findex + 1;
bindex := bindex - 1;
end if;
end if;
end if;
end process;
-- the mixer combines all six filtered channels to produce a 1.17 result that
-- is scaled at 6/8ths of full-scale
mix : process( clk, reset )
variable count : unsigned(0 downto 0);
variable idle : std_logic;
variable result : signed(17 downto 0);
begin
if reset = '1' then
audio <= "00" & X"0000";
output_en <= '0';
count := "0";
idle := '1';
result := (others => '0');
elsif clk'event and clk = '1' then
if (idle = '1') then
output_en <= '0';
if (start_filt = '1') then
if (count = "1") then
idle := '0';
end if;
result := filt1a(31 downto 14) +
filt1b(31 downto 14) +
filt1c(31 downto 14) +
filt2a(31 downto 14) +
filt2b(31 downto 14) +
filt2c(31 downto 14);
count := count + 1;
end if;
else
if (start_filt = '0') then
idle := '1';
output_en <= '1';
audio <= std_logic_vector( result );
end if;
end if;
end if;
end process;
audio_en <= output_en;
end architecture behaviour;
|
gpl-2.0
|
62b36335c00ecf51964022ccce212c8c
| 0.450898 | 3.800351 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab11_MemoryArbiter/lab11_MemoryArbiter_lib/hdl/memoryarbiter_struct.vhd
| 1 | 3,122 |
-- VHDL Entity lab11_MemoryArbiter_lib.MemoryArbiter.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 02:31:01 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY MemoryArbiter IS
PORT(
Addr_fromFetchStage : IN std_logic_vector (15 DOWNTO 0);
Addr_fromMemStage : IN std_logic_vector (15 DOWNTO 0);
R : IN std_logic;
W : IN std_logic;
reset : IN std_logic;
Addr_toMemory : OUT std_logic_vector (15 DOWNTO 0);
Write_Control : OUT std_logic;
mdelay_toFetchStage : OUT std_logic;
mdelay_toMemStage : OUT std_logic
);
-- Declarations
END MemoryArbiter ;
--
-- VHDL Architecture lab11_MemoryArbiter_lib.MemoryArbiter.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 02:31:01 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF MemoryArbiter IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL dout2 : std_logic;
-- Implicit buffer signal declarations
SIGNAL mdelay_toFetchStage_internal : std_logic;
BEGIN
-- ModuleWare code(v1.12) for instance 'ZERO' of 'constval'
mdelay_toMemStage <= '0';
-- ModuleWare code(v1.12) for instance 'ZERO_a' of 'constval'
dout <= '0';
-- ModuleWare code(v1.12) for instance 'ZERO_b' of 'constval'
dout2 <= '0';
-- ModuleWare code(v1.12) for instance 'U_0' of 'mux'
u_0combo_proc: PROCESS(dout1, dout, reset)
BEGIN
CASE reset IS
WHEN '0' => mdelay_toFetchStage_internal <= dout1;
WHEN '1' => mdelay_toFetchStage_internal <= dout;
WHEN OTHERS => mdelay_toFetchStage_internal <= 'X';
END CASE;
END PROCESS u_0combo_proc;
-- ModuleWare code(v1.12) for instance 'WE_MUX' of 'mux'
we_muxcombo_proc: PROCESS(W, dout2, reset)
BEGIN
CASE reset IS
WHEN '0' => Write_Control <= W;
WHEN '1' => Write_Control <= dout2;
WHEN OTHERS => Write_Control <= 'X';
END CASE;
END PROCESS we_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'to_MemAddr_MUX' of 'mux'
to_memaddr_muxcombo_proc: PROCESS(Addr_fromFetchStage,
Addr_fromMemStage,
mdelay_toFetchStage_internal)
BEGIN
CASE mdelay_toFetchStage_internal IS
WHEN '0' => Addr_toMemory <= Addr_fromFetchStage;
WHEN '1' => Addr_toMemory <= Addr_fromMemStage;
WHEN OTHERS => Addr_toMemory <= (OTHERS => 'X');
END CASE;
END PROCESS to_memaddr_muxcombo_proc;
-- ModuleWare code(v1.12) for instance 'toMemAddr_Control' of 'or'
dout1 <= R OR W;
-- Instance port mappings.
-- Implicit buffered output assignments
mdelay_toFetchStage <= mdelay_toFetchStage_internal;
END struct;
|
gpl-2.0
|
bd077372347062b967593c07bb36210c
| 0.615951 | 3.655738 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab10_RegFile/lab10_RegFile_lib/hdl/Reg_Behavior.vhd
| 1 | 713 |
--
-- VHDL Architecture lab10_RegFile_lib.Reg.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 22:38:44 04/ 8/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Reg IS
GENERIC(size: positive := 16);
PORT( d: IN std_logic_vector (size-1 downto 0);
q: OUT std_logic_vector (size-1 downto 0) := (others=>'0');
c,e: IN std_logic);
END ENTITY Reg;
ARCHITECTURE Behavior OF Reg IS
BEGIN
PROCESS(c)
BEGIN
IF(rising_edge(c) and e='1') THEN
q <= d;
END IF;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
f853e360089390c9115661069107ed30
| 0.57784 | 3.316279 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_addsub_dbl.vhd
| 1 | 19,361 |
-------------------------------------------------------------------------------
--
-- Title : fp23_addsub_dbl
-- Design : FFT
-- Author : Kapitanov Alexander
-- Company :
-- E-mail : [email protected]
--
-------------------------------------------------------------------------------
--
-- Description : floating point adder and subtractor into one entity
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.reduce_pack.or_reduce;
use work.fp_m1_pkg.fp23_data;
library unisim;
use unisim.vcomponents.DSP48E1;
use unisim.vcomponents.DSP48E2;
entity fp23_addsub_dbl is
generic (
USE_MLT : boolean:=FALSE; --! Use DSP48E1/2 blocks or not
XSERIES : string:="7SERIES" --! Xilinx series: ULTRA / 7SERIES
);
port (
aa : in fp23_data; --! Summand/Minuend A
bb : in fp23_data; --! Summand/Substrahend B
cc_add : out fp23_data; --! Sum C
cc_sub : out fp23_data; --! Dif C
reset : in std_logic; --! '0' - Reset
enable : in std_logic; --! Input data enable
valid : out std_logic; --! Output data valid
clk : in std_logic --! Clock
);
end fp23_addsub_dbl;
architecture fp23_addsub_dbl of fp23_addsub_dbl is
type std_logic_array_5xn is array (4 downto 0) of std_logic_vector(5 downto 0);
signal aa_z : fp23_data;
signal b1_z : fp23_data;
signal b2_z : fp23_data;
signal comp : std_logic_vector(22 downto 0);
signal muxa_man : std_logic_vector(15 downto 0);
signal muxb_man : std_logic_vector(15 downto 0);
signal muxa_exp : std_logic_vector(5 downto 0);
signal muxb_exp : std_logic_vector(5 downto 0);
signal mux1_sig : std_logic;
signal mux2_sig : std_logic;
signal exp_dif : std_logic_vector(5 downto 0);
signal impl_a : std_logic;
signal impl_b : std_logic;
signal man_az : std_logic_vector(16 downto 0);
signal subtract : std_logic_vector(1 downto 0);
signal sub_dsp : std_logic;
signal msb_num1 : std_logic_vector(4 downto 0);
signal msb_num2 : std_logic_vector(4 downto 0);
signal msb_dec1 : std_logic_vector(15 downto 0);
signal msb_dec2 : std_logic_vector(15 downto 0);
signal expc1 : std_logic_vector(5 downto 0);
signal expc2 : std_logic_vector(5 downto 0);
signal frac1 : std_logic_vector(15 downto 0);
signal frac2 : std_logic_vector(15 downto 0);
signal set_zero1 : std_logic;
signal set_zero2 : std_logic;
signal new_man1 : std_logic_vector(15 downto 0);
signal new_man2 : std_logic_vector(15 downto 0);
signal expaz : std_logic_array_5xn;
signal sign_1 : std_logic_vector(5 downto 0);
signal sign_2 : std_logic_vector(5 downto 0);
signal dout_val_v : std_logic_vector(7 downto 0);
signal exp_a0 : std_logic;
signal exp_b0 : std_logic;
signal exp_ab : std_logic;
signal exp_zz : std_logic_vector(5 downto 0);
begin
---- add or sub operation ----
aa_z <= aa when rising_edge(clk);
pr_addsub: process(clk) is
begin
if rising_edge(clk) then
b1_z <= bb;
b2_z <= (bb.exp, not bb.sig, bb.man);
end if;
end process;
exp_a0 <= or_reduce(aa.exp) when rising_edge(clk);
exp_b0 <= or_reduce(bb.exp) when rising_edge(clk);
exp_ab <= not (exp_a0 or exp_b0) when rising_edge(clk);
exp_zz <= exp_zz(exp_zz'left-1 downto 0) & exp_ab when rising_edge(clk);
---- check difference (least/most attribute) ----
pr_ex: process(clk) is
begin
if rising_edge(clk) then
comp <= ('0' & aa.exp & aa.man) - ('0' & bb.exp & bb.man);
end if;
end process;
---- data switch multiplexer ----
pr_mux: process(clk) is
begin
if rising_edge(clk) then
if (comp(22) = '1') then
muxa_man <= b1_z.man;
muxa_exp <= b1_z.exp;
muxb_man <= aa_z.man;
muxb_exp <= aa_z.exp;
mux1_sig <= b1_z.sig;
mux2_sig <= b2_z.sig;
else
muxa_man <= aa_z.man;
muxa_exp <= aa_z.exp;
muxb_man <= b1_z.man;
muxb_exp <= b1_z.exp;
mux1_sig <= aa_z.sig;
mux2_sig <= aa_z.sig;
end if;
end if;
end process;
---- implied '1' for fraction ----
pr_imp: process(clk) is
begin
if rising_edge(clk) then
if (comp(22) = '1') then
impl_a <= exp_b0;
impl_b <= exp_a0;
else
impl_a <= exp_a0;
impl_b <= exp_b0;
end if;
end if;
end process;
---- Find exponent ----
exp_dif <= muxa_exp - muxb_exp when rising_edge(clk);
pr_manz: process(clk) is
begin
if rising_edge(clk) then
subtract <= subtract(subtract'left-1 downto 0) & (aa.sig xor bb.sig);
sub_dsp <= subtract(1);
end if;
end process;
man_az <= impl_a & muxa_man when rising_edge(clk);
xUSE_DSP48: if (USE_MLT = TRUE) generate
constant CONST_ONE : std_logic_vector(15 downto 0):=x"8000";
signal dsp_aa : std_logic_vector(29 downto 0);
signal dsp_bb : std_logic_vector(17 downto 0);
signal dsp_cc : std_logic_vector(47 downto 0);
signal sum_man1 : std_logic_vector(47 downto 0);
signal sum_man2 : std_logic_vector(47 downto 0);
signal shift_man : std_logic_vector(15 downto 0);
signal alu_add : std_logic_vector(3 downto 0):=x"0";
signal alu_sub : std_logic_vector(3 downto 0):=x"0";
signal dsp_mlt : std_logic;
signal dsp_res : std_logic;
begin
---- Reset DSP nodes ----
pr_mlt: process(clk) is
begin
if rising_edge(clk) then
if (exp_dif(5 downto 4) = "00") then
dsp_res <= '0';
else
dsp_res <= '1';
end if;
end if;
end process;
---- Shift vector for fraction ----
shift_man <= STD_LOGIC_VECTOR(SHR(UNSIGNED(CONST_ONE), UNSIGNED(exp_dif(4 downto 0)))) when rising_edge(clk);
pr_manz: process(clk) is
begin
if rising_edge(clk) then
alu_add <= "00" & sub_dsp & sub_dsp;
alu_sub <= "00" & not(sub_dsp) & not(sub_dsp);
end if;
end process;
---- Find fraction by using DSP48 ----
dsp_aa(16 downto 00) <= impl_b & muxb_man;
dsp_aa(29 downto 17) <= (others=>'0');
dsp_bb <= "00" & shift_man;
dsp_cc(14 downto 00) <= (others =>'0');
dsp_cc(31 downto 15) <= man_az when rising_edge(clk);
dsp_cc(47 downto 32) <= (others =>'0');
xDSP48E1: if (XSERIES = "7SERIES") generate
align_add: DSP48E1
generic map (
ALUMODEREG => 1,
ADREG => 0,
AREG => 2,
BCASCREG => 0,
BREG => 0,
CREG => 1,
DREG => 0,
MREG => 1,
PREG => 1
)
port map (
P => sum_man1,
A => dsp_aa,
ACIN => (others=>'0'),
ALUMODE => alu_add,
B => dsp_bb,
BCIN => (others=>'0'),
C => dsp_cc,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others=>'0'),
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
CLK => clk,
D => (others=>'0'),
INMODE => "00000",
MULTSIGNIN => '0',
OPMODE => "0110101",
PCIN => (others=>'0'),
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => dsp_res,
RSTP => reset
);
align_sub: DSP48E1
generic map (
ALUMODEREG => 1,
ADREG => 0,
AREG => 2,
BCASCREG => 0,
BREG => 0,
CREG => 1,
DREG => 0,
MREG => 1,
PREG => 1
)
port map (
P => sum_man2,
A => dsp_aa,
ACIN => (others=>'0'),
ALUMODE => alu_sub,
B => dsp_bb,
BCIN => (others=>'0'),
C => dsp_cc,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others=>'0'),
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
CLK => clk,
D => (others=>'0'),
INMODE => "00000",
MULTSIGNIN => '0',
OPMODE => "0110101",
PCIN => (others=>'0'),
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => dsp_res,
RSTP => reset
);
end generate;
xDSP48E2: if (XSERIES = "ULTRA") generate
align_add: DSP48E2
generic map (
ALUMODEREG => 1,
ADREG => 0,
AREG => 2,
BCASCREG => 0,
BREG => 0,
CREG => 1,
DREG => 0,
MREG => 1,
PREG => 1
)
port map (
P => sum_man1,
A => dsp_aa,
ACIN => (others=>'0'),
ALUMODE => alu_add,
B => dsp_bb,
BCIN => (others=>'0'),
C => dsp_cc,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others=>'0'),
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
CLK => clk,
D => (others=>'0'),
INMODE => "00000",
MULTSIGNIN => '0',
OPMODE => "000110101",
PCIN => (others=>'0'),
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => dsp_res,
RSTP => reset
);
align_sub: DSP48E2
generic map (
ALUMODEREG => 1,
ADREG => 0,
AREG => 2,
BCASCREG => 0,
BREG => 0,
CREG => 1,
DREG => 0,
MREG => 1,
PREG => 1
)
port map (
P => sum_man2,
A => dsp_aa,
ACIN => (others=>'0'),
ALUMODE => alu_sub,
B => dsp_bb,
BCIN => (others=>'0'),
C => dsp_cc,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => (others=>'0'),
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
CLK => clk,
D => (others=>'0'),
INMODE => "00000",
MULTSIGNIN => '0',
OPMODE => "000110101",
PCIN => (others=>'0'),
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => dsp_res,
RSTP => reset
);
end generate;
msb_dec1 <= sum_man1(32 downto 17);
msb_dec2 <= sum_man2(32 downto 17);
pr_del: process(clk) is
begin
if rising_edge(clk) then
new_man1 <= sum_man1(31 downto 16);
new_man2 <= sum_man2(31 downto 16);
new_man1 <= sum_man1(31 downto 16);
new_man2 <= sum_man2(31 downto 16);
end if;
end process;
end generate;
xUSE_LOGIC: if (USE_MLT = FALSE) generate
signal norm_man : std_logic_vector(16 downto 0);
signal diff_man : std_logic_vector(16 downto 0);
signal diff_exp : std_logic_vector(1 downto 0);
signal addsub : std_logic;
signal sumdif : std_logic;
signal sum_mt1 : std_logic_vector(17 downto 0);
signal sum_mt2 : std_logic_vector(17 downto 0);
signal man_shift : std_logic_vector(16 downto 0);
signal man_az1 : std_logic_vector(16 downto 0);
signal man_az2 : std_logic_vector(16 downto 0);
begin
man_shift <= impl_b & muxb_man when rising_edge(clk);
norm_man <= STD_LOGIC_VECTOR(SHR(UNSIGNED(man_shift), UNSIGNED(exp_dif(3 downto 0)))) when rising_edge(clk);
diff_exp <= exp_dif(5 downto 4) when rising_edge(clk);
pr_norm_man: process(clk) is
begin
if rising_edge(clk) then
if (diff_exp = "00") then
diff_man <= norm_man;
else
diff_man <= (others => '0');
end if;
end if;
end process;
addsub <= not sub_dsp when rising_edge(clk);
sumdif <= addsub when rising_edge(clk);
-- sum of fractions --
pr_man: process(clk) is
begin
if rising_edge(clk) then
man_az1 <= man_az;
man_az2 <= man_az1;
if (sumdif = '1') then
sum_mt1 <= ('0' & man_az2) + ('0' & diff_man);
else
sum_mt1 <= ('0' & man_az2) - ('0' & diff_man);
end if;
if (sumdif = '1') then
sum_mt2 <= ('0' & man_az2) - ('0' & diff_man);
else
sum_mt2 <= ('0' & man_az2) + ('0' & diff_man);
end if;
end if;
end process;
msb_dec1 <= sum_mt1(17 downto 2);
msb_dec2 <= sum_mt2(17 downto 2);
new_man1 <= sum_mt1(16 downto 1) when rising_edge(clk);
new_man2 <= sum_mt2(16 downto 1) when rising_edge(clk);
end generate;
---- find MSB (highest '1' position) ----
pr_align: process(clk) is
begin
if rising_edge(clk) then
---- Add ----
if (msb_dec1(15-00)='1') then msb_num1 <= "00000";
elsif (msb_dec1(15-01)='1') then msb_num1 <= "00001";
elsif (msb_dec1(15-02)='1') then msb_num1 <= "00010";
elsif (msb_dec1(15-03)='1') then msb_num1 <= "00011";
elsif (msb_dec1(15-04)='1') then msb_num1 <= "00100";
elsif (msb_dec1(15-05)='1') then msb_num1 <= "00101";
elsif (msb_dec1(15-06)='1') then msb_num1 <= "00110";
elsif (msb_dec1(15-07)='1') then msb_num1 <= "00111";
elsif (msb_dec1(15-08)='1') then msb_num1 <= "01000";
elsif (msb_dec1(15-09)='1') then msb_num1 <= "01001";
elsif (msb_dec1(15-10)='1') then msb_num1 <= "01010";
elsif (msb_dec1(15-11)='1') then msb_num1 <= "01011";
elsif (msb_dec1(15-12)='1') then msb_num1 <= "01100";
elsif (msb_dec1(15-13)='1') then msb_num1 <= "01101";
elsif (msb_dec1(15-14)='1') then msb_num1 <= "01110";
elsif (msb_dec1(15-15)='1') then msb_num1 <= "01111";
else msb_num1 <= "11111";
end if;
---- Sub ----
if (msb_dec2(15-00)='1') then msb_num2 <= "00000";
elsif (msb_dec2(15-01)='1') then msb_num2 <= "00001";
elsif (msb_dec2(15-02)='1') then msb_num2 <= "00010";
elsif (msb_dec2(15-03)='1') then msb_num2 <= "00011";
elsif (msb_dec2(15-04)='1') then msb_num2 <= "00100";
elsif (msb_dec2(15-05)='1') then msb_num2 <= "00101";
elsif (msb_dec2(15-06)='1') then msb_num2 <= "00110";
elsif (msb_dec2(15-07)='1') then msb_num2 <= "00111";
elsif (msb_dec2(15-08)='1') then msb_num2 <= "01000";
elsif (msb_dec2(15-09)='1') then msb_num2 <= "01001";
elsif (msb_dec2(15-10)='1') then msb_num2 <= "01010";
elsif (msb_dec2(15-11)='1') then msb_num2 <= "01011";
elsif (msb_dec2(15-12)='1') then msb_num2 <= "01100";
elsif (msb_dec2(15-13)='1') then msb_num2 <= "01101";
elsif (msb_dec2(15-14)='1') then msb_num2 <= "01110";
elsif (msb_dec2(15-15)='1') then msb_num2 <= "01111";
else msb_num2 <= "11111";
end if;
end if;
end process;
frac1 <= STD_LOGIC_VECTOR(SHL(UNSIGNED(new_man1), UNSIGNED(msb_num1(3 downto 0)))) when rising_edge(clk);
frac2 <= STD_LOGIC_VECTOR(SHL(UNSIGNED(new_man2), UNSIGNED(msb_num2(3 downto 0)))) when rising_edge(clk);
set_zero1 <= msb_num1(4);
set_zero2 <= msb_num2(4);
---- exponent increment ----
pr_expx: process(clk) is
begin
if rising_edge(clk) then
---- Set ones (error of rounding fp data) ----
if (set_zero1 = '0') then
if (expaz(4) < ('0' & msb_num1)) then
expc1 <= "000000";
else
expc1 <= expaz(4) - msb_num1 + '1';
end if;
else
expc1 <= "000000";
end if;
if (set_zero2 = '0') then
if (expaz(4) < ('0' & msb_num2)) then
expc2 <= "000000";
else
expc2 <= expaz(4) - msb_num2 + '1';
end if;
else
expc2 <= "000000";
end if;
end if;
end process;
---- exp & sign delay ----
pr_expz: process(clk) is
begin
if rising_edge(clk) then
expaz <= expaz(expaz'left-1 downto 0) & muxa_exp;
sign_1 <= sign_1(sign_1'left-1 downto 0) & mux1_sig;
sign_2 <= sign_2(sign_2'left-1 downto 0) & mux2_sig;
end if;
end process;
---- output product ----
pr_dout: process(clk) is
begin
if rising_edge(clk) then
if (exp_zz(exp_zz'left) = '1') then
cc_add <= ("000000", '0', x"0000");
cc_sub <= ("000000", '0', x"0000");
else
cc_add <= (expc1, sign_1(sign_1'left), frac1);
cc_sub <= (expc2, sign_2(sign_2'left), frac2);
end if;
end if;
end process;
dout_val_v <= dout_val_v(dout_val_v'left-1 downto 0) & enable when rising_edge(clk);
valid <= dout_val_v(dout_val_v'left) when rising_edge(clk);
end fp23_addsub_dbl;
|
mit
|
060766b5c9782e70fc3289cdc203b513
| 0.505656 | 2.892724 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/util/Adder.vhd
| 1 | 2,226 |
------------------------------------
-- 32 BIT CARRY LOOK AHEAD ADDER --
-- PORT MAPPING --
-- A : 32 bit input value --
-- B : 32 bit input value --
-- CIN : 1 bit input carry --
------------------------------------
-- C : 32 bit output value A+B --
-- COUT : 1 bit output carry --
------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder IS
PORT
(
in_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_cin : IN STD_LOGIC;
---------------------------------------------
out_c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_cout : OUT STD_LOGIC
);
END adder;
ARCHITECTURE behavioral OF adder IS
-- Sum values without carry
SIGNAL s_sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Carry generators
SIGNAL s_generate : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Carry propagators
SIGNAL s_propagate : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Calculated carry values
SIGNAL s_carry : STD_LOGIC_VECTOR(31 DOWNTO 1);
BEGIN
-- Calculate the sum a + b discarding carry
s_sum <= in_a XOR in_b;
-- Calculate carry generators
s_generate <= in_a AND in_b;
-- Calculate carry propagators
s_propagate <= in_a OR in_b;
-- Pre calculate each carry
PROCESS(s_generate, s_propagate, s_carry, in_cin)
BEGIN
-- C(i+1) = G(i) + (P(i)C(i))
-- Calculate base case
s_carry(1) <= s_generate(0) OR (s_propagate(0) AND in_cin);
FOR i IN 1 TO 30 LOOP
-- Recursively calculate all intermediate carries
s_carry(i + 1) <= s_generate(i) OR (s_propagate(i) AND s_carry(i));
END LOOP;
-- Calculate carry out --
out_cout <= s_generate(31) OR (s_propagate(31) AND s_carry(31));
END PROCESS;
-- Calculate final sum --
out_c(0) <= s_sum(0) XOR in_cin;
out_c(31 DOWNTO 1) <= s_sum(31 DOWNTO 1) XOR s_carry(31 DOWNTO 1);
END behavioral;
|
mit
|
beb2d6425c69d78f1067573a22b00ebe
| 0.483827 | 3.596123 | false | false | false | false |
KimSJ/HDLC_chip
|
hdlctransmitter_tb.vhd
| 1 | 2,148 |
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity HdlcTransmitter_tb is
end HdlcTransmitter_tb;
architecture behavioural of HdlcTransmitter_tb is
component HdlcTransmitter is
generic (
TxReqChainSize : integer := 2 -- defines length of metastability chain; must be at least two.
);
port (
-- microprocesser interface
Din : in Std_Logic_Vector (7 downto 0); -- Tx register
TxLast : in Std_Logic;
TxWR : in Std_Logic;
TxReq : out Std_Logic; -- high if space in register
TxRST : in Std_Logic;
-- bit clock := '0'
TxCLK : in Std_Logic;
-- line interface := '0'
TxD : buffer Std_Logic;
TxEn : buffer Std_Logic
);
end component HdlcTransmitter;
signal Din : Std_Logic_Vector (7 downto 0); -- Tx register
signal TxLast : Std_Logic := '0';
signal TxWR : Std_Logic := '0';
signal TxReq : Std_Logic; -- high if space in register
signal TxRST : Std_Logic := '0';
-- bit clock
signal TxCLK : Std_Logic;
-- line interface
signal TxD : Std_Logic;
signal TxEn : Std_Logic;
signal byteCount : integer := 0;
begin
transmitter : HdlcTransmitter PORT MAP (Din, TxLast, TxWR , TxReq, TxRST, TxCLK, TxD, TxEn);
process
-- drive the txClock
begin
txCLK <= '0';
wait for 20 us;
txCLK <= '1';
wait for 20 us;
end process;
TxRST <= '0' after 0 us, '1' after 1 us, '0' after 2 us;
process (TxReq)
-- write another byte
type tDataStream is array (0 to 8) of Std_Logic_Vector(7 downto 0);
variable dataStream : tDataStream :=
(
x"AA",
x"00",
x"3C",
x"FF",
x"0F",
x"F0",
x"55",
x"49",
x"54"
);
begin
if rising_edge(TxReq) then
byteCount <= (byteCount + 1) mod 9;
if byteCount > 5 then
TxLast <= '1';
else
TxLast <= '0';
end if;
Din <= datastream(byteCount);
TxWR <= '1' after 10 ns, '0' after 100 ns;
end if;
-- Din <= "00001000" after 0 us, "00000000" after 100 us, "00001111" after 200 us, "00001010" after 300 us, "00000000" after 500 us, "00000000" after 600 us;
end process;
end behavioural;
|
gpl-3.0
|
b9699b8e264a350bf30bad6b00f4e9c0
| 0.636406 | 2.84127 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd
| 1 | 4,378 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
768280fe9f50f0e6e89b8f36407e7b0e
| 0.574692 | 4.632804 | false | false | false | false |
ymahajan456/HighLevelSynthesis
|
Version_1.0/Testing/ALU.vhd
| 1 | 2,182 |
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
--alu_ops_map = {
-- "+": "000",
-- "-": "001",
-- "*": "010",
-- "/": "011",
-- "!": "100",
-- "&": "101",
-- "^": "110",
-- "|": "111"
-- }
ENTITY ALU IS
GENERIC(
data_width: INTEGER := 16);
PORT(
in_1: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
in_2: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
sel: IN STD_LOGIC_VECTOR( 0 TO 2 ) := (others => '0'));
END ENTITY;
architecture alu_le_le of ALU is
signal add_out, sub_out, mul_out, div_out, not_out, and_out, xor_out, or_out: std_logic_vector(0 to data_width-1) := (others => '0');
begin
process(in_1, in_2)
begin
add_out <= std_logic_vector((unsigned(in_1)) + (unsigned(in_2)));-- after 2 ns;
--sub_out <= std_logic_vector(to_integer(unsigned(in_1)) - to_integer(unsigned(in_2)));-- after 2 ns;
--mul_out <= std_logic_vector(to_integer(unsigned(in_1)) * to_integer(unsigned(in_2)));-- after 3 ns;
--div_out <= std_logic_vector(to_integer(unsigned(in_1)) / to_integer(unsigned(in_2)));-- after 3 ns;
or_out <= in_1 or in_2;-- after 1 ns;
and_out <= in_1 and in_2;-- after 1 ns;
not_out <= not in_1;-- after 1 ns;
xor_out <= in_1 xor in_2;-- after 1 ns;
end process;
process(sel,add_out,sub_out,mul_out,div_out,or_out,and_out,not_out,xor_out)
begin
if(sel = "000") then
outp <= add_out;
elsif(sel = "001") then
outp <= sub_out;
elsif(sel = "010") then
outp <= mul_out;
elsif(sel = "011") then
outp <= div_out;
elsif(sel = "100") then
outp <= not_out;
elsif(sel = "101") then
outp <= and_out;
elsif(sel = "110") then
outp <= xor_out;
elsif(sel = "111") then
outp <= or_out;
else
outp <= (others => '0');
end if;
end process;
end architecture;
|
gpl-3.0
|
70b24c1d6f50d59156361758966badce
| 0.500458 | 2.948649 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/memory/Register.vhd
| 1 | 1,158 |
-------------------------------------
-- 32 BIT PARALLEL REGISTER --
-- PORT MAPPING --
-- D : 32 bit input data --
-- EN : 1 bit input enable --
-- CLK: 1 bit input clock --
-------------------------------------
-- Q:32g bit output data --
-------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY parallel_register IS
GENERIC
(
g_data_width : POSITIVE := 32
);
PORT
(
in_d : IN STD_LOGIC_VECTOR(g_data_width - 1 DOWNTO 0);
in_en : IN STD_LOGIC;
in_clk : IN STD_LOGIC;
------------------------------------------
out_q : OUT STD_LOGIC_VECTOR(g_data_width - 1 DOWNTO 0)
);
END parallel_register;
ARCHITECTURE behavioral OF parallel_register IS
-- Register memory signal
SIGNAL s_memory : STD_LOGIC_VECTOR(g_data_width - 1 DOWNTO 0);
BEGIN
-- Wire output data to register memory
out_q <= s_memory;
PROCESS(in_en, in_clk)
BEGIN
-- Write to memory in rising edge if register is enabled
IF(in_en = '1' AND (in_clk'EVENT AND in_clk = '1')) THEN
s_memory <= in_d;
END IF;
END PROCESS;
END behavioral;
|
mit
|
c863f9454e3b1c91c64accbcd746ced2
| 0.517271 | 3.467066 | false | false | false | false |
ymahajan456/HighLevelSynthesis
|
Version_1.0/Testing/test_bench.vhd
| 1 | 3,256 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all ;
use ieee.std_logic_textio.all;
entity tb is
end entity;
architecture test of tb is
component binding is
generic(data_width : integer := 16);
port(
clk,reset : in std_logic;
start : in std_logic;
a,b,c,d : in std_logic_vector(data_width-1 downto 0);
output_0, output_1, output_2 : out std_logic_vector(data_width-1 downto 0) := (others => '0');
complete: out std_logic := '0');
end component;
function vec_to_str (x : std_logic_vector) return String is
variable L : line ;
variable W : String (1 to x'length) := (others =>'0');
begin
write(L,x);
W(L.all'range) := L.all;
Deallocate(L);
return W ;
end vec_to_str ;
signal clk,start: std_logic := '0';
signal rst: std_logic := '1';
signal done: std_logic;
--signal a_in, b_in, c_in, d_in, out0_ref, out1_ref, out2_ref : std_logic_vector(data_width-1 downto 0);
signal a,b,c,d,out_0, out_1, out_2: std_logic_vector(15 downto 0) := (others => '0');
begin
dut: binding
generic map(16)
port map(clk => clk, reset => rst,start => start, a => a, b=> b, c=>c, d=> d, output_0 => out_0, output_1 => out_1, output_2 => out_2, complete => done);
process
begin
clk <= not clk;
wait for 10 ns;
end process;
process
file f: text open read_mode is "test.txt";
variable a_in, b_in, c_in, d_in, out0_ref, out1_ref, out2_ref : std_logic_vector(15 downto 0);
variable L: line;
variable fail_count: integer := 0;
variable in_count: integer := 0;
begin
rst <= '1';
wait until (clk = '1');
wait until (clk = '1');
rst <= '0';
wait until (clk = '1');
while not endfile(f) loop
readline(f,L);
read(L,a_in);
read(L,b_in);
read(L,c_in);
read(L,d_in);
read(L,out0_ref);
read(L,out1_ref);
read(L,out2_ref);
in_count := in_count + 1;
report "Test Number : " & integer'image(in_count);
a <= a_in;
b <= b_in;
c <= c_in;
d <= d_in;
wait until (clk = '1');
start <= '1';
wait until (clk = '1');
wait until (clk = '1');
start <= '0';
wait until(done = '1');
wait until(clk = '0');
if (not ((out0_ref = out_0) and (out1_ref = out_1) and (out2_ref = out_2))) then
fail_count := fail_count + 1;
report "Error :: Inputs are : " & vec_to_str(a) & " " & vec_to_str(b) & " " & vec_to_str(c) & " " & vec_to_str(d);
report "Outputs are : " & vec_to_str(out_0) & " " & vec_to_str(out_1) & " " & vec_to_str(out_2);
end if;
end loop;
report "Test Completed with " & integer'image(fail_count) & " failures";
wait;
end process;
end architecture;
|
gpl-3.0
|
afbbbb329138587daad97bcf20b16261
| 0.475123 | 3.292214 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/adapt_wm8731.vhdl
| 1 | 8,064 |
-- Adapt to WM8731 codec on e.g. MikroElektronika dev board
-- (C) Copyright 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
-- ======================================================================
-- top-level entity for WM8731 adapt
entity wm8731_adapt is
port (
-- async reset
areset : in std_logic;
-- audio samples
audio : in std_logic_vector(17 downto 0);
aclk48k : in std_logic;
-- codec interface
aud_sck : in std_logic;
aud_mosi : out std_logic;
aud_dacl : out std_logic;
aud_sda : out std_logic;
aud_scl : out std_logic;
cfg_done : out std_logic
);
end entity wm8731_adapt;
-- ======================================================================
-- We operate the WM8731 with the following register configuration:
-- 00: 010000000: LRINBOTH=0b, LINMUTE=1b, LINVOL=00000b
-- 01: 010000000: RLINBOTH=0b, RINMUTE=1b, RINVOL=00000b
-- 02: 000000000: LRHPBOTH=0b, LZCEN=0b, LHPVOL=0000000b
-- 03: 000000000: RLHPBOTH=0b, RZCEN=0b, RHPVOL=0000000b
-- 04: 000010010: SIDEATT=00b, SIDETONE=0b, DACSEL=1b, BYPASS=0b, INSEL=0b, MUTEMIC=1b, MICBOOST=0b
-- 05: 000000000: HPOR=0b, DACMU=0b, DEEMP=00b, ADCHPD=0b
-- 06: 001100111: POWEROFF=0b, CLKOUTPD=1b, OSCPD=1b, OUTPD=0b, DACPD=0b, ADCPD=1b, MICPD=1b, LINEINPD=1b
-- 07: 000000010: BCLKINV=0b, MS=0b, LRSWAP=0b, LRP=0b, IWL=00b, FORMAT=10b
-- 08: 000000000: CLKODIV2=0b, CLKIDIV2=0b, SR=0000b, BOSR=0b, USB/NORMAL=0b
-- 09: 000000001: ACTIVE=1b
architecture behaviour of wm8731_adapt is
signal sync_48k : std_logic;
signal psync_48k : std_logic;
signal dacl : std_logic;
signal sda : std_logic;
signal scl : std_logic;
-- I2C configuration state machine
subtype scl_type is unsigned(1 downto 0);
constant SCL0 : scl_type := "01";
constant SCL1 : scl_type := "11";
constant SCL2 : scl_type := "10";
constant SCL3 : scl_type := "00";
signal phase : scl_type := SCL0;
subtype state_type is unsigned(4 downto 0);
constant IDLE : state_type := "10100";
constant START : state_type := "11100";
constant BIT7 : state_type := "01100";
constant BIT6 : state_type := "01101";
constant BIT5 : state_type := "01111";
constant BIT4 : state_type := "01110";
constant BIT3 : state_type := "01010";
constant BIT2 : state_type := "01011";
constant BIT1 : state_type := "01001";
constant BIT0 : state_type := "01000";
constant ACK : state_type := "11000";
constant STOP : state_type := "10000";
constant DONE : state_type := "10001";
signal state : state_type := IDLE;
signal bytes : unsigned(1 downto 0) := "00"; -- 3 bytes transferred per word
signal words : unsigned(3 downto 0) := X"0"; -- 10 words to program
type TCONFIG is array(0 to 9) of std_logic_vector(23 downto 0);
constant CONFIG : TCONFIG := (X"350080", X"350280", X"350400", X"350600",
X"350812", X"350a00", X"350c67", X"350e02",
X"351000", X"351201");
signal cfgword : std_logic_vector(23 downto 0);
-- stream buffer
signal sample : std_logic_vector(15 downto 0);
signal scount : unsigned(7 downto 0);
begin -- behaviour
-- 48 kHz sample clock to aligned to audio source
p_clk48 : process(aud_sck, areset) is
begin
if areset = '1' then
sync_48k <= '0';
psync_48k <= '0';
elsif aud_sck'event and aud_sck = '1' then
psync_48k <= sync_48k;
sync_48k <= aclk48k;
end if;
end process;
-- configuration at startup
-- bare-bones I2C running at 12 kHz
-- writes CONFIG blindly, without checking for byte ACKs
p_config : process(aclk48k, areset) is
begin
if areset = '1' then
phase <= SCL0;
state <= IDLE;
bytes <= (others => '0');
words <= (others => '0');
sda <= '1';
scl <= '1';
elsif aclk48k'event and aclk48k = '1' then
case phase is
when SCL0 =>
if ((state = IDLE) or (state = STOP) or (state = DONE)) then
scl <= '1';
else
scl <= '0';
end if;
phase <= SCL1;
when SCL1 =>
case state is
when IDLE =>
sda <= '0';
state <= START;
cfgword <= CONFIG(to_integer(words));
when START =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT7;
when BIT7 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT6;
when BIT6 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT5;
when BIT5 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT4;
when BIT4 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT3;
when BIT3 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT2;
when BIT2 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT1;
when BIT1 =>
sda <= cfgword(23);
cfgword <= cfgword(22 downto 0) & '0';
state <= BIT0;
when BIT0 =>
sda <= '1';
state <= ACK;
when ACK =>
sda <= '0';
state <= STOP;
when STOP =>
sda <= '1';
if ((bytes >= 2) and (words >= 9)) then
state <= DONE;
else
if (bytes < 2) then
bytes <= bytes + 1;
else
words <= words + 1;
bytes <= (others => '0');
end if;
state <= IDLE;
end if;
when others => null;
end case;
phase <= SCL2;
when SCL2 =>
scl <= '1';
phase <= SCL3;
when SCL3 =>
phase <= SCL0;
end case;
end if;
end process;
-- formatted audio stream (I2S right-justified)
-- relies on fact that 16-bit sample rotates evenly into 128 bits per channel
p_stream : process(aud_sck, areset) is
begin
if areset = '1' then
dacl <= '0';
sample <= (others => '0');
scount <= X"00";
elsif aud_sck'event and aud_sck = '0' then
if (sync_48k = '1') and (psync_48k = '0') then
-- start: left channel
sample <= audio(17 downto 2);
dacl <= '1';
scount <= X"00";
else
if (scount = 127) then
dacl <= '0';
end if;
sample <= sample(14 downto 0) & sample(15);
scount <= scount + 1;
end if;
end if;
end process;
-- wire in outputs
aud_mosi <= sample(15);
aud_dacl <= dacl;
aud_sda <= sda;
aud_scl <= scl;
cfg_done <= '1' when (state = DONE) else '0';
end behaviour;
|
gpl-2.0
|
021b319215d9680f0d859f3540116a67
| 0.525918 | 3.579228 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/t80/t80se.vhd
| 1 | 5,868 |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
t80mode => Mode
)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
|
gpl-2.0
|
6d9194865316e03f3d36ed735613b1b5
| 0.57362 | 3.210066 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab10_RegFile/lab10_RegFile_lib/hdl/RegisterFile_Structure.vhd
| 1 | 2,739 |
--
-- VHDL Architecture lab10_RegFile_lib.RegisterFile.Structure
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 07:18:21 04/ 9/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RegisterFile IS
GENERIC(RegWidth : positive := 16; -- The number of bits in each register
RegSel : positive := 4); -- Select a register. Can select up to 2^RegSel ReadWrite Registers
PORT ( ReadAddr_0, ReadAddr_1 : IN std_logic_vector(RegSel-1 DOWNTO 0); -- Read Data Address
RD0, RD1 : OUT std_logic_vector(RegWidth-1 DOWNTO 0); -- Read Data Outputs
WriteAddr : IN std_logic_vector(RegSel-1 DOWNTO 0); -- Write Data Address
WD : IN std_logic_vector(RegWidth-1 DOWNTO 0); -- Write Data Input
clock, write_enable : IN std_logic
);
END ENTITY RegisterFile;
--
ARCHITECTURE Structure OF RegisterFile IS
-- One-hot Decoder Selects
SIGNAL RegRead_0, RegRead_1: std_logic_vector((2**RegSel)-1 downto 0 );
SIGNAL RegWrite: std_logic_vector((2**RegSel)-1 downto 0 );
-- Read Outputs
SIGNAL RegOut_0, RegOut_1: std_logic_vector(RegWidth-1 downto 0 );
BEGIN
-- Read Decoder for reading the first operand
ReadDecode_0: ENTITY work.Decoder(Behavior)
GENERIC MAP(size=> RegSel)
PORT MAP( sel=> ReadAddr_0, onehot=> RegRead_0, enable=> '1');
-- Read Decoder for reading the second operand
ReadDecode_1: ENTITY work.Decoder(Behavior)
GENERIC MAP(size=> RegSel)
PORT MAP( sel=> ReadAddr_1, onehot=> RegRead_1, enable=> '1');
-- Write Decoder
WriteDecode: ENTITY work.Decoder(Behavior)
GENERIC MAP(size=> RegSel)
PORT MAP( sel=> WriteAddr, onehot=> RegWrite, enable=> write_enable);
-- Instantiate an array of ReadWrite Registers
RegArray: FOR i in 0 to ((2**RegSel)-1) GENERATE
SIGNAL WE: std_logic;
BEGIN
WE <= (RegWrite(i) and write_enable);
RegI: ENTITY work.RegReadWrite(mixed)
GENERIC MAP(size=>RegWidth)
PORT MAP( D=> WD, -- Write Data
Q0=> RegOut_0, Q1=> RegOut_1, -- Intermediate Read Outputs
c=>clock,
load=> WE, -- Write Select
read0=>RegRead_0(i), read1=>RegRead_1(i) -- Read Select
);
END GENERATE RegArray;
RD0<= RegOut_0;
RD1<= RegOut_1;
END ARCHITECTURE Structure;
|
gpl-2.0
|
3b276485f5992cd4809f4072ada5e3e2
| 0.568091 | 4.075893 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano/DE0_Nano_TRDB_D5M_LT24_top_level.vhd
| 1 | 3,391 |
-- #############################################################################
-- DE0_Nano_TRDB_D5M_LT24_top_level.vhd
-- ====================================
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_TRDB_D5M_LT24_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
LED : out std_logic_vector(7 downto 0);
-- KEY_N
KEY_N : in std_logic_vector(1 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
EPCS_ASDO : out std_logic;
EPCS_DATA0 : in std_logic;
EPCS_DCLK : out std_logic;
EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
G_SENSOR_CS_N : out std_logic;
G_SENSOR_INT : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
GPIO_2 : inout std_logic_vector(12 downto 0);
GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic;
-- GPIO_1
GPIO_1_LT24_ADC_BUSY : in std_logic;
GPIO_1_LT24_ADC_CS_N : out std_logic;
GPIO_1_LT24_ADC_DCLK : out std_logic;
GPIO_1_LT24_ADC_DIN : out std_logic;
GPIO_1_LT24_ADC_DOUT : in std_logic;
GPIO_1_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_1_LT24_CS_N : out std_logic;
GPIO_1_LT24_D : out std_logic_vector(15 downto 0);
GPIO_1_LT24_LCD_ON : out std_logic;
GPIO_1_LT24_RD_N : out std_logic;
GPIO_1_LT24_RESET_N : out std_logic;
GPIO_1_LT24_RS : out std_logic;
GPIO_1_LT24_WR_N : out std_logic
);
end entity DE0_Nano_TRDB_D5M_LT24_top_level;
architecture rtl of DE0_Nano_TRDB_D5M_LT24_top_level is
begin
end;
|
unlicense
|
242d5179009969fca81c7cd265dbc194
| 0.506045 | 3.099634 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab10_MergeAll/lab10_TopLevel_lib/hdl/toplevel_struct.vhd
| 1 | 16,435 |
-- VHDL Entity lab10_TopLevel_lib.TopLevel.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 22:32:49 04/27/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY TopLevel IS
GENERIC(
AddressBits : POSITIVE := 16;
n : POSITIVE := 16;
BitWidth : POSITIVE := 16;
RegWidth : POSITIVE := 16;
RegSel : POSITIVE := 4
);
PORT(
clk : IN std_logic;
interrupt : IN std_logic := '0';
reset : IN std_logic := '0';
decode_pcval_out_TrackerOut : OUT std_logic_vector (RegWidth-1 DOWNTO 0)
);
-- Declarations
END TopLevel ;
--
-- VHDL Architecture lab10_TopLevel_lib.TopLevel.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 09:15:52 04/29/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
LIBRARY std;
USE std.textio.all;
LIBRARY lab10_memory_stage_lib;
LIBRARY lab10_RegFile_lib;
LIBRARY lab10_WriteBack_Stage_lib;
LIBRARY lab11_MemoryArbiter_lib;
LIBRARY lab11_RegisterTracker_lib;
LIBRARY lab12_Memory_lib;
LIBRARY lab7_lib;
LIBRARY lab8_new_lib;
LIBRARY lab9_new_lib;
ARCHITECTURE struct OF TopLevel IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL Addr : std_logic_vector(15 DOWNTO 0);
SIGNAL Addr_toMemory : std_logic_vector(15 DOWNTO 0);
SIGNAL Control : std_logic_vector(n-1 DOWNTO 0);
SIGNAL Control_Out : std_logic_vector(2 DOWNTO 0);
SIGNAL Control_toRegFile : std_logic;
SIGNAL Control_toWB : std_logic;
SIGNAL DataOut : std_logic_vector(BitWidth-1 DOWNTO 0);
SIGNAL Data_Store : std_logic_vector(15 DOWNTO 0);
SIGNAL Dest : std_logic_vector(3 DOWNTO 0);
SIGNAL Dest_Execute_Out : std_logic_vector(3 DOWNTO 0);
SIGNAL Dest_toRegFile : std_logic_vector(3 DOWNTO 0);
SIGNAL Dest_toWB : std_logic_vector(3 DOWNTO 0);
SIGNAL Extra : std_logic_vector(15 DOWNTO 0);
SIGNAL Extra_Execute_Out : std_logic_vector(15 DOWNTO 0);
SIGNAL L : std_logic_vector(15 DOWNTO 0);
SIGNAL R : std_logic_vector(15 DOWNTO 0);
SIGNAL R1 : std_logic;
SIGNAL RD0 : std_logic_vector(RegWidth-1 DOWNTO 0);
SIGNAL RD1 : std_logic_vector(RegWidth-1 DOWNTO 0);
SIGNAL ReadAddr_0 : std_logic_vector(RegSel-1 DOWNTO 0);
SIGNAL ReadAddr_1 : std_logic_vector(RegSel-1 DOWNTO 0);
SIGNAL RegWrite_current : std_logic;
SIGNAL Result : std_logic_vector(15 DOWNTO 0);
SIGNAL Value_toRegFile : std_logic_vector(15 DOWNTO 0);
SIGNAL Value_toWB : std_logic_vector(15 DOWNTO 0);
SIGNAL W : std_logic;
SIGNAL Write_Control : std_logic;
SIGNAL can_move_on : std_logic;
SIGNAL decode_pcval_out : std_logic_vector(15 DOWNTO 0);
SIGNAL dependsOn_op1 : std_logic;
SIGNAL dependsOn_op2 : std_logic;
SIGNAL inst : std_logic_vector(15 DOWNTO 0);
SIGNAL jaddress : std_logic_vector(15 DOWNTO 0);
SIGNAL jump : std_logic;
SIGNAL maddr : std_logic_vector(15 DOWNTO 0);
SIGNAL mdelay_toFetchStage : std_logic;
SIGNAL mdelay_toMemStage : std_logic;
SIGNAL pcval : std_logic_vector(15 DOWNTO 0);
SIGNAL stall : std_logic;
-- Component Declarations
COMPONENT memory_stage
PORT (
Control : IN std_logic_vector (2 DOWNTO 0);
Data_In : IN std_logic_vector (15 DOWNTO 0);
Dest : IN std_logic_vector (3 DOWNTO 0);
Extra : IN std_logic_vector (15 DOWNTO 0);
Result : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
mdelay : IN std_logic;
Addr : OUT std_logic_vector (15 DOWNTO 0);
Control_toWB : OUT std_logic;
Data_Store : OUT std_logic_vector (15 DOWNTO 0);
Dest_toWB : OUT std_logic_vector (3 DOWNTO 0);
R : OUT std_logic;
Value_toWB : OUT std_logic_vector (15 DOWNTO 0);
W : OUT std_logic;
stall : OUT std_logic
);
END COMPONENT;
COMPONENT RegisterFile
GENERIC (
RegWidth : positive := 16; -- The number of bits in each register
RegSel : positive := 4
);
PORT (
ReadAddr_0 : IN std_logic_vector (RegSel-1 DOWNTO 0);
ReadAddr_1 : IN std_logic_vector (RegSel-1 DOWNTO 0);
WD : IN std_logic_vector (RegWidth-1 DOWNTO 0);
WriteAddr : IN std_logic_vector (RegSel-1 DOWNTO 0);
clock : IN std_logic;
write_enable : IN std_logic;
RD0 : OUT std_logic_vector (RegWidth-1 DOWNTO 0);
RD1 : OUT std_logic_vector (RegWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lab10_WriteBack_Stage
PORT (
Control : IN std_logic;
Dest : IN std_logic_vector (3 DOWNTO 0);
Value : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
Control_toRegFile : OUT std_logic;
Dest_toRegFile : OUT std_logic_vector (3 DOWNTO 0);
Value_toRegFile : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT MemoryArbiter
PORT (
Addr_fromFetchStage : IN std_logic_vector (15 DOWNTO 0);
Addr_fromMemStage : IN std_logic_vector (15 DOWNTO 0);
R : IN std_logic;
W : IN std_logic;
reset : IN std_logic;
Addr_toMemory : OUT std_logic_vector (15 DOWNTO 0);
Write_Control : OUT std_logic;
mdelay_toFetchStage : OUT std_logic;
mdelay_toMemStage : OUT std_logic
);
END COMPONENT;
COMPONENT RegisterFile_Tracker
GENERIC (
RegWidth : positive := 16; -- The number of bits in each register
addr_size : positive := 4
);
PORT (
Clear_WriteAddr : IN std_logic_vector (addr_size-1 DOWNTO 0);
Mark_WriteAddr : IN std_logic_vector (addr_size-1 DOWNTO 0);
ReadAddr_0 : IN std_logic_vector (addr_size-1 DOWNTO 0);
ReadAddr_1 : IN std_logic_vector (addr_size-1 DOWNTO 0);
RegWrite_current : IN std_logic;
RegWrite_previous : IN std_logic;
clock : IN std_logic;
decode_pcval_out : IN std_logic_vector (RegWidth-1 DOWNTO 0);
dependsOn_op1 : IN std_logic;
dependsOn_op2 : IN std_logic;
reset : IN std_logic;
can_move_on : OUT std_logic;
decode_pcval_out_TrackerOut : OUT std_logic_vector (RegWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT SRAM
PORT (
Addr : IN std_logic_vector (15 DOWNTO 0);
DataIn : IN std_logic_vector (15 DOWNTO 0);
clock : IN std_logic;
we : IN std_logic;
DataOut : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT fetch_stage
PORT (
can_move_on : IN std_logic;
clk : IN std_logic;
interrupt : IN std_logic := '0';
jaddr : IN std_logic_vector (15 DOWNTO 0);
jump : IN std_logic := '0';
mdata : IN std_logic_vector (15 DOWNTO 0);
mdelay : IN std_logic := '0';
reset : IN std_logic := '0';
stall : IN std_logic;
inst : OUT std_logic_vector (15 DOWNTO 0);
maddr : OUT std_logic_vector (15 DOWNTO 0);
pcval : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT Decode_stage
GENERIC (
n : POSITIVE := 24; -- control output length
n_toExecute : POSITIVE := 16 -- control output length, sent to the execute stage
);
PORT (
RD0 : IN std_logic_vector (15 DOWNTO 0);
RD1 : IN std_logic_vector (15 DOWNTO 0);
can_move_on : IN std_logic;
clock : IN std_logic;
inst : IN std_logic_vector (15 DOWNTO 0);
jump : IN std_logic;
pcval : IN std_logic_vector (15 DOWNTO 0);
stall : IN std_logic;
A0 : OUT std_logic_vector (3 DOWNTO 0);
A1 : OUT std_logic_vector (3 DOWNTO 0);
Control : OUT std_logic_vector (n_toExecute-1 DOWNTO 0);
Dest : OUT std_logic_vector (3 DOWNTO 0);
Extra : OUT std_logic_vector (15 DOWNTO 0);
L : OUT std_logic_vector (15 DOWNTO 0);
R : OUT std_logic_vector (15 DOWNTO 0);
RegWrite_current : OUT std_logic;
decode_pcval_out : OUT std_logic_vector (15 DOWNTO 0);
dependsOn_op1 : OUT std_logic;
dependsOn_op2 : OUT std_logic
);
END COMPONENT;
COMPONENT execute_stage
PORT (
Control : IN std_logic_vector (15 DOWNTO 0);
Dest : IN std_logic_vector (3 DOWNTO 0);
Extra : IN std_logic_vector (15 DOWNTO 0);
L : IN std_logic_vector (15 DOWNTO 0);
R : IN std_logic_vector (15 DOWNTO 0);
can_move_on : IN std_logic;
clk : IN std_logic;
pcval : IN std_logic_vector (15 DOWNTO 0);
rst : IN std_logic;
stall : IN std_logic;
Control_Out : OUT std_logic_vector (2 DOWNTO 0);
Dest_Execute_Out : OUT std_logic_vector (3 DOWNTO 0);
Extra_Execute_Out : OUT std_logic_vector (15 DOWNTO 0);
Result : OUT std_logic_vector (15 DOWNTO 0);
jaddress : OUT std_logic_vector (15 DOWNTO 0);
jump : OUT std_logic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : Decode_stage USE ENTITY lab8_new_lib.Decode_stage;
FOR ALL : MemoryArbiter USE ENTITY lab11_MemoryArbiter_lib.MemoryArbiter;
FOR ALL : RegisterFile USE ENTITY lab10_RegFile_lib.RegisterFile;
FOR ALL : RegisterFile_Tracker USE ENTITY lab11_RegisterTracker_lib.RegisterFile_Tracker;
FOR ALL : SRAM USE ENTITY lab12_Memory_lib.SRAM;
FOR ALL : execute_stage USE ENTITY lab9_new_lib.execute_stage;
FOR ALL : fetch_stage USE ENTITY lab7_lib.fetch_stage;
FOR ALL : lab10_WriteBack_Stage USE ENTITY lab10_WriteBack_Stage_lib.lab10_WriteBack_Stage;
FOR ALL : memory_stage USE ENTITY lab10_memory_stage_lib.memory_stage;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_3 : memory_stage
PORT MAP (
Control => Control_Out,
Data_In => DataOut,
Dest => Dest_Execute_Out,
Extra => Extra_Execute_Out,
Result => Result,
clk => clk,
mdelay => mdelay_toMemStage,
Addr => Addr,
Control_toWB => Control_toWB,
Data_Store => Data_Store,
Dest_toWB => Dest_toWB,
R => R1,
Value_toWB => Value_toWB,
W => W,
stall => stall
);
U_6 : RegisterFile
GENERIC MAP (
RegWidth => 16, -- The number of bits in each register
RegSel => 4
)
PORT MAP (
ReadAddr_0 => ReadAddr_0,
ReadAddr_1 => ReadAddr_1,
RD0 => RD0,
RD1 => RD1,
WriteAddr => Dest_toRegFile,
WD => Value_toRegFile,
clock => clk,
write_enable => Control_toRegFile
);
U_4 : lab10_WriteBack_Stage
PORT MAP (
Control => Control_toWB,
Dest => Dest_toWB,
Value => Value_toWB,
clk => clk,
Control_toRegFile => Control_toRegFile,
Dest_toRegFile => Dest_toRegFile,
Value_toRegFile => Value_toRegFile
);
U_5 : MemoryArbiter
PORT MAP (
Addr_fromFetchStage => maddr,
Addr_fromMemStage => Addr,
R => R1,
W => W,
reset => reset,
Addr_toMemory => Addr_toMemory,
Write_Control => Write_Control,
mdelay_toFetchStage => mdelay_toFetchStage,
mdelay_toMemStage => mdelay_toMemStage
);
U_8 : RegisterFile_Tracker
GENERIC MAP (
RegWidth => 16, -- The number of bits in each register
addr_size => 4
)
PORT MAP (
ReadAddr_0 => ReadAddr_0,
ReadAddr_1 => ReadAddr_1,
Mark_WriteAddr => Dest,
Clear_WriteAddr => Dest_toRegFile,
dependsOn_op1 => dependsOn_op1,
dependsOn_op2 => dependsOn_op2,
RegWrite_current => RegWrite_current,
RegWrite_previous => Control_toRegFile,
clock => clk,
reset => reset,
decode_pcval_out => decode_pcval_out,
decode_pcval_out_TrackerOut => decode_pcval_out_TrackerOut,
can_move_on => can_move_on
);
U_7 : SRAM
PORT MAP (
Addr => Addr_toMemory,
DataIn => Data_Store,
clock => clk,
we => Write_Control,
DataOut => DataOut
);
U_0 : fetch_stage
PORT MAP (
can_move_on => can_move_on,
clk => clk,
interrupt => interrupt,
jaddr => jaddress,
jump => jump,
mdata => DataOut,
mdelay => mdelay_toFetchStage,
reset => reset,
stall => stall,
inst => inst,
maddr => maddr,
pcval => pcval
);
U_1 : Decode_stage
GENERIC MAP (
n => 24, -- control output length
n_toExecute => 16 -- control output length, sent to the execute stage
)
PORT MAP (
inst => inst,
pcval => pcval,
A0 => ReadAddr_0,
A1 => ReadAddr_1,
RD0 => RD0,
RD1 => RD1,
L => L,
R => R,
Control => Control,
Dest => Dest,
Extra => Extra,
decode_pcval_out => decode_pcval_out,
dependsOn_op1 => dependsOn_op1,
dependsOn_op2 => dependsOn_op2,
RegWrite_current => RegWrite_current,
clock => clk,
stall => stall,
jump => jump,
can_move_on => can_move_on
);
U_2 : execute_stage
PORT MAP (
Control => Control,
Dest => Dest,
Extra => Extra,
L => L,
R => R,
can_move_on => can_move_on,
clk => clk,
pcval => decode_pcval_out,
rst => reset,
stall => stall,
Control_Out => Control_Out,
Dest_Execute_Out => Dest_Execute_Out,
Extra_Execute_Out => Extra_Execute_Out,
Result => Result,
jaddress => jaddress,
jump => jump
);
END struct;
|
gpl-2.0
|
718f40370ada69f1299cea5e432ecb04
| 0.501065 | 4.027199 | false | false | false | false |
a4a881d4/ringbus
|
V3.0/testbench/rbus2_tb.vhd
| 1 | 2,507 |
---------------------------------------------------------------------------------------------------
--
-- Title : Testbench for Two End Point Example for Ring Bus
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : rbus2_tb.vhd
-- Generated : 2013/9/10
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Testbench for Two End Point Example for Ring Bus
-- two end point
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RBUS2_TB is
end RBUS2_TB;
library simio;
use simio.SIMIO_PACKAGE.all;
architecture sim of RBUS2_TB is
component RBUS2
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- CPU bus
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
Dout : out std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
-- out
viewAout : out std_logic_vector( 9 downto 0 );
viewDout : out std_logic_vector( 127 downto 0 );
viewenout : out std_logic
);
end component;
signal clk : STD_LOGIC :='0';
signal rst : STD_LOGIC :='0';
signal dspce,dspwr,wr : std_logic :='0';
signal rd : std_logic :='0';
signal addr : std_logic_vector( 7 downto 0 );
signal Din : std_logic_vector( 7 downto 0 );
signal Dout : std_logic_vector( 7 downto 0 );
signal cpuClk : std_logic :='0';
signal viewAout : std_logic_vector( 9 downto 0 );
signal viewDout : std_logic_vector( 127 downto 0 );
signal viewenout : std_logic :='0';
begin
cpu:dspemulator
generic map(
DSP_INC_FILE => "V3.0/testbench/rbus2.inx",
ABUS_WIDTH => 8,
DBUS_WIDTH => 8 )
port map(
clk => clk,
dspce => dspce,
dspa => addr,
data => din,
wr => dspwr,
IOstb => cpuClk
);
ttu:RBUS2
port map(
-- system
clk =>clk,
rst => rst,
wr => wr,
rd => '0',
addr => addr,
Din => Din,
cpuClk => cpuClk,
-- out
viewAout => viewAout,
viewDout => viewDout,
viewenout => viewenout
);
wr<=not ( dspwr );
rst <= '1', '0' after 10 ns;
clk <= not clk after 1 ns;
end sim;
|
lgpl-3.0
|
65a1eb656c385c948b187ef0f2d3ea52
| 0.473474 | 3.34713 | false | false | false | false |
ymahajan456/HighLevelSynthesis
|
Version_1.0/Testing/control_path.vhd
| 1 | 2,807 |
-- ============================================================
-- File Name: control_path.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2016-11-22
-- ************************************************************
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY control_path IS
PORT(
start: IN STD_LOGIC := '0';
complete: OUT STD_LOGIC := '0';
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
T: OUT STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0'));
END ENTITY;
ARCHITECTURE control OF control_path IS
TYPE fsm_state IS ( init, S0, S1, S2, S3, S4, S5, done );
SIGNAL nQ, Q: fsm_state := init;
BEGIN
clock: PROCESS(clk)
BEGIN
if(clk'EVENT AND clk = '1') THEN
Q <= nQ;
END IF;
END PROCESS;
next_state: PROCESS( reset, start, Q )
begin
nQ <= Q;
IF (reset = '1') THEN
nQ <= init;
ELSE
CASE Q IS
WHEN init =>
if (start = '1') then nQ <= S0;
END IF;
WHEN S0 => nQ <= S1;
WHEN S1 => nQ <= S2;
WHEN S2 => nQ <= S3;
WHEN S3 => nQ <= S4;
WHEN S4 => nQ <= S5;
WHEN S5 => nQ <= done;
WHEN done => nQ <= init;
WHEN OTHERS => nQ <= init;
END CASE;
END IF;
END PROCESS;
T_process: PROCESS ( Q )
BEGIN
T <= (OTHERS => '0');
complete <= '0';
CASE Q IS
WHEN init =>
T(12) <= '1';
T(13) <= '1';
T(14) <= '1';
T(15) <= '1';
WHEN S0 =>
T(16) <= '1';
T(17) <= '1';
T ( 6 TO 8 ) <= "110";
T ( 9 TO 11 ) <= "111";
T ( 23 TO 24 ) <= "10";
T ( 29 TO 30 ) <= "01";
T ( 35 TO 35 ) <= "1";
WHEN S1 =>
T(18) <= '1';
T(19) <= '1';
T ( 23 TO 24 ) <= "10";
T ( 29 TO 30 ) <= "01";
T ( 31 TO 31 ) <= "1";
T ( 32 TO 32 ) <= "1";
WHEN S2 =>
T(20) <= '1';
T(21) <= '1';
T(22) <= '1';
T ( 0 TO 2 ) <= "100";
T ( 3 TO 5 ) <= "101";
T ( 23 TO 24 ) <= "11";
T ( 25 TO 26 ) <= "01";
T ( 27 TO 28 ) <= "10";
T ( 29 TO 30 ) <= "10";
T ( 31 TO 31 ) <= "1";
T ( 32 TO 32 ) <= "1";
T ( 33 TO 33 ) <= "1";
T ( 34 TO 34 ) <= "1";
T ( 36 TO 36 ) <= "1";
WHEN S3 =>
T(16) <= '1';
T(17) <= '1';
T ( 3 TO 5 ) <= "111";
T ( 25 TO 26 ) <= "10";
T ( 27 TO 28 ) <= "01";
T ( 33 TO 33 ) <= "1";
T ( 34 TO 34 ) <= "1";
WHEN S4 =>
T(21) <= '1';
T ( 25 TO 26 ) <= "10";
WHEN S5 =>
T(20) <= '1';
T ( 0 TO 2 ) <= "110";
T ( 23 TO 24 ) <= "01";
T ( 25 TO 26 ) <= "01";
WHEN done => complete <= '1';
END CASE;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
9f75624956f4502e027cc20d3455b988
| 0.382615 | 2.693858 | false | false | false | false |
ymahajan456/HighLevelSynthesis
|
Version_1.0/Testing/binding.vhd
| 1 | 2,685 |
-- ============================================================
-- File Name: binding.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2016-11-22
-- ************************************************************
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY binding IS
GENERIC(
data_width: INTEGER := 16);
PORT(
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
a: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
d: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
b: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
c: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_0: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_1: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_2: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
start: IN STD_LOGIC := '0';
complete: OUT STD_LOGIC := '0');
END ENTITY;
ARCHITECTURE top_level OF binding IS
COMPONENT data_path IS
GENERIC(
data_width: INTEGER := 16);
PORT(
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
T: IN STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0');
a: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
d: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
b: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
c: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_0: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_1: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_2: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0'));
END COMPONENT;
COMPONENT control_path IS
PORT(
start: IN STD_LOGIC := '0';
complete: OUT STD_LOGIC := '0';
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
T: OUT STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0'));
END COMPONENT;
SIGNAL T: STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0');
BEGIN
data_path0: data_path
GENERIC MAP(
data_width => data_width
)
PORT MAP(
clk => clk,
reset => reset,
T => T,
a => a,
d => d,
b => b,
c => c,
output_0 => output_0,
output_1 => output_1,
output_2 => output_2
);
control_path0: control_path
PORT MAP(
start => start,
complete => complete,
clk => clk,
reset => reset,
T => T
);
END ARCHITECTURE;
|
gpl-3.0
|
753e034f6e5a8f7a61ee13a5ac255b01
| 0.502048 | 2.993311 | false | false | false | false |
KimSJ/HDLC_chip
|
hdlcreceiver.vhd
| 1 | 6,701 |
-- hdlcreceiver.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity HdlcReceiver is
generic (
rxReqChainSize : integer := 2 -- defines length of metastability chain; must be at least two.
);
port (
-- microprocesser interface
Dout : out Std_Logic_Vector (7 downto 0); -- rx register
rxLast : out Std_Logic; -- high if rx frame complete
rxRD : in Std_Logic; -- read strobe
rxReq : out Std_Logic; -- high if data available
rxErr : out Std_Logic; -- high if CRC error
rxUnderrun : out Std_Logic; -- high if byte not read in time
rxAbort : out Std_Logic; -- high if Abort received mid-frame
rxRST : in Std_Logic;
-- bit clock
sysClk : in Std_Logic; -- 16MHz
-- line interface
rxD : in Std_Logic;
rxEn : buffer Std_Logic
);
-- translate_off
-- check bounds of generics -- error reported only on execution
begin
assert( rxReqChainSize > 1 )
report "rxReqChainSize should be at least 2!"
severity ERROR;
-- translate_on
end HdlcReceiver;
architecture behavioural of HdlcReceiver is
signal shiftReg : Std_Logic_Vector (7 downto 0);
signal bitClk : Std_Logic;
signal bitCount : Std_Logic_Vector (2 downto 0);
signal onesCount : Std_Logic_Vector (2 downto 0);
signal flagRx, abortRx : Std_Logic;
signal clkDiv : Std_Logic_Vector(5 downto 0);
signal data_change : boolean;
signal data_was : Std_Logic := '1';
signal skipBit : boolean;
signal skippedBit : boolean;
signal flagSpotted : boolean;
function To_Std_Logic(L: BOOLEAN) return std_ulogic is
begin
if L then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
function IncrementSLV(V: Std_Logic_Vector) return Std_Logic_Vector is
begin
return Std_Logic_Vector(unsigned(V) + unsigned'("1"));
end function IncrementSLV;
type rxState_type is (sReset, sIdle, sStartFlags, sRxData, sRxDone, sRxErr, sRxAbort, sRxUnderrun);
type reg_type is record
state : rxState_type;
-- registered outputs
rxLast : Std_Logic; -- high if rx frame complete
rxReq : Std_Logic; -- high if data available
rxErr : Std_Logic; -- high if CRC error
rxUnderrun : Std_Logic; -- high if byte not read in time
rxAbort : Std_Logic; -- high if Abort received mid-frame
end record;
signal r, rin : reg_type;
constant r0 : reg_type := (
state => sReset,
rxLast => '0',
rxReq => '0',
rxErr => '0',
rxUnderrun => '0',
rxAbort => '0'
);
-- translate_off
-- stuff for debugging simulations
signal stateDecode : integer;
signal nextStateDecode : integer;
-- translate_on
signal debug_v : Std_Logic_Vector(2 downto 0);
signal debug : Std_Logic := '0';
begin
-- translate_off
-- stuff for debugging simulations
with r.state select
stateDecode <= 0 when sReset,
1 when sIdle,
2 when sStartFlags,
3 when sRxData,
4 when sRxDone,
5 when sRxErr,
6 when sRxAbort,
7 when sRxUnderrun;
with rin.state select
nextStateDecode <= 0 when sReset,
1 when sIdle,
2 when sStartFlags,
3 when sRxData,
4 when sRxDone,
5 when sRxErr,
6 when sRxAbort,
7 when sRxUnderrun;
-- translate_on
-- *************** Main state machine ****************
comb : process (bitCount, r)
begin
rxLast <= r.rxLast;
rxReq <= r.rxReq;
rxErr <= r.rxErr;
rxUnderrun <= r.rxUnderrun;
rxAbort <= r.rxAbort;
case r.state is
when sReset =>
rin.state <= sIdle; -- held reset by reset, until released
rin.rxErr <= r.rxErr;
rin.rxUnderrun <= r.rxUnderrun;
rin.rxAbort <= r.rxAbort;
when sIdle =>
if bitCount = "000" and flagRx = '1' then
rin.state <= sStartFlags;
-- else
-- rin.state <= r.state;
end if;
-- rin.rxErr <= r.rxErr;
-- rin.rxUnderrun <= r.rxUnderrun;
-- rin.rxAbort <= r.rxAbort;
when sStartFlags =>
if abortRx = '1' then
rin.state <= sIdle;
elsif bitCount = "000" and flagRx = '0' then
rin.state <= sRxData;
end if;
-- rin.rxErr <= r.rxErr;
-- rin.rxUnderrun <= r.rxUnderrun;
-- rin.rxAbort <= r.rxAbort;
when sRxData =>
if abortRx = '1' then
rin.state <= sRxAbort;
elsif bitCount = "000" and flagRx = '1' then
rin.state <= sRxDone;
-- else
-- rin.state <= r.state;
-- rin.rxErr <= r.rxErr;
-- rin.rxUnderrun <= r.rxUnderrun;
-- rin.rxAbort <= r.rxAbort;
end if;
when sRxDone | sRxErr | sRxAbort | sRxUnderrun => -- hold state until reset
-- rin.state <= r.state;
-- rin.rxErr <= r.rxErr;
-- rin.rxUnderrun <= r.rxUnderrun;
-- rin.rxAbort <= r.rxAbort;
end case;
end process comb;
reg : process (bitClk, rxRST)
begin
if rxRST = '1' then
r <= r0;
elsif rising_edge(bitClk) and not skipBit then
r <= rin;
end if;
end process reg;
-- *************** Clock recovery ********************
pBitClk: process (sysClk)
variable edge_detect : Std_Logic_Vector (2 downto 0);
begin
bitClk <= clkDiv(5);
data_change <= data_was /= edge_detect(2) and data_was /= edge_detect(1) and data_was /= edge_detect(0);
if rising_edge(sysClk) then
edge_detect := rxD & edge_detect(2 downto 1);
if data_change then
clkDiv <= "000011";
data_was <= not data_was;
else
clkDiv <= IncrementSLV(clkDiv);
end if;
end if;
end process pBitClk;
-- ************* Data/flag recovery *****************
pShiftReg: process (bitClk, rxRST)
begin
skipBit <= shiftReg(7 downto 2) = "111110" and rxD = '0' and not skippedBit;
flagSpotted <= onesCount = "110" and rxD = '0'; -- "01111110" received
if rxRST='1' then
shiftReg <= (others => '1');
onesCount <= (others => '0');
flagRx <= '0';
abortRx <= '0';
bitCount <= (others => '0');
else
if rising_edge(bitClk) and not skipBit then
shiftReg <= rxD & shiftReg(7 downto 1);
if flagSpotted then
bitCount <= "000";
else
bitCount <= incrementSLV(bitCount);
end if;
if bitCount <= "000" then
Dout <= shiftReg;
end if;
end if;
if rising_edge(bitClk) then
skippedBit <= skipBit;
if onesCount /= "111" then -- count to 7 then stop
if rxD = '0' then
onesCount <= "000";
else
onesCount <= Std_Logic_Vector(unsigned(onesCount) + unsigned'("1"));
end if;
end if;
flagRx <= To_Std_Logic(flagSpotted); -- latch flag spotted
abortRx <= To_Std_Logic((onesCount = "110" and rxD = '1') or onesCount = "111"); -- seven or more '1's received
end if;
end if;
end process pShiftReg;
end behavioural;
|
gpl-3.0
|
b10c672f5b31bee00db560fa2dc2c85d
| 0.628264 | 3.129846 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
DE10/TimePilotDE10.vhd
| 1 | 7,571 |
-- VHDL for Time Pilot (Konami Arcade Emulator) on Terasic DE10 Lite
-- (C) Copyright 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
-- ======================================================================
-- top-level entity for DE-10 Lite
entity TimePilotDE10 is
-- clocks
port (ADC_CLK_10 : in std_logic;
MAX10_CLK1_50 : in std_logic;
MAX10_CLK2_50 : in std_logic;
-- pushbuttons
KEY : in std_logic_vector(1 downto 0);
-- slide switches
SW : in std_logic_vector(9 downto 0);
-- discrete LEDs
LEDR : out std_logic_vector(9 downto 0);
-- 7-segment LED displays
HEX0 : out std_logic_vector(7 downto 0);
HEX1 : out std_logic_vector(7 downto 0);
HEX2 : out std_logic_vector(7 downto 0);
HEX3 : out std_logic_vector(7 downto 0);
HEX4 : out std_logic_vector(7 downto 0);
HEX5 : out std_logic_vector(7 downto 0);
-- expansion header
GPIO : inout std_logic_vector(35 downto 0);
-- Arduino Uno expansion
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : in std_logic;
-- VGA
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_WE_N : out std_logic;
DRAM_CS_N : out std_logic;
-- Accelerometer
GSENSOR_SDI : in std_logic;
GSENSOR_SDO : out std_logic;
GSENSOR_CS_n : out std_logic;
GSENSOR_SCLK : out std_logic;
GSENSOR_INT : in std_logic_vector(2 downto 1)
);
end entity TimePilotDE10;
-- ======================================================================
architecture behaviour of TimePilotDE10 is
-- clocks and resets
signal clk36864 : std_logic;
signal clk25000 : std_logic;
signal clk12288 : std_logic;
signal tpreset : std_logic;
-- video signals
signal red : std_logic_vector(7 downto 0);
signal grn : std_logic_vector(7 downto 0);
signal blu : std_logic_vector(7 downto 0);
signal xpixel : std_logic_vector(7 downto 0);
signal ypixel : std_logic_vector(7 downto 0);
signal pxclk : std_logic;
signal hsync : std_logic;
signal hblank : std_logic;
signal phblank : std_logic;
signal vsync : std_logic;
signal vblank : std_logic;
-- audio signals
signal audio : std_logic_vector(17 downto 0);
signal aclk : std_logic;
-- VGA signals
signal vga_red : std_logic_vector(3 downto 0);
signal vga_grn : std_logic_vector(3 downto 0);
signal vga_blu : std_logic_vector(3 downto 0);
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
-- audio output signals as per MicroElecktronika WM8731 board
signal aud_mosi : std_logic;
signal aud_dacl : std_logic;
signal aud_sda : std_logic;
signal aud_scl : std_logic;
signal aud_cfg : std_logic;
begin -- behaviour
tpreset <= not KEY(0);
-- PLL for master clocks
MAIN_CLK : entity work.pll73728
port map (
inclk0 => MAX10_CLK1_50,
c0 => clk36864, -- 36.864 MHz for time pilot
c1 => clk25000, -- 25.000 MHz for VGA conversion
c2 => clk12288 -- 12.288 MHz for audio codec
);
-- time pilot!
TIME_PILOT : entity work.time_pilot
port map (
mclk => clk36864,
mreset => tpreset,
p1start => '1',
p2start => '1',
coin1 => '1',
coin2 => '1',
fire => '1',
joy_up => '1',
joy_down => '1',
joy_left => '1',
joy_right => '1',
dip1 => X"ff",
dip2 => X"f3",
red => red,
grn => grn,
blu => blu,
hsync => hsync,
hblank => hblank,
vsync => vsync,
vblank => vblank,
xpixel => xpixel,
ypixel => ypixel,
pxclk => pxclk,
audio => audio,
aclk48k => aclk
);
-- VGA conversion
VGA_CONV : entity work.Vid2Vga
generic map (
VLINES => 256,
HPIXELS => 256,
VBITS => 8,
HBITS => 8,
SRCBITS => 8,
OUTBITS => 4
)
port map (
vreset => tpreset,
vgaclk => clk25000,
red => red,
grn => grn,
blu => blu,
hblank => hblank,
vblank => vblank,
xpixel => not ypixel,
ypixel => xpixel,
pxclk => pxclk,
vga_red => vga_red,
vga_grn => vga_grn,
vga_blu => vga_blu,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- VGA
VGA_R <= vga_red;
VGA_G <= vga_grn;
VGA_B <= vga_blu;
VGA_HS <= vga_hsync;
VGA_VS <= vga_vsync;
AUDIO_CONV : entity work.wm8731_adapt
port map (
areset => tpreset,
audio => audio,
aclk48k => aclk,
aud_sck => clk12288,
aud_mosi => aud_mosi,
aud_dacl => aud_dacl,
aud_sda => aud_sda,
aud_scl => aud_scl,
cfg_done => aud_cfg
);
-- GPIO header for audio
GPIO(0) <= clk12288 when (aud_cfg = '1') else 'Z';
GPIO(1) <= aud_mosi when (aud_cfg = '1') else 'Z';
GPIO(2) <= aud_dacl when (aud_cfg = '1') else 'Z';
GPIO(3) <= '0' when ((aud_cfg = '1') and (aud_sda = '0')) else 'Z';
GPIO(4) <= '0' when ((aud_cfg = '1') and (aud_scl = '0')) else 'Z';
-- unused outputs
LEDR <= (others => '0');
HEX0 <= (others => '1');
HEX1 <= (others => '1');
HEX2 <= (others => '1');
HEX3 <= (others => '1');
HEX4 <= (others => '1');
HEX5 <= (others => '1');
GPIO(35 downto 5) <= (others => 'Z');
ARDUINO_IO <= (others => 'Z');
DRAM_ADDR <= (others => '0');
DRAM_DQ <= (others => 'Z');
DRAM_BA <= (others => '0');
DRAM_LDQM <= '0';
DRAM_UDQM <= '0';
DRAM_RAS_N <= '1';
DRAM_CAS_N <= '1';
DRAM_CKE <= '0';
DRAM_CLK <= '0';
DRAM_WE_N <= '1';
DRAM_CS_N <= '1';
GSENSOR_SDO <= 'Z';
GSENSOR_CS_n <= '1';
GSENSOR_SCLK <= '0';
end behaviour;
|
gpl-2.0
|
47a212ad6af1aca2dfa327ad9b699389
| 0.524766 | 3.442929 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano-SoC/DE0_Nano_SoC_LT24_top_level.vhd
| 1 | 4,489 |
-- #############################################################################
-- DE0_Nano_SoC_LT24_top_level.vhd
-- ===============================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_LT24_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0_LT24_ADC_BUSY : in std_logic;
GPIO_0_LT24_ADC_CS_N : out std_logic;
GPIO_0_LT24_ADC_DCLK : out std_logic;
GPIO_0_LT24_ADC_DIN : out std_logic;
GPIO_0_LT24_ADC_DOUT : in std_logic;
GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_0_LT24_CS_N : out std_logic;
GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
GPIO_0_LT24_LCD_ON : out std_logic;
GPIO_0_LT24_RD_N : out std_logic;
GPIO_0_LT24_RESET_N : out std_logic;
GPIO_0_LT24_RS : out std_logic;
GPIO_0_LT24_WR_N : out std_logic;
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_LT24_top_level;
architecture rtl of DE0_Nano_SoC_LT24_top_level is
begin
end;
|
unlicense
|
72fb1d31eaf6d0e0f4151c6d4dd5dec0
| 0.508577 | 3.123869 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab10_RegFile/lab10_RegFile_lib/hdl/Decoder_Behavior.vhd
| 1 | 1,104 |
--
-- VHDL Architecture lab10_RegFile_lib.Decoder.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 23:12:41 04/ 8/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
ENTITY Decoder IS
GENERIC( size: positive := 4); -- 16 registers available
PORT( sel: IN std_logic_vector(size-1 downto 0) := (others=>'0');
onehot: OUT std_logic_vector( (2**size)-1 downto 0 );
enable: IN std_logic);
END ENTITY Decoder;
ARCHITECTURE Behavior OF Decoder IS
BEGIN
PROCESS(sel, enable)
VARIABLE selection: natural;
VARIABLE result: std_logic_vector( (2**size)-1 downto 0 );
CONSTANT zero: std_logic_vector( (2**size)-1 downto 0 ) := (others=> '0');
BEGIN
result := zero;
IF(enable = '1') THEN
selection := to_integer( ieee.numeric_std.unsigned(sel) );
result(selection) := '1';
END IF;
onehot <= result;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
991a30082286fe6a79ce47a0214ab152
| 0.605072 | 3.549839 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/time_pilot.vhd
| 1 | 28,619 |
-- VHDL for Time Pilot (Konami Arcade Emulator)
-- (C) Copyright 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
-- ======================================================================
-- top-level entity for time pilot
entity time_pilot is
generic (
LOGINFO : boolean := false
);
port (mclk : in std_logic; -- 36.864 MHz
mreset : in std_logic; -- active-high
-- discrete inputs
p1start : in std_logic;
p2start : in std_logic;
coin1 : in std_logic;
coin2 : in std_logic;
fire : in std_logic;
joy_up : in std_logic;
joy_down : in std_logic;
joy_left : in std_logic;
joy_right : in std_logic;
dip1 : in std_logic_vector(7 downto 0);
dip2 : in std_logic_vector(7 downto 0);
-- video output
red : out std_logic_vector(7 downto 0);
grn : out std_logic_vector(7 downto 0);
blu : out std_logic_vector(7 downto 0);
hsync : out std_logic;
hblank : out std_logic;
vsync : out std_logic;
vblank : out std_logic;
xpixel : out std_logic_vector(7 downto 0);
ypixel : out std_logic_vector(7 downto 0);
pxclk : out std_logic;
-- audio output
audio : out std_logic_vector(17 downto 0);
aclk48k : out std_logic
);
end entity time_pilot;
-- ======================================================================
architecture behaviour of time_pilot is
-- clocks and resets
signal mz80_clk : std_logic;
signal mz80_reset : std_logic;
signal az80_clk : std_logic;
signal az80_reset : std_logic;
signal psg_clk : std_logic;
signal psg_reset : std_logic;
signal ac97_bit_clk : std_logic;
-- ROMs
signal tm1_data_out : std_logic_vector(7 downto 0);
signal tm2_data_out : std_logic_vector(7 downto 0);
signal tm3_data_out : std_logic_vector(7 downto 0);
signal tm4_data_out : std_logic_vector(7 downto 0);
signal tm5_data_out : std_logic_vector(7 downto 0);
signal tm6_data_out : std_logic_vector(7 downto 0);
signal e9_data_out : std_logic_vector(7 downto 0);
signal e12_data_out : std_logic_vector(7 downto 0);
signal tm7_data_out : std_logic_vector(7 downto 0);
-- RAMs
signal mz80_sprite_wel : std_logic;
signal mz80_sprite_weh : std_logic;
signal mz80_sprite_datal : std_logic_vector(7 downto 0);
signal mz80_sprite_datah : std_logic_vector(7 downto 0);
signal mz80_tilec_we : std_logic;
signal mz80_tilec_rdata : std_logic_vector(7 downto 0);
signal mz80_tilev_we : std_logic;
signal mz80_tilev_rdata : std_logic_vector(7 downto 0);
signal mz80_ram_we : std_logic;
signal mz80_ram_rdata : std_logic_vector(7 downto 0);
signal az80_ram_we : std_logic;
signal az80_ram_rdata : std_logic_vector(7 downto 0);
-- Main Z80 interface
signal mz80_addr : std_logic_vector(15 downto 0);
signal mz80_data_in : std_logic_vector(7 downto 0);
signal mz80_data_out : std_logic_vector(7 downto 0);
signal mz80_m1 : std_logic;
signal mz80_mreq : std_logic;
signal mz80_iorq : std_logic;
signal mz80_rd : std_logic;
signal mz80_wr : std_logic;
signal mz80_rfsh : std_logic;
signal mz80_halt : std_logic;
signal mz80_busak : std_logic;
signal mz80_nmi : std_logic;
signal mz80_pnmi : std_logic;
-- rasterizer interface
signal rast_red : std_logic_vector(7 downto 0);
signal rast_grn : std_logic_vector(7 downto 0);
signal rast_blu : std_logic_vector(7 downto 0);
signal rast_xpixel : std_logic_vector(7 downto 0);
signal rast_pixel_clk : std_logic;
signal rast_hsync : std_logic;
signal rast_hblank : std_logic;
signal rast_vsync : std_logic;
signal rast_vblank : std_logic;
signal rast_pvblank : std_logic;
signal rast_video_line : std_logic_vector(7 downto 0);
signal rast_sprom_addr : std_logic_vector(13 downto 0);
signal rast_sprom_data : std_logic_vector(7 downto 0);
signal rast_strom_addr : std_logic_vector(12 downto 0);
signal rast_spram_addr : std_logic_vector(9 downto 0);
signal rast_spraml_data : std_logic_vector(7 downto 0);
signal rast_spramh_data : std_logic_vector(7 downto 0);
signal rast_tiram_addr : std_logic_vector(9 downto 0);
signal rast_tcram_data : std_logic_vector(7 downto 0);
signal rast_tvram_data : std_logic_vector(7 downto 0);
signal rast_pprom_addr : std_logic_vector(7 downto 0);
signal rast_tprom_addr : std_logic_vector(7 downto 0);
-- rasterizer integration
signal mz80_nmi_enable : std_logic;
-- audio integration
signal audio_int : std_logic;
signal audio_command : std_logic_vector(7 downto 0);
signal audio_filt_1 : std_logic_vector(5 downto 0);
signal audio_filt_2 : std_logic_vector(5 downto 0);
signal audio_sample_1 : std_logic_vector(7 downto 0);
signal audio_sample_2 : std_logic_vector(7 downto 0);
signal audio_select_1 : std_logic_vector(1 downto 0);
signal audio_select_2 : std_logic_vector(1 downto 0);
signal audio_data : std_logic_vector(17 downto 0);
signal audio_strobe : std_logic;
signal audio_psgnew : std_logic;
-- discrete inputs
signal iw1 : std_logic_vector(7 downto 0);
signal iw2 : std_logic_vector(7 downto 0);
signal iw3 : std_logic_vector(7 downto 0);
-- Audio Z80 interface
signal az80_addr : std_logic_vector(15 downto 0);
signal az80_data_in : std_logic_vector(7 downto 0);
signal az80_data_out : std_logic_vector(7 downto 0);
signal az80_m1 : std_logic;
signal az80_mreq : std_logic;
signal az80_iorq : std_logic;
signal az80_rd : std_logic;
signal az80_wr : std_logic;
signal az80_rfsh : std_logic;
signal az80_halt : std_logic;
signal az80_busak : std_logic;
-- Programmable sound generators
signal psg1_di : std_logic_vector(7 downto 0);
signal psg1_do : std_logic_vector(7 downto 0);
signal psg1_oe : std_logic;
signal psg1_bdir : std_logic;
signal psg1_bc1 : std_logic;
signal psg1_audioA : std_logic_vector(7 downto 0);
signal psg1_audioB : std_logic_vector(7 downto 0);
signal psg1_audioC : std_logic_vector(7 downto 0);
signal psg1_portAo : std_logic_vector(7 downto 0);
signal psg1_portBi : std_logic_vector(7 downto 0);
signal psg1_portBo : std_logic_vector(7 downto 0);
signal psg1_portAoe : std_logic;
signal psg1_portBoe : std_logic;
signal psg1_awe : std_logic;
signal psg1_dwe : std_logic;
signal psg2_di : std_logic_vector(7 downto 0);
signal psg2_do : std_logic_vector(7 downto 0);
signal psg2_oe : std_logic;
signal psg2_bdir : std_logic;
signal psg2_bc1 : std_logic;
signal psg2_audioA : std_logic_vector(7 downto 0);
signal psg2_audioB : std_logic_vector(7 downto 0);
signal psg2_audioC : std_logic_vector(7 downto 0);
signal psg2_portAo : std_logic_vector(7 downto 0);
signal psg2_portBo : std_logic_vector(7 downto 0);
signal psg2_portAoe : std_logic;
signal psg2_portBoe : std_logic;
signal psg2_awe : std_logic;
signal psg2_dwe : std_logic;
begin -- behaviour
-- derive the 3.072 MHz clock for the main Z80 (div 12)
main_t80_clock : process(mclk, mreset)
variable lcount : unsigned(7 downto 0);
begin
if (mreset = '1') then
lcount := X"00";
mz80_clk <= '0';
elsif (mclk'event and mclk = '1') then
if (lcount = X"05") then
mz80_clk <= '1';
lcount := lcount + 1;
elsif (lcount = X"0b") then
mz80_clk <= '0';
lcount := X"00";
else
lcount := lcount + 1;
end if;
end if;
end process main_t80_clock;
-- derive a 1.8432 MHz clock for the audio Z80 (div 20) (3% faster than original)
audio_t80_clock : process(mclk, mreset)
variable lcount : unsigned(7 downto 0);
begin
if (mreset = '1') then
lcount := X"00";
az80_clk <= '0';
elsif (mclk'event and mclk = '1') then
if (lcount = X"09") then
az80_clk <= '1';
lcount := lcount + 1;
elsif (lcount = X"13") then
az80_clk <= '0';
lcount := X"00";
else
lcount := lcount + 1;
end if;
end if;
end process audio_t80_clock;
-- derive the 12.288 MHz AC97 bit clock of arbitrary phase (div 3)
ac97_clock : process(mclk, mreset)
variable lcount : unsigned(7 downto 0);
begin
if (mreset = '1') then
lcount := X"00";
ac97_bit_clk <= '0';
elsif (mclk'event and mclk = '1') then
if (lcount = X"01") then
ac97_bit_clk <= '1';
lcount := lcount + 1;
elsif (lcount = X"02") then
ac97_bit_clk <= '0';
lcount := X"00";
else
lcount := lcount + 1;
end if;
end if;
end process ac97_clock;
-- =======================================================================
-- ROMs
-- =======================================================================
TM1_ROM : entity work.tm1
port map (
addr => mz80_addr(12 downto 0),
dout => tm1_data_out
);
TM2_ROM : entity work.tm2
port map (
addr => mz80_addr(12 downto 0),
dout => tm2_data_out
);
TM3_ROM : entity work.tm3
port map (
addr => mz80_addr(12 downto 0),
dout => tm3_data_out
);
TM4_ROM : entity work.tm4
port map (
addr => rast_sprom_addr(12 downto 0),
dout => tm4_data_out
);
TM5_ROM : entity work.tm5
port map (
addr => rast_sprom_addr(12 downto 0),
dout => tm5_data_out
);
TM6_ROM : entity work.tm6
port map (
addr => rast_strom_addr,
dout => tm6_data_out
);
E9_ROM : entity work.e9
port map (
addr => rast_pprom_addr,
dout => e9_data_out
);
E12_ROM : entity work.e12
port map (
addr => rast_tprom_addr,
dout => e12_data_out
);
TM7_ROM : entity work.tm7
port map (
addr => az80_addr(11 downto 0),
dout => tm7_data_out
);
-- =======================================================================
-- RAMs
-- =======================================================================
SPRITE_RAM_L : entity work.dpram1k
port map (
clka => mz80_clk,
clkb => mclk,
ena => '1',
enb => '1',
wea => mz80_sprite_wel,
web => '0',
addra => mz80_addr(9 downto 0),
addrb => rast_spram_addr,
dia => mz80_data_out,
dib => (others => '0'),
doa => mz80_sprite_datal,
dob => rast_spraml_data
);
mz80_sprite_wel <= '1' when ((mz80_mreq = '0') and
(mz80_wr = '0') and
(mz80_addr(15 downto 10) = "101100"))
else '0';
SPRITE_RAM_H : entity work.dpram1k
port map (
clka => mz80_clk,
clkb => mclk,
ena => '1',
enb => '1',
wea => mz80_sprite_weh,
web => '0',
addra => mz80_addr(9 downto 0),
addrb => rast_spram_addr,
dia => mz80_data_out,
dib => (others => '0'),
doa => mz80_sprite_datah,
dob => rast_spramh_data
);
mz80_sprite_weh <= '1' when ((mz80_mreq = '0') and
(mz80_wr = '0') and
(mz80_addr(15 downto 10) = "101101"))
else '0';
TILE_COLOR_RAM : entity work.dpram1k
port map (
clka => mz80_clk,
clkb => mclk,
ena => '1',
enb => '1',
wea => mz80_tilec_we,
web => '0',
addra => mz80_addr(9 downto 0),
addrb => rast_tiram_addr,
dia => mz80_data_out,
dib => (others => '0'),
doa => mz80_tilec_rdata,
dob => rast_tcram_data
);
TILE_VIDEO_RAM : entity work.dpram1k
port map (
clka => mz80_clk,
clkb => mclk,
ena => '1',
enb => '1',
wea => mz80_tilev_we,
web => '0',
addra => mz80_addr(9 downto 0),
addrb => rast_tiram_addr,
dia => mz80_data_out,
dib => (others => '0'),
doa => mz80_tilev_rdata,
dob => rast_tvram_data
);
mz80_tilec_we <= '1' when ((mz80_mreq = '0') and
(mz80_wr = '0') and
(mz80_addr(15 downto 10) = "101000"))
else '0';
mz80_tilev_we <= '1' when ((mz80_mreq = '0') and
(mz80_wr = '0') and
(mz80_addr(15 downto 10) = "101001"))
else '0';
MZ80_RAM : entity work.ram2k
port map (
clk => mz80_clk,
we => mz80_ram_we,
a => mz80_addr(10 downto 0),
di => mz80_data_out,
do => mz80_ram_rdata
);
mz80_ram_we <= '1' when ((mz80_mreq = '0') and
(mz80_wr = '0') and
(mz80_addr(15 downto 11) = "10101"))
else '0';
AZ80RAM : entity work.ram1k
port map (
clk => az80_clk,
we => az80_ram_we,
a => az80_addr(9 downto 0),
di => az80_data_out,
do => az80_ram_rdata
);
az80_ram_we <= '1' when ((az80_mreq = '0') and
(az80_wr = '0') and
(az80_addr(15 downto 12) = X"3"))
else '0';
-- =======================================================================
-- main Z80
-- =======================================================================
MZ80 : entity work.t80se
port map (
RESET_n => mz80_reset,
CLK_n => mz80_clk,
CLKEN => '1',
WAIT_n => '1',
INT_n => '1',
NMI_n => mz80_nmi,
BUSRQ_n => '1',
M1_n => mz80_m1,
MREQ_n => mz80_mreq,
IORQ_n => mz80_iorq,
RD_n => mz80_rd,
WR_n => mz80_wr,
RFSH_n => mz80_rfsh,
HALT_n => mz80_halt,
BUSAK_n => mz80_busak,
A => mz80_addr,
DI => mz80_data_in,
DO => mz80_data_out
);
mz80_reset <= not mreset;
-- NMI vertical blanking
MZ80NMI : process(mz80_reset, mz80_clk, rast_vblank) is
begin
if (mz80_reset = '0') then
mz80_nmi <= '1';
elsif mz80_clk'event and mz80_clk = '0' then
rast_pvblank <= rast_vblank;
if mz80_nmi_enable = '0' then
mz80_nmi <= '1';
elsif (rast_pvblank = '0') and (rast_vblank = '1') then
mz80_nmi <= '0';
end if;
end if;
end process;
mz80_data_in <=
tm1_data_out when (mz80_addr(15 downto 13) = "000") else
tm2_data_out when (mz80_addr(15 downto 13) = "001") else
tm3_data_out when (mz80_addr(15 downto 13) = "010") else
mz80_tilec_rdata when (mz80_addr(15 downto 10) = "101000") else -- tile color RAM
mz80_tilev_rdata when (mz80_addr(15 downto 10) = "101001") else -- tile video RAM
mz80_ram_rdata when (mz80_addr(15 downto 11) = "10101") else -- program RAM
mz80_sprite_datal when (mz80_addr(15 downto 10) = "101100") else -- sprite RAM low
mz80_sprite_datah when (mz80_addr(15 downto 10) = "101101") else -- sprite RAM hi
rast_video_line when (mz80_addr(15 downto 4) = X"c00") else -- video scan line
dip2 when (mz80_addr(15 downto 4) = X"c20") else -- DIP switch 2
iw1 when (mz80_addr(15 downto 4) = X"c30") else -- inputs 1
iw2 when (mz80_addr(15 downto 4) = X"c32") else -- inputs 2
iw3 when (mz80_addr(15 downto 4) = X"c34") else -- inputs 3
dip1 when (mz80_addr(15 downto 4) = X"c36") else -- DIP switch 1
X"ff";
-- log NMI, reads of video scan line, writes to sprite and tile ram
g_loginfo : if LOGINFO generate
p_loginfo : process(mz80_clk)
variable l : line;
begin
if mz80_clk'event and (mz80_clk = '1') then
mz80_pnmi <= mz80_nmi;
if (mz80_addr(15 downto 4) = X"c00") and (mz80_mreq = '0') and (mz80_rd = '0') then
write(l, now);
write(l, string'(": read video line="));
hwrite(l, rast_video_line);
writeline(output, l);
end if;
if (mz80_addr = X"c300") and (mz80_mreq = '0') and (mz80_wr = '0') then
write(l, now);
write(l, string'(": NMI enable="));
hwrite(l, mz80_data_out);
writeline(output, l);
end if;
if (mz80_sprite_wel = '1') or (mz80_sprite_weh = '1') then
write(l, now);
write(l, string'(": sprite @"));
hwrite(l, mz80_addr);
write(l, string'("="));
hwrite(l, mz80_data_out);
writeline(output, l);
end if;
if (mz80_tilec_we = '1') then
write(l, now);
write(l, string'(": tile color @"));
hwrite(l, mz80_addr);
write(l, string'("="));
hwrite(l, mz80_data_out);
writeline(output, l);
end if;
if (mz80_tilev_we = '1') then
write(l, now);
write(l, string'(": tile video @"));
hwrite(l, mz80_addr);
write(l, string'("="));
hwrite(l, mz80_data_out);
writeline(output, l);
end if;
if (mz80_pnmi = '1') and (mz80_nmi = '0') then
write(l, now);
write(l, string'(": NMI"));
writeline(output, l);
end if;
end if;
end process p_loginfo;
end generate g_loginfo;
-- Main Z80 integration
MZ80W : process(mz80_reset, mz80_clk) is
variable inthold : unsigned(2 downto 0);
begin
if (mz80_reset = '0') then
audio_int <= '1';
audio_command <= X"00";
mz80_nmi_enable <= '0';
elsif mz80_clk'event and mz80_clk = '1' then
if ((mz80_mreq = '0') and (mz80_wr = '0')) then
if (mz80_addr = X"c000") then
audio_command <= mz80_data_out;
elsif (mz80_addr = X"c304") then
audio_int <= not mz80_data_out(0);
inthold := "111";
elsif (mz80_addr = X"c300") then
mz80_nmi_enable <= mz80_data_out(0);
elsif (inthold > 0) then
if (inthold = 1) then
audio_int <= '1';
end if;
inthold := inthold - 1;
end if;
end if;
end if;
end process;
iw1 <= "111" & p2start & p1start & '1' & coin2 & coin1;
iw2 <= "111" & fire & joy_down & joy_up & joy_right & joy_left;
iw3 <= "111" & fire & joy_down & joy_up & joy_right & joy_left;
-- =======================================================================
-- Rasterizer
-- =======================================================================
RAST : entity work.rasterizer
port map (
clk => mclk,
reset => mreset,
rgb_out_red => rast_red,
rgb_out_grn => rast_grn,
rgb_out_blu => rast_blu,
rgb_out_pixel_clock => rast_pixel_clk,
rgb_out_x => rast_xpixel,
rgb_hsync => rast_hsync,
rgb_hblank => rast_hblank,
rgb_vsync => rast_vsync,
rgb_vblank => rast_vblank,
video_line => rast_video_line,
sprom_addr => rast_sprom_addr,
sprom_data => rast_sprom_data,
strom_addr => rast_strom_addr,
strom_data => tm6_data_out,
spram_addr => rast_spram_addr,
spraml_data => rast_spraml_data,
spramh_data => rast_spramh_data,
tiram_addr => rast_tiram_addr,
tcram_data => rast_tcram_data,
tvram_data => rast_tvram_data,
pprom_addr => rast_pprom_addr,
pprom_data => e9_data_out(3 downto 0),
tprom_addr => rast_tprom_addr,
tprom_data => e12_data_out(3 downto 0)
);
rast_sprom_data <= tm4_data_out when rast_sprom_addr(13) = '0' else
tm5_data_out;
red <= rast_red;
grn <= rast_grn;
blu <= rast_blu;
vsync <= rast_vsync;
vblank <= rast_vblank;
hsync <= rast_hsync;
hblank <= rast_hblank;
pxclk <= rast_pixel_clk;
xpixel <= rast_xpixel;
ypixel <= rast_video_line;
-- =======================================================================
-- audio Z80
-- =======================================================================
AZ80 : entity work.t80se
port map (
RESET_n => az80_reset,
CLK_n => az80_clk,
CLKEN => '1',
WAIT_n => '1',
INT_n => audio_int,
NMI_n => '1',
BUSRQ_n => '1',
M1_n => az80_m1,
MREQ_n => az80_mreq,
IORQ_n => az80_iorq,
RD_n => az80_rd,
WR_n => az80_wr,
RFSH_n => az80_rfsh,
HALT_n => az80_halt,
BUSAK_n => az80_busak,
A => az80_addr,
DI => az80_data_in,
DO => az80_data_out
);
az80_reset <= not mreset;
az80_data_in <=
tm7_data_out when (az80_addr(15 downto 13) = "000") else
az80_ram_rdata when (az80_addr(15 downto 13) = "001") else
psg1_do when (az80_addr(15 downto 13) = "010") else
psg2_do when (az80_addr(15 downto 13) = "011") else
X"ff";
-- =======================================================================
-- Programmable sound generators
-- =======================================================================
PSG1 : entity work.ay_3_8910_psg
port map (
I_DA => psg1_di,
O_DA => psg1_do,
O_DA_OE_L => psg1_oe, -- ignore, unused
I_BDIR => psg1_bdir,
I_BC2 => '1',
I_BC1 => psg1_bc1,
O_AUDIO_A => psg1_audioA,
O_AUDIO_B => psg1_audioB,
O_AUDIO_C => psg1_audioC,
I_IOA => X"ff",
O_IOA => psg1_portAo, -- ignore, unused
O_IOA_OE_L => psg1_portAoe, -- ignore, unused
I_IOB => psg1_portBi,
O_IOB => psg1_portBo, -- ignore, unused
O_IOB_OE_L => psg1_portBoe, -- ignore, unused
ENA => '1',
RESET_L => psg_reset,
CLK => psg_clk
);
psg_reset <= not mreset;
psg1_awe <= '1' when ((az80_mreq = '0') and
(az80_wr = '0') and
(az80_addr(15 downto 12) = X"5"))
else '0';
psg1_dwe <= '1' when ((az80_mreq = '0') and
(az80_wr = '0') and
(az80_addr(15 downto 12) = X"4"))
else '0';
-- PSG1 strobe
p_psg1io : process(psg_clk, mreset) is
begin
if mreset = '1' then
psg1_bdir <= '0';
psg1_bc1 <= '0';
psg1_di <= (others => '0');
elsif psg_clk'event and psg_clk = '0' then
if (psg1_awe = '1') then
psg1_di <= az80_data_out;
psg1_bdir <= '1';
psg1_bc1 <= '1';
elsif (psg1_dwe = '1') then
psg1_di <= az80_data_out;
psg1_bdir <= '1';
psg1_bc1 <= '0';
else
psg1_bdir <= '0';
psg1_bc1 <= '1';
end if;
end if;
end process;
-- PSG1 Port B inputs
psg1_portBi(3 downto 0) <= (others => '0');
p_psg1Bup : process(psg_clk, mreset) is
variable div512 : unsigned(8 downto 0);
variable index : unsigned(3 downto 0);
type NIB10 is array(0 to 9) of std_logic_vector(3 downto 0);
constant UPPERNIB : NIB10 := (X"0", X"1", X"2", X"3", X"4",
X"9", X"A", X"B", X"A", X"D");
begin
if mreset = '1' then
div512 := (others => '0');
index := X"0";
psg1_portBi(7 downto 4) <= (others => '0');
elsif psg_clk'event and psg_clk = '1' then
if div512 = 511 then
if index = 9 then
index := X"0";
else
index := index + 1;
end if;
end if;
div512 := div512 + 1;
psg1_portBi(7 downto 4) <= UPPERNIB(to_integer(index));
end if;
end process;
PSG2 : entity work.ay_3_8910_psg
port map (
I_DA => psg2_di,
O_DA => psg2_do,
O_DA_OE_L => psg2_oe, -- ignore, unused
I_BDIR => psg2_bdir,
I_BC2 => '1',
I_BC1 => psg2_bc1,
O_AUDIO_A => psg2_audioA,
O_AUDIO_B => psg2_audioB,
O_AUDIO_C => psg2_audioC,
I_IOA => X"ff",
O_IOA => psg2_portAo, -- ignore, unused
O_IOA_OE_L => psg2_portAoe, -- ignore, unused
I_IOB => X"ff",
O_IOB => psg2_portBo, -- ignore, unused
O_IOB_OE_L => psg2_portBoe, -- ignore, unused
ENA => '1',
RESET_L => psg_reset,
CLK => psg_clk
);
psg2_awe <= '1' when ((az80_mreq = '0') and
(az80_wr = '0') and
(az80_addr(15 downto 12) = X"7"))
else '0';
psg2_dwe <= '1' when ((az80_mreq = '0') and
(az80_wr = '0') and
(az80_addr(15 downto 12) = X"6"))
else '0';
-- PSG2 strobe
p_psg2io : process(psg_clk, mreset) is
begin
if mreset = '1' then
psg2_bdir <= '0';
psg2_bc1 <= '0';
psg2_di <= (others => '0');
elsif psg_clk'event and psg_clk = '0' then
if (psg2_awe = '1') then
psg2_di <= az80_data_out;
psg2_bdir <= '1';
psg2_bc1 <= '1';
elsif (psg2_dwe = '1') then
psg2_di <= az80_data_out;
psg2_bdir <= '1';
psg2_bc1 <= '0';
else
psg2_bdir <= '0';
psg2_bc1 <= '1';
end if;
end if;
end process;
-- audio filter selections
p_filt : process(psg_clk, mreset) is
begin
if mreset = '1' then
audio_filt_1 <= (others => '0');
audio_filt_2 <= (others => '0');
elsif psg_clk'event and psg_clk = '1' then
if ((az80_mreq = '0') and
(az80_wr = '0') and
(az80_addr(15) = '1')) then
audio_filt_1 <= az80_addr(11 downto 6);
audio_filt_2 <= az80_addr(5 downto 0);
end if;
end if;
end process;
-- =======================================================================
-- Resampler/filter
-- =======================================================================
RESAMPLER : entity work.resampler
port map (
clk => ac97_bit_clk,
reset => mreset,
psgclk => psg_clk,
psgnew => audio_psgnew, -- ignored
sample_1 => audio_sample_1,
select_1 => audio_select_1,
chan1_en => "111",
chan1_filt => audio_filt_1,
sample_2 => audio_sample_2,
select_2 => audio_select_2,
chan2_en => "111",
chan2_filt => audio_filt_2,
audio => audio_data,
audio_en => audio_strobe
);
audio_sample_1 <= psg1_audioA when (audio_select_1 = "00") else
psg1_audioB when (audio_select_1 = "01") else
psg1_audioC when (audio_select_1 = "10") else
X"00";
audio_sample_2 <= psg2_audioA when (audio_select_2 = "00") else
psg2_audioB when (audio_select_2 = "01") else
psg2_audioC when (audio_select_2 = "10") else
X"00";
audio <= audio_data;
aclk48k <= audio_strobe;
end behaviour;
|
gpl-2.0
|
d11579cb8394cfcf510ad1ffb657ae75
| 0.499913 | 3.283502 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab8_new/lab8_new_lib/hdl/ALU_ROM_Behavior.vhd
| 1 | 13,908 |
--
-- VHDL Architecture lab8_new_lib.ALU_ROM.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 14:20:24 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY ALU_ROM IS
GENERIC( output_length: POSITIVE := 24); -- output length n
PORT( inst: IN STD_LOGIC_VECTOR(15 downto 0); -- input instruction
ALU_ROM_Out: OUT STD_LOGIC_VECTOR(output_length-1 downto 0));
END ENTITY ALU_ROM;
--
ARCHITECTURE Behavior of ALU_ROM IS
SIGNAL isShift: std_logic := '0';
SIGNAL alu_opcode: std_logic_vector(2 downto 0) := (OTHERS => '0');
BEGIN
PROCESS(ALL)
BEGIN
isShift <= inst(3);
alu_opcode <= inst(2 downto 0);
-- ALU operations
if( isShift = '0' ) then
CASE alu_opcode IS
-- ADD (0) -- refering to inst 3-0 bits
when "000" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2) (bit 22-21)
"1" & -- Write Back Register control (1 bit)
"0" & "0" & -- Memory Stage Control (bits 19-18) (2 bit)
"0" & "0" & "11" & -- Additional Execute Control (bits 17-14), 4 bit
"0" & "1001" & "00" & "0" & "0" & -- Execute Control (bits 13-5), 9-bit
"0" & "00" & "01"; -- Decode Control (bits 4-0), 5-bit
-- ADC (1)
when "001" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "11" & -- Additional Execute Control
"0" & "1001" & "01" & "0" & "0" & -- Execute Stage Control
"0" & "00" & "01"; -- Decode Stage Control
-- SUB (2)
when "010" => ALU_ROM_Out <=
"1" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "11" & -- Additional Execute Control
"0" & "0110" & "10" & "0" & "0" & -- Execution Stage Control
"0" & "11" & "01"; -- Decode Stage Control
-- SBC (3)
when "011" => ALU_ROM_Out <=
"1" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "11" & -- Additional Execute Control
"0" & "0110" & "11" & "0" & "0" & -- Execution Stage Control
"0" & "11" & "01"; -- Decode Stage Control
-- AND (4)
when "100" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "1110" & "00" & "0" & "0" & -- Execution Stage
"0" & "00" & "01"; -- Decode Stage Control
-- OR (5)
when "101" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "1011" & "00" & "0" & "0" & -- Execution Stage
"0" & "00" & "01"; -- Decode Stage Control
-- XOR (6)
when "110" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"11" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "1001" & "00" & "0" & "0" & -- Execution
"0" & "00" & "01"; -- Decode Stage Control
-- NOT (7)
when "111" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "0000" & "00" & "0" & "0" & -- Execution Stage
"0" & "00" & "01"; -- Decode Stage Control
-- ERROR
when others => ALU_ROM_Out <= (OTHERS => 'X');
END CASE;
-- Shift operations
elsif( isShift = '1') then
CASE alu_opcode IS
-- SL (8)
when "000" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"0" & "1000" & "00" & "1" & "0" & -- Execution Stage
"0" & "00" & "00"; -- Decode Stage
-- SRL (9)
when "001" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"0" & "1001" & "00" & "1" & "0" & -- Execution Stage
"0" & "00" & "00"; -- Decode Stage
-- SRA (10)
when "010" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"0" & "1010" & "00" & "1" & "0" & -- Execution Stage
"0" & "00" & "00"; -- Decode Stage
-- RRA (14) -- **** comment: they're weird
when "110" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "10" & -- Additional Execute Control
"0" & "1110" & "00" & "1" & "0" & -- Execution Stage
"0" & "00" & "00"; -- Decode Stage
-- RR (13)
when "101" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "10" & -- Additional Execute Control
"0" & "1101" & "00" & "1" & "0" & -- Execution Stage
"0" & "00" & "00"; -- Decode Stage
-- RL (12)
when "100" => ALU_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "10" & -- Additional Execute Control
"0" & "1100" & "00" & "1" & "0" & -- Execution Stage
"0" & "00" & "00"; -- Decode Stage
-- ERROR
when others => ALU_ROM_Out <= (OTHERS => 'X');
END CASE;
end if;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
4f069b4ae54d89857fbe8c6990711fdd
| 0.262798 | 5.795 | false | false | false | false |
KimSJ/HDLC_chip
|
arduinointerface.vhd
| 1 | 4,336 |
-- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming strb is left high between accesses)
-- set port low bits to input
-- set RmW, strb to 1, 0 (10 = command "read low-nibble")
-- read the value of b3..b0
-- set strb 1 (11 = command "read high-nibble)
-- read the value of b7..b4 in the low bits of the data you read.
-- for multi-byte reads, repeat last four steps
-- Note: always read the low nibble first, because the high nibble is latched at the same time
-- make sure you wait at least three cycles between writes and reads:
-- OUT <port>, <regA>
-- ORI <regA>, 0x10 // take the opportunity to set up next out value
-- NOP
-- IN <regB>, <port> // read the low nibble
-- OUT <port>, <regA> // set up hi nibble read
-- ANDI <regB>, 0x0F // extract low nibble
-- ANDI <regA>, 0xEF // take the opportunity to set up next out value
-- IN <regC>, <port> // read the high nibble
-- ANDI <regC>, 0x0F
-- SWAP
-- OR <RegC>, <RegB> // build the byte
-- <store it>
-- <check for more data available, then loop>
-- this code should be able to input about one byte/microsecond with 16MHz processor.
-- to write this peripheral:
-- (assuming strb is left high between accesses)
-- set RnW to 0 (strb no change, so no write yet; output buffers now disabled)
-- set port low bits to output
-- write the lo-nibble value, with b5, b4 = 00
-- write the hi-nibble value, with b5, b4 = 01
-- for multi-byte writes, repeat last two steps
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity arduinointerface is
port (
-- arduino pins
data: inout Std_Logic_Vector (3 downto 0);
strb: in Std_Logic;
RnW: in Std_Logic;
clk: in Std_Logic;
rst: in Std_Logic;
-- io pins
rd, wr: out Std_Logic := '0';
q: out Std_Logic_Vector (7 downto 0);
i: in Std_Logic_Vector (7 downto 0)
);
end arduinointerface;
architecture behavioural of arduinointerface is
signal RnWin : Std_Logic_Vector (2 downto 0); -- metastability chain -> shifting down (low bit is "last" value)
signal strbin : Std_Logic_Vector (2 downto 0); -- metastability chain -> shifting down (low bit is "last" value)
signal dout : Std_Logic_Vector (3 downto 0); -- latch for high nibble when low nibble is read
begin
process (clk, strb, RnW, rst)
begin
if rst = '1' then
wr <= '0';
rd <= '0';
RnWin <= (others => '0');
strbin <= (others => '0');
q <= (others => '0');
dout <= (others => '0');
elsif rising_edge(clk) then
-- strobes output for use by peripheral, indicating a read or write has taken place.
wr <= (strbin(1) and not strbin(0)) and not RnWin(1); -- positive-going write pulse edge generated when second nibble written
rd <= (strbin(1) and not strbin(0)) and RnWin(1); -- poistive-going read pulse generated when host requests second nibble
-- shift the metastability chains down
RnWin <= RnW & RnWin (RnWin'length-1 downto 1);
strbin <= strb & strbin (strbin'length-1 downto 1);
-- deal with strobe events
if strbin(1) /= strbin(0) then -- we have a strobe event
if RnWin(1) = '0' then -- we are being written
if strbin(1) = '1' then -- latch the high nibble
q(7 downto 4) <= data;
else -- latch the low nibble
q(3 downto 0) <= data;
end if;
else
if strbin(1) = '0' then -- we're reading the low nibble, so...
dout <= i(7 downto 4); -- ... latch the high nibble at the same time
end if;
end if;
end if;
end if;
end process;
tristate : process (RnWin(1), strbin(1), data) -- Behavioral representation of tri-states.
begin -- pattern from http://www.altera.co.uk/support/examples/vhdl/v_bidir.html
if RnWin(1) = '1' then -- we are being read
if strbin(1) = '0' then -- read the low nibble
data <= i(3 downto 0);
else -- read the high nibble
data <= dout;
end if;
else -- we are being written
data <= "ZZZZ";
end if;
end process;
end behavioural;
|
gpl-3.0
|
d61d40c3cedb92876e3b8b926383fe45
| 0.647601 | 3.174231 | false | false | false | false |
sdenel/An-N-bits-pipelined-addsub-using-VHDL
|
src/fullAdder.vhd
| 1 | 523 |
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity fullAdder is
-- Full, 1 bit adder
port(
a, b, c: in std_logic;
r, s : out std_logic
);
end entity fullAdder;
architecture rtl of fullAdder is
signal s1, c1, c2 : std_logic;
component halfAdder
port(
a, b : in std_logic;
s, c : out std_logic
);
end component halfAdder;
begin
i1: halfAdder port map(a=>a , b=>b, s=>s1, c=>c1);
i2: halfAdder port map(a=>s1, b=>c, s=>s , c=>c2 );
r <= c1 or c2;
end architecture rtl;
|
mit
|
1bbb291d8137def16df842598677e7f5
| 0.636711 | 2.478673 | false | false | false | false |
KimSJ/HDLC_chip
|
hdlcreceiver_tb.vhd
| 1 | 4,392 |
-- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming strb is left high between accesses)
-- set port low bits to input
-- set RmW, strb to 1, 0 (10 = command "read low-nibble")
-- read the value
-- set strb 1 (11 = command "read high-nibble)
-- read the value
-- for multi-byte reads, repeat last four steps
-- to write this peripheral:
-- (assuming strb is left high between accesses)
-- set RnW to 0 (strb no change, so no write yet; output buffers now disabled)
-- set port low bits to output
-- write the lo-nibble value, with b5, b4 = 00
-- write the hi-nibble value, with b5, b4 = 01
-- for multi-byte writes, repeat last two steps
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity hdlcreceiver_tb is
end entity hdlcreceiver_tb;
architecture behavioural of hdlcreceiver_tb is
signal q : Std_Logic_Vector (7 downto 0); -- q is the values read
signal rxLast : Std_Logic; -- the databus
signal rxRD : Std_Logic := '1';
signal rxReq : Std_Logic;
signal rst: Std_Logic :='1';
signal rxErr : Std_Logic; -- high if CRC error
signal rxUnderrun : Std_Logic; -- high if byte not read in time
signal rxAbort : Std_Logic; -- high if Abort received mid-frame
signal clock: Std_Logic := '1';
signal rxD, rxEn: Std_Logic;
signal cycle : integer :=0;
component hdlcreceiver is
generic (
rxReqChainSize : integer := 2
);
port (
-- microprocesser interface
Dout : out Std_Logic_Vector (7 downto 0); -- rx register
rxLast : out Std_Logic;
rxRD : in Std_Logic; -- read strobe
rxReq : out Std_Logic; -- high if data available
rxErr : out Std_Logic; -- high if CRC error
rxUnderrun : out Std_Logic; -- high if byte not read in time
rxAbort : out Std_Logic; -- high if Abort received mid-frame
rxRST : in Std_Logic;
-- bit clock
sysClk : in Std_Logic; -- 16MHz
-- line interface
rxD : in Std_Logic;
rxEn : buffer Std_Logic
);
end component hdlcreceiver;
type tDataItem is record
rxD: Std_Logic;
rxRST: Std_Logic;
rxRD: Std_Logic;
end record tDataItem;
type tDataList is array (0 to 44) of tDataItem;
constant dataList : tDataList := (
-- test abort (10 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
-- test reset to abort clear (1 value)
('0','1','0'),
-- test flag detect (8 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('0','0','0'),
-- test inserted bit removal (9 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('0','0','0'),
('0','0','0'),
('1','0','0'),
-- test normal data -- 0xAA (8 values)
('0','0','0'),
('1','0','0'),
('0','0','0'),
('1','0','0'),
('0','0','0'),
('1','0','0'),
('0','0','0'),
('1','0','0'),
-- test frame-end flag detect (8 values)
('0','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('1','0','0'),
('0','0','0')
);
begin
iface : hdlcreceiver
port map (
Dout => q,
rxLast => rxLast,
rxRD => rxRd,
rxReq => rxReq,
rxErr => rxErr,
rxUnderrun => rxUnderrun,
rxAbort => rxAbort,
rxRST => rst,
-- bit clock
sysClk => clock,
-- line interface
rxD => rxD,
rxEn => rxEn
);
-- rst <= '1' after 0 ns, '0' after 100 ns;
process
-- drive the txClock
begin
clock <= '0';
wait for 62 ns;
clock <= '1';
wait for 63 ns;
end process;
process (clock)
begin
if rising_edge(clock) then
cycle <= (cycle + 1) mod (64 * dataList'length);
if cycle = 0 then
-- i <= (i(0) & i(7 downto 1)) xor "0" & i(0) & "00" & i(0) & "0" & i(0) & "0";
end if;
if (cycle mod 64) = 0 then
rxD <= dataList(cycle/64).rxD;
rst <= dataList(cycle/64).rxRST;
end if;
end if;
end process;
end behavioural;
|
gpl-3.0
|
c106413000a9f9f99f3ee16fac3f8a9d
| 0.559654 | 2.711111 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd
| 1 | 6,873 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
be2c0e56d8b0aeff3c030b2f3ea6c858
| 0.580096 | 3.735326 | false | false | false | false |
a4a881d4/ringbus
|
simio/probe.vhd
| 1 | 2,584 |
-- This unit is a probe
-- The outout will be writen to a file
-- signal1, signal2, signal3, signal4
-- and so on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity probe is
generic ( PROBE_FILE : string := "UNUSED";
SIGNAL1_WIDTH : NATURAL:=6;
SIGNAL1_MASK : integer:=0;
SIGNAL1_TRG : integer:=0;
SIGNAL2_WIDTH : NATURAL:=6;
SIGNAL2_MASK : integer:=0;
SIGNAL2_TRG : integer:=0;
SIGNAL3_WIDTH : NATURAL:=6;
SIGNAL3_MASK : integer:=0;
SIGNAL3_TRG : integer:=0;
SIGNAL4_WIDTH : NATURAL:=6;
SIGNAL4_MASK : integer:=0;
SIGNAL4_TRG : integer:=0);
port (
clk : in std_logic;
signal1 : in std_logic_vector(SIGNAL1_WIDTH-1 downto 0);
signal2 : in std_logic_vector(SIGNAL2_WIDTH-1 downto 0);
signal3 : in std_logic_vector(SIGNAL3_WIDTH-1 downto 0);
signal4 : in std_logic_vector(SIGNAL4_WIDTH-1 downto 0));
end probe;
architecture simulation of probe is
begin
process(clk)
variable init:boolean:=false;
variable lineno:integer:=0;
variable idata:integer:=0;
variable v1mask,v1trg: std_logic_vector( SIGNAL1_WIDTH-1 downto 0);
variable v2mask,v2trg: std_logic_vector( SIGNAL2_WIDTH-1 downto 0);
variable v3mask,v3trg: std_logic_vector( SIGNAL3_WIDTH-1 downto 0);
variable v4mask,v4trg: std_logic_vector( SIGNAL4_WIDTH-1 downto 0);
FILE data_file: TEXT IS OUT PROBE_FILE;
variable buf:line;
begin
v1mask:=CONV_STD_LOGIC_VECTOR(SIGNAL1_MASK,SIGNAL1_WIDTH);
v1trg:=CONV_STD_LOGIC_VECTOR(SIGNAL1_TRG,SIGNAL1_WIDTH);
v2mask:=CONV_STD_LOGIC_VECTOR(SIGNAL2_MASK,SIGNAL2_WIDTH);
v2trg:=CONV_STD_LOGIC_VECTOR(SIGNAL2_TRG,SIGNAL2_WIDTH);
v3mask:=CONV_STD_LOGIC_VECTOR(SIGNAL3_MASK,SIGNAL3_WIDTH);
v3trg:=CONV_STD_LOGIC_VECTOR(SIGNAL3_TRG,SIGNAL3_WIDTH);
v4mask:=CONV_STD_LOGIC_VECTOR(SIGNAL4_MASK,SIGNAL4_WIDTH);
v4trg:=CONV_STD_LOGIC_VECTOR(SIGNAL4_TRG,SIGNAL4_WIDTH);
if clk'event and clk='1' then
if (signal1 and v1mask)=v1trg and
(signal2 and v2mask)=v2trg and
(signal3 and v3mask)=v3trg and
(signal4 and v4mask)=v4trg then
idata:=CONV_INTEGER(unsigned(signal1));
WRITE(buf,hex_to_str(idata),right,8);
idata:=CONV_INTEGER(unsigned(signal2));
WRITE(buf,hex_to_str(idata),right,8);
idata:=CONV_INTEGER(unsigned(signal3));
WRITE(buf,hex_to_str(idata),right,8);
idata:=CONV_INTEGER(unsigned(signal4));
WRITE(buf,hex_to_str(idata),right,8);
WRITELINE(data_file,buf);
end if;
end if;
end process;
end simulation;
|
lgpl-3.0
|
72a5dd19c4ae97b3901adb17ef206888
| 0.696207 | 2.757737 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_float2fix.vhd
| 1 | 7,290 |
-------------------------------------------------------------------------------
--
-- Title : fp23_float2fix
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : Float fp23 to signed fix converter
--
-------------------------------------------------------------------------------
--
-- Version 1.0 15.08.2013
-- Description:
-- Bus width for:
-- din = 23
-- dout = 16
-- exp = 6
-- sign = 1
-- mant = 15 + 1
-- Math expression:
-- A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)
-- NB:
-- Converting from float to fixed takes only 7 clock cycles
--
-- Another algorithm: double precision with 2 DSP48E1.
--
-- Version 1.1 22.08.2014
-- Description: Data width has been changed from 27 to 24.
-- 16 bits - fraction,
-- 1 bit - sign,
-- 7 bits - exponent
--
-- > 2 DSP48E1 blocks used (MEGA_DSP);
--
-- Version 1.2 14.05.2015
-- > SLICEL logic has been simplified;
--
-- Version 1.3 01.11.2015
-- > remove 1 block DSP48E1;
--
-- Version 1.4 01.11.2015
-- > Clear all unrouted signals and components;
--
-- Version 1.5 01.02.2016
-- > Add Barrel shifter instead of DSP48E1;
--
-- Version 1.6 04.04.2016
-- > Careful: check all conditions of input fp data
-- Example: exp = 0x1F, sig = 0, man = 0x0;
--
-- Version 1.7 05.04.2016
-- > Data out width is only 16 bits.
--
-- Version 1.8 07.04.2016
-- > Add constant for negative data converter.
--
-- Version 1.9 22.01.2018
-- > Change exp shift logic.
--
-- Version 1.10 23.01.2018
-- > Overflow and underflow logic has been improved.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library unisim;
--use unisim.vcomponents.LUT6;
library work;
use work.fp_m1_pkg.fp23_data;
entity fp23_float2fix is
generic(
DW : integer:=16 --! Output data width
);
port(
din : in fp23_data; --! Float input data
ena : in std_logic; --! Data enable
scale : in std_logic_vector(05 downto 0); --! Scale factor
dout : out std_logic_vector(DW-1 downto 0); --! Fixed output data
vld : out std_logic; --! Data out valid
clk : in std_logic; --! Clock
reset : in std_logic; --! Negative reset
overflow : out std_logic --! Flag overflow
);
end fp23_float2fix;
architecture fp23_float2fix of fp23_float2fix is
signal exp_dif : std_logic_vector(4 downto 0);
signal exp_dift : std_logic_vector(5 downto 0);
signal mant : std_logic_vector(DW downto 0);
signal implied : std_logic;
signal frac : std_logic_vector(DW-1 downto 0); --
signal sign_z : std_logic_vector(2 downto 0);
signal valid : std_logic_vector(3 downto 0);
signal shift : std_logic_vector(5 downto 0);
--signal man_shift : std_logic_vector(31 downto 0);
signal norm_man : std_logic_vector(DW-1 downto 0);
signal overflow_i : std_logic;
signal exp_null : std_logic;
signal exp_nullz : std_logic;
signal exp_nullt : std_logic;
signal exp_cmp : std_logic;
signal exp_ovr : std_logic;
begin
shift <= scale when rising_edge(clk);
---- exp difference ----
pr_exp: process(clk) is
begin
if rising_edge(clk) then
exp_dift <= din.exp - shift;
end if;
end process;
pr_cmp: process(clk) is
begin
if rising_edge(clk) then
if (din.exp < shift) then
exp_cmp <= '1';
else
exp_cmp <= '0';
end if;
end if;
end process;
exp_null <= exp_cmp when rising_edge(clk);
exp_nullz <= exp_null when rising_edge(clk);
pr_ovf: process(clk) is
begin
if rising_edge(clk) then
if ("001110" < exp_dift) then
exp_ovr <= '1';
else
exp_ovr <= '0';
end if;
end if;
end process;
exp_nullt <= exp_ovr when rising_edge(clk);
-- implied for mantissa and find sign
pr_impl: process(clk) is
begin
if rising_edge(clk) then
if (din.exp = x"00") then
implied <='0';
else
implied <='1';
end if;
end if;
end process;
-- find fraction --
frac <= din.man when rising_edge(clk);
pr_man: process(clk) is
begin
if rising_edge(clk) then
mant <= implied & frac;
end if;
end process;
sign_z <= sign_z(sign_z'left-1 downto 0) & din.sig when rising_edge(clk);
-- barrel shifter --
exp_dif <= not exp_dift(4 downto 0) when rising_edge(clk);
norm_man <= STD_LOGIC_VECTOR(SHR(UNSIGNED(mant(DW downto 1)), UNSIGNED(exp_dif(3 downto 0)))) when rising_edge(clk);
-- data valid and data out --
pr_out: process(clk) is
begin
if rising_edge(clk) then
if (reset = '1') then
dout <= (others => '0');
else
if (exp_nullz = '1') then
dout <= (others => '0');
else
if (exp_nullt = '1') then
dout(DW-1) <= sign_z(2);
for ii in 0 to DW-2 loop
dout(ii) <= not sign_z(2);
end loop;
else
if (sign_z(2) = '1') then
dout <= (not norm_man) + 1;
else
dout <= norm_man;
end if;
end if;
end if;
end if;
end if;
end process;
valid <= valid(valid'left-1 downto 0) & ena when rising_edge(clk);
vld <= valid(valid'left-1) when rising_edge(clk);
pr_ovr: process(clk) is
begin
if rising_edge(clk) then
overflow_i <= exp_nullt and not exp_nullz;--(exp_hi or exp_lo);
end if;
end process;
overflow <= overflow_i when rising_edge(clk);
end fp23_float2fix;
|
mit
|
8cf1f3418c938c685dad576162954b44
| 0.55144 | 3.157211 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab10_WriteBack_Stage/lab10_WriteBack_Stage_lib/hdl/lab10_writeback_stage_struct.vhd
| 1 | 2,710 |
-- VHDL Entity lab10_WriteBack_Stage_lib.lab10_WriteBack_Stage.symbol
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 01:13:04 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY lab10_WriteBack_Stage IS
PORT(
Control : IN std_logic;
Dest : IN std_logic_vector (3 DOWNTO 0);
Value : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
Control_toRegFile : OUT std_logic;
Dest_toRegFile : OUT std_logic_vector (3 DOWNTO 0);
Value_toRegFile : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END lab10_WriteBack_Stage ;
--
-- VHDL Architecture lab10_WriteBack_Stage_lib.lab10_WriteBack_Stage.struct
--
-- Created:
-- by - Hong.Hong (HSM)
-- at - 01:13:04 04/23/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF lab10_WriteBack_Stage IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL load_enable : std_logic;
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
SIGNAL mw_U_0reg_cval : std_logic_vector(15 DOWNTO 0) := "0000000000000000";
-- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'adff'
SIGNAL mw_U_1reg_cval : std_logic_vector(3 DOWNTO 0) := "0000";
-- ModuleWare signal declarations(v1.12) for instance 'U_2' of 'adff'
SIGNAL mw_U_2reg_cval : std_logic := '0';
BEGIN
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
Value_toRegFile <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_U_0reg_cval <= Value;
END IF;
END IF;
END PROCESS u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_1' of 'adff'
Dest_toRegFile <= mw_U_1reg_cval;
u_1seq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_U_1reg_cval <= Dest;
END IF;
END IF;
END PROCESS u_1seq_proc;
-- ModuleWare code(v1.12) for instance 'U_2' of 'adff'
Control_toRegFile <= mw_U_2reg_cval;
u_2seq_proc: PROCESS (clk)BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (load_enable = '1') THEN
mw_U_2reg_cval <= Control;
END IF;
END IF;
END PROCESS u_2seq_proc;
-- ModuleWare code(v1.12) for instance 'ONE' of 'constval'
load_enable <= '1';
-- Instance port mappings.
END struct;
|
gpl-2.0
|
4bd71095d57ef3c472eb53566b59eae4
| 0.607011 | 3.195755 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/dpram1k.vhd
| 1 | 2,048 |
-- A dual-port 1KiB RAM described as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram1k is
port(clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
addra : in std_logic_vector(9 downto 0);
addrb : in std_logic_vector(9 downto 0);
dia : in std_logic_vector(7 downto 0);
dib : in std_logic_vector(7 downto 0);
doa : out std_logic_vector(7 downto 0);
dob : out std_logic_vector(7 downto 0));
end dpram1k;
architecture syn of dpram1k is
type ram_type is array (0 to 1023) of std_logic_vector(7 downto 0);
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if CLKA'event and CLKA = '1' then
if ENA = '1' then
if WEA = '1' then
RAM(conv_integer(ADDRA)) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA));
end if;
end if;
end process;
process (CLKB)
begin
if CLKB'event and CLKB = '1' then
if ENB = '1' then
if WEB = '1' then
RAM(conv_integer(ADDRB)) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB));
end if;
end if;
end process;
end syn;
|
gpl-2.0
|
9f05c1e3bbf63afca2e053b6e138afe7
| 0.646484 | 3.611993 | false | false | false | false |
KimSJ/HDLC_chip
|
hdlctransmitter.vhd
| 1 | 8,359 |
-- hdlctransmitter.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "txLast" set.
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity HdlcTransmitter is
generic (
TxReqChainSize : integer := 2 -- defines length of metastability chain; must be at least two.
);
port (
-- microprocesser interface
Din : in Std_Logic_Vector (7 downto 0); -- Tx register
txLast : in Std_Logic;
txWR : in Std_Logic;
txReq : out Std_Logic; -- high if space in register
txRST : in Std_Logic;
-- bit clock
txCLK : in Std_Logic;
-- line interface
txD : buffer Std_Logic;
txEn : buffer Std_Logic
);
-- translate_off
-- check bounds of generics -- error reported only on execution
begin
assert( txReqChainSize > 1 )
report "txReqChainSize should be at least 2!"
severity ERROR;
-- translate_on
end HdlcTransmitter;
architecture behavioural of HdlcTransmitter is
type txStateType is (Idle, StartFlag, SendData, SendLast, SendCRC1, SendCRC2, FinalFlag);
signal txState, txNextState : txStateType;
signal txFIFO, txShiftReg : Std_Logic_Vector (7 downto 0);
signal txBitCount : Std_Logic_Vector (2 downto 0);
signal txOneCount : Std_Logic_Vector (2 downto 0);
signal txShiftEnable : Std_Logic;
signal txShiftClk, dontSwallow: Std_Logic;
signal txRq : Std_Logic_Vector (txReqChainSize-1 downto 0); -- shifted through to minimise metastability;
-- 0 means reg is full
-- processor watches top bit, HDLC watches bit 0
-- calculate an initialisation vector for txRq chain (all-ones)
signal txReqChainEmpty : Std_Logic_Vector (txReqChainSize-1 downto 0) := (others => '1');
signal crcReg : Std_Logic_Vector (15 downto 0) := x"AAAA";
signal zeroIns : Std_Logic; -- output of state machine indicating that zero insertion after five 1's is active
-- handy alias
signal DataWaiting : boolean;
component crc16 is
port (clk, reset, ce, din: in std_logic;
crc_sum: out std_logic_vector(15 downto 0));
end component crc16;
signal txCrcEn : Std_Logic;
signal crcReset : Std_Logic;
-- translate_off
-- stuff for debugging simulations
signal stateDecode : integer;
signal nextStateDecode : integer;
-- translate_on
begin
-- translate_off
-- stuff for debugging simulations
process (txState) begin
if txState = Idle then
stateDecode <= 0;
elsif txState = StartFlag then
stateDecode <= 1;
elsif txState = SendData then
stateDecode <= 2;
elsif txState = SendLast then
stateDecode <= 3;
elsif txState = SendCRC1 then
stateDecode <= 4;
elsif txState = SendCRC2 then
stateDecode <= 5;
elsif txState = FinalFlag then
stateDecode <= 6;
end if;
end process;
process (txNextState) begin
if txNextState = Idle then
nextStateDecode <= 0;
elsif txNextState = StartFlag then
nextStateDecode <= 1;
elsif txNextState = SendData then
nextStateDecode <= 2;
elsif txNextState = SendLast then
nextStateDecode <= 3;
elsif txNextState = SendCRC1 then
nextStateDecode <= 4;
elsif txNextState = SendCRC2 then
nextStateDecode <= 5;
elsif txNextState = FinalFlag then
nextStateDecode <= 6;
end if;
end process;
-- translate_on
txReq <= txRq(txReqChainSize-1) AND NOT txRST; -- use top bit so it appears full to processor as soon as reg is written. De-assert when reset
txD <= txShiftReg(0);
DataWaiting <= txRq(0) = '0';
-- pulse dontSwallower: removes a txCLK pulse when zero insertion required
txShiftClk <= txClk and dontSwallow;
pTxShiftClk : process(txCLK, txOneCount)
begin
if falling_edge(txCLK) then
if txOneCount="100" and txD = '1' and zeroIns = '1' then
dontSwallow <= '0';
else
dontSwallow <= '1';
end if;
end if;
end process pTxShiftClk;
-- latching data into tx holding reg (FIFO)
pTxFIFO : process(txRST, txWR)
begin
if txRST = '1' then
txFIFO <= "00000000";
elsif rising_edge(txWR) then
txFIFO <= Din;
end if;
end process pTxFIFO;
-- txEn
pTxEn : process(txRST, txCLK)
begin
if txRST = '1' then
txEn <= '0';
elsif rising_edge(txCLK) then
if txState = Idle then
txEn <= '0';
else
txEn <= '1';
end if;
end if;
end process pTxEn;
-- ZeroIns
pZeroIns : process(txRST, txCLK)
begin
if txRST = '1' then
zeroIns <= '0';
elsif rising_edge(txCLK) then
case txState is
when Idle | StartFlag | FinalFlag => zeroIns <= '0';
when others =>zeroIns <= '1';
end case;
end if;
end process pZeroIns;
-- generate Tx request signal for processor
pTxRq : process(txRST, txWR, txCLK)
begin
if txRST = '1' then
txRq <= txReqChainEmpty; -- mark reg empty
elsif rising_edge(txWR) then
txRq (txReqChainSize-1) <= '0'; -- insert "full" signal at top of metastab chain
elsif rising_edge(txCLK) and dontSwallow = '1' then
if txBitCount = "000" and (txState = SendData OR txState = SendLast) then -- loading byte into shift reg
txRq <= txReqChainEmpty; -- signal that we've taken the data
else
txRq(txReqChainSize-2 downto 0) <= txRq(txReqChainSize-1 downto 1); -- shift the "full" signal through metastab chain
end if;
end if;
end process pTxRq;
-- mark where crc should be calculated
process (txState, txShiftClk)
begin
if rising_edge(txShiftClk) then
if txState = SendData or txState = SendLast then
txCrcEn <= '1';
crcReset <= '0';
else
txCrcEn <= '0';
if txState = idle then
crcReset <='1';
else
crcReset <='0';
end if;
end if;
end if;
end process;
-- calculate CRC -- instantiate CRC engine
TxCrcGen : crc16
port map ( clk => txShiftClk,
reset => crcReset,
ce => txCrcEn,
din => txD,
crc_sum => crcReg
);
-- ******* Main state machine *********
-- register
process(txShiftClk, txRST)
-- clocked on bit count rolling over (8 bits tx'd)
begin
if txRST = '1' then
txState <= Idle;
elsif rising_edge(txShiftClk) then
if txBitCount = "000" then
txState <= txNextState;
else
txState <= txState;
end if;
end if;
end process;
-- state register inputs
process
( DataWaiting, txState --
)
begin
case txState is
when Idle =>
if DataWaiting then
txNextState <= StartFlag;
else
txNextState <= Idle;
end if;
when StartFlag =>
txNextState <= SendData;
when SendData =>
if txLast = '1' then
txNextState <= SendLast;
else
txNextState <= SendData;
end if;
when SendLast =>
txNextState <= SendCRC1;
when SendCRC1 =>
txNextState <= SendCRC2;
when SendCRC2 =>
txNextState <= FinalFlag;
when FinalFlag =>
txNextState <= Idle;
end case;
end process;
-- clocking data into shift reg (out of tx holding reg, CRC, flag or abort)
pTxData : process(txRST, txRq, txCLK, txShiftEnable)
begin
if txRST = '1' then
txBitCount <= "000";
elsif rising_edge(txCLK) then
if txOneCount = "100" and txD ='1' and ZeroIns = '1' then
txShiftReg(0) <= '0';
-- note we're not incrementing the bit count whilst we insert the extra zero
else
txBitCount <= Std_Logic_Vector(unsigned(txBitCount) + 1); -- increment bit count
if txBitCount = "000" and dontSwallow = '1' then -- we've reached a byte boundary
case txState is
when Idle | StartFlag | FinalFlag =>
txShiftReg <= "01111110";
when SendData | SendLast =>
if txRq(0) = '1' then
-- we have underrun
-- TODO: insert underrun handling
else
-- load in next byte
txShiftReg <= txFIFO;
end if;
when SendCRC1 =>
txShiftReg <= crcReg (15 downto 8);
when SendCRC2 =>
txShiftReg <= crcReg (7 downto 0);
end case;
else -- we need to shift out next bit
txShiftReg (6 downto 0) <= txShiftReg (7 downto 1);
end if;
end if;
end if;
end process pTxData;
-- Ones counter counts successive ones when enabled
pTxOneCount : process(txCLK, txRST, txEn)
begin
if txRST = '1' OR txEn = '0' then
txOneCount <= "000";
elsif rising_edge(txCLK) then
if txShiftReg (0) = '0' then
txOneCount <= "000";
else
txOneCount <= Std_Logic_Vector(unsigned(txOneCount) + 1);
end if;
end if;
end process pTxOneCount;
end behavioural;
|
gpl-3.0
|
598b04b83fd37783a375e065d50ff40d
| 0.661323 | 3.347617 | false | false | false | false |
NESHomebrew/cs207-NES-Guitar-Synth
|
DesignLab Libraries/A245/Chip_Designer/Simulate_Your_Chip_Design.vhd
| 1 | 1,502 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library DesignLab;
--use DesignLab.ALL;
entity Simulate_Your_CCL_Design is
end entity;
architecture sim of Simulate_Your_CCL_Design is
constant period: time := 10 ns;
signal clk: std_logic := '1';
signal rst: std_logic := '0';
COMPONENT A245
PORT(
--Put your custom external connections here
buttons : IN std_logic_vector(3 downto 0);
leds : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Define your external connections here
signal buttons: std_logic_vector(3 downto 0) := "1010";
signal leds: std_logic_vector(3 downto 0);
begin
clk <= not clk after period/2;
-- Reset
process
begin
wait for 5 ns;
rst <= '1';
wait for 20 ns;
rst <= '0';
wait;
end process;
uut: A245 PORT MAP(
--Define your external connections here
buttons => buttons,
leds => leds
);
process
begin
wait until rst='1';
wait until rst='0';
wait until rising_edge(clk);
-- This is where you should start providing your stimulus to test your design.
-- Provide stimulus on the buttons
buttons <= "0000";
wait for 100 ns;
-- Check that the leds match
assert( leds = "0000");
-- Provide stimulus on the buttons
buttons <= "1111";
wait for 100 ns;
-- Check that the leds match
assert( leds = "1111");
wait for 200 ns;
report "Finsihed" severity failure;
end process;
end sim;
|
mit
|
f316c9e3c194b93f14da1353f0166187
| 0.651798 | 3.429224 | false | false | false | false |
KimSJ/HDLC_chip
|
icestick_arduino.vhd
| 1 | 3,728 |
-- iCEcube top-level file
-- Example Arduino interface for iCEstick
--
-- eight outputs connected to LEDs and some of J3; eight inputs connected to J1
--
-- Notes:
-- OSCI is 12 MHz on pin 2 of USB chip
--
library IEEE;
use IEEE.STD_LOGIC_1164.All;
entity iCEstick_arduino is
port (
-- J1 ("top")
PIO0_02 : inout Std_Logic; -- J1 p3
PIO0_03 : inout Std_Logic; -- J1 p4
PIO0_04 : inout Std_Logic; -- J1 p5
PIO0_05 : inout Std_Logic; -- J1 p6
PIO0_06 : inout Std_Logic; -- J1 p7
PIO0_07 : inout Std_Logic; -- J1 p8
PIO0_08 : inout Std_Logic; -- J1 p9
PIO0_09 : inout Std_Logic; -- J1 p10
-- J2 (Pmod socket)
PIO1_02 : inout Std_Logic; -- connector p1
PIO1_03 : inout Std_Logic; -- connector p2
PIO1_04 : inout Std_Logic; -- connector p3
PIO1_05 : inout Std_Logic; -- connector p4
PIO1_06 : inout Std_Logic; -- connector p7
PIO1_07 : inout Std_Logic; -- connector p8
PIO1_08 : inout Std_Logic; -- connector p9
PIO1_09 : inout Std_Logic; -- connector p10
-- J3 ("bottom")
PIO2_17 : inout Std_Logic; -- J3 p3
PIO2_16 : inout Std_Logic; -- J3 p4
PIO2_15 : inout Std_Logic; -- J3 p5
PIO2_14 : inout Std_Logic; -- J3 p6
PIO2_13 : inout Std_Logic; -- J3 p7
PIO2_12 : inout Std_Logic; -- J3 p8
PIO2_11 : inout Std_Logic; -- J3 p9
PIO2_10 : inout Std_Logic; -- J3 p10
-- LED port
-- red LEDs numbered clockwise
LED1 : inout Std_Logic; -- PIO1_14 Red
LED2 : inout Std_Logic; -- PIO1_13 Red
LED3 : inout Std_Logic; -- PIO1_12 Red
LED4 : inout Std_Logic; -- PIO1_11 Red
-- green LED
LED5 : inout Std_Logic; -- PIO1_10 Green
-- IrDA
RXD : inout Std_Logic; -- PIO1_19 Receive data pin
TXD : inout Std_Logic; -- PIO1_18 Transmit data pin
SD : inout Std_Logic; -- PIO1_20 Shut down
-- RS232 (connection to USB chip)
RS232_Rx_TTL : inout Std_Logic;
RS232_Tx_TTL : inout Std_Logic;
RTSn : inout Std_Logic;
DTRn : inout Std_Logic;
CTSn : inout Std_Logic;
DSRn : inout Std_Logic;
DCDn : inout Std_Logic;
-- SPI/Config
SPI_SCK : inout Std_Logic;
SPI_SI : inout Std_Logic;
SPI_SO : inout Std_Logic;
SPI_SS_B : inout Std_Logic;
CDONE : inout Std_Logic;
CREST : inout Std_Logic;
-- pin 21 is driven from iCE_CLK -- 12MHz osc.
clk : inout Std_Logic
);
end iCEstick_arduino;
architecture behavioural of iCEstick_arduino is
component arduinointerface is
port (
data: inout Std_Logic_Vector (3 downto 0);
strb: in Std_Logic;
RnW: in Std_Logic;
clk: in Std_Logic;
rst: in Std_Logic;
-- io pins
rd, wr: out Std_Logic := '0';
q: out Std_Logic_Vector (7 downto 0);
i: in Std_Logic_Vector (7 downto 0)
);
end component arduinointerface;
begin
top : arduinointerface
port map (
-- arduino pins on the Pmod socket
data(0) => PIO1_02,
data(1) => PIO1_03,
data(2) => PIO1_04,
data(3) => PIO1_05,
strb => PIO1_06,
RnW => PIO1_07,
clk => PIO1_08,
rst => PIO1_09,
-- io pins
rd => PIO2_11, -- J3 p9
wr => PIO2_10, -- J3 p10
q(7) => PIO2_17,
q(6) => PIO2_16,
q(5) => PIO2_15,
q(4) => LED5,
q(3) => LED4,
q(2) => LED3,
q(1) => LED2,
q(0) => LED1, -- J3 and LEDs
i(7) => PIO0_09,
i(6) => PIO0_08,
i(5) => PIO0_07,
i(4) => PIO0_06,
i(3) => PIO0_05,
i(2) => PIO0_04,
i(1) => PIO0_02,
i(0) => PIO0_02 -- J1
);
end behavioural;
|
gpl-3.0
|
94aab65bf2c88a564bf48922d7dd7dfb
| 0.543991 | 2.44459 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/top_ghdl_sdl.vhd
| 1 | 3,538 |
-- SDL adapter for Konami Arcade Emulator
-- (C) Copyright 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
use work.sdl_ghdl.all;
-- no-ports top-level entity
entity top_ghdl_sdl is
end entity top_ghdl_sdl;
architecture behaviour of top_ghdl_sdl is
-- clocks and resets
signal mclk : std_logic;
signal mreset : std_logic;
-- video signals
signal red : std_logic_vector(7 downto 0);
signal grn : std_logic_vector(7 downto 0);
signal blu : std_logic_vector(7 downto 0);
signal xpixel : std_logic_vector(7 downto 0);
signal ypixel : std_logic_vector(7 downto 0);
signal pxclk : std_logic;
signal hsync : std_logic;
signal hblank : std_logic;
signal phblank : std_logic;
signal vsync : std_logic;
signal vblank : std_logic;
signal pvblank : std_logic;
-- audio signals
signal audio : std_logic_vector(17 downto 0);
signal aclk : std_logic;
begin -- behaviour
-- generate the master reset
master_reset : process
variable dummy: integer := 0;
begin
dummy := init_sdl(0);
mreset <= '1';
wait for 100 us;
mreset <= '0';
wait;
end process master_reset;
-- generate the 36.864 MHz master clock
master_clk : process
begin
loop
mclk <= '0';
wait for 13.942 ns;
mclk <= '1';
wait for 13.942 ns;
end loop;
end process master_clk;
-- game implementation
TIME_PILOT : entity work.time_pilot
generic map (
LOGINFO => true
)
port map (
mclk => mclk,
mreset => mreset,
p1start => '1',
p2start => '1',
coin1 => '1',
coin2 => '1',
fire => '1',
joy_up => '1',
joy_down => '1',
joy_left => '1',
joy_right => '1',
dip1 => X"ff",
dip2 => X"f3",
red => red,
grn => grn,
blu => blu,
hsync => hsync,
hblank => hblank,
vsync => vsync,
vblank => vblank,
xpixel => xpixel,
ypixel => ypixel,
pxclk => pxclk,
audio => audio,
aclk48k => aclk
);
-- marshal video signal to SDL frame
-- original screen rotated 90 degrees (
sdl_video : process(pxclk)
variable dummy : integer := 0;
begin
if pxclk'event and pxclk = '1' then
if vblank = '0' and hblank = '0' then
dummy := put_pixel(255 - to_integer(unsigned(ypixel)),
to_integer(unsigned(xpixel)),
to_integer(unsigned(red)),
to_integer(unsigned(grn)),
to_integer(unsigned(blu)));
end if;
end if;
end process sdl_video;
end behaviour;
|
gpl-2.0
|
0d1caaf259b0d49af775c9fa24e4ae0c
| 0.590164 | 3.732068 | false | false | false | false |
fkmclane/AutoPidact
|
vhdl/PWM.vhd
| 1 | 730 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
cycle : natural := 50000;
width : natural := 255
);
port(
clk : in std_logic;
pwm : in unsigned;
q : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal clock : std_logic := '1';
begin
cg0: entity work.ClockGenerator
generic map(count => cycle)
port map(clk => clk, rst => '1', q => clock);
process(clock, pwm)
variable value : integer range 0 to width := 0;
begin
if (clock'event) and (clock = '1') then
value := value + 1;
end if;
if (value > width) then
value := 0;
end if;
if (value >= pwm) then
q <= '0';
else
q <= '1';
end if;
end process;
end RTL;
|
mit
|
9b6194b7d27aa86b586b7b7bc57d4251
| 0.60137 | 2.796935 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/memory/Ram.vhd
| 1 | 1,933 |
-------------------------------------
-- ?g word 32 bit SRAM --
-- PORT MAPPING --
-- DATA: 32 bit input value --
-- ADDR: ceil(log2(?g)) bit address--
-- WE : 1 bit write enable --
-- EN : 1 bit enable --
-- CLK : 1 bit RAM clock --
-------------------------------------
-- OUT: 32 bit output value --
-------------------------------------
USE WORK.ram_types.ALL;
LIBRARY ieee;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY ram IS
GENERIC
(
g_addr_width : POSITIVE := 10
);
PORT
(
in_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_addr : IN STD_LOGIC_VECTOR(g_addr_width - 1 DOWNTO 0);
in_we : IN STD_LOGIC;
in_en : IN STD_LOGIC;
in_clk : IN STD_LOGIC;
----------------------------------------------------------
out_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ram;
ARCHITECTURE behavioral OF ram IS
SIGNAL s_memory : ram_data(2**g_addr_width - 1 DOWNTO 0);
------------------------------------------------------------------
-- RAM initialization with data file --
ATTRIBUTE ram_init_file : string; --
ATTRIBUTE ram_init_file OF s_memory: SIGNAL IS "quanta.mif"; --
------------------------------------------------------------------
BEGIN
PROCESS(in_en, in_clk)
BEGIN
-- Read/Write to memory on rising edge if enabled
IF(in_en = '1' AND RISING_EDGE(in_clk)) THEN
IF(in_we = '1') THEN
-- Write input word to addr
s_memory(CONV_INTEGER(in_addr)) <= in_data;
ELSE
-- Read output word from addr
out_data <= s_memory(CONV_INTEGER(in_addr));
END IF;
END IF;
END PROCESS;
END behavioral;
|
mit
|
984b549c4ff26737d6fdbcd02d3a64db
| 0.431971 | 4.183983 | false | false | false | false |
arcade-lab/uarch-phases
|
src/lib/tracing/tracing.vhd
| 1 | 8,865 |
------------------------------------------------------------------------------
-- This file is part of a signal tracing utility for the LEON3 processor
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
-- Copyright (C) 2013, System Level Design (SLD) group @ Columbia University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Component: tracing
-- File: tracing.vhd
-- Author(s): Van Bui - ARCADE @ Columbia University
-- Paolo Mantovani - SLD @ Columbia University
-- Description: Logger for processor signals
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
package tracing is
constant PCOUTLOW : integer range 0 to 2 := 0;
constant MEM_SIZE_LOG : integer := 20;
constant MEM_BITS : integer := 32;
constant WIN_SIZE_LOG : integer := 21;
constant BANK_SIZE_LOG : integer := 14;
constant COUNT_BITS : integer := MEM_SIZE_LOG;
constant ACTIVITY_BITS : integer := 4;
constant AHB_BITS : integer := 2;
constant NUM_SRAMS : integer := 60;
constant NUM_SAMPLES : integer := 983040;
constant PC_BITS : integer := MEM_BITS;
constant haddr_mask : std_logic_vector(MEM_BITS-1 downto 0) := X"000FFFFF";
constant zero_adx : std_logic_vector(MEM_SIZE_LOG - 1 downto 0) := (others => '0');
constant one_adx : std_logic_vector(MEM_SIZE_LOG - 1 downto 0) := conv_std_logic_vector(1, MEM_SIZE_LOG);
constant one_count : std_logic_vector(COUNT_BITS - 1 downto 0) := conv_std_logic_vector(1, COUNT_BITS);
constant pc_adx : std_logic_vector(MEM_SIZE_LOG - 1 downto 0) := conv_std_logic_vector(4, MEM_SIZE_LOG);
constant pc_act : std_logic_vector(ACTIVITY_BITS - 1 downto 0) := conv_std_logic_vector(0, ACTIVITY_BITS);
constant inst_adx : std_logic_vector(MEM_SIZE_LOG - 1 downto 0) := conv_std_logic_vector(6, MEM_SIZE_LOG);
constant inst_act : std_logic_vector(ACTIVITY_BITS - 1 downto 0) := conv_std_logic_vector(1, ACTIVITY_BITS);
constant ahb_adx : std_logic_vector(MEM_SIZE_LOG - 1 downto 0) := conv_std_logic_vector(7, MEM_SIZE_LOG);
constant ahb_act : std_logic_vector(ACTIVITY_BITS - 1 downto 0) := conv_std_logic_vector(2, ACTIVITY_BITS);
constant nop_sig : std_logic_vector(MEM_BITS-1 downto 0) := X"01000000";
constant memop : std_logic_vector(1 downto 0) := conv_std_logic_vector(3,2);
constant NWIN : integer := 8;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
subtype pcouttype is std_logic_vector(MEM_BITS-1 downto PCOUTLOW);
subtype word is std_logic_vector(MEM_BITS-1 downto 0);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
type uvector is array (integer range <>) of std_ulogic;
type vectorarray is array (integer range <>) of std_logic_vector(MEM_BITS-1 downto 0);
type dcachestatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag, dblwrite, loadpend);
type icachestatetype is (idle, trans, streaming, stop);
type exceptionstatetype is (run, trap, dsu1, dsu2);
-- pipeline outputs
type fetch_reg_out_type is record
pc : pcouttype;
branch : std_ulogic;
end record;
type decode_reg_out_type is record
pc : pcouttype;
inst : word;
pv : std_ulogic;
annul : std_ulogic;
end record;
type regacc_reg_out_type is record
pc : pcouttype;
inst : word;
pv : std_ulogic;
rfe1 : std_ulogic;
rfe2 : std_ulogic;
annul : std_ulogic;
rfa1 : rfatype;
rfa2 : rfatype;
end record;
type execute_reg_out_type is record
pc : pcouttype;
inst : word;
pv : std_ulogic;
rfe : std_ulogic;
annul : std_ulogic;
op1 : word;
op2 : word;
cnt : std_logic_vector(1 downto 0);
ld : std_ulogic;
end record;
type memory_reg_out_type is record
pc : pcouttype;
inst : word;
pv : std_ulogic;
dci_enaddr : std_ulogic;
annul : std_ulogic;
ld : std_ulogic;
result : word;
end record;
type exception_reg_out_type is record
pc : pcouttype;
rstate : exceptionstatetype;
inst : word;
annul : std_ulogic;
annul_all : std_ulogic;
result : word;
ld : std_ulogic;
pv : std_ulogic;
end record;
type write_reg_out_type is record
wreg : std_ulogic;
result : word;
wa : rfatype;
end record;
type trace_dcache_type is record
enaddr : std_ulogic;
nullify : std_ulogic;
read : std_ulogic;
regread : std_ulogic;
dstate : dcachestatetype;
hit : std_ulogic;
valid : std_ulogic;
forcemiss : std_ulogic;
pagefault : std_ulogic;
lock : std_ulogic;
asi : std_ulogic;
end record;
type trace_icache_type is record
inull : std_ulogic;
istate : icachestatetype;
fault : std_ulogic;
end record;
type ipreg_out_type is record
f : fetch_reg_out_type;
d : decode_reg_out_type;
a : regacc_reg_out_type;
e : execute_reg_out_type;
m : memory_reg_out_type;
x : exception_reg_out_type;
w : write_reg_out_type;
holdn : std_ulogic;
fpohold : std_ulogic;
dcohold : std_ulogic;
icohold : std_ulogic;
dcache : trace_dcache_type;
icache : trace_icache_type;
bpmiss : std_ulogic;
muli : std_ulogic;
divi : std_ulogic;
exbpmiss : std_ulogic;
rabpmiss : std_ulogic;
deannul : std_ulogic;
muloready : std_ulogic;
divoready : std_ulogic;
end record;
type ipsigs is record
sig1 : std_logic_vector(7 downto 0);
sig2 : std_logic_vector(7 downto 0);
sig3 : std_logic_vector(7 downto 0);
sig4 : std_logic_vector(7 downto 0);
end record;
type softsigs is record
reset_stats : std_ulogic;
dump_stats : std_ulogic;
sample_rate : std_ulogic;
sample_event : std_ulogic;
end record;
component ahb_rate_trace is
generic (
tech : integer := virtex7;
hindex : integer range 0 to NAHBSLV-1 := 5;
hmask : integer := 16#ffc#;
haddr : integer := 16#b00#;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ipreg : in ipreg_out_type;
ahbso : out ahb_slv_out_type);
end component;
component packer
port (
rst : in std_ulogic;
clk : in std_ulogic;
ipreg : in ipreg_out_type;
mem_selected : in std_logic_vector(AHB_BITS-1 downto 0);
activity : in std_logic_vector(ACTIVITY_BITS-1 downto 0);
packsigs : out std_logic_vector(MEM_BITS-1 downto 0) := (others => '0'));
end component; -- packer
component syncram_dp_wrapper
generic (
tech : integer := 0;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
rdaddr : in std_logic_vector((MEM_SIZE_LOG-1) downto 0);
rden : in std_ulogic;
packsigs : in std_logic_vector((MEM_BITS -1) downto 0);
sample : in std_ulogic;
reset_log : in std_ulogic;
stop_log : in std_ulogic;
full_log : out std_ulogic;
memout : out std_logic_vector(MEM_BITS-1 downto 0);
irq : out std_logic_vector(NAHBIRQ-1 downto 0));
end component;
component detect_mem_access is
port (
ahbsi : in ahb_slv_in_type;
mem_selected : out std_logic_vector(AHB_BITS-1 downto 0));
end component;
end tracing;
|
gpl-3.0
|
347d9ae092c4fd509153c955bac2ce53
| 0.585561 | 3.570278 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE1-SoC/DE1_SoC_TRDB_D5M_top_level.vhd
| 1 | 6,415 |
-- #############################################################################
-- DE1_SoC_TRDB_D5M_top_level.vhd
-- ==============================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.8
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_TRDB_D5M_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic;
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_TRDB_D5M_top_level;
architecture rtl of DE1_SoC_TRDB_D5M_top_level is
begin
end;
|
unlicense
|
10941c46820596ef98e9170cdd1fd65f
| 0.510678 | 3.126218 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE0-Nano-SoC/DE0_Nano_SoC_TRDB_D5M_LT24_top_level.vhd
| 1 | 4,960 |
-- #############################################################################
-- DE0_Nano_SoC_TRDB_D5M_LT24_top_level.vhd
-- ========================================
--
-- BOARD : DE0-Nano-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.5
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_SoC_TRDB_D5M_LT24_top_level is
port(
-- ADC
ADC_CONVST : out std_logic;
ADC_SCK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
-- ARDUINO
ARDUINO_IO : inout std_logic_vector(15 downto 0);
ARDUINO_RESET_N : inout std_logic;
-- CLOCK
FPGA_CLK1_50 : in std_logic;
FPGA_CLK2_50 : in std_logic;
FPGA_CLK3_50 : in std_logic;
-- KEY
KEY_N : in std_logic_vector(1 downto 0);
-- LED
LED : out std_logic_vector(7 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- GPIO_0
GPIO_0_LT24_ADC_BUSY : in std_logic;
GPIO_0_LT24_ADC_CS_N : out std_logic;
GPIO_0_LT24_ADC_DCLK : out std_logic;
GPIO_0_LT24_ADC_DIN : out std_logic;
GPIO_0_LT24_ADC_DOUT : in std_logic;
GPIO_0_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_0_LT24_CS_N : out std_logic;
GPIO_0_LT24_D : out std_logic_vector(15 downto 0);
GPIO_0_LT24_LCD_ON : out std_logic;
GPIO_0_LT24_RD_N : out std_logic;
GPIO_0_LT24_RESET_N : out std_logic;
GPIO_0_LT24_RS : out std_logic;
GPIO_0_LT24_WR_N : out std_logic;
-- GPIO_1
GPIO_1_D5M_D : in std_logic_vector(11 downto 0);
GPIO_1_D5M_FVAL : in std_logic;
GPIO_1_D5M_LVAL : in std_logic;
GPIO_1_D5M_PIXCLK : in std_logic;
GPIO_1_D5M_RESET_N : out std_logic;
GPIO_1_D5M_SCLK : inout std_logic;
GPIO_1_D5M_SDATA : inout std_logic;
GPIO_1_D5M_STROBE : in std_logic;
GPIO_1_D5M_TRIGGER : out std_logic;
GPIO_1_D5M_XCLKIN : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C0_SCLK : inout std_logic;
HPS_I2C0_SDAT : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE0_Nano_SoC_TRDB_D5M_LT24_top_level;
architecture rtl of DE0_Nano_SoC_TRDB_D5M_LT24_top_level is
begin
end;
|
unlicense
|
4c56e77a3464c623a9969da29e684a5f
| 0.510282 | 3.044813 | false | false | false | false |
sahandKashani/Altera-FPGA-top-level-files
|
DE1-SoC/DE1_SoC_top_level.vhd
| 1 | 5,944 |
-- #############################################################################
-- DE1_SoC_top_level.vhd
-- =====================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.7
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_top_level;
architecture rtl of DE1_SoC_top_level is
begin
end;
|
unlicense
|
dc96d11e0465e0383212ca0478303e5a
| 0.509421 | 3.195699 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/CHAR_ROM/simulation/bmg_stim_gen.vhd
| 1 | 12,571 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (6 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0):= hex_to_std_logic_vector("0",7);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(6 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(6 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"CHAR_ROM.mif",
DEFAULT_DATA,
7,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
mit
|
02d763ce37a97888532d12dcc18f918e
| 0.547371 | 3.68327 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/CHAR_ROM/simulation/CHAR_ROM_tb.vhd
| 1 | 4,355 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: CHAR_ROM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY CHAR_ROM_tb IS
END ENTITY;
ARCHITECTURE CHAR_ROM_tb_ARCH OF CHAR_ROM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
CHAR_ROM_synth_inst:ENTITY work.CHAR_ROM_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
mit
|
770bb20800a060f41650ae9d11c39772
| 0.619059 | 4.623142 | false | false | false | false |
hsm5xw/ece4435-final-project
|
ECE 4435_finalProject_codeEdit/ECE4435_finalProject_code/HDS/lab8_new/lab8_new_lib/hdl/Decode_ROM_Behavior.vhd
| 1 | 10,298 |
--
-- VHDL Architecture lab8_new_lib.Decode_ROM.Behavior
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 14:18:05 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
--
-- VHDL Architecture lab_8_lib.ROM.synth
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 10:44:11 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Decode_ROM IS
GENERIC( output_length: POSITIVE := 24); -- output length n
PORT( inst: IN STD_LOGIC_VECTOR(15 downto 0); -- 16-bit input
Decode_ROM_Out: OUT STD_LOGIC_VECTOR(output_length-1 downto 0));
END ENTITY Decode_ROM;
--
ARCHITECTURE Behavior OF Decode_ROM IS
SIGNAL Testing_opcode: std_logic_vector(2 downto 0);
BEGIN
PROCESS(ALL)
VARIABLE Decode_ROM_opcode: std_logic_vector(2 downto 0) := (OTHERS => '0'); -- 3 bit opcode( bit 15-13 )
BEGIN
Decode_ROM_opcode := inst(15 downto 13);
Testing_opcode <= Decode_ROM_opcode;
CASE Decode_ROM_opcode IS
-- LD
when "001" => Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes bit 23)
"10" & -- Register Tracker Control (op1, op2) (bit 22-21)
"1" & -- Write Back Register Control (bit 20)
"1" & "0" & -- Memory Stage Control (bits 19-18), 2 bit
"0" & "0" & "00" & -- Additional Execute Control (bits 17-14), 4bit
"0" & "1001" & "00" & "0" & "0" & -- Execute Control (bits 13-5), 9-bit
"0" & "00" & "00"; -- Decode Control (bits 4-0), 5-bit
-- ST
when "010" => Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"01" & -- Register Tracker Control (op1, op2)
"0" & -- Write Back Register Control
"0" & "1" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"0" & "1001" & "00" & "0" & "0" & -- Execute Control
"0" & "00" & "00"; -- Decode Control
-- MOV
when "011" => Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "1111" & "00" & "0" & "0" & -- Execute Control
"0" & "00" & "00"; -- Decode Control
-- LIL, LIH
when "100" =>
if( inst(8) = '0') then
Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"00" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "1111" & "00" & "0" & "0" & -- Execute Control
"0" & "01" & "00"; -- Decode Control
elsif( inst(8) = '1') then
Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"01" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"1" & "1111" & "00" & "0" & "0" & -- Execute Control
"0" & "10" & "00"; -- Decode Control
end if;
-- JMP, JAL
when "110" =>
if( inst(8) = '0') then
Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"10" & -- Register Tracker Control (op1, op2)
"0" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"1" & "0" & "00" & -- Additional Execute Control
"0" & "1001" & "00" & "0" & "0" & -- Execute Control
"1" & "00" & "10"; -- Decode Control
elsif( inst(8) = '1') then
Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"10" & -- Register Tracker Control (op1, op2)
"1" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"1" & "1" & "00" & -- Additional Execute Control
"0" & "1001" & "00" & "0" & "0" & -- Execute Control
"1" & "00" & "10"; -- Decode Control
end if;
-- Branches
when "111" =>
-- BR
if( inst(12 downto 9) = "0000" ) then
Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"00" & -- Register Tracker Control (op1, op2)
"0" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"1" & "0" & "00" & -- Additional Execute Control
"0" & "1001" & "00" & "0" & "1" & -- Execute Control
"0" & "01" & "11"; -- Decode Control
-- BC, BO, BN, BZ
else Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"00" & -- Register Tracker Control (op1, op2)
"0" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"0" & "1001" & "00" & "0" & "1" & -- Execute Control
"0" & "01" & "11"; -- Decode Control
end if;
-- NOP
when "000" => Decode_ROM_Out <=
"0" & -- Extra Decode Control (from error fixes)
"00" & -- Register Tracker Control (op1, op2)
"0" & -- Write Back Register Control
"0" & "0" & -- Memory Stage Control
"0" & "0" & "00" & -- Additional Execute Control
"0" & "0000" & "00" & "0" & "0" & -- Execute Control
"0" & "00" & "00"; -- Decode Control
when others => Decode_ROM_Out <= (OTHERS => 'X'); -- ignore otherwise
END CASE;
END PROCESS;
END ARCHITECTURE Behavior;
|
gpl-2.0
|
4b86a37d45d76b3152853982f89e0713
| 0.284036 | 5.569497 | false | false | false | false |
Zunth5/LED-CLOCK
|
LEDgrid/ipcore_dir/CHAR_ROM.vhd
| 1 | 5,384 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file CHAR_ROM.vhd when simulating
-- the core, CHAR_ROM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY CHAR_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END CHAR_ROM;
ARCHITECTURE CHAR_ROM_a OF CHAR_ROM IS
-- synthesis translate_off
COMPONENT wrapped_CHAR_ROM
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_CHAR_ROM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 10,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "CHAR_ROM.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 1024,
c_read_depth_b => 1024,
c_read_width_a => 7,
c_read_width_b => 7,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 1024,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 7,
c_write_width_b => 7,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_CHAR_ROM
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END CHAR_ROM_a;
|
mit
|
d56f2e398d8893b84b97be2e8707bc81
| 0.528046 | 3.976366 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/t80/t80_mcode.vhd
| 1 | 72,380 |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0235 : Added IM 2 fix by Mike Johnson
--
-- 0238 : Added NoRead signal
--
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
--
-- 0242 : Fixed I/O instruction timing, cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.t80_pack.all;
entity t80_mcode is
generic(
t80mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end t80_mcode;
architecture rtl of t80_mcode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if t80mode = 3 then
case cc is
when "000" => return F(7) = '0'; -- NZ
when "001" => return F(7) = '1'; -- Z
when "010" => return F(4) = '0'; -- NC
when "011" => return F(4) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if t80mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if t80mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if t80mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if t80mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if t80mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if t80mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif t80mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if t80mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif t80mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if t80mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and t80mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if t80mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if t80mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if t80mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if t80mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if t80mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if t80mode = 3 then
I_DJNZ <= '1';
elsif t80mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or t80mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and t80mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if t80mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
when "11010011" =>
if t80mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if t80mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if t80mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if t80mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RLD <= '1';
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RRD <= '1';
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI, RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
-- note B is decremented AFTER being put on the bus
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
--IncDec_16 <= "0010";
IncDec_16 <= "0110";
else
--IncDec_16 <= "1010";
IncDec_16 <= "1110";
end if;
TStates <= "100";
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
-- note B is decremented BEFORE being put on the bus.
-- mikej fix for hl inc
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110"; -- mikej
else
IncDec_16 <= "1110"; -- mikej
end if;
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if t80mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if t80mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if t80mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if t80mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if t80mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
|
gpl-2.0
|
1f45a65e1200dcaa90d413f272d4ed89
| 0.381031 | 4.542203 | false | false | false | false |
a4a881d4/ringbus
|
simio/iqdaemulator.vhd
| 1 | 1,015 |
-- This unit is a IQDAemulator
-- The outout will be writen to a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity IQDAemulator is
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iin : in std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' );
Qin : in std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' ));
end IQDAemulator;
architecture simulation of IQDAemulator is
begin
process(clk)
variable idata:integer:=0;
FILE data_file: TEXT IS OUT DA_FILE;
variable buf:line;
begin
if clk'event and clk='1' then
if ce='1' then
idata:=CONV_INTEGER(unsigned(Iin));
WRITE(buf,hex_to_str(idata),right,8);
idata:=CONV_INTEGER(unsigned(Qin));
WRITE(buf,hex_to_str(idata),right,8);
WRITELINE(data_file,buf);
end if;
end if;
end process;
end simulation;
|
lgpl-3.0
|
041f0f7704cd41a38af40b257e5290a6
| 0.651232 | 2.851124 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/component/Controller.vhd
| 1 | 36,841 |
-----------------------------------
-- PROCESSOR CONTROL UNIT --
-- PORT MAPPING --
-- IR: 32 bit instruction reg --
-- ST: 32 bit status reg --
-- CLK: 1 bit system clock --
-----------------------------------
-- MASK: 32 bit MDR data mask --
-- CLK: 38 bit clock signal --
-- FUN: 8 bit function signal --
-- SEL: 15 bit selection signal --
-----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE WORK.controller_constants.ALL;
ENTITY controller IS
PORT
(
-- Negated main clock
in_clk : IN STD_LOGIC;
-- Controller state machine input signals
in_ir : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_st : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Processor control signals
out_mask : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_en : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);
out_fun : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10));
out_sel : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16))
);
END controller;
ARCHITECTURE behavioral OF controller IS
-- State machine current stat, starts as fetch 0
signal s_state : t_state_type := fetch_0;
BEGIN
-- Observe the clock signal
PROCESS(in_clk)
BEGIN
-- Trigger a control cycle on every rising edge
IF(in_clk'EVENT AND in_clk = '1') THEN
-- Observe state machine
CASE s_state IS
-- FETCH CYCLE
-- MAR <--- PC
-- PC <--- PC + 1
-- MDR, IR <--- RAM[MAR]
-- MAR <--- PC
-- PC <--- PC + 1
WHEN fetch_0 =>
-- Disable all active components from last controller cycle
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
-- Set main data multplexer to value of program counter
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "011";
-- Set the pc multiplexer to output pc incrementer value
out_sel(c_select_mux_pc_incrementer) <= '1';
-- Save main data to mar
out_en(c_clock_mar) <= '1';
-- Save pc incrementer result to pc
out_en(c_clock_program_counter) <= '1';
-- Enable ram reading
out_fun(c_function_ram_we) <= '0';
-- Finish fetch 0
s_state <= fetch_1;
-- Ram read control signal
WHEN fetch_1 =>
-- Disable all active components from last controller cycle
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
-- Enable ram read signal
out_en(c_clock_ram) <= '1';
-- Finish fetch 1
s_state <= fetch_2;
WHEN fetch_2 =>
-- Disable all active components from last controller cycle
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
-- Save ram output to mdr
out_en(c_clock_mdr) <= '1';
-- Save ram output to ir
out_en(c_clock_instruction_register) <= '1';
-- Finish fetch cycle
s_state <= execute_0;
-- Execute last fetched instruction
WHEN execute_0 =>
-- Disable all active components from last controller cycle
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
-- Observe opcode as positive integer
CASE TO_INTEGER(UNSIGNED(in_ir(31 DOWNTO 24))) IS
-- Load imediate
WHEN c_opcode_loadImediate =>
-- Set data mask to clear top 16 bits
out_mask <= x"0000FFFF";
-- Set main multiplexer to data mask output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "100";
-- Load register with data
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Finish execution cycle
s_state <= fetch_0;
-- Load direct
WHEN c_opcode_loadDirect =>
-- Set data mask to clear top 16 bits
out_mask <= x"0000FFFF";
-- Set main multiplexer to data mask output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "100";
-- Load MAR with data
out_en(c_clock_mar) <= '1';
-- Set ram to read mode
out_fun(c_function_ram_we) <= '0';
-- Set state to execute 1
s_state <= execute_1;
-- Store direct
WHEN c_opcode_storeDirect =>
-- Store data from source register in register a in the next rising edge
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set alu to repeat value from register a
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set main multiplexer to data mask output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "100";
-- Load address from data mask to MAR
out_en(c_clock_mar) <= '1';
-- Set ram to write mode
out_fun(c_function_ram_we) <= '1';
-- Set state to execute 1
s_state <= execute_1;
-- Add
WHEN c_opcode_addDirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to add
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0001";
-- Set state to execute 1
s_state <= execute_1;
-- Move
WHEN c_opcode_moveDirect =>
-- Load register a from source
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_a) <= '1';
-- Set alu to pass
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Set state to execute 1
s_state <= execute_1;
-- Sub
WHEN c_opcode_subDirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to SUB
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0010";
-- Set state to execute 1
s_state <= execute_1;
-- And
WHEN c_opcode_andDirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to AND
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0101";
-- Set state to execute 1
s_state <= execute_1;
-- Or
WHEN c_opcode_orDirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to OR
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0110";
-- Set state to execute 1
s_state <= execute_1;
-- Xor
WHEN c_opcode_xorDirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to XOR
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0111";
-- Set state to execute 1
s_state <= execute_1;
-- Xnor
WHEN c_opcode_xnorDirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to XNOR
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "1000";
-- Set state to execute 1
s_state <= execute_1;
-- Jump
WHEN c_opcode_jumpIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set alu opcode to pass a
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set state to execute 1
s_state <= execute_1;
-- Jump equals
WHEN c_opcode_jumpEqualsIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to SUB
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0010";
-- Set state to execute 1
s_state <= execute_1;
-- Jump not equals
WHEN c_opcode_jumpNotEqualsIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to SUB
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0010";
-- Set state to execute 1
s_state <= execute_1;
-- Jump lesser then
WHEN c_opcode_jumpLesserThenIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to SUB
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0010";
-- Set state to execute 1
s_state <= execute_1;
-- Jump greater then or equals
WHEN c_opcode_jumpGreaterThenIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set alu opcode to SUB
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0010";
-- Set state to execute 1
s_state <= execute_1;
-- LSL
WHEN c_opcode_shiftLogicalLeft =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set shifter opcode to LSL
out_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter) <= "001";
-- Set state to execute 1
s_state <= execute_1;
-- LSR
WHEN c_opcode_shiftLogicalRight =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set shifter opcode to LSR
out_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter) <= "010";
-- Set state to execute 1
s_state <= execute_1;
-- ASL
WHEN c_opcode_shiftArithmeticLeft =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set shifter opcode to ASL
out_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter) <= "011";
-- Set state to execute 1
s_state <= execute_1;
-- ASR
WHEN c_opcode_shiftArithmeticRight =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set shifter opcode to ASR
out_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter) <= "100";
-- Set state to execute 1
s_state <= execute_1;
-- RL
WHEN c_opcode_shiftRotateLeft =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set shifter opcode to RL
out_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter) <= "101";
-- Set state to execute 1
s_state <= execute_1;
-- RR
WHEN c_opcode_shiftRotateRight =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set shifter opcode to RR
out_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter) <= "110";
-- Set state to execute 1
s_state <= execute_1;
-- LOAD INDIRECT
WHEN c_opcode_loadIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set state to execute 1
s_state <= execute_1;
-- STORE INDIRECT
WHEN c_opcode_storeIndirect =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Load register b from register bank
out_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b) <= in_ir(18 DOWNTO 14);
out_en(c_clock_register_b) <= '1';
-- Set state to execute 1
s_state <= execute_1;
WHEN c_opcode_jumpAndLink =>
-- Load register a from register bank
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(23 DOWNTO 19);
out_en(c_clock_register_a) <= '1';
-- Set alu opcode to pass a
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set the pc multiplexer to output data bus
out_sel(c_select_mux_pc_incrementer) <= '0';
-- Set main multiplexer output to pc
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "011";
s_state <= execute_1;
-- Invalid opcodes
WHEN OTHERS =>
-- Skip invalid instructions and go back to fetch cycle
s_state <= fetch_0;
END CASE;
WHEN execute_1 =>
-- Disable all active components from last controller cycle
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
-- Observe opcode
CASE TO_INTEGER(UNSIGNED(in_ir(31 DOWNTO 24))) IS
-- Load direct
WHEN c_opcode_loadDirect =>
-- Read ram on next clock rising edge
out_en(c_clock_ram) <= '1';
-- Set state to execute 2
s_state <= execute_2;
-- Store direct
WHEN c_opcode_storeDirect =>
-- Set main multiplexer output to alu
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Store value in ram on the next rising edge
out_en(c_clock_ram) <= '1';
s_state <= fetch_0;
-- Add
WHEN c_opcode_addDirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Move
WHEN c_opcode_moveDirect =>
-- Move value from source to destination
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Sub
WHEN c_opcode_subDirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Set status mux to ALU
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "0";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- And
WHEN c_opcode_andDirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to ALU
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "0";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Or
WHEN c_opcode_orDirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to ALU
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "0";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Xor
WHEN c_opcode_xorDirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to ALU
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "0";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Xnor
WHEN c_opcode_xnorDirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to ALU
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "0";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Jump
WHEN c_opcode_jumpIndirect =>
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- set pc incrementer mux to main mux output
out_sel(c_select_mux_pc_incrementer) <= '0';
-- Load PC
out_en(c_clock_program_counter) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- Jump equals
WHEN c_opcode_jumpEqualsIndirect =>
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Set status to execute 2
s_state <= execute_2;
-- Jump not equals
WHEN c_opcode_jumpNotEqualsIndirect =>
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Set status to execute 2
s_state <= execute_2;
-- Jump lesser then
WHEN c_opcode_jumpLesserThenIndirect =>
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Set status to execute 2
s_state <= execute_2;
-- Jump greater then or equals
WHEN c_opcode_jumpGreaterThenIndirect =>
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Set status to execute 2
s_state <= execute_2;
-- LSL
WHEN c_opcode_shiftLogicalLeft =>
-- Set main multiplexer to shifter output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "000";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to shifter
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "1";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- LSR
WHEN c_opcode_shiftLogicalRight =>
-- Set main multiplexer to shifter output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "000";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to shifter
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "1";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- ASL
WHEN c_opcode_shiftArithmeticLeft =>
-- Set main multiplexer to shifter output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "000";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to shifter
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "1";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- ASR
WHEN c_opcode_shiftArithmeticRight =>
-- Set main multiplexer to shifter output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "000";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to shifter
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "1";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- RL
WHEN c_opcode_shiftRotateLeft =>
-- Set main multiplexer to shifter output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "000";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to shifter
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "1";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
-- RR
WHEN c_opcode_shiftRotateRight =>
-- Set main multiplexer to shifter output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "000";
-- Load result to destination register
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
-- Set status mux to shifter
out_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter) <= "1";
-- Load status to Status Register
out_en(c_clock_status_register) <= '1';
-- Finish cycle
s_state <= fetch_0;
WHEN c_opcode_loadIndirect =>
-- Set alu opcode to PASS B
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "1001";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load MAR with data
out_en(c_clock_mar) <= '1';
-- Set ram to read mode
out_fun(c_function_ram_we) <= '0';
-- Finish cycle
s_state <= execute_2;
WHEN c_opcode_storeIndirect =>
-- Set alu opcode to PASS B
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "1001";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Load MAR with data
out_en(c_clock_mar) <= '1';
-- Set ram to write mode
out_fun(c_function_ram_we) <= '1';
-- Finish cycle
s_state <= execute_2;
WHEN c_opcode_jumpAndLink =>
-- Store PC into jump register
out_en(c_clock_registerbank + c_register_returnAddress) <= '1';
s_state <= execute_2;
-- VHDL forces code to catch all cases
-- Invalid cases should never get passed execute 0
WHEN OTHERS =>
s_state <= fetch_0;
END CASE;
WHEN execute_2 =>
-- Disable all active components from last controller cycle
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
-- Observe opcode
CASE TO_INTEGER(UNSIGNED(in_ir(31 DOWNTO 24))) IS
-- Load direct
WHEN c_opcode_loadDirect =>
out_en(c_clock_mdr) <= '1';
s_state <= execute_3;
-- Jump equals
WHEN c_opcode_jumpEqualsIndirect =>
-- If result was 0, do the jump
IF(in_st(0) = '1') THEN
-- Load jump address register to register a
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(13 DOWNTO 9);
out_en(c_clock_register_a) <= '1';
-- Set alu opcode to PASS
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Use next state to load jump address to pc
s_state <= execute_3;
ELSE
-- finish cycle
s_state <= fetch_0;
END IF;
-- Jump not equals
WHEN c_opcode_jumpNotEqualsIndirect =>
-- If result was not 0, do the jump
IF(in_st(0) = '0') THEN
-- Load jump address register to register a
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(13 DOWNTO 9);
out_en(c_clock_register_a) <= '1';
-- Set alu opcode to PASS
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Use next state to load jump address to pc
s_state <= execute_3;
ELSE
-- finish cycle
s_state <= fetch_0;
END IF;
-- Jump lesser then
WHEN c_opcode_jumpLesserThenIndirect =>
-- If the signal of the result is negative, do the jump
IF(in_st(2) = '1') THEN
-- Load jump address register to register a
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(13 DOWNTO 9);
out_en(c_clock_register_a) <= '1';
-- Set alu opcode to PASS
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Use next state to load jump address to pc
s_state <= execute_3;
ELSE
-- finish cycle
s_state <= fetch_0;
END IF;
-- Jump greater then or equals
WHEN c_opcode_jumpGreaterThenIndirect =>
-- If the signal of the result was not negative, do the jump
IF(in_st(2) = '0') THEN
-- Load jump address register to register a
out_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a) <= in_ir(13 DOWNTO 9);
out_en(c_clock_register_a) <= '1';
-- Set alu opcode to PASS
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Set main multiplexer to alu output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- Use next state to load jump address to pc
s_state <= execute_3;
ELSE
-- finish cycle
s_state <= fetch_0;
END IF;
WHEN c_opcode_loadIndirect =>
-- Read value from ram on the next rising edge
out_en(c_clock_ram) <= '1';
s_state <= execute_3;
WHEN c_opcode_storeIndirect =>
-- Set alu opcode to PASS A
out_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu) <= "0011";
-- Store value in ram on the next rising edge
out_en(c_clock_ram) <= '1';
s_state <= fetch_0;
WHEN c_opcode_jumpAndLink =>
-- Set main multiplexer output to alu
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "001";
-- store register A into pc
out_en(c_clock_program_counter) <= '1';
s_state <= fetch_0;
WHEN OTHERS =>
s_state <= fetch_0;
END CASE;
WHEN execute_3 =>
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
CASE TO_INTEGER(UNSIGNED(in_ir(31 DOWNTO 24))) IS
-- Load direct
WHEN c_opcode_loadDirect =>
-- Set main multiplexer to mdr output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "010";
-- Load destination register from MDR
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
s_state <= fetch_0;
-- Jump equals
WHEN c_opcode_jumpEqualsIndirect =>
-- set pc incrementer mux to main mux output
out_sel(c_select_mux_pc_incrementer) <= '0';
out_en(c_clock_program_counter) <= '1';
-- finish cycle
s_state <= fetch_0;
-- Jump not equals
WHEN c_opcode_jumpNotEqualsIndirect =>
-- set pc incrementer mux to main mux output
out_sel(c_select_mux_pc_incrementer) <= '0';
out_en(c_clock_program_counter) <= '1';
-- finish cycle
s_state <= fetch_0;
-- Jump lesser then
WHEN c_opcode_jumpLesserThenIndirect =>
-- set pc incrementer mux to main mux output
out_sel(c_select_mux_pc_incrementer) <= '0';
out_en(c_clock_program_counter) <= '1';
-- finish cycle
s_state <= fetch_0;
-- Jump greater then or equals
WHEN c_opcode_jumpGreaterThenIndirect =>
-- set pc incrementer mux to main mux output
out_sel(c_select_mux_pc_incrementer) <= '0';
out_en(c_clock_program_counter) <= '1';
-- finish cycle
s_state <= fetch_0;
WHEN c_opcode_loadIndirect =>
out_en(c_clock_mdr) <= '1';
s_state <= execute_4;
WHEN OTHERS =>
s_state <= fetch_0;
END CASE;
WHEN execute_4 =>
out_en <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, out_en'LENGTH));
CASE TO_INTEGER(UNSIGNED(in_ir(31 DOWNTO 24))) IS
WHEN c_opcode_loadIndirect =>
-- Set main multiplexer to mdr output
out_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main) <= "010";
-- Load destination register from MDR
out_en(c_clock_registerbank + TO_INTEGER(UNSIGNED(in_ir(23 DOWNTO 19)))) <= '1';
s_state <= fetch_0;
WHEN OTHERS =>
s_state <= fetch_0;
END CASE;
END CASE;
END IF;
END PROCESS;
END behavioral;
|
mit
|
00d9072fe6cf11cae6c400e5d2e0ab06
| 0.583752 | 3.38581 | false | false | false | false |
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp_m1_pkg.vhd
| 1 | 5,332 |
-------------------------------------------------------------------------------
--
-- Title : fp_m1_pkg
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-- Description : FP useful package
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
package fp_m1_pkg is
---- SIN / COS CALCULATING ----
constant xNFFT : integer:=11;
type std_logic_array_Kx16 is array (0 to 2**(xNFFT-1)-1) of std_logic_vector(15 downto 0);
type std_logic_array_Kx32 is array (0 to 2**(xNFFT-1)-1) of std_logic_vector(31 downto 0);
function find_sin(xx : integer) return std_logic_array_Kx16;
function find_cos(xx : integer) return std_logic_array_Kx16;
type int16_complex is record
re : std_logic_vector(15 downto 00);
im : std_logic_vector(15 downto 00);
end record;
type fp23_data is record
exp : std_logic_vector(5 downto 0);
sig : std_logic;
man : std_logic_vector(15 downto 0);
end record;
type fp23_complex is record
re : fp23_data;
im : fp23_data;
end record;
procedure find_fp(
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(22 downto 0)
);
procedure find_float(
data_i : in std_logic_vector(15 downto 0);
data_o : out fp23_data
);
end fp_m1_pkg;
package body fp_m1_pkg is
function find_sin(xx : integer) return std_logic_array_Kx16 is
variable pi_new : real:=0.0;
variable si_new : std_logic_array_Kx16;
begin
for ii in 0 to 2**(xx-1)-1 loop
pi_new := (real(ii) * MATH_PI)/(2.0**xx);
si_new(ii) := STD_LOGIC_VECTOR(CONV_SIGNED(INTEGER(32767.0*SIN(-pi_new)),16));
end loop;
return si_new;
end find_sin;
function find_cos(xx : integer) return std_logic_array_Kx16 is
variable pi_new : real:=0.0;
variable co_new : std_logic_array_Kx16;
begin
for ii in 0 to 2**(xx-1)-1 loop
pi_new := (real(ii) * MATH_PI)/(2.0**xx);
co_new(ii) := STD_LOGIC_VECTOR(CONV_SIGNED(INTEGER(32767.0*COS(pi_new)),16));
end loop;
return co_new;
end find_cos;
procedure find_float(
data_i : in std_logic_vector(15 downto 0);
data_o : out fp23_data
)
is
variable msb : std_logic_vector(05 downto 00):="000001";
variable man : std_logic_vector(15 downto 00):=(others=>'0');
begin
if (data_i(15) = '1') then
man := data_i xor x"FFFF";
else
man := data_i;
end if;
xl: for jj in 0 to 15 loop
if (man = x"0000") then
msb := "100000";
exit;
else
if (man(15) = '1') then
man := man(14 downto 00) & '0';
exit;
else
msb := msb + '1';
man := man(14 downto 00) & '0';
end if;
end if;
end loop;
msb := "100000" - msb;
data_o.sig := data_i(15);
data_o.man := man;
data_o.exp := msb;
end find_float;
procedure find_fp(
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(22 downto 0)
)
is
variable msb : std_logic_vector(05 downto 00):="000001";
variable man : std_logic_vector(15 downto 00):=(others=>'0');
begin
if (data_i(15) = '1') then
man := data_i xor x"FFFF";
else
man := data_i;
end if;
xl: for jj in 0 to 15 loop
if (man = x"0000") then
msb := "100000";
exit;
else
if (man(15) = '1') then
man := man(14 downto 00) & '0';
exit;
else
msb := msb + '1';
man := man(14 downto 00) & '0';
end if;
end if;
end loop;
msb := "100000" - msb;
data_o(16) := data_i(15);
data_o(15 downto 00) := man;
data_o(22 downto 17) := msb;
end find_fp;
end package body fp_m1_pkg;
|
mit
|
80fd6614f4dd7aebd442cd4a04c90448
| 0.560765 | 3.196643 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/controllers/io/BusController.vhd
| 1 | 1,538 |
----------------------------------------
-- Memory address bus controller --
-- PORT MAPPING --
-- mar : 32 bit mar input --
-- data : 32 bit data input --
-- io_in : 32 bit io input --
-- ram_in : 32 bit ram input --
-- clk : 1 bit clock --
----------------------------------------
-- addr : 32 bit address output --
-- data_out : 32 bit data output --
-- mdr : 32 bit mdr output --
-- ram_clk : 1 bit ram clock --
-- io_clk : 1 bit io clock --
----------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bus_controller IS
PORT
(
in_mar : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_io : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_ram : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_en : IN STD_LOGIC;
-------------------------------------------
out_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_mdr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_ram_en : OUT STD_LOGIC;
out_io_en : OUT STD_LOGIC
);
END bus_controller;
ARCHITECTURE behavioral OF bus_controller IS
BEGIN
out_addr <= in_mar;
out_data <= in_data;
PROCESS(in_mar, in_en, in_ram, in_io)
BEGIN
IF(in_mar(31) = '1') THEN
out_io_en <= in_en;
out_ram_en <= '0';
out_mdr <= in_io;
ELSE
out_io_en <= '0';
out_ram_en <= in_en;
out_mdr <= in_ram;
END IF;
END PROCESS;
END behavioral;
|
mit
|
a07fc978d59e5b8192b6964c788d1ea2
| 0.494798 | 3.119675 | false | false | false | false |
sdenel/An-N-bits-pipelined-addsub-using-VHDL
|
src/tb_addsub.vhd
| 1 | 1,563 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_addsub_rtl is end;
architecture bench of tb_addsub_rtl is
constant CLK_PER: time := 20 ns;
constant NBITS : natural := 8;
signal clk : std_logic := '0';
signal rst, sub : std_logic;
signal a, b, z0, z1, z2 : std_logic_vector(NBITS-1 downto 0);
begin
UUT0: entity work.addsub(rtl)
generic map(
NBITS=> NBITS,
NPIPELINE=> 0, -- 0, 1, 2...
ISRESET=> '0'
)
port map (clk, rst, sub, a, b, z0);
UUT1: entity work.addsub(rtl)
generic map(
NBITS=> NBITS,
NPIPELINE=> 1, -- 0, 1, 2...
ISRESET=> '0'
)
port map (clk, rst, sub, a, b, z1);
UUT2: entity work.addsub(rtl)
generic map(
NBITS=> NBITS,
NPIPELINE=> 2, -- 0, 1, 2...
ISRESET=> '0'
)
port map (clk, rst, sub, a, b, z2);
clk <= not clk after CLK_PER/2;
rst <= '0', '1' after CLK_PER/4, '0' after 3*CLK_PER/4;
process
begin
wait for 3*CLK_PER/4; -- z doit être 31-12=19
a <= std_logic_vector(to_unsigned(31, a'length));
b <= std_logic_vector(to_unsigned(12, a'length));
sub <= '1';
wait until rising_edge(clk);
wait for 3*CLK_PER/4; -- z doit être 35+10=45
a <= std_logic_vector(to_unsigned(35, a'length));
b <= std_logic_vector(to_unsigned(10, a'length));
sub <= '0';
wait until rising_edge(clk);
wait for 3*CLK_PER/4; -- z doit être 0+0=0
a <= std_logic_vector(to_unsigned(0, a'length));
b <= std_logic_vector(to_unsigned(0, a'length));
sub <= '0';
wait until rising_edge(clk);
wait;
end process;
end architecture bench;
|
mit
|
5e48343b282818396ab4fda4d08e5f4f
| 0.609615 | 2.508039 | false | false | false | false |
a4a881d4/ringbus
|
V3.0/pcie/EPTLPIn.vhd
| 1 | 3,907 |
---------------------------------------------------------------------------------------------------
--
-- Title : Bus End Point Recieve to TLP interface
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : EPTLPIn.vhd
-- Generated : 2013/9/15
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring Bus End Point Recieve to TLP interface
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.rb_config.all;
entity EPTLPIN is
generic(
Awidth : natural:= 64;
Bwidth : natural:= 128;
PCIwidth : natural:= 64;
BUFAWidth : natural := 4;
BUFSIZE : natural := 2**BUFAWidth
);
port(
-- system interface
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- bus interface
rx_sop : in std_logic;
rx: in std_logic_vector(Bwidth-1 downto 0);
-- TLP interface
clk_pci : in std_logic;
rst_pci : in std_logic;
trn_td : out std_logic_vector( PCIwidth-1 downto 0);
trn_tsrc_rdy_n : out std_logic;
trn_select_n : in std_logic;
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic
--
completer_id_i : in std_logic_vector(15 downto 0)
);
end EPTLPIN;
architecture behave of EPTLPIN is
type state is (
IDLE,
QW0DW1,
QWXDW0,
QWXDW1
);
type TLP is array of ( BUFSIZE*33-1 downto 0 ) of std_logic_vector( Bwidth-1 downto 0 );
--type TLPH is array of ( BUFSIZE-1 downto 0 ) of std_logic_vector( Bwidth-1 downto 0 );
signal wraddr_i, rdaddr_i : std_logic_vector( 4 downto 0 ) := (others => '0');
signal wrid_i, rdid_i : std_logic_vector( BUFAwidth-1 downto 0 ) := (others => '0');
signal tlpstate : state := IDLE;
signal TLP_i : TLP := (others =>(others => '0'));
signal lenc : std_logic_vector( len_length-1 downto 0 ) := (others => '0');
signal errcnt : std_logic_vector( 15 downto 0 ) := (others => '0');
signal hold : std_logic := '0';
begin
sopWRP:process(clk,rst)
begin
if rst='1' then
wraddr_i<=(others => '0');
wrid_i<=(others => '0');
lenc<=(others => '0');
errcnt<=(others => '0');
elsif rising_edge(clk) then
if rx_sop='1'
and rx( command_end downto command_start )=command_write
then
wraddr_i<=zeros(4 downto 0);
TLP_i(conv_integer("100000"&wrid_i))<='0' &
RX_MEM_WR64_FMT_TYPE &
'0' &
Device_TC &
"0000" &
Device_TD &
Device_EP &
Device_ATTR &
"00" &
rx( len_end downto len_start )&"0000" &
completer_id_i &
Device_WR_TAG &
"11111111" &
rx( addr_start+Awidth-1 downto addr_start )
;
lenc<=rx( len_end downto len_start )-1;
hold<='1';
elsif lenc/=zeros( len_length-1 downto 0 ) then
lenc<=lenc-1;
wraddr_i<=addr_i+1;
THP_i(conv_integer(wraddr_i&wrid_i))<=rx;
else
if wrid_i+1 /= rdid_i then
wrid_i<=wrid_i+1;
else
errcnt<=errcnt+1;
end if
end if;
end if;
end process;
sofRRP:process(clk_pci,rst_pci)
begin
if rst_pci='1' then
rdaddr_i<=(others => '0');
rdid_i<=(others => '0');
tlpstate<=IDLE;
elsif rising_edge(clk_pci) then
if trn_select_n='1' then
case tlpstate is
when IDLE =>
if trn_tsof_n='1' then
tlpstate<=QW0DW1;
rdaddr_i<=(others => '0');
end if;
when QW0DW1 =>
end if;
end if;
end process;
end behave;
|
lgpl-3.0
|
6ba86d048d841eb48b010a3df4635b7c
| 0.491682 | 3.258549 | false | false | false | false |
whiterocker/time-pilot-vhdl
|
src/rasterizer.vhd
| 1 | 21,869 |
-- Video rasterizer in VHDL for Konami Arcade Emulator
-- (C) Copyright 2011, 2017 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
--
-- Premise: a dual-port block RAM is accessed from a Z80 processor
-- which populates sections with video, color, and sprite data. Separately,
-- a ROM set loader has populated portions of the dual-port block RAM with
-- static tile and sprite bitmap data. The rasterizer's job is to scan the
-- data from the second access port, and marshall that data to a 256x256 CRT
-- signal via a triple 8-bit video DAC.
-- 256x256 CRT:
--
-- horizontal:
-- __ _ __ ___________________________________________________
-- |_|_|__| |_
-- A B C D
--
-- D = 256 pixels
-- A = 1 pixel back porch
-- B = 22 pixels sync
-- C = 1 pixel front porch
-- ----------
-- 280 pixels
--
-- vertical:
-- __ _ __ ___________________________________________________
-- |_|_|__| |_
-- E F G H
--
-- H = 256 lines
-- E = 8 lines back porch
-- F = 3 lines sync
-- G = 11 lines front porch
-- ---------
-- 278 lines
--
-- Video data is held ROMs and in two 2 kiB dual-port RAMs that are byte-addressable
-- in this implementation. The dual-port RAM is organized as follows:
--
-- sprite tiles ROM 16 KiB
-- static tiles ROM 8 KiB
-- sprite RAM 2 KiB
-- tile RAM 2 KiB
-- sprite palette ROM 256 B
-- tile palette ROM 256 B
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rasterizer is
port (
clk: in std_logic;
reset: in std_logic;
rgb_out_red: out std_logic_vector(7 downto 0);
rgb_out_grn: out std_logic_vector(7 downto 0);
rgb_out_blu: out std_logic_vector(7 downto 0);
rgb_out_pixel_clock: out std_logic;
rgb_out_x: out std_logic_vector(7 downto 0);
rgb_hsync: out std_logic;
rgb_hblank: out std_logic; -- active-high
rgb_vsync: out std_logic;
rgb_vblank: out std_logic; -- active-high
video_line: out std_logic_vector(7 downto 0);
sprom_addr: out std_logic_vector(13 downto 0);
sprom_data: in std_logic_vector(7 downto 0);
strom_addr: out std_logic_vector(12 downto 0);
strom_data: in std_logic_vector(7 downto 0);
spram_addr: out std_logic_vector(9 downto 0);
spraml_data: in std_logic_vector(7 downto 0);
spramh_data: in std_logic_vector(7 downto 0);
tiram_addr: out std_logic_vector(9 downto 0);
tcram_data: in std_logic_vector(7 downto 0);
tvram_data: in std_logic_vector(7 downto 0);
pprom_addr: out std_logic_vector(7 downto 0);
pprom_data: in std_logic_vector(3 downto 0);
tprom_addr: out std_logic_vector(7 downto 0);
tprom_data: in std_logic_vector(3 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of clk : signal is "CLK";
attribute SIGIS of reset : signal is "RST";
attribute SIGIS of rgb_out_pixel_clock : signal is "CLK";
end entity rasterizer;
-- Maintain sline which is the scan line of the output signal.
architecture behaviour of rasterizer is
component pixel_ram
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(8 downto 0);
dpra : in std_logic_vector(8 downto 0);
di : in std_logic_vector(4 downto 0);
dpo : out std_logic_vector(4 downto 0)
);
end component;
for pixel_buf : pixel_ram use entity work.pixel_ram;
signal pixel_clk : std_logic;
signal div8 : unsigned(3 downto 0);
signal sline : unsigned(8 downto 0) := (others => '0'); -- scan vertical (278 lines)
signal vpos : unsigned(7 downto 0); -- frame vertical (256x256)
signal vpos2 : unsigned(7 downto 0); -- frame vertical (256x256)
signal vblank : std_logic;
signal spixel : unsigned(8 downto 0) := (others => '0'); -- scan pixel count (280 per line)
signal hpos : unsigned(7 downto 0); -- frame horizontal (256x256)
signal hblank : std_logic;
signal phblank : std_logic;
signal colour : std_logic_vector(4 downto 0);
constant zero8 : unsigned := "00000000";
constant zero10 : unsigned := "0000000000";
constant zero5 : std_logic_vector := "00000";
signal pixel_we : std_logic;
signal pixel_waddr : std_logic_vector(8 downto 0);
signal pixel_raddr : std_logic_vector(8 downto 0);
signal pixel_wdata : std_logic_vector(4 downto 0);
signal pixel_rdata : std_logic_vector(4 downto 0);
subtype state_type is unsigned(3 downto 0);
constant INIT : state_type := "0000";
constant GET_TILE_BYTES : state_type := "0001";
constant GET_TILE_PIXEL : state_type := "0010";
constant ADVANCE_TILE_PIXEL : state_type := "0011";
constant GET_SPRITE_B31_SEL_B20 : state_type := "1000";
constant GET_SPRITE_B20 : state_type := "1001";
constant CHECK_SPRITE_ROW : state_type := "1010";
constant GET_SPRITE_PIXEL : state_type := "1011";
constant ADVANCE_SPRITE_PIXEL : state_type := "1100";
-- main rasterizer FSM state
signal state : state_type;
-- desired and current tile plane
signal dplane, tplane : std_logic;
-- tile flip x/y
signal tflipx, tflipy : std_logic;
-- sprite flip x/y
signal sflipx, sflipy : std_logic;
-- tile/sprite bytes as described above
signal tb0, tb1 : std_logic_vector(7 downto 0);
signal sb0, sb1, sb2, sb3 : std_logic_vector(7 downto 0);
-- element index into the tile or sprite ROM
signal index : unsigned(4 downto 0);
-- horizontal pixel position within tile on screen (always left-to-right)
signal thpos : unsigned(2 downto 0);
-- horizontal half-tile offset, reflects whether tile is vertically flipped
signal thoff : std_logic;
-- vertical pixel position within tile ROM: forward or reverse of thpos
signal tvoff : std_logic_vector(2 downto 0);
-- pixel's location in tile ROM byte is 0x88 shifted right by this amount
signal tpshift : std_logic_vector(1 downto 0);
-- palette index for current sprite pixel
signal spalix : std_logic_vector(1 downto 0);
-- active sprite row calculated from sprite's Y coordinate and vertical
-- orientation (normal and flipped row cached to meet timing)
signal sprow, nrow, frow : unsigned(7 downto 0);
-- active sprite pixel X
signal sprpx : unsigned(7 downto 0);
-- horizontal pixel position within sprite on screen (always left-to-right)
signal shpos : unsigned(3 downto 0);
-- horizontal pixel position within sprite ROM: forward or reverse of shpos
signal shoff : unsigned(3 downto 0);
-- sprite low/high byte select
signal splohi : std_logic;
begin -- behaviour
rgb_out_pixel_clock <= pixel_clk;
-- free-running pixel position counters and pixel clock
-- input clock is 36.864 MHz, pixel clock is 4.608 MHz (div 8)
-- sline is 0..277 and spixel is 0..279
count: process(clk, reset)
begin
if reset = '1' then
div8 <= "0000";
spixel <= (others => '0');
sline <= (others => '0');
pixel_clk <= '0';
elsif clk'event and clk = '0' then
case div8 is
when X"1" => div8 <= X"2";
if (spixel = 279) then
spixel <= (others => '0');
if (sline = 277) then
sline <= (others => '0');
else
sline <= sline + 1;
end if;
else
spixel <= spixel + 1;
end if;
when X"3" => div8 <= X"4"; pixel_clk <= '1';
when X"7" => div8 <= X"0"; pixel_clk <= '0';
when others => div8 <= div8 + 1;
end case;
end if;
end process count;
hpos <= spixel(7 downto 0) when (spixel <= 255) else X"00";
vpos <= sline(7 downto 0) when (sline <= 255) else X"00";
vpos2 <= vpos - 1;
-- horizontal and vertical sync and blank pulses
rgb_hsync <= '0' when ((spixel >= 257) and (spixel < 279)) else '1';
rgb_vsync <= '0' when ((sline >= 264) and (sline < 267)) else '1';
hblank <= '1' when (spixel > 255) else '0';
vblank <= '1' when (sline > 255) else '0';
rgb_vblank <= vblank;
rgb_hblank <= hblank;
-- raster position
rgb_out_x <= std_logic_vector(hpos);
video_line <= std_logic_vector(vpos2);
-----------------------------------------------------------------------------
-- screen renders flipped on its side:
--
-- (origin) 16 lines of black
-- +-------------------------+0
-- | |0
-- P | |
-- U | |T
-- - | |I
-- 2 | |D
-- | |E
-- | |R
-- | |C
-- | |
-- E | |
-- R0 | |
-- O0 | |
-- C0 | |
-- S0 | |
-- -1 | |
-- I | |
-- H | |
-- | |
-- | |
-- | |
-- 0 | |
-- P0 | |
-- U | |
-- - | |
-- 1 | |
-- | |
-- +-------------------------+
-- 16 lines of black
-----------------------------------------------------------------------------
-- tile RAM: 16 bits per playfield tile position, 32x32=1024 tiles
-- color RAM:
-- 0x000: b0 .. .. .. .. .. .. ..
--
-- 0x3f0: .. .. .. .. .. .. .. b0
-- video RAM:
-- 0x400: b1 .. .. .. .. .. .. ..
--
-- 0x7ff: .. .. .. .. .. .. .. b1
--
-- For each tile: romoff=(((b0 & 0x20) << 3) | b1), pal_base=(b0 & 0x1f),
-- flipx=(b0 & 0x40), flipy=(b0 & 0x80)
--
-- Each static tile is 8x8 pixels, each pixel is 2 bits, so each tile is 16
-- bytes long. The 16-byte tile is organized as follows (no flipping). If
-- b0_7 is the most-significant bit of byte 0, and bf_0 is the least-significant
-- bit of byte f, then 2-bit pixels are derived as:
--
-- (0,0) is [b0_7,b0_3] .. (3,0) is [b0_4,b0_0] (4,0) is [b8_7,b8_3] .. (7,0) is [b8_4,b8_0]
-- ..
-- (0,7) is [b7_7,bf_3] .. (3,0) is [b7_4,b7_0] (4,0) is [bf_7,bf_3] .. (7,0) is [bf_4,bf_0]
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- sprite RAM: 32 bits per sprite, 24 sprites
--
-- Unlike tile RAM which is organized in a playfield matrix, the sprite data
-- block describes the x,y location of each sprite as well as other
-- operational parameters such as the applicable sprite tile in a 32-bit
-- structure.
--
-- 0x010: b0 b1 .. .. .. .. .. ..
-- 0x020: .. .. .. .. .. .. .. ..
-- 0x030: .. .. .. .. .. .. b0 b1
--
-- 0x410: b2 b3 .. .. .. .. .. ..
-- 0x420: .. .. .. .. .. .. .. ..
-- 0x430: .. .. .. .. .. .. b2 b3
--
-- For each sprite: y=(241-b3), x=b0, spr_tile=b1, pal_base=(b2 & 0x3f),
-- flipy=(b2 & 0x80), flipx=~(b2 & 0x40)
--
-- Each sprite tile is 16x16 pixels, each pixel is 2 bits, so each tile is 64
-- contiguous bytes long. The 64-byte tile is organized as follows (no
-- flipping). If b00_7 is the most-significant bit of byte 00, and b3f_0 is
-- the least-significant bit of byte 3f, then 2-bit pixels are derived as:
--
-- (0,0)[b00_3,b00_7] .. (3,0)[b00_0,b00_4] .. (7,0)[b08_0,b08_4] .. (b,0)[b10_0,b10_4] .. (f,0)[b18_0,b18_4]
-- ..
-- (0,7)[b07_3,b07_7] .. (3,7)[b07_0,b07_4] .. (7,7)[b0f_0,b0f_4] .. (b,7)[b17_0,b17_4] .. (f,7)[b1f_0,b1f_4]
-- (0,8)[b20_3,b20_7] .. (3,8)[b20_0,b20_4] .. (7,8)[b28_0,b28_4] .. (b,7)[b30_0,b30_4] .. (f,8)[b38_0,b38_4]
-- ..
-- (0,f)[b27_3,b27_7] .. (3,f)[b27_0,b27_4] .. (7,f)[b2f_0,b2f_4] .. (b,f)[b37_0,b37_4] .. (f,f)[b3f_0,b3f_4]
--
-----------------------------------------------------------------------------
-- tile flips and plane
tflipy <= not tb0(7);
tflipx <= not tb0(6);
tplane <= tb0(4);
-- 3-bit vertical pixel position within tile
tvoff <= not std_logic_vector(vpos(2 downto 0)) when (tflipy = '0') else
std_logic_vector(vpos(2 downto 0));
-- 1-bit horizontal half-tile position
thoff <= not std_logic(thpos(2)) when (tflipx = '0') else
std_logic(thpos(2));
-- sprite normal and flipped row calculations (within sprite)
nrow <= (vpos + unsigned(sb3) - 241); -- normal orientation: vpos - (241 - sy)
frow <= (unsigned(not sb3) - vpos); -- flipped orientation: (241 - sy) + 15 - vpos
-- sprite flips
sflipy <= sb2(7);
sflipx <= not sb2(6);
-- 4-bit horizontal pixel position within sprite
shoff <= shpos when (sflipx = '0') else not shpos;
-- sprite bitmap ROM address
sprom_addr <= sb1 & std_logic(sprow(3)) &
std_logic_vector(shoff(3 downto 2)) &
std_logic_vector(sprow(2 downto 0));
-- sprite pixel x position
sprpx <= unsigned(sb0) + shpos;
-- tile bitmap ROM address
strom_addr <= tb0(5) & tb1(7 downto 0) & thoff & tvoff;
-- tile color and video RAM address
tiram_addr <= std_logic_vector(vpos(7 downto 3)) & std_logic_vector(index);
-- tile bitmap bit selects
tpshift <= std_logic_vector(thpos(1 downto 0)) when (tflipx = '0') else
not std_logic_vector(thpos(1 downto 0));
-- tile color palette ROM address
tprom_addr <= '0' & tb0(4 downto 0) & strom_data(4) & strom_data(0) when (tpshift = "00") else
'0' & tb0(4 downto 0) & strom_data(5) & strom_data(1) when (tpshift = "01") else
'0' & tb0(4 downto 0) & strom_data(6) & strom_data(2) when (tpshift = "10") else
'0' & tb0(4 downto 0) & strom_data(7) & strom_data(3);
-- sprite color palette ROM address
spalix <= sprom_data(3) & sprom_data(7) when shoff(1 downto 0) = 0 else
sprom_data(2) & sprom_data(6) when shoff(1 downto 0) = 1 else
sprom_data(1) & sprom_data(5) when shoff(1 downto 0) = 2 else
sprom_data(0) & sprom_data(4);
pprom_addr <= sb2(5 downto 0) & spalix;
-- sprite RAM address
spram_addr <= "0000" & std_logic_vector(index) & splohi;
-- Finite state machine to paint a single horizontal line, by:
-- 0. wait for horizontal scan to start
-- 1. emit all static tile rows on plane 0
-- 2. overwrite all non-zero row pixels for all sprites intersecting the line
-- 3. overwrite all static tile rows on plane 1
fsm: process (clk, reset)
begin -- process fsm
if reset = '1' then
state <= INIT;
tb0 <= X"00"; tb1 <= X"00";
sb0 <= X"00"; sb1 <= X"00"; sb2 <= X"00"; sb3 <= X"00";
sprow <= X"00";
shpos <= "0000";
index <= "00000";
thpos <= "000";
dplane <= '0';
splohi <= '0';
pixel_waddr <= "000000000";
pixel_wdata <= "00000";
pixel_we <= '0';
elsif clk'event and clk = '0' then -- falling clock edge
phblank <= hblank;
case state is
when INIT =>
if ((phblank = '1') and (hblank = '0')) then
state <= GET_TILE_BYTES;
index <= "00000";
thpos <= "000";
end if;
when GET_TILE_BYTES =>
tb0 <= tcram_data;
tb1 <= tvram_data;
state <= GET_TILE_PIXEL;
when GET_TILE_PIXEL =>
if (tplane = dplane) then -- only write pixel data on active plane
pixel_waddr <= std_logic(vpos(0)) & std_logic_vector(index) &
std_logic_vector(thpos);
pixel_wdata <= '1' & tprom_data(3 downto 0);
pixel_we <= '1';
else
thpos <= "111"; -- advance to end of tile index
end if;
state <= ADVANCE_TILE_PIXEL;
when ADVANCE_TILE_PIXEL =>
if ((thpos = 7) and (index = 31)) then
if dplane = '0' then
-- keep index at 31, sprite indices decrement from there
state <= GET_SPRITE_B31_SEL_B20;
splohi <= '1';
else
dplane <= '0';
state <= INIT;
end if;
elsif (thpos = 7) then
index <= index + 1;
state <= GET_TILE_BYTES;
else
state <= GET_TILE_PIXEL;
end if;
thpos <= thpos + 1;
pixel_we <= '0';
when GET_SPRITE_B31_SEL_B20 =>
sb1 <= spraml_data; sb3 <= spramh_data;
splohi <= '0';
state <= GET_SPRITE_B20;
when GET_SPRITE_B20 =>
sb0 <= spraml_data; sb2 <= spramh_data;
shpos <= "0000";
state <= CHECK_SPRITE_ROW;
when CHECK_SPRITE_ROW =>
-- process this sprite if this scan line intersects, skip otherwise
if ((nrow < 16) and (sflipy = '0')) then
state <= GET_SPRITE_PIXEL;
sprow <= nrow;
elsif ((frow < 16) and (sflipy = '1')) then
state <= GET_SPRITE_PIXEL;
sprow <= frow;
else
shpos <= "1111";
state <= ADVANCE_SPRITE_PIXEL;
end if;
when GET_SPRITE_PIXEL =>
-- only write pixel data on active sprite, colour zero is transparent
if ((sprow < 16) and not (spalix = "00")) then
pixel_waddr <= std_logic(vpos(0)) & std_logic_vector(sprpx);
pixel_wdata <= '0' & pprom_data(3 downto 0);
pixel_we <= '1';
end if;
state <= ADVANCE_SPRITE_PIXEL;
when ADVANCE_SPRITE_PIXEL =>
if ((shpos = 15) and (index = 8)) then
dplane <= '1';
state <= GET_TILE_BYTES;
index <= "00000";
elsif (shpos = 15) then
index <= index - 1;
splohi <= '1';
state <= GET_SPRITE_B31_SEL_B20;
else
state <= GET_SPRITE_PIXEL;
end if;
shpos <= shpos + 1;
pixel_we <= '0';
when others => null;
end case;
end if;
end process fsm;
-----------------------------------------------------------------------------
-- double-buffering pixel RAM holds a single scan line for output while
-- composing the next one
pixel_buf : pixel_ram
port map (
clk => clk,
we => pixel_we,
a => pixel_waddr,
dpra => pixel_raddr,
di => pixel_wdata,
dpo => pixel_rdata
);
-----------------------------------------------------------------------------
-- output the assembled scan line from double-buffering pixel RAM
scanout : process(clk, reset)
begin
if reset = '1' then
pixel_raddr <= "000000000";
colour <= "11111";
elsif clk'event and clk = '0' then
pixel_raddr <= std_logic(vpos2(0)) & std_logic_vector(hpos);
if ((vblank = '1') or (hblank = '1')) then
colour <= "00000";
else
colour <= pixel_rdata;
end if;
end if;
end process scanout;
-----------------------------------------------------------------------------
-- mapping 5-bit colours to 24-bit RGB
rgb: process(clk, reset)
type tColourROM is array(0 to 31) of std_logic_vector(7 downto 0);
constant redROM : tColourROM :=
( X"00",X"e5",X"e5",X"00",X"e5",X"00",X"95",X"ab",
X"95",X"00",X"59",X"00",X"74",X"ad",X"70",X"ce",
X"00",X"e5",X"00",X"00",X"e5",X"00",X"e5",X"00",
X"e5",X"b5",X"00",X"00",X"00",X"00",X"50",X"ce" );
constant grnROM : tColourROM :=
( X"00",X"00",X"74",X"9e",X"e5",X"44",X"95",X"ab",
X"95",X"ab",X"74",X"00",X"74",X"00",X"00",X"ce",
X"00",X"00",X"00",X"e5",X"e5",X"ab",X"00",X"59",
X"74",X"b5",X"00",X"50",X"59",X"74",X"00",X"ce" );
constant bluROM : tColourROM :=
( X"00",X"00",X"00",X"00",X"00",X"e5",X"00",X"ab",
X"95",X"e5",X"00",X"95",X"74",X"ad",X"00",X"ce",
X"00",X"00",X"e5",X"00",X"00",X"e5",X"e5",X"e5",
X"00",X"b5",X"59",X"59",X"50",X"e5",X"50",X"ce" );
begin -- process rgb
if reset = '1' then
rgb_out_red <= X"00";
rgb_out_grn <= X"00";
rgb_out_blu <= X"00";
elsif clk'event and clk = '0' then
rgb_out_red <= redROM( to_integer(unsigned(colour)) );
rgb_out_grn <= grnROM( to_integer(unsigned(colour)) );
rgb_out_blu <= bluROM( to_integer(unsigned(colour)) );
end if;
end process rgb;
end behaviour;
|
gpl-2.0
|
f294cb1bc39e75bd79e846a22b314082
| 0.510037 | 3.38163 | false | false | false | false |
KimSJ/HDLC_chip
|
crc16.vhd
| 1 | 1,020 |
-------------------------------------------------------------------------
-- 16-bit Serial CRC-CCITT Generator.
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc16 is
port (clk, reset, ce, din: in std_logic;
crc_sum: out std_logic_vector(15 downto 0));
end crc16;
architecture behavior of crc16 is
signal X: std_logic_vector(15 downto 0);
begin
reg:process(reset, clk, ce)
begin
if reset = '1' then
X <= (others => '1');
elsif ce = '1' then
if falling_edge(clk) then
X(0) <= Din xor X(15);
X(1) <= X(0);
X(2) <= X(1);
X(3) <= X(2);
X(4) <= X(3);
X(5) <= X(4) xor (din xor X(15));
X(6) <= X(5);
X(7) <= X(6);
X(8) <= X(7);
X(9) <= X(8);
X(10) <= X(9);
X(11) <= X(10);
X(12) <= X(11) xor (din xor X(15));
X(13) <= X(12);
X(14) <= X(13);
X(15) <= X(14);
end if;
end if;
end process;
crc_sum <= X;
end behavior;
|
gpl-3.0
|
51d53c7dcf92e0013d87db104bc705ba
| 0.417647 | 2.615385 | false | false | false | false |
arcade-lab/uarch-phases
|
src/lib/tracing/packer.vhd
| 1 | 4,866 |
------------------------------------------------------------------------------
-- This file is part of a signal tracing utility for the LEON3 processor
-- Copyright (C) 2017, ARCADE Lab @ Columbia University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-----------------------------------------------------------------------------
-- Entity: packer
-- File: packer.vhd
-- Author: Van Bui - ARCADE @ Columbia University
-- Description: packs data
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sld;
use sld.tracing.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity packer is
port (
rst : in std_ulogic;
clk : in std_ulogic;
ipreg : in ipreg_out_type;
mem_selected : in std_logic_vector(AHB_BITS-1 downto 0);
activity : in std_logic_vector(ACTIVITY_BITS-1 downto 0);
packsigs : out std_logic_vector(MEM_BITS-1 downto 0) := (others => '0'));
end packer;
architecture beh of packer is
signal flastpc : std_logic_vector(MEM_BITS-1 downto 0) := (others => '0');
signal fnextpc : std_logic_vector(MEM_BITS-1 downto 0) := (others => '0');
signal elastpc : std_logic_vector(MEM_BITS-1 downto 0) := (others => '0');
signal enextpc : std_logic_vector(MEM_BITS-1 downto 0) := (others => '0');
begin --beh
pack_sigs : process (clk, rst)
begin
if rst = '0' then
flastpc <= (others => '0');
elastpc <= (others => '0');
elsif clk'event and clk = '1' then
flastpc <= fnextpc;
elastpc <= enextpc;
end if;
end process;
next_pc : process(ipreg)
begin
fnextpc <= ipreg.f.pc;
enextpc <= ipreg.e.pc;
end process;
packit : process(ipreg, flastpc, fnextpc, elastpc, enextpc)
begin
packsigs(0) <= ipreg.icohold or ipreg.holdn;
packsigs(1) <= ipreg.dcohold or ipreg.holdn;
packsigs(2) <= ipreg.fpohold or ipreg.holdn;
if (ipreg.dcache.pagefault='1') then -- page fault from data access
packsigs(3) <= '1';
else
packsigs(3) <= '0';
end if;
if (ipreg.icache.fault='1') then -- page fault from instruction access
packsigs(4) <= '1';
else
packsigs(4) <= '0';
end if;
if ((ipreg.d.annul='1')) then
packsigs(5) <= '1';
else
packsigs(5) <= '0';
end if;
if ((ipreg.d.pv='0')) then
packsigs(6) <= '1';
else
packsigs(6) <= '0';
end if;
if ((ipreg.a.annul='1')) then
packsigs(7) <= '1';
else
packsigs(7) <= '0';
end if;
if ((ipreg.a.pv='0')) then
packsigs(8) <= '1';
else
packsigs(8) <= '0';
end if;
if ((ipreg.e.annul='1')) then
packsigs(9) <= '1';
else
packsigs(9) <= '0';
end if;
if ((ipreg.e.pv='0')) then
packsigs(10) <= '1';
else
packsigs(10) <= '0';
end if;
if ((ipreg.m.annul='1')) then
packsigs(11) <= '1';
else
packsigs(11) <= '0';
end if;
if ((ipreg.m.pv='0')) then
packsigs(12) <= '1';
else
packsigs(12) <= '0';
end if;
if ((ipreg.x.annul='1')) then
packsigs(13) <= '1';
else
packsigs(13) <= '0';
end if;
if ((ipreg.x.pv='0')) then
packsigs(14) <= '1';
else
packsigs(14) <= '0';
end if;
packsigs(15) <= ipreg.a.rfe1;
packsigs(16) <= ipreg.a.rfe2;
packsigs(18 downto 17) <= ipreg.e.inst(31 downto 30);
packsigs(20 downto 19) <= ipreg.m.inst(31 downto 30);
packsigs(22 downto 21) <= ipreg.x.inst(31 downto 30);
packsigs(23) <= ipreg.m.ld;
packsigs(24) <= ipreg.x.ld;
packsigs(25) <= ipreg.w.wreg;
if ipreg.x.rstate=run then
packsigs(27 downto 26) <= "00";
elsif ipreg.x.rstate=trap then
packsigs(27 downto 26) <= "01";
elsif ipreg.x.rstate=dsu1 then
packsigs(27 downto 26) <= "10";
else
packsigs(27 downto 26) <= "11";
end if;
packsigs(29 downto 28) <= mem_selected(1 downto 0);
packsigs(31 downto 30) <= ipreg.e.cnt;
end process;
end beh;
|
gpl-3.0
|
0aa56a9a4c0d49b4e155b128f25f80b4
| 0.542951 | 3.513357 | false | false | false | false |
hlamer/ktexteditor
|
autotests/input/syntax/vhdl/light52_tb.vhdl
| 3 | 6,697 |
--------------------------------------------------------------------------------
-- light52_tb.vhdl --
--------------------------------------------------------------------------------
-- This test bench simulates the execution of some program (whose object code
-- is in package obj_code_pkg, in the form of a memory init constant) and logs
-- the execution to a text file called 'hw_sim_log.txt' (light52_tb_pkg.vhdl).
--
-- This test bench does no actual tests on the core. Instead, the simulation log
-- is meant to be matched against the simulation log produced by running the
-- same program on the software simulator B51 (also included with this project).
--
-- This will catch errors in the implementation of the CPU if the simulated
-- program has anough coverage -- the opcode tester is meant to cover all CPU
-- opcodes in many (not all) of their corner cases.
-- This scheme will not help in catching errors in the peripheral modules,
-- mainly because the current version of B51 does not simulate them.
--
--------------------------------------------------------------------------------
-- Copyright (C) 2012 Jose A. Ruiz
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.light52_pkg.all;
use work.obj_code_pkg.all;
use work.light52_tb_pkg.all;
use work.txt_util.all;
entity light52_tb is
generic (BCD : boolean := true);
end;
architecture testbench of light52_tb is
--------------------------------------------------------------------------------
-- Simulation parameters
-- FIXME these should be in parameter package
-- Simulated clock period is the same as the usual target, the DE-1 board
constant T : time := 20 ns; -- 50MHz
constant SIMULATION_LENGTH : integer := 400000;
--------------------------------------------------------------------------------
-- MPU interface
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal p0_out : std_logic_vector(7 downto 0);
signal p1_out : std_logic_vector(7 downto 0);
signal p2_in : std_logic_vector(7 downto 0);
signal p3_in : std_logic_vector(7 downto 0);
signal external_irq : std_logic_vector(7 downto 0);
signal txd, rxd : std_logic;
--------------------------------------------------------------------------------
-- Logging signals & simulation control
-- Asserted high to disable the clock and terminate the simulation.
signal done : std_logic := '0';
-- Log file
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
-- Info record needed by the logging fuctions
signal log_info : t_log_info;
begin
---- UUT instantiation ---------------------------------------------------------
uut: entity work.light52_mcu
generic map (
IMPLEMENT_BCD_INSTRUCTIONS => BCD,
CODE_ROM_SIZE => work.obj_code_pkg.XCODE_SIZE,
XDATA_RAM_SIZE => work.obj_code_pkg.XDATA_SIZE,
OBJ_CODE => work.obj_code_pkg.object_code
)
port map (
clk => clk,
reset => reset,
txd => txd,
rxd => rxd,
external_irq => external_irq,
p0_out => p0_out,
p1_out => p1_out,
p2_in => p2_in,
p3_in => p3_in
);
-- UART is looped back in the test bench.
rxd <= txd;
-- I/O ports are looped back and otherwise unused.
p2_in <= p0_out;
p3_in <= p1_out;
-- External IRQ inputs are tied to port P1 for test purposes
external_irq <= p1_out;
---- Master clock: free running clock used as main module clock ------------
run_master_clock: process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process run_master_clock;
---- Main simulation process: reset MCU and wait for fixed period ----------
drive_uut: process
begin
-- Leave reset asserted for a few clock cycles...
reset <= '1';
wait for T*4;
reset <= '0';
-- ...and wait for the test to hit a termination condition (evaluated by
-- function log_cpu_activity) or to just timeout.
wait for T*SIMULATION_LENGTH;
-- If we arrive here, the simulation timed out (termination conditions
-- trigger a failed assertion).
-- So print a timeout message and quit.
print("TB timed out.");
done <= '1';
wait;
end process drive_uut;
-- Logging process: launch logger functions --------------------------------
log_execution: process
begin
-- Log cpu activity until done='1'.
log_cpu_activity(clk, reset, done, "/uut",
log_info, work.obj_code_pkg.XCODE_SIZE, "log_info",
X"0000", log_file, con_file);
-- Flush console log file when finished.
log_flush_console(log_info, con_file);
wait;
end process log_execution;
end architecture testbench;
|
gpl-2.0
|
494783ce971f16615079c7cfbd3318ab
| 0.531731 | 4.534191 | false | false | false | false |
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/Processor.vhd
| 1 | 18,377 |
-----------------------------------
-- PROCESSOR --
-- Test bench for now --
-----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE WORK.controller_constants.ALL;
ENTITY processor IS
PORT
(
-- Main processor clock
system_clock : IN STD_LOGIC;
-- Debug outputs
--ir : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--mar : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--mdr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--pc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--r4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--signal_alu : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ra : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--rb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--status : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
switches : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
hex : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END processor;
ARCHITECTURE behavioral OF processor IS
-- Control signals from the controller
SIGNAL s_controller_mask : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_controller_en : STD_LOGIC_VECTOR(40 DOWNTO 0);
SIGNAL s_controller_fun : STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL s_controller_sel : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- Program counter input/output signals
SIGNAL s_pc_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_pc_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Program counter incrementer unity data output
SIGNAL s_pc_incrementer_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Memory addres register data output
SIGNAL s_mar_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Ram data output
SIGNAL s_ram_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Instruction register data output
SIGNAL s_ir_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_ram_enable : STD_LOGIC;
SIGNAL s_io_enable : STD_LOGIC;
-- Main bus data
SIGNAL s_bus_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Main bus address
SIGNAL s_bus_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- IO data output
SIGNAL s_io_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Hex display output
SIGNAL s_hex_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Memory destination register data input
SIGNAL s_mdr_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Memory destination register data output
SIGNAL s_mdr_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Value masked by the controler data mask
SIGNAL s_mask_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Main data multiplexer
SIGNAL s_main_mux_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Register bank output for register a
SIGNAL s_register_bank_output_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Register bank output for register b
SIGNAL s_register_bank_output_b : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Alu register a output
SIGNAL s_register_a_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Alu register b output
SIGNAL s_register_b_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Bit shifter data output
SIGNAL s_shifter_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Bit shifter status flag output
SIGNAL s_shifter_status_output : STD_LOGIC_VECTOR(31 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
-- Alu register data output
SIGNAL s_alu_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Alu status flag output
SIGNAL s_alu_status_output : STD_LOGIC_VECTOR(31 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
-- Status multiplexer data output (selects status from alu or bit shifter)
SIGNAL s_mux_status_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Status register output
SIGNAL s_status_register_output : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Register bank register signals
SIGNAL s_reg_00 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_01 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_02 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_03 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_04 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_05 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_06 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_07 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_08 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_09 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_10 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_11 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_12 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_13 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_14 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_15 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_16 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_17 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_18 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_19 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_20 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_21 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_22 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_23 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_24 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_25 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_26 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_27 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_28 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_29 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_30 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg_31 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
-- Debug output hooks
--ir(31 DOWNTO 0) <= s_ir_output(31 DOWNTO 0);
--mar(31 DOWNTO 0) <= s_mar_output(31 DOWNTO 0);
--mdr(31 DOWNTO 0) <= s_mdr_output(31 DOWNTO 0);
--pc(31 DOWNTO 0) <= s_ram_output(31 DOWNTO 0);
--r0(31 DOWNTO 0) <= s_reg_31(31 DOWNTO 0);
--r1(31 DOWNTO 0) <= s_reg_01(31 DOWNTO 0);
--r2(31 DOWNTO 0) <= s_reg_02(31 DOWNTO 0);
--r3(31 DOWNTO 0) <= s_reg_03(31 DOWNTO 0);
--r4(31 DOWNTO 0) <= s_reg_04(31 DOWNTO 0);
--signal_alu(31 DOWNTO 0) <= s_alu_output(31 DOWNTO 0);
--ra(31 DOWNTO 0) <= s_register_a_output(31 DOWNTO 0);
--rb(31 DOWNTO 0) <= s_register_b_output(31 DOWNTO 0);
--status(31 DOWNTO 0) <= s_status_register_output;
hex(31 DOWNTO 0) <= s_hex_output;
-- Main data multiplexer driven by control selection signal
main_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 3
)
PORT MAP
(
in_i(0) => s_shifter_output,
in_i(1) => s_alu_output,
in_i(2) => s_mdr_output,
in_i(3) => s_pc_output,
in_i(4) => s_mask_output,
in_sel(2 DOWNTO 0) => s_controller_sel(c_select_mux_main + c_select_mux_main_width - 1 DOWNTO c_select_mux_main),
out_o => s_main_mux_output
);
-- Controller unity receives ir, status and negated clock for double speed
controller: ENTITY WORK.controller(behavioral)
PORT MAP
(
in_ir => s_ir_output,
in_st => s_status_register_output,
in_clk => NOT(system_clock),
out_mask => s_controller_mask,
out_en => s_controller_en,
out_fun => s_controller_fun,
out_sel => s_controller_sel
);
-- Program counter register
program_counter: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_pc_input,
s_controller_en(c_clock_program_counter),
system_clock,
s_pc_output
);
-- Program counter incrementer
pc_incrementer: ENTITY WORK.adder(behavioral)
PORT MAP
(
s_pc_output,
STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
'1',
s_pc_incrementer_output,
OPEN
);
-- Program counter data selection multiplexer
pc_incrementer_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 1
)
PORT MAP
(
in_i(0) => s_main_mux_output,
in_i(1) => s_pc_incrementer_output,
in_sel => s_controller_sel(c_select_mux_pc_incrementer DOWNTO c_select_mux_pc_incrementer),
out_o => s_pc_input
);
-- Memory address register
memory_address_register: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(c_clock_mar),
system_clock,
s_mar_output
);
-- Memory destination register
memory_destination_register: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_ram_output,
s_controller_en(c_clock_mdr),
system_clock,
s_mdr_output
);
-- Instruction register
instruction_register: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_ram_output,
s_controller_en(c_clock_instruction_register),
system_clock,
s_ir_output
);
-- Memory mapped IO controller
mem_io: ENTITY WORK.ram_io(behavioral)
PORT MAP
(
s_main_mux_output, -- mem_io data
s_mar_output, -- mem_io addr
buttons, -- board buttons
switches, -- board switches
s_controller_fun(c_function_ram_we), -- mem_io combined write enable
s_controller_en(c_clock_ram),
system_clock,
-------------------------------------------
s_ram_output, -- fans out to registers
s_hex_output
);
-- -- IO/Memory bus controller
-- io_memory_bus: ENTITY WORK.bus_controller(behavioral)
-- PORT MAP
-- (
-- s_mar_output,
-- s_main_mux_output,
-- s_io_output,
-- s_ram_output,
-- s_controller_en(c_clock_ram),
-- s_bus_addr,
-- s_bus_data,
-- s_mdr_input,
-- s_ram_enable,
-- s_io_enable
-- );
-- -- IO controller
-- io_data_controller: ENTITY WORK.io_controller(behavioral)
-- PORT MAP
-- (
-- s_bus_data,
-- s_bus_addr,
-- s_controller_fun(c_function_ram_we),
-- s_io_enable,
-- system_clock,
-- buttons,
-- switches,
-- s_io_output,
-- s_hex_output
-- );
-- -- Ram block
-- ram: ENTITY WORK.ram(behavioral)
-- GENERIC MAP
-- (
-- g_addr_width => 10
-- )
-- PORT MAP
-- (
-- s_bus_data,
-- s_bus_addr(9 DOWNTO 0),
-- s_controller_fun(c_function_ram_we),
-- s_ram_enable,
-- system_clock,
-- s_ram_output
-- );
-- Alu register a
register_a: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_register_bank_output_a,
s_controller_en(c_clock_register_a),
system_clock,
s_register_a_output
);
-- Alu register b
register_b: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_register_bank_output_b,
s_controller_en(c_clock_register_b),
system_clock,
s_register_b_output
);
-- Bit shifter
shifter: ENTITY WORK.shifter(behavioral)
PORT MAP
(
s_register_a_output,
s_controller_fun(c_function_shifter + c_function_shifter_width - 1 DOWNTO c_function_shifter),
s_shifter_output,
s_shifter_status_output(3 DOWNTO 0)
);
-- Alu
alu: ENTITY WORK.alu(behavioral)
PORT MAP
(
s_register_a_output,
s_register_b_output,
s_controller_fun(c_function_alu_cin),
s_controller_fun(c_function_alu + c_function_alu_width - 1 DOWNTO c_function_alu),
s_alu_output,
s_alu_status_output(3 DOWNTO 0)
);
-- Status selector multiplexer driven by control selection signal
status_mux: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 1
)
PORT MAP
(
in_i(0) => s_alu_status_output,
in_i(1) => s_shifter_status_output,
in_sel => s_controller_sel(c_select_mux_status_alu_shifter DOWNTO c_select_mux_status_alu_shifter),
out_o => s_mux_status_output
);
-- Status register
status_register: ENTITY WORK.parallel_register
PORT MAP
(
s_mux_status_output,
s_controller_en(c_clock_status_register),
system_clock,
s_status_register_output
);
-- Register bank registers
r00: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(0),
system_clock,
s_reg_00
);
r01: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(1),
system_clock,
s_reg_01
);
r02: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(2),
system_clock,
s_reg_02
);
r03: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(3),
system_clock,
s_reg_03
);
r04: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(4),
system_clock,
s_reg_04
);
r05: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(5),
system_clock,
s_reg_05
);
r06: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(6),
system_clock,
s_reg_06
);
r07: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(7),
system_clock,
s_reg_07
);
r08: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(8),
system_clock,
s_reg_08
);
r09: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(9),
system_clock,
s_reg_09
);
r10: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(10),
system_clock,
s_reg_10
);
r11: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(11),
system_clock,
s_reg_11
);
r12: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(12),
system_clock,
s_reg_12
);
r13: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(13),
system_clock,
s_reg_13
);
r14: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(14),
system_clock,
s_reg_14
);
r15: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(15),
system_clock,
s_reg_15
);
r16: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(16),
system_clock,
s_reg_16
);
r17: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(17),
system_clock,
s_reg_17
);
r18: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(18),
system_clock,
s_reg_18
);
r19: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(19),
system_clock,
s_reg_19
);
r20: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(20),
system_clock,
s_reg_20
);
r21: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(21),
system_clock,
s_reg_21
);
r22: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(22),
system_clock,
s_reg_22
);
r23: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(23),
system_clock,
s_reg_23
);
r24: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(24),
system_clock,
s_reg_24
);
r25: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(25),
system_clock,
s_reg_25
);
r26: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(26),
system_clock,
s_reg_26
);
r27: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(27),
system_clock,
s_reg_27
);
r28: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(28),
system_clock,
s_reg_28
);
r29: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(29),
system_clock,
s_reg_29
);
r30: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(30),
system_clock,
s_reg_30
);
r31: ENTITY WORK.parallel_register(behavioral)
PORT MAP
(
s_main_mux_output,
s_controller_en(31),
system_clock,
s_reg_31
);
-- Register bank data output a multiplexer driven by selection signal
m1: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 5
)
PORT MAP
(
in_i(0) => s_reg_00,
in_i(1) => s_reg_01,
in_i(2) => s_reg_02,
in_i(3) => s_reg_03,
in_i(4) => s_reg_04,
in_i(5) => s_reg_05,
in_i(6) => s_reg_06,
in_i(7) => s_reg_07,
in_i(8) => s_reg_08,
in_i(9) => s_reg_09,
in_i(10) => s_reg_10,
in_i(11) => s_reg_11,
in_i(12) => s_reg_12,
in_i(13) => s_reg_13,
in_i(14) => s_reg_14,
in_i(15) => s_reg_15,
in_i(16) => s_reg_16,
in_i(17) => s_reg_17,
in_i(18) => s_reg_18,
in_i(19) => s_reg_19,
in_i(20) => s_reg_20,
in_i(21) => s_reg_21,
in_i(22) => s_reg_22,
in_i(23) => s_reg_23,
in_i(24) => s_reg_24,
in_i(25) => s_reg_25,
in_i(26) => s_reg_26,
in_i(27) => s_reg_27,
in_i(28) => s_reg_28,
in_i(29) => s_reg_29,
in_i(30) => s_reg_30,
in_i(31) => s_reg_31,
in_sel => s_controller_sel(c_select_mux_registerbank_a + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_a),
out_o => s_register_bank_output_a
);
-- Register bank data output b multiplexer driven by selection signal
m2: ENTITY WORK.mux(behavioral)
GENERIC MAP
(
g_selection_width => 5
)
PORT MAP
(
in_i(0) => s_reg_00,
in_i(1) => s_reg_01,
in_i(2) => s_reg_02,
in_i(3) => s_reg_03,
in_i(4) => s_reg_04,
in_i(5) => s_reg_05,
in_i(6) => s_reg_06,
in_i(7) => s_reg_07,
in_i(8) => s_reg_08,
in_i(9) => s_reg_09,
in_i(10) => s_reg_10,
in_i(11) => s_reg_11,
in_i(12) => s_reg_12,
in_i(13) => s_reg_13,
in_i(14) => s_reg_14,
in_i(15) => s_reg_15,
in_i(16) => s_reg_16,
in_i(17) => s_reg_17,
in_i(18) => s_reg_18,
in_i(19) => s_reg_19,
in_i(20) => s_reg_20,
in_i(21) => s_reg_21,
in_i(22) => s_reg_22,
in_i(23) => s_reg_23,
in_i(24) => s_reg_24,
in_i(25) => s_reg_25,
in_i(26) => s_reg_26,
in_i(27) => s_reg_27,
in_i(28) => s_reg_28,
in_i(29) => s_reg_29,
in_i(30) => s_reg_30,
in_i(31) => s_reg_31,
in_sel => s_controller_sel(c_select_mux_registerbank_b + c_select_mux_registerbank_width - 1 DOWNTO c_select_mux_registerbank_b),
out_o => s_register_bank_output_b
);
-- Data masking
s_mask_output <= s_controller_mask AND s_mdr_output;
END behavioral;
|
mit
|
0a727a32e946188a9e2c741ff8bb2aa3
| 0.633292 | 2.642272 | false | false | false | false |
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