repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
fpga-logi/logi-hard
|
hdl/primitive/tdp_bram.vhd
| 2 | 2,498 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
entity tdp_bram is
generic (
DATA_A : integer := 16;
ADDR_A : integer := 10;
DATA_B : integer := 16;
ADDR_B : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_A-1 downto 0);
a_din : in std_logic_vector(DATA_A-1 downto 0);
a_dout : out std_logic_vector(DATA_A-1 downto 0);
-- Port B
b_clk : in std_logic;
b_wr : in std_logic;
b_addr : in std_logic_vector(ADDR_B-1 downto 0);
b_din : in std_logic_vector(DATA_B-1 downto 0);
b_dout : out std_logic_vector(DATA_B-1 downto 0)
);
end tdp_bram;
architecture rtl of tdp_bram is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
function max(val1: INTEGER; val2: INTEGER) return natural is
variable res : natural;
begin
if val1 > val2 then
return val1 ;
end if ;
return val2 ;
end function MAX;
function min(val1: INTEGER; val2: INTEGER) return natural is
variable res : natural;
begin
if val1 < val2 then
return val1 ;
end if ;
return val2 ;
end function min;
constant minWidth : integer := min(DATA_A, DATA_B);
constant maxWidth : integer := max(DATA_A, DATA_B);
constant RATIO : integer := maxWidth / minWidth;
-- Shared memory
type mem_type is array ( 2**(max(ADDR_A,ADDR_B))-1 downto 0 ) of std_logic_vector(minWidth-1 downto 0);
shared variable mem : mem_type;
begin
assert (DATA_B>=DATA_A) report "Port B must be the larger of the two" severity ERROR;
-- Port A
process(a_clk)
begin
if(a_clk'event and a_clk='1') then
if(a_wr='1') then
mem(conv_integer(a_addr)) := a_din;
end if;
a_dout <= mem(conv_integer(a_addr));
end if;
end process;
-- Port B
process(b_clk)
begin
if(b_clk'event and b_clk='1') then
for i in 0 to RATIO-1 loop
if(b_wr='1') then
mem(conv_integer(b_addr & std_logic_vector(to_unsigned(i,log2(RATIO))))):= b_din((i+1)*minWidth-1 downto i*minWidth);
end if;
b_dout(((i+1)*minWidth)-1 downto i*minWidth) <= mem(conv_integer(b_addr & std_logic_vector(to_unsigned(i,log2(RATIO)))));
end loop ;
end if;
end process;
end rtl;
|
lgpl-3.0
|
f89d163ffcaa7cc77f6f0887e2abe178
| 0.608887 | 2.901278 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_pwm.vhd
| 1 | 4,122 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:11 08/28/2013
-- Design Name:
-- Module Name: wishbone_pwm - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.control_pack.all ;
entity wishbone_pwm is
generic( nb_chan : positive := 7;
wb_addr_size : natural := 16; -- Address port size for wishbone
wb_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
pwm_out : out std_logic_vector(nb_chan-1 downto 0)
);
end wishbone_pwm;
architecture Behavioral of wishbone_pwm is
signal pwm_regs : slv16_array(0 to (nb_chan+1)) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal reverse_outputs : std_logic_vector(0 to (nb_chan-1));
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= pwm_regs(conv_integer(wbs_address)) ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
register_mngmt : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
pwm_regs(conv_integer(wbs_address)) <= wbs_writedata;
end if ;
end if;
end process register_mngmt;
pwm_ctrl : pwm
generic map(NB_CHANNEL => nb_chan)
port map(
clk => gls_clk,
resetn => (NOT gls_reset),
divider => pwm_regs(0),
period => pwm_regs(1),
pulse_width => pwm_regs(2 to (2+(nb_chan-1))),
pwm => reverse_outputs
);
gen_reverse : for i in 0 to nb_chan-1 generate
pwm_out(i) <= reverse_outputs(i) ;
end generate ;
end Behavioral;
|
lgpl-3.0
|
82d340983dff0f571c86c1185dd57b02
| 0.599951 | 3.575022 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altserial_flash_loader/_primary.vhd
| 1 | 1,302 |
library verilog;
use verilog.vl_types.all;
entity altserial_flash_loader is
generic(
enhanced_mode : integer := 0;
intended_device_family: string := "Cyclone";
enable_shared_access: string := "OFF";
enable_quad_spi_support: integer := 0;
lpm_type : string := "ALTSERIAL_FLASH_LOADER"
);
port(
data_in : in vl_logic_vector(3 downto 0);
noe : in vl_logic;
asmi_access_granted: in vl_logic;
data_out : out vl_logic_vector(3 downto 0);
data_oe : in vl_logic_vector(3 downto 0);
sdoin : in vl_logic;
asmi_access_request: out vl_logic;
data0out : out vl_logic;
scein : in vl_logic;
dclkin : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of enhanced_mode : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of enable_shared_access : constant is 1;
attribute mti_svvh_generic_type of enable_quad_spi_support : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end altserial_flash_loader;
|
bsd-2-clause
|
f23a6f0a97d197cf16022ab20f51a736
| 0.586022 | 3.709402 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb.vhd
| 1 | 6,208 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 77
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-3.0
|
f095a821a115e763e46f42f1c0b455f8
| 0.626772 | 4.012928 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/output_pin_cntl.vhd
| 2 | 1,660 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:51:17 12/20/2009
-- Design Name:
-- Module Name: output_pin_cntl - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Description: The output pin register and controller for the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.20 - File written, will test with rest of processor; not complex enough to warrant the time
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity output_pin_cntl is
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(3 downto 0);
pins : out STD_LOGIC_VECTOR (15 downto 0));
end output_pin_cntl;
architecture Behavioral of output_pin_cntl is
begin
opin: process (clock, reset) is
variable opin_reg : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
begin
if falling_edge(clock) then
if enable = '1' then
opin_reg(conv_integer(unsigned(sel))) := data;
end if;
end if;
if reset = '1' then
opin_reg := (others => '0');
end if;
pins <= opin_reg;
end process;
end Behavioral;
|
mit
|
3203c513f9b9485e2e392e4f62fee1ac
| 0.56747 | 3.608696 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_s6/simulation/fg_tb_synth.vhd
| 1 | 11,517 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 1,
C_DOUT_WIDTH => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pulse_regen_s6_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
e33a99556ba50d376982f55c0e5b820a
| 0.44239 | 3.971379 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/crc_check.vhd
| 1 | 12,138 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-03-17 12:13:46 +0100 (Wed, 17 Mar 2010) $
-- Revision : $Revision: 62 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
library work;
use work.all;
--use work.app_pack.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity crc_checker is
generic (
NROF_DATACONN : integer;
DATAWIDTH : integer;
NROF_WINDOWS : integer;
POLYNOMIAL : std_logic_vector
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
-- APP_CFG_REG : in AppCfgRegTp;
INITVALUE : in std_logic;
en_decoder : in std_logic;
-- Data input
PAR_SYNC_IN : in std_logic_vector(DATAWIDTH-1 downto 0);
PAR_DATA_IN : in std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID_IN : in std_logic;
PAR_DATA_BLACKVALID_IN : in std_logic;
PAR_DATA_CRCVALID_IN : in std_logic;
PAR_DATA_LINE_IN : in std_logic;
PAR_DATA_FRAME_IN : in std_logic;
START_KERNEL_IN : in std_logic;
KERNEL_ODD_EVEN_IN : in std_logic;
VIDEO_SYNC_IN : in std_logic_vector(4 downto 0);
-- Data out
PAR_SYNC_OUT : out std_logic_vector(DATAWIDTH-1 downto 0);
PAR_DATA_OUT : out std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID_OUT : out std_logic;
PAR_DATA_BLACKVALID_OUT : out std_logic;
PAR_DATA_CRCVALID_OUT : out std_logic;
PAR_DATA_LINE_OUT : out std_logic;
PAR_DATA_FRAME_OUT : out std_logic;
START_KERNEL_OUT : out std_logic;
KERNEL_ODD_EVEN_OUT : out std_logic;
VIDEO_SYNC_OUT : out std_logic_vector(4 downto 0);
--status
CRC_STATUS : out std_logic_vector(NROF_DATACONN-1 downto 0)
);
end crc_checker;
---------------------------
-- BEHAVIOUR DESCRIPTION --
---------------------------
architecture rtl of crc_checker is
component crc_calc
generic (
DATAWIDTH : integer := 8;
POLYNOMIAL : std_logic_vector := "101001101";
USE_CRC_TOOL : boolean := TRUE
);
port ( -- System
-- APP_CFG_REG : in AppCfgRegTp;
INITVALUE : in std_logic;
CLOCK : in std_logic;
RESET : in std_logic;
-- Data input
INIT : in std_logic;
DATA_IN : in std_logic_vector(DATAWIDTH-1 downto 0);
CRC_OUT : out std_logic_vector(DATAWIDTH-1 downto 0)
);
end component;
component crc_comp
generic (
DATAWIDTH : integer := 8
);
port ( -- System
CLOCK : in std_logic;
RESET : in std_logic;
-- Data input
en_decoder : in std_logic;
VALID : in std_logic;
SENS_CRC_IN : in std_logic_vector(DATAWIDTH-1 downto 0);
CALC_CRC_IN : in std_logic_vector(DATAWIDTH-1 downto 0);
STATUS : out std_logic
);
end component;
--signals
type CRCcheckstatetp is ( Idle,
Valid
);
signal CRCcheckstate : CRCcheckstatetp;
signal init : std_logic;
signal calc_CRC : std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
signal PAR_DATA_int : std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0) ;
signal PAR_DATA_IMGVALID_int : std_logic;
signal PAR_DATA_BLACKVALID_int : std_logic;
signal PAR_DATA_CRCVALID_int : std_logic;
signal PAR_DATA_LINE_int : std_logic;
signal PAR_DATA_FRAME_int : std_logic;
signal PAR_SYNC_int : std_logic_vector((DATAWIDTH)-1 downto 0) ;
signal START_KERNEL_int : std_logic;
signal KERNEL_ODD_EVEN_int : std_logic;
signal VIDEO_SYNC_int : std_logic_vector(4 downto 0);
begin
-- generate parallel CRC checkers
generate_CRC: for i in 0 to (NROF_DATACONN-1) generate
the_crc_calc: crc_calc
generic map(
DATAWIDTH => DATAWIDTH ,
POLYNOMIAL => POLYNOMIAL ,
USE_CRC_TOOL => TRUE
)
port map(
-- APP_CFG_REG => APP_CFG_REG,
INITVALUE => INITVALUE ,
CLOCK => CLOCK ,
RESET => RESET ,
INIT => init ,
DATA_IN => PAR_DATA_int((i*DATAWIDTH)+(DATAWIDTH-1) downto (i*DATAWIDTH)) ,
CRC_OUT => calc_crc((i*DATAWIDTH)+(DATAWIDTH-1) downto (i*DATAWIDTH))
);
the_crc_comp: crc_comp
generic map(
DATAWIDTH => DATAWIDTH
)
port map(
CLOCK => CLOCK ,
RESET => RESET ,
en_decoder => en_decoder ,
VALID => PAR_DATA_CRCVALID_int ,
SENS_CRC_IN => PAR_DATA_int((i*DATAWIDTH)+(DATAWIDTH-1) downto (i*DATAWIDTH)) ,
CALC_CRC_IN => calc_crc((i*DATAWIDTH)+(DATAWIDTH-1) downto (i*DATAWIDTH)) ,
STATUS => CRC_STATUS(i)
);
end generate;
InitProcess: process(RESET, CLOCK)
begin
if (RESET = '1') then
init <= '1';
CRCcheckstate <= Idle;
elsif(CLOCK'event and CLOCK = '1') then
if (en_decoder ='1') then
case CRCcheckstate is
when Idle =>
init <= '1';
if (PAR_DATA_IMGVALID_IN = '1' or PAR_DATA_BLACKVALID_IN = '1') then
init <= '0';
CRCcheckstate <= Valid;
end if;
when Valid =>
init <= '0';
if (PAR_DATA_IMGVALID_IN = '0' and PAR_DATA_BLACKVALID_IN = '0') then
init <= '1';
CRCcheckstate <= Idle;
end if;
when others =>
CRCcheckstate <= Idle;
end case;
else
init <= '1';
CRCcheckstate <= Idle;
end if;
end if;
end process;
DataProcess: process(RESET, CLOCK)
begin
if (RESET = '1') then
PAR_DATA_IMGVALID_OUT <= '0';
PAR_DATA_BLACKVALID_OUT <= '0';
PAR_DATA_CRCVALID_OUT <= '0';
PAR_DATA_IMGVALID_int <= '0';
PAR_DATA_BLACKVALID_int <= '0';
PAR_DATA_CRCVALID_int <= '0';
PAR_DATA_LINE_int <= '0';
PAR_DATA_FRAME_int <= '0';
START_KERNEL_int <= '0';
KERNEL_ODD_EVEN_int <= '0';
VIDEO_SYNC_int <= (others => '0');
START_KERNEL_OUT <= '0';
KERNEL_ODD_EVEN_OUT <= '0';
VIDEO_SYNC_OUT <= (others => '0');
PAR_DATA_LINE_OUT <= '0';
PAR_DATA_FRAME_OUT <= '0';
PAR_SYNC_int <= (others => '0');
PAR_SYNC_OUT <= (others => '0');
elsif (CLOCK'event and CLOCK = '1') then
PAR_DATA_int <= PAR_DATA_IN;
PAR_DATA_OUT <= PAR_DATA_int;
PAR_DATA_IMGVALID_int <= PAR_DATA_IMGVALID_IN;
PAR_DATA_BLACKVALID_int <= PAR_DATA_BLACKVALID_IN;
PAR_DATA_IMGVALID_OUT <= PAR_DATA_IMGVALID_int;
PAR_DATA_BLACKVALID_OUT <= PAR_DATA_BLACKVALID_int;
PAR_DATA_CRCVALID_int <= PAR_DATA_CRCVALID_IN;
PAR_DATA_CRCVALID_OUT <= PAR_DATA_CRCVALID_int;
PAR_DATA_LINE_int <= PAR_DATA_LINE_IN;
PAR_DATA_FRAME_int <= PAR_DATA_FRAME_IN;
PAR_DATA_LINE_OUT <= PAR_DATA_LINE_int;
PAR_DATA_FRAME_OUT <= PAR_DATA_FRAME_int;
PAR_SYNC_int <= PAR_SYNC_IN;
PAR_SYNC_OUT <= PAR_SYNC_int;
START_KERNEL_int <= START_KERNEL_IN;
KERNEL_ODD_EVEN_int <= KERNEL_ODD_EVEN_IN;
VIDEO_SYNC_int <= VIDEO_SYNC_IN;
START_KERNEL_OUT <= START_KERNEL_int;
KERNEL_ODD_EVEN_OUT <= KERNEL_ODD_EVEN_int;
VIDEO_SYNC_OUT <= VIDEO_SYNC_int;
end if;
end process;
end rtl;
|
gpl-3.0
|
bbe51ac5f45f847668269ee43868914f
| 0.43714 | 4.405808 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_dram_fifo.vhd
| 2 | 10,087 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_dram_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth;
BURST_SIZE : positive := 4;
THRESHOLD : positive := 4;
FIFO_SIZE : positive := 8_000_000;
SYNC_LOGIC_INTERFACE : boolean := false;
IS_READ : boolean := true ;
sdram_address_width : positive := 24;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0')
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
write_fifo, read_fifo : in std_logic ;
fifo_input: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
fifo_output : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
fifo_empty, fifo_full : out std_logic ;
fifo_reset : out std_logic ;
fifo_threshold : out std_logic;
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end wishbone_dram_fifo;
architecture RTL of wishbone_dram_fifo is
component dram_fifo is
generic(CACHE_SIZE : positive := 2048;
FIFO_SIZE : positive := 8_000_000;
sdram_address_width : positive := 24;
SYNC_READ : boolean := true;
SYNC_WRITE : boolean := true;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- FIFO interface
reset_fifo : in std_logic ;
write_fifo, read_fifo : in std_logic ;
nb_available : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
refresh_active, flush_active : out std_logic ;
-- Interface to issue reads or write data
cmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : out STD_LOGIC; -- Is this a write?
cmd_address : out STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
sdram_data_out : in STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
sdram_data_ready : in STD_LOGIC
);
end component;
constant address_space_nbit : integer := MAX((nbit(BURST_SIZE)+1), 3);
signal read_from_bus, write_from_bus, reset_fifo: std_logic ;
signal data_from_bus, data_to_bus : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_available_fifo : std_logic_vector(31 downto 0 );
signal write_ack, read_ack, read_ack_old, write_ack_old, write_ack_re, read_ack_fe : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal control_space_data_spacen : std_logic ;
begin
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
write_ack_old <= write_ack ;
end if;
end process write_bloc;
write_ack_re <= (not write_ack_old) and write_ack ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0';
control_latched <= (others => '0');
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
read_ack_old <= read_ack ;
end if;
end process read_bloc;
read_ack_fe <= (not read_ack) and read_ack_old;
wbs_ack <= read_ack or write_ack;
gen_read_fifo : if IS_READ generate
fifo_read_from_bus : dram_fifo
generic map(CACHE_SIZE => 2048,
FIFO_SIZE => FIFO_SIZE,
sdram_address_width => 24,
SYNC_READ => false,
SYNC_WRITE => true,
CACHE_ADDRESS =>CACHE_ADDRESS)
port map(
clk => gls_clk,
reset => gls_reset,
-- FIFO interface
reset_fifo => reset_fifo,
write_fifo => write_fifo,
read_fifo => read_from_bus,
nb_available => nb_available_fifo,
data_out => data_to_bus, -- to bus
data_in => fifo_input, -- from logic
refresh_active => refresh_active,
flush_active => flush_active,
-- Interface to issue reads or write data
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
end generate ;
gen_write_fifo : if NOT IS_READ generate
fifo_write_from_bus : dram_fifo
generic map(CACHE_SIZE => 2048,
FIFO_SIZE => FIFO_SIZE,
sdram_address_width => 24,
SYNC_READ => true,
SYNC_WRITE => false,
CACHE_ADDRESS =>CACHE_ADDRESS)
port map(
clk => gls_clk,
reset => gls_reset,
-- FIFO interface
reset_fifo => reset_fifo,
write_fifo => write_from_bus,
read_fifo => read_fifo,
nb_available => nb_available_fifo,
data_out => fifo_output, -- to logic
data_in => data_from_bus, -- from bus
refresh_active => refresh_active,
flush_active => flush_active,
-- Interface to issue reads or write data
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
data_to_bus <= (others => '0');
end generate ;
control_space_data_spacen <= wbs_address((address_space_nbit-1)) ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_available_fifo(15 downto 0)) when wbs_address(1 downto 0)= "01" else
( nb_available_fifo(31 downto 16)) when wbs_address(1 downto 0)= "10" else
(others => '0');
wbs_readdata <= control_latched when control_space_data_spacen = '1' else
data_to_bus ;
--read_from_bus <= read_ack_fe when control_space_data_spacen = '0' else
-- '0' ;
read_from_bus <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
--write_from_bus <= write_ack_re when control_space_data_spacen = '0' else
-- '0' ;
write_from_bus <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' else
'0' ;
reset_fifo <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "01"else
'1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "10"else
'0' ;
fifo_reset <= reset_fifo ;
data_from_bus <= wbs_writedata ;
fifo_threshold <= '1' when nb_available_fifo > THRESHOLD else
'0' ;
fifo_full <= '1' when nb_available_fifo >= FIFO_SIZE else
'0' ;
end RTL;
|
lgpl-3.0
|
b2169b952a37bb6f3a6ab2b765bb208b
| 0.612075 | 3.217544 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pctrl.vhd
| 1 | 18,511 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-3.0
|
33ecae151d00ffa88b84b0841962a5b5
| 0.512452 | 3.232798 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_s6.vhd
| 1 | 10,574 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file pulse_regen_s6.vhd when simulating
-- the core, pulse_regen_s6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY pulse_regen_s6 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END pulse_regen_s6;
ARCHITECTURE pulse_regen_s6_a OF pulse_regen_s6 IS
-- synthesis translate_off
COMPONENT wrapped_pulse_regen_s6
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_pulse_regen_s6 USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 4,
c_default_value => "BlankString",
c_din_width => 1,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 1,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 2,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 15,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 14,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 4,
c_rd_depth => 16,
c_rd_freq => 1,
c_rd_pntr_width => 4,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 4,
c_wr_depth => 16,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 4,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_pulse_regen_s6
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid
);
-- synthesis translate_on
END pulse_regen_s6_a;
|
gpl-3.0
|
f862338c571530d905137050ef0c764c
| 0.522224 | 3.356825 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl
| 1 | 51,061 |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Tue Aug 1 10:07:10 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl
-- Design : blk_mem_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_wrapper_init is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
enb : in STD_LOGIC;
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end blk_mem_gen_0_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5F649B969696100A7D7D9696AFA5100A969696A0C8B412079696969696960300",
INIT_01 => X"969696C8C891100A967D87AFAF96100A8C647896969610076E55829696961006",
INIT_02 => X"CDC891969696200AAFAF96967D87200A9696968C64782207969696BED7AA1106",
INIT_03 => X"96969664649B200A96AFA57D7D96200AA0C8B49696962007BED7AA9696962006",
INIT_04 => X"9696969696963107A5968CA0968C300A969696875F7D320D9696966E55822106",
INIT_05 => X"9696969696964109B9CDA59696964009C3C396A0968C4005A5968CA0968C4207",
INIT_06 => X"96B4789678B4501496B4789678B450069696879696A5500A969696969696520A",
INIT_07 => X"00000000000000000000000000000000969696969696511496A08C968CA0500A",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => addrb(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addra(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clkb,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dina(7 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => doutb(31 downto 0),
DOBDO(31 downto 0) => doutb(63 downto 32),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => enb,
ENBWREN => ena,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => enb,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => wea(0),
WEBWE(6) => wea(0),
WEBWE(5) => wea(0),
WEBWE(4) => wea(0),
WEBWE(3) => wea(0),
WEBWE(2) => wea(0),
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
enb : in STD_LOGIC;
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_0_blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.blk_mem_gen_0_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
enb : in STD_LOGIC;
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_0_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
enb : in STD_LOGIC;
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_0_blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_0_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_3_6_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
enb : in STD_LOGIC;
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_3_6_synth : entity is "blk_mem_gen_v8_3_6_synth";
end blk_mem_gen_0_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_0_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 8 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 4.4085 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 4000;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 500;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 64;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 4000;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 500;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is 64;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_v8_3_6";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0_blk_mem_gen_v8_3_6 : entity is "yes";
end blk_mem_gen_0_blk_mem_gen_v8_3_6;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_0_blk_mem_gen_v8_3_6_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_0 : entity is "blk_mem_gen_v8_3_6,Vivado 2017.1";
end blk_mem_gen_0;
architecture STRUCTURE of blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.4085 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "blk_mem_gen_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4000;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 500;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 64;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4000;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 500;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 64;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.blk_mem_gen_0_blk_mem_gen_v8_3_6
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => addrb(8 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(63 downto 0) => doutb(63 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
gpl-3.0
|
18fff66ae5b0fbd08098a8c3083512a0
| 0.690997 | 3.402252 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_k7.vhd
| 1 | 10,574 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file pulse_regen_k7.vhd when simulating
-- the core, pulse_regen_k7. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY pulse_regen_k7 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END pulse_regen_k7;
ARCHITECTURE pulse_regen_k7_a OF pulse_regen_k7 IS
-- synthesis translate_off
COMPONENT wrapped_pulse_regen_k7
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_pulse_regen_k7 USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 4,
c_default_value => "BlankString",
c_din_width => 1,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 1,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 2,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 15,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 14,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 4,
c_rd_depth => 16,
c_rd_freq => 1,
c_rd_pntr_width => 4,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 4,
c_wr_depth => 16,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 4,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_pulse_regen_k7
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid
);
-- synthesis translate_on
END pulse_regen_k7_a;
|
gpl-3.0
|
a5fbccab421f7e3ecd15be50394889d8
| 0.522224 | 3.356825 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/Clock_Mgt.vhd
| 2 | 8,289 |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Clock_Mgt
--Module Description:
-- The clock manager/generator takes the 50 MHz clock from the Nexys 2 board
-- and produces four clock signals using three DCMs. They are:
-- the main clock, 1.5625 MHz
-- the doubled clock, 3.125 MHz
-- an inverted main clock, 1.5625 MHz
-- a 90 degree shifted doubled clock, 3.125 MHz
-- As a side note, I would have only needed one clock signal if I had my
-- way with which memory resources were on the board and how they were
-- organized.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Clock_Mgt is
Port ( board_clock : in STD_LOGIC;
clock1_out : out STD_LOGIC;
clock2_out : out STD_LOGIC;
clock3_out : out STD_LOGIC;
clock4_out : out STD_LOGIC);
end Clock_Mgt;
architecture Behavioral of Clock_Mgt is
--//Signals\\--
--These signals carry DCM 1's outputs and feedback signals
signal DCM_1_out : STD_LOGIC;
signal DCM_1_90 : STD_LOGIC;
signal DCM1_feedback_in : STD_LOGIC;
signal DCM1_feedback_out : STD_LOGIC;
--These signals carry DCM 2's outputs and feedback signals
signal DCM_2_dbl : STD_LOGIC;
signal DCM_2_inv : STD_LOGIC;
signal DCM2_feedback_in : STD_LOGIC;
signal DCM2_feedback_out : STD_LOGIC;
--These signals carry DCM 4's input and output
signal DCM_3_out : STD_LOGIC;
signal DCM_3_in : STD_LOGIC;
--This signal carries the board clock after it's been put
--through a global clock buffer
signal buf_board_clock : STD_LOGIC;
--\\Signals//--
begin
--This BUFG buffers the board clock
board_clk: BUFG
port map (O => buf_board_clock,
I => board_clock);
--These DCMs cut the clock down and generate the appropriate clock signals
--DCM 1 generates a shifted 25 MHz clock that'll be cut down by DCM 3 to make the
--shifted, doubled clock used for the memory bus controller. This DCM also produces
--the main clock, 1.5625 MHz
DCM_1 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 32, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 40.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => DCM_1_out, -- DCM CLK synthesis out (M/D)
CLKIN => buf_board_clock,
CLK90 => DCM_1_90,
CLKFB => DCM1_feedback_in,
CLK0 => DCM1_feedback_out
);
--This BUFG buffers DCM1's feedback
DCM1_feedback: BUF
port map (O => DCM1_feedback_in,
I => DCM1_feedback_out);
--DCM 2 produces the inverted main clock, as well as the doubled clock for use by the
--IF stage
DCM_2 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 640.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => DCM_1_out, -- Clock input (from IBUFG, BUFG or DCM)
CLK2X => DCM_2_dbl,
CLK180 => DCM_2_inv,
CLKFB => DCM2_feedback_in,
CLK0 => DCM2_feedback_out
);
--This BUFG buffers DCM3's feedback
DCM2_feedback: BUF
port map (O => DCM2_feedback_in,
I => DCM2_feedback_out);
--This buffer takes care of buffering the 25 MHz shifted clock from DCM 1 so
--that DCM 3 can use it. I had to do this because of, I think, fanout problems
DCM1_DCM3_buf: BUFG
port map (O => DCM_3_in,
I => DCM_1_90);
--DCM 3 takes the shifted, 25 MHz clock signal and divides it down to 3.125 MHz as the
--shifted, doubled clock that the memory bus controller uses
DCM_3 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 16, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 40.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => DCM_3_out, -- DCM CLK synthesis out (M/D)
CLKIN => DCM_3_in
);
--Because of the high fanout of some of these clocks, I placed them all on
--global clock buffers. To be perfectly honest, I'm not sure I needed to do
--this, but I think it provides higher stability
--Main Clock
clock1_out_buf: BUFG
port map (O => clock1_out,
I => DCM_1_out);
--Doubled Clock
clock2_out_buf: BUFG
port map (O => clock2_out,
I => DCM_2_dbl);
--Inverted Clock
clock3_out_buf: BUFG
port map (O => clock3_out,
I => DCM_2_inv);
--Shifted Clock
clock4_out_buf: BUFG
port map (O => clock4_out,
I => DCM_3_out);
end Behavioral;
|
mit
|
70b59d330e2de62e3948180c6adb9aba
| 0.602244 | 3.437993 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/fmc_imageon_vita_receiver.vhd
| 1 | 25,402 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Sep 15, 2011
-- Design Name: FMC-IMAGEON
-- Module Name: fmc_imageon_vita_receiver.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Virtex-6
-- Kintex-7, Zynq
-- Avnet Boards: FMC-IMAGEON
--
-- Tool versions: ISE 14.1
--
-- Description: FMC-IMAGEON VITA receiver interface.
--
-- Dependencies:
--
-- Revision: Sep 15, 2011: 1.00 Initial version:
-- - VITA SPI controller
-- Sep 22, 2011: 1.01 Added:
-- - ISERDES interface
-- Sep 28, 2011: 1.02 Added:
-- - sync channel decoder
-- - crc checker
-- - data remapper
-- Oct 20, 2011: 1.03 Modify:
-- - iserdes (use BUFR)
-- Oct 21, 2011: 1.04 Added:
-- - fpn prnu correction
-- Nov 03, 2011: 1.05 Added:
-- - trigger generator
-- Dec 19, 2011: 1.06 Modified:
-- - port to Kintex-7
-- Jan 12, 2012: 1.07 Added:
-- - new fsync output port
-- Modify:
-- - syncgen
-- Feb 06, 2012: 1.08 Modify:
-- - triggergenerator
-- (new version with debounce logic)
-- - new C_XSVI_DIRECT_OUTPUT option
-- Feb 22, 2012: 1.09 Modified
-- - port to Zynq
-- - new C_XSVI_USE_SYNCGEN option
-- May 13, 2012: 1.10 Optimize
-- - remove one layer of registers
-- May 28, 2012: 1.11 Modify
-- - host_triggen_cnt_update
-- (for simultaneous update of high/low values)
-- Jun 01, 2012: 1.12 Modify:
-- - Move syncgen after demux_fifo
-- - Increase size of demux_fifo
-- (to tolerate jitter in video timing from sensor)
-- - Add programmable delay on framestart for syncgen
-- Jul 31, 2012: 1.13 Modify:
-- - define clk200, clk, clk4x with SIGIS = CLK
-- - define reset with SIGIS = RST
-- - port to Spartan-6
--
------------------------------------------------------------------
------------------------------------------------------------------------------
-- fmc_imageon_vita_receiver.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: fmc_imageon_vita_receiver.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Sep 15 13:07:23 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library fmc_imageon_vita_receiver_v1_13_a;
use fmc_imageon_vita_receiver_v1_13_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH --
-- C_S_AXI_ADDR_WIDTH --
-- C_S_AXI_MIN_SIZE --
-- C_USE_WSTRB --
-- C_DPHASE_TIMEOUT --
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY --
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK --
-- S_AXI_ARESETN --
-- S_AXI_AWADDR --
-- S_AXI_AWVALID --
-- S_AXI_WDATA --
-- S_AXI_WSTRB --
-- S_AXI_WVALID --
-- S_AXI_BREADY --
-- S_AXI_ARADDR --
-- S_AXI_ARVALID --
-- S_AXI_RREADY --
-- S_AXI_ARREADY --
-- S_AXI_RDATA --
-- S_AXI_RRESP --
-- S_AXI_RVALID --
-- S_AXI_WREADY --
-- S_AXI_BRESP --
-- S_AXI_BVALID --
-- S_AXI_AWREADY --
------------------------------------------------------------------------------
entity fmc_imageon_vita_receiver is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_XSVI_DATA_WIDTH : integer := 10;
C_XSVI_DIRECT_OUTPUT : integer := 0;
C_XSVI_USE_SYNCGEN : integer := 1;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk200 : in std_logic;
clk : in std_logic;
clk4x : in std_logic;
reset : in std_logic;
oe : in std_logic;
-- I/O pins
io_vita_clk_pll : out std_logic;
io_vita_reset_n : out std_logic;
io_vita_spi_sclk : out std_logic;
io_vita_spi_ssel_n : out std_logic;
io_vita_spi_mosi : out std_logic;
io_vita_spi_miso : in std_logic;
io_vita_trigger : out std_logic_vector(2 downto 0);
io_vita_monitor : in std_logic_vector(1 downto 0);
io_vita_clk_out_p : in std_logic;
io_vita_clk_out_n : in std_logic;
io_vita_sync_p : in std_logic;
io_vita_sync_n : in std_logic;
io_vita_data_p : in std_logic_vector(7 downto 0);
io_vita_data_n : in std_logic_vector(7 downto 0);
-- Trigger Port
trigger1 : in std_logic;
-- Frame Sync Port
fsync : out std_logic;
-- XSVI Port
xsvi_vsync_o : out std_logic;
xsvi_hsync_o : out std_logic;
xsvi_vblank_o : out std_logic;
xsvi_hblank_o : out std_logic;
xsvi_active_video_o : out std_logic;
xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0);
-- Debug Ports
debug_host_o : out std_logic_vector(231 downto 0);
debug_spi_o : out std_logic_vector( 95 downto 0);
debug_iserdes_o : out std_logic_vector(229 downto 0);
debug_decoder_o : out std_logic_vector(186 downto 0);
debug_crc_o : out std_logic_vector( 87 downto 0);
debug_triggen_o : out std_logic_vector( 9 downto 0);
debug_video_o : out std_logic_vector( 31 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity fmc_imageon_vita_receiver;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of fmc_imageon_vita_receiver is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 64;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity fmc_imageon_vita_receiver_v1_13_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_XSVI_DATA_WIDTH => C_XSVI_DATA_WIDTH,
C_XSVI_DIRECT_OUTPUT => C_XSVI_DIRECT_OUTPUT,
C_XSVI_USE_SYNCGEN => C_XSVI_USE_SYNCGEN,
C_FAMILY => C_FAMILY,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk200 => clk200,
clk => clk,
clk4x => clk4x,
reset => reset,
oe => oe,
-- I/O pins
io_vita_clk_pll => io_vita_clk_pll,
io_vita_reset_n => io_vita_reset_n,
io_vita_spi_sclk => io_vita_spi_sclk,
io_vita_spi_ssel_n => io_vita_spi_ssel_n,
io_vita_spi_mosi => io_vita_spi_mosi,
io_vita_spi_miso => io_vita_spi_miso,
io_vita_trigger => io_vita_trigger,
io_vita_monitor => io_vita_monitor,
io_vita_clk_out_p => io_vita_clk_out_p,
io_vita_clk_out_n => io_vita_clk_out_n,
io_vita_sync_p => io_vita_sync_p,
io_vita_sync_n => io_vita_sync_n,
io_vita_data_p => io_vita_data_p,
io_vita_data_n => io_vita_data_n,
-- Trigger Port
trigger1 => trigger1,
-- Frame Sync Port
fsync => fsync,
-- XSVI Port
xsvi_vsync_o => xsvi_vsync_o,
xsvi_hsync_o => xsvi_hsync_o,
xsvi_vblank_o => xsvi_vblank_o,
xsvi_hblank_o => xsvi_hblank_o,
xsvi_active_video_o => xsvi_active_video_o,
xsvi_video_data_o => xsvi_video_data_o,
-- Debug Ports
debug_host_o => debug_host_o,
debug_spi_o => debug_spi_o,
debug_iserdes_o => debug_iserdes_o,
debug_decoder_o => debug_decoder_o,
debug_crc_o => debug_crc_o,
debug_triggen_o => debug_triggen_o,
debug_video_o => debug_video_o,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
gpl-3.0
|
fe43784c49afbe519f3e7590e69df274
| 0.41792 | 4.221004 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/led8_sseg.vhd
| 2 | 3,208 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
entity led8_sseg is
generic(
clock_freq_hz : natural := 50_000_000;
refresh_rate_hz : natural := 800
);
port
(
clk : in std_logic ;
reset : in std_logic ;
led: in std_logic_vector(7 downto 0);
an : out std_logic_vector(4 downto 0);
sseg_out : out std_logic_vector(7 downto 0)
);
end led8_sseg ;
architecture Behavioral of led8_sseg is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal sseg0, sseg1, sseg2, sseg3, sseg_clk: std_logic_vector(7 downto 0);
signal divider_counter : std_logic_vector(31 downto 0);
signal divider_end : std_logic ;
signal an_r : std_logic_vector(4 downto 0) := "00001";
begin
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, 32));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, 32));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
an_r(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
an_r(4 downto 1) <= an_r(3 downto 0);
an_r(0) <= an_r(4);
end if ;
end if ;
end process ;
with an_r select
sseg_out <= sseg0 when "00001",
sseg1 when "00010",
sseg2 when "00100",
sseg3 when "01000",
sseg_clk when "10000",
(others => '0') when others ;
an <= an_r ;
-- --CONVERT THE LEDS TO THE 4X SEVEN SEGMENTS LED segements
with led(1 downto 0) select
sseg0 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(3 downto 2) select
sseg1 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(5 downto 4) select
sseg2 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
with led(7 downto 6) select
sseg3 <= "00000100" when "01",
"00010000" when "10",
"00010100" when "11",
"00000000" when "00";
end Behavioral;
|
lgpl-3.0
|
ce0ac5199100ca126b56bdee39b6d5cc
| 0.618766 | 3.230614 | false | false | false | false |
fpga-logi/logi-hard
|
test_bench/wishbone_to_xil_fifo_tb.vhd
| 1 | 7,299 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:55:00 11/25/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/wishbone_to_xil_fifo_tb.vhd
-- Project Name: test_fifo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: wishbone_to_xil_fifo
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY wishbone_to_xil_fifo_tb IS
END wishbone_to_xil_fifo_tb;
ARCHITECTURE behavior OF wishbone_to_xil_fifo_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wishbone_to_xil_fifo
PORT(
gls_reset : IN std_logic;
gls_clk : IN std_logic;
wbs_address : IN std_logic_vector(15 downto 0);
wbs_writedata : IN std_logic_vector(15 downto 0);
wbs_readdata : OUT std_logic_vector(15 downto 0);
wbs_strobe : IN std_logic;
wbs_cycle : IN std_logic;
wbs_write : IN std_logic;
wbs_ack : OUT std_logic;
fifo_rst : OUT std_logic;
wr_clk : OUT std_logic;
dout : OUT std_logic_vector(15 downto 0);
wr_en : OUT std_logic;
full : IN std_logic;
wr_data_count : IN std_logic_vector(15 downto 0);
overflow : IN std_logic;
rd_clk : OUT std_logic;
din : IN std_logic_vector(15 downto 0);
rd_en : OUT std_logic;
empty : IN std_logic;
rd_data_count : IN std_logic_vector(15 downto 0);
underflow : IN std_logic
);
END COMPONENT;
COMPONENT xil_fifo
PORT(
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(127 downto 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(15 downto 0);
full : OUT std_logic;
overflow : OUT std_logic;
empty : OUT std_logic;
underflow : OUT std_logic;
rd_data_count : OUT std_logic_vector(9 downto 0);
wr_data_count : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
--Inputs
signal gls_reset : std_logic := '0';
signal gls_clk : std_logic := '0';
signal wbs_address : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_strobe : std_logic := '0';
signal wbs_cycle : std_logic := '0';
signal wbs_write : std_logic := '0';
signal full : std_logic := '0';
signal wr_data_count : std_logic_vector(15 downto 0) := (others => '0');
signal overflow : std_logic := '0';
signal din : std_logic_vector(15 downto 0) := (others => '0');
signal fifo_din : std_logic_vector(127 downto 0) := (others => '0');
signal empty : std_logic := '0';
signal rd_data_count : std_logic_vector(15 downto 0) := (others => '0');
signal underflow : std_logic := '0';
--Outputs
signal wbs_readdata : std_logic_vector(15 downto 0);
signal wbs_ack : std_logic;
signal fifo_rst : std_logic;
signal wr_clk : std_logic;
signal dout : std_logic_vector(15 downto 0);
signal wr_en : std_logic;
signal rd_clk : std_logic;
signal rd_en : std_logic;
-- Clock period definitions
constant gls_clk_period : time := 10 ns;
constant wr_clk_period : time := 10 ns;
constant rd_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: wishbone_to_xil_fifo PORT MAP (
gls_reset => gls_reset,
gls_clk => gls_clk,
wbs_address => wbs_address,
wbs_writedata => wbs_writedata,
wbs_readdata => wbs_readdata,
wbs_strobe => wbs_strobe,
wbs_cycle => wbs_cycle,
wbs_write => wbs_write,
wbs_ack => wbs_ack,
fifo_rst => fifo_rst,
wr_clk => wr_clk,
dout => open,
wr_en => open,
full => full,
wr_data_count => wr_data_count,
overflow => overflow,
rd_clk => rd_clk,
din => din,
rd_en => rd_en,
empty => empty,
rd_data_count => rd_data_count,
underflow => underflow
);
uut2: xil_fifo PORT MAP (
rst => fifo_rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => fifo_din,
wr_en => wr_en,
rd_en => rd_en,
dout => din,
full => full,
overflow => overflow,
empty => empty,
underflow => underflow,
rd_data_count => rd_data_count(9 downto 0),
wr_data_count => wr_data_count(9 downto 0)
);
rd_data_count(15 downto 10) <= (others => '0');
wr_data_count(15 downto 10) <= (others => '0');
-- Clock process definitions
gls_clk_process :process
begin
gls_clk <= '0';
wait for gls_clk_period/2;
gls_clk <= '1';
wait for gls_clk_period/2;
end process;
wr_clk_process :process
begin
wr_clk <= '0';
wait for wr_clk_period/2;
wr_clk <= '1';
wait for wr_clk_period/2;
end process;
rd_clk_process :process
begin
rd_clk <= '0';
wait for rd_clk_period/2;
rd_clk <= '1';
wait for rd_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wr_en <= '0' ;
wait until gls_reset = '0' ;
wait for wr_clk_period*10;
for i in 0 to 7 loop
wr_en <= '1' ;
fifo_din <= std_logic_vector(to_unsigned(i, 128));
wait for wr_clk_period;
end loop ;
wr_en <= '0' ;
wait for wr_clk_period*10;
-- insert stimulus here
wait;
end process;
wish_stim_proc: process
begin
gls_reset <= '1' ;
wbs_address <= std_logic_vector(to_unsigned(0, 16));
wbs_writedata <= std_logic_vector(to_unsigned(0, 16));
wbs_strobe <= '0';
wbs_cycle <= '0';
wbs_write <= '0';
wait for wr_clk_period*10;
gls_reset <= '0' ;
wait for wr_clk_period*500;
for i in 0 to 100 loop
wbs_address <= std_logic_vector(to_unsigned(130, 16));
wbs_strobe <= '1';
wbs_cycle <= '1';
wait for wr_clk_period*4;
wbs_strobe <= '0';
wbs_cycle <= '0';
wait for wr_clk_period*10;
wbs_address <= std_logic_vector(to_unsigned(0, 16));
wbs_strobe <= '1';
wbs_cycle <= '1';
wait for wr_clk_period*4;
wbs_strobe <= '0';
wbs_cycle <= '0';
wait for wr_clk_period*10;
end loop ;
wait for wr_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
ed64b9c5b3576e06b15089e745ef70d9
| 0.560488 | 3.352779 | false | false | false | false |
miguelgarcia/sase2017-hls-video
|
hdmi_in_hls/repo/digilent/ip/clock_forwarder_1.0/hdl/clock_forwarder_v1_0_S00_AXI.vhd
| 3 | 15,001 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_forwarder_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end clock_forwarder_v1_0_S00_AXI;
architecture arch_imp of clock_forwarder_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
gpl-3.0
|
ad36f81b2dc8d3a5e6b6d8c7764153ca
| 0.618092 | 3.452474 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_idelayctrl.vhd
| 1 | 9,390 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2011-02-01 09:18:32 +0100 (di, 01 feb 2011) $
-- Revision : $Revision: 747 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity iserdes_idelayctrl is
generic (
NROF_DELAYCTRLS : integer;
IDELAYCLK_MULT : integer;
IDELAYCLK_DIV : integer;
GENIDELAYCLK : boolean
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
CLK200 : in std_logic;
idelay_ctrl_rdy : out std_logic
);
end entity iserdes_idelayctrl;
architecture syn of iserdes_idelayctrl is
constant ONES : std_logic_vector(NROF_DELAYCTRLS-1 downto 0) := (others => '1');
constant zeros : std_logic_vector(15 downto 0) := (others => '0');
constant zero : std_logic := '0';
signal idelay_ctrl_rdy_i : std_logic_vector(NROF_DELAYCTRLS-1 downto 0);
signal REF_CLK0 : std_logic;
signal REF_CLK180 : std_logic;
signal REF_CLK270 : std_logic;
signal REF_CLK2X : std_logic;
signal REF_CLK2X180 : std_logic;
signal REF_CLK90 : std_logic;
signal REF_CLKDV : std_logic;
signal REF_CLKFX : std_logic;
signal REF_CLKFX180 : std_logic;
signal REF_LOCKED : std_logic;
signal REF_CLKFB : std_logic;
signal REF_CLKIN : std_logic;
signal RESET_DELAYCTRL : std_logic;
signal REF_CLK : std_logic;
begin
gen_own_clk: if (GENIDELAYCLK = TRUE) generate
--needs bufg on feedback & output
ref_feedback_BUFG_inst : BUFG
port map (
O => REF_CLKFB, -- Clock buffer output
I => REF_CLK0 -- Clock buffer input
);
ref_out_BUFG_inst : BUFG
port map (
O => REF_CLK, -- Clock buffer output
I => REF_CLKFX -- Clock buffer input
);
REF_CLKIN <= CLOCK;
DCM_ADV_inst : DCM_ADV
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => IDELAYCLK_DIV, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => IDELAYCLK_MULT, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE, FIXED,
-- VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibration circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "HIGH", -- HIGH or LOW frequency mode for frequency synthesis
-- HIGH: 25MHz < CLKIN < 350MHz
-- : 140MHz < CLKFX < 350MHz
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-- HIGH or LOW frequency mode for frequency synthesis
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
SIM_DEVICE => "VIRTEX5", -- Set target device, "VIRTEX4" or "VIRTEX5"
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => REF_CLK0, -- 0 degree DCM CLK output
CLK180 => REF_CLK180, -- 180 degree DCM CLK output
CLK270 => REF_CLK270, -- 270 degree DCM CLK output
CLK2X => REF_CLK2X, -- 2X DCM CLK output
CLK2X180 => REF_CLK2X180, -- 2X, 180 degree DCM CLK out
CLK90 => REF_CLK90, -- 90 degree DCM CLK output
CLKDV => REF_CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => REF_CLKFX, -- DCM CLK synthesis out (M/D)
CLKFX180 => REF_CLKFX180, -- 180 degree CLK synthesis out
DO => open, -- 16-bit data output for Dynamic Reconfiguration Port (DRP)
DRDY => open, -- Ready output signal from the DRP
LOCKED => REF_LOCKED, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
CLKFB => REF_CLKFB, -- DCM clock feedback
CLKIN => REF_CLKIN, -- Clock input (from IBUFG, BUFG or DCM)
DADDR => zeros(6 downto 0), -- 7-bit address for the DRP
DCLK => zero, -- Clock for the DRP
DEN => zero, -- Enable input for the DRP
DI => zeros(15 downto 0), -- 16-bit data input for the DRP
DWE => zero, -- Active high allows for writing configuration memory
PSCLK => zero, -- Dynamic phase adjust clock input
PSEN => zero, -- Dynamic phase adjust enable input
PSINCDEC => zero, -- Dynamic phase adjust increment/decrement
RST => RESET -- DCM asynchronous reset input
);
RESET_DELAYCTRL <= not REF_LOCKED;
end generate;
use_ext_clk: if (GENIDELAYCLK = FALSE) generate
RESET_DELAYCTRL <= RESET;
REF_CLK <= CLK200;
end generate;
IDELAYCTRL_INST : for bnk_i in 0 to NROF_DELAYCTRLS-1 generate
u_idelayctrl : IDELAYCTRL
port map (
rdy => idelay_ctrl_rdy_i(bnk_i),
refclk => REF_CLK,
rst => RESET_DELAYCTRL
);
end generate IDELAYCTRL_INST;
idelay_ctrl_rdy <= '1' when (idelay_ctrl_rdy_i = ONES) else
'0';
end architecture syn;
|
gpl-3.0
|
048b0f9173c68a8d3c5a5576cac50262
| 0.484132 | 4.827763 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_ping.vhd
| 2 | 3,005 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:56:26 05/26/2014
-- Design Name:
-- Module Name: wishbone_ping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.control_pack.all ;
entity wishbone_ping is
generic( nb_ping : positive := 2;
clock_period_ns : integer := 10
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( 15 downto 0);
wbs_readdata : out std_logic_vector( 15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
ping_io : inout std_logic_vector(nb_ping-1 downto 0 )
);
end wishbone_ping;
architecture Behavioral of wishbone_ping is
type reg16_array is array (0 to (nb_ping-1)) of std_logic_vector(15 downto 0) ;
signal ping_regs : reg16_array ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal enable_reg : std_logic_vector(15 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
enable_reg <= wbs_writedata ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= ping_regs(conv_integer(wbs_address)) ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
gen_trigs_echo : for i in 0 to nb_ping-1 generate
pinger : ping_sensor
generic map(CLK_FREQ_NS => clock_period_ns)
port map(
clk => gls_clk,
reset => gls_reset,
ping_io => ping_io(i),
ping_enable => enable_reg(i),
state_debug => open,
echo_length => ping_regs(i),
echo_done_out => open,
timeout => open,
busy => open
);
end generate ;
end Behavioral;
|
lgpl-3.0
|
7d2e1c4a787ed493a1b2d8d58bfff490
| 0.583694 | 3.368834 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_hdmi_out_v1_05_a/hdl/vhdl/fmc_imageon_hdmi_out.vhd
| 1 | 11,403 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Aug 31, 2011
-- Design Name: FMC-IMAGEON
-- Module Name: fmc_imageon_hdmi_out.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Spartan-6, Virtex-6
-- Artix-7, Kintex-7, Virtex-7, Zynq
-- Avnet Boards: FMC-IMAGEON
--
-- Tool versions: ISE 13.4
--
-- Description: FMC-IMAGEON HDMI output interface.
--
-- Dependencies:
--
-- Revision: Aug 31, 2011: 1.01 Initial version
-- Nov 11, 2011: 1.02 Add logic to embed syncs
-- Add vblank/hblank ports
-- Remove vsync/hsync ports
-- Add embed_syncs port
-- Dec 05, 2011: 1.03 Place embed logic in sub-module
-- Feb 06, 2012: 1.04 Add IOB attribute to "FORCE"
-- Feb 21, 2012: 1.05 Add support for Zynq
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity fmc_imageon_hdmi_out is
Generic
(
C_DATA_WIDTH : integer := 16;
C_FAMILY : string := "virtex6"
);
Port
(
clk : in std_logic;
reset : in std_logic;
oe : in std_logic;
embed_syncs : in std_logic;
-- Audio Input Port
audio_spdif : in std_logic;
-- XSVI Input Port
xsvi_vblank_i : in std_logic;
xsvi_hblank_i : in std_logic;
-- xsvi_vsync_i : in std_logic;
-- xsvi_hsync_i : in std_logic;
xsvi_active_video_i : in std_logic;
xsvi_video_data_i : in std_logic_vector((C_DATA_WIDTH-1) downto 0);
-- I/O pins
io_hdmio_spdif : out std_logic;
io_hdmio_video : out std_logic_vector(15 downto 0);
io_hdmio_clk : out std_logic;
-- Debug Port
debug_o : out std_logic_vector(39 downto 0)
);
end fmc_imageon_hdmi_out;
architecture rtl of fmc_imageon_hdmi_out is
signal clk_n : std_logic;
signal net0 : std_logic;
signal net1 : std_logic;
signal oe_n : std_logic;
--
-- Input Delay
--
signal vblank_d : std_logic;
signal hblank_d : std_logic;
signal active_video_d : std_logic;
signal video_data_d : std_logic_vector((C_DATA_WIDTH-1) downto 0);
--
-- ADV7511 Embed Syncs
--
component adv7511_embed_syncs is
Port
(
clk : in std_logic;
reset : in std_logic;
-- Video Input
vblank_i : in std_logic;
hblank_i : in std_logic;
active_video_i : in std_logic;
video_data_i : in std_logic_vector(15 downto 0);
-- Video Output
video_data_o : out std_logic_vector(15 downto 0)
);
end component adv7511_embed_syncs;
signal video_data_es : std_logic_vector((C_DATA_WIDTH-1) downto 0);
--
-- Audio Port
--
signal spdif_r : std_logic;
--
-- Video Port
--
signal video_r : std_logic_vector(15 downto 0);
--
-- IOB Registers
--
signal hdmio_spdif_o : std_logic;
signal hdmio_video_o : std_logic_vector(15 downto 0);
signal hdmio_clk_o : std_logic;
signal hdmio_spdif_t : std_logic;
signal hdmio_video_t : std_logic_vector(15 downto 0);
signal hdmio_clk_t : std_logic;
attribute IOB : string;
attribute IOB of hdmio_spdif_o: signal is "FORCE";
attribute IOB of hdmio_video_o: signal is "FORCE";
attribute IOB of hdmio_clk_o : signal is "FORCE";
begin
clk_n <= not clk;
oe_n <= not oe;
net0 <= '0';
net1 <= '1';
--
-- Input Delay
--
input_delay_l : process (clk)
begin
if Rising_Edge(clk) then
vblank_d <= xsvi_vblank_i;
hblank_d <= xsvi_hblank_i;
active_video_d <= xsvi_active_video_i;
video_data_d <= xsvi_video_data_i;
end if;
end process;
--
-- ADV7511 Embed Syncs
--
embed_syncs_l : adv7511_embed_syncs
port map
(
clk => clk,
reset => reset,
-- Video Input
vblank_i => vblank_d,
hblank_i => hblank_d,
active_video_i => active_video_d,
video_data_i => video_data_d,
-- Video Output
video_data_o => video_data_es
);
--
-- Audio Port
--
spdif_r <= audio_spdif;
--
-- XSVI Port
--
XSVI_16BIT_GEN : if (C_DATA_WIDTH = 16) generate
xsvi_16bit_iregs_l : process (clk)
begin
if Rising_Edge(clk) then
if ( embed_syncs = '1' ) then
video_r <= video_data_es(15 downto 0);
else
video_r <= video_data_es(15 downto 0);
end if;
end if;
end process;
end generate XSVI_16BIT_GEN;
--
-- IOB Registers
--
io_oregs_l : process (clk)
begin
if Rising_Edge(clk) then
hdmio_spdif_o <= spdif_r;
hdmio_video_o <= video_r;
--
hdmio_spdif_t <= oe_n;
hdmio_video_t <= (others => oe_n);
end if;
end process;
S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate
ODDR_hdmio_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmio_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmio_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmio_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S3ADSP_GEN;
S6_GEN : if (C_FAMILY = "spartan6") generate
ODDR_hdmio_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmio_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmio_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmio_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6" or C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
ODDR_hdmio_clk_o : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmio_clk_o,
C => clk,
CE => net1,
D1 => net0,
D2 => net1,
R => net0,
S => net0);
ODDR_hdmio_clk_t : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmio_clk_t,
C => clk,
CE => net1,
D1 => oe_n,
D2 => oe_n,
R => net0,
S => net0);
end generate V6_GEN;
--
-- Tri-stateable outputs
-- Can be used to disable outputs to FMC connector
-- until FMC module is correctly identified.
--
OBUFT_hdmio_spdif : OBUFT
port map (
O => io_hdmio_spdif,
I => hdmio_spdif_o,
T => hdmio_spdif_t
);
IO1: for I in 0 to 15 generate
OBUFT_hdmio_video : OBUFT
port map (
O => io_hdmio_video(I),
I => hdmio_video_o(I),
T => hdmio_video_t(I)
);
end generate IO1;
OBUFT_hdmio_clk : OBUFT
port map (
O => io_hdmio_clk,
I => hdmio_clk_o,
T => hdmio_clk_t
);
--
-- Debug Port
-- Can be used to connect to ChipScope for debugging.
-- Having a port makes these signals accessible for debug via EDK.
--
debug_l : process (clk)
begin
if Rising_Edge(clk) then
debug_o(15 downto 0) <= video_r;
debug_o( 16) <= spdif_r;
debug_o( 17) <= '0';
debug_o( 18) <= '0';
debug_o( 19) <= embed_syncs;
debug_o(35 downto 20) <= video_data_d;
debug_o( 36) <= active_video_d;
debug_o( 37) <= hblank_d;
debug_o( 38) <= vblank_d;
debug_o( 39) <= '0';
end if;
end process;
end rtl;
|
gpl-3.0
|
d6011198d502b7889e0533ca2462be33
| 0.444269 | 3.773329 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_2/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg.vhd
| 1 | 11,931 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(19-1 DOWNTO 0);
DOUT : OUT std_logic_vector(19-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg;
|
gpl-3.0
|
d628099fb2247cd1b6fbdcb2dd4baaad
| 0.515464 | 3.832637 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/Mem_Ctrl_TB.vhd
| 2 | 4,318 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:34:53 05/09/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3_System/Mem_Ctrl_TB.vhd
-- Project Name: OZ-3_System
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Mem_Ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Mem_Ctrl_TB IS
END Mem_Ctrl_TB;
ARCHITECTURE behavior OF Mem_Ctrl_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Mem_Ctrl
PORT(
flash_address_from_OZ3 : IN std_logic_vector(22 downto 0);
dbl_clk_from_OZ3 : IN std_logic;
dRAM_WR_from_OZ3 : IN std_logic;
dRAM_address_from_OZ3 : IN std_logic_vector(22 downto 0);
dRAM_data_from_OZ3 : IN std_logic_vector(15 downto 0);
data_bus : IN std_logic_vector(15 downto 0);
dRAM_ce : OUT std_logic;
dRAM_lb : OUT std_logic;
dRAM_ub : OUT std_logic;
dRAM_adv : OUT std_logic;
dRAM_cre : OUT std_logic;
dRAM_clk : OUT std_logic;
flash_ce : OUT std_logic;
mem_oe : OUT std_logic;
mem_we : OUT std_logic;
address_bus : OUT std_logic_vector(22 downto 0);
dRAM_data_to_OZ3 : OUT std_logic_vector(15 downto 0);
instruction_to_OZ3 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal flash_address_from_OZ3 : std_logic_vector(22 downto 0) := (others => '0');
signal dbl_clk_from_OZ3 : std_logic := '0';
signal dRAM_WR_from_OZ3 : std_logic := '0';
signal dRAM_address_from_OZ3 : std_logic_vector(22 downto 0) := (others => '0');
signal dRAM_data_from_OZ3 : std_logic_vector(15 downto 0) := (others => '0');
signal data_bus : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal dRAM_ce : std_logic;
signal dRAM_lb : std_logic;
signal dRAM_ub : std_logic;
signal dRAM_adv : std_logic;
signal dRAM_cre : std_logic;
signal dRAM_clk : std_logic;
signal flash_ce : std_logic;
signal mem_oe : std_logic;
signal mem_we : std_logic;
signal address_bus : std_logic_vector(22 downto 0);
signal dRAM_data_to_OZ3 : std_logic_vector(15 downto 0);
signal instruction_to_OZ3 : std_logic_vector(15 downto 0);
-- Clock period definitions
constant dbl_clk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Mem_Ctrl PORT MAP (
flash_address_from_OZ3 => flash_address_from_OZ3,
dbl_clk_from_OZ3 => dbl_clk_from_OZ3,
dRAM_WR_from_OZ3 => dRAM_WR_from_OZ3,
dRAM_address_from_OZ3 => dRAM_address_from_OZ3,
dRAM_data_from_OZ3 => dRAM_data_from_OZ3,
data_bus => data_bus,
dRAM_ce => dRAM_ce,
dRAM_lb => dRAM_lb,
dRAM_ub => dRAM_ub,
dRAM_adv => dRAM_adv,
dRAM_cre => dRAM_cre,
dRAM_clk => dRAM_clk,
flash_ce => flash_ce,
mem_oe => mem_oe,
mem_we => mem_we,
address_bus => address_bus,
dRAM_data_to_OZ3 => dRAM_data_to_OZ3,
instruction_to_OZ3 => instruction_to_OZ3
);
-- Clock process definitions
dbl_clk_process :process
begin
dbl_clk_from_OZ3 <= '0';
wait for dbl_clk_period/2;
dbl_clk_from_OZ3 <= '1';
wait for dbl_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
|
mit
|
ce7c038aedb7ecbb08af6d1c5c0e1acd
| 0.57434 | 3.381363 | false | false | false | false |
miguelgarcia/sase2017-hls-video
|
hdmi_in_hls/repo/sase/hdl/vhdl/my_video_filter_line_buffers_val_1.vhd
| 2 | 4,625 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity my_video_filter_line_buffers_val_1_ram is
generic(
mem_type : string := "block";
dwidth : integer := 8;
awidth : integer := 13;
mem_size : integer := 5760
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of my_video_filter_line_buffers_val_1_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity my_video_filter_line_buffers_val_1 is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 5760;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of my_video_filter_line_buffers_val_1 is
component my_video_filter_line_buffers_val_1_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
my_video_filter_line_buffers_val_1_ram_U : component my_video_filter_line_buffers_val_1_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
|
gpl-3.0
|
dbcb622cd5c95531f5629cd68c184e27
| 0.539892 | 3.443783 | false | false | false | false |
mediocregopher/chdl
|
src/chdl_examples/gamma/basic.vhd
| 1 | 1,767 |
ENTITY fullAdder IS
PORT(a : in bit;
b : in bit;
cin : in bit;
s : out bit;
cout : out bit);
BEGIN
END ENTITY fullAdder;
ARCHITECTURE ARCH OF fullAdder IS
SIGNAL axorb : bit;
BEGIN
axorb <= (a xor b);
s <= (axorb xor cin);
cout <= ((axorb and cin) or (a and b));
END ARCHITECTURE fullAdder;
ENTITY main IS
PORT(a : in ARRAY(10#7# DOWNTO 10#0#) OF BIT;
b : in ARRAY(10#7# DOWNTO 10#0#) OF BIT;
s : out ARRAY(10#7# DOWNTO 10#0#) OF BIT;
cout : out BIT);
BEGIN
END ENTITY main;
ARCHITECTURE ARCH OF main IS
SIGNAL tmp : ARRAY(10#8# DOWNTO 10#0#) OF BIT;
BEGIN
tmp(0) <= '0';
cout <= tmp(8);
G__7999 : ENTITY fullAdder(ARCH) PORT MAP(a => a(0)
, b => b(0)
, cin => tmp(0)
, s => s(0)
, cout => tmp(1)
);
G__8000 : ENTITY fullAdder(ARCH) PORT MAP(a => a(1)
, b => b(1)
, cin => tmp(1)
, s => s(1)
, cout => tmp(2)
);
G__8001 : ENTITY fullAdder(ARCH) PORT MAP(a => a(2)
, b => b(2)
, cin => tmp(2)
, s => s(2)
, cout => tmp(3)
);
G__8002 : ENTITY fullAdder(ARCH) PORT MAP(a => a(3)
, b => b(3)
, cin => tmp(3)
, s => s(3)
, cout => tmp(4)
);
G__8003 : ENTITY fullAdder(ARCH) PORT MAP(a => a(4)
, b => b(4)
, cin => tmp(4)
, s => s(4)
, cout => tmp(5)
);
G__8004 : ENTITY fullAdder(ARCH) PORT MAP(a => a(5)
, b => b(5)
, cin => tmp(5)
, s => s(5)
, cout => tmp(6)
);
G__8005 : ENTITY fullAdder(ARCH) PORT MAP(a => a(6)
, b => b(6)
, cin => tmp(6)
, s => s(6)
, cout => tmp(7)
);
G__8006 : ENTITY fullAdder(ARCH) PORT MAP(a => a(7)
, b => b(7)
, cin => tmp(7)
, s => s(7)
, cout => tmp(8)
);
END ARCHITECTURE main;
|
epl-1.0
|
a2ab94bf71e9ab863378c9e9c0e5bca7
| 0.480475 | 2.748056 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd
| 1 | 5,073 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
de55326a84ee38c356a242eea8d758fd
| 0.542874 | 4.767857 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_64i_16o_k7.vhd
| 1 | 10,500 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file afifo_64i_16o_k7.vhd when simulating
-- the core, afifo_64i_16o_k7. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY afifo_64i_16o_k7 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END afifo_64i_16o_k7;
ARCHITECTURE afifo_64i_16o_k7_a OF afifo_64i_16o_k7 IS
-- synthesis translate_off
COMPONENT wrapped_afifo_64i_16o_k7
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_afifo_64i_16o_k7 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 12,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "4kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 4093,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 4092,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 14,
c_rd_depth => 16384,
c_rd_freq => 1,
c_rd_pntr_width => 14,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 12,
c_wr_depth => 4096,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 12,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_afifo_64i_16o_k7
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END afifo_64i_16o_k7_a;
|
gpl-3.0
|
93487622302d81fcf08ab42847b515f9
| 0.522667 | 3.322785 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_i2c_master.vhd
| 2 | 6,013 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:43:52 07/03/2014
-- Design Name:
-- Module Name: wishbone_i2c_master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- memory layout
--0x00 : read/write fifo
--0x01r : status register (bit 0 is nacked)
--0x01w : control register (bit 0 is reset and bit 1 is enable)
entity wishbone_i2c_master is
generic(
wb_size : natural := 16 -- data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
scl, sda : inout std_logic
);
end wishbone_i2c_master;
architecture Behavioral of wishbone_i2c_master is
component i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(
clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
signal status_register, control_register, decoded_read : std_logic_vector(15 downto 0);
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- i2c control signals
signal i2c_write, i2c_ack, i2c_nack, i2c_busy, i2c_nacked, i2c_ack_old, i2c_ack_re, i2c_reset, i2c_enable: std_logic ;
signal slave_addr : std_logic_vector(6 downto 0);
-- fifo control register
signal write_fifo_pop, write_fifo_push, write_fifo_empty, write_fifo_reset : std_logic ;
signal write_fifo_in, write_fifo_out : std_logic_vector(7 downto 0);
signal read_fifo_pop, read_fifo_push, read_fifo_empty, read_fifo_reset : std_logic ;
signal read_fifo_in, read_fifo_out : std_logic_vector(7 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
control_register <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '0' then
write_ack <= '1';
elsif ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '1' then
control_register <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
--status_register <= (others => '0');
elsif rising_edge(gls_clk) then
wbs_readdata <= decoded_read ; -- this is not clear if this should only happen in the read part
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
decoded_read <= status_register when wbs_address(0) = '1' else
X"00" & read_fifo_out ;
slave_addr <= control_register(15 downto 9) ;
write_fifo_in <= wbs_writedata(7 downto 0);
write_fifo_push <= (not write_ack) and (wbs_strobe and wbs_write and wbs_cycle) and not wbs_address(0);
write_fifo : small_fifo generic map( WIDTH => 8 , DEPTH => 8)
port map(
clk => gls_clk, resetn =>(not write_fifo_reset),
push => write_fifo_push,
pop => write_fifo_pop,
full => open,
empty => write_fifo_empty,
limit => open,
data_in => write_fifo_in,
data_out => write_fifo_out
);
i2c_reset <= control_register(0);
i2c_enable <= control_register(1);
status_register(1) <= i2c_nacked ;
status_register(0) <= i2c_busy ;
status_register(15 downto 2) <= (others => '0');
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
i2c_ack_old <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
i2c_ack_old <= i2c_ack ;
if i2c_nack = '1' then
i2c_nacked <= '1' ;
elsif i2c_reset = '1' then
i2c_nacked <= '0' ;
end if ;
end if ;
end process ;
i2c_ack_re <= i2c_ack and (not i2c_ack_old) ;
write_fifo_pop <= i2c_ack_re ;
write_fifo_reset <= i2c_nack or i2c_reset;
i2c_write <= '1' when i2c_enable = '1' and write_fifo_empty = '0' else
'0' ;
i2c_master_ctrl : i2c_master
generic map(i2c_freq_hz => 100_000,
clk_freq_hz => 100_000_000)
port map(
clk => gls_clk,
reset => gls_reset,
slave_addr => slave_addr,
data_in => write_fifo_out,
i2c_read => '0',
i2c_write => i2c_write,
scl => scl,
sda => sda,
data_out => open,
new_data => open,
ack => i2c_ack,
nack => i2c_nack,
busy => i2c_busy
);
end Behavioral;
|
lgpl-3.0
|
4dc7e99cb7efd576ff2fe2e207eb1715
| 0.605521 | 2.987084 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/Input_Port_MUX.vhd
| 2 | 1,322 |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Input_Port_MUX
--Module Description:
-- This module is a simple 4x32 multiplexer to extend the input ports of the
-- OZ-3.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Input_Port_MUX is
Port ( input0 : in STD_LOGIC_VECTOR (31 downto 0);
input1 : in STD_LOGIC_VECTOR (31 downto 0);
input2 : in STD_LOGIC_VECTOR (31 downto 0);
input3 : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (31 downto 0));
end Input_Port_MUX;
architecture Behavioral of Input_Port_MUX is
begin
main: process(input0, input1, input2, input3, sel)
begin
if sel = b"00" then
output <= input0;
elsif sel = b"01" then
output <= input1;
elsif sel = b"10" then
output <= input2;
elsif sel = b"11" then
output <= input3;
end if;
end process;
end Behavioral;
|
mit
|
e08f1fe42e6e62e25ef6973ca752d66c
| 0.557489 | 3.582656 | false | false | false | false |
CprE488/Final
|
system/hdl/system_v_tc_vid_out_0_wrapper.vhd
| 1 | 10,199 |
-------------------------------------------------------------------------------
-- system_v_tc_vid_out_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_01_a.all;
entity system_v_tc_vid_out_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_v_tc_vid_out_0_wrapper : entity is "v_tc_v5_01_a";
end system_v_tc_vid_out_0_wrapper;
architecture STRUCTURE of system_v_tc_vid_out_0_wrapper is
component v_tc is
generic (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_AUTO_SWITCH : integer;
C_MAX_PIXELS : integer;
C_MAX_LINES : integer;
C_NUM_FSYNCS : integer;
C_DETECT_EN : integer;
C_GENERATE_EN : integer;
C_DET_HSYNC_EN : integer;
C_DET_VSYNC_EN : integer;
C_DET_HBLANK_EN : integer;
C_DET_VBLANK_EN : integer;
C_DET_AVIDEO_EN : integer;
C_DET_ACHROMA_EN : integer;
C_GEN_HSYNC_EN : integer;
C_GEN_VSYNC_EN : integer;
C_GEN_HBLANK_EN : integer;
C_GEN_VBLANK_EN : integer;
C_GEN_AVIDEO_EN : integer;
C_GEN_ACHROMA_EN : integer;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_CPARITY : integer;
C_SYNC_EN : integer;
C_GEN_VBLANK_POLARITY : integer;
C_GEN_HBLANK_POLARITY : integer;
C_GEN_VSYNC_POLARITY : integer;
C_GEN_HSYNC_POLARITY : integer;
C_GEN_AVIDEO_POLARITY : integer;
C_GEN_ACHROMA_POLARITY : integer;
C_GEN_VACTIVE_SIZE : integer;
C_GEN_HACTIVE_SIZE : integer;
C_GEN_HFRAME_SIZE : integer;
C_GEN_F0_VFRAME_SIZE : integer;
C_GEN_HSYNC_START : integer;
C_GEN_HSYNC_END : integer;
C_GEN_F0_VBLANK_HSTART : integer;
C_GEN_F0_VBLANK_HEND : integer;
C_GEN_F0_VSYNC_VSTART : integer;
C_GEN_F0_VSYNC_VEND : integer;
C_GEN_F0_VSYNC_HSTART : integer;
C_GEN_F0_VSYNC_HEND : integer;
C_FSYNC_HSTART0 : integer;
C_FSYNC_VSTART0 : integer;
C_FSYNC_HSTART1 : integer;
C_FSYNC_VSTART1 : integer;
C_FSYNC_HSTART2 : integer;
C_FSYNC_VSTART2 : integer;
C_FSYNC_HSTART3 : integer;
C_FSYNC_VSTART3 : integer;
C_FSYNC_HSTART4 : integer;
C_FSYNC_VSTART4 : integer;
C_FSYNC_HSTART5 : integer;
C_FSYNC_VSTART5 : integer;
C_FSYNC_HSTART6 : integer;
C_FSYNC_VSTART6 : integer;
C_FSYNC_HSTART7 : integer;
C_FSYNC_VSTART7 : integer;
C_FSYNC_HSTART8 : integer;
C_FSYNC_VSTART8 : integer;
C_FSYNC_HSTART9 : integer;
C_FSYNC_VSTART9 : integer;
C_FSYNC_HSTART10 : integer;
C_FSYNC_VSTART10 : integer;
C_FSYNC_HSTART11 : integer;
C_FSYNC_VSTART11 : integer;
C_FSYNC_HSTART12 : integer;
C_FSYNC_VSTART12 : integer;
C_FSYNC_HSTART13 : integer;
C_FSYNC_VSTART13 : integer;
C_FSYNC_HSTART14 : integer;
C_FSYNC_VSTART14 : integer;
C_FSYNC_HSTART15 : integer;
C_FSYNC_VSTART15 : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(C_NUM_FSYNCS-1 to 0)
);
end component;
begin
v_tc_vid_out_0 : v_tc
generic map (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_AUTO_SWITCH => 1,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_DETECT_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_VIDEO_FORMAT => 0,
C_GEN_CPARITY => 0,
C_SYNC_EN => 1,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VACTIVE_SIZE => 720,
C_GEN_HACTIVE_SIZE => 1280,
C_GEN_HFRAME_SIZE => 1650,
C_GEN_F0_VFRAME_SIZE => 750,
C_GEN_HSYNC_START => 1390,
C_GEN_HSYNC_END => 1430,
C_GEN_F0_VBLANK_HSTART => 1280,
C_GEN_F0_VBLANK_HEND => 1280,
C_GEN_F0_VSYNC_VSTART => 724,
C_GEN_F0_VSYNC_VEND => 729,
C_GEN_F0_VSYNC_HSTART => 1280,
C_GEN_F0_VSYNC_HEND => 1280,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
port map (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aclken => s_axi_aclken,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
intc_if => intc_if,
clk => clk,
resetn => resetn,
clken => clken,
det_clken => det_clken,
gen_clken => gen_clken,
fsync_in => fsync_in,
vblank_in => vblank_in,
vsync_in => vsync_in,
hblank_in => hblank_in,
hsync_in => hsync_in,
active_video_in => active_video_in,
active_chroma_in => active_chroma_in,
vblank_out => vblank_out,
vsync_out => vsync_out,
hblank_out => hblank_out,
hsync_out => hsync_out,
active_video_out => active_video_out,
active_chroma_out => active_chroma_out,
fsync_out => fsync_out
);
end architecture STRUCTURE;
|
gpl-3.0
|
c66f293d655ad514da80521490aa958f
| 0.569075 | 2.989156 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_interface_s6.vhd
| 1 | 9,001 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2012 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Apr 23, 2012
-- Design Name: FMC-IMAGEON
-- Module Name: iserdes_interface_s6.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Spartan 6
-- Avnet Boards: FMC-IMAGEON
-- Tool versions: ISE 13.4
-- Description: Spartan 6 10:1 iSerDes Top
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
library work;
use work.all;
library unisim;
use unisim.vcomponents.all;
entity iserdes_interface_s6 is
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- serdes clock, directly connected to bondpads
SCLKP : in std_logic;
SCLKN : in std_logic;
-- serdes data, directly connected to bondpads
SDATAP : in std_logic_vector(4 downto 0);
SDATAN : in std_logic_vector(4 downto 0);
-- control
ALIGN_START : in std_logic;
FIFO_EN : in std_logic;
TRAINING : in std_logic_vector(9 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
-- status
PLL_LOCKED : out std_logic;
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
-- parallel data out
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector(49 downto 0)
);
end iserdes_interface_s6;
architecture rtl of iserdes_interface_s6 is
component iserdes_datadeser_s6 is
port (
RESET : in std_logic;
CLOCK : in std_logic;
PCLK01x : in std_logic;
PCLK02x : in std_logic;
PCLK10x : in std_logic;
STROBE : in std_logic;
SDATAP : in std_logic;
SDATAN : in std_logic;
ALIGN_START : in std_logic;
FIFO_EN : in std_logic;
TRAINING : in std_logic_vector(9 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector(9 downto 0)
);
end component;
signal RXCLKINT : std_logic;
signal RXCLK : std_logic;
signal PLL_CLKFBOUT : std_logic;
signal PLL_CLKOUT0 : std_logic;
signal PLL_CLKOUT1 : std_logic;
signal PLL_CLKOUT2 : std_logic;
signal PLL_LOCKED_i : std_logic;
signal PCLK01x : std_logic;
signal PCLK02x : std_logic;
signal PCLK10x : std_logic;
signal BUFPLL_LOCKED : std_logic;
signal SERDES_STROBE : std_logic;
signal SERDES_RESET : std_logic;
signal ALIGN_BUSY_i : std_logic_vector(4 downto 0);
signal ALIGNED_i : std_logic_vector(4 downto 0);
signal FIFO_EMPTY_i : std_logic_vector(4 downto 0);
begin
-- Signal Assignment
PLL_LOCKED <= PLL_LOCKED_i;
SERDES_RESET <= not BUFPLL_LOCKED;
-- Electrical I/O Interface
IBUFDS_RXCLK : IBUFDS
generic map (
IOSTANDARD => "TMDS_33" ,
DIFF_TERM => FALSE
)
port map (
I => SCLKP ,
IB => SCLKN ,
O => RXCLKINT
);
BUFIO2_RXCLK : BUFIO2
generic map (
DIVIDE_BYPASS => TRUE ,
DIVIDE => 1
)
port map (
I => RXCLKINT ,
SERDESSTROBE => open ,
IOCLK => open ,
DIVCLK => RXCLK
);
-- PLL
PLL_BASE_ISERDES : PLL_BASE
generic map (
CLKIN_PERIOD => 5.0 ,
CLKFBOUT_MULT => 2 , -- DDR CLK
CLKOUT0_DIVIDE => 1 , -- 2x DDR CLK 10x CLKIN
CLKOUT1_DIVIDE => 10 , -- 5/ DDR CLK 1x CLKIN
CLKOUT2_DIVIDE => 5 , -- 2.5/ DDR CLK 2x CLKIN
COMPENSATION => "INTERNAL"
)
port map
(
CLKFBOUT => PLL_CLKFBOUT ,
CLKOUT0 => PLL_CLKOUT0 ,
CLKOUT1 => PLL_CLKOUT1 ,
CLKOUT2 => PLL_CLKOUT2 ,
CLKOUT3 => open ,
CLKOUT4 => open ,
CLKOUT5 => open ,
LOCKED => PLL_LOCKED_i ,
CLKFBIN => PLL_CLKFBOUT ,
CLKIN => RXCLK ,
RST => RESET
);
-- Clock Buffers
BUFG_PCLK01x : BUFG
port map (
I => PLL_CLKOUT1 ,
O => PCLK01x
);
BUFG_PCLK02x : BUFG
port map (
I => PLL_CLKOUT2 ,
O => PCLK02x
);
BUFPLL_PCLK10x : BUFPLL
generic map (
DIVIDE => 5
)
port map (
PLLIN => PLL_CLKOUT0 ,
GCLK => PCLK02x ,
LOCKED => PLL_LOCKED_i ,
IOCLK => PCLK10x ,
SERDESSTROBE => SERDES_STROBE ,
LOCK => BUFPLL_LOCKED
);
SERDESPATHGEN: for i in 0 to 4 generate
ISERDES_DATADESER_PATH : iserdes_datadeser_s6
port map (
RESET => SERDES_RESET ,
CLOCK => CLOCK ,
PCLK01x => PCLK01x ,
PCLK02x => PCLK02x ,
PCLK10x => PCLK10x ,
STROBE => SERDES_STROBE ,
SDATAP => SDATAP(i) ,
SDATAN => SDATAN(i) ,
ALIGN_START => ALIGN_START ,
FIFO_EN => FIFO_EN ,
TRAINING => TRAINING ,
MANUAL_TAP => MANUAL_TAP ,
ALIGN_BUSY => ALIGN_BUSY_i(i) ,
ALIGNED => ALIGNED_i(i) ,
FIFO_RDEN => FIFO_RDEN ,
FIFO_EMPTY => FIFO_EMPTY_i(i) ,
FIFO_DATAOUT => FIFO_DATAOUT(((i * 10) + 9) downto (i * 10))
);
end generate;
process (ALIGN_BUSY_i)
variable TEMP : std_logic;
begin
TEMP := '0';
for i in ALIGN_BUSY_i'low to ALIGN_BUSY_i'high loop
TEMP := TEMP or ALIGN_BUSY_i(i);
end loop;
ALIGN_BUSY <= TEMP;
end process;
process (ALIGNED_i)
variable TEMP : std_logic;
begin
TEMP := '1';
for i in ALIGNED_i'low to ALIGNED_i'high loop
TEMP := TEMP and ALIGNED_i(i);
end loop;
ALIGNED <= TEMP;
end process;
process (FIFO_EMPTY_i)
variable TEMP : std_logic;
begin
TEMP := '0';
for i in FIFO_EMPTY_i'low to FIFO_EMPTY_i'high loop
TEMP := TEMP or FIFO_EMPTY_i(i);
end loop;
FIFO_EMPTY <= TEMP;
end process;
end rtl;
|
gpl-3.0
|
132bc565cdba2f712fd62d751b68b558
| 0.417398 | 4.321171 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/hold.vhd
| 2 | 1,988 |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hold is
generic(HOLD_TIME : positive := 4; HOLD_LEVEL : std_logic := '1');
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
input: in STD_LOGIC;
output: out STD_LOGIC;
holding : out std_logic
);
end hold;
architecture Behavioral of hold is
signal Qp : unsigned(nbit(HOLD_TIME) - 1 downto 0) := (others => '0');
signal old_value : std_logic ;
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
Qp <= (others => '0') ;
elsif Qp = 0 then
if old_value /= input and input = HOLD_LEVEL then
Qp <= to_unsigned(HOLD_TIME - 1, nbit(HOLD_TIME)) ;
end if;
old_value <= input ;
else
Qp <= Qp - 1;
end if;
end if;
end process;
output <= input when Qp = 0 else
old_value ;
holding <= '0' when Qp = 0 else
'1' ;
end Behavioral;
|
lgpl-3.0
|
82b77af992b142869a86867a55a60b0f
| 0.561368 | 3.512367 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/fifo_bt_txd/fifo_bt_txd_sim_netlist.vhdl
| 1 | 238,552 |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Tue Aug 15 10:43:42 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/fifo_bt_txd/fifo_bt_txd_sim_netlist.vhdl
-- Design : fifo_bt_txd
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_bt_txd_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_bt_txd_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => Q(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DIADI(15 downto 12) => B"0000",
DIADI(11 downto 8) => din(7 downto 4),
DIADI(7 downto 4) => B"0000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_19\,
DOBDO(11 downto 8) => D(7 downto 4),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_27\,
DOBDO(3 downto 0) => D(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => SR(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_compare : entity is "compare";
end fifo_bt_txd_compare;
architecture STRUCTURE of fifo_bt_txd_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_compare_3 is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_compare_3 : entity is "compare";
end fifo_bt_txd_compare_3;
architecture STRUCTURE of fifo_bt_txd_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55550400"
)
port map (
I0 => wr_rst_busy,
I1 => comp2,
I2 => \out\,
I3 => wr_en,
I4 => comp1,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_compare_4 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_compare_4 : entity is "compare";
end fifo_bt_txd_compare_4;
architecture STRUCTURE of fifo_bt_txd_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BABBBBBBAAAAAAAA"
)
port map (
I0 => comp0,
I1 => \out\,
I2 => rd_en,
I3 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I4 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I5 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_compare_5 : entity is "compare";
end fifo_bt_txd_compare_5;
architecture STRUCTURE of fifo_bt_txd_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_bt_txd_rd_bin_cntr;
architecture STRUCTURE of fifo_bt_txd_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \out\(0),
D => plusOp(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_rd_fwft is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_rd_fwft : entity is "rd_fwft";
end fifo_bt_txd_rd_fwft;
architecture STRUCTURE of fifo_bt_txd_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
empty <= empty_fwft_i;
\out\(1 downto 0) <= curr_fwft_state(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABBBBBB"
)
port map (
I0 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
I3 => curr_fwft_state(1),
I4 => curr_fwft_state(0),
O => tmp_ram_rd_en
);
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFCB8000"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => ram_empty_fb_i_reg,
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => aempty_fwft_i0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_i,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_o_i,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => empty_fwft_i
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => rd_en,
I2 => curr_fwft_state(1),
I3 => curr_fwft_state(0),
O => \gc0.count_d1_reg[9]\(0)
);
\goreg_bm.dout_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
D => next_fwft_state(0),
Q => user_valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_synchronizer_ff : entity is "synchronizer_ff";
end fifo_bt_txd_synchronizer_ff;
architecture STRUCTURE of fifo_bt_txd_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_bt_txd_synchronizer_ff_0;
architecture STRUCTURE of fifo_bt_txd_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_bt_txd_synchronizer_ff_1;
architecture STRUCTURE of fifo_bt_txd_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_bt_txd_synchronizer_ff_2;
architecture STRUCTURE of fifo_bt_txd_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_bt_txd_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_bt_txd_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \fifo_bt_txd_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \fifo_bt_txd_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_bt_txd_synchronizer_ff__parameterized0_6\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_bt_txd_synchronizer_ff__parameterized0_6\ : entity is "synchronizer_ff";
end \fifo_bt_txd_synchronizer_ff__parameterized0_6\;
architecture STRUCTURE of \fifo_bt_txd_synchronizer_ff__parameterized0_6\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_bt_txd_synchronizer_ff__parameterized0_7\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_bt_txd_synchronizer_ff__parameterized0_7\ : entity is "synchronizer_ff";
end \fifo_bt_txd_synchronizer_ff__parameterized0_7\;
architecture STRUCTURE of \fifo_bt_txd_synchronizer_ff__parameterized0_7\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_bt_txd_synchronizer_ff__parameterized0_8\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_bt_txd_synchronizer_ff__parameterized0_8\ : entity is "synchronizer_ff";
end \fifo_bt_txd_synchronizer_ff__parameterized0_8\;
architecture STRUCTURE of \fifo_bt_txd_synchronizer_ff__parameterized0_8\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_wr_bin_cntr is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_bt_txd_wr_bin_cntr;
architecture STRUCTURE of fifo_bt_txd_wr_bin_cntr is
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair12";
begin
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
I4 => wr_pntr_plus2(4),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
I5 => wr_pntr_plus2(5),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
I2 => wr_pntr_plus2(7),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => wr_pntr_plus2(7),
I3 => wr_pntr_plus2(8),
O => \plusOp__0\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(7),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => wr_pntr_plus2(6),
I3 => wr_pntr_plus2(8),
I4 => wr_pntr_plus2(9),
O => \plusOp__0\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus2(5),
I1 => wr_pntr_plus2(3),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => wr_pntr_plus2(2),
I5 => wr_pntr_plus2(4),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_13_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_13_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_13_out(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(4),
Q => p_13_out(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(5),
Q => p_13_out(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(6),
Q => p_13_out(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(7),
Q => p_13_out(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(8),
Q => p_13_out(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => Q(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => Q(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => Q(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => Q(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(4),
Q => Q(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(5),
Q => Q(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(6),
Q => Q(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(7),
Q => Q(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(8),
Q => Q(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => Q(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => wr_pntr_plus2(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => wr_pntr_plus2(9)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(0),
I1 => RD_PNTR_WR(0),
I2 => p_13_out(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(2),
I1 => RD_PNTR_WR(2),
I2 => p_13_out(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => RD_PNTR_WR(2),
I2 => wr_pntr_plus2(3),
I3 => RD_PNTR_WR(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(4),
I1 => RD_PNTR_WR(4),
I2 => p_13_out(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => RD_PNTR_WR(4),
I2 => wr_pntr_plus2(5),
I3 => RD_PNTR_WR(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(6),
I1 => RD_PNTR_WR(6),
I2 => p_13_out(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => RD_PNTR_WR(6),
I2 => wr_pntr_plus2(7),
I3 => RD_PNTR_WR(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(8),
I1 => RD_PNTR_WR(8),
I2 => p_13_out(9),
I3 => RD_PNTR_WR(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => RD_PNTR_WR(8),
I2 => wr_pntr_plus2(9),
I3 => RD_PNTR_WR(9),
O => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_bt_txd_blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_bt_txd_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_bt_txd_blk_mem_gen_prim_wrapper
port map (
D(7 downto 0) => D(7 downto 0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_bt_txd_clk_x_pntrs;
architecture STRUCTURE of fifo_bt_txd_clk_x_pntrs is
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc0.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\fifo_bt_txd_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\fifo_bt_txd_synchronizer_ff__parameterized0_6\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\fifo_bt_txd_synchronizer_ff__parameterized0_7\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\fifo_bt_txd_synchronizer_ff__parameterized0_8\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => RD_PNTR_WR(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => RD_PNTR_WR(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => RD_PNTR_WR(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => RD_PNTR_WR(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => RD_PNTR_WR(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => RD_PNTR_WR(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => RD_PNTR_WR(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => RD_PNTR_WR(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => RD_PNTR_WR(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => RD_PNTR_WR(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_bt_txd_rd_status_flags_as;
architecture STRUCTURE of fifo_bt_txd_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
c0: entity work.fifo_bt_txd_compare_4
port map (
comp1 => comp1,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.fifo_bt_txd_compare_5
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_bt_txd_reset_blk_ramfifo;
architecture STRUCTURE of fifo_bt_txd_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
wr_rst_busy <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.fifo_bt_txd_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.fifo_bt_txd_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.fifo_bt_txd_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.fifo_bt_txd_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_bt_txd_wr_status_flags_as;
architecture STRUCTURE of fifo_bt_txd_wr_status_flags_as is
signal c2_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.fifo_bt_txd_compare
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.fifo_bt_txd_compare_3
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c2_n_0,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_0,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_bt_txd_blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_bt_txd_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_bt_txd_blk_mem_gen_prim_width
port map (
D(7 downto 0) => D(7 downto 0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_rd_logic is
port (
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_rd_logic : entity is "rd_logic";
end fifo_bt_txd_rd_logic;
architecture STRUCTURE of fifo_bt_txd_rd_logic is
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_2_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
begin
\gr1.gr1_int.rfwft\: entity work.fifo_bt_txd_rd_fwft
port map (
E(0) => E(0),
empty => empty,
\gc0.count_d1_reg[9]\(0) => p_7_out,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0) => \out\(1 downto 0),
\out\(1) => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => p_0_in(0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gras.rsts\: entity work.fifo_bt_txd_rd_status_flags_as
port map (
\gpregsm1.curr_fwft_state_reg[1]\(1) => \gr1.gr1_int.rfwft_n_0\,
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_0_in(0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.fifo_bt_txd_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => p_7_out,
Q(9 downto 0) => Q(9 downto 0),
\out\(0) => \out\(1),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_wr_logic is
port (
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst_busy : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_wr_logic : entity is "wr_logic";
end fifo_bt_txd_wr_logic;
architecture STRUCTURE of fifo_bt_txd_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwas.wsts\: entity work.fifo_bt_txd_wr_status_flags_as
port map (
E(0) => \^wea\(0),
full => full,
\out\ => \out\,
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c2/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.fifo_bt_txd_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_bt_txd_blk_mem_gen_top;
architecture STRUCTURE of fifo_bt_txd_blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_bt_txd_blk_mem_gen_generic_cstr
port map (
D(7 downto 0) => D(7 downto 0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_blk_mem_gen_v8_3_6_synth is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_blk_mem_gen_v8_3_6_synth : entity is "blk_mem_gen_v8_3_6_synth";
end fifo_bt_txd_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of fifo_bt_txd_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.fifo_bt_txd_blk_mem_gen_top
port map (
D(7 downto 0) => D(7 downto 0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_blk_mem_gen_v8_3_6 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_v8_3_6";
end fifo_bt_txd_blk_mem_gen_v8_3_6;
architecture STRUCTURE of fifo_bt_txd_blk_mem_gen_v8_3_6 is
begin
inst_blk_mem_gen: entity work.fifo_bt_txd_blk_mem_gen_v8_3_6_synth
port map (
D(7 downto 0) => D(7 downto 0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_memory is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_memory : entity is "memory";
end fifo_bt_txd_memory;
architecture STRUCTURE of fifo_bt_txd_memory is
signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.fifo_bt_txd_blk_mem_gen_v8_3_6
port map (
D(7 downto 0) => doutb(7 downto 0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
WEA(0) => WEA(0),
din(7 downto 0) => din(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(0),
Q => dout(0),
R => SR(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(1),
Q => dout(1),
R => SR(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(2),
Q => dout(2),
R => SR(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(3),
Q => dout(3),
R => SR(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(4),
Q => dout(4),
R => SR(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(5),
Q => dout(5),
R => SR(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(6),
Q => dout(6),
R => SR(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => doutb(7),
Q => dout(7),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_bt_txd_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_bt_txd_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_bt_txd_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
Q(9 downto 0) => p_0_out(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
rd_clk => rd_clk,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_bt_txd_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_0_out(9 downto 0),
E(0) => p_5_out,
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
empty => empty,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_bt_txd_wr_logic
port map (
AR(0) => wr_rst_i(1),
Q(9 downto 0) => p_12_out(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
full => full,
\out\ => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.fifo_bt_txd_memory
port map (
E(0) => p_5_out,
Q(9 downto 0) => p_12_out(9 downto 0),
SR(0) => rd_rst_i(0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.fifo_bt_txd_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
rd_clk => rd_clk,
rst => rst,
wr_clk => wr_clk,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_fifo_generator_top : entity is "fifo_generator_top";
end fifo_bt_txd_fifo_generator_top;
architecture STRUCTURE of fifo_bt_txd_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_bt_txd_fifo_generator_ramfifo
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_fifo_generator_v13_1_4_synth is
port (
wr_rst_busy : out STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_fifo_generator_v13_1_4_synth : entity is "fifo_generator_v13_1_4_synth";
end fifo_bt_txd_fifo_generator_v13_1_4_synth;
architecture STRUCTURE of fifo_bt_txd_fifo_generator_v13_1_4_synth is
begin
\gconvfifo.rf\: entity work.fifo_bt_txd_fifo_generator_top
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd_fifo_generator_v13_1_4 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_bt_txd_fifo_generator_v13_1_4 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_bt_txd_fifo_generator_v13_1_4 : entity is "fifo_generator_v13_1_4";
end fifo_bt_txd_fifo_generator_v13_1_4;
architecture STRUCTURE of fifo_bt_txd_fifo_generator_v13_1_4 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_bt_txd_fifo_generator_v13_1_4_synth
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_bt_txd is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_bt_txd : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_bt_txd : entity is "fifo_bt_txd,fifo_generator_v13_1_4,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_bt_txd : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_bt_txd : entity is "fifo_generator_v13_1_4,Vivado 2017.1";
end fifo_bt_txd;
architecture STRUCTURE of fifo_bt_txd is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1022;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.fifo_bt_txd_fifo_generator_v13_1_4
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
7ab5c523ff19961695438969c875c610
| 0.605851 | 2.845324 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/virtual_instrument/logi_virtual_components_pack.vhd
| 2 | 3,945 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package logi_virtual_components_pack is
component logi_virtual_sw is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
sw : out std_logic_vector(15 downto 0)
);
end component;
component logi_virtual_pb is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
pb : out std_logic_vector(15 downto 0)
);
end component;
component logi_virtual_led is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
led : in std_logic_vector(15 downto 0)
);
end component;
component logi_virtual_7seg is
generic(
wb_size : natural := 16 ;-- Data port size for wishbone
fade_cycle : positive := 3_600_000
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
cathodes : in std_logic_vector(7 downto 0); -- common cathode
anodes : in std_logic_vector(7 downto 0)
);
end component;
end logi_virtual_components_pack;
package body logi_virtual_components_pack is
end logi_virtual_components_pack;
|
lgpl-3.0
|
985b2f37657b701761c0dcd2ac8a9418
| 0.618251 | 3.649399 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/OZ3_TB.vhd
| 2 | 4,505 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:19:49 05/08/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3_System/OZ3_TB.vhd
-- Project Name: OZ-3_System
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: OZ3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY OZ3_TB IS
END OZ3_TB;
ARCHITECTURE behavior OF OZ3_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OZ3
PORT(
main_clock : IN std_logic;
dbl_clock : IN std_logic;
inv_clock : IN std_logic;
reset : IN std_logic;
input_pins : IN std_logic_vector(15 downto 0);
input_port : IN std_logic_vector(31 downto 0);
instruction_in : IN std_logic_vector(15 downto 0);
dRAM_data_in : IN std_logic_vector(15 downto 0);
output_pins : OUT std_logic_vector(15 downto 0);
output_port : OUT std_logic_vector(31 downto 0);
instruction_addr_out : OUT std_logic_vector(22 downto 0);
dRAM_data_out : OUT std_logic_vector(15 downto 0);
dRAM_addr_out : OUT std_logic_vector(22 downto 0);
dRAM_WR_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal main_clock : std_logic := '0';
signal dbl_clock : std_logic := '0';
signal inv_clock : std_logic := '0';
signal reset : std_logic := '0';
signal input_pins : std_logic_vector(15 downto 0) := (others => '0');
signal input_port : std_logic_vector(31 downto 0) := (others => '0');
signal instruction_in : std_logic_vector(15 downto 0) := (others => '0');
signal dRAM_data_in : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal output_pins : std_logic_vector(15 downto 0);
signal output_port : std_logic_vector(31 downto 0);
signal instruction_addr_out : std_logic_vector(22 downto 0);
signal dRAM_data_out : std_logic_vector(15 downto 0);
signal dRAM_addr_out : std_logic_vector(22 downto 0);
signal dRAM_WR_out : std_logic;
-- Clock period definitions
constant main_clock_period : time := 20 ns;
constant dbl_clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OZ3 PORT MAP (
main_clock => main_clock,
dbl_clock => dbl_clock,
inv_clock => inv_clock,
reset => reset,
input_pins => input_pins,
input_port => input_port,
instruction_in => instruction_in,
dRAM_data_in => dRAM_data_in,
output_pins => output_pins,
output_port => output_port,
instruction_addr_out => instruction_addr_out,
dRAM_data_out => dRAM_data_out,
dRAM_addr_out => dRAM_addr_out,
dRAM_WR_out => dRAM_WR_out
);
-- Clock process definitions
main_clock_process :process
begin
main_clock <= '1';
inv_clock <= '0';
wait for main_clock_period/2;
main_clock <= '0';
inv_clock <= '1';
wait for main_clock_period/2;
end process;
dbl_clock_process :process
begin
dbl_clock <= '1';
wait for dbl_clock_period/2;
dbl_clock <= '0';
wait for dbl_clock_period/2;
end process;
dRAM_data_test :process
begin
wait for 2.5 ns;
loop
dRAM_data_in <= x"0000";
wait for 5 ns;
dRAM_data_in <= x"FFFF";
wait for 5 ns;
end loop;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 200 ns;
instruction_in <= "0110000000100000";
wait for 10 ns;
instruction_in <= "0000000000000011";
wait for 10 ns;
instruction_in <= x"0000";
wait;
end process;
END;
|
mit
|
7e62a3babd147d226d02469a17e0c24d
| 0.581354 | 3.530564 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
| 1 | 16,641 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-3.0
|
cb876faebb654b75eda4f34245e760d5
| 0.524067 | 3.333534 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/fifo_bt_txd/synth/fifo_bt_txd.vhd
| 1 | 38,911 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_4;
USE fifo_generator_v13_1_4.fifo_generator_v13_1_4;
ENTITY fifo_bt_txd IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_bt_txd;
ARCHITECTURE fifo_bt_txd_arch OF fifo_bt_txd IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_bt_txd_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_4 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_bt_txd_arch: ARCHITECTURE IS "fifo_generator_v13_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_bt_txd_arch : ARCHITECTURE IS "fifo_bt_txd,fifo_generator_v13_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_bt_txd_arch: ARCHITECTURE IS "fifo_bt_txd,fifo_generator_v13_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_ME" &
"MINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THR" &
"ESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERF" &
"ACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WID" &
"TH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYP" &
"E_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_E" &
"RROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10" &
",C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=10" &
"23,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSE" &
"RT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_4
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_bt_txd_arch;
|
gpl-3.0
|
10ad9e7c97829a7ad4982d3da2dbf8e6
| 0.627226 | 2.903373 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/wishbone_intercon.vhd
| 2 | 3,410 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_pack.all ;
entity wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end wishbone_intercon;
architecture Behavioral of wishbone_intercon is
signal cs_vector : std_logic_vector(0 to (memory_map'length-1));
signal ack_vector : std_logic_vector(0 to (memory_map'length-1));
begin
gen_cs : for i in 0 to (memory_map'length-1) generate
cs_vector(i) <= '1' when wbs_address(wbs_address'length-1 downto find_X(memory_map(i))) = memory_map(i)(wbs_address'length-1 downto find_X(memory_map(i))) else
'0' ;
ack_vector(i) <= wbm_ack(i) and cs_vector(i) ;
wbm_address(i)(wbs_address'length-1 downto find_X(memory_map(i))) <= (others => '0') ;
wbm_address(i)(find_X(memory_map(i))-1 downto 0) <= wbs_address(find_X(memory_map(i))-1 downto 0) ;
wbm_writedata(i) <= wbs_writedata ;
wbm_write(i) <= wbs_write and cs_vector(i) ;
wbm_strobe(i) <= wbs_strobe and cs_vector(i) ;
wbm_cycle(i) <= wbs_cycle and cs_vector(i) ;
wbs_readdata <= wbm_readdata(i) when cs_vector(i) = '1' else
(others => 'Z') ;
end generate ;
wbs_ack <= '1' when ack_vector /= 0 else
'0' ;
wbs_readdata <= wbs_address when cs_vector = 0 else
(others => 'Z') ;
end Behavioral;
|
lgpl-3.0
|
56586b7ed741213c0ae6e137b7232803
| 0.659238 | 3.282002 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/alt_cal_sv/_primary.vhd
| 1 | 1,777 |
library verilog;
use verilog.vl_types.all;
entity alt_cal_sv is
generic(
number_of_channels: integer := 1;
channel_address_width: integer := 1;
sim_model_mode : string := "TRUE";
lpm_type : string := "alt_cal_sv";
lpm_hint : string := "UNUSED";
sample_length : vl_logic_vector(0 to 7) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0);
pma_base_address: vl_logic_vector(0 to 11) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
);
port(
busy : out vl_logic;
clock : in vl_logic;
dprio_addr : out vl_logic_vector(15 downto 0);
dprio_busy : in vl_logic;
dprio_datain : in vl_logic_vector(15 downto 0);
dprio_dataout : out vl_logic_vector(15 downto 0);
dprio_rden : out vl_logic;
dprio_wren : out vl_logic;
quad_addr : out vl_logic_vector(8 downto 0);
remap_addr : in vl_logic_vector(11 downto 0);
reset : in vl_logic;
start : in vl_logic;
testbuses : in vl_logic_vector(7 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of sim_model_mode : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of sample_length : constant is 1;
attribute mti_svvh_generic_type of pma_base_address : constant is 1;
end alt_cal_sv;
|
bsd-2-clause
|
afe4099c4db854f3701cffeb25662a18
| 0.575127 | 3.35283 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/afifo_64i_16o.vhd
| 1 | 4,114 |
library ieee;
use ieee.std_logic_1164.all;
entity afifo_64i_16o is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_vector(63 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(15 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end entity afifo_64i_16o;
architecture rtl of afifo_64i_16o is
--
-- Device specific FIFOs
--
component afifo_64i_16o_s6
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_vector(63 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(15 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
component afifo_64i_16o_v6
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_vector(63 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(15 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
component afifo_64i_16o_k7
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_vector(63 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(15 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
begin
S6_GEN : if (C_FAMILY = "spartan6") generate
afifo_64i_16o_s6_l : afifo_64i_16o_s6
port map (
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty
);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6") generate
afifo_64i_16o_v6_l : afifo_64i_16o_v6
port map (
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty
);
end generate V6_GEN;
K7_GEN : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
afifo_64i_16o_k7_l : afifo_64i_16o_k7
port map (
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty
);
end generate K7_GEN;
end rtl;
|
gpl-3.0
|
c2cae8fa697d7dc3f5e1e37b4e54fff6
| 0.345406 | 4.303347 | false | false | false | false |
mediocregopher/chdl
|
src/chdl_examples/md5/md5.vhd
| 1 | 97,191 |
ENTITY CHIP9684 IS
PORT(SIGNAL_IN9685 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9686 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9687 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9688 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9689 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9690 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9691 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9692 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9693 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9684;
ARCHITECTURE ARCH OF CHIP9684 IS
SIGNAL SIGNAL9694 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9694 <= SIGNAL_IN9688;
SIGNAL_OUT9693 <= SIGNAL_IN9687;
SIGNAL_OUT9692 <= SIGNAL_IN9686;
SIGNAL_OUT9691 <= (SIGNAL_IN9686 + ((((SIGNAL_IN9685 + ((SIGNAL_IN9686 and SIGNAL_IN9687) or ((not SIGNAL_IN9686) and SIGNAL_IN9688))) + TO_UNSIGNED(3614090360, 32)) + SIGNAL_IN9689) rol 7));
SIGNAL9694 <= SIGNAL_IN9688;
END ARCHITECTURE ARCH;
ENTITY CHIP9695 IS
PORT(SIGNAL_IN9696 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9697 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9698 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9699 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9700 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9701 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9702 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9703 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9704 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9695;
ARCHITECTURE ARCH OF CHIP9695 IS
SIGNAL SIGNAL9705 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9705 <= SIGNAL_IN9699;
SIGNAL_OUT9704 <= SIGNAL_IN9698;
SIGNAL_OUT9703 <= SIGNAL_IN9697;
SIGNAL_OUT9702 <= (SIGNAL_IN9697 + ((((SIGNAL_IN9696 + ((SIGNAL_IN9697 and SIGNAL_IN9698) or ((not SIGNAL_IN9697) and SIGNAL_IN9699))) + TO_UNSIGNED(3905402710, 32)) + SIGNAL_IN9700) rol 12));
SIGNAL9705 <= SIGNAL_IN9699;
END ARCHITECTURE ARCH;
ENTITY CHIP9706 IS
PORT(SIGNAL_IN9707 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9708 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9709 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9710 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9711 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9712 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9713 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9714 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9715 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9706;
ARCHITECTURE ARCH OF CHIP9706 IS
SIGNAL SIGNAL9716 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9716 <= SIGNAL_IN9710;
SIGNAL_OUT9715 <= SIGNAL_IN9709;
SIGNAL_OUT9714 <= SIGNAL_IN9708;
SIGNAL_OUT9713 <= (SIGNAL_IN9708 + ((((SIGNAL_IN9707 + ((SIGNAL_IN9708 and SIGNAL_IN9709) or ((not SIGNAL_IN9708) and SIGNAL_IN9710))) + TO_UNSIGNED(606105819, 32)) + SIGNAL_IN9711) rol 17));
SIGNAL9716 <= SIGNAL_IN9710;
END ARCHITECTURE ARCH;
ENTITY CHIP9717 IS
PORT(SIGNAL_IN9718 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9719 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9720 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9721 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9722 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9723 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9724 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9725 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9726 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9717;
ARCHITECTURE ARCH OF CHIP9717 IS
SIGNAL SIGNAL9727 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9727 <= SIGNAL_IN9721;
SIGNAL_OUT9726 <= SIGNAL_IN9720;
SIGNAL_OUT9725 <= SIGNAL_IN9719;
SIGNAL_OUT9724 <= (SIGNAL_IN9719 + ((((SIGNAL_IN9718 + ((SIGNAL_IN9719 and SIGNAL_IN9720) or ((not SIGNAL_IN9719) and SIGNAL_IN9721))) + TO_UNSIGNED(3250441966, 32)) + SIGNAL_IN9722) rol 22));
SIGNAL9727 <= SIGNAL_IN9721;
END ARCHITECTURE ARCH;
ENTITY CHIP9728 IS
PORT(SIGNAL_IN9729 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9730 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9731 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9732 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9733 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9734 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9735 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9736 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9737 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9728;
ARCHITECTURE ARCH OF CHIP9728 IS
SIGNAL SIGNAL9738 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9738 <= SIGNAL_IN9732;
SIGNAL_OUT9737 <= SIGNAL_IN9731;
SIGNAL_OUT9736 <= SIGNAL_IN9730;
SIGNAL_OUT9735 <= (SIGNAL_IN9730 + ((((SIGNAL_IN9729 + ((SIGNAL_IN9730 and SIGNAL_IN9731) or ((not SIGNAL_IN9730) and SIGNAL_IN9732))) + TO_UNSIGNED(4118548399, 32)) + SIGNAL_IN9733) rol 7));
SIGNAL9738 <= SIGNAL_IN9732;
END ARCHITECTURE ARCH;
ENTITY CHIP9739 IS
PORT(SIGNAL_IN9740 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9741 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9742 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9743 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9744 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9745 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9746 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9747 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9748 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9739;
ARCHITECTURE ARCH OF CHIP9739 IS
SIGNAL SIGNAL9749 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9749 <= SIGNAL_IN9743;
SIGNAL_OUT9748 <= SIGNAL_IN9742;
SIGNAL_OUT9747 <= SIGNAL_IN9741;
SIGNAL_OUT9746 <= (SIGNAL_IN9741 + ((((SIGNAL_IN9740 + ((SIGNAL_IN9741 and SIGNAL_IN9742) or ((not SIGNAL_IN9741) and SIGNAL_IN9743))) + TO_UNSIGNED(1200080426, 32)) + SIGNAL_IN9744) rol 12));
SIGNAL9749 <= SIGNAL_IN9743;
END ARCHITECTURE ARCH;
ENTITY CHIP9750 IS
PORT(SIGNAL_IN9751 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9752 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9753 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9754 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9755 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9756 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9757 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9758 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9759 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9750;
ARCHITECTURE ARCH OF CHIP9750 IS
SIGNAL SIGNAL9760 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9760 <= SIGNAL_IN9754;
SIGNAL_OUT9759 <= SIGNAL_IN9753;
SIGNAL_OUT9758 <= SIGNAL_IN9752;
SIGNAL_OUT9757 <= (SIGNAL_IN9752 + ((((SIGNAL_IN9751 + ((SIGNAL_IN9752 and SIGNAL_IN9753) or ((not SIGNAL_IN9752) and SIGNAL_IN9754))) + TO_UNSIGNED(2821735955, 32)) + SIGNAL_IN9755) rol 17));
SIGNAL9760 <= SIGNAL_IN9754;
END ARCHITECTURE ARCH;
ENTITY CHIP9761 IS
PORT(SIGNAL_IN9762 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9763 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9764 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9765 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9766 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9767 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9768 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9769 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9770 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9761;
ARCHITECTURE ARCH OF CHIP9761 IS
SIGNAL SIGNAL9771 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9771 <= SIGNAL_IN9765;
SIGNAL_OUT9770 <= SIGNAL_IN9764;
SIGNAL_OUT9769 <= SIGNAL_IN9763;
SIGNAL_OUT9768 <= (SIGNAL_IN9763 + ((((SIGNAL_IN9762 + ((SIGNAL_IN9763 and SIGNAL_IN9764) or ((not SIGNAL_IN9763) and SIGNAL_IN9765))) + TO_UNSIGNED(4249261313, 32)) + SIGNAL_IN9766) rol 22));
SIGNAL9771 <= SIGNAL_IN9765;
END ARCHITECTURE ARCH;
ENTITY CHIP9772 IS
PORT(SIGNAL_IN9773 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9774 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9775 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9776 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9777 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9778 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9779 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9780 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9781 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9772;
ARCHITECTURE ARCH OF CHIP9772 IS
SIGNAL SIGNAL9782 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9782 <= SIGNAL_IN9776;
SIGNAL_OUT9781 <= SIGNAL_IN9775;
SIGNAL_OUT9780 <= SIGNAL_IN9774;
SIGNAL_OUT9779 <= (SIGNAL_IN9774 + ((((SIGNAL_IN9773 + ((SIGNAL_IN9774 and SIGNAL_IN9775) or ((not SIGNAL_IN9774) and SIGNAL_IN9776))) + TO_UNSIGNED(1770035416, 32)) + SIGNAL_IN9777) rol 7));
SIGNAL9782 <= SIGNAL_IN9776;
END ARCHITECTURE ARCH;
ENTITY CHIP9783 IS
PORT(SIGNAL_IN9784 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9785 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9786 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9787 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9788 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9789 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9790 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9791 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9792 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9783;
ARCHITECTURE ARCH OF CHIP9783 IS
SIGNAL SIGNAL9793 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9793 <= SIGNAL_IN9787;
SIGNAL_OUT9792 <= SIGNAL_IN9786;
SIGNAL_OUT9791 <= SIGNAL_IN9785;
SIGNAL_OUT9790 <= (SIGNAL_IN9785 + ((((SIGNAL_IN9784 + ((SIGNAL_IN9785 and SIGNAL_IN9786) or ((not SIGNAL_IN9785) and SIGNAL_IN9787))) + TO_UNSIGNED(2336552879, 32)) + SIGNAL_IN9788) rol 12));
SIGNAL9793 <= SIGNAL_IN9787;
END ARCHITECTURE ARCH;
ENTITY CHIP9794 IS
PORT(SIGNAL_IN9795 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9796 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9797 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9798 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9799 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9800 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9801 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9802 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9803 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9794;
ARCHITECTURE ARCH OF CHIP9794 IS
SIGNAL SIGNAL9804 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9804 <= SIGNAL_IN9798;
SIGNAL_OUT9803 <= SIGNAL_IN9797;
SIGNAL_OUT9802 <= SIGNAL_IN9796;
SIGNAL_OUT9801 <= (SIGNAL_IN9796 + ((((SIGNAL_IN9795 + ((SIGNAL_IN9796 and SIGNAL_IN9797) or ((not SIGNAL_IN9796) and SIGNAL_IN9798))) + TO_UNSIGNED(4294925233, 32)) + SIGNAL_IN9799) rol 17));
SIGNAL9804 <= SIGNAL_IN9798;
END ARCHITECTURE ARCH;
ENTITY CHIP9805 IS
PORT(SIGNAL_IN9806 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9807 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9808 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9809 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9810 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9811 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9812 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9813 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9814 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9805;
ARCHITECTURE ARCH OF CHIP9805 IS
SIGNAL SIGNAL9815 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9815 <= SIGNAL_IN9809;
SIGNAL_OUT9814 <= SIGNAL_IN9808;
SIGNAL_OUT9813 <= SIGNAL_IN9807;
SIGNAL_OUT9812 <= (SIGNAL_IN9807 + ((((SIGNAL_IN9806 + ((SIGNAL_IN9807 and SIGNAL_IN9808) or ((not SIGNAL_IN9807) and SIGNAL_IN9809))) + TO_UNSIGNED(2304563134, 32)) + SIGNAL_IN9810) rol 22));
SIGNAL9815 <= SIGNAL_IN9809;
END ARCHITECTURE ARCH;
ENTITY CHIP9816 IS
PORT(SIGNAL_IN9817 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9818 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9819 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9820 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9821 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9822 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9823 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9824 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9825 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9816;
ARCHITECTURE ARCH OF CHIP9816 IS
SIGNAL SIGNAL9826 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9826 <= SIGNAL_IN9820;
SIGNAL_OUT9825 <= SIGNAL_IN9819;
SIGNAL_OUT9824 <= SIGNAL_IN9818;
SIGNAL_OUT9823 <= (SIGNAL_IN9818 + ((((SIGNAL_IN9817 + ((SIGNAL_IN9818 and SIGNAL_IN9819) or ((not SIGNAL_IN9818) and SIGNAL_IN9820))) + TO_UNSIGNED(1804603682, 32)) + SIGNAL_IN9821) rol 7));
SIGNAL9826 <= SIGNAL_IN9820;
END ARCHITECTURE ARCH;
ENTITY CHIP9827 IS
PORT(SIGNAL_IN9828 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9829 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9830 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9831 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9832 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9833 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9834 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9835 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9836 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9827;
ARCHITECTURE ARCH OF CHIP9827 IS
SIGNAL SIGNAL9837 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9837 <= SIGNAL_IN9831;
SIGNAL_OUT9836 <= SIGNAL_IN9830;
SIGNAL_OUT9835 <= SIGNAL_IN9829;
SIGNAL_OUT9834 <= (SIGNAL_IN9829 + ((((SIGNAL_IN9828 + ((SIGNAL_IN9829 and SIGNAL_IN9830) or ((not SIGNAL_IN9829) and SIGNAL_IN9831))) + TO_UNSIGNED(4254626195, 32)) + SIGNAL_IN9832) rol 12));
SIGNAL9837 <= SIGNAL_IN9831;
END ARCHITECTURE ARCH;
ENTITY CHIP9838 IS
PORT(SIGNAL_IN9839 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9840 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9841 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9842 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9843 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9844 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9845 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9846 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9847 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9838;
ARCHITECTURE ARCH OF CHIP9838 IS
SIGNAL SIGNAL9848 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9848 <= SIGNAL_IN9842;
SIGNAL_OUT9847 <= SIGNAL_IN9841;
SIGNAL_OUT9846 <= SIGNAL_IN9840;
SIGNAL_OUT9845 <= (SIGNAL_IN9840 + ((((SIGNAL_IN9839 + ((SIGNAL_IN9840 and SIGNAL_IN9841) or ((not SIGNAL_IN9840) and SIGNAL_IN9842))) + TO_UNSIGNED(2792965006, 32)) + SIGNAL_IN9843) rol 17));
SIGNAL9848 <= SIGNAL_IN9842;
END ARCHITECTURE ARCH;
ENTITY CHIP9849 IS
PORT(SIGNAL_IN9850 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9851 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9852 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9853 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9854 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9855 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9856 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9857 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9858 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9849;
ARCHITECTURE ARCH OF CHIP9849 IS
SIGNAL SIGNAL9859 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9859 <= SIGNAL_IN9853;
SIGNAL_OUT9858 <= SIGNAL_IN9852;
SIGNAL_OUT9857 <= SIGNAL_IN9851;
SIGNAL_OUT9856 <= (SIGNAL_IN9851 + ((((SIGNAL_IN9850 + ((SIGNAL_IN9851 and SIGNAL_IN9852) or ((not SIGNAL_IN9851) and SIGNAL_IN9853))) + TO_UNSIGNED(1236535329, 32)) + SIGNAL_IN9854) rol 22));
SIGNAL9859 <= SIGNAL_IN9853;
END ARCHITECTURE ARCH;
ENTITY CHIP9860 IS
PORT(SIGNAL_IN9861 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9862 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9863 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9864 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9865 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9866 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9867 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9868 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9869 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9860;
ARCHITECTURE ARCH OF CHIP9860 IS
SIGNAL SIGNAL9870 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9870 <= SIGNAL_IN9864;
SIGNAL_OUT9869 <= SIGNAL_IN9863;
SIGNAL_OUT9868 <= SIGNAL_IN9862;
SIGNAL_OUT9867 <= (SIGNAL_IN9862 + ((((SIGNAL_IN9861 + ((SIGNAL_IN9864 and SIGNAL_IN9862) or ((not SIGNAL_IN9864) and SIGNAL_IN9863))) + TO_UNSIGNED(4129170786, 32)) + SIGNAL_IN9865) rol 5));
SIGNAL9870 <= SIGNAL_IN9864;
END ARCHITECTURE ARCH;
ENTITY CHIP9871 IS
PORT(SIGNAL_IN9872 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9873 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9874 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9875 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9876 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9877 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9878 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9879 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9880 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9871;
ARCHITECTURE ARCH OF CHIP9871 IS
SIGNAL SIGNAL9881 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9881 <= SIGNAL_IN9875;
SIGNAL_OUT9880 <= SIGNAL_IN9874;
SIGNAL_OUT9879 <= SIGNAL_IN9873;
SIGNAL_OUT9878 <= (SIGNAL_IN9873 + ((((SIGNAL_IN9872 + ((SIGNAL_IN9875 and SIGNAL_IN9873) or ((not SIGNAL_IN9875) and SIGNAL_IN9874))) + TO_UNSIGNED(3225465664, 32)) + SIGNAL_IN9876) rol 9));
SIGNAL9881 <= SIGNAL_IN9875;
END ARCHITECTURE ARCH;
ENTITY CHIP9882 IS
PORT(SIGNAL_IN9883 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9884 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9885 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9886 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9887 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9888 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9889 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9890 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9891 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9882;
ARCHITECTURE ARCH OF CHIP9882 IS
SIGNAL SIGNAL9892 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9892 <= SIGNAL_IN9886;
SIGNAL_OUT9891 <= SIGNAL_IN9885;
SIGNAL_OUT9890 <= SIGNAL_IN9884;
SIGNAL_OUT9889 <= (SIGNAL_IN9884 + ((((SIGNAL_IN9883 + ((SIGNAL_IN9886 and SIGNAL_IN9884) or ((not SIGNAL_IN9886) and SIGNAL_IN9885))) + TO_UNSIGNED(643717713, 32)) + SIGNAL_IN9887) rol 14));
SIGNAL9892 <= SIGNAL_IN9886;
END ARCHITECTURE ARCH;
ENTITY CHIP9893 IS
PORT(SIGNAL_IN9894 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9895 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9896 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9897 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9898 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9899 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9900 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9901 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9902 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9893;
ARCHITECTURE ARCH OF CHIP9893 IS
SIGNAL SIGNAL9903 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9903 <= SIGNAL_IN9897;
SIGNAL_OUT9902 <= SIGNAL_IN9896;
SIGNAL_OUT9901 <= SIGNAL_IN9895;
SIGNAL_OUT9900 <= (SIGNAL_IN9895 + ((((SIGNAL_IN9894 + ((SIGNAL_IN9897 and SIGNAL_IN9895) or ((not SIGNAL_IN9897) and SIGNAL_IN9896))) + TO_UNSIGNED(3921069994, 32)) + SIGNAL_IN9898) rol 20));
SIGNAL9903 <= SIGNAL_IN9897;
END ARCHITECTURE ARCH;
ENTITY CHIP9904 IS
PORT(SIGNAL_IN9905 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9906 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9907 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9908 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9909 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9910 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9911 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9912 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9913 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9904;
ARCHITECTURE ARCH OF CHIP9904 IS
SIGNAL SIGNAL9914 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9914 <= SIGNAL_IN9908;
SIGNAL_OUT9913 <= SIGNAL_IN9907;
SIGNAL_OUT9912 <= SIGNAL_IN9906;
SIGNAL_OUT9911 <= (SIGNAL_IN9906 + ((((SIGNAL_IN9905 + ((SIGNAL_IN9908 and SIGNAL_IN9906) or ((not SIGNAL_IN9908) and SIGNAL_IN9907))) + TO_UNSIGNED(3593408605, 32)) + SIGNAL_IN9909) rol 5));
SIGNAL9914 <= SIGNAL_IN9908;
END ARCHITECTURE ARCH;
ENTITY CHIP9915 IS
PORT(SIGNAL_IN9916 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9917 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9918 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9919 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9920 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9921 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9922 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9923 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9924 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9915;
ARCHITECTURE ARCH OF CHIP9915 IS
SIGNAL SIGNAL9925 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9925 <= SIGNAL_IN9919;
SIGNAL_OUT9924 <= SIGNAL_IN9918;
SIGNAL_OUT9923 <= SIGNAL_IN9917;
SIGNAL_OUT9922 <= (SIGNAL_IN9917 + ((((SIGNAL_IN9916 + ((SIGNAL_IN9919 and SIGNAL_IN9917) or ((not SIGNAL_IN9919) and SIGNAL_IN9918))) + TO_UNSIGNED(38016083, 32)) + SIGNAL_IN9920) rol 9));
SIGNAL9925 <= SIGNAL_IN9919;
END ARCHITECTURE ARCH;
ENTITY CHIP9926 IS
PORT(SIGNAL_IN9927 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9928 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9929 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9930 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9931 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9932 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9933 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9934 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9935 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9926;
ARCHITECTURE ARCH OF CHIP9926 IS
SIGNAL SIGNAL9936 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9936 <= SIGNAL_IN9930;
SIGNAL_OUT9935 <= SIGNAL_IN9929;
SIGNAL_OUT9934 <= SIGNAL_IN9928;
SIGNAL_OUT9933 <= (SIGNAL_IN9928 + ((((SIGNAL_IN9927 + ((SIGNAL_IN9930 and SIGNAL_IN9928) or ((not SIGNAL_IN9930) and SIGNAL_IN9929))) + TO_UNSIGNED(3634488961, 32)) + SIGNAL_IN9931) rol 14));
SIGNAL9936 <= SIGNAL_IN9930;
END ARCHITECTURE ARCH;
ENTITY CHIP9937 IS
PORT(SIGNAL_IN9938 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9939 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9940 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9941 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9942 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9943 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9944 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9945 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9946 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9937;
ARCHITECTURE ARCH OF CHIP9937 IS
SIGNAL SIGNAL9947 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9947 <= SIGNAL_IN9941;
SIGNAL_OUT9946 <= SIGNAL_IN9940;
SIGNAL_OUT9945 <= SIGNAL_IN9939;
SIGNAL_OUT9944 <= (SIGNAL_IN9939 + ((((SIGNAL_IN9938 + ((SIGNAL_IN9941 and SIGNAL_IN9939) or ((not SIGNAL_IN9941) and SIGNAL_IN9940))) + TO_UNSIGNED(3889429448, 32)) + SIGNAL_IN9942) rol 20));
SIGNAL9947 <= SIGNAL_IN9941;
END ARCHITECTURE ARCH;
ENTITY CHIP9948 IS
PORT(SIGNAL_IN9949 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9950 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9951 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9952 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9953 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9954 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9955 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9956 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9957 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9948;
ARCHITECTURE ARCH OF CHIP9948 IS
SIGNAL SIGNAL9958 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9958 <= SIGNAL_IN9952;
SIGNAL_OUT9957 <= SIGNAL_IN9951;
SIGNAL_OUT9956 <= SIGNAL_IN9950;
SIGNAL_OUT9955 <= (SIGNAL_IN9950 + ((((SIGNAL_IN9949 + ((SIGNAL_IN9952 and SIGNAL_IN9950) or ((not SIGNAL_IN9952) and SIGNAL_IN9951))) + TO_UNSIGNED(568446438, 32)) + SIGNAL_IN9953) rol 5));
SIGNAL9958 <= SIGNAL_IN9952;
END ARCHITECTURE ARCH;
ENTITY CHIP9959 IS
PORT(SIGNAL_IN9960 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9961 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9962 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9963 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9964 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9965 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9966 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9967 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9968 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9959;
ARCHITECTURE ARCH OF CHIP9959 IS
SIGNAL SIGNAL9969 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9969 <= SIGNAL_IN9963;
SIGNAL_OUT9968 <= SIGNAL_IN9962;
SIGNAL_OUT9967 <= SIGNAL_IN9961;
SIGNAL_OUT9966 <= (SIGNAL_IN9961 + ((((SIGNAL_IN9960 + ((SIGNAL_IN9963 and SIGNAL_IN9961) or ((not SIGNAL_IN9963) and SIGNAL_IN9962))) + TO_UNSIGNED(3275163606, 32)) + SIGNAL_IN9964) rol 9));
SIGNAL9969 <= SIGNAL_IN9963;
END ARCHITECTURE ARCH;
ENTITY CHIP9970 IS
PORT(SIGNAL_IN9971 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9972 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9973 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9974 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9975 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9976 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9977 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9978 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9979 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9970;
ARCHITECTURE ARCH OF CHIP9970 IS
SIGNAL SIGNAL9980 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9980 <= SIGNAL_IN9974;
SIGNAL_OUT9979 <= SIGNAL_IN9973;
SIGNAL_OUT9978 <= SIGNAL_IN9972;
SIGNAL_OUT9977 <= (SIGNAL_IN9972 + ((((SIGNAL_IN9971 + ((SIGNAL_IN9974 and SIGNAL_IN9972) or ((not SIGNAL_IN9974) and SIGNAL_IN9973))) + TO_UNSIGNED(4107603335, 32)) + SIGNAL_IN9975) rol 14));
SIGNAL9980 <= SIGNAL_IN9974;
END ARCHITECTURE ARCH;
ENTITY CHIP9981 IS
PORT(SIGNAL_IN9982 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9983 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9984 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9985 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9986 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9987 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9988 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9989 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9990 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9981;
ARCHITECTURE ARCH OF CHIP9981 IS
SIGNAL SIGNAL9991 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9991 <= SIGNAL_IN9985;
SIGNAL_OUT9990 <= SIGNAL_IN9984;
SIGNAL_OUT9989 <= SIGNAL_IN9983;
SIGNAL_OUT9988 <= (SIGNAL_IN9983 + ((((SIGNAL_IN9982 + ((SIGNAL_IN9985 and SIGNAL_IN9983) or ((not SIGNAL_IN9985) and SIGNAL_IN9984))) + TO_UNSIGNED(1163531501, 32)) + SIGNAL_IN9986) rol 20));
SIGNAL9991 <= SIGNAL_IN9985;
END ARCHITECTURE ARCH;
ENTITY CHIP9992 IS
PORT(SIGNAL_IN9993 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9994 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9995 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9996 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9997 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT9998 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9999 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10000 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10001 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9992;
ARCHITECTURE ARCH OF CHIP9992 IS
SIGNAL SIGNAL10002 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10002 <= SIGNAL_IN9996;
SIGNAL_OUT10001 <= SIGNAL_IN9995;
SIGNAL_OUT10000 <= SIGNAL_IN9994;
SIGNAL_OUT9999 <= (SIGNAL_IN9994 + ((((SIGNAL_IN9993 + ((SIGNAL_IN9996 and SIGNAL_IN9994) or ((not SIGNAL_IN9996) and SIGNAL_IN9995))) + TO_UNSIGNED(2850285829, 32)) + SIGNAL_IN9997) rol 5));
SIGNAL10002 <= SIGNAL_IN9996;
END ARCHITECTURE ARCH;
ENTITY CHIP10003 IS
PORT(SIGNAL_IN10004 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10005 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10006 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10007 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10008 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10009 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10010 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10011 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10012 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10003;
ARCHITECTURE ARCH OF CHIP10003 IS
SIGNAL SIGNAL10013 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10013 <= SIGNAL_IN10007;
SIGNAL_OUT10012 <= SIGNAL_IN10006;
SIGNAL_OUT10011 <= SIGNAL_IN10005;
SIGNAL_OUT10010 <= (SIGNAL_IN10005 + ((((SIGNAL_IN10004 + ((SIGNAL_IN10007 and SIGNAL_IN10005) or ((not SIGNAL_IN10007) and SIGNAL_IN10006))) + TO_UNSIGNED(4243563512, 32)) + SIGNAL_IN10008) rol 9));
SIGNAL10013 <= SIGNAL_IN10007;
END ARCHITECTURE ARCH;
ENTITY CHIP10014 IS
PORT(SIGNAL_IN10015 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10016 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10017 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10018 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10019 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10020 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10021 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10022 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10023 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10014;
ARCHITECTURE ARCH OF CHIP10014 IS
SIGNAL SIGNAL10024 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10024 <= SIGNAL_IN10018;
SIGNAL_OUT10023 <= SIGNAL_IN10017;
SIGNAL_OUT10022 <= SIGNAL_IN10016;
SIGNAL_OUT10021 <= (SIGNAL_IN10016 + ((((SIGNAL_IN10015 + ((SIGNAL_IN10018 and SIGNAL_IN10016) or ((not SIGNAL_IN10018) and SIGNAL_IN10017))) + TO_UNSIGNED(1735328473, 32)) + SIGNAL_IN10019) rol 14));
SIGNAL10024 <= SIGNAL_IN10018;
END ARCHITECTURE ARCH;
ENTITY CHIP10025 IS
PORT(SIGNAL_IN10026 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10027 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10028 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10029 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10030 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10031 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10032 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10033 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10034 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10025;
ARCHITECTURE ARCH OF CHIP10025 IS
SIGNAL SIGNAL10035 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10035 <= SIGNAL_IN10029;
SIGNAL_OUT10034 <= SIGNAL_IN10028;
SIGNAL_OUT10033 <= SIGNAL_IN10027;
SIGNAL_OUT10032 <= (SIGNAL_IN10027 + ((((SIGNAL_IN10026 + ((SIGNAL_IN10029 and SIGNAL_IN10027) or ((not SIGNAL_IN10029) and SIGNAL_IN10028))) + TO_UNSIGNED(2368359562, 32)) + SIGNAL_IN10030) rol 20));
SIGNAL10035 <= SIGNAL_IN10029;
END ARCHITECTURE ARCH;
ENTITY CHIP10036 IS
PORT(SIGNAL_IN10037 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10038 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10039 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10040 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10041 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10042 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10043 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10044 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10045 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10036;
ARCHITECTURE ARCH OF CHIP10036 IS
SIGNAL SIGNAL10046 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10046 <= SIGNAL_IN10040;
SIGNAL_OUT10045 <= SIGNAL_IN10039;
SIGNAL_OUT10044 <= SIGNAL_IN10038;
SIGNAL_OUT10043 <= (SIGNAL_IN10038 + ((((SIGNAL_IN10037 + (SIGNAL_IN10038 xor (SIGNAL_IN10039 xor SIGNAL_IN10040))) + TO_UNSIGNED(4294588738, 32)) + SIGNAL_IN10041) rol 4));
SIGNAL10046 <= SIGNAL_IN10040;
END ARCHITECTURE ARCH;
ENTITY CHIP10047 IS
PORT(SIGNAL_IN10048 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10049 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10050 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10051 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10052 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10053 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10054 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10055 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10056 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10047;
ARCHITECTURE ARCH OF CHIP10047 IS
SIGNAL SIGNAL10057 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10057 <= SIGNAL_IN10051;
SIGNAL_OUT10056 <= SIGNAL_IN10050;
SIGNAL_OUT10055 <= SIGNAL_IN10049;
SIGNAL_OUT10054 <= (SIGNAL_IN10049 + ((((SIGNAL_IN10048 + (SIGNAL_IN10049 xor (SIGNAL_IN10050 xor SIGNAL_IN10051))) + TO_UNSIGNED(2272392833, 32)) + SIGNAL_IN10052) rol 11));
SIGNAL10057 <= SIGNAL_IN10051;
END ARCHITECTURE ARCH;
ENTITY CHIP10058 IS
PORT(SIGNAL_IN10059 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10060 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10061 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10062 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10063 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10064 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10065 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10066 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10067 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10058;
ARCHITECTURE ARCH OF CHIP10058 IS
SIGNAL SIGNAL10068 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10068 <= SIGNAL_IN10062;
SIGNAL_OUT10067 <= SIGNAL_IN10061;
SIGNAL_OUT10066 <= SIGNAL_IN10060;
SIGNAL_OUT10065 <= (SIGNAL_IN10060 + ((((SIGNAL_IN10059 + (SIGNAL_IN10060 xor (SIGNAL_IN10061 xor SIGNAL_IN10062))) + TO_UNSIGNED(1839030562, 32)) + SIGNAL_IN10063) rol 16));
SIGNAL10068 <= SIGNAL_IN10062;
END ARCHITECTURE ARCH;
ENTITY CHIP10069 IS
PORT(SIGNAL_IN10070 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10071 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10072 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10073 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10074 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10075 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10076 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10077 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10078 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10069;
ARCHITECTURE ARCH OF CHIP10069 IS
SIGNAL SIGNAL10079 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10079 <= SIGNAL_IN10073;
SIGNAL_OUT10078 <= SIGNAL_IN10072;
SIGNAL_OUT10077 <= SIGNAL_IN10071;
SIGNAL_OUT10076 <= (SIGNAL_IN10071 + ((((SIGNAL_IN10070 + (SIGNAL_IN10071 xor (SIGNAL_IN10072 xor SIGNAL_IN10073))) + TO_UNSIGNED(4259657740, 32)) + SIGNAL_IN10074) rol 23));
SIGNAL10079 <= SIGNAL_IN10073;
END ARCHITECTURE ARCH;
ENTITY CHIP10080 IS
PORT(SIGNAL_IN10081 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10082 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10083 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10084 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10085 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10086 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10087 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10088 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10089 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10080;
ARCHITECTURE ARCH OF CHIP10080 IS
SIGNAL SIGNAL10090 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10090 <= SIGNAL_IN10084;
SIGNAL_OUT10089 <= SIGNAL_IN10083;
SIGNAL_OUT10088 <= SIGNAL_IN10082;
SIGNAL_OUT10087 <= (SIGNAL_IN10082 + ((((SIGNAL_IN10081 + (SIGNAL_IN10082 xor (SIGNAL_IN10083 xor SIGNAL_IN10084))) + TO_UNSIGNED(2763975236, 32)) + SIGNAL_IN10085) rol 4));
SIGNAL10090 <= SIGNAL_IN10084;
END ARCHITECTURE ARCH;
ENTITY CHIP10091 IS
PORT(SIGNAL_IN10092 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10093 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10094 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10095 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10096 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10097 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10098 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10099 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10100 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10091;
ARCHITECTURE ARCH OF CHIP10091 IS
SIGNAL SIGNAL10101 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10101 <= SIGNAL_IN10095;
SIGNAL_OUT10100 <= SIGNAL_IN10094;
SIGNAL_OUT10099 <= SIGNAL_IN10093;
SIGNAL_OUT10098 <= (SIGNAL_IN10093 + ((((SIGNAL_IN10092 + (SIGNAL_IN10093 xor (SIGNAL_IN10094 xor SIGNAL_IN10095))) + TO_UNSIGNED(1272893353, 32)) + SIGNAL_IN10096) rol 11));
SIGNAL10101 <= SIGNAL_IN10095;
END ARCHITECTURE ARCH;
ENTITY CHIP10102 IS
PORT(SIGNAL_IN10103 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10104 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10105 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10106 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10107 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10108 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10109 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10110 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10111 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10102;
ARCHITECTURE ARCH OF CHIP10102 IS
SIGNAL SIGNAL10112 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10112 <= SIGNAL_IN10106;
SIGNAL_OUT10111 <= SIGNAL_IN10105;
SIGNAL_OUT10110 <= SIGNAL_IN10104;
SIGNAL_OUT10109 <= (SIGNAL_IN10104 + ((((SIGNAL_IN10103 + (SIGNAL_IN10104 xor (SIGNAL_IN10105 xor SIGNAL_IN10106))) + TO_UNSIGNED(4139469664, 32)) + SIGNAL_IN10107) rol 16));
SIGNAL10112 <= SIGNAL_IN10106;
END ARCHITECTURE ARCH;
ENTITY CHIP10113 IS
PORT(SIGNAL_IN10114 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10115 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10116 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10117 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10118 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10119 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10120 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10121 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10122 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10113;
ARCHITECTURE ARCH OF CHIP10113 IS
SIGNAL SIGNAL10123 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10123 <= SIGNAL_IN10117;
SIGNAL_OUT10122 <= SIGNAL_IN10116;
SIGNAL_OUT10121 <= SIGNAL_IN10115;
SIGNAL_OUT10120 <= (SIGNAL_IN10115 + ((((SIGNAL_IN10114 + (SIGNAL_IN10115 xor (SIGNAL_IN10116 xor SIGNAL_IN10117))) + TO_UNSIGNED(3200236656, 32)) + SIGNAL_IN10118) rol 23));
SIGNAL10123 <= SIGNAL_IN10117;
END ARCHITECTURE ARCH;
ENTITY CHIP10124 IS
PORT(SIGNAL_IN10125 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10126 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10127 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10128 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10129 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10130 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10131 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10132 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10133 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10124;
ARCHITECTURE ARCH OF CHIP10124 IS
SIGNAL SIGNAL10134 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10134 <= SIGNAL_IN10128;
SIGNAL_OUT10133 <= SIGNAL_IN10127;
SIGNAL_OUT10132 <= SIGNAL_IN10126;
SIGNAL_OUT10131 <= (SIGNAL_IN10126 + ((((SIGNAL_IN10125 + (SIGNAL_IN10126 xor (SIGNAL_IN10127 xor SIGNAL_IN10128))) + TO_UNSIGNED(681279174, 32)) + SIGNAL_IN10129) rol 4));
SIGNAL10134 <= SIGNAL_IN10128;
END ARCHITECTURE ARCH;
ENTITY CHIP10135 IS
PORT(SIGNAL_IN10136 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10137 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10138 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10139 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10140 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10141 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10142 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10143 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10144 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10135;
ARCHITECTURE ARCH OF CHIP10135 IS
SIGNAL SIGNAL10145 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10145 <= SIGNAL_IN10139;
SIGNAL_OUT10144 <= SIGNAL_IN10138;
SIGNAL_OUT10143 <= SIGNAL_IN10137;
SIGNAL_OUT10142 <= (SIGNAL_IN10137 + ((((SIGNAL_IN10136 + (SIGNAL_IN10137 xor (SIGNAL_IN10138 xor SIGNAL_IN10139))) + TO_UNSIGNED(3936430074, 32)) + SIGNAL_IN10140) rol 11));
SIGNAL10145 <= SIGNAL_IN10139;
END ARCHITECTURE ARCH;
ENTITY CHIP10146 IS
PORT(SIGNAL_IN10147 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10148 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10149 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10150 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10151 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10152 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10153 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10154 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10155 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10146;
ARCHITECTURE ARCH OF CHIP10146 IS
SIGNAL SIGNAL10156 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10156 <= SIGNAL_IN10150;
SIGNAL_OUT10155 <= SIGNAL_IN10149;
SIGNAL_OUT10154 <= SIGNAL_IN10148;
SIGNAL_OUT10153 <= (SIGNAL_IN10148 + ((((SIGNAL_IN10147 + (SIGNAL_IN10148 xor (SIGNAL_IN10149 xor SIGNAL_IN10150))) + TO_UNSIGNED(3572445317, 32)) + SIGNAL_IN10151) rol 16));
SIGNAL10156 <= SIGNAL_IN10150;
END ARCHITECTURE ARCH;
ENTITY CHIP10157 IS
PORT(SIGNAL_IN10158 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10159 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10160 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10161 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10162 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10163 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10164 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10165 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10166 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10157;
ARCHITECTURE ARCH OF CHIP10157 IS
SIGNAL SIGNAL10167 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10167 <= SIGNAL_IN10161;
SIGNAL_OUT10166 <= SIGNAL_IN10160;
SIGNAL_OUT10165 <= SIGNAL_IN10159;
SIGNAL_OUT10164 <= (SIGNAL_IN10159 + ((((SIGNAL_IN10158 + (SIGNAL_IN10159 xor (SIGNAL_IN10160 xor SIGNAL_IN10161))) + TO_UNSIGNED(76029189, 32)) + SIGNAL_IN10162) rol 23));
SIGNAL10167 <= SIGNAL_IN10161;
END ARCHITECTURE ARCH;
ENTITY CHIP10168 IS
PORT(SIGNAL_IN10169 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10170 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10171 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10172 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10173 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10174 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10175 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10176 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10177 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10168;
ARCHITECTURE ARCH OF CHIP10168 IS
SIGNAL SIGNAL10178 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10178 <= SIGNAL_IN10172;
SIGNAL_OUT10177 <= SIGNAL_IN10171;
SIGNAL_OUT10176 <= SIGNAL_IN10170;
SIGNAL_OUT10175 <= (SIGNAL_IN10170 + ((((SIGNAL_IN10169 + (SIGNAL_IN10170 xor (SIGNAL_IN10171 xor SIGNAL_IN10172))) + TO_UNSIGNED(3654602809, 32)) + SIGNAL_IN10173) rol 4));
SIGNAL10178 <= SIGNAL_IN10172;
END ARCHITECTURE ARCH;
ENTITY CHIP10179 IS
PORT(SIGNAL_IN10180 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10181 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10182 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10183 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10184 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10185 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10186 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10187 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10188 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10179;
ARCHITECTURE ARCH OF CHIP10179 IS
SIGNAL SIGNAL10189 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10189 <= SIGNAL_IN10183;
SIGNAL_OUT10188 <= SIGNAL_IN10182;
SIGNAL_OUT10187 <= SIGNAL_IN10181;
SIGNAL_OUT10186 <= (SIGNAL_IN10181 + ((((SIGNAL_IN10180 + (SIGNAL_IN10181 xor (SIGNAL_IN10182 xor SIGNAL_IN10183))) + TO_UNSIGNED(3873151461, 32)) + SIGNAL_IN10184) rol 11));
SIGNAL10189 <= SIGNAL_IN10183;
END ARCHITECTURE ARCH;
ENTITY CHIP10190 IS
PORT(SIGNAL_IN10191 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10192 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10193 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10194 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10195 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10196 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10197 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10198 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10199 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10190;
ARCHITECTURE ARCH OF CHIP10190 IS
SIGNAL SIGNAL10200 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10200 <= SIGNAL_IN10194;
SIGNAL_OUT10199 <= SIGNAL_IN10193;
SIGNAL_OUT10198 <= SIGNAL_IN10192;
SIGNAL_OUT10197 <= (SIGNAL_IN10192 + ((((SIGNAL_IN10191 + (SIGNAL_IN10192 xor (SIGNAL_IN10193 xor SIGNAL_IN10194))) + TO_UNSIGNED(530742520, 32)) + SIGNAL_IN10195) rol 16));
SIGNAL10200 <= SIGNAL_IN10194;
END ARCHITECTURE ARCH;
ENTITY CHIP10201 IS
PORT(SIGNAL_IN10202 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10203 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10204 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10205 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10206 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10207 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10208 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10209 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10210 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10201;
ARCHITECTURE ARCH OF CHIP10201 IS
SIGNAL SIGNAL10211 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10211 <= SIGNAL_IN10205;
SIGNAL_OUT10210 <= SIGNAL_IN10204;
SIGNAL_OUT10209 <= SIGNAL_IN10203;
SIGNAL_OUT10208 <= (SIGNAL_IN10203 + ((((SIGNAL_IN10202 + (SIGNAL_IN10203 xor (SIGNAL_IN10204 xor SIGNAL_IN10205))) + TO_UNSIGNED(3299628645, 32)) + SIGNAL_IN10206) rol 23));
SIGNAL10211 <= SIGNAL_IN10205;
END ARCHITECTURE ARCH;
ENTITY CHIP10212 IS
PORT(SIGNAL_IN10213 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10214 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10215 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10216 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10217 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10218 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10219 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10220 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10221 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10212;
ARCHITECTURE ARCH OF CHIP10212 IS
SIGNAL SIGNAL10222 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10222 <= SIGNAL_IN10216;
SIGNAL_OUT10221 <= SIGNAL_IN10215;
SIGNAL_OUT10220 <= SIGNAL_IN10214;
SIGNAL_OUT10219 <= (SIGNAL_IN10214 + ((((SIGNAL_IN10213 + (SIGNAL_IN10215 xor (SIGNAL_IN10214 or (not SIGNAL_IN10216)))) + TO_UNSIGNED(4096336452, 32)) + SIGNAL_IN10217) rol 6));
SIGNAL10222 <= SIGNAL_IN10216;
END ARCHITECTURE ARCH;
ENTITY CHIP10223 IS
PORT(SIGNAL_IN10224 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10225 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10226 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10227 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10228 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10229 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10230 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10231 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10232 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10223;
ARCHITECTURE ARCH OF CHIP10223 IS
SIGNAL SIGNAL10233 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10233 <= SIGNAL_IN10227;
SIGNAL_OUT10232 <= SIGNAL_IN10226;
SIGNAL_OUT10231 <= SIGNAL_IN10225;
SIGNAL_OUT10230 <= (SIGNAL_IN10225 + ((((SIGNAL_IN10224 + (SIGNAL_IN10226 xor (SIGNAL_IN10225 or (not SIGNAL_IN10227)))) + TO_UNSIGNED(1126891415, 32)) + SIGNAL_IN10228) rol 10));
SIGNAL10233 <= SIGNAL_IN10227;
END ARCHITECTURE ARCH;
ENTITY CHIP10234 IS
PORT(SIGNAL_IN10235 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10236 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10237 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10238 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10239 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10240 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10241 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10242 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10243 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10234;
ARCHITECTURE ARCH OF CHIP10234 IS
SIGNAL SIGNAL10244 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10244 <= SIGNAL_IN10238;
SIGNAL_OUT10243 <= SIGNAL_IN10237;
SIGNAL_OUT10242 <= SIGNAL_IN10236;
SIGNAL_OUT10241 <= (SIGNAL_IN10236 + ((((SIGNAL_IN10235 + (SIGNAL_IN10237 xor (SIGNAL_IN10236 or (not SIGNAL_IN10238)))) + TO_UNSIGNED(2878612391, 32)) + SIGNAL_IN10239) rol 15));
SIGNAL10244 <= SIGNAL_IN10238;
END ARCHITECTURE ARCH;
ENTITY CHIP10245 IS
PORT(SIGNAL_IN10246 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10247 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10248 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10249 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10250 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10251 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10252 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10253 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10254 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10245;
ARCHITECTURE ARCH OF CHIP10245 IS
SIGNAL SIGNAL10255 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10255 <= SIGNAL_IN10249;
SIGNAL_OUT10254 <= SIGNAL_IN10248;
SIGNAL_OUT10253 <= SIGNAL_IN10247;
SIGNAL_OUT10252 <= (SIGNAL_IN10247 + ((((SIGNAL_IN10246 + (SIGNAL_IN10248 xor (SIGNAL_IN10247 or (not SIGNAL_IN10249)))) + TO_UNSIGNED(4237533241, 32)) + SIGNAL_IN10250) rol 21));
SIGNAL10255 <= SIGNAL_IN10249;
END ARCHITECTURE ARCH;
ENTITY CHIP10256 IS
PORT(SIGNAL_IN10257 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10258 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10259 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10260 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10261 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10262 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10263 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10264 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10265 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10256;
ARCHITECTURE ARCH OF CHIP10256 IS
SIGNAL SIGNAL10266 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10266 <= SIGNAL_IN10260;
SIGNAL_OUT10265 <= SIGNAL_IN10259;
SIGNAL_OUT10264 <= SIGNAL_IN10258;
SIGNAL_OUT10263 <= (SIGNAL_IN10258 + ((((SIGNAL_IN10257 + (SIGNAL_IN10259 xor (SIGNAL_IN10258 or (not SIGNAL_IN10260)))) + TO_UNSIGNED(1700485571, 32)) + SIGNAL_IN10261) rol 6));
SIGNAL10266 <= SIGNAL_IN10260;
END ARCHITECTURE ARCH;
ENTITY CHIP10267 IS
PORT(SIGNAL_IN10268 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10269 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10270 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10271 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10272 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10273 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10274 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10275 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10276 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10267;
ARCHITECTURE ARCH OF CHIP10267 IS
SIGNAL SIGNAL10277 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10277 <= SIGNAL_IN10271;
SIGNAL_OUT10276 <= SIGNAL_IN10270;
SIGNAL_OUT10275 <= SIGNAL_IN10269;
SIGNAL_OUT10274 <= (SIGNAL_IN10269 + ((((SIGNAL_IN10268 + (SIGNAL_IN10270 xor (SIGNAL_IN10269 or (not SIGNAL_IN10271)))) + TO_UNSIGNED(2399980690, 32)) + SIGNAL_IN10272) rol 10));
SIGNAL10277 <= SIGNAL_IN10271;
END ARCHITECTURE ARCH;
ENTITY CHIP10278 IS
PORT(SIGNAL_IN10279 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10280 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10281 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10282 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10283 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10284 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10285 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10286 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10287 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10278;
ARCHITECTURE ARCH OF CHIP10278 IS
SIGNAL SIGNAL10288 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10288 <= SIGNAL_IN10282;
SIGNAL_OUT10287 <= SIGNAL_IN10281;
SIGNAL_OUT10286 <= SIGNAL_IN10280;
SIGNAL_OUT10285 <= (SIGNAL_IN10280 + ((((SIGNAL_IN10279 + (SIGNAL_IN10281 xor (SIGNAL_IN10280 or (not SIGNAL_IN10282)))) + TO_UNSIGNED(4293915773, 32)) + SIGNAL_IN10283) rol 15));
SIGNAL10288 <= SIGNAL_IN10282;
END ARCHITECTURE ARCH;
ENTITY CHIP10289 IS
PORT(SIGNAL_IN10290 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10291 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10292 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10293 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10294 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10295 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10296 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10297 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10298 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10289;
ARCHITECTURE ARCH OF CHIP10289 IS
SIGNAL SIGNAL10299 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10299 <= SIGNAL_IN10293;
SIGNAL_OUT10298 <= SIGNAL_IN10292;
SIGNAL_OUT10297 <= SIGNAL_IN10291;
SIGNAL_OUT10296 <= (SIGNAL_IN10291 + ((((SIGNAL_IN10290 + (SIGNAL_IN10292 xor (SIGNAL_IN10291 or (not SIGNAL_IN10293)))) + TO_UNSIGNED(2240044497, 32)) + SIGNAL_IN10294) rol 21));
SIGNAL10299 <= SIGNAL_IN10293;
END ARCHITECTURE ARCH;
ENTITY CHIP10300 IS
PORT(SIGNAL_IN10301 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10302 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10303 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10304 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10305 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10306 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10307 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10308 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10309 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10300;
ARCHITECTURE ARCH OF CHIP10300 IS
SIGNAL SIGNAL10310 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10310 <= SIGNAL_IN10304;
SIGNAL_OUT10309 <= SIGNAL_IN10303;
SIGNAL_OUT10308 <= SIGNAL_IN10302;
SIGNAL_OUT10307 <= (SIGNAL_IN10302 + ((((SIGNAL_IN10301 + (SIGNAL_IN10303 xor (SIGNAL_IN10302 or (not SIGNAL_IN10304)))) + TO_UNSIGNED(1873313359, 32)) + SIGNAL_IN10305) rol 6));
SIGNAL10310 <= SIGNAL_IN10304;
END ARCHITECTURE ARCH;
ENTITY CHIP10311 IS
PORT(SIGNAL_IN10312 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10313 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10314 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10315 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10316 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10317 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10318 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10319 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10320 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10311;
ARCHITECTURE ARCH OF CHIP10311 IS
SIGNAL SIGNAL10321 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10321 <= SIGNAL_IN10315;
SIGNAL_OUT10320 <= SIGNAL_IN10314;
SIGNAL_OUT10319 <= SIGNAL_IN10313;
SIGNAL_OUT10318 <= (SIGNAL_IN10313 + ((((SIGNAL_IN10312 + (SIGNAL_IN10314 xor (SIGNAL_IN10313 or (not SIGNAL_IN10315)))) + TO_UNSIGNED(4264355552, 32)) + SIGNAL_IN10316) rol 10));
SIGNAL10321 <= SIGNAL_IN10315;
END ARCHITECTURE ARCH;
ENTITY CHIP10322 IS
PORT(SIGNAL_IN10323 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10324 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10325 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10326 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10327 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10328 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10329 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10330 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10331 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10322;
ARCHITECTURE ARCH OF CHIP10322 IS
SIGNAL SIGNAL10332 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10332 <= SIGNAL_IN10326;
SIGNAL_OUT10331 <= SIGNAL_IN10325;
SIGNAL_OUT10330 <= SIGNAL_IN10324;
SIGNAL_OUT10329 <= (SIGNAL_IN10324 + ((((SIGNAL_IN10323 + (SIGNAL_IN10325 xor (SIGNAL_IN10324 or (not SIGNAL_IN10326)))) + TO_UNSIGNED(2734768916, 32)) + SIGNAL_IN10327) rol 15));
SIGNAL10332 <= SIGNAL_IN10326;
END ARCHITECTURE ARCH;
ENTITY CHIP10333 IS
PORT(SIGNAL_IN10334 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10335 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10336 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10337 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10338 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10339 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10340 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10341 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10342 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10333;
ARCHITECTURE ARCH OF CHIP10333 IS
SIGNAL SIGNAL10343 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10343 <= SIGNAL_IN10337;
SIGNAL_OUT10342 <= SIGNAL_IN10336;
SIGNAL_OUT10341 <= SIGNAL_IN10335;
SIGNAL_OUT10340 <= (SIGNAL_IN10335 + ((((SIGNAL_IN10334 + (SIGNAL_IN10336 xor (SIGNAL_IN10335 or (not SIGNAL_IN10337)))) + TO_UNSIGNED(1309151649, 32)) + SIGNAL_IN10338) rol 21));
SIGNAL10343 <= SIGNAL_IN10337;
END ARCHITECTURE ARCH;
ENTITY CHIP10344 IS
PORT(SIGNAL_IN10345 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10346 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10347 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10348 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10349 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10350 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10351 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10352 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10353 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10344;
ARCHITECTURE ARCH OF CHIP10344 IS
SIGNAL SIGNAL10354 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10354 <= SIGNAL_IN10348;
SIGNAL_OUT10353 <= SIGNAL_IN10347;
SIGNAL_OUT10352 <= SIGNAL_IN10346;
SIGNAL_OUT10351 <= (SIGNAL_IN10346 + ((((SIGNAL_IN10345 + (SIGNAL_IN10347 xor (SIGNAL_IN10346 or (not SIGNAL_IN10348)))) + TO_UNSIGNED(4149444226, 32)) + SIGNAL_IN10349) rol 6));
SIGNAL10354 <= SIGNAL_IN10348;
END ARCHITECTURE ARCH;
ENTITY CHIP10355 IS
PORT(SIGNAL_IN10356 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10357 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10358 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10359 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10360 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10361 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10362 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10363 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10364 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10355;
ARCHITECTURE ARCH OF CHIP10355 IS
SIGNAL SIGNAL10365 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10365 <= SIGNAL_IN10359;
SIGNAL_OUT10364 <= SIGNAL_IN10358;
SIGNAL_OUT10363 <= SIGNAL_IN10357;
SIGNAL_OUT10362 <= (SIGNAL_IN10357 + ((((SIGNAL_IN10356 + (SIGNAL_IN10358 xor (SIGNAL_IN10357 or (not SIGNAL_IN10359)))) + TO_UNSIGNED(3174756917, 32)) + SIGNAL_IN10360) rol 10));
SIGNAL10365 <= SIGNAL_IN10359;
END ARCHITECTURE ARCH;
ENTITY CHIP10366 IS
PORT(SIGNAL_IN10367 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10368 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10369 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10370 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10371 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10372 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10373 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10374 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10375 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10366;
ARCHITECTURE ARCH OF CHIP10366 IS
SIGNAL SIGNAL10376 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10376 <= SIGNAL_IN10370;
SIGNAL_OUT10375 <= SIGNAL_IN10369;
SIGNAL_OUT10374 <= SIGNAL_IN10368;
SIGNAL_OUT10373 <= (SIGNAL_IN10368 + ((((SIGNAL_IN10367 + (SIGNAL_IN10369 xor (SIGNAL_IN10368 or (not SIGNAL_IN10370)))) + TO_UNSIGNED(718787259, 32)) + SIGNAL_IN10371) rol 15));
SIGNAL10376 <= SIGNAL_IN10370;
END ARCHITECTURE ARCH;
ENTITY CHIP10377 IS
PORT(SIGNAL_IN10378 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10379 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10380 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10381 : IN UNSIGNED(31 downto 0);
SIGNAL_IN10382 : IN UNSIGNED(31 downto 0);
SIGNAL_OUT10383 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10384 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10385 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT10386 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP10377;
ARCHITECTURE ARCH OF CHIP10377 IS
SIGNAL SIGNAL10387 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL10387 <= SIGNAL_IN10381;
SIGNAL_OUT10386 <= SIGNAL_IN10380;
SIGNAL_OUT10385 <= SIGNAL_IN10379;
SIGNAL_OUT10384 <= (SIGNAL_IN10379 + ((((SIGNAL_IN10378 + (SIGNAL_IN10380 xor (SIGNAL_IN10379 or (not SIGNAL_IN10381)))) + TO_UNSIGNED(3951481745, 32)) + SIGNAL_IN10382) rol 21));
SIGNAL10387 <= SIGNAL_IN10381;
END ARCHITECTURE ARCH;
ENTITY CHIP9398 IS
PORT(SIGNAL_IN9399 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9400 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9401 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9402 : IN UNSIGNED(31 downto 0);
SIGNAL_IN9403 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
SIGNAL_OUT9404 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9405 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9406 : OUT UNSIGNED(31 downto 0);
SIGNAL_OUT9407 : OUT UNSIGNED(31 downto 0));
BEGIN
END ENTITY CHIP9398;
ARCHITECTURE ARCH OF CHIP9398 IS
SIGNAL SIGNAL9408 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9409 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9410 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9411 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9412 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9413 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9414 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9415 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9416 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9417 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9418 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9419 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9420 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9421 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9422 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9423 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9424 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9425 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9426 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9427 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9428 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9429 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9430 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9431 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9432 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9433 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9434 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9435 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9436 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9437 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9438 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9439 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9440 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9441 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9442 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9443 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9444 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9445 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9446 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9447 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9448 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9449 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9450 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9451 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9452 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9453 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9454 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9455 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9456 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9457 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9458 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9459 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9460 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9461 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9462 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9463 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9464 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9465 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9466 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9467 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9468 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9469 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9470 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9471 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9472 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9473 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9474 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9475 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9476 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9477 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9478 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9479 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9480 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9481 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9482 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9483 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9484 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9485 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9486 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9487 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9488 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9489 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9490 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9491 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9492 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9493 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9494 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9495 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9496 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9497 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9498 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9499 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9500 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9501 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9502 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9503 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9504 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9505 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9506 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9507 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9508 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9509 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9510 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9511 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9512 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9513 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9514 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9515 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9516 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9517 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9518 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9519 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9520 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9521 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9522 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9523 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9524 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9525 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9526 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9527 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9528 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9529 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9530 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9531 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9532 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9533 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9534 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9535 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9536 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9537 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9538 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9539 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9540 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9541 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9542 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9543 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9544 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9545 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9546 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9547 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9548 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9549 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9550 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9551 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9552 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9553 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9554 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9555 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9556 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9557 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9558 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9559 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9560 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9561 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9562 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9563 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9564 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9565 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9566 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9567 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9568 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9569 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9570 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9571 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9572 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9573 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9574 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9575 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9576 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9577 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9578 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9579 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9580 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9581 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9582 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9583 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9584 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9585 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9586 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9587 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9588 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9589 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9590 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9591 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9592 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9593 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9594 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9595 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9596 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9597 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9598 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9599 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9600 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9601 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9602 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9603 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9604 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9605 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9606 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9607 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9608 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9609 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9610 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9611 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9612 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9613 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9614 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9615 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9616 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9617 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9618 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9619 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9620 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9621 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9622 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9623 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9624 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9625 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9626 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9627 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9628 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9629 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9630 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9631 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9632 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9633 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9634 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9635 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9636 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9637 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9638 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9639 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9640 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9641 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9642 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9643 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9644 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9645 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9646 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9647 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9648 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9649 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9650 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9651 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9652 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9653 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9654 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9655 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9656 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9657 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9658 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9659 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9660 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9661 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9662 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9663 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9664 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9665 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9666 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9667 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9668 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9669 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9670 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9671 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9672 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9673 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9674 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9675 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9676 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9677 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9678 : UNSIGNED(31 downto 0);
SIGNAL SIGNAL9679 : UNSIGNED(31 downto 0);
BEGIN
SIGNAL9408 <= UNSIGNED(SIGNAL_IN9403(31 DOWNTO 0));
SIGNAL9409 <= UNSIGNED(SIGNAL_IN9403(63 DOWNTO 32));
SIGNAL9410 <= UNSIGNED(SIGNAL_IN9403(95 DOWNTO 64));
SIGNAL9411 <= UNSIGNED(SIGNAL_IN9403(127 DOWNTO 96));
SIGNAL9412 <= UNSIGNED(SIGNAL_IN9403(159 DOWNTO 128));
SIGNAL9413 <= UNSIGNED(SIGNAL_IN9403(191 DOWNTO 160));
SIGNAL9414 <= UNSIGNED(SIGNAL_IN9403(223 DOWNTO 192));
SIGNAL9415 <= UNSIGNED(SIGNAL_IN9403(255 DOWNTO 224));
SIGNAL9416 <= UNSIGNED(SIGNAL_IN9403(287 DOWNTO 256));
SIGNAL9417 <= UNSIGNED(SIGNAL_IN9403(319 DOWNTO 288));
SIGNAL9418 <= UNSIGNED(SIGNAL_IN9403(351 DOWNTO 320));
SIGNAL9419 <= UNSIGNED(SIGNAL_IN9403(383 DOWNTO 352));
SIGNAL9420 <= UNSIGNED(SIGNAL_IN9403(415 DOWNTO 384));
SIGNAL9421 <= UNSIGNED(SIGNAL_IN9403(447 DOWNTO 416));
SIGNAL9422 <= UNSIGNED(SIGNAL_IN9403(479 DOWNTO 448));
SIGNAL9423 <= UNSIGNED(SIGNAL_IN9403(511 DOWNTO 480));
CHIP_INST10388 : ENTITY CHIP9684(ARCH) PORT MAP(SIGNAL_IN9685 => SIGNAL_IN9399
, SIGNAL_IN9686 => SIGNAL_IN9400
, SIGNAL_IN9687 => SIGNAL_IN9401
, SIGNAL_IN9688 => SIGNAL_IN9402
, SIGNAL_IN9689 => SIGNAL9408
, SIGNAL_OUT9690 => SIGNAL9425
, SIGNAL_OUT9691 => SIGNAL9489
, SIGNAL_OUT9692 => SIGNAL9553
, SIGNAL_OUT9693 => SIGNAL9617
);
CHIP_INST10389 : ENTITY CHIP9695(ARCH) PORT MAP(SIGNAL_IN9696 => SIGNAL9425
, SIGNAL_IN9697 => SIGNAL9489
, SIGNAL_IN9698 => SIGNAL9553
, SIGNAL_IN9699 => SIGNAL9617
, SIGNAL_IN9700 => SIGNAL9409
, SIGNAL_OUT9701 => SIGNAL9426
, SIGNAL_OUT9702 => SIGNAL9490
, SIGNAL_OUT9703 => SIGNAL9554
, SIGNAL_OUT9704 => SIGNAL9618
);
CHIP_INST10390 : ENTITY CHIP9706(ARCH) PORT MAP(SIGNAL_IN9707 => SIGNAL9426
, SIGNAL_IN9708 => SIGNAL9490
, SIGNAL_IN9709 => SIGNAL9554
, SIGNAL_IN9710 => SIGNAL9618
, SIGNAL_IN9711 => SIGNAL9410
, SIGNAL_OUT9712 => SIGNAL9427
, SIGNAL_OUT9713 => SIGNAL9491
, SIGNAL_OUT9714 => SIGNAL9555
, SIGNAL_OUT9715 => SIGNAL9619
);
CHIP_INST10391 : ENTITY CHIP9717(ARCH) PORT MAP(SIGNAL_IN9718 => SIGNAL9427
, SIGNAL_IN9719 => SIGNAL9491
, SIGNAL_IN9720 => SIGNAL9555
, SIGNAL_IN9721 => SIGNAL9619
, SIGNAL_IN9722 => SIGNAL9411
, SIGNAL_OUT9723 => SIGNAL9428
, SIGNAL_OUT9724 => SIGNAL9492
, SIGNAL_OUT9725 => SIGNAL9556
, SIGNAL_OUT9726 => SIGNAL9620
);
CHIP_INST10392 : ENTITY CHIP9728(ARCH) PORT MAP(SIGNAL_IN9729 => SIGNAL9428
, SIGNAL_IN9730 => SIGNAL9492
, SIGNAL_IN9731 => SIGNAL9556
, SIGNAL_IN9732 => SIGNAL9620
, SIGNAL_IN9733 => SIGNAL9412
, SIGNAL_OUT9734 => SIGNAL9429
, SIGNAL_OUT9735 => SIGNAL9493
, SIGNAL_OUT9736 => SIGNAL9557
, SIGNAL_OUT9737 => SIGNAL9621
);
CHIP_INST10393 : ENTITY CHIP9739(ARCH) PORT MAP(SIGNAL_IN9740 => SIGNAL9429
, SIGNAL_IN9741 => SIGNAL9493
, SIGNAL_IN9742 => SIGNAL9557
, SIGNAL_IN9743 => SIGNAL9621
, SIGNAL_IN9744 => SIGNAL9413
, SIGNAL_OUT9745 => SIGNAL9430
, SIGNAL_OUT9746 => SIGNAL9494
, SIGNAL_OUT9747 => SIGNAL9558
, SIGNAL_OUT9748 => SIGNAL9622
);
CHIP_INST10394 : ENTITY CHIP9750(ARCH) PORT MAP(SIGNAL_IN9751 => SIGNAL9430
, SIGNAL_IN9752 => SIGNAL9494
, SIGNAL_IN9753 => SIGNAL9558
, SIGNAL_IN9754 => SIGNAL9622
, SIGNAL_IN9755 => SIGNAL9414
, SIGNAL_OUT9756 => SIGNAL9431
, SIGNAL_OUT9757 => SIGNAL9495
, SIGNAL_OUT9758 => SIGNAL9559
, SIGNAL_OUT9759 => SIGNAL9623
);
CHIP_INST10395 : ENTITY CHIP9761(ARCH) PORT MAP(SIGNAL_IN9762 => SIGNAL9431
, SIGNAL_IN9763 => SIGNAL9495
, SIGNAL_IN9764 => SIGNAL9559
, SIGNAL_IN9765 => SIGNAL9623
, SIGNAL_IN9766 => SIGNAL9415
, SIGNAL_OUT9767 => SIGNAL9432
, SIGNAL_OUT9768 => SIGNAL9496
, SIGNAL_OUT9769 => SIGNAL9560
, SIGNAL_OUT9770 => SIGNAL9624
);
CHIP_INST10396 : ENTITY CHIP9772(ARCH) PORT MAP(SIGNAL_IN9773 => SIGNAL9432
, SIGNAL_IN9774 => SIGNAL9496
, SIGNAL_IN9775 => SIGNAL9560
, SIGNAL_IN9776 => SIGNAL9624
, SIGNAL_IN9777 => SIGNAL9416
, SIGNAL_OUT9778 => SIGNAL9433
, SIGNAL_OUT9779 => SIGNAL9497
, SIGNAL_OUT9780 => SIGNAL9561
, SIGNAL_OUT9781 => SIGNAL9625
);
CHIP_INST10397 : ENTITY CHIP9783(ARCH) PORT MAP(SIGNAL_IN9784 => SIGNAL9433
, SIGNAL_IN9785 => SIGNAL9497
, SIGNAL_IN9786 => SIGNAL9561
, SIGNAL_IN9787 => SIGNAL9625
, SIGNAL_IN9788 => SIGNAL9417
, SIGNAL_OUT9789 => SIGNAL9434
, SIGNAL_OUT9790 => SIGNAL9498
, SIGNAL_OUT9791 => SIGNAL9562
, SIGNAL_OUT9792 => SIGNAL9626
);
CHIP_INST10398 : ENTITY CHIP9794(ARCH) PORT MAP(SIGNAL_IN9795 => SIGNAL9434
, SIGNAL_IN9796 => SIGNAL9498
, SIGNAL_IN9797 => SIGNAL9562
, SIGNAL_IN9798 => SIGNAL9626
, SIGNAL_IN9799 => SIGNAL9418
, SIGNAL_OUT9800 => SIGNAL9435
, SIGNAL_OUT9801 => SIGNAL9499
, SIGNAL_OUT9802 => SIGNAL9563
, SIGNAL_OUT9803 => SIGNAL9627
);
CHIP_INST10399 : ENTITY CHIP9805(ARCH) PORT MAP(SIGNAL_IN9806 => SIGNAL9435
, SIGNAL_IN9807 => SIGNAL9499
, SIGNAL_IN9808 => SIGNAL9563
, SIGNAL_IN9809 => SIGNAL9627
, SIGNAL_IN9810 => SIGNAL9419
, SIGNAL_OUT9811 => SIGNAL9436
, SIGNAL_OUT9812 => SIGNAL9500
, SIGNAL_OUT9813 => SIGNAL9564
, SIGNAL_OUT9814 => SIGNAL9628
);
CHIP_INST10400 : ENTITY CHIP9816(ARCH) PORT MAP(SIGNAL_IN9817 => SIGNAL9436
, SIGNAL_IN9818 => SIGNAL9500
, SIGNAL_IN9819 => SIGNAL9564
, SIGNAL_IN9820 => SIGNAL9628
, SIGNAL_IN9821 => SIGNAL9420
, SIGNAL_OUT9822 => SIGNAL9437
, SIGNAL_OUT9823 => SIGNAL9501
, SIGNAL_OUT9824 => SIGNAL9565
, SIGNAL_OUT9825 => SIGNAL9629
);
CHIP_INST10401 : ENTITY CHIP9827(ARCH) PORT MAP(SIGNAL_IN9828 => SIGNAL9437
, SIGNAL_IN9829 => SIGNAL9501
, SIGNAL_IN9830 => SIGNAL9565
, SIGNAL_IN9831 => SIGNAL9629
, SIGNAL_IN9832 => SIGNAL9421
, SIGNAL_OUT9833 => SIGNAL9438
, SIGNAL_OUT9834 => SIGNAL9502
, SIGNAL_OUT9835 => SIGNAL9566
, SIGNAL_OUT9836 => SIGNAL9630
);
CHIP_INST10402 : ENTITY CHIP9838(ARCH) PORT MAP(SIGNAL_IN9839 => SIGNAL9438
, SIGNAL_IN9840 => SIGNAL9502
, SIGNAL_IN9841 => SIGNAL9566
, SIGNAL_IN9842 => SIGNAL9630
, SIGNAL_IN9843 => SIGNAL9422
, SIGNAL_OUT9844 => SIGNAL9439
, SIGNAL_OUT9845 => SIGNAL9503
, SIGNAL_OUT9846 => SIGNAL9567
, SIGNAL_OUT9847 => SIGNAL9631
);
CHIP_INST10403 : ENTITY CHIP9849(ARCH) PORT MAP(SIGNAL_IN9850 => SIGNAL9439
, SIGNAL_IN9851 => SIGNAL9503
, SIGNAL_IN9852 => SIGNAL9567
, SIGNAL_IN9853 => SIGNAL9631
, SIGNAL_IN9854 => SIGNAL9423
, SIGNAL_OUT9855 => SIGNAL9440
, SIGNAL_OUT9856 => SIGNAL9504
, SIGNAL_OUT9857 => SIGNAL9568
, SIGNAL_OUT9858 => SIGNAL9632
);
CHIP_INST10404 : ENTITY CHIP9860(ARCH) PORT MAP(SIGNAL_IN9861 => SIGNAL9440
, SIGNAL_IN9862 => SIGNAL9504
, SIGNAL_IN9863 => SIGNAL9568
, SIGNAL_IN9864 => SIGNAL9632
, SIGNAL_IN9865 => SIGNAL9409
, SIGNAL_OUT9866 => SIGNAL9441
, SIGNAL_OUT9867 => SIGNAL9505
, SIGNAL_OUT9868 => SIGNAL9569
, SIGNAL_OUT9869 => SIGNAL9633
);
CHIP_INST10405 : ENTITY CHIP9871(ARCH) PORT MAP(SIGNAL_IN9872 => SIGNAL9441
, SIGNAL_IN9873 => SIGNAL9505
, SIGNAL_IN9874 => SIGNAL9569
, SIGNAL_IN9875 => SIGNAL9633
, SIGNAL_IN9876 => SIGNAL9414
, SIGNAL_OUT9877 => SIGNAL9442
, SIGNAL_OUT9878 => SIGNAL9506
, SIGNAL_OUT9879 => SIGNAL9570
, SIGNAL_OUT9880 => SIGNAL9634
);
CHIP_INST10406 : ENTITY CHIP9882(ARCH) PORT MAP(SIGNAL_IN9883 => SIGNAL9442
, SIGNAL_IN9884 => SIGNAL9506
, SIGNAL_IN9885 => SIGNAL9570
, SIGNAL_IN9886 => SIGNAL9634
, SIGNAL_IN9887 => SIGNAL9419
, SIGNAL_OUT9888 => SIGNAL9443
, SIGNAL_OUT9889 => SIGNAL9507
, SIGNAL_OUT9890 => SIGNAL9571
, SIGNAL_OUT9891 => SIGNAL9635
);
CHIP_INST10407 : ENTITY CHIP9893(ARCH) PORT MAP(SIGNAL_IN9894 => SIGNAL9443
, SIGNAL_IN9895 => SIGNAL9507
, SIGNAL_IN9896 => SIGNAL9571
, SIGNAL_IN9897 => SIGNAL9635
, SIGNAL_IN9898 => SIGNAL9408
, SIGNAL_OUT9899 => SIGNAL9444
, SIGNAL_OUT9900 => SIGNAL9508
, SIGNAL_OUT9901 => SIGNAL9572
, SIGNAL_OUT9902 => SIGNAL9636
);
CHIP_INST10408 : ENTITY CHIP9904(ARCH) PORT MAP(SIGNAL_IN9905 => SIGNAL9444
, SIGNAL_IN9906 => SIGNAL9508
, SIGNAL_IN9907 => SIGNAL9572
, SIGNAL_IN9908 => SIGNAL9636
, SIGNAL_IN9909 => SIGNAL9413
, SIGNAL_OUT9910 => SIGNAL9445
, SIGNAL_OUT9911 => SIGNAL9509
, SIGNAL_OUT9912 => SIGNAL9573
, SIGNAL_OUT9913 => SIGNAL9637
);
CHIP_INST10409 : ENTITY CHIP9915(ARCH) PORT MAP(SIGNAL_IN9916 => SIGNAL9445
, SIGNAL_IN9917 => SIGNAL9509
, SIGNAL_IN9918 => SIGNAL9573
, SIGNAL_IN9919 => SIGNAL9637
, SIGNAL_IN9920 => SIGNAL9418
, SIGNAL_OUT9921 => SIGNAL9446
, SIGNAL_OUT9922 => SIGNAL9510
, SIGNAL_OUT9923 => SIGNAL9574
, SIGNAL_OUT9924 => SIGNAL9638
);
CHIP_INST10410 : ENTITY CHIP9926(ARCH) PORT MAP(SIGNAL_IN9927 => SIGNAL9446
, SIGNAL_IN9928 => SIGNAL9510
, SIGNAL_IN9929 => SIGNAL9574
, SIGNAL_IN9930 => SIGNAL9638
, SIGNAL_IN9931 => SIGNAL9423
, SIGNAL_OUT9932 => SIGNAL9447
, SIGNAL_OUT9933 => SIGNAL9511
, SIGNAL_OUT9934 => SIGNAL9575
, SIGNAL_OUT9935 => SIGNAL9639
);
CHIP_INST10411 : ENTITY CHIP9937(ARCH) PORT MAP(SIGNAL_IN9938 => SIGNAL9447
, SIGNAL_IN9939 => SIGNAL9511
, SIGNAL_IN9940 => SIGNAL9575
, SIGNAL_IN9941 => SIGNAL9639
, SIGNAL_IN9942 => SIGNAL9412
, SIGNAL_OUT9943 => SIGNAL9448
, SIGNAL_OUT9944 => SIGNAL9512
, SIGNAL_OUT9945 => SIGNAL9576
, SIGNAL_OUT9946 => SIGNAL9640
);
CHIP_INST10412 : ENTITY CHIP9948(ARCH) PORT MAP(SIGNAL_IN9949 => SIGNAL9448
, SIGNAL_IN9950 => SIGNAL9512
, SIGNAL_IN9951 => SIGNAL9576
, SIGNAL_IN9952 => SIGNAL9640
, SIGNAL_IN9953 => SIGNAL9417
, SIGNAL_OUT9954 => SIGNAL9449
, SIGNAL_OUT9955 => SIGNAL9513
, SIGNAL_OUT9956 => SIGNAL9577
, SIGNAL_OUT9957 => SIGNAL9641
);
CHIP_INST10413 : ENTITY CHIP9959(ARCH) PORT MAP(SIGNAL_IN9960 => SIGNAL9449
, SIGNAL_IN9961 => SIGNAL9513
, SIGNAL_IN9962 => SIGNAL9577
, SIGNAL_IN9963 => SIGNAL9641
, SIGNAL_IN9964 => SIGNAL9422
, SIGNAL_OUT9965 => SIGNAL9450
, SIGNAL_OUT9966 => SIGNAL9514
, SIGNAL_OUT9967 => SIGNAL9578
, SIGNAL_OUT9968 => SIGNAL9642
);
CHIP_INST10414 : ENTITY CHIP9970(ARCH) PORT MAP(SIGNAL_IN9971 => SIGNAL9450
, SIGNAL_IN9972 => SIGNAL9514
, SIGNAL_IN9973 => SIGNAL9578
, SIGNAL_IN9974 => SIGNAL9642
, SIGNAL_IN9975 => SIGNAL9411
, SIGNAL_OUT9976 => SIGNAL9451
, SIGNAL_OUT9977 => SIGNAL9515
, SIGNAL_OUT9978 => SIGNAL9579
, SIGNAL_OUT9979 => SIGNAL9643
);
CHIP_INST10415 : ENTITY CHIP9981(ARCH) PORT MAP(SIGNAL_IN9982 => SIGNAL9451
, SIGNAL_IN9983 => SIGNAL9515
, SIGNAL_IN9984 => SIGNAL9579
, SIGNAL_IN9985 => SIGNAL9643
, SIGNAL_IN9986 => SIGNAL9416
, SIGNAL_OUT9987 => SIGNAL9452
, SIGNAL_OUT9988 => SIGNAL9516
, SIGNAL_OUT9989 => SIGNAL9580
, SIGNAL_OUT9990 => SIGNAL9644
);
CHIP_INST10416 : ENTITY CHIP9992(ARCH) PORT MAP(SIGNAL_IN9993 => SIGNAL9452
, SIGNAL_IN9994 => SIGNAL9516
, SIGNAL_IN9995 => SIGNAL9580
, SIGNAL_IN9996 => SIGNAL9644
, SIGNAL_IN9997 => SIGNAL9421
, SIGNAL_OUT9998 => SIGNAL9453
, SIGNAL_OUT9999 => SIGNAL9517
, SIGNAL_OUT10000 => SIGNAL9581
, SIGNAL_OUT10001 => SIGNAL9645
);
CHIP_INST10417 : ENTITY CHIP10003(ARCH) PORT MAP(SIGNAL_IN10004 => SIGNAL9453
, SIGNAL_IN10005 => SIGNAL9517
, SIGNAL_IN10006 => SIGNAL9581
, SIGNAL_IN10007 => SIGNAL9645
, SIGNAL_IN10008 => SIGNAL9410
, SIGNAL_OUT10009 => SIGNAL9454
, SIGNAL_OUT10010 => SIGNAL9518
, SIGNAL_OUT10011 => SIGNAL9582
, SIGNAL_OUT10012 => SIGNAL9646
);
CHIP_INST10418 : ENTITY CHIP10014(ARCH) PORT MAP(SIGNAL_IN10015 => SIGNAL9454
, SIGNAL_IN10016 => SIGNAL9518
, SIGNAL_IN10017 => SIGNAL9582
, SIGNAL_IN10018 => SIGNAL9646
, SIGNAL_IN10019 => SIGNAL9415
, SIGNAL_OUT10020 => SIGNAL9455
, SIGNAL_OUT10021 => SIGNAL9519
, SIGNAL_OUT10022 => SIGNAL9583
, SIGNAL_OUT10023 => SIGNAL9647
);
CHIP_INST10419 : ENTITY CHIP10025(ARCH) PORT MAP(SIGNAL_IN10026 => SIGNAL9455
, SIGNAL_IN10027 => SIGNAL9519
, SIGNAL_IN10028 => SIGNAL9583
, SIGNAL_IN10029 => SIGNAL9647
, SIGNAL_IN10030 => SIGNAL9420
, SIGNAL_OUT10031 => SIGNAL9456
, SIGNAL_OUT10032 => SIGNAL9520
, SIGNAL_OUT10033 => SIGNAL9584
, SIGNAL_OUT10034 => SIGNAL9648
);
CHIP_INST10420 : ENTITY CHIP10036(ARCH) PORT MAP(SIGNAL_IN10037 => SIGNAL9456
, SIGNAL_IN10038 => SIGNAL9520
, SIGNAL_IN10039 => SIGNAL9584
, SIGNAL_IN10040 => SIGNAL9648
, SIGNAL_IN10041 => SIGNAL9413
, SIGNAL_OUT10042 => SIGNAL9457
, SIGNAL_OUT10043 => SIGNAL9521
, SIGNAL_OUT10044 => SIGNAL9585
, SIGNAL_OUT10045 => SIGNAL9649
);
CHIP_INST10421 : ENTITY CHIP10047(ARCH) PORT MAP(SIGNAL_IN10048 => SIGNAL9457
, SIGNAL_IN10049 => SIGNAL9521
, SIGNAL_IN10050 => SIGNAL9585
, SIGNAL_IN10051 => SIGNAL9649
, SIGNAL_IN10052 => SIGNAL9416
, SIGNAL_OUT10053 => SIGNAL9458
, SIGNAL_OUT10054 => SIGNAL9522
, SIGNAL_OUT10055 => SIGNAL9586
, SIGNAL_OUT10056 => SIGNAL9650
);
CHIP_INST10422 : ENTITY CHIP10058(ARCH) PORT MAP(SIGNAL_IN10059 => SIGNAL9458
, SIGNAL_IN10060 => SIGNAL9522
, SIGNAL_IN10061 => SIGNAL9586
, SIGNAL_IN10062 => SIGNAL9650
, SIGNAL_IN10063 => SIGNAL9419
, SIGNAL_OUT10064 => SIGNAL9459
, SIGNAL_OUT10065 => SIGNAL9523
, SIGNAL_OUT10066 => SIGNAL9587
, SIGNAL_OUT10067 => SIGNAL9651
);
CHIP_INST10423 : ENTITY CHIP10069(ARCH) PORT MAP(SIGNAL_IN10070 => SIGNAL9459
, SIGNAL_IN10071 => SIGNAL9523
, SIGNAL_IN10072 => SIGNAL9587
, SIGNAL_IN10073 => SIGNAL9651
, SIGNAL_IN10074 => SIGNAL9422
, SIGNAL_OUT10075 => SIGNAL9460
, SIGNAL_OUT10076 => SIGNAL9524
, SIGNAL_OUT10077 => SIGNAL9588
, SIGNAL_OUT10078 => SIGNAL9652
);
CHIP_INST10424 : ENTITY CHIP10080(ARCH) PORT MAP(SIGNAL_IN10081 => SIGNAL9460
, SIGNAL_IN10082 => SIGNAL9524
, SIGNAL_IN10083 => SIGNAL9588
, SIGNAL_IN10084 => SIGNAL9652
, SIGNAL_IN10085 => SIGNAL9409
, SIGNAL_OUT10086 => SIGNAL9461
, SIGNAL_OUT10087 => SIGNAL9525
, SIGNAL_OUT10088 => SIGNAL9589
, SIGNAL_OUT10089 => SIGNAL9653
);
CHIP_INST10425 : ENTITY CHIP10091(ARCH) PORT MAP(SIGNAL_IN10092 => SIGNAL9461
, SIGNAL_IN10093 => SIGNAL9525
, SIGNAL_IN10094 => SIGNAL9589
, SIGNAL_IN10095 => SIGNAL9653
, SIGNAL_IN10096 => SIGNAL9412
, SIGNAL_OUT10097 => SIGNAL9462
, SIGNAL_OUT10098 => SIGNAL9526
, SIGNAL_OUT10099 => SIGNAL9590
, SIGNAL_OUT10100 => SIGNAL9654
);
CHIP_INST10426 : ENTITY CHIP10102(ARCH) PORT MAP(SIGNAL_IN10103 => SIGNAL9462
, SIGNAL_IN10104 => SIGNAL9526
, SIGNAL_IN10105 => SIGNAL9590
, SIGNAL_IN10106 => SIGNAL9654
, SIGNAL_IN10107 => SIGNAL9415
, SIGNAL_OUT10108 => SIGNAL9463
, SIGNAL_OUT10109 => SIGNAL9527
, SIGNAL_OUT10110 => SIGNAL9591
, SIGNAL_OUT10111 => SIGNAL9655
);
CHIP_INST10427 : ENTITY CHIP10113(ARCH) PORT MAP(SIGNAL_IN10114 => SIGNAL9463
, SIGNAL_IN10115 => SIGNAL9527
, SIGNAL_IN10116 => SIGNAL9591
, SIGNAL_IN10117 => SIGNAL9655
, SIGNAL_IN10118 => SIGNAL9418
, SIGNAL_OUT10119 => SIGNAL9464
, SIGNAL_OUT10120 => SIGNAL9528
, SIGNAL_OUT10121 => SIGNAL9592
, SIGNAL_OUT10122 => SIGNAL9656
);
CHIP_INST10428 : ENTITY CHIP10124(ARCH) PORT MAP(SIGNAL_IN10125 => SIGNAL9464
, SIGNAL_IN10126 => SIGNAL9528
, SIGNAL_IN10127 => SIGNAL9592
, SIGNAL_IN10128 => SIGNAL9656
, SIGNAL_IN10129 => SIGNAL9421
, SIGNAL_OUT10130 => SIGNAL9465
, SIGNAL_OUT10131 => SIGNAL9529
, SIGNAL_OUT10132 => SIGNAL9593
, SIGNAL_OUT10133 => SIGNAL9657
);
CHIP_INST10429 : ENTITY CHIP10135(ARCH) PORT MAP(SIGNAL_IN10136 => SIGNAL9465
, SIGNAL_IN10137 => SIGNAL9529
, SIGNAL_IN10138 => SIGNAL9593
, SIGNAL_IN10139 => SIGNAL9657
, SIGNAL_IN10140 => SIGNAL9408
, SIGNAL_OUT10141 => SIGNAL9466
, SIGNAL_OUT10142 => SIGNAL9530
, SIGNAL_OUT10143 => SIGNAL9594
, SIGNAL_OUT10144 => SIGNAL9658
);
CHIP_INST10430 : ENTITY CHIP10146(ARCH) PORT MAP(SIGNAL_IN10147 => SIGNAL9466
, SIGNAL_IN10148 => SIGNAL9530
, SIGNAL_IN10149 => SIGNAL9594
, SIGNAL_IN10150 => SIGNAL9658
, SIGNAL_IN10151 => SIGNAL9411
, SIGNAL_OUT10152 => SIGNAL9467
, SIGNAL_OUT10153 => SIGNAL9531
, SIGNAL_OUT10154 => SIGNAL9595
, SIGNAL_OUT10155 => SIGNAL9659
);
CHIP_INST10431 : ENTITY CHIP10157(ARCH) PORT MAP(SIGNAL_IN10158 => SIGNAL9467
, SIGNAL_IN10159 => SIGNAL9531
, SIGNAL_IN10160 => SIGNAL9595
, SIGNAL_IN10161 => SIGNAL9659
, SIGNAL_IN10162 => SIGNAL9414
, SIGNAL_OUT10163 => SIGNAL9468
, SIGNAL_OUT10164 => SIGNAL9532
, SIGNAL_OUT10165 => SIGNAL9596
, SIGNAL_OUT10166 => SIGNAL9660
);
CHIP_INST10432 : ENTITY CHIP10168(ARCH) PORT MAP(SIGNAL_IN10169 => SIGNAL9468
, SIGNAL_IN10170 => SIGNAL9532
, SIGNAL_IN10171 => SIGNAL9596
, SIGNAL_IN10172 => SIGNAL9660
, SIGNAL_IN10173 => SIGNAL9417
, SIGNAL_OUT10174 => SIGNAL9469
, SIGNAL_OUT10175 => SIGNAL9533
, SIGNAL_OUT10176 => SIGNAL9597
, SIGNAL_OUT10177 => SIGNAL9661
);
CHIP_INST10433 : ENTITY CHIP10179(ARCH) PORT MAP(SIGNAL_IN10180 => SIGNAL9469
, SIGNAL_IN10181 => SIGNAL9533
, SIGNAL_IN10182 => SIGNAL9597
, SIGNAL_IN10183 => SIGNAL9661
, SIGNAL_IN10184 => SIGNAL9420
, SIGNAL_OUT10185 => SIGNAL9470
, SIGNAL_OUT10186 => SIGNAL9534
, SIGNAL_OUT10187 => SIGNAL9598
, SIGNAL_OUT10188 => SIGNAL9662
);
CHIP_INST10434 : ENTITY CHIP10190(ARCH) PORT MAP(SIGNAL_IN10191 => SIGNAL9470
, SIGNAL_IN10192 => SIGNAL9534
, SIGNAL_IN10193 => SIGNAL9598
, SIGNAL_IN10194 => SIGNAL9662
, SIGNAL_IN10195 => SIGNAL9423
, SIGNAL_OUT10196 => SIGNAL9471
, SIGNAL_OUT10197 => SIGNAL9535
, SIGNAL_OUT10198 => SIGNAL9599
, SIGNAL_OUT10199 => SIGNAL9663
);
CHIP_INST10435 : ENTITY CHIP10201(ARCH) PORT MAP(SIGNAL_IN10202 => SIGNAL9471
, SIGNAL_IN10203 => SIGNAL9535
, SIGNAL_IN10204 => SIGNAL9599
, SIGNAL_IN10205 => SIGNAL9663
, SIGNAL_IN10206 => SIGNAL9410
, SIGNAL_OUT10207 => SIGNAL9472
, SIGNAL_OUT10208 => SIGNAL9536
, SIGNAL_OUT10209 => SIGNAL9600
, SIGNAL_OUT10210 => SIGNAL9664
);
CHIP_INST10436 : ENTITY CHIP10212(ARCH) PORT MAP(SIGNAL_IN10213 => SIGNAL9472
, SIGNAL_IN10214 => SIGNAL9536
, SIGNAL_IN10215 => SIGNAL9600
, SIGNAL_IN10216 => SIGNAL9664
, SIGNAL_IN10217 => SIGNAL9408
, SIGNAL_OUT10218 => SIGNAL9473
, SIGNAL_OUT10219 => SIGNAL9537
, SIGNAL_OUT10220 => SIGNAL9601
, SIGNAL_OUT10221 => SIGNAL9665
);
CHIP_INST10437 : ENTITY CHIP10223(ARCH) PORT MAP(SIGNAL_IN10224 => SIGNAL9473
, SIGNAL_IN10225 => SIGNAL9537
, SIGNAL_IN10226 => SIGNAL9601
, SIGNAL_IN10227 => SIGNAL9665
, SIGNAL_IN10228 => SIGNAL9415
, SIGNAL_OUT10229 => SIGNAL9474
, SIGNAL_OUT10230 => SIGNAL9538
, SIGNAL_OUT10231 => SIGNAL9602
, SIGNAL_OUT10232 => SIGNAL9666
);
CHIP_INST10438 : ENTITY CHIP10234(ARCH) PORT MAP(SIGNAL_IN10235 => SIGNAL9474
, SIGNAL_IN10236 => SIGNAL9538
, SIGNAL_IN10237 => SIGNAL9602
, SIGNAL_IN10238 => SIGNAL9666
, SIGNAL_IN10239 => SIGNAL9422
, SIGNAL_OUT10240 => SIGNAL9475
, SIGNAL_OUT10241 => SIGNAL9539
, SIGNAL_OUT10242 => SIGNAL9603
, SIGNAL_OUT10243 => SIGNAL9667
);
CHIP_INST10439 : ENTITY CHIP10245(ARCH) PORT MAP(SIGNAL_IN10246 => SIGNAL9475
, SIGNAL_IN10247 => SIGNAL9539
, SIGNAL_IN10248 => SIGNAL9603
, SIGNAL_IN10249 => SIGNAL9667
, SIGNAL_IN10250 => SIGNAL9413
, SIGNAL_OUT10251 => SIGNAL9476
, SIGNAL_OUT10252 => SIGNAL9540
, SIGNAL_OUT10253 => SIGNAL9604
, SIGNAL_OUT10254 => SIGNAL9668
);
CHIP_INST10440 : ENTITY CHIP10256(ARCH) PORT MAP(SIGNAL_IN10257 => SIGNAL9476
, SIGNAL_IN10258 => SIGNAL9540
, SIGNAL_IN10259 => SIGNAL9604
, SIGNAL_IN10260 => SIGNAL9668
, SIGNAL_IN10261 => SIGNAL9420
, SIGNAL_OUT10262 => SIGNAL9477
, SIGNAL_OUT10263 => SIGNAL9541
, SIGNAL_OUT10264 => SIGNAL9605
, SIGNAL_OUT10265 => SIGNAL9669
);
CHIP_INST10441 : ENTITY CHIP10267(ARCH) PORT MAP(SIGNAL_IN10268 => SIGNAL9477
, SIGNAL_IN10269 => SIGNAL9541
, SIGNAL_IN10270 => SIGNAL9605
, SIGNAL_IN10271 => SIGNAL9669
, SIGNAL_IN10272 => SIGNAL9411
, SIGNAL_OUT10273 => SIGNAL9478
, SIGNAL_OUT10274 => SIGNAL9542
, SIGNAL_OUT10275 => SIGNAL9606
, SIGNAL_OUT10276 => SIGNAL9670
);
CHIP_INST10442 : ENTITY CHIP10278(ARCH) PORT MAP(SIGNAL_IN10279 => SIGNAL9478
, SIGNAL_IN10280 => SIGNAL9542
, SIGNAL_IN10281 => SIGNAL9606
, SIGNAL_IN10282 => SIGNAL9670
, SIGNAL_IN10283 => SIGNAL9418
, SIGNAL_OUT10284 => SIGNAL9479
, SIGNAL_OUT10285 => SIGNAL9543
, SIGNAL_OUT10286 => SIGNAL9607
, SIGNAL_OUT10287 => SIGNAL9671
);
CHIP_INST10443 : ENTITY CHIP10289(ARCH) PORT MAP(SIGNAL_IN10290 => SIGNAL9479
, SIGNAL_IN10291 => SIGNAL9543
, SIGNAL_IN10292 => SIGNAL9607
, SIGNAL_IN10293 => SIGNAL9671
, SIGNAL_IN10294 => SIGNAL9409
, SIGNAL_OUT10295 => SIGNAL9480
, SIGNAL_OUT10296 => SIGNAL9544
, SIGNAL_OUT10297 => SIGNAL9608
, SIGNAL_OUT10298 => SIGNAL9672
);
CHIP_INST10444 : ENTITY CHIP10300(ARCH) PORT MAP(SIGNAL_IN10301 => SIGNAL9480
, SIGNAL_IN10302 => SIGNAL9544
, SIGNAL_IN10303 => SIGNAL9608
, SIGNAL_IN10304 => SIGNAL9672
, SIGNAL_IN10305 => SIGNAL9416
, SIGNAL_OUT10306 => SIGNAL9481
, SIGNAL_OUT10307 => SIGNAL9545
, SIGNAL_OUT10308 => SIGNAL9609
, SIGNAL_OUT10309 => SIGNAL9673
);
CHIP_INST10445 : ENTITY CHIP10311(ARCH) PORT MAP(SIGNAL_IN10312 => SIGNAL9481
, SIGNAL_IN10313 => SIGNAL9545
, SIGNAL_IN10314 => SIGNAL9609
, SIGNAL_IN10315 => SIGNAL9673
, SIGNAL_IN10316 => SIGNAL9423
, SIGNAL_OUT10317 => SIGNAL9482
, SIGNAL_OUT10318 => SIGNAL9546
, SIGNAL_OUT10319 => SIGNAL9610
, SIGNAL_OUT10320 => SIGNAL9674
);
CHIP_INST10446 : ENTITY CHIP10322(ARCH) PORT MAP(SIGNAL_IN10323 => SIGNAL9482
, SIGNAL_IN10324 => SIGNAL9546
, SIGNAL_IN10325 => SIGNAL9610
, SIGNAL_IN10326 => SIGNAL9674
, SIGNAL_IN10327 => SIGNAL9414
, SIGNAL_OUT10328 => SIGNAL9483
, SIGNAL_OUT10329 => SIGNAL9547
, SIGNAL_OUT10330 => SIGNAL9611
, SIGNAL_OUT10331 => SIGNAL9675
);
CHIP_INST10447 : ENTITY CHIP10333(ARCH) PORT MAP(SIGNAL_IN10334 => SIGNAL9483
, SIGNAL_IN10335 => SIGNAL9547
, SIGNAL_IN10336 => SIGNAL9611
, SIGNAL_IN10337 => SIGNAL9675
, SIGNAL_IN10338 => SIGNAL9421
, SIGNAL_OUT10339 => SIGNAL9484
, SIGNAL_OUT10340 => SIGNAL9548
, SIGNAL_OUT10341 => SIGNAL9612
, SIGNAL_OUT10342 => SIGNAL9676
);
CHIP_INST10448 : ENTITY CHIP10344(ARCH) PORT MAP(SIGNAL_IN10345 => SIGNAL9484
, SIGNAL_IN10346 => SIGNAL9548
, SIGNAL_IN10347 => SIGNAL9612
, SIGNAL_IN10348 => SIGNAL9676
, SIGNAL_IN10349 => SIGNAL9412
, SIGNAL_OUT10350 => SIGNAL9485
, SIGNAL_OUT10351 => SIGNAL9549
, SIGNAL_OUT10352 => SIGNAL9613
, SIGNAL_OUT10353 => SIGNAL9677
);
CHIP_INST10449 : ENTITY CHIP10355(ARCH) PORT MAP(SIGNAL_IN10356 => SIGNAL9485
, SIGNAL_IN10357 => SIGNAL9549
, SIGNAL_IN10358 => SIGNAL9613
, SIGNAL_IN10359 => SIGNAL9677
, SIGNAL_IN10360 => SIGNAL9419
, SIGNAL_OUT10361 => SIGNAL9486
, SIGNAL_OUT10362 => SIGNAL9550
, SIGNAL_OUT10363 => SIGNAL9614
, SIGNAL_OUT10364 => SIGNAL9678
);
CHIP_INST10450 : ENTITY CHIP10366(ARCH) PORT MAP(SIGNAL_IN10367 => SIGNAL9486
, SIGNAL_IN10368 => SIGNAL9550
, SIGNAL_IN10369 => SIGNAL9614
, SIGNAL_IN10370 => SIGNAL9678
, SIGNAL_IN10371 => SIGNAL9410
, SIGNAL_OUT10372 => SIGNAL9487
, SIGNAL_OUT10373 => SIGNAL9551
, SIGNAL_OUT10374 => SIGNAL9615
, SIGNAL_OUT10375 => SIGNAL9679
);
CHIP_INST10451 : ENTITY CHIP10377(ARCH) PORT MAP(SIGNAL_IN10378 => SIGNAL9487
, SIGNAL_IN10379 => SIGNAL9551
, SIGNAL_IN10380 => SIGNAL9615
, SIGNAL_IN10381 => SIGNAL9679
, SIGNAL_IN10382 => SIGNAL9417
, SIGNAL_OUT10383 => SIGNAL_OUT9404
, SIGNAL_OUT10384 => SIGNAL_OUT9405
, SIGNAL_OUT10385 => SIGNAL_OUT9406
, SIGNAL_OUT10386 => SIGNAL_OUT9407
);
END ARCHITECTURE ARCH;
|
epl-1.0
|
35871e98ac5d8b88c0add6471ddaa5fa
| 0.693068 | 3.500234 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/dcfifo/_primary.vhd
| 1 | 3,167 |
library verilog;
use verilog.vl_types.all;
entity dcfifo is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
delay_rdusedw : integer := 1;
delay_wrusedw : integer := 1;
rdsync_delaypipe: integer := 0;
wrsync_delaypipe: integer := 0;
intended_device_family: string := "Stratix";
lpm_showahead : string := "OFF";
underflow_checking: string := "ON";
overflow_checking: string := "ON";
clocks_are_synchronized: string := "FALSE";
use_eab : string := "ON";
add_ram_output_register: string := "OFF";
lpm_hint : string := "USE_EAB=ON";
lpm_type : string := "dcfifo";
add_usedw_msb_bit: string := "OFF";
read_aclr_synch : string := "OFF";
write_aclr_synch: string := "OFF";
add_width : integer := 1;
ram_block_type : string := "AUTO"
);
port(
data : in vl_logic_vector;
rdclk : in vl_logic;
wrclk : in vl_logic;
aclr : in vl_logic;
rdreq : in vl_logic;
wrreq : in vl_logic;
rdfull : out vl_logic;
wrfull : out vl_logic;
rdempty : out vl_logic;
wrempty : out vl_logic;
rdusedw : out vl_logic_vector;
wrusedw : out vl_logic_vector;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_width : constant is 1;
attribute mti_svvh_generic_type of lpm_widthu : constant is 1;
attribute mti_svvh_generic_type of lpm_numwords : constant is 1;
attribute mti_svvh_generic_type of delay_rdusedw : constant is 1;
attribute mti_svvh_generic_type of delay_wrusedw : constant is 1;
attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1;
attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_showahead : constant is 1;
attribute mti_svvh_generic_type of underflow_checking : constant is 1;
attribute mti_svvh_generic_type of overflow_checking : constant is 1;
attribute mti_svvh_generic_type of clocks_are_synchronized : constant is 1;
attribute mti_svvh_generic_type of use_eab : constant is 1;
attribute mti_svvh_generic_type of add_ram_output_register : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of add_usedw_msb_bit : constant is 1;
attribute mti_svvh_generic_type of read_aclr_synch : constant is 1;
attribute mti_svvh_generic_type of write_aclr_synch : constant is 1;
attribute mti_svvh_generic_type of add_width : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
end dcfifo;
|
bsd-2-clause
|
bae3dd78de41da3daa087d578f9b1deb
| 0.596779 | 3.838788 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/iserdes_fifo_10_bit.vhd
| 1 | 5,802 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file iserdes_fifo_10_bit.vhd when simulating
-- the core, iserdes_fifo_10_bit. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY iserdes_fifo_10_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(9 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(9 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END iserdes_fifo_10_bit;
ARCHITECTURE iserdes_fifo_10_bit_a OF iserdes_fifo_10_bit IS
-- synthesis translate_off
component wrapped_iserdes_fifo_10_bit
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(9 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(9 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_iserdes_fifo_10_bit use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 10,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "virtex5",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 10,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_iserdes_fifo_10_bit
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty);
-- synthesis translate_on
END iserdes_fifo_10_bit_a;
|
gpl-3.0
|
17a9c227f4bea9e9a4044ae6f8e74316
| 0.547915 | 3.453571 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/virtual_instrument/logi_virtual_sw.vhd
| 2 | 3,238 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:04 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_sw - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_sw is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
sw : out std_logic_vector(15 downto 0)
);
end logi_virtual_sw;
architecture Behavioral of logi_virtual_sw is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
sw <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
lgpl-3.0
|
56f85804405de56e43d685cbefbbb830
| 0.592341 | 3.679545 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/user_logic.vhd
| 1 | 93,084 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Sep 15, 2011
-- Design Name: FMC-IMAGEON
-- Module Name: user_logic.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Virtex-6
-- Kintex-7, Zynq
-- Avnet Boards: FMC-IMAGEON
--
-- Tool versions: ISE 14.1
--
-- Description: FMC-IMAGEON VITA receiver - User Logic.
-- This layer implements the following programming model
-- 0x00 - SPI_CONTROL
-- [ 0] VITA_RESET
-- [ 1] SPI_RESET
-- [ 8] SPI_STATUS_BUSY
-- [ 9] SPI_STATUS_ERROR
-- [16] SPI_TXFIFO_FULL
-- [24] SPI_RXFIFO_EMPTY
-- 0x04 - SPI_TIMING[15:0]
-- 0x08 - SPI_TXFIFO_DATA[31:0]
-- 0x0C - SPI_RXFIFO_DATA[31:0]
-- 0x10 - ISERDES_CONTROL
-- [ 0] ISERDES_RESET
-- [ 1] ISERDES_AUTO_ALIGN
-- [ 2] ISERDES_ALIGN_START
-- [ 3] ISERDES_FIFO_ENABLE
-- [ 8] ISERDES_CLK_READY
-- [ 9] ISERDES_ALIGN_BUSY
-- [10] ISERDES_ALIGNED
-- [23:16] ISERDES_TXCLK_STATUS
-- [31:24] ISERDES_RXCLK_STATUS
-- 0x14 - ISERDES_TRAINING
-- 0x18 - ISERDES_MANUAL_TAP
-- 0x1C - {unused}
-- 0x20 - DECODER_CONTROL
-- [0] DECODER_RESET
-- [1] DECODER_ENABLE
-- 0x24 - DECODER_STARTODDEVEN
-- 0x28 - DECODER_CODES_LS_LE
-- [15: 0] CODE_LS
-- [31:16] CODE_LE
-- 0x2C - DECODER_CODES_FS_FE
-- [15: 0] CODE_FS
-- [31:16] CODE_FE
-- 0x30 - DECODER_CODES_BL_IMG
-- [15: 0] CODE_BL
-- [31:16] CODE_IMG
-- 0x34 - DECODER_CODES_TR_CRC
-- [15: 0] CODE_TR
-- [31:16] CODE_CRC
-- 0x38 - DECODER_CNT_BLACK_LINES
-- 0x3C - DECODER_CNT_IMAGE_LINES
-- 0x40 - DECODER_CNT_BLACK_PIXELS
-- 0x44 - DECODER_CNT_IMAGE_PIXELS
-- 0x48 - DECODER_CNT_FRAMES
-- 0x4C - DECODER_CNT_WINDOWS
-- 0x50 - DECODER_CNT_CLOCKS
-- 0x54 - DECODER_CNT_START_LINES
-- 0x58 - DECODER_CNT_END_LINES
-- 0x5C - SYNCGEN_DELAY
-- [15: 0] DELAY
-- 0x60 - SYNCGEN_HTIMING1
-- [15: 0] HACTIVE
-- [31:16] HFPORCH
-- 0x64 - SYNCGEN_HTIMING2
-- [15: 0] HSYNC
-- [31:16] HBPORCH
-- 0x68 - SYNCGEN_VTIMING1
-- [15: 0] VACTIVE
-- [31:16] VFPORCH
-- 0x6C - SYNCGEN_VTIMING2
-- [15: 0] VSYNC
-- [31:16] VBPORCH
-- 0x70 - CRC_CONTROL
-- [0] CRC_RESET
-- [1] CRC_INITVALUE
-- 0x74 - CRC_STATUS
-- 0x78 - REMAPPER_CONTROL[7:0]
-- [2:0] REMAPPER_WRITE_CFG
-- [6:4] REMAPPER_MODE
-- 0x7C - {unused}
-- 0x80 - FPN_PRNU_VALUES[ 31: 0]
-- [ 7: 0] PRNU_0
-- [15: 8] FPN_0
-- [23:16] PRNU_1
-- [31:24] FPN_1
-- 0x84 - FPN_PRNU_VALUES[ 63: 32]
-- [ 7: 0] PRNU_2
-- [15: 8] FPN_2
-- [23:16] PRNU_3
-- [31:24] FPN_3
-- 0x88 - FPN_PRNU_VALUES[ 95: 64]
-- 0x8C - FPN_PRNU_VALUES[127: 96]
-- 0x90 - FPN_PRNU_VALUES[159:128]
-- 0x94 - FPN_PRNU_VALUES[191:160]
-- 0x98 - FPN_PRNU_VALUES[223:192]
-- 0x9C - FPN_PRNU_VALUES[255:224]
-- [ 7: 0] PRNU_14
-- [15: 8] FPN_14
-- [23:16] PRNU_15
-- [31:24] FPN_15
-- 0xA0 - {unused}
-- 0xA4 - {unused}
-- 0xA8 - {unused}
-- 0xAC - {unused}
-- 0xB0 - {unused}
-- 0xB4 - {unused}
-- 0xB8 - {unused}
-- 0xBC - {unused}
-- 0xC0 - DECODER_CNT_MONITOR0_HIGH
-- 0xC4 - DECODER_CNT_MONITOR0_LOW
-- 0xC8 - DECODER_CNT_MONITOR1_HIGH
-- 0xCC - DECODER_CNT_MONITOR1_LOW
-- 0xD0 - {unused}
-- 0xD4 - {unused}
-- 0xD8 - {unused}
-- 0xDC - TRIGGEN_EXT_DEBOUNCE
-- 0xE0 - TRIGGEN_CONTROL
-- [ 2: 0] TRIGGEN_ENABLE
-- [ 6: 4] TRIGGEN_SYNC2READOUT
-- [ 8] TRIGGEN_READOUTTRIGGER
-- [ 16] TRIGGEN_EXT_POLARITY
-- [ 24] TRIGGEN_CNT_UPDATE
-- [30:28] TRIGGEN_GEN_POLARITY
-- 0xE4 - TRIGGEN_DEFAULT_FREQ
-- 0xE8 - TRIGGEN_TRIG0_HIGH
-- 0xEC - TRIGGEN_TRIG0_LOW
-- 0xF0 - TRIGGEN_TRIG1_HIGH
-- 0xF4 - TRIGGEN_TRIG1_LOW
-- 0xF8 - TRIGGEN_TRIG2_HIGH
-- 0xFC - TRIGGEN_TRIG2_LOW
--
--
-- Dependencies:
--
-- Revision: Sep 15, 2011: 1.00 Initial version:
-- - VITA SPI controller
-- Sep 22, 2011: 1.01 Added:
-- - ISERDES interface
-- Sep 28, 2011: 1.02 Added:
-- - sync channel decoder
-- - crc checker
-- - data remapper
-- Oct 20, 2011: 1.03 Modify:
-- - iserdes (use BUFR)
-- Oct 21, 2011: 1.04 Added:
-- - fpn prnu correction
-- Nov 03, 2011: 1.05 Added:
-- - trigger generator
-- Dec 19, 2011: 1.06 Modified:
-- - port to Kintex-7
-- Jan 12, 2012: 1.07 Added:
-- - new fsync output port
-- Modify:
-- - syncgen
-- Feb 06, 2012: 1.08 Modify:
-- - triggergenerator
-- (new version with debounce logic)
-- - new C_XSVI_DIRECT_OUTPUT option
-- Feb 22, 2012: 1.09 Modified
-- - port to Zynq
-- - new C_XSVI_USE_SYNCGEN option
-- May 13, 2012: 1.10 Optimize
-- - remove one layer of registers
-- May 28, 2012: 1.11 Added
-- - host_triggen_cnt_update
-- (for simultaneous update of high/low values)
-- - host_triggen_gen_polarity
-- Jun 01, 2012: 1.12 Modify:
-- - Move syncgen after demux_fifo
-- - Increase size of demux_fifo
-- (to tolerate jitter in video timing from sensor)
-- - Add programmable delay on framestart for syncgen
-- Jul 31, 2012: 1.13 Modify:
-- - define clk200, clk, clk4x with SIGIS = CLK
-- - define reset with SIGIS = RST
-- - port to Spartan-6
--
------------------------------------------------------------------
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu Sep 15 13:07:23 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
library fmc_imageon_vita_receiver_v1_13_a;
use fmc_imageon_vita_receiver_v1_13_a.fmc_imageon_vita_core;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_XSVI_DATA_WIDTH : integer := 10;
C_XSVI_DIRECT_OUTPUT : integer := 0;
C_XSVI_USE_SYNCGEN : integer := 1;
C_FAMILY : string := "virtex6";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 64;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk200 : in std_logic;
clk : in std_logic;
clk4x : in std_logic;
reset : in std_logic;
oe : in std_logic;
-- I/O pins
io_vita_clk_pll : out std_logic;
io_vita_reset_n : out std_logic;
io_vita_spi_sclk : out std_logic;
io_vita_spi_ssel_n : out std_logic;
io_vita_spi_mosi : out std_logic;
io_vita_spi_miso : in std_logic;
io_vita_trigger : out std_logic_vector(2 downto 0);
io_vita_monitor : in std_logic_vector(1 downto 0);
io_vita_clk_out_p : in std_logic;
io_vita_clk_out_n : in std_logic;
io_vita_sync_p : in std_logic;
io_vita_sync_n : in std_logic;
io_vita_data_p : in std_logic_vector(7 downto 0);
io_vita_data_n : in std_logic_vector(7 downto 0);
-- Trigger Port
trigger1 : in std_logic;
-- Frame Sync Port
fsync : out std_logic;
-- XSVI Port
xsvi_vsync_o : out std_logic;
xsvi_hsync_o : out std_logic;
xsvi_vblank_o : out std_logic;
xsvi_hblank_o : out std_logic;
xsvi_active_video_o : out std_logic;
xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0);
-- Debug Ports
debug_host_o : out std_logic_vector(231 downto 0);
debug_spi_o : out std_logic_vector( 95 downto 0);
debug_iserdes_o : out std_logic_vector(229 downto 0);
debug_decoder_o : out std_logic_vector(186 downto 0);
debug_crc_o : out std_logic_vector( 87 downto 0);
debug_triggen_o : out std_logic_vector( 9 downto 0);
debug_video_o : out std_logic_vector( 31 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--
signal slv_reg32 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg33 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg34 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg35 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg36 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg37 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg38 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg39 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--
signal slv_reg55 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg56 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg57 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg58 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg59 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg60 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg61 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg62 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg63 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--
signal slv_reg_write_sel : std_logic_vector(63 downto 0);
signal slv_reg_read_sel : std_logic_vector(63 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_reg4_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg16_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg17_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg18_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg19_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg20_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg21_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg22_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg23_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg24_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg25_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg26_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg27_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--
signal slv_reg32_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg33_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg34_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg35_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg36_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg37_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg38_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg39_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--
signal slv_reg48_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg49_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg50_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg51_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
--
signal slv_reg55_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg56_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg57_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg58_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg59_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg60_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg61_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg62_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg63_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
-- HOST Interface - VITA
signal host_vita_reset : std_logic;
-- HOST Interface - SPI
signal host_spi_clk : std_logic;
signal host_spi_reset : std_logic;
signal host_spi_timing : std_logic_vector(15 downto 0);
signal host_spi_status_busy : std_logic;
signal host_spi_status_error : std_logic;
signal host_spi_txfifo_clk : std_logic;
signal host_spi_txfifo_wen_a1 : std_logic;
signal host_spi_txfifo_wen : std_logic;
signal host_spi_txfifo_din : std_logic_vector(31 downto 0);
signal host_spi_txfifo_full : std_logic;
signal host_spi_rxfifo_clk : std_logic;
signal host_spi_rxfifo_ren : std_logic;
signal host_spi_rxfifo_dout : std_logic_vector(31 downto 0);
signal host_spi_rxfifo_empty : std_logic;
-- HOST Interface - ISERDES
signal host_iserdes_reset : std_logic;
signal host_iserdes_auto_align : std_logic;
signal host_iserdes_align_start : std_logic;
signal host_iserdes_fifo_enable : std_logic;
signal host_iserdes_manual_tap : std_logic_vector(9 downto 0);
signal host_iserdes_training : std_logic_vector(9 downto 0);
--
signal host_iserdes_clk_ready : std_logic;
signal host_iserdes_clk_status : std_logic_vector(15 downto 0);
signal host_iserdes_align_busy : std_logic;
signal host_iserdes_aligned : std_logic;
-- HOST Interface - Sync Channel Decoder
signal host_decoder_reset : std_logic;
signal host_decoder_enable : std_logic;
signal host_decoder_startoddeven : std_logic_vector(31 downto 0);
signal host_decoder_code_ls : std_logic_vector(9 downto 0);
signal host_decoder_code_le : std_logic_vector(9 downto 0);
signal host_decoder_code_fs : std_logic_vector(9 downto 0);
signal host_decoder_code_fe : std_logic_vector(9 downto 0);
signal host_decoder_code_bl : std_logic_vector(9 downto 0);
signal host_decoder_code_img : std_logic_vector(9 downto 0);
signal host_decoder_code_tr : std_logic_vector(9 downto 0);
signal host_decoder_code_crc : std_logic_vector(9 downto 0);
signal host_decoder_frame_start : std_logic;
signal host_decoder_cnt_black_lines : std_logic_vector(31 downto 0);
signal host_decoder_cnt_image_lines : std_logic_vector(31 downto 0);
signal host_decoder_cnt_black_pixels : std_logic_vector(31 downto 0);
signal host_decoder_cnt_image_pixels : std_logic_vector(31 downto 0);
signal host_decoder_cnt_frames : std_logic_vector(31 downto 0);
signal host_decoder_cnt_windows : std_logic_vector(31 downto 0);
signal host_decoder_cnt_clocks : std_logic_vector(31 downto 0);
signal host_decoder_cnt_start_lines : std_logic_vector(31 downto 0);
signal host_decoder_cnt_end_lines : std_logic_vector(31 downto 0);
signal host_decoder_cnt_monitor0high : std_logic_vector(31 downto 0);
signal host_decoder_cnt_monitor0low : std_logic_vector(31 downto 0);
signal host_decoder_cnt_monitor1high : std_logic_vector(31 downto 0);
signal host_decoder_cnt_monitor1low : std_logic_vector(31 downto 0);
-- HOST Interface - CRC Checker
signal host_crc_reset : std_logic;
signal host_crc_initvalue : std_logic;
signal host_crc_status : std_logic_vector(31 downto 0);
-- HOST Interface - Data Channel Remapper
signal host_remapper_write_cfg : std_logic_vector(2 downto 0);
signal host_remapper_mode : std_logic_vector(2 downto 0);
-- HOST Interface - Trigger Generator
signal host_triggen_enable : std_logic_vector(2 downto 0);
signal host_triggen_sync2readout : std_logic_vector(2 downto 0);
signal host_triggen_readouttrigger : std_logic;
signal host_triggen_default_freq : std_logic_vector(31 downto 0);
signal host_triggen_cnt_trigger0high : std_logic_vector(31 downto 0);
signal host_triggen_cnt_trigger0low : std_logic_vector(31 downto 0);
signal host_triggen_cnt_trigger1high : std_logic_vector(31 downto 0);
signal host_triggen_cnt_trigger1low : std_logic_vector(31 downto 0);
signal host_triggen_cnt_trigger2high : std_logic_vector(31 downto 0);
signal host_triggen_cnt_trigger2low : std_logic_vector(31 downto 0);
signal host_triggen_ext_debounce : std_logic_vector(31 downto 0);
signal host_triggen_ext_polarity : std_logic;
signal host_triggen_cnt_update : std_logic;
signal host_triggen_gen_polarity : std_logic_vector(2 downto 0);
-- HOST Interface - FPN/PRNU Correction
signal host_fpn_prnu_values : std_logic_vector((16*16)-1 downto 0);
-- HOST Interface - Sync Generator
signal host_syncgen_delay : std_logic_vector(15 downto 0);
signal host_syncgen_hactive : std_logic_vector(15 downto 0);
signal host_syncgen_hfporch : std_logic_vector(15 downto 0);
signal host_syncgen_hsync : std_logic_vector(15 downto 0);
signal host_syncgen_hbporch : std_logic_vector(15 downto 0);
signal host_syncgen_vactive : std_logic_vector(15 downto 0);
signal host_syncgen_vfporch : std_logic_vector(15 downto 0);
signal host_syncgen_vsync : std_logic_vector(15 downto 0);
signal host_syncgen_vbporch : std_logic_vector(15 downto 0);
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(63 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(63 downto 0);
slv_write_ack <= Bus2IP_WrCE( 0) or Bus2IP_WrCE( 1) or Bus2IP_WrCE( 2) or Bus2IP_WrCE( 3) or Bus2IP_WrCE( 4) or Bus2IP_WrCE( 5) or Bus2IP_WrCE( 6) or Bus2IP_WrCE( 7)
or Bus2IP_WrCE( 8) or Bus2IP_WrCE( 9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15)
or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23)
or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31)
or Bus2IP_WrCE(32) or Bus2IP_WrCE(33) or Bus2IP_WrCE(34) or Bus2IP_WrCE(35) or Bus2IP_WrCE(36) or Bus2IP_WrCE(37) or Bus2IP_WrCE(38) or Bus2IP_WrCE(39)
or Bus2IP_WrCE(40) or Bus2IP_WrCE(41) or Bus2IP_WrCE(42) or Bus2IP_WrCE(43) or Bus2IP_WrCE(44) or Bus2IP_WrCE(45) or Bus2IP_WrCE(46) or Bus2IP_WrCE(47)
or Bus2IP_WrCE(48) or Bus2IP_WrCE(49) or Bus2IP_WrCE(50) or Bus2IP_WrCE(51) or Bus2IP_WrCE(52) or Bus2IP_WrCE(53) or Bus2IP_WrCE(54) or Bus2IP_WrCE(55)
or Bus2IP_WrCE(56) or Bus2IP_WrCE(57) or Bus2IP_WrCE(58) or Bus2IP_WrCE(59) or Bus2IP_WrCE(60) or Bus2IP_WrCE(61) or Bus2IP_WrCE(62) or Bus2IP_WrCE(63);
slv_read_ack <= Bus2IP_RdCE( 0) or Bus2IP_RdCE( 1) or Bus2IP_RdCE( 2) or Bus2IP_RdCE( 3) or Bus2IP_RdCE( 4) or Bus2IP_RdCE( 5) or Bus2IP_RdCE( 6) or Bus2IP_RdCE( 7)
or Bus2IP_RdCE( 8) or Bus2IP_RdCE( 9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15)
or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23)
or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31)
or Bus2IP_RdCE(32) or Bus2IP_RdCE(33) or Bus2IP_RdCE(34) or Bus2IP_RdCE(35) or Bus2IP_RdCE(36) or Bus2IP_RdCE(37) or Bus2IP_RdCE(38) or Bus2IP_RdCE(39)
or Bus2IP_RdCE(40) or Bus2IP_RdCE(41) or Bus2IP_RdCE(42) or Bus2IP_RdCE(43) or Bus2IP_RdCE(44) or Bus2IP_RdCE(45) or Bus2IP_RdCE(46) or Bus2IP_RdCE(47)
or Bus2IP_RdCE(48) or Bus2IP_RdCE(49) or Bus2IP_RdCE(50) or Bus2IP_RdCE(51) or Bus2IP_RdCE(52) or Bus2IP_RdCE(53) or Bus2IP_RdCE(54) or Bus2IP_RdCE(55)
or Bus2IP_RdCE(56) or Bus2IP_RdCE(57) or Bus2IP_RdCE(58) or Bus2IP_RdCE(59) or Bus2IP_RdCE(60) or Bus2IP_RdCE(61) or Bus2IP_RdCE(62) or Bus2IP_RdCE(63);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
--
slv_reg55 <= (others => '0');
slv_reg56 <= (others => '0');
slv_reg57 <= (others => '0');
slv_reg58 <= (others => '0');
slv_reg59 <= (others => '0');
slv_reg60 <= (others => '0');
slv_reg61 <= (others => '0');
slv_reg62 <= (others => '0');
slv_reg63 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0100000000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0010000000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001000000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000100000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000010000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000001000000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000100000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000010000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000001000000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000100000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000010000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000001000000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000100000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000010000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000001000000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000100000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000010000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000001000000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000100000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000010000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000001000000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000100000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000010000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg32(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000001000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg33(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg34(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg35(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg36(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg37(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg38(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg39(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--
when "0000000000000000000000000000000000000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg55(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg56(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg57(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg58(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg59(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg60(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg61(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg62(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000000000000000000000000000000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg63(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39 ) is
begin
case slv_reg_read_sel is
when "1000000000000000000000000000000000000000000000000000000000000000" =>
--slv_ip2bus_data <= slv_reg0;
-- 0x00 - SPI_CONTROL
-- [ 0] VITA_RESET
-- [ 1] SPI_RESET
-- [ 8] SPI_STATUS_BUSY
-- [ 9] SPI_STATUS_ERROR
-- [16] SPI_TXFIFO_FULL
-- [24] SPI_RXFIFO_EMPTY
slv_ip2bus_data <= "0000000" & host_spi_rxfifo_empty &
"0000000" & host_spi_txfifo_full &
"000000" & host_spi_status_error & host_spi_status_busy &
"000000" & host_spi_reset & host_vita_reset;
when "0100000000000000000000000000000000000000000000000000000000000000" =>
-- 0x04 - SPI_TIMING[15:0]
slv_ip2bus_data <= slv_reg1;
when "0010000000000000000000000000000000000000000000000000000000000000" =>
-- 0x08 - SPI_TXFIFO_DATA[31:0]
slv_ip2bus_data <= slv_reg2;
when "0001000000000000000000000000000000000000000000000000000000000000" =>
--slv_ip2bus_data <= slv_reg3;
-- 0x0C - SPI_RXFIFO_DATA[31:0]
slv_ip2bus_data <= host_spi_rxfifo_dout;
when "0000100000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg4_r1;
when "0000010000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "0000001000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "0000000100000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "0000000010000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "0000000001000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "0000000000100000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "0000000000010000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "0000000000001000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "0000000000000100000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "0000000000000010000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg14_r1;
when "0000000000000001000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg15_r1;
when "0000000000000000100000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg16_r1;
when "0000000000000000010000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg17_r1;
when "0000000000000000001000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg18_r1;
when "0000000000000000000100000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg19_r1;
when "0000000000000000000010000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg20_r1;
when "0000000000000000000001000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg21_r1;
when "0000000000000000000000100000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg22_r1;
when "0000000000000000000000010000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg23;
when "0000000000000000000000001000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg24;
when "0000000000000000000000000100000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg25;
when "0000000000000000000000000010000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg26;
when "0000000000000000000000000001000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg27;
when "0000000000000000000000000000100000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg28;
when "0000000000000000000000000000010000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg29_r1;
when "0000000000000000000000000000001000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg30;
when "0000000000000000000000000000000100000000000000000000000000000000" => slv_ip2bus_data <= slv_reg31;
when "0000000000000000000000000000000010000000000000000000000000000000" => slv_ip2bus_data <= slv_reg32;
when "0000000000000000000000000000000001000000000000000000000000000000" => slv_ip2bus_data <= slv_reg33;
when "0000000000000000000000000000000000100000000000000000000000000000" => slv_ip2bus_data <= slv_reg34;
when "0000000000000000000000000000000000010000000000000000000000000000" => slv_ip2bus_data <= slv_reg35;
when "0000000000000000000000000000000000001000000000000000000000000000" => slv_ip2bus_data <= slv_reg36;
when "0000000000000000000000000000000000000100000000000000000000000000" => slv_ip2bus_data <= slv_reg37;
when "0000000000000000000000000000000000000010000000000000000000000000" => slv_ip2bus_data <= slv_reg38;
when "0000000000000000000000000000000000000001000000000000000000000000" => slv_ip2bus_data <= slv_reg39;
--
when "0000000000000000000000000000000000000000000000001000000000000000" => slv_ip2bus_data <= slv_reg48_r1;
when "0000000000000000000000000000000000000000000000000100000000000000" => slv_ip2bus_data <= slv_reg49_r1;
when "0000000000000000000000000000000000000000000000000010000000000000" => slv_ip2bus_data <= slv_reg50_r1;
when "0000000000000000000000000000000000000000000000000001000000000000" => slv_ip2bus_data <= slv_reg51_r1;
--
when "0000000000000000000000000000000000000000000000000000000100000000" => slv_ip2bus_data <= slv_reg55;
when "0000000000000000000000000000000000000000000000000000000010000000" => slv_ip2bus_data <= slv_reg56;
when "0000000000000000000000000000000000000000000000000000000001000000" => slv_ip2bus_data <= slv_reg57;
when "0000000000000000000000000000000000000000000000000000000000100000" => slv_ip2bus_data <= slv_reg58;
when "0000000000000000000000000000000000000000000000000000000000010000" => slv_ip2bus_data <= slv_reg59;
when "0000000000000000000000000000000000000000000000000000000000001000" => slv_ip2bus_data <= slv_reg60;
when "0000000000000000000000000000000000000000000000000000000000000100" => slv_ip2bus_data <= slv_reg61;
when "0000000000000000000000000000000000000000000000000000000000000010" => slv_ip2bus_data <= slv_reg62;
when "0000000000000000000000000000000000000000000000000000000000000001" => slv_ip2bus_data <= slv_reg63;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
--
-- HOST Interface - SPI
--
host_spi_clk <= Bus2IP_Clk;
host_spi_txfifo_clk <= Bus2IP_Clk;
host_spi_rxfifo_clk <= Bus2IP_Clk;
host_spi_process : process ( Bus2IP_Clk )
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
host_vita_reset <= '0';
host_spi_reset <= '0';
host_spi_timing <= (others => '0');
host_spi_txfifo_wen_a1 <= '0';
host_spi_txfifo_wen <= '0';
host_spi_txfifo_din <= (others => '0');
host_spi_rxfifo_ren <= '0';
else
-- 0x00 - SPI_CONTROL
-- [ 0] VITA_RESET
-- [ 1] SPI_RESET
-- [ 8] SPI_STATUS_BUSY
-- [ 9] SPI_STATUS_ERROR
-- [16] SPI_TXFIFO_FULL
-- [24] SPI_RXFIFO_EMPTY
host_vita_reset <= slv_reg0(0);
host_spi_reset <= slv_reg0(1);
host_spi_timing <= slv_reg1(15 downto 0);
-- slv_reg2 is valid 1 cycle after slv_reg_write_sel(63-2)
host_spi_txfifo_wen_a1 <= slv_reg_write_sel(63-2);
host_spi_txfifo_wen <= host_spi_txfifo_wen_a1;
host_spi_txfifo_din <= slv_reg2;
-- use write to pop value from RXFIFO ...
host_spi_rxfifo_ren <= slv_reg_write_sel(63-3);
end if;
end if;
end process host_spi_process;
slv_reg4_w1 <= slv_reg4;
slv_reg5_w1 <= slv_reg5;
slv_reg6_w1 <= slv_reg6;
slv_reg8_w1 <= slv_reg8;
slv_reg9_w1 <= slv_reg9;
slv_reg10_w1 <= slv_reg10;
slv_reg11_w1 <= slv_reg11;
slv_reg12_w1 <= slv_reg12;
slv_reg13_w1 <= slv_reg13;
slv_reg23_w1 <= slv_reg23;
slv_reg24_w1 <= slv_reg24;
slv_reg25_w1 <= slv_reg25;
slv_reg26_w1 <= slv_reg26;
slv_reg27_w1 <= slv_reg27;
slv_reg28_w1 <= slv_reg28;
slv_reg30_w1 <= slv_reg30;
--
slv_reg32_w1 <= slv_reg32;
slv_reg33_w1 <= slv_reg33;
slv_reg34_w1 <= slv_reg34;
slv_reg35_w1 <= slv_reg35;
slv_reg36_w1 <= slv_reg36;
slv_reg37_w1 <= slv_reg37;
slv_reg38_w1 <= slv_reg38;
slv_reg39_w1 <= slv_reg39;
--
slv_reg55_w1 <= slv_reg55;
slv_reg56_w1 <= slv_reg56;
slv_reg57_w1 <= slv_reg57;
slv_reg58_w1 <= slv_reg58;
slv_reg59_w1 <= slv_reg59;
slv_reg60_w1 <= slv_reg60;
slv_reg61_w1 <= slv_reg61;
slv_reg62_w1 <= slv_reg62;
slv_reg63_w1 <= slv_reg63;
host_iserdes_process : process ( clk )
begin
if clk'event and clk = '1' then
if reset = '1' then
-- slv_reg4_w1 <= (others => '0');
slv_reg4_r1 <= (others => '0');
-- slv_reg5_w1 <= (others => '0');
-- slv_reg6_w1 <= (others => '0');
-- slv_reg8_w1 <= (others => '0');
-- slv_reg9_w1 <= (others => '0');
-- slv_reg10_w1 <= (others => '0');
-- slv_reg11_w1 <= (others => '0');
-- slv_reg12_w1 <= (others => '0');
-- slv_reg13_w1 <= (others => '0');
slv_reg14_r1 <= (others => '0');
slv_reg15_r1 <= (others => '0');
slv_reg16_r1 <= (others => '0');
slv_reg17_r1 <= (others => '0');
slv_reg18_r1 <= (others => '0');
slv_reg19_r1 <= (others => '0');
slv_reg20_r1 <= (others => '0');
slv_reg21_r1 <= (others => '0');
slv_reg22_r1 <= (others => '0');
-- slv_reg23_w1 <= (others => '0');
-- slv_reg24_w1 <= (others => '0');
-- slv_reg25_w1 <= (others => '0');
-- slv_reg26_w1 <= (others => '0');
-- slv_reg27_w1 <= (others => '0');
-- slv_reg28_w1 <= (others => '0');
slv_reg29_r1 <= (others => '0');
-- slv_reg30_w1 <= (others => '0');
--
-- slv_reg32_w1 <= (others => '0');
-- slv_reg33_w1 <= (others => '0');
-- slv_reg34_w1 <= (others => '0');
-- slv_reg35_w1 <= (others => '0');
-- slv_reg36_w1 <= (others => '0');
-- slv_reg37_w1 <= (others => '0');
-- slv_reg38_w1 <= (others => '0');
-- slv_reg39_w1 <= (others => '0');
--
slv_reg48_r1 <= (others => '0');
slv_reg49_r1 <= (others => '0');
slv_reg50_r1 <= (others => '0');
slv_reg51_r1 <= (others => '0');
--
-- slv_reg55_w1 <= (others => '0');
-- slv_reg56_w1 <= (others => '0');
-- slv_reg57_w1 <= (others => '0');
-- slv_reg58_w1 <= (others => '0');
-- slv_reg59_w1 <= (others => '0');
-- slv_reg60_w1 <= (others => '0');
-- slv_reg61_w1 <= (others => '0');
-- slv_reg62_w1 <= (others => '0');
-- slv_reg63_w1 <= (others => '0');
--
host_iserdes_reset <= '0';
host_iserdes_auto_align <= '0';
host_iserdes_align_start <= '0';
host_iserdes_fifo_enable <= '0';
host_iserdes_training <= (others => '0');
host_iserdes_manual_tap <= (others => '0');
--
host_fpn_prnu_values <= (others => '0');
--
host_triggen_enable <= (others => '0');
host_triggen_sync2readout <= (others => '0');
host_triggen_readouttrigger <= '0';
host_triggen_default_freq <= (others => '0');
host_triggen_cnt_trigger0high <= (others => '0');
host_triggen_cnt_trigger0low <= (others => '0');
host_triggen_cnt_trigger1high <= (others => '0');
host_triggen_cnt_trigger1low <= (others => '0');
host_triggen_cnt_trigger2high <= (others => '0');
host_triggen_cnt_trigger2low <= (others => '0');
host_triggen_ext_debounce <= (others => '0');
host_triggen_ext_polarity <= '0';
host_triggen_cnt_update <= '0';
else
-- slv_reg4_w1 <= slv_reg4;
-- slv_reg5_w1 <= slv_reg5;
-- slv_reg6_w1 <= slv_reg6;
-- slv_reg8_w1 <= slv_reg8;
-- slv_reg9_w1 <= slv_reg9;
-- slv_reg10_w1 <= slv_reg10;
-- slv_reg11_w1 <= slv_reg11;
-- slv_reg12_w1 <= slv_reg12;
-- slv_reg13_w1 <= slv_reg13;
-- slv_reg23_w1 <= slv_reg23;
-- slv_reg24_w1 <= slv_reg24;
-- slv_reg25_w1 <= slv_reg25;
-- slv_reg26_w1 <= slv_reg26;
-- slv_reg27_w1 <= slv_reg27;
-- slv_reg28_w1 <= slv_reg28;
-- slv_reg30_w1 <= slv_reg30;
--
-- slv_reg32_w1 <= slv_reg32;
-- slv_reg33_w1 <= slv_reg33;
-- slv_reg34_w1 <= slv_reg34;
-- slv_reg35_w1 <= slv_reg35;
-- slv_reg36_w1 <= slv_reg36;
-- slv_reg37_w1 <= slv_reg37;
-- slv_reg38_w1 <= slv_reg38;
-- slv_reg39_w1 <= slv_reg39;
--
-- slv_reg55_w1 <= slv_reg55;
-- slv_reg56_w1 <= slv_reg56;
-- slv_reg57_w1 <= slv_reg57;
-- slv_reg58_w1 <= slv_reg58;
-- slv_reg59_w1 <= slv_reg59;
-- slv_reg60_w1 <= slv_reg60;
-- slv_reg61_w1 <= slv_reg61;
-- slv_reg62_w1 <= slv_reg62;
-- slv_reg63_w1 <= slv_reg63;
--
-- 0x10 - ISERDES_CONTROL
-- [ 0] ISERDES_RESET
-- [ 1] ISERDES_AUTO_ALIGN
-- [ 2] ISERDES_ALIGN_START
-- [ 3] ISERDES_FIFO_ENABLE
-- [ 8] ISERDES_CLK_READY
-- [ 9] ISERDES_ALIGN_BUSY
-- [10] ISERDES_ALIGNED
-- [23:16] ISERDES_TXCLK_STATUS
-- [31:24] ISERDES_RXCLK_STATUS
host_iserdes_reset <= slv_reg4_w1(0);
host_iserdes_auto_align <= slv_reg4_w1(1);
host_iserdes_align_start <= slv_reg4_w1(2);
host_iserdes_fifo_enable <= slv_reg4_w1(3);
slv_reg4_r1 <= host_iserdes_clk_status &
"00000" & host_iserdes_aligned & host_iserdes_align_busy & host_iserdes_clk_ready &
"0000" & host_iserdes_fifo_enable & host_iserdes_align_start & host_iserdes_auto_align & host_iserdes_reset;
--
-- 0x14 - ISERDES_TRAINING
host_iserdes_training <= slv_reg5_w1(9 downto 0);
--
-- 0x18 - ISERDES_MANUAL_TAP
host_iserdes_manual_tap <= slv_reg6_w1(9 downto 0);
--
-- 0x20 - DECODER_CONTROL[7:0]
-- [0] DECODER_RESET
-- [1] DECODER_ENABLE
host_decoder_reset <= slv_reg8_w1(0);
host_decoder_enable <= slv_reg8_w1(1);
--
-- 0x24 - DECODER_STARTODDEVEN
host_decoder_startoddeven <= slv_reg9_w1;
--
-- 0x28 - DECODER_CODES_LS_LE
host_decoder_code_ls <= slv_reg10_w1( 9 downto 0);
host_decoder_code_le <= slv_reg10_w1(25 downto 16);
--
-- 0x2C - DECODER_CODES_FS_FE
host_decoder_code_fs <= slv_reg11_w1( 9 downto 0);
host_decoder_code_fe <= slv_reg11_w1(25 downto 16);
--
-- 0x30 - DECODER_CODES_BL_IMG
host_decoder_code_bl <= slv_reg12_w1( 9 downto 0);
host_decoder_code_img <= slv_reg12_w1(25 downto 16);
--
-- 0x34 - DECODER_CODES_TR_CRC
host_decoder_code_tr <= slv_reg13_w1( 9 downto 0);
host_decoder_code_crc <= slv_reg13_w1(25 downto 16);
if ( host_decoder_frame_start = '1' ) then
--
-- 0x38 - DECODER_CNT_BLACK_LINES
slv_reg14_r1 <= host_decoder_cnt_black_lines;
--
-- 0x3C - DECODER_CNT_IMAGE_LINES
slv_reg15_r1 <= host_decoder_cnt_image_lines;
--
-- 0x40 - DECODER_CNT_BLACK_PIXELS
slv_reg16_r1 <= host_decoder_cnt_black_pixels;
--
-- 0x44 - DECODER_CNT_IMAGE_PIXELS
slv_reg17_r1 <= host_decoder_cnt_image_pixels;
--
-- 0x48 - DECODER_CNT_FRAMES
slv_reg18_r1 <= host_decoder_cnt_frames;
--
-- 0x4C - DECODER_CNT_WINDOWS
slv_reg19_r1 <= host_decoder_cnt_windows;
--
-- 0x50 - DECODER_CNT_CLOCKS
slv_reg20_r1 <= host_decoder_cnt_clocks;
--
-- 0x54 - DECODER_CNT_START_LINES
slv_reg21_r1 <= host_decoder_cnt_start_lines;
--
-- 0x58 - DECODER_CNT_END_LINES
slv_reg22_r1 <= host_decoder_cnt_end_lines;
end if; --if ( host_decoder_frame_start = '1' ) then
-- 0x5C - SYNCGEN_DELAY
-- [15: 0] DELAY
host_syncgen_delay <= slv_reg23_w1(15 downto 0);
-- 0x60 - SYNCGEN_HTIMING1
-- [15: 0] HACTIVE
-- [31:16] HFPORCH
-- 0x64 - SYNCGEN_HTIMING2
-- [15: 0] HSYNC
-- [31:16] HBPORCH
-- 0x68 - SYNCGEN_VTIMING1
-- [15: 0] VACTIVE
-- [31:16] VFPORCH
-- 0x6C - SYNCGEN_VTIMING2
-- [15: 0] VSYNC
-- [31:16] VBPORCH
host_syncgen_hactive <= slv_reg24_w1(15 downto 0);
host_syncgen_hfporch <= slv_reg24_w1(31 downto 16);
host_syncgen_hsync <= slv_reg25_w1(15 downto 0);
host_syncgen_hbporch <= slv_reg25_w1(31 downto 16);
host_syncgen_vactive <= slv_reg26_w1(15 downto 0);
host_syncgen_vfporch <= slv_reg26_w1(31 downto 16);
host_syncgen_vsync <= slv_reg27_w1(15 downto 0);
host_syncgen_vbporch <= slv_reg27_w1(31 downto 16);
--
-- 0x70 - CRC_CONTROL[7:0]
-- [0] CRC_RESET
-- [1] CRC_INITVALUE
host_crc_reset <= slv_reg28_w1(0);
host_crc_initvalue <= slv_reg28_w1(1);
--
-- 0x74 - CRC_STATUS
slv_reg29_r1 <= host_crc_status;
--
-- 0x78 - REMAPPER_CONTROL[7:0]
-- [2:0] REMAPPER_WRITE_CFG
-- [6:4] REMAPPER_MODE
host_remapper_write_cfg <= slv_reg30_w1(2 downto 0);
host_remapper_mode <= slv_reg30_w1(6 downto 4);
-- 0x80 - FPN_PRNU_VALUES[ 31: 0]
-- 0x84 - FPN_PRNU_VALUES[ 63: 32]
-- 0x88 - FPN_PRNU_VALUES[ 95: 64]
-- 0x8C - FPN_PRNU_VALUES[127: 96]
-- 0x90 - FPN_PRNU_VALUES[159:128]
-- 0x94 - FPN_PRNU_VALUES[191:160]
-- 0x98 - FPN_PRNU_VALUES[223:192]
-- 0x9C - FPN_PRNU_VALUES[255:224]
host_fpn_prnu_values( 31 downto 0) <= slv_reg32_w1;
host_fpn_prnu_values( 63 downto 32) <= slv_reg33_w1;
host_fpn_prnu_values( 95 downto 64) <= slv_reg34_w1;
host_fpn_prnu_values(127 downto 96) <= slv_reg35_w1;
host_fpn_prnu_values(159 downto 128) <= slv_reg36_w1;
host_fpn_prnu_values(191 downto 160) <= slv_reg37_w1;
host_fpn_prnu_values(223 downto 192) <= slv_reg38_w1;
host_fpn_prnu_values(255 downto 224) <= slv_reg39_w1;
--
-- 0xC0 - DECODER_CNT_MONITOR0_HIGH
slv_reg48_r1 <= host_decoder_cnt_monitor0high;
--
-- 0xC4 - DECODER_CNT_MONITOR0_LOW
slv_reg49_r1 <= host_decoder_cnt_monitor0low;
--
-- 0xC8 - DECODER_CNT_MONITOR1_HIGH
slv_reg50_r1 <= host_decoder_cnt_monitor1high;
--
-- 0xCC - DECODER_CNT_MONITOR1_LOW
slv_reg51_r1 <= host_decoder_cnt_monitor1low;
--
-- 0xDC - TRIGGEN_EXT_DEBOUNCE
host_triggen_ext_debounce <= slv_reg55_w1;
--
-- 0xE0 - TRIGGEN_CONTROL
-- [ 2: 0] TRIGGEN_ENABLE
-- [ 6: 4] TRIGGEN_SYNC2READOUT
-- [ 8] TRIGGEN_READOUTTRIGGER
-- [ 16] TRIGGEN_EXT_POLARITY
-- [ 24] TRIGGEN_CNT_UPDATE
-- [30:28] TRIGGEN_GEN_POLARITY
host_triggen_enable <= slv_reg56_w1(2 downto 0);
host_triggen_sync2readout <= slv_reg56_w1(6 downto 4);
host_triggen_readouttrigger <= slv_reg56_w1(8);
host_triggen_ext_polarity <= slv_reg56_w1(16);
host_triggen_cnt_update <= slv_reg56_w1(24);
host_triggen_gen_polarity <= slv_reg56_w1(30 downto 28);
--
-- 0xE4 - TRIGGEN_DEFAULT_FREQ
host_triggen_default_freq <= slv_reg57_w1;
--
if ( host_triggen_cnt_update = '1' ) then
--
-- 0xE8 - TRIGGEN_TRIG0_HIGH
host_triggen_cnt_trigger0high <= slv_reg58_w1;
--
-- 0xEC - TRIGGEN_TRIG0_LOW
host_triggen_cnt_trigger0low <= slv_reg59_w1;
--
-- 0xF0 - TRIGGEN_TRIG1_HIGH
host_triggen_cnt_trigger1high <= slv_reg60_w1;
--
-- 0xF4 - TRIGGEN_TRIG1_LOW
host_triggen_cnt_trigger1low <= slv_reg61_w1;
--
-- 0xF8 - TRIGGEN_TRIG2_HIGH
host_triggen_cnt_trigger2high <= slv_reg62_w1;
--
-- 0xFC - TRIGGEN_TRIG2_LOW
host_triggen_cnt_trigger2low <= slv_reg63_w1;
--
end if; -- if ( host_triggen_cnt_update == '1' ) then
end if;
end if;
end process host_iserdes_process;
------------------------------------------
-- VITA Receiver Core Logic
------------------------------------------
VITA_CORE_I : entity fmc_imageon_vita_receiver_v1_13_a.fmc_imageon_vita_core
generic map
(
C_XSVI_DATA_WIDTH => C_XSVI_DATA_WIDTH,
C_XSVI_DIRECT_OUTPUT => C_XSVI_DIRECT_OUTPUT,
C_XSVI_USE_SYNCGEN => C_XSVI_USE_SYNCGEN,
C_FAMILY => C_FAMILY
)
port map
(
clk200 => clk200,
clk => clk,
clk4x => clk4x,
reset => reset,
oe => oe,
-- HOST Interface - VITA
host_vita_reset => host_vita_reset,
-- HOST Interface - SPI
host_spi_clk => host_spi_clk,
host_spi_reset => host_spi_reset,
host_spi_timing => host_spi_timing,
host_spi_status_busy => host_spi_status_busy,
host_spi_status_error => host_spi_status_error,
host_spi_txfifo_clk => host_spi_txfifo_clk,
host_spi_txfifo_wen => host_spi_txfifo_wen,
host_spi_txfifo_din => host_spi_txfifo_din,
host_spi_txfifo_full => host_spi_txfifo_full,
host_spi_rxfifo_clk => host_spi_rxfifo_clk,
host_spi_rxfifo_ren => host_spi_rxfifo_ren,
host_spi_rxfifo_dout => host_spi_rxfifo_dout,
host_spi_rxfifo_empty => host_spi_rxfifo_empty,
-- HOST Interface - ISERDES
host_iserdes_reset => host_iserdes_reset,
host_iserdes_auto_align => host_iserdes_auto_align,
host_iserdes_align_start => host_iserdes_align_start,
host_iserdes_fifo_enable => host_iserdes_fifo_enable,
host_iserdes_manual_tap => host_iserdes_manual_tap,
host_iserdes_training => host_iserdes_training,
host_iserdes_clk_ready => host_iserdes_clk_ready,
host_iserdes_clk_status => host_iserdes_clk_status,
host_iserdes_align_busy => host_iserdes_align_busy,
host_iserdes_aligned => host_iserdes_aligned,
-- HOST Interface - Sync Channel Decoder
host_decoder_reset => host_decoder_reset,
host_decoder_enable => host_decoder_enable,
host_decoder_startoddeven => host_decoder_startoddeven,
host_decoder_code_ls => host_decoder_code_ls,
host_decoder_code_le => host_decoder_code_le,
host_decoder_code_fs => host_decoder_code_fs,
host_decoder_code_fe => host_decoder_code_fe,
host_decoder_code_bl => host_decoder_code_bl,
host_decoder_code_img => host_decoder_code_img,
host_decoder_code_tr => host_decoder_code_tr,
host_decoder_code_crc => host_decoder_code_crc,
host_decoder_frame_start => host_decoder_frame_start,
host_decoder_cnt_black_lines => host_decoder_cnt_black_lines,
host_decoder_cnt_image_lines => host_decoder_cnt_image_lines,
host_decoder_cnt_black_pixels => host_decoder_cnt_black_pixels,
host_decoder_cnt_image_pixels => host_decoder_cnt_image_pixels,
host_decoder_cnt_frames => host_decoder_cnt_frames,
host_decoder_cnt_windows => host_decoder_cnt_windows,
host_decoder_cnt_clocks => host_decoder_cnt_clocks,
host_decoder_cnt_start_lines => host_decoder_cnt_start_lines,
host_decoder_cnt_end_lines => host_decoder_cnt_end_lines,
host_decoder_cnt_monitor0high => host_decoder_cnt_monitor0high,
host_decoder_cnt_monitor0low => host_decoder_cnt_monitor0low,
host_decoder_cnt_monitor1high => host_decoder_cnt_monitor1high,
host_decoder_cnt_monitor1low => host_decoder_cnt_monitor1low,
-- HOST Interface - CRC Checker
host_crc_reset => host_crc_reset,
host_crc_initvalue => host_crc_initvalue,
host_crc_status => host_crc_status,
-- HOST Interface - Data Channel Remapper
host_remapper_write_cfg => host_remapper_write_cfg,
host_remapper_mode => host_remapper_mode,
-- HOST Interface - Trigger Generator
host_triggen_enable => host_triggen_enable,
host_triggen_sync2readout => host_triggen_sync2readout,
host_triggen_readouttrigger => host_triggen_readouttrigger,
host_triggen_default_freq => host_triggen_default_freq,
host_triggen_cnt_trigger0high => host_triggen_cnt_trigger0high,
host_triggen_cnt_trigger0low => host_triggen_cnt_trigger0low,
host_triggen_cnt_trigger1high => host_triggen_cnt_trigger1high,
host_triggen_cnt_trigger1low => host_triggen_cnt_trigger1low,
host_triggen_cnt_trigger2high => host_triggen_cnt_trigger2high,
host_triggen_cnt_trigger2low => host_triggen_cnt_trigger2low,
host_triggen_ext_debounce => host_triggen_ext_debounce,
host_triggen_ext_polarity => host_triggen_ext_polarity,
host_triggen_gen_polarity => host_triggen_gen_polarity,
-- HOST Interface - FPN/PRNU Correction
host_fpn_prnu_values => host_fpn_prnu_values,
-- HOST Interface - Sync Generator
host_syncgen_delay => host_syncgen_delay,
host_syncgen_hactive => host_syncgen_hactive,
host_syncgen_hfporch => host_syncgen_hfporch,
host_syncgen_hsync => host_syncgen_hsync,
host_syncgen_hbporch => host_syncgen_hbporch,
host_syncgen_vactive => host_syncgen_vactive,
host_syncgen_vfporch => host_syncgen_vfporch,
host_syncgen_vsync => host_syncgen_vsync,
host_syncgen_vbporch => host_syncgen_vbporch,
-- I/O pins
io_vita_clk_pll => io_vita_clk_pll,
io_vita_reset_n => io_vita_reset_n,
io_vita_spi_sclk => io_vita_spi_sclk,
io_vita_spi_ssel_n => io_vita_spi_ssel_n,
io_vita_spi_mosi => io_vita_spi_mosi,
io_vita_spi_miso => io_vita_spi_miso,
io_vita_trigger => io_vita_trigger,
io_vita_monitor => io_vita_monitor,
io_vita_clk_out_p => io_vita_clk_out_p,
io_vita_clk_out_n => io_vita_clk_out_n,
io_vita_sync_p => io_vita_sync_p,
io_vita_sync_n => io_vita_sync_n,
io_vita_data_p => io_vita_data_p,
io_vita_data_n => io_vita_data_n,
-- Trigger Port
trigger1 => trigger1,
-- Frame Sync Port
fsync => fsync,
-- XSVI Port
xsvi_vsync_o => xsvi_vsync_o,
xsvi_hsync_o => xsvi_hsync_o,
xsvi_vblank_o => xsvi_vblank_o,
xsvi_hblank_o => xsvi_hblank_o,
xsvi_active_video_o => xsvi_active_video_o,
xsvi_video_data_o => xsvi_video_data_o,
-- Debug Port
debug_spi_o => debug_spi_o,
debug_iserdes_o => debug_iserdes_o,
debug_decoder_o => debug_decoder_o,
debug_crc_o => debug_crc_o,
debug_triggen_o => debug_triggen_o,
debug_video_o => debug_video_o
);
--
-- Debug Port
-- Can be used to connect to ChipScope for debugging.
-- Having a port makes these signals accessible for debug via EDK.
--
debug_host_l : process (Bus2IP_Clk)
begin
if Rising_Edge(Bus2IP_Clk) then
debug_host_o( 31 downto 0) <= Bus2IP_Addr;
debug_host_o( 63 downto 32) <= Bus2IP_Data;
debug_host_o( 95 downto 64) <= slv_ip2bus_data;
debug_host_o(159 downto 96) <= Bus2IP_WrCE;
debug_host_o(223 downto 160) <= Bus2IP_RdCE;
debug_host_o( 224) <= Bus2IP_CS(0);
debug_host_o( 225) <= Bus2IP_RNW;
debug_host_o(229 downto 226) <= Bus2IP_BE;
debug_host_o( 230) <= slv_write_ack;
debug_host_o( 231) <= slv_read_ack;
end if;
end process;
end IMP;
|
gpl-3.0
|
db95bf1b1380c3b0ad755cdb55847437
| 0.506188 | 3.775155 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/sseg_4x.vhd
| 2 | 3,193 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:42 01/14/2015
-- Design Name:
-- Module Name: sseg_4x - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity sseg_4x is
generic(
clock_freq_hz : natural := 100_000_000;
refresh_rate_hz : natural := 100
);
port(
clk, reset : in std_logic ;
bcd_in : in std_logic_vector(15 downto 0);
-- SSEG to EDU from Host
sseg_cathode_out : out std_logic_vector(4 downto 0); -- common cathode
sseg_anode_out : out std_logic_vector(7 downto 0) -- sseg anode
);
end sseg_4x;
architecture Behavioral of sseg_4x is
constant clk_divider : positive := clock_freq_hz/(refresh_rate_hz*5);
signal divider_counter : std_logic_vector(nbit(clk_divider)-1 downto 0);
signal divider_end : std_logic ;
signal cathode_buffer : std_logic_vector(4 downto 0);
signal segs : slv8_array(0 to 3) ;
begin
gen_seg_decoder : for i in 0 to 3 generate
with bcd_in(((i+1)*4)-1 downto (i*4)) select
segs(i) <= X"3F" when "0000",
X"06" when "0001",
X"5B" when "0010",
X"4F" when "0011",
X"66" when "0100",
X"6D" when "0101",
X"7D" when "0110",
X"07" when "0111",
X"7F" when "1000",
X"6F" when "1001",
X"77" when "1010",
X"7C" when "1011",
X"39" when "1100",
X"5E" when "1101",
X"79" when "1110",
X"71" when others;
end generate ;
-- sseg logic
process(clk, reset)
begin
if reset = '1' then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= std_logic_vector(to_unsigned(clk_divider, nbit(clk_divider)));
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
divider_end <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cathode_buffer(0) <= '1' ;
cathode_buffer(4 downto 1) <= (others => '0');
elsif clk'event and clk = '1' then
if divider_end = '1' then
cathode_buffer(4 downto 1) <= cathode_buffer(3 downto 0);
cathode_buffer(0) <= cathode_buffer(4);
end if ;
end if ;
end process ;
with cathode_buffer select
sseg_anode_out <= segs(0) when "01000",
segs(1) when "00100",
segs(2) when "00010",
segs(3) when "00001",
(others => '0') when others ;
sseg_cathode_out <= cathode_buffer ;
end Behavioral;
|
lgpl-3.0
|
3e28db3f46015a21f776ead5e01946b5
| 0.597557 | 3.124266 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altmult_accum/_primary.vhd
| 1 | 17,708 |
library verilog;
use verilog.vl_types.all;
entity altmult_accum is
generic(
width_a : integer := 2;
width_b : integer := 2;
width_c : integer := 22;
width_result : integer := 5;
number_of_multipliers: integer := 1;
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
multiplier1_direction: string := "UNUSED";
multiplier3_direction: string := "UNUSED";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg: string := "CLOCK0";
addnsub_pipeline_aclr: string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr: string := "ACLR3";
accum_sload_pipeline_reg: string := "CLOCK0";
accum_sload_pipeline_aclr: string := "ACLR3";
representation_a: string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a: string := "CLOCK0";
sign_pipeline_aclr_a: string := "ACLR3";
port_signb : string := "PORT_CONNECTIVITY";
representation_b: string := "UNSIGNED";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b: string := "CLOCK0";
sign_pipeline_aclr_b: string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR3";
lpm_type : string := "altmult_accum";
lpm_hint : string := "UNUSED";
extra_multiplier_latency: integer := 0;
extra_accumulator_latency: integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
intended_device_family: string := "Stratix";
accum_round_aclr: string := "ACLR3";
accum_round_pipeline_aclr: string := "ACLR3";
accum_round_pipeline_reg: string := "CLOCK0";
accum_round_reg : string := "CLOCK0";
accum_saturation_aclr: string := "ACLR3";
accum_saturation_pipeline_aclr: string := "ACLR3";
accum_saturation_pipeline_reg: string := "CLOCK0";
accum_saturation_reg: string := "CLOCK0";
accum_sload_upper_data_aclr: string := "ACLR3";
accum_sload_upper_data_pipeline_aclr: string := "ACLR3";
accum_sload_upper_data_pipeline_reg: string := "CLOCK0";
accum_sload_upper_data_reg: string := "CLOCK0";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr: string := "ACLR3";
mult_saturation_reg: string := "CLOCK0";
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
width_upper_data: integer := 1;
multiplier_rounding: string := "NO";
multiplier_saturation: string := "NO";
accumulator_rounding: string := "NO";
accumulator_saturation: string := "NO";
port_mult_is_saturated: string := "UNUSED";
port_accum_is_saturated: string := "UNUSED";
int_width_a : vl_notype;
int_width_b : vl_notype;
int_width_result: vl_notype;
int_extra_width : vl_notype;
diff_width_a : vl_notype;
diff_width_b : vl_notype;
sat_for_ini : vl_notype;
mult_round_for_ini: vl_notype;
bits_to_round : vl_notype;
sload_for_limit : vl_notype;
accum_sat_for_limit: vl_notype;
int_width_extra_bit: vl_notype;
preadder_mode : string := "SIMPLE";
loadconst_value : integer := 0;
width_coef : integer := 0;
loadconst_control_register: string := "CLOCK0";
loadconst_control_aclr: string := "ACLR0";
coefsel0_register: string := "CLOCK0";
coefsel1_register: string := "CLOCK0";
coefsel2_register: string := "CLOCK0";
coefsel3_register: string := "CLOCK0";
coefsel0_aclr : string := "ACLR0";
coefsel1_aclr : string := "ACLR0";
coefsel2_aclr : string := "ACLR0";
coefsel3_aclr : string := "ACLR0";
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
datac : in vl_logic_vector;
scanina : in vl_logic_vector;
scaninb : in vl_logic_vector;
sourcea : in vl_logic;
sourceb : in vl_logic;
accum_sload_upper_data: in vl_logic_vector;
addnsub : in vl_logic;
accum_sload : in vl_logic;
signa : in vl_logic;
signb : in vl_logic;
clock0 : in vl_logic;
clock1 : in vl_logic;
clock2 : in vl_logic;
clock3 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
aclr0 : in vl_logic;
aclr1 : in vl_logic;
aclr2 : in vl_logic;
aclr3 : in vl_logic;
result : out vl_logic_vector;
overflow : out vl_logic;
scanouta : out vl_logic_vector;
scanoutb : out vl_logic_vector;
mult_round : in vl_logic;
mult_saturation : in vl_logic;
accum_round : in vl_logic;
accum_saturation: in vl_logic;
mult_is_saturated: out vl_logic;
accum_is_saturated: out vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of width_c : constant is 1;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of input_reg_a : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a : constant is 1;
attribute mti_svvh_generic_type of multiplier1_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier3_direction : constant is 1;
attribute mti_svvh_generic_type of input_reg_b : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b : constant is 1;
attribute mti_svvh_generic_type of port_addnsub : constant is 1;
attribute mti_svvh_generic_type of addnsub_reg : constant is 1;
attribute mti_svvh_generic_type of addnsub_aclr : constant is 1;
attribute mti_svvh_generic_type of addnsub_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of addnsub_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of accum_sload_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of representation_a : constant is 1;
attribute mti_svvh_generic_type of port_signa : constant is 1;
attribute mti_svvh_generic_type of sign_reg_a : constant is 1;
attribute mti_svvh_generic_type of sign_aclr_a : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_reg_a : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_aclr_a : constant is 1;
attribute mti_svvh_generic_type of port_signb : constant is 1;
attribute mti_svvh_generic_type of representation_b : constant is 1;
attribute mti_svvh_generic_type of sign_reg_b : constant is 1;
attribute mti_svvh_generic_type of sign_aclr_b : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_reg_b : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_aclr_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_reg : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr : constant is 1;
attribute mti_svvh_generic_type of output_reg : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of extra_multiplier_latency : constant is 1;
attribute mti_svvh_generic_type of extra_accumulator_latency : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of accum_round_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_round_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_round_reg : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_reg : constant is 1;
attribute mti_svvh_generic_type of mult_round_aclr : constant is 1;
attribute mti_svvh_generic_type of mult_round_reg : constant is 1;
attribute mti_svvh_generic_type of mult_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of mult_saturation_reg : constant is 1;
attribute mti_svvh_generic_type of input_source_a : constant is 1;
attribute mti_svvh_generic_type of input_source_b : constant is 1;
attribute mti_svvh_generic_type of width_upper_data : constant is 1;
attribute mti_svvh_generic_type of multiplier_rounding : constant is 1;
attribute mti_svvh_generic_type of multiplier_saturation : constant is 1;
attribute mti_svvh_generic_type of accumulator_rounding : constant is 1;
attribute mti_svvh_generic_type of accumulator_saturation : constant is 1;
attribute mti_svvh_generic_type of port_mult_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_accum_is_saturated : constant is 1;
attribute mti_svvh_generic_type of int_width_a : constant is 3;
attribute mti_svvh_generic_type of int_width_b : constant is 3;
attribute mti_svvh_generic_type of int_width_result : constant is 3;
attribute mti_svvh_generic_type of int_extra_width : constant is 3;
attribute mti_svvh_generic_type of diff_width_a : constant is 3;
attribute mti_svvh_generic_type of diff_width_b : constant is 3;
attribute mti_svvh_generic_type of sat_for_ini : constant is 3;
attribute mti_svvh_generic_type of mult_round_for_ini : constant is 3;
attribute mti_svvh_generic_type of bits_to_round : constant is 3;
attribute mti_svvh_generic_type of sload_for_limit : constant is 3;
attribute mti_svvh_generic_type of accum_sat_for_limit : constant is 3;
attribute mti_svvh_generic_type of int_width_extra_bit : constant is 3;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_register : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel0_register : constant is 1;
attribute mti_svvh_generic_type of coefsel1_register : constant is 1;
attribute mti_svvh_generic_type of coefsel2_register : constant is 1;
attribute mti_svvh_generic_type of coefsel3_register : constant is 1;
attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of coef0_0 : constant is 1;
attribute mti_svvh_generic_type of coef0_1 : constant is 1;
attribute mti_svvh_generic_type of coef0_2 : constant is 1;
attribute mti_svvh_generic_type of coef0_3 : constant is 1;
attribute mti_svvh_generic_type of coef0_4 : constant is 1;
attribute mti_svvh_generic_type of coef0_5 : constant is 1;
attribute mti_svvh_generic_type of coef0_6 : constant is 1;
attribute mti_svvh_generic_type of coef0_7 : constant is 1;
attribute mti_svvh_generic_type of coef1_0 : constant is 1;
attribute mti_svvh_generic_type of coef1_1 : constant is 1;
attribute mti_svvh_generic_type of coef1_2 : constant is 1;
attribute mti_svvh_generic_type of coef1_3 : constant is 1;
attribute mti_svvh_generic_type of coef1_4 : constant is 1;
attribute mti_svvh_generic_type of coef1_5 : constant is 1;
attribute mti_svvh_generic_type of coef1_6 : constant is 1;
attribute mti_svvh_generic_type of coef1_7 : constant is 1;
attribute mti_svvh_generic_type of coef2_0 : constant is 1;
attribute mti_svvh_generic_type of coef2_1 : constant is 1;
attribute mti_svvh_generic_type of coef2_2 : constant is 1;
attribute mti_svvh_generic_type of coef2_3 : constant is 1;
attribute mti_svvh_generic_type of coef2_4 : constant is 1;
attribute mti_svvh_generic_type of coef2_5 : constant is 1;
attribute mti_svvh_generic_type of coef2_6 : constant is 1;
attribute mti_svvh_generic_type of coef2_7 : constant is 1;
attribute mti_svvh_generic_type of coef3_0 : constant is 1;
attribute mti_svvh_generic_type of coef3_1 : constant is 1;
attribute mti_svvh_generic_type of coef3_2 : constant is 1;
attribute mti_svvh_generic_type of coef3_3 : constant is 1;
attribute mti_svvh_generic_type of coef3_4 : constant is 1;
attribute mti_svvh_generic_type of coef3_5 : constant is 1;
attribute mti_svvh_generic_type of coef3_6 : constant is 1;
attribute mti_svvh_generic_type of coef3_7 : constant is 1;
end altmult_accum;
|
bsd-2-clause
|
e9556ec2d7e342fa5c8babf8efa764fb
| 0.624915 | 3.643621 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng.vhd
| 1 | 4,004 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
76067754583334f59c2fccdebc6cdca4
| 0.641858 | 4.241525 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/pid_filter.vhd
| 2 | 5,699 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 17:37:14 07/01/2013
-- Design Name:
-- Module Name: pid_filter - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
-- inspired by http://crap.gforge.inria.fr/doc2.php
entity pid_filter is
generic(clk_period_ns : integer := 8;
pid_period_ns : integer := 20000000); -- 50Hz PID for RC based ESC
port(
clk, resetn : in std_logic ;
en : in std_logic ;
K, AK : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
setpoint : in signed(15 downto 0);
measure : in signed(15 downto 0);
cmd : out std_logic_vector(15 downto 0);
dir : out std_logic
);
end pid_filter;
architecture Behavioral of pid_filter is
constant tick_modulo : integer := (pid_period_ns/clk_period_ns)-1 ;
signal tick_count : std_logic_vector(nbit(tick_modulo)-1 downto 0);
signal cycle_count, cycle_count_old : std_logic_vector(1 downto 0);
signal en_cycle_counter : std_logic ;
signal reload : std_logic ;
signal acc, sum : signed(31 downto 0);
signal mult_op : unsigned(31 downto 0);
signal op1, op2 : unsigned(15 downto 0);
signal mc, xn, xnn : signed(15 downto 0);
signal xn_sign, xnn_sign, mc_sign, sign, sign_latched : std_logic ;
signal latch_res : std_logic ;
begin
process(clk, resetn)
begin
if resetn= '0' then
tick_count <= std_logic_vector(to_unsigned(tick_modulo, nbit(tick_modulo)));
elsif clk'event and clk='1' then
if reload= '1' then
tick_count <= std_logic_vector(to_unsigned(tick_modulo, nbit(tick_modulo)));
else
tick_count <= tick_count - 1 ;
end if ;
end if ;
end process ;
reload <= '1' when tick_count = 0 else
'0' ;
process(clk, resetn)
begin
if resetn= '0' then
cycle_count <=(others => '1');
cycle_count_old <= (others => '0');
elsif clk'event and clk='1' then
if reload= '1' then
cycle_count <=(others => '1');
elsif en_cycle_counter = '1' then
cycle_count <= cycle_count - 1 ;
end if ;
cycle_count_old <= cycle_count ;
end if ;
end process ;
en_cycle_counter <= '1' when cycle_count /= 0 else
'0';
process(clk, resetn)
begin
if resetn = '0' then
mult_op <= (others => '0') ;
elsif clk'event and clk = '1' then
if reload = '1' then
mult_op <= (others => '0') ;
else
mult_op <= op1 * op2 ;
end if ;
end if ;
end process ;
sum <= (acc - signed(mult_op)) when sign_latched = '0' else
(acc + signed(mult_op)) ;
process(clk, resetn)
begin
if resetn = '0' then
acc <= (others => '0') ;
sign_latched <= '0' ;
elsif clk'event and clk = '1' then
if reload = '1' then
acc <= (others => '0') ;
else
acc <= sum;
end if ;
sign_latched <= sign ;
end if ;
end process ;
-- sequence
-- 1) acc += K * xn
-- 2) acc -= AK * xn-1
-- 3) acc += B * mcn-1
-- 4) mcn = acc/1024
with cycle_count select
op1 <= unsigned(K) when "11",
unsigned(AK) when "10",
unsigned(B) when "01",
(others => '0') when others;
with cycle_count select
op2 <= unsigned(abs(xn)) when "11",
unsigned(abs(xnn)) when "10",
unsigned(abs(mc)) when "01",
(others => '0') when others;
with cycle_count select
sign <= xn_sign when "11",
(NOT xnn_sign) when "10",
mc_sign when "01",
'0' when others;
xn_sign <= '1' when xn > 0 else
'0' ;
xnn_sign <= '1' when xnn > 0 else
'0' ;
mc_sign <= '1' when mc > 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
xnn <= (others => '0') ;
xn <= (others => '0') ;
elsif clk'event and clk = '1' then
if reload = '1' then
xn <= setpoint - measure ;
xnn <= xn ;
end if ;
end if ;
end process ;
latch_res <= '1' when cycle_count = 0 and cycle_count_old=1 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
mc <= (others => '0') ;
elsif clk'event and clk = '1' then
if latch_res = '1' then
mc <= acc(25 downto 10) ;
end if ;
end if ;
end process ;
cmd <= (others => '0') when en = '0' else
(not std_logic_vector(mc)) when mc < 0 else
std_logic_vector(mc) ;
dir <= '1' when mc < 0 else
'0' ;
end Behavioral;
|
lgpl-3.0
|
3abb056c652a9a686524b3f8e98166d8
| 0.60765 | 3.13304 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_mux.vhd
| 1 | 6,165 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2011-01-11 13:22:13 +0100 (di, 11 jan 2011) $
-- Revision : $Revision: 712 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--xilinx:
---------
--Library XilinxCoreLib;
library unisim;
use unisim.vcomponents.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity iserdes_mux is
generic(
DATAWIDTH : integer;
NROF_CONN : integer
);
port(
CLOCK : in std_logic;
RESET : in std_logic;
CLKDIV : in std_logic;
-- select comes from the bitalign/wordalign statemachine and is aligned to CLOCK
SEL : in std_logic_vector(15 downto 0);
-- from/to ISERDES
IODELAY_ISERDES_RESET : out std_logic_vector(NROF_CONN-1 downto 0);
IODELAY_INC : out std_logic_vector(NROF_CONN-1 downto 0);
IODELAY_CE : out std_logic_vector(NROF_CONN-1 downto 0);
ISERDES_BITSLIP : out std_logic_vector(NROF_CONN-1 downto 0);
ISERDES_DATA : in std_logic_vector((DATAWIDTH*NROF_CONN)-1 downto 0);
-- made as a one dimensional array, multidimensional arrays parameterisable with generics do not exist in VHDL
--from/to sync
SYNC_RESET : in std_logic;
SYNC_INC : in std_logic;
SYNC_CE : in std_logic;
SYNC_BITSLIP : in std_logic;
SYNC_DATA : out std_logic_vector(DATAWIDTH-1 downto 0)
);
end iserdes_mux;
architecture rtl of iserdes_mux is
begin
muxgen: if (NROF_CONN > 1) generate
multiplexer: process(RESET, CLKDIV)
variable index : integer range 0 to (NROF_CONN-1);
begin
if (RESET = '1') then
IODELAY_ISERDES_RESET <= (others => '0');
IODELAY_INC <= (others => '0');
IODELAY_CE <= (others => '0');
ISERDES_BITSLIP <= (others => '0');
SYNC_DATA <= (others => '0');
elsif (CLKDIV'event and CLKDIV = '1') then
index := TO_INTEGER(UNSIGNED(SEL));
IODELAY_ISERDES_RESET(index) <= SYNC_RESET;
IODELAY_INC(index) <= SYNC_INC;
IODELAY_CE(index) <= SYNC_CE;
SYNC_DATA <= ISERDES_DATA(((index+1)*DATAWIDTH)-1 downto (index*DATAWIDTH));
ISERDES_BITSLIP(index) <= SYNC_BITSLIP;
end if;
end process multiplexer;
end generate;
nomuxgen: if (NROF_CONN = 1) generate
multiplexer: process(RESET, CLKDIV)
variable index : integer range 0 to (NROF_CONN-1);
begin
if (RESET = '1') then
IODELAY_ISERDES_RESET <= (others => '0');
IODELAY_INC <= (others => '0');
IODELAY_CE <= (others => '0');
ISERDES_BITSLIP <= (others => '0');
SYNC_DATA <= (others => '0');
elsif (CLKDIV'event and CLKDIV = '1') then
IODELAY_ISERDES_RESET(0) <= SYNC_RESET;
IODELAY_INC(0) <= SYNC_INC;
IODELAY_CE(0) <= SYNC_CE;
ISERDES_BITSLIP(0) <= SYNC_BITSLIP;
SYNC_DATA <= ISERDES_DATA;
end if;
end process multiplexer;
end generate;
end rtl;
|
gpl-3.0
|
ad82cb0e84d68f94d19e4c0906c031f7
| 0.474939 | 4.706107 | false | false | false | false |
diedricm/prMagicTutorial
|
src/downcounter.vhd
| 1 | 641 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity downcounter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rst_val : in STD_LOGIC_VECTOR (15 downto 0);
trigger : out STD_LOGIC);
end downcounter;
architecture Behavioral of downcounter is
signal cnt : unsigned(22 downto 0);
begin
trigger <= '1' when cnt = 0 else '0';
process (clk, rst)
begin
if rst = '1' then
cnt <= unsigned(rst_val);
elsif rising_edge(clk) then
cnt <= cnt - 1;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
282810dfeb96f90d83be168eff644925
| 0.555382 | 3.838323 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/virtual_instrument/logi_virtual_pb.vhd
| 2 | 3,235 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:18:41 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_pb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_pb is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
pb : out std_logic_vector(15 downto 0)
);
end logi_virtual_pb;
architecture Behavioral of logi_virtual_pb is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
pb <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
lgpl-3.0
|
727163c4c755350c8eb73050b7aa87cd
| 0.59289 | 3.688712 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_64i_16o_k7_ste/example_design/afifo_64i_16o_k7_top.vhd
| 1 | 19,646 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_64i_16o_k7_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(16-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(14-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_64i_16o_k7_top;
architecture xilinx of afifo_64i_16o_k7_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_64i_16o_k7 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_64i_16o_k7
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
gpl-3.0
|
3abad45c59fa298e32400e71b81fedec
| 0.475771 | 3.951327 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_32_k7.vhd
| 1 | 10,438 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file afifo_32_k7.vhd when simulating
-- the core, afifo_32_k7. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY afifo_32_k7 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END afifo_32_k7;
ARCHITECTURE afifo_32_k7_a OF afifo_32_k7 IS
-- synthesis translate_off
COMPONENT wrapped_afifo_32_k7
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_afifo_32_k7 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 4,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 2,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 13,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 12,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 4,
c_rd_depth => 16,
c_rd_freq => 1,
c_rd_pntr_width => 4,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 4,
c_wr_depth => 16,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 4,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_afifo_32_k7
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END afifo_32_k7_a;
|
gpl-3.0
|
e405c9f7fce8cc80f06686ba66d79d76
| 0.520789 | 3.345513 | false | false | false | false |
CprE488/Final
|
system/pcores/led_pwm_v1_01_a/hdl/vhdl/clk_prescaler.vhd
| 2 | 4,365 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:16 11/19/2014
-- Design Name:
-- Module Name: clk_prescaler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_prescaler is
Port ( in_clk : in STD_LOGIC;
rst : in STD_LOGIC;
prescaler_value : in STD_LOGIC_VECTOR (4 downto 0);
out_clk : out STD_LOGIC);
end clk_prescaler;
architecture Behavioral of clk_prescaler is
signal clk_count : unsigned(31 downto 0);
signal clk_count_vector : std_logic_vector(31 downto 0);
begin
clock_scaler_proc: process(in_clk, rst)
begin
if(rst = '1') then
clk_count <= (others => '0');
out_clk <= '0';
elsif(rising_edge(in_clk)) then
clk_count <= clk_count + 1;
case prescaler_value is
when "00000" =>
out_clk <= in_clk;
when "00001" =>
out_clk <= clk_count_vector(0);
when "00010" =>
out_clk <= clk_count_vector(1);
when "00011" =>
out_clk <= clk_count_vector(2);
when "00100" =>
out_clk <= clk_count_vector(3);
when "00101" =>
out_clk <= clk_count_vector(4);
when "00110" =>
out_clk <= clk_count_vector(5);
when "00111" =>
out_clk <= clk_count_vector(6);
when "01000" =>
out_clk <= clk_count_vector(7);
when "01001" =>
out_clk <= clk_count_vector(8);
when "01010" =>
out_clk <= clk_count_vector(9);
when "01011" =>
out_clk <= clk_count_vector(10);
when "01100" =>
out_clk <= clk_count_vector(11);
when "01101" =>
out_clk <= clk_count_vector(12);
when "01110" =>
out_clk <= clk_count_vector(13);
when "01111" =>
out_clk <= clk_count_vector(14);
when "10000" =>
out_clk <= clk_count_vector(15);
when "10001" =>
out_clk <= clk_count_vector(16);
when "10010" =>
out_clk <= clk_count_vector(17);
when "10011" =>
out_clk <= clk_count_vector(18);
when "10100" =>
out_clk <= clk_count_vector(19);
when "10101" =>
out_clk <= clk_count_vector(20);
when "10110" =>
out_clk <= clk_count_vector(21);
when "10111" =>
out_clk <= clk_count_vector(22);
when "11000" =>
out_clk <= clk_count_vector(23);
when "11001" =>
out_clk <= clk_count_vector(24);
when "11010" =>
out_clk <= clk_count_vector(25);
when "11011" =>
out_clk <= clk_count_vector(26);
when "11100" =>
out_clk <= clk_count_vector(27);
when "11101" =>
out_clk <= clk_count_vector(28);
when "11110" =>
out_clk <= clk_count_vector(29);
when "11111" =>
out_clk <= clk_count_vector(30);
when others =>
out_clk <= '0';
end case;
end if;
end process;
clk_count_vector <= std_logic_vector(clk_count);
end Behavioral;
|
gpl-3.0
|
9016d309c047077ea09b7ac2723b793b
| 0.430011 | 4.304734 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/iserdes_fifo_6_bit.vhd
| 1 | 5,790 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file iserdes_fifo_6_bit.vhd when simulating
-- the core, iserdes_fifo_6_bit. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY iserdes_fifo_6_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(5 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(5 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END iserdes_fifo_6_bit;
ARCHITECTURE iserdes_fifo_6_bit_a OF iserdes_fifo_6_bit IS
-- synthesis translate_off
component wrapped_iserdes_fifo_6_bit
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(5 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(5 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_iserdes_fifo_6_bit use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 6,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "virtex5",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 6,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_iserdes_fifo_6_bit
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty);
-- synthesis translate_on
END iserdes_fifo_6_bit_a;
|
gpl-3.0
|
fd79385e2f7185cf66373cf2c52206b2
| 0.546978 | 3.446429 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_64i_16o_v6.vhd
| 1 | 10,500 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file afifo_64i_16o_v6.vhd when simulating
-- the core, afifo_64i_16o_v6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY afifo_64i_16o_v6 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END afifo_64i_16o_v6;
ARCHITECTURE afifo_64i_16o_v6_a OF afifo_64i_16o_v6 IS
-- synthesis translate_off
COMPONENT wrapped_afifo_64i_16o_v6
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_afifo_64i_16o_v6 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 12,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "virtex6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "4kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 4093,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 4092,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 14,
c_rd_depth => 16384,
c_rd_freq => 1,
c_rd_pntr_width => 14,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 12,
c_wr_depth => 4096,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 12,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_afifo_64i_16o_v6
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END afifo_64i_16o_v6_a;
|
gpl-3.0
|
dc540fdf99616d25baa271b64dcfc13b
| 0.522667 | 3.322785 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/sld_virtual_jtag/_primary.vhd
| 1 | 2,432 |
library verilog;
use verilog.vl_types.all;
entity sld_virtual_jtag is
generic(
lpm_type : string := "SLD_VIRTUAL_JTAG";
lpm_hint : string := "SLD_VIRTUAL_JTAG";
sld_auto_instance_index: string := "NO";
sld_instance_index: integer := 0;
sld_ir_width : integer := 1;
sld_sim_n_scan : integer := 0;
sld_sim_total_length: integer := 0;
sld_sim_action : string := ""
);
port(
tdo : in vl_logic;
ir_out : in vl_logic_vector;
tck : out vl_logic;
tdi : out vl_logic;
ir_in : out vl_logic_vector;
virtual_state_cdr: out vl_logic;
virtual_state_sdr: out vl_logic;
virtual_state_e1dr: out vl_logic;
virtual_state_pdr: out vl_logic;
virtual_state_e2dr: out vl_logic;
virtual_state_udr: out vl_logic;
virtual_state_cir: out vl_logic;
virtual_state_uir: out vl_logic;
jtag_state_tlr : out vl_logic;
jtag_state_rti : out vl_logic;
jtag_state_sdrs : out vl_logic;
jtag_state_cdr : out vl_logic;
jtag_state_sdr : out vl_logic;
jtag_state_e1dr : out vl_logic;
jtag_state_pdr : out vl_logic;
jtag_state_e2dr : out vl_logic;
jtag_state_udr : out vl_logic;
jtag_state_sirs : out vl_logic;
jtag_state_cir : out vl_logic;
jtag_state_sir : out vl_logic;
jtag_state_e1ir : out vl_logic;
jtag_state_pir : out vl_logic;
jtag_state_e2ir : out vl_logic;
jtag_state_uir : out vl_logic;
tms : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of sld_auto_instance_index : constant is 1;
attribute mti_svvh_generic_type of sld_instance_index : constant is 1;
attribute mti_svvh_generic_type of sld_ir_width : constant is 1;
attribute mti_svvh_generic_type of sld_sim_n_scan : constant is 1;
attribute mti_svvh_generic_type of sld_sim_total_length : constant is 1;
attribute mti_svvh_generic_type of sld_sim_action : constant is 1;
end sld_virtual_jtag;
|
bsd-2-clause
|
a6f4f7ffcb2616e71db55b1eb2ed596d
| 0.565378 | 3.340659 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/iserdes_fifo_8_bit.vhd
| 1 | 5,790 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file iserdes_fifo_8_bit.vhd when simulating
-- the core, iserdes_fifo_8_bit. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY iserdes_fifo_8_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END iserdes_fifo_8_bit;
ARCHITECTURE iserdes_fifo_8_bit_a OF iserdes_fifo_8_bit IS
-- synthesis translate_off
component wrapped_iserdes_fifo_8_bit
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_iserdes_fifo_8_bit use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "virtex5",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_iserdes_fifo_8_bit
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty);
-- synthesis translate_on
END iserdes_fifo_8_bit_a;
|
gpl-3.0
|
c8171506c7c660264a5b7339aaca39a1
| 0.546978 | 3.446429 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_nes.vhd
| 2 | 4,337 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
-------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:25:53 12/17/2013
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description: NES (nintendo) controller wishbone driver to access NES data from the EDU board
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_nes is
generic(
wb_size : natural := 16; -- Data port size for wishbone
N: integer := 17 --17 bit overflow 131k
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
--nes data signals
nes1_dat : in std_logic;
nes2_dat : in std_logic;
nes_lat : out std_logic;
nes_clk : out std_logic;
nes1_data_out: out std_logic_vector(7 downto 0);
nes2_data_out: out std_logic_vector(7 downto 0)
);
end wishbone_nes;
architecture Behavioral of wishbone_nes is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal nes1_data_out_buf: std_logic_vector(7 downto 0);
signal nes2_data_out_buf: std_logic_vector(7 downto 0);
begin
wbs_ack <= read_ack or write_ack;
--WBM-WRITE
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
--sseg_edu_regs <= (others => (others => '0')) ; --RESET REGISTERS HERE
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
--sseg_edu_regs(conv_integer(wbs_address(1 downto 0))) <= wbs_writedata; --WRITE TO REGISTERS HERE
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
--WBM-READ
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= nes2_data_out_buf & nes1_data_out_buf; --MASTER READ FROM REGISTERS HERE
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
nes1: entity work.nes_ctl
port map(
clk => gls_clk,
reset => gls_reset,
nes_dat => nes1_dat,
nes_lat => nes_lat,
nes_clk => nes_clk,
nes_data_out => nes1_data_out_buf
);
nes2: entity work.nes_ctl
port map(
clk => gls_clk,
reset => gls_reset,
nes_dat => nes2_dat,
nes_lat => open,
nes_clk => open,
nes_data_out => nes2_data_out_buf
);
nes1_data_out <= nes1_data_out_buf;
nes2_data_out <= nes2_data_out_buf;
end Behavioral;
|
lgpl-3.0
|
7cf752d6a4bb4bf42b861f8f95858e84
| 0.604104 | 3.412274 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/OZ3_TB.vhd
| 2 | 4,898 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:58 01/01/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Back Up/FPGA/Projects/Current Projects/Systems/OZ-3/OZ3_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: OZ3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY OZ3_TB IS
END OZ3_TB;
ARCHITECTURE behavior OF OZ3_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OZ3
PORT(
clock : IN std_logic;
reset : IN std_logic;
input_pins : IN std_logic_vector(15 downto 0);
input_port : IN std_logic_vector(31 downto 0);
instruction_in : IN std_logic_vector(15 downto 0);
dRAM_data_in : IN std_logic_vector(15 downto 0);
output_pins : OUT std_logic_vector(15 downto 0);
output_port : OUT std_logic_vector(31 downto 0);
instruction_addr_out : OUT std_logic_vector(22 downto 0);
dRAM_data_out : OUT std_logic_vector(15 downto 0);
dRAM_addr_out : OUT std_logic_vector(22 downto 0);
dRAM_WR_out : OUT std_logic;
mem_ctrl_clk_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal input_pins : std_logic_vector(15 downto 0) := (others => '0');
signal input_port : std_logic_vector(31 downto 0) := (others => '0');
signal instruction_in : std_logic_vector(15 downto 0) := (others => '0');
signal dRAM_data_in : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal output_pins : std_logic_vector(15 downto 0);
signal output_port : std_logic_vector(31 downto 0);
signal instruction_addr_out : std_logic_vector(22 downto 0);
signal dRAM_data_out : std_logic_vector(15 downto 0);
signal dRAM_addr_out : std_logic_vector(22 downto 0);
signal dRAM_WR_out : std_logic;
signal mem_ctrl_clk_out : std_logic;
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OZ3 PORT MAP (
clock => clock,
reset => reset,
input_pins => input_pins,
input_port => input_port,
instruction_in => instruction_in,
dRAM_data_in => dRAM_data_in,
output_pins => output_pins,
output_port => output_port,
instruction_addr_out => instruction_addr_out,
dRAM_data_out => dRAM_data_out,
dRAM_addr_out => dRAM_addr_out,
dRAM_WR_out => dRAM_WR_out,
mem_ctrl_clk_out => mem_ctrl_clk_out
);
-- Clock process definitions
clock_process :process
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 200 ns;
reset <= '0';
dRAM_data_in <= x"FFFF";
--Send instruction addi r1, r0, 7FFF
instruction_in <= b"0010000000100000";
wait for 10 ns;
instruction_in <= b"0111111111111111";
--End of instruction addi r1, r0, 7FFF
--Send instruction ldu r1, r0, addr
wait for 10 ns;
instruction_in <= b"0110010000100000";
wait for 10 ns;
instruction_in <= b"0000000111110000";
--End of instruction ldu r1, r0, addr
--Send instruction addi r2, r0, 8001
wait for 10 ns;
instruction_in <= b"0010000001000000";
wait for 10 ns;
instruction_in <= b"1000000000000001";
--End of instruction addi r2, r0, 8001
--Send instruction add r0, r2, r1 (dummy add)
wait for 10 ns;
instruction_in <= b"0011110000000010";
wait for 10 ns;
instruction_in <= b"0000100000000000";
--End of instruction add r0, r2, r1
--Send instruction brnc r0, 31
wait for 10 ns;
instruction_in <= b"1000010000000000";
wait for 10 ns;
instruction_in <= b"0000000000011111";
--End of instruction brnc r0, 31
wait for 10 ns;
instruction_in <= b"0000000000000000";
wait;
end process;
END;
|
mit
|
681a09d8dde03646fb8b3be07bddf677
| 0.594528 | 3.531363 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_uart.vhd
| 2 | 4,699 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_uart is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
baudrate : positive := 115_200
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
tx_out : out std_logic ;
rx_in : in std_logic
);
end wishbone_uart;
architecture Behavioral of wishbone_uart is
component async_serial is
generic(CLK_FREQ : positive := 100_000_000; BAUDRATE : positive := 115_200) ;
port( clk, reset : in std_logic ;
rx : in std_logic ;
tx : out std_logic ;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_ready : out std_logic ;
data_send : in std_logic ;
available : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal rx_register, tx_register : std_logic_vector(7 downto 0);
signal ctrl_register : std_logic_vector(15 downto 0);
signal send_data, data_ready, uart_available : std_logic ;
-- fifo signals
signal fifo_empty, pop_fifo : std_logic ;
signal fifo_out : std_logic_vector(7 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
tx_register <= wbs_writedata(7 downto 0) ;
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
ctrl_register(1 downto 0) <= (others => '0');
elsif rising_edge(gls_clk) then
ctrl_register(0) <= uart_available ;
-- if data_ready = '1' then
-- ctrl_register(1) <= data_ready ;
-- elsif read_ack = '1' and (wbs_strobe = '0' or wbs_cycle = '0' ) then -- reset when read
-- ctrl_register(1) <= '0' ;
-- end if ;
if read_ack = '1' and (wbs_strobe = '0' or wbs_cycle = '0' ) then -- reset when read
pop_fifo <= '1' ;
else
pop_fifo <= '0' ;
end if ;
ctrl_register(1) <= not fifo_empty;
-- wbs_readdata <= ctrl_register(7 downto 0) & rx_register ;
wbs_readdata <= ctrl_register(7 downto 0) & fifo_out ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
send_data <= '1' when write_ack = '1' and wbs_address(0) = '0' and uart_available = '1' else
'0' ;
ctrl_register(15 downto 2) <= (others => '0');
serial_0 : async_serial
generic map(CLK_FREQ => 100_000_000, BAUDRATE => 115_200)
port map( clk => gls_clk, reset => gls_reset ,
rx => rx_in,
tx => tx_out,
data_out => rx_register,
data_in => tx_register,
data_ready => data_ready,
data_send => send_data,
available => uart_available
);
fifo_0 : small_fifo
generic map( WIDTH => 8, DEPTH => 256, THRESHOLD => 4)
port map(clk => gls_clk,
resetn => not gls_reset,
push => data_ready,
pop => pop_fifo,
full => open,
empty => fifo_empty,
limit => open,
data_in => rx_register,
data_out => fifo_out
);
end Behavioral;
|
lgpl-3.0
|
c72cd9d994914d8885a46f1b7d383e2a
| 0.595233 | 3.21409 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altsource_probe/_primary.vhd
| 1 | 2,302 |
library verilog;
use verilog.vl_types.all;
entity altsource_probe is
generic(
lpm_hint : string := "UNUSED";
sld_instance_index: integer := 0;
source_initial_value: string := "0";
sld_ir_width : integer := 4;
probe_width : integer := 1;
source_width : integer := 1;
instance_id : string := "UNUSED";
lpm_type : string := "altsource_probe";
sld_auto_instance_index: string := "YES";
SLD_NODE_INFO : integer := 4746752;
enable_metastability: string := "NO"
);
port(
jtag_state_sdr : in vl_logic;
ir_in : in vl_logic_vector;
jtag_state_cir : in vl_logic;
jtag_state_udr : in vl_logic;
jtag_state_e1dr : in vl_logic;
source_clk : in vl_logic;
probe : in vl_logic_vector;
source : out vl_logic_vector;
ir_out : out vl_logic_vector;
jtag_state_cdr : in vl_logic;
jtag_state_tlr : in vl_logic;
tdi : in vl_logic;
jtag_state_uir : in vl_logic;
source_ena : in vl_logic;
tdo : out vl_logic;
clrn : in vl_logic;
raw_tck : in vl_logic;
usr1 : in vl_logic;
ena : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of sld_instance_index : constant is 1;
attribute mti_svvh_generic_type of source_initial_value : constant is 1;
attribute mti_svvh_generic_type of sld_ir_width : constant is 1;
attribute mti_svvh_generic_type of probe_width : constant is 1;
attribute mti_svvh_generic_type of source_width : constant is 1;
attribute mti_svvh_generic_type of instance_id : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of sld_auto_instance_index : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_INFO : constant is 1;
attribute mti_svvh_generic_type of enable_metastability : constant is 1;
end altsource_probe;
|
bsd-2-clause
|
113ab5810caf26027832115be348b832
| 0.56212 | 3.619497 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/WB.vhd
| 2 | 2,486 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:57:25 10/26/2009
-- Design Name:
-- Module Name: WB - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-- Description: The WB (writeback) stage of the OZ-3 pipeline.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.30 - File written and syntax checked
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity WB is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
data_from_MEM : in STD_LOGIC_VECTOR(31 downto 0);
cntl_from_ID : in STD_LOGIC_VECTOR(5 downto 0);
rfile_write_data_to_ID : out STD_LOGIC_VECTOR(31 downto 0); --These two outputs also used for
rfile_write_addr_to_ID : out STD_LOGIC_VECTOR(4 downto 0); --forwarding logic
rfile_write_e_to_ID : out STD_LOGIC);
end WB;
architecture Behavioral of WB is
--//Component Declarations\\--
component GenReg is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Component Declarations//--
--//Signal Declarations\\--
signal buffer_1_2 : STD_LOGIC_VECTOR(5 downto 0);
signal buffer_2_3 : STD_LOGIC_VECTOR(5 downto 0);
signal buffer_out : STD_LOGIC_VECTOR(5 downto 0);
--\\Signal Declarations//--
begin
in_reg: GenReg generic map (size => 32)
port map (clock, '1', reset, data_from_MEM, rfile_write_data_to_ID);
buf1 : GenReg generic map (size => 6)
port map (clock, '1', reset, cntl_from_ID, buffer_1_2);
buf2 : GenReg generic map (size => 6)
port map (clock, '1', reset, buffer_1_2, buffer_2_3);
buf3 : GenReg generic map (size => 6)
port map (clock, '1', reset, buffer_2_3, buffer_out);
rfile_write_addr_to_ID <= buffer_out(5 downto 1);
rfile_write_e_to_ID <= buffer_out(0);
end Behavioral;
|
mit
|
fd331cf99c8c10cbf05304ee310b36d0
| 0.590909 | 3.391542 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/edge_triggered_latch.vhd
| 2 | 1,756 |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 20:17:12 04/14/2012
-- Design Name:
-- Module Name: generic_latch - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity edge_triggered_latch is
generic(NBIT : positive := 8; POL : std_logic :='1');
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end edge_triggered_latch;
architecture Behavioral of edge_triggered_latch is
signal Qp : std_logic_vector((NBIT - 1) downto 0);
signal old_value : std_logic := '0' ;
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0');
old_value <= '0' ;
elsif clk'event and clk = '1' then
if sraz = '1' then
Qp <= (others => '0');
elsif en /= old_value and en = POL then
Qp <= d ;
end if ;
old_value <= en ;
end if ;
end process ;
q <= Qp;
end Behavioral;
|
lgpl-3.0
|
a7d251227208a96fbb758a21fe141d6e
| 0.556948 | 3.526104 | false | false | false | false |
ricardo-jasinski/vhdl-csv-file-reader
|
hdl/testbench/csv_file_reader_pkg_tb.vhd
| 1 | 3,209 |
use std.env.all;
use std.textio.all;
use work.testbench_utils.all;
use work.csv_file_reader_pkg.all;
-- Testbench for the csv_file_reader_pkg package. Test the package's basic
-- operation by reading data from known test files and checking the values read
-- against their expected values.
entity csv_file_read_pkg_tb is
end;
architecture testbench of csv_file_read_pkg_tb is
procedure read_test_files is
variable csv_file_1: csv_file_reader_type;
variable csv_file_2: csv_file_reader_type;
variable read_string: string(1 to 256);
variable read_integer: integer;
variable read_boolean: boolean;
variable read_real: real;
begin
puts("opening CSV files");
csv_file_1.initialize("c:\intel\projects\fpga\decision_tree_nsl_kdd\vhdl\testbench\data\test_file_1.csv");
csv_file_2.initialize("c:\intel\projects\fpga\decision_tree_nsl_kdd\vhdl\testbench\data\test_file_2.csv");
puts("testing 1st line of the csv file: 1,abc,true,0.5,0110");
csv_file_1.readline;
read_integer := csv_file_1.read_integer;
read_string := csv_file_1.read_string;
read_boolean := csv_file_1.read_boolean;
read_real := csv_file_1.read_real;
assert_that("integer value read is 1", read_integer = 1);
assert_that("string value read is 'abc'", read_string(1 to 3) = "abc");
assert_that("boolean value read is 'true'", read_boolean = true);
assert_that("real value read is 0.5", read_real = 0.5);
assert_that("end of file was not reached", csv_file_1.end_of_file = false);
puts("testing 1st line of the 2nd csv file: 3,def,false,-0.5,0110");
csv_file_2.readline;
read_integer := csv_file_2.read_integer;
read_string := csv_file_2.read_string;
read_boolean := csv_file_2.read_boolean;
read_real := csv_file_2.read_real;
assert_that("integer value read is 3", read_integer = 3);
assert_that("string value read is 'def'", read_string(1 to 3) = "def");
assert_that("boolean value read is 'false'", read_boolean = false);
assert_that("real value read is -0.5", read_real = -0.5);
assert_that("end of file was not reached", csv_file_1.end_of_file = false);
puts("testing 2nd line of the csv file: 2,xyz,false,-1.0,0000");
csv_file_1.readline;
read_integer := csv_file_1.read_integer;
read_string := csv_file_1.read_string;
read_boolean := csv_file_1.read_boolean;
read_real := csv_file_1.read_real;
assert_that("integer value read is 2", read_integer = 2);
assert_that("string value read is 'xyz'", read_string(1 to 3) = "xyz");
assert_that("boolean value read is 'false'", read_boolean = false);
assert_that("real value read is -1.0", read_real = -1.0);
assert_that("end of file was reached", csv_file_1.end_of_file = true);
end;
begin
run_tests: process begin
puts("Starting testbench...");
read_test_files;
puts("End of testbench. All tests passed.");
finish;
end process;
end;
|
unlicense
|
e099c4746b6e1f90dd912e1b5d5de5b6
| 0.619196 | 3.443133 | false | true | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/dps_utim64/_primary.vhd
| 1 | 1,431 |
library verilog;
use verilog.vl_types.all;
entity dps_utim64 is
generic(
L_PARAM_MAIN_STT_IDLE: vl_logic := Hi0;
L_PARAM_MAIN_STT_RD_WAIT: vl_logic := Hi1;
L_PARAM_IRQ_STT_IDLE: vl_logic_vector(0 to 1) := (Hi0, Hi0);
L_PARAM_IRQ_STT_IRQ: vl_logic_vector(0 to 1) := (Hi0, Hi1);
L_PARAM_IRQ_STT_FLAG: vl_logic_vector(0 to 1) := (Hi1, Hi0)
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iTIMER_CLOCK : in vl_logic;
iREQ_VALID : in vl_logic;
oREQ_BUSY : out vl_logic;
iREQ_RW : in vl_logic;
iREQ_ADDR : in vl_logic_vector(4 downto 0);
iREQ_DATA : in vl_logic_vector(31 downto 0);
oREQ_VALID : out vl_logic;
oREQ_DATA : out vl_logic_vector(31 downto 0);
oIRQ_VALID : out vl_logic;
iIRQ_ACK : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of L_PARAM_MAIN_STT_IDLE : constant is 1;
attribute mti_svvh_generic_type of L_PARAM_MAIN_STT_RD_WAIT : constant is 1;
attribute mti_svvh_generic_type of L_PARAM_IRQ_STT_IDLE : constant is 1;
attribute mti_svvh_generic_type of L_PARAM_IRQ_STT_IRQ : constant is 1;
attribute mti_svvh_generic_type of L_PARAM_IRQ_STT_FLAG : constant is 1;
end dps_utim64;
|
bsd-2-clause
|
9dce06539b6ae9048eb6a26fa80b6f9c
| 0.569532 | 3.124454 | false | false | false | false |
diedricm/prMagicTutorial
|
src/upcounter.vhd
| 1 | 609 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity upcounter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rst_val : in STD_LOGIC_VECTOR (15 downto 0);
trigger : out STD_LOGIC);
end upcounter;
architecture Behavioral of upcounter is
signal cnt : unsigned(21 downto 0);
begin
trigger <= '1' when cnt = 0 else '0';
process (clk, rst)
begin
if rst = '1' then
cnt <= unsigned(rst_val);
elsif rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
a03296e25207dec2ec6e84da3e377018
| 0.574713 | 3.713415 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dgen.vhd
| 1 | 4,720 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
gpl-3.0
|
b18fc7f5eaf72cc7be6a0c8fdaed5b7f
| 0.607627 | 4.083045 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl.vhd
| 2 | 15,657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-3.0
|
b2cae0db3f11cf3544ef81b11076f6a8
| 0.525133 | 3.364926 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/cam_deser_4_to_pixels_v2.vhd
| 2 | 7,076 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:09:09 12/17/2014
-- Design Name:
-- Module Name: cam_deser_4_to_pixels - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cam_deser_4_to_pixels_v2 is
generic(INVERT_DATA : boolean := true);
port(
deser_clk, sys_clk : in std_logic ;
sys_reset : in std_logic ;
data_in_deser : in std_logic_vector(3 downto 0);
raw_deser : out std_logic_vector(9 downto 0);
pixel_out_clk, pixel_out_hsync, pixel_out_vsync : out std_logic ;
pixel_out_data : out std_logic_vector(7 downto 0);
synced_out : out std_logic
);
end cam_deser_4_to_pixels_v2;
architecture Behavioral of cam_deser_4_to_pixels_v2 is
type synced_states is (WAIT_SYNC, ACC) ;
type array_3 is array(0 to 2) of std_logic_vector(9 downto 0);
COMPONENT fifo_sync
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal current_state, next_state : synced_states ;
signal data_acc : array_3 ;
signal data_shift_register : std_logic_vector(23 downto 0);
signal sync_phase, sync_mask, old_phase : std_logic_vector(3 downto 0);
signal shift_counter : std_logic_vector(2 downto 0);
signal en_shift, reset_shift : std_logic ;
signal pixel_valid, pixel_valid_long, frame_valid, line_valid : std_logic ;
signal pixel_data : std_logic_vector(7 downto 0);
signal pixel_out_clk_deser_clk, pixel_out_hsync_deser_clk, pixel_out_vsync_deser_clk : std_logic ;
signal pixel_out_data_deser_clk : std_logic_vector(7 downto 0);
signal pixel_out_clk_sync1, pixel_out_hsync_sync1, pixel_out_vsync_sync1 : std_logic ;
signal pixel_out_data_sync1 : std_logic_vector(7 downto 0);
signal raw_deser_data, raw_deser_deser_clk, raw_deser_sync1 : std_logic_vector(9 downto 0) ;
signal sync_pattern : std_logic ;
signal in_sync_0, in_sync_1 : std_logic ;
signal rd_sync, sync_empty, sync_full : std_logic ;
signal sync_out : std_logic_vector(9 downto 0);
begin
with_invert : if INVERT_DATA generate
process(deser_clk, sys_reset)
begin
if sys_reset = '1' then
data_shift_register <= (others => '0') ;
elsif deser_clk'event and deser_clk = '1' then
data_shift_register(data_shift_register'high-4 downto 0) <= data_shift_register(data_shift_register'high downto 4) ;
data_shift_register(data_shift_register'high downto data_shift_register'high-3) <= not data_in_deser ;
end if ;
end process ;
end generate ;
without_invert : if not INVERT_DATA generate
process(deser_clk, sys_reset)
begin
if sys_reset = '1' then
data_shift_register <= (others => '0') ;
elsif deser_clk'event and deser_clk = '1' then
data_shift_register(data_shift_register'high-4 downto 0) <= data_shift_register(data_shift_register'high downto 4) ;
data_shift_register(data_shift_register'high downto data_shift_register'high-3) <= data_in_deser ;
end if ;
end process ;
end generate ;
gen_detect_start_stop : for i in 0 to 3 generate
sync_phase(i) <= '1' when data_shift_register(i+1 downto i) = "10" and data_shift_register(i+12) = '0' else
--'1' when data_shift_register(i+1) = '1' and data_shift_register(i+12) = '0' else
'0' ; -- start bit is a 0 to 1 transition
end generate ;
process(deser_clk, sys_reset)
begin
if sys_reset = '1' then
shift_counter(0) <= '1' ;
shift_counter(shift_counter'high downto 1) <= (others => '0') ;
elsif deser_clk'event and deser_clk = '1' then
if reset_shift = '1' then
shift_counter(0) <= '1' ;
shift_counter(shift_counter'high downto 1) <= (others => '0') ;
elsif en_shift = '1' then
shift_counter(0) <= shift_counter(shift_counter'high) ;
shift_counter(shift_counter'high downto 1) <= shift_counter(shift_counter'high-1 downto 0) ;
end if ;
end if ;
end process ;
sync_mask <= old_phase when (sync_phase and old_phase) /= 0 else
"0001" when sync_phase(0) = '1' else
"0010" when sync_phase(1) = '1' else
"0100" when sync_phase(2) = '1' else
"1000" when sync_phase(3) = '1' else
"0000" ;
process(deser_clk, sys_reset)
begin
if sys_reset = '1' then
old_phase <= (others => '0') ;
elsif deser_clk'event and deser_clk = '1' then
if current_state = WAIT_SYNC and next_state = ACC then
old_phase <= sync_mask ;
end if ;
end if ;
end process ;
en_shift <= '1' when current_state = WAIT_SYNC and sync_phase /=0 else
'1' when current_state = ACC else
'0' ;
reset_shift <= '0' ; --'1' when current_state = WAIT_SYNC and sync_phase = 0 else
--'0' ;
process(deser_clk, sys_reset)
begin
if sys_reset = '1' then
current_state <= WAIT_SYNC ;
elsif deser_clk'event and deser_clk = '1' then
current_state <= next_state ;
end if ;
end process ;
process(current_state, shift_counter, sync_phase)
begin
next_state <= current_state ;
case current_state is
when WAIT_SYNC =>
if sync_phase /= 0 then
next_state <= ACC ;
end if ;
when ACC =>
if shift_counter(2) = '1' then
next_state <= WAIT_SYNC ;
end if ;
when others =>
next_state <= WAIT_SYNC ;
end case ;
end process ;
pixel_valid <= '1' when current_state = WAIT_SYNC and sync_phase /= 0 and sync_full = '0' else
'0' ;
with sync_mask select
raw_deser_data <= data_shift_register(11 downto 2) when "0001",
data_shift_register(12 downto 3) when "0010",
data_shift_register(13 downto 4) when "0100",
data_shift_register(14 downto 5) when "1000",
(others => '0') when others ;
synchronizer_0 : fifo_sync
PORT MAP (
rst => sys_reset,
wr_clk => deser_clk,
rd_clk => sys_clk,
din => raw_deser_data,
wr_en => pixel_valid,
rd_en => rd_sync,
dout => sync_out,
full => sync_full,
empty => sync_empty
);
process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
rd_sync <= '0' ;
elsif sys_clk'event and sys_clk = '1' then
if sync_empty = '0' then
rd_sync <= '1' ;
else
rd_sync <= '0' ;
end if ;
end if ;
end process ;
pixel_out_clk <= not sync_empty ;
pixel_out_hsync <= not sync_out(8) ;
pixel_out_vsync <= not sync_out(9) ;
pixel_out_data <= sync_out(7 downto 0) ;
raw_deser <= sync_out;
synced_out <= '1' when current_state = ACC else
'1' when current_state = WAIT_SYNC and sync_phase /= 0 else
'0' ;
end Behavioral;
|
lgpl-3.0
|
d9049491cc0e10896b2543851a084019
| 0.645562 | 2.973109 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/MEMIO_TB.vhd
| 2 | 4,944 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:12:40 12/10/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/MEMIO_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MEMIO
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY MEMIO_TB IS
END MEMIO_TB;
ARCHITECTURE behavior OF MEMIO_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MEMIO
PORT(
clock : IN std_logic;
reset : IN std_logic;
cntl_from_ID : IN std_logic_vector(20 downto 0);
ALU_result_from_EX : IN std_logic_vector(31 downto 0);
RAM_dest_data_reg : IN std_logic_vector(31 downto 0);
ipin_reg_data : IN std_logic_vector(15 downto 0);
iprt_data : IN std_logic_vector(31 downto 0);
dRAM_data_in : IN std_logic_vector(15 downto 0);
dRAM_data_out : OUT std_logic_vector(15 downto 0);
dRAM_WR : out STD_LOGIC;
dRAM_addr : OUT std_logic_vector(22 downto 0);
result_reg_adr_to_ID : OUT std_logic_vector(4 downto 0);
pflag_to_cond : OUT std_logic;
opin_clk_e : OUT std_logic;
opin_select : OUT std_logic_vector(3 downto 0);
opin_1_0 : OUT std_logic;
oprt_data : OUT std_logic_vector(31 downto 0);
oprt_reg_clk_e : OUT std_logic;
data_reg_addr : OUT std_logic_vector(4 downto 0);
data_to_WB : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal cntl_from_ID : std_logic_vector(20 downto 0) := (others => '0');
signal ALU_result_from_EX : std_logic_vector(31 downto 0) := (others => '0');
signal RAM_dest_data_reg : std_logic_vector(31 downto 0) := (others => '0');
signal ipin_reg_data : std_logic_vector(15 downto 0) := (others => '0');
signal iprt_data : std_logic_vector(31 downto 0) := (others => '0');
signal dRAM_data_in : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal dRAM_data_out : std_logic_vector(15 downto 0);
signal dRAM_WR : std_logic;
signal dRAM_addr : std_logic_vector(22 downto 0);
signal result_reg_adr_to_ID : std_logic_vector(4 downto 0);
signal pflag_to_cond : std_logic;
signal opin_clk_e : std_logic;
signal opin_select : std_logic_vector(3 downto 0);
signal opin_1_0 : std_logic;
signal oprt_data : std_logic_vector(31 downto 0);
signal oprt_reg_clk_e : std_logic;
signal data_reg_addr : std_logic_vector(4 downto 0);
signal data_to_WB : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MEMIO PORT MAP (
clock => clock,
reset => reset,
cntl_from_ID => cntl_from_ID,
ALU_result_from_EX => ALU_result_from_EX,
RAM_dest_data_reg => RAM_dest_data_reg,
ipin_reg_data => ipin_reg_data,
iprt_data => iprt_data,
dRAM_data_in => dRAM_data_in,
dRAM_data_out => dRAM_data_out,
dRAM_WR => dRAM_WR,
dRAM_addr => dRAM_addr,
result_reg_adr_to_ID => result_reg_adr_to_ID,
pflag_to_cond => pflag_to_cond,
opin_clk_e => opin_clk_e,
opin_select => opin_select,
opin_1_0 => opin_1_0,
oprt_data => oprt_data,
oprt_reg_clk_e => oprt_reg_clk_e,
data_reg_addr => data_reg_addr,
data_to_WB => data_to_WB
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
cntl_from_ID <= b"100000001000110000100";
wait for 20 ns;
RAM_dest_data_reg <= x"F000000F";
ALU_result_from_EX <= x"000000F5";
cntl_from_ID <= b"000000000000000000000";
wait;
end process;
END;
|
mit
|
4eef239d61a4a9558e4a61d38eb43f2f
| 0.57322 | 3.397938 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng.vhd
| 1 | 4,004 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
fdcf376b627f186cfca3e5f200518a3f
| 0.641858 | 4.241525 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/dcfifo_fefifo/_primary.vhd
| 1 | 1,041 |
library verilog;
use verilog.vl_types.all;
entity dcfifo_fefifo is
generic(
lpm_widthad : integer := 1;
lpm_numwords : integer := 1;
underflow_checking: string := "ON";
overflow_checking: string := "ON";
lpm_mode : string := "READ"
);
port(
usedw_in : in vl_logic_vector;
wreq : in vl_logic;
rreq : in vl_logic;
clock : in vl_logic;
aclr : in vl_logic;
empty : out vl_logic;
full : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_widthad : constant is 1;
attribute mti_svvh_generic_type of lpm_numwords : constant is 1;
attribute mti_svvh_generic_type of underflow_checking : constant is 1;
attribute mti_svvh_generic_type of overflow_checking : constant is 1;
attribute mti_svvh_generic_type of lpm_mode : constant is 1;
end dcfifo_fefifo;
|
bsd-2-clause
|
0d7d6e4244c0ebcbaa2efc3d7c433b9e
| 0.559078 | 3.898876 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_core.vhd
| 1 | 42,086 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2011-02-21 14:30:23 +0100 (ma, 21 feb 2011) $
-- Revision : $Revision: 800 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--xilinx:
---------
library unisim;
use unisim.vcomponents.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity iserdes_core is
generic(
DATAWIDTH : integer := 10; -- can be 4, 6, 8 or 10 for DDR, can be 2, 3, 4, 5, 6, 7, or 8 for SDR.
DATA_RATE : string := "DDR"; -- DDR/SDR
DIFF_TERM : boolean := TRUE;
USE_FIFO : boolean := FALSE;
USE_BLOCKRAMFIFO : boolean := TRUE;
INVERT_OUTPUT : boolean := FALSE;
INVERSE_BITORDER : boolean := FALSE;
C_FAMILY : string := "virtex6"
);
port(
CLOCK : in std_logic; --system clock, sync to local clock
RESET : in std_logic;
-- Data IO
-- clk src can be internal or external
CLK : in std_logic; -- high speed serial clock, either internal/external source,
CLKb : in std_logic; -- can come from DCM/PLL, IBUF, BUFIO
CLKDIV : in std_logic; -- parallel clock, derived from CLK using DCM/PLL or BUFR
-- can be same as clock/appclock in synchronous systems
-- differential data input -> from outside, necesarry buffer is present in this file
SDATAP : in std_logic;
SDATAN : in std_logic;
--Ctrl IO, all controls should run on CLKDIV/parallelclk
IODELAY_ISERDES_RESET : in std_logic;
-- iodelay control
IODELAY_INC : in std_logic;
IODELAY_CE : in std_logic;
-- iserdes_nodelay control
ISERDES_BITSLIP : in std_logic;
ISERDES_DATAOUT : out std_logic_vector(DATAWIDTH-1 downto 0); --iserdes data, sync to clkdiv. can be used when fifo is not used
-- fifo control
FIFO_RESET : in std_logic;
--write side, sync to clkdiv
FIFO_WREN : in std_logic;
--readside
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector(DATAWIDTH-1 downto 0)
);
attribute S: string;
attribute keep: string;
attribute S of FIFO_EMPTY : signal is "yes";
attribute keep of FIFO_EMPTY : signal is "yes";
end iserdes_core;
architecture rtl of iserdes_core is
component iserdes_fifo_10_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(9 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(9 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END component;
component iserdes_fifo_8_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END component;
component iserdes_fifo_6_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(5 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(5 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END component;
signal SerialIn : std_logic;
signal SerialIoDelayOut : std_logic;
constant zero : std_logic := '0';
constant one : std_logic := '1';
constant zeros : std_logic_vector(31 downto 0) := X"00000000";
signal SHIFT_FROM_SLAVE1 : std_logic;
signal SHIFT_FROM_SLAVE2 : std_logic;
signal SHIFT_TO_SLAVE1 : std_logic;
signal SHIFT_TO_SLAVE2 : std_logic;
signal MASTER_DATA : std_logic_vector(7 downto 0);
signal SLAVE_DATA : std_logic_vector(7 downto 0);
signal ISERDES_DATA : std_logic_vector(DATAWIDTH-1 downto 0);
signal DI : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(15 downto 0);
signal CLKb_inv : std_logic;
signal CLKDIVb_inv : std_logic;
signal FIFO_FULL : std_logic;
attribute S of FIFO_FULL : signal is "yes";
attribute keep of FIFO_FULL : signal is "yes";
begin
CLKb_inv <= not CLKB;
-- differential buffer
IBUFDS_inst : IBUFDS
generic map (
CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only)
DIFF_TERM => DIFF_TERM, -- Differential Termination (Virtex-4/5, Spartan-3E/3A)
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT")
port map (
O => SerialIn , -- Clock buffer output
I => SDATAP , -- Diff_p clock buffer input (connect directly to top-level port)
IB => SDATAN -- Diff_n clock buffer input (connect directly to top-level port)
);
IODELAY_V5_GEN : if (C_FAMILY = "virtex5") generate
-- iodelay
IODELAY_inst : IODELAY
generic map (
DELAY_SRC => "I",
-- Specify which input port to be used
-- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
HIGH_PERFORMANCE_MODE => TRUE,
-- TRUE specifies lower jitter
-- at expense of more power
IDELAY_TYPE => "VARIABLE",
-- "DEFAULT", "FIXED" or "VARIABLE"
IDELAY_VALUE => 0,
-- 0 to 63 tap values
ODELAY_VALUE => 0,
-- 0 to 63 tap values
REFCLK_FREQUENCY => 200.0,
-- Frequency used for IDELAYCTRL
-- 175.0 to 225.0
SIGNAL_PATTERN => "DATA"
-- Input signal type, "CLOCK" or "DATA"
)
port map (
DATAOUT => SerialIoDelayOut , -- 1-bit delayed data output
C => CLKDIV , -- 1-bit clock input
CE => IODELAY_CE , -- 1-bit clock enable input
DATAIN => zero , -- 1-bit internal data input
IDATAIN => SerialIn , -- 1-bit input data input (connect to port)
INC => IODELAY_INC , -- 1-bit increment/decrement input
ODATAIN => zero , -- 1-bit output data input
RST => IODELAY_ISERDES_RESET , -- 1-bit active high, synch reset input
T => one -- 1-bit 3-state control input
);
end generate IODELAY_V5_GEN;
IODELAY_V6_GEN : if (C_FAMILY = "virtex6") generate
-- iodelay
IODELAYE1_inst : IODELAYE1
generic map (
DELAY_SRC => "I",
-- Specify which input port to be used
-- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
HIGH_PERFORMANCE_MODE => TRUE,
-- TRUE specifies lower jitter
-- at expense of more power
IDELAY_TYPE => "VARIABLE",
-- "DEFAULT", "FIXED" or "VARIABLE"
IDELAY_VALUE => 0,
-- 0 to 63 tap values
ODELAY_VALUE => 0,
-- 0 to 63 tap values
REFCLK_FREQUENCY => 200.0,
-- Frequency used for IDELAYCTRL
-- 175.0 to 225.0
SIGNAL_PATTERN => "DATA"
-- Input signal type, "CLOCK" or "DATA"
)
port map (
DATAOUT => SerialIoDelayOut , -- 1-bit delayed data output
C => CLKDIV , -- 1-bit clock input
CE => IODELAY_CE , -- 1-bit clock enable input
DATAIN => zero , -- 1-bit internal data input
IDATAIN => SerialIn , -- 1-bit input data input (connect to port)
INC => IODELAY_INC , -- 1-bit increment/decrement input
ODATAIN => zero , -- 1-bit output data input
RST => IODELAY_ISERDES_RESET , -- 1-bit active high, synch reset input
T => one , -- 1-bit 3-state control input
CINVCTRL => '0' , -- 1-bit input: Dynamic clock inversion input
CLKIN => '0' , -- 1-bit input: Clock delay input
CNTVALUEIN => (others => '0') , -- 5-bit input: Counter value input
CNTVALUEOUT => open -- 5-bit output: Counter value output
);
end generate IODELAY_V6_GEN;
IDELAY_K7_GEN : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
-- iodelay
IDELAYE2_inst : IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- Dynamic clock inversion
DELAY_SRC => "IDATAIN",
-- Specify which input port to be used
-- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
HIGH_PERFORMANCE_MODE => "TRUE",
-- TRUE specifies lower jitter
-- at expense of more power
IDELAY_TYPE => "VARIABLE",
-- "DEFAULT", "FIXED" or "VARIABLE"
IDELAY_VALUE => 0,
-- 0 to 63 tap values
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
-- Frequency used for IDELAYCTRL
-- 175.0 to 225.0
SIGNAL_PATTERN => "DATA"
-- Input signal type, "CLOCK" or "DATA"
)
port map (
CNTVALUEOUT => open,
CINVCTRL => '0',
CNTVALUEIN => (others => '0'),
LD => '0',
LDPIPEEN => '0',
--
DATAOUT => SerialIoDelayOut , -- 1-bit delayed data output
C => CLKDIV , -- 1-bit clock input
CE => IODELAY_CE , -- 1-bit clock enable input
DATAIN => zero , -- 1-bit internal data input
IDATAIN => SerialIn , -- 1-bit input data input (connect to port)
INC => IODELAY_INC , -- 1-bit increment/decrement input
REGRST => IODELAY_ISERDES_RESET -- 1-bit active high, synch reset input
);
end generate IDELAY_K7_GEN;
-- iserdes
-- datawidth
-- can be 4, 6, 8 or 10 for DDR, can be 2, 3, 4, 5, 6, 7, or 8 for SDR.
MASTER_ISERDES_V5_GEN : if (C_FAMILY = "virtex5") generate
Master_iserdes : ISERDES_NODELAY
generic map(
BITSLIP_ENABLE => TRUE ,
DATA_RATE => DATA_RATE ,
DATA_WIDTH => DATAWIDTH ,
INIT_Q1 => '0' ,
INIT_Q2 => '0' ,
INIT_Q3 => '0' ,
INIT_Q4 => '0' ,
INTERFACE_TYPE => "NETWORKING" ,
NUM_CE => 2 ,
SERDES_MODE => "MASTER"
)
port map (
BITSLIP => ISERDES_BITSLIP ,
CE1 => one ,
CE2 => one ,
CLK => CLK ,
CLKB => CLKb_inv ,
CLKDIV => CLKDIV ,
D => SerialIoDelayOut ,
OCLK => zero ,
RST => IODELAY_ISERDES_RESET ,
SHIFTIN1 => zero ,
SHIFTIN2 => zero ,
Q1 => MASTER_DATA(0) ,
Q2 => MASTER_DATA(1) ,
Q3 => MASTER_DATA(2) ,
Q4 => MASTER_DATA(3) ,
Q5 => MASTER_DATA(4) ,
Q6 => MASTER_DATA(5) ,
SHIFTOUT1 => SHIFT_TO_SLAVE1 ,
SHIFTOUT2 => SHIFT_TO_SLAVE2
);
MASTER_DATA(6) <= '0';
MASTER_DATA(7) <= '0';
end generate MASTER_ISERDES_V5_GEN;
MASTER_ISERDES_V6_GEN : if (C_FAMILY = "virtex6") generate
Master_iserdes : ISERDESE1
generic map(
DATA_RATE => DATA_RATE ,
DATA_WIDTH => DATAWIDTH ,
INIT_Q1 => '0' ,
INIT_Q2 => '0' ,
INIT_Q3 => '0' ,
INIT_Q4 => '0' ,
INTERFACE_TYPE => "NETWORKING" ,
NUM_CE => 2 ,
SERDES_MODE => "MASTER" ,
--
DYN_CLKDIV_INV_EN => FALSE , -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => FALSE , -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
IOBDELAY => "IFD" ,
OFB_USED => FALSE ,
SRVAL_Q1 => '0' ,
SRVAL_Q2 => '0' ,
SRVAL_Q3 => '0' ,
SRVAL_Q4 => '0'
)
port map (
BITSLIP => ISERDES_BITSLIP ,
CE1 => one ,
CE2 => one ,
CLK => CLK ,
CLKB => CLKb_inv ,
CLKDIV => CLKDIV ,
DDLY => SerialIoDelayOut , -- 1-bit input: Serial data from IDELAYE2
OCLK => zero ,
RST => IODELAY_ISERDES_RESET ,
SHIFTIN1 => zero ,
SHIFTIN2 => zero ,
Q1 => MASTER_DATA(0) ,
Q2 => MASTER_DATA(1) ,
Q3 => MASTER_DATA(2) ,
Q4 => MASTER_DATA(3) ,
Q5 => MASTER_DATA(4) ,
Q6 => MASTER_DATA(5) ,
SHIFTOUT1 => SHIFT_TO_SLAVE1 ,
SHIFTOUT2 => SHIFT_TO_SLAVE2 ,
--
D => '0',
O => open,
OFB => '0', -- 1-bit input: Data feedback from OSERDESE2
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inv pins to switch clk polarity
DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion
DYNCLKSEL => '0' -- 1-bit input: Dynamic CLK/CLKB inversion
);
MASTER_DATA(6) <= '0';
MASTER_DATA(7) <= '0';
end generate MASTER_ISERDES_V6_GEN;
MASTER_ISERDES_K7_GEN : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
Master_iserdes : ISERDESE2
generic map(
DATA_RATE => DATA_RATE ,
DATA_WIDTH => DATAWIDTH ,
INIT_Q1 => '0' ,
INIT_Q2 => '0' ,
INIT_Q3 => '0' ,
INIT_Q4 => '0' ,
INTERFACE_TYPE => "NETWORKING" ,
NUM_CE => 2 ,
SERDES_MODE => "MASTER" ,
--
DYN_CLKDIV_INV_EN => "FALSE" , -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => "FALSE" , -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
IOBDELAY => "IFD" ,
OFB_USED => "FALSE" ,
SRVAL_Q1 => '0' ,
SRVAL_Q2 => '0' ,
SRVAL_Q3 => '0' ,
SRVAL_Q4 => '0'
)
port map (
BITSLIP => ISERDES_BITSLIP ,
CE1 => one ,
CE2 => one ,
CLK => CLK ,
CLKB => CLKb_inv ,
CLKDIV => CLKDIV ,
DDLY => SerialIoDelayOut , -- 1-bit input: Serial data from IDELAYE2
OCLK => zero ,
RST => IODELAY_ISERDES_RESET ,
SHIFTIN1 => zero ,
SHIFTIN2 => zero ,
Q1 => MASTER_DATA(0) ,
Q2 => MASTER_DATA(1) ,
Q3 => MASTER_DATA(2) ,
Q4 => MASTER_DATA(3) ,
Q5 => MASTER_DATA(4) ,
Q6 => MASTER_DATA(5) ,
Q7 => MASTER_DATA(6) ,
Q8 => MASTER_DATA(7) ,
SHIFTOUT1 => SHIFT_TO_SLAVE1 ,
SHIFTOUT2 => SHIFT_TO_SLAVE2 ,
--
D => '0',
O => open,
CLKDIVP => '0', -- 1-bit input: TBD
OFB => '0', -- 1-bit input: Data feedback from OSERDESE2
OCLKB => '0', -- 1-bit input: High speed negative edge output clock
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inv pins to switch clk polarity
DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion
DYNCLKSEL => '0' -- 1-bit input: Dynamic CLK/CLKB inversion
);
end generate MASTER_ISERDES_K7_GEN;
-- dual serdes modules needed for widths of 8 and 10 in DDR mode, and 7 and 8 in SDR mode
Slave_iserdes_gen: if (DATAWIDTH >6) generate
SLAVE_ISERDES_V5_V6_REORDER : if (C_FAMILY = "virtex5" or C_FAMILY = "virtex6") generate
Normal_Output: if (INVERT_OUTPUT=FALSE) generate
Normal_order: if (INVERSE_BITORDER=FALSE) generate
ISERDES_DATA(5 downto 0) <= MASTER_DATA(5 downto 0);
ISERDES_DATA(DATAWIDTH-1 downto 6) <= SLAVE_DATA(DATAWIDTH-5 downto 2);
end generate;
Inverse_order: if (INVERSE_BITORDER=TRUE) generate
gen_inverse_master: for i in 0 to 5 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= MASTER_DATA(i);
end generate;
gen_inverse_slave: for i in 6 to DATAWIDTH-1 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= SLAVE_DATA(i-4);
end generate;
end generate;
end generate;
Inverse_Output: if (INVERT_OUTPUT=TRUE) generate
Normal_order: if (INVERSE_BITORDER=FALSE) generate
ISERDES_DATA(5 downto 0) <= not MASTER_DATA(5 downto 0);
ISERDES_DATA(DATAWIDTH-1 downto 6) <= not SLAVE_DATA(DATAWIDTH-5 downto 2);
end generate;
Inverse_order: if (INVERSE_BITORDER=TRUE) generate
gen_inverse_master: for i in 0 to 5 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= not MASTER_DATA(i);
end generate;
gen_inverse_slave: for i in 6 to DATAWIDTH-1 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= not SLAVE_DATA(i-4);
end generate;
end generate;
end generate;
end generate SLAVE_ISERDES_V5_V6_REORDER;
SLAVE_ISERDES_K7_REORDER : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
Normal_Output: if (INVERT_OUTPUT=FALSE) generate
Normal_order: if (INVERSE_BITORDER=FALSE) generate
ISERDES_DATA(7 downto 0) <= MASTER_DATA(7 downto 0);
ISERDES_DATA(DATAWIDTH-1 downto 8) <= SLAVE_DATA(DATAWIDTH-7 downto 2);
end generate;
Inverse_order: if (INVERSE_BITORDER=TRUE) generate
gen_inverse_master: for i in 0 to 7 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= MASTER_DATA(i);
end generate;
gen_inverse_slave: for i in 8 to DATAWIDTH-1 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= SLAVE_DATA(i-6);
end generate;
end generate;
end generate;
Inverse_Output: if (INVERT_OUTPUT=TRUE) generate
Normal_order: if (INVERSE_BITORDER=FALSE) generate
ISERDES_DATA(7 downto 0) <= not MASTER_DATA(7 downto 0);
ISERDES_DATA(DATAWIDTH-1 downto 8) <= not SLAVE_DATA(DATAWIDTH-7 downto 2);
end generate;
Inverse_order: if (INVERSE_BITORDER=TRUE) generate
gen_inverse_master: for i in 0 to 7 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= not MASTER_DATA(i);
end generate;
gen_inverse_slave: for i in 8 to DATAWIDTH-1 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= not SLAVE_DATA(i-6);
end generate;
end generate;
end generate;
end generate SLAVE_ISERDES_K7_REORDER;
SLAVE_ISERDES_V5_GEN : if (C_FAMILY = "virtex5") generate
Slave_iserdes : ISERDES_NODELAY
generic map(
BITSLIP_ENABLE => TRUE ,
DATA_RATE => DATA_RATE ,
DATA_WIDTH => DATAWIDTH ,
INIT_Q1 => '0' ,
INIT_Q2 => '0' ,
INIT_Q3 => '0' ,
INIT_Q4 => '0' ,
INTERFACE_TYPE => "NETWORKING" ,
NUM_CE => 2 ,
SERDES_MODE => "SLAVE"
)
port map (
BITSLIP => ISERDES_BITSLIP ,
CE1 => one ,
CE2 => one ,
CLK => CLK ,
CLKB => CLKb_inv ,
CLKDIV => CLKDIV ,
D => zero ,
OCLK => zero ,
RST => IODELAY_ISERDES_RESET ,
SHIFTIN1 => SHIFT_TO_SLAVE1 ,
SHIFTIN2 => SHIFT_TO_SLAVE2 ,
Q1 => SLAVE_DATA(0) ,
Q2 => SLAVE_DATA(1) ,
Q3 => SLAVE_DATA(2) ,
Q4 => SLAVE_DATA(3) ,
Q5 => SLAVE_DATA(4) ,
Q6 => SLAVE_DATA(5) ,
SHIFTOUT1 => SHIFT_FROM_SLAVE1 ,
SHIFTOUT2 => SHIFT_FROM_SLAVE2
);
SLAVE_DATA(6) <= '0';
SLAVE_DATA(7) <= '0';
end generate SLAVE_ISERDES_V5_GEN;
SLAVE_ISERDES_V6_GEN : if (C_FAMILY = "virtex6") generate
Slave_iserdes : ISERDESE1
generic map(
DATA_RATE => DATA_RATE ,
DATA_WIDTH => DATAWIDTH ,
INIT_Q1 => '0' ,
INIT_Q2 => '0' ,
INIT_Q3 => '0' ,
INIT_Q4 => '0' ,
INTERFACE_TYPE => "NETWORKING" ,
NUM_CE => 2 ,
SERDES_MODE => "SLAVE" ,
--
DYN_CLKDIV_INV_EN => FALSE, -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => FALSE, -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
IOBDELAY => "NONE",
OFB_USED => FALSE ,
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
BITSLIP => ISERDES_BITSLIP ,
CE1 => one ,
CE2 => one ,
CLK => CLK ,
CLKB => CLKb_inv ,
CLKDIV => CLKDIV ,
DDLY => zero , -- 1-bit input: Serial data from IDELAYE2
OCLK => zero ,
RST => IODELAY_ISERDES_RESET ,
SHIFTIN1 => SHIFT_TO_SLAVE1 ,
SHIFTIN2 => SHIFT_TO_SLAVE2 ,
Q1 => SLAVE_DATA(0) ,
Q2 => SLAVE_DATA(1) ,
Q3 => SLAVE_DATA(2) ,
Q4 => SLAVE_DATA(3) ,
Q5 => SLAVE_DATA(4) ,
Q6 => SLAVE_DATA(5) ,
SHIFTOUT1 => SHIFT_FROM_SLAVE1 ,
SHIFTOUT2 => SHIFT_FROM_SLAVE2 ,
--
D => '0',
O => open,
OFB => '0', -- 1-bit input: Data feedback from OSERDESE2
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inv pins to switch clk polarity
DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion
DYNCLKSEL => '0' -- 1-bit input: Dynamic CLK/CLKB inversion
);
SLAVE_DATA(6) <= '0';
SLAVE_DATA(7) <= '0';
end generate SLAVE_ISERDES_V6_GEN;
SLAVE_ISERDES_K7_GEN : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
Slave_iserdes : ISERDESE2
generic map(
DATA_RATE => DATA_RATE ,
DATA_WIDTH => DATAWIDTH ,
INIT_Q1 => '0' ,
INIT_Q2 => '0' ,
INIT_Q3 => '0' ,
INIT_Q4 => '0' ,
INTERFACE_TYPE => "NETWORKING" ,
NUM_CE => 2 ,
SERDES_MODE => "SLAVE" ,
--
DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
IOBDELAY => "NONE",
OFB_USED => "FALSE" ,
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
BITSLIP => ISERDES_BITSLIP ,
CE1 => one ,
CE2 => one ,
CLK => CLK ,
CLKB => CLKb_inv ,
CLKDIV => CLKDIV ,
DDLY => zero , -- 1-bit input: Serial data from IDELAYE2
OCLK => zero ,
RST => IODELAY_ISERDES_RESET ,
SHIFTIN1 => SHIFT_TO_SLAVE1 ,
SHIFTIN2 => SHIFT_TO_SLAVE2 ,
Q1 => SLAVE_DATA(0) ,
Q2 => SLAVE_DATA(1) ,
Q3 => SLAVE_DATA(2) ,
Q4 => SLAVE_DATA(3) ,
Q5 => SLAVE_DATA(4) ,
Q6 => SLAVE_DATA(5) ,
Q7 => SLAVE_DATA(6) ,
Q8 => SLAVE_DATA(7) ,
SHIFTOUT1 => SHIFT_FROM_SLAVE1 ,
SHIFTOUT2 => SHIFT_FROM_SLAVE2 ,
--
D => '0',
O => open,
CLKDIVP => '0',
OFB => '0', -- 1-bit input: Data feedback from OSERDESE2
OCLKB => '0', -- 1-bit input: High speed negative edge output clock
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inv pins to switch clk polarity
DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion
DYNCLKSEL => '0' -- 1-bit input: Dynamic CLK/CLKB inversion
);
end generate SLAVE_ISERDES_K7_GEN;
end generate;
Noslave_iserdes_gen: if (DATAWIDTH <= 6) generate
Normal_Output: if (INVERT_OUTPUT=FALSE) generate
Normal_order: if (INVERSE_BITORDER=FALSE) generate
ISERDES_DATA(DATAWIDTH-1 downto 0) <= MASTER_DATA(DATAWIDTH-1 downto 0);
end generate;
Inverse_order: if (INVERSE_BITORDER=TRUE) generate
gen_inverse_master: for i in 0 to DATAWIDTH-1 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= MASTER_DATA(i);
end generate;
end generate;
end generate;
Inverse_Output: if (INVERT_OUTPUT=TRUE) generate
Normal_order: if (INVERSE_BITORDER=FALSE) generate
ISERDES_DATA(DATAWIDTH-1 downto 0) <= not MASTER_DATA(DATAWIDTH-1 downto 0);
end generate;
Inverse_order: if (INVERSE_BITORDER=TRUE) generate
gen_inverse_master: for i in 0 to DATAWIDTH-1 generate
ISERDES_DATA((DATAWIDTH-1)-i) <= not MASTER_DATA(i);
end generate;
end generate;
end generate;
SHIFT_FROM_SLAVE1 <= '0';
SHIFT_FROM_SLAVE2 <= '0';
end generate;
ISERDES_DATAOUT <= ISERDES_DATA;
-- fifo
fifogen: if (USE_FIFO = TRUE) generate
blockramgen: if(USE_BLOCKRAMFIFO = TRUE) generate
FIFO18_inst : FIFO18
generic map (
ALMOST_FULL_OFFSET => X"080" , -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"080" , -- Sets the almost empty threshold
DATA_WIDTH => 18 , -- Sets data width to 4, 9, or 18
DO_REG => 1 , -- Enable output register ( 0 or 1), Must be 1 if the EN_SYN = FALSE
EN_SYN => FALSE , -- Specified FIFO as Asynchronous (FALSE) or
-- Synchronous (TRUE)
FIRST_WORD_FALL_THROUGH => FALSE , -- Sets the FIFO FWFT to TRUE or FALSE
SIM_MODE => "SAFE"
)
-- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation
-- Design Guide" for details
port map (
ALMOSTEMPTY => open , -- 1-bit almost empty output flag
ALMOSTFULL => open , -- 1-bit almost full output flag
DO => DO , -- 16-bit data output
DOP => open , -- 2-bit parity data output
EMPTY => FIFO_EMPTY , -- 1-bit empty output flag
FULL => FIFO_FULL , -- 1-bit full output flag
RDCOUNT => open , -- 12-bit read count output
RDERR => open , -- 1-bit read error output
WRCOUNT => open , -- 12-bit write count output
WRERR => open , -- 1-bit write error
DI => DI , -- 16-bit data input
DIP => zeros(1 downto 0) , -- 2-bit parity input
RDCLK => CLOCK , -- 1-bit read clock input
RDEN => FIFO_RDEN , -- 1-bit read enable input
RST => FIFO_RESET , -- 1-bit reset input
WRCLK => CLKDIV , -- 1-bit write clock input
WREN => FIFO_WREN -- 1-bit write enable input
);
-- End of FIFO18_inst instantiation
DI(15 downto DATAWIDTH) <= (others => '0');
DI(DATAWIDTH-1 downto 0) <= ISERDES_DATA;
FIFO_DATAOUT <= DO(DATAWIDTH-1 downto 0);
end generate;
distramgen: if(USE_BLOCKRAMFIFO = FALSE) generate
gen_10bit_fifo: if DATAWIDTH=10 generate
fifo_10bit: iserdes_fifo_10_bit
port map(
rst => FIFO_RESET , -- 1-bit reset input
wr_clk => CLKDIV , -- 1-bit write clock input
rd_clk => CLOCK , -- 1-bit read clock input
din => DI(9 downto 0) , -- data input
wr_en => FIFO_WREN , -- 1-bit write enable input
rd_en => FIFO_RDEN , -- 1-bit read enable input
dout => FIFO_DATAOUT , -- data output
full => FIFO_FULL ,
empty => FIFO_EMPTY -- 1-bit empty output flag
);
end generate;
gen_8bit_fifo: if DATAWIDTH=8 generate
fifo_8bit: iserdes_fifo_8_bit
port map(
rst => FIFO_RESET , -- 1-bit reset input
wr_clk => CLKDIV , -- 1-bit write clock input
rd_clk => CLOCK , -- 1-bit read clock input
din => DI(7 downto 0) , -- data input
wr_en => FIFO_WREN , -- 1-bit write enable input
rd_en => FIFO_RDEN , -- 1-bit read enable input
dout => FIFO_DATAOUT , -- data output
full => FIFO_FULL ,
empty => FIFO_EMPTY -- 1-bit empty output flag
);
end generate;
gen_6bit_fifo: if DATAWIDTH=6 generate
fifo_6bit: iserdes_fifo_6_bit
port map(
rst => FIFO_RESET , -- 1-bit reset input
wr_clk => CLKDIV , -- 1-bit write clock input
rd_clk => CLOCK , -- 1-bit read clock input
din => DI(5 downto 0) , -- data input
wr_en => FIFO_WREN , -- 1-bit write enable input
rd_en => FIFO_RDEN , -- 1-bit read enable input
dout => FIFO_DATAOUT , -- data output
full => FIFO_FULL ,
empty => FIFO_EMPTY -- 1-bit empty output flag
);
end generate;
DI(15 downto DATAWIDTH) <= (others => '0');
DI(DATAWIDTH-1 downto 0) <= ISERDES_DATA;
end generate;
end generate;
nofifogen: if (USE_FIFO = FALSE) generate
FIFO_DATAOUT <= ISERDES_DATA;
FIFO_EMPTY <= '0';
end generate;
end rtl;
|
gpl-3.0
|
c8605ceee76ebb6fea1870ef59087e3b
| 0.393385 | 4.807082 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/flexible_lvds_tx/_primary.vhd
| 1 | 1,883 |
library verilog;
use verilog.vl_types.all;
entity flexible_lvds_tx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_input: string := "ON";
use_new_coreclk_ckt: string := "FALSE";
outclock_multiply_by: integer := 1;
outclock_duty_cycle: integer := 50;
outclock_divide_by: integer := 1;
use_self_generated_outclock: string := "FALSE";
REGISTER_WIDTH : vl_notype;
DOUBLE_DESER : vl_notype;
LOAD_CNTR_MODULUS: vl_notype
);
port(
tx_in : in vl_logic_vector;
tx_fastclk : in vl_logic;
tx_slowclk : in vl_logic;
tx_regclk : in vl_logic;
tx_locked : in vl_logic;
pll_areset : in vl_logic;
pll_outclock : in vl_logic;
tx_out : out vl_logic_vector;
tx_outclock : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of registered_input : constant is 1;
attribute mti_svvh_generic_type of use_new_coreclk_ckt : constant is 1;
attribute mti_svvh_generic_type of outclock_multiply_by : constant is 1;
attribute mti_svvh_generic_type of outclock_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of outclock_divide_by : constant is 1;
attribute mti_svvh_generic_type of use_self_generated_outclock : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of DOUBLE_DESER : constant is 3;
attribute mti_svvh_generic_type of LOAD_CNTR_MODULUS : constant is 3;
end flexible_lvds_tx;
|
bsd-2-clause
|
cfac5d8a505fc419c6d972e9c59de59e
| 0.629315 | 3.721344 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_tb.vhd
| 1 | 6,208 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 78
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-3.0
|
78c670528b29079f3a9abc71f861d4f7
| 0.626772 | 4.012928 | false | false | false | false |
CprE488/Final
|
system/hdl/system.vhd
| 1 | 155,406 |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
SWs_8Bits_TRI_IO : inout std_logic_vector(7 downto 0);
LEDs_8Bits_TRI_IO : out std_logic_vector(7 downto 0);
BTNs_5Bits_TRI_IO : inout std_logic_vector(4 downto 0);
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : in std_logic;
processing_system7_0_PS_CLK : in std_logic;
processing_system7_0_PS_PORB : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
fmc_imageon_iic_0_Sda_pin : inout std_logic;
fmc_imageon_iic_0_Scl_pin : inout std_logic;
fmc_imageon_hdmi_out_0_io_hdmio_spdif_pin : out std_logic;
fmc_imageon_hdmi_out_0_io_hdmio_video_pin : out std_logic_vector(15 downto 0);
fmc_imageon_hdmi_out_0_io_hdmio_clk_pin : out std_logic;
fmc_imageon_hdmi_in_0_io_hdmii_spdif_pin : in std_logic;
fmc_imageon_hdmi_in_0_io_hdmii_video_pin : in std_logic_vector(15 downto 0);
fmc_imageon_hdmi_in_0_clk_pin : in std_logic;
fmc_imageon_video_clk1_pin : in std_logic;
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic;
led8 : out std_logic;
led9 : out std_logic;
led10 : out std_logic;
led11 : out std_logic;
led12 : out std_logic;
led13 : out std_logic;
led14 : out std_logic;
led15 : out std_logic;
led16 : out std_logic;
led17 : out std_logic;
led18 : out std_logic;
led19 : out std_logic;
led20 : out std_logic;
led21 : out std_logic;
led22 : out std_logic;
led23 : out std_logic;
led24 : out std_logic;
led25 : out std_logic;
led26 : out std_logic;
led27 : out std_logic;
led28 : out std_logic;
led29 : out std_logic;
fmc_imageon_iic_0_Reset_pin : out std_logic
);
end system;
architecture STRUCTURE of system is
component system_axi4lite_0_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(7 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(7 downto 0);
M_AXI_AWID : out std_logic_vector(95 downto 0);
M_AXI_AWADDR : out std_logic_vector(255 downto 0);
M_AXI_AWLEN : out std_logic_vector(63 downto 0);
M_AXI_AWSIZE : out std_logic_vector(23 downto 0);
M_AXI_AWBURST : out std_logic_vector(15 downto 0);
M_AXI_AWLOCK : out std_logic_vector(15 downto 0);
M_AXI_AWCACHE : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(23 downto 0);
M_AXI_AWREGION : out std_logic_vector(31 downto 0);
M_AXI_AWQOS : out std_logic_vector(31 downto 0);
M_AXI_AWUSER : out std_logic_vector(7 downto 0);
M_AXI_AWVALID : out std_logic_vector(7 downto 0);
M_AXI_AWREADY : in std_logic_vector(7 downto 0);
M_AXI_WID : out std_logic_vector(95 downto 0);
M_AXI_WDATA : out std_logic_vector(255 downto 0);
M_AXI_WSTRB : out std_logic_vector(31 downto 0);
M_AXI_WLAST : out std_logic_vector(7 downto 0);
M_AXI_WUSER : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic_vector(7 downto 0);
M_AXI_WREADY : in std_logic_vector(7 downto 0);
M_AXI_BID : in std_logic_vector(95 downto 0);
M_AXI_BRESP : in std_logic_vector(15 downto 0);
M_AXI_BUSER : in std_logic_vector(7 downto 0);
M_AXI_BVALID : in std_logic_vector(7 downto 0);
M_AXI_BREADY : out std_logic_vector(7 downto 0);
M_AXI_ARID : out std_logic_vector(95 downto 0);
M_AXI_ARADDR : out std_logic_vector(255 downto 0);
M_AXI_ARLEN : out std_logic_vector(63 downto 0);
M_AXI_ARSIZE : out std_logic_vector(23 downto 0);
M_AXI_ARBURST : out std_logic_vector(15 downto 0);
M_AXI_ARLOCK : out std_logic_vector(15 downto 0);
M_AXI_ARCACHE : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(23 downto 0);
M_AXI_ARREGION : out std_logic_vector(31 downto 0);
M_AXI_ARQOS : out std_logic_vector(31 downto 0);
M_AXI_ARUSER : out std_logic_vector(7 downto 0);
M_AXI_ARVALID : out std_logic_vector(7 downto 0);
M_AXI_ARREADY : in std_logic_vector(7 downto 0);
M_AXI_RID : in std_logic_vector(95 downto 0);
M_AXI_RDATA : in std_logic_vector(255 downto 0);
M_AXI_RRESP : in std_logic_vector(15 downto 0);
M_AXI_RLAST : in std_logic_vector(7 downto 0);
M_AXI_RUSER : in std_logic_vector(7 downto 0);
M_AXI_RVALID : in std_logic_vector(7 downto 0);
M_AXI_RREADY : out std_logic_vector(7 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_leds_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_btns_5bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(4 downto 0);
GPIO_IO_O : out std_logic_vector(4 downto 0);
GPIO_IO_T : out std_logic_vector(4 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(0 to 0);
S_AXI_HP0_RID : out std_logic_vector(0 to 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(0 to 0);
S_AXI_HP0_AWID : in std_logic_vector(0 to 0);
S_AXI_HP0_WID : in std_logic_vector(0 to 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(0 to 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_fmc_imageon_iic_0_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to 0)
);
end component;
component system_fmc_imageon_hdmi_out_0_wrapper is
port (
clk : in std_logic;
reset : in std_logic;
oe : in std_logic;
embed_syncs : in std_logic;
audio_spdif : in std_logic;
xsvi_vblank_i : in std_logic;
xsvi_hblank_i : in std_logic;
xsvi_active_video_i : in std_logic;
xsvi_video_data_i : in std_logic_vector(15 downto 0);
io_hdmio_spdif : out std_logic;
io_hdmio_video : out std_logic_vector(15 downto 0);
io_hdmio_clk : out std_logic;
debug_o : out std_logic_vector(39 downto 0)
);
end component;
component system_v_vid_in_axi4s_0_wrapper is
port (
vid_in_clk : in std_logic;
rst : in std_logic;
vid_de : in std_logic;
vid_vblank : in std_logic;
vid_hblank : in std_logic;
vid_vsync : in std_logic;
vid_hsync : in std_logic;
vid_data : in std_logic_vector(15 downto 0);
aclk : in std_logic;
aresetn : in std_logic;
aclken : in std_logic;
m_axis_video_tdata : out std_logic_vector(15 downto 0);
m_axis_video_tvalid : out std_logic;
m_axis_video_tready : in std_logic;
m_axis_video_tuser : out std_logic;
m_axis_video_tlast : out std_logic;
vtd_active_video : out std_logic;
vtd_vblank : out std_logic;
vtd_hblank : out std_logic;
vtd_vsync : out std_logic;
vtd_hsync : out std_logic;
wr_error : out std_logic;
empty : out std_logic;
axis_enable : in std_logic
);
end component;
component system_v_axi4s_vid_out_0_wrapper is
port (
aclk : in std_logic;
rst : in std_logic;
aresetn : in std_logic;
aclken : in std_logic;
s_axis_video_tdata : in std_logic_vector(15 downto 0);
s_axis_video_tvalid : in std_logic;
s_axis_video_tready : out std_logic;
s_axis_video_tuser : in std_logic;
s_axis_video_tlast : in std_logic;
video_out_clk : in std_logic;
video_de : out std_logic;
video_vsync : out std_logic;
video_hsync : out std_logic;
video_vblank : out std_logic;
video_hblank : out std_logic;
video_data : out std_logic_vector(15 downto 0);
vtg_vsync : in std_logic;
vtg_hsync : in std_logic;
vtg_vblank : in std_logic;
vtg_hblank : in std_logic;
vtg_act_vid : in std_logic;
vtg_ce : out std_logic;
vtg_fsync : out std_logic;
locked : out std_logic;
wr_error : out std_logic;
empty : out std_logic
);
end component;
component system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(15 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(63 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(7 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(15 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(1 downto 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(1 downto 0);
S_AXI_AWID : in std_logic_vector(1 downto 0);
S_AXI_AWADDR : in std_logic_vector(63 downto 0);
S_AXI_AWLEN : in std_logic_vector(15 downto 0);
S_AXI_AWSIZE : in std_logic_vector(5 downto 0);
S_AXI_AWBURST : in std_logic_vector(3 downto 0);
S_AXI_AWLOCK : in std_logic_vector(3 downto 0);
S_AXI_AWCACHE : in std_logic_vector(7 downto 0);
S_AXI_AWPROT : in std_logic_vector(5 downto 0);
S_AXI_AWQOS : in std_logic_vector(7 downto 0);
S_AXI_AWUSER : in std_logic_vector(1 downto 0);
S_AXI_AWVALID : in std_logic_vector(1 downto 0);
S_AXI_AWREADY : out std_logic_vector(1 downto 0);
S_AXI_WID : in std_logic_vector(1 downto 0);
S_AXI_WDATA : in std_logic_vector(127 downto 0);
S_AXI_WSTRB : in std_logic_vector(15 downto 0);
S_AXI_WLAST : in std_logic_vector(1 downto 0);
S_AXI_WUSER : in std_logic_vector(1 downto 0);
S_AXI_WVALID : in std_logic_vector(1 downto 0);
S_AXI_WREADY : out std_logic_vector(1 downto 0);
S_AXI_BID : out std_logic_vector(1 downto 0);
S_AXI_BRESP : out std_logic_vector(3 downto 0);
S_AXI_BUSER : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic_vector(1 downto 0);
S_AXI_BREADY : in std_logic_vector(1 downto 0);
S_AXI_ARID : in std_logic_vector(1 downto 0);
S_AXI_ARADDR : in std_logic_vector(63 downto 0);
S_AXI_ARLEN : in std_logic_vector(15 downto 0);
S_AXI_ARSIZE : in std_logic_vector(5 downto 0);
S_AXI_ARBURST : in std_logic_vector(3 downto 0);
S_AXI_ARLOCK : in std_logic_vector(3 downto 0);
S_AXI_ARCACHE : in std_logic_vector(7 downto 0);
S_AXI_ARPROT : in std_logic_vector(5 downto 0);
S_AXI_ARQOS : in std_logic_vector(7 downto 0);
S_AXI_ARUSER : in std_logic_vector(1 downto 0);
S_AXI_ARVALID : in std_logic_vector(1 downto 0);
S_AXI_ARREADY : out std_logic_vector(1 downto 0);
S_AXI_RID : out std_logic_vector(1 downto 0);
S_AXI_RDATA : out std_logic_vector(127 downto 0);
S_AXI_RRESP : out std_logic_vector(3 downto 0);
S_AXI_RLAST : out std_logic_vector(1 downto 0);
S_AXI_RUSER : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic_vector(1 downto 0);
S_AXI_RREADY : in std_logic_vector(1 downto 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(0 to 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(0 to 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(0 to 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(0 to 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(0 to 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(0 to 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(0 to 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component system_led_pwm_0_wrapper is
port (
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic;
led8 : out std_logic;
led9 : out std_logic;
led10 : out std_logic;
led11 : out std_logic;
led12 : out std_logic;
led13 : out std_logic;
led14 : out std_logic;
led15 : out std_logic;
led16 : out std_logic;
led17 : out std_logic;
led18 : out std_logic;
led19 : out std_logic;
led20 : out std_logic;
led21 : out std_logic;
led22 : out std_logic;
led23 : out std_logic;
led24 : out std_logic;
led25 : out std_logic;
led26 : out std_logic;
led27 : out std_logic;
led28 : out std_logic;
led29 : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end component;
component system_fmc_imageon_hdmi_in_0_wrapper is
port (
clk : in std_logic;
io_hdmii_spdif : in std_logic;
io_hdmii_video : in std_logic_vector(15 downto 0);
video_vblank : out std_logic;
video_hblank : out std_logic;
video_de : out std_logic;
video_data : out std_logic_vector(15 downto 0);
audio_spdif : out std_logic;
debug_o : out std_logic_vector(23 downto 0)
);
end component;
component system_v_tc_vid_in_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
end component;
component system_v_tc_vid_out_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal BTNs_5Bits_TRI_IO_I : std_logic_vector(4 downto 0);
signal BTNs_5Bits_TRI_IO_O : std_logic_vector(4 downto 0);
signal BTNs_5Bits_TRI_IO_T : std_logic_vector(4 downto 0);
signal SWs_8Bits_TRI_IO_I : std_logic_vector(7 downto 0);
signal SWs_8Bits_TRI_IO_O : std_logic_vector(7 downto 0);
signal SWs_8Bits_TRI_IO_T : std_logic_vector(7 downto 0);
signal axi4lite_0_M_ARADDR : std_logic_vector(255 downto 0);
signal axi4lite_0_M_ARESETN : std_logic_vector(7 downto 0);
signal axi4lite_0_M_ARREADY : std_logic_vector(7 downto 0);
signal axi4lite_0_M_ARVALID : std_logic_vector(7 downto 0);
signal axi4lite_0_M_AWADDR : std_logic_vector(255 downto 0);
signal axi4lite_0_M_AWREADY : std_logic_vector(7 downto 0);
signal axi4lite_0_M_AWVALID : std_logic_vector(7 downto 0);
signal axi4lite_0_M_BREADY : std_logic_vector(7 downto 0);
signal axi4lite_0_M_BRESP : std_logic_vector(15 downto 0);
signal axi4lite_0_M_BVALID : std_logic_vector(7 downto 0);
signal axi4lite_0_M_RDATA : std_logic_vector(255 downto 0);
signal axi4lite_0_M_RREADY : std_logic_vector(7 downto 0);
signal axi4lite_0_M_RRESP : std_logic_vector(15 downto 0);
signal axi4lite_0_M_RVALID : std_logic_vector(7 downto 0);
signal axi4lite_0_M_WDATA : std_logic_vector(255 downto 0);
signal axi4lite_0_M_WREADY : std_logic_vector(7 downto 0);
signal axi4lite_0_M_WSTRB : std_logic_vector(31 downto 0);
signal axi4lite_0_M_WVALID : std_logic_vector(7 downto 0);
signal axi4lite_0_S_ARADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_ARBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_ARLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_AWBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_AWLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_BID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_BREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_BRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_BVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_RDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_RID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_RLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_RREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_RRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_RVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_WDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_WID : std_logic_vector(11 downto 0);
signal axi4lite_0_S_WLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_WREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_WSTRB : std_logic_vector(3 downto 0);
signal axi4lite_0_S_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WID : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(5 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(127 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(127 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(15 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(1 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tdata : std_logic_vector(15 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tlast : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tready : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tuser : std_logic_vector(0 to 0);
signal axi_vdma_0_M_AXIS_MM2S_tvalid : std_logic;
signal fmc_imageon_hdmi_in_0_video_data : std_logic_vector(15 downto 0);
signal fmc_imageon_hdmi_in_0_video_de : std_logic;
signal fmc_imageon_hdmi_in_0_video_hblank : std_logic;
signal fmc_imageon_hdmi_in_0_video_vblank : std_logic;
signal fmc_imageon_hdmi_out_0_io_hdmio_clk : std_logic;
signal fmc_imageon_hdmi_out_0_io_hdmio_spdif : std_logic;
signal fmc_imageon_hdmi_out_0_io_hdmio_video : std_logic_vector(15 downto 0);
signal fmc_imageon_iic_0_Gpo : std_logic_vector(0 to 0);
signal fmc_imageon_iic_0_Scl_I : std_logic;
signal fmc_imageon_iic_0_Scl_O : std_logic;
signal fmc_imageon_iic_0_Scl_T : std_logic;
signal fmc_imageon_iic_0_Sda_I : std_logic;
signal fmc_imageon_iic_0_Sda_O : std_logic;
signal fmc_imageon_iic_0_Sda_T : std_logic;
signal fmc_imageon_video_clk1 : std_logic;
signal led_pwm_0_led0 : std_logic;
signal led_pwm_0_led1 : std_logic;
signal led_pwm_0_led2 : std_logic;
signal led_pwm_0_led3 : std_logic;
signal led_pwm_0_led4 : std_logic;
signal led_pwm_0_led5 : std_logic;
signal led_pwm_0_led6 : std_logic;
signal led_pwm_0_led7 : std_logic;
signal led_pwm_0_led8 : std_logic;
signal led_pwm_0_led9 : std_logic;
signal led_pwm_0_led10 : std_logic;
signal led_pwm_0_led11 : std_logic;
signal led_pwm_0_led12 : std_logic;
signal led_pwm_0_led13 : std_logic;
signal led_pwm_0_led14 : std_logic;
signal led_pwm_0_led15 : std_logic;
signal led_pwm_0_led16 : std_logic;
signal led_pwm_0_led17 : std_logic;
signal led_pwm_0_led18 : std_logic;
signal led_pwm_0_led19 : std_logic;
signal led_pwm_0_led20 : std_logic;
signal led_pwm_0_led21 : std_logic;
signal led_pwm_0_led22 : std_logic;
signal led_pwm_0_led23 : std_logic;
signal led_pwm_0_led24 : std_logic;
signal led_pwm_0_led25 : std_logic;
signal led_pwm_0_led26 : std_logic;
signal led_pwm_0_led27 : std_logic;
signal led_pwm_0_led28 : std_logic;
signal led_pwm_0_led29 : std_logic;
signal net_fmc_imageon_hdmi_in_0_clk_pin : std_logic;
signal net_fmc_imageon_hdmi_in_0_io_hdmii_spdif_pin : std_logic;
signal net_fmc_imageon_hdmi_in_0_io_hdmii_video_pin : std_logic_vector(15 downto 0);
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_gnd96 : std_logic_vector(95 downto 0);
signal net_vcc0 : std_logic;
signal net_vcc2 : std_logic_vector(1 downto 0);
signal pgassign1 : std_logic_vector(7 downto 0);
signal pgassign2 : std_logic_vector(1 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_CLK1 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N_0 : std_logic;
signal v_axi4s_vid_out_0_video_data : std_logic_vector(15 downto 0);
signal v_axi4s_vid_out_0_video_de : std_logic;
signal v_axi4s_vid_out_0_video_hblank : std_logic;
signal v_axi4s_vid_out_0_video_vblank : std_logic;
signal v_axi4s_vid_out_0_vtg_ce : std_logic;
signal v_tc_vid_out_0_VTIMING_OUT_active_video : std_logic;
signal v_tc_vid_out_0_VTIMING_OUT_hblank : std_logic;
signal v_tc_vid_out_0_VTIMING_OUT_hsync : std_logic;
signal v_tc_vid_out_0_VTIMING_OUT_vblank : std_logic;
signal v_tc_vid_out_0_VTIMING_OUT_vsync : std_logic;
signal v_vid_in_axi4s_0_M_AXIS_VIDEO_tdata : std_logic_vector(15 downto 0);
signal v_vid_in_axi4s_0_M_AXIS_VIDEO_tlast : std_logic;
signal v_vid_in_axi4s_0_M_AXIS_VIDEO_tready : std_logic;
signal v_vid_in_axi4s_0_M_AXIS_VIDEO_tuser : std_logic_vector(0 to 0);
signal v_vid_in_axi4s_0_M_AXIS_VIDEO_tvalid : std_logic;
signal v_vid_in_axi4s_0_VTIMING_OUT_active_video : std_logic;
signal v_vid_in_axi4s_0_VTIMING_OUT_hblank : std_logic;
signal v_vid_in_axi4s_0_VTIMING_OUT_hsync : std_logic;
signal v_vid_in_axi4s_0_VTIMING_OUT_vblank : std_logic;
signal v_vid_in_axi4s_0_VTIMING_OUT_vsync : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_axi4lite_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_sws_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_leds_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_btns_5bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_fmc_imageon_iic_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_fmc_imageon_hdmi_out_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_v_vid_in_axi4s_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_v_axi4s_vid_out_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_vdma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_led_pwm_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_fmc_imageon_hdmi_in_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_v_tc_vid_in_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_v_tc_vid_out_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
fmc_imageon_hdmi_out_0_io_hdmio_spdif_pin <= fmc_imageon_hdmi_out_0_io_hdmio_spdif;
fmc_imageon_hdmi_out_0_io_hdmio_video_pin <= fmc_imageon_hdmi_out_0_io_hdmio_video;
fmc_imageon_hdmi_out_0_io_hdmio_clk_pin <= fmc_imageon_hdmi_out_0_io_hdmio_clk;
net_fmc_imageon_hdmi_in_0_io_hdmii_spdif_pin <= fmc_imageon_hdmi_in_0_io_hdmii_spdif_pin;
net_fmc_imageon_hdmi_in_0_io_hdmii_video_pin <= fmc_imageon_hdmi_in_0_io_hdmii_video_pin;
net_fmc_imageon_hdmi_in_0_clk_pin <= fmc_imageon_hdmi_in_0_clk_pin;
fmc_imageon_video_clk1 <= fmc_imageon_video_clk1_pin;
led0 <= led_pwm_0_led0;
led1 <= led_pwm_0_led1;
led2 <= led_pwm_0_led2;
led3 <= led_pwm_0_led3;
led4 <= led_pwm_0_led4;
led5 <= led_pwm_0_led5;
led6 <= led_pwm_0_led6;
led7 <= led_pwm_0_led7;
led8 <= led_pwm_0_led8;
led9 <= led_pwm_0_led9;
led10 <= led_pwm_0_led10;
led11 <= led_pwm_0_led11;
led12 <= led_pwm_0_led12;
led13 <= led_pwm_0_led13;
led14 <= led_pwm_0_led14;
led15 <= led_pwm_0_led15;
led16 <= led_pwm_0_led16;
led17 <= led_pwm_0_led17;
led18 <= led_pwm_0_led18;
led19 <= led_pwm_0_led19;
led20 <= led_pwm_0_led20;
led21 <= led_pwm_0_led21;
led22 <= led_pwm_0_led22;
led23 <= led_pwm_0_led23;
led24 <= led_pwm_0_led24;
led25 <= led_pwm_0_led25;
led26 <= led_pwm_0_led26;
led27 <= led_pwm_0_led27;
led28 <= led_pwm_0_led28;
led29 <= led_pwm_0_led29;
fmc_imageon_iic_0_Reset_pin <= fmc_imageon_iic_0_Gpo(0);
axi_interconnect_1_S_ARADDR(63 downto 32) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_ARLEN(15 downto 8) <= B"00000000";
axi_interconnect_1_S_ARSIZE(5 downto 3) <= B"000";
axi_interconnect_1_S_ARBURST(3 downto 2) <= B"00";
axi_interconnect_1_S_ARPROT(5 downto 3) <= B"000";
axi_interconnect_1_S_ARCACHE(7 downto 4) <= B"0000";
axi_interconnect_1_S_ARVALID(1 downto 1) <= B"0";
axi_interconnect_1_S_RREADY(1 downto 1) <= B"0";
axi_interconnect_1_S_AWADDR(31 downto 0) <= B"00000000000000000000000000000000";
axi_interconnect_1_S_AWLEN(7 downto 0) <= B"00000000";
axi_interconnect_1_S_AWSIZE(2 downto 0) <= B"000";
axi_interconnect_1_S_AWBURST(1 downto 0) <= B"00";
axi_interconnect_1_S_AWPROT(2 downto 0) <= B"000";
axi_interconnect_1_S_AWCACHE(3 downto 0) <= B"0000";
axi_interconnect_1_S_AWVALID(0 downto 0) <= B"0";
axi_interconnect_1_S_WDATA(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
axi_interconnect_1_S_WSTRB(7 downto 0) <= B"00000000";
axi_interconnect_1_S_WLAST(0 downto 0) <= B"0";
axi_interconnect_1_S_WVALID(0 downto 0) <= B"0";
axi_interconnect_1_S_BREADY(0 downto 0) <= B"0";
pgassign1(7 downto 7) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(6 downto 6) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(5 downto 5) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(4 downto 4) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(3 downto 3) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(2 downto 2) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign1(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign2(1 downto 1) <= processing_system7_0_FCLK_CLK1(0 to 0);
pgassign2(0 downto 0) <= processing_system7_0_FCLK_CLK1(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_gnd96(95 downto 0) <= B"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
net_vcc0 <= '1';
net_vcc2(1 downto 0) <= B"11";
axi4lite_0 : system_axi4lite_0_wrapper
port map (
INTERCONNECT_ACLK => pgassign1(7),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N_0,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi4lite_0_M_ARESETN,
IRQ => open,
S_AXI_ACLK => pgassign1(7 downto 7),
S_AXI_AWID => axi4lite_0_S_AWID,
S_AXI_AWADDR => axi4lite_0_S_AWADDR,
S_AXI_AWLEN => axi4lite_0_S_AWLEN,
S_AXI_AWSIZE => axi4lite_0_S_AWSIZE,
S_AXI_AWBURST => axi4lite_0_S_AWBURST,
S_AXI_AWLOCK => axi4lite_0_S_AWLOCK,
S_AXI_AWCACHE => axi4lite_0_S_AWCACHE,
S_AXI_AWPROT => axi4lite_0_S_AWPROT,
S_AXI_AWQOS => axi4lite_0_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi4lite_0_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi4lite_0_S_AWREADY(0 to 0),
S_AXI_WID => axi4lite_0_S_WID,
S_AXI_WDATA => axi4lite_0_S_WDATA,
S_AXI_WSTRB => axi4lite_0_S_WSTRB,
S_AXI_WLAST => axi4lite_0_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi4lite_0_S_WVALID(0 to 0),
S_AXI_WREADY => axi4lite_0_S_WREADY(0 to 0),
S_AXI_BID => axi4lite_0_S_BID,
S_AXI_BRESP => axi4lite_0_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi4lite_0_S_BVALID(0 to 0),
S_AXI_BREADY => axi4lite_0_S_BREADY(0 to 0),
S_AXI_ARID => axi4lite_0_S_ARID,
S_AXI_ARADDR => axi4lite_0_S_ARADDR,
S_AXI_ARLEN => axi4lite_0_S_ARLEN,
S_AXI_ARSIZE => axi4lite_0_S_ARSIZE,
S_AXI_ARBURST => axi4lite_0_S_ARBURST,
S_AXI_ARLOCK => axi4lite_0_S_ARLOCK,
S_AXI_ARCACHE => axi4lite_0_S_ARCACHE,
S_AXI_ARPROT => axi4lite_0_S_ARPROT,
S_AXI_ARQOS => axi4lite_0_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi4lite_0_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi4lite_0_S_ARREADY(0 to 0),
S_AXI_RID => axi4lite_0_S_RID,
S_AXI_RDATA => axi4lite_0_S_RDATA,
S_AXI_RRESP => axi4lite_0_S_RRESP,
S_AXI_RLAST => axi4lite_0_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi4lite_0_S_RVALID(0 to 0),
S_AXI_RREADY => axi4lite_0_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign1,
M_AXI_AWID => open,
M_AXI_AWADDR => axi4lite_0_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi4lite_0_M_AWVALID,
M_AXI_AWREADY => axi4lite_0_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi4lite_0_M_WDATA,
M_AXI_WSTRB => axi4lite_0_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi4lite_0_M_WVALID,
M_AXI_WREADY => axi4lite_0_M_WREADY,
M_AXI_BID => net_gnd96,
M_AXI_BRESP => axi4lite_0_M_BRESP,
M_AXI_BUSER => net_gnd8,
M_AXI_BVALID => axi4lite_0_M_BVALID,
M_AXI_BREADY => axi4lite_0_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi4lite_0_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi4lite_0_M_ARVALID,
M_AXI_ARREADY => axi4lite_0_M_ARREADY,
M_AXI_RID => net_gnd96,
M_AXI_RDATA => axi4lite_0_M_RDATA,
M_AXI_RRESP => axi4lite_0_M_RRESP,
M_AXI_RLAST => net_gnd8,
M_AXI_RUSER => net_gnd8,
M_AXI_RVALID => axi4lite_0_M_RVALID,
M_AXI_RREADY => axi4lite_0_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
SWs_8Bits : system_sws_8bits_wrapper
port map (
S_AXI_ACLK => pgassign1(7),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(0),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(8 downto 0),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(0),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(0),
S_AXI_WDATA => axi4lite_0_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi4lite_0_M_WVALID(0),
S_AXI_WREADY => axi4lite_0_M_WREADY(0),
S_AXI_BRESP => axi4lite_0_M_BRESP(1 downto 0),
S_AXI_BVALID => axi4lite_0_M_BVALID(0),
S_AXI_BREADY => axi4lite_0_M_BREADY(0),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(8 downto 0),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(0),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(0),
S_AXI_RDATA => axi4lite_0_M_RDATA(31 downto 0),
S_AXI_RRESP => axi4lite_0_M_RRESP(1 downto 0),
S_AXI_RVALID => axi4lite_0_M_RVALID(0),
S_AXI_RREADY => axi4lite_0_M_RREADY(0),
IP2INTC_Irpt => open,
GPIO_IO_I => SWs_8Bits_TRI_IO_I,
GPIO_IO_O => SWs_8Bits_TRI_IO_O,
GPIO_IO_T => SWs_8Bits_TRI_IO_T,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
LEDs_8Bits : system_leds_8bits_wrapper
port map (
S_AXI_ACLK => pgassign1(7),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(1),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(40 downto 32),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(1),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(1),
S_AXI_WDATA => axi4lite_0_M_WDATA(63 downto 32),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(7 downto 4),
S_AXI_WVALID => axi4lite_0_M_WVALID(1),
S_AXI_WREADY => axi4lite_0_M_WREADY(1),
S_AXI_BRESP => axi4lite_0_M_BRESP(3 downto 2),
S_AXI_BVALID => axi4lite_0_M_BVALID(1),
S_AXI_BREADY => axi4lite_0_M_BREADY(1),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(40 downto 32),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(1),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(1),
S_AXI_RDATA => axi4lite_0_M_RDATA(63 downto 32),
S_AXI_RRESP => axi4lite_0_M_RRESP(3 downto 2),
S_AXI_RVALID => axi4lite_0_M_RVALID(1),
S_AXI_RREADY => axi4lite_0_M_RREADY(1),
IP2INTC_Irpt => open,
GPIO_IO_I => net_gnd8,
GPIO_IO_O => LEDs_8Bits_TRI_IO,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
BTNs_5Bits : system_btns_5bits_wrapper
port map (
S_AXI_ACLK => pgassign1(7),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(2),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(72 downto 64),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(2),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(2),
S_AXI_WDATA => axi4lite_0_M_WDATA(95 downto 64),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(11 downto 8),
S_AXI_WVALID => axi4lite_0_M_WVALID(2),
S_AXI_WREADY => axi4lite_0_M_WREADY(2),
S_AXI_BRESP => axi4lite_0_M_BRESP(5 downto 4),
S_AXI_BVALID => axi4lite_0_M_BVALID(2),
S_AXI_BREADY => axi4lite_0_M_BREADY(2),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(72 downto 64),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(2),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(2),
S_AXI_RDATA => axi4lite_0_M_RDATA(95 downto 64),
S_AXI_RRESP => axi4lite_0_M_RRESP(5 downto 4),
S_AXI_RVALID => axi4lite_0_M_RVALID(2),
S_AXI_RREADY => axi4lite_0_M_RREADY(2),
IP2INTC_Irpt => open,
GPIO_IO_I => BTNs_5Bits_TRI_IO_I,
GPIO_IO_O => BTNs_5Bits_TRI_IO_O,
GPIO_IO_T => BTNs_5Bits_TRI_IO_T,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => net_gnd0,
I2C0_SDA_O => open,
I2C0_SDA_T => open,
I2C0_SCL_I => net_gnd0,
I2C0_SCL_O => open,
I2C0_SCL_T => open,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi4lite_0_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi4lite_0_S_AWVALID(0),
M_AXI_GP0_BREADY => axi4lite_0_S_BREADY(0),
M_AXI_GP0_RREADY => axi4lite_0_S_RREADY(0),
M_AXI_GP0_WLAST => axi4lite_0_S_WLAST(0),
M_AXI_GP0_WVALID => axi4lite_0_S_WVALID(0),
M_AXI_GP0_ARID => axi4lite_0_S_ARID,
M_AXI_GP0_AWID => axi4lite_0_S_AWID,
M_AXI_GP0_WID => axi4lite_0_S_WID,
M_AXI_GP0_ARBURST => axi4lite_0_S_ARBURST,
M_AXI_GP0_ARLOCK => axi4lite_0_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi4lite_0_S_ARSIZE,
M_AXI_GP0_AWBURST => axi4lite_0_S_AWBURST,
M_AXI_GP0_AWLOCK => axi4lite_0_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi4lite_0_S_AWSIZE,
M_AXI_GP0_ARPROT => axi4lite_0_S_ARPROT,
M_AXI_GP0_AWPROT => axi4lite_0_S_AWPROT,
M_AXI_GP0_ARADDR => axi4lite_0_S_ARADDR,
M_AXI_GP0_AWADDR => axi4lite_0_S_AWADDR,
M_AXI_GP0_WDATA => axi4lite_0_S_WDATA,
M_AXI_GP0_ARCACHE => axi4lite_0_S_ARCACHE,
M_AXI_GP0_ARLEN => axi4lite_0_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi4lite_0_S_ARQOS,
M_AXI_GP0_AWCACHE => axi4lite_0_S_AWCACHE,
M_AXI_GP0_AWLEN => axi4lite_0_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi4lite_0_S_AWQOS,
M_AXI_GP0_WSTRB => axi4lite_0_S_WSTRB,
M_AXI_GP0_ACLK => pgassign1(7),
M_AXI_GP0_ARREADY => axi4lite_0_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi4lite_0_S_AWREADY(0),
M_AXI_GP0_BVALID => axi4lite_0_S_BVALID(0),
M_AXI_GP0_RLAST => axi4lite_0_S_RLAST(0),
M_AXI_GP0_RVALID => axi4lite_0_S_RVALID(0),
M_AXI_GP0_WREADY => axi4lite_0_S_WREADY(0),
M_AXI_GP0_BID => axi4lite_0_S_BID,
M_AXI_GP0_RID => axi4lite_0_S_RID,
M_AXI_GP0_BRESP => axi4lite_0_S_BRESP,
M_AXI_GP0_RRESP => axi4lite_0_S_RRESP,
M_AXI_GP0_RDATA => axi4lite_0_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_1_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_1_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_1_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_1_M_BID(0 to 0),
S_AXI_HP0_RID => axi_interconnect_1_M_RID(0 to 0),
S_AXI_HP0_RDATA => axi_interconnect_1_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => pgassign2(1),
S_AXI_HP0_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_1_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_1_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_1_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_1_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_1_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_1_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_1_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_1_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_1_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_1_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_1_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_1_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_1_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_1_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_1_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_1_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_1_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_1_M_ARID(0 to 0),
S_AXI_HP0_AWID => axi_interconnect_1_M_AWID(0 to 0),
S_AXI_HP0_WID => axi_interconnect_1_M_WID(0 to 0),
S_AXI_HP0_WDATA => axi_interconnect_1_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_1_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => processing_system7_0_FCLK_CLK1(0),
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N_0,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => net_gnd1(0 to 0),
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
fmc_imageon_iic_0 : system_fmc_imageon_iic_0_wrapper
port map (
S_AXI_ACLK => pgassign1(7),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(3),
IIC2INTC_Irpt => open,
S_AXI_AWADDR => axi4lite_0_M_AWADDR(104 downto 96),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(3),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(3),
S_AXI_WDATA => axi4lite_0_M_WDATA(127 downto 96),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(15 downto 12),
S_AXI_WVALID => axi4lite_0_M_WVALID(3),
S_AXI_WREADY => axi4lite_0_M_WREADY(3),
S_AXI_BRESP => axi4lite_0_M_BRESP(7 downto 6),
S_AXI_BVALID => axi4lite_0_M_BVALID(3),
S_AXI_BREADY => axi4lite_0_M_BREADY(3),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(104 downto 96),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(3),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(3),
S_AXI_RDATA => axi4lite_0_M_RDATA(127 downto 96),
S_AXI_RRESP => axi4lite_0_M_RRESP(7 downto 6),
S_AXI_RVALID => axi4lite_0_M_RVALID(3),
S_AXI_RREADY => axi4lite_0_M_RREADY(3),
Sda_I => fmc_imageon_iic_0_Sda_I,
Sda_O => fmc_imageon_iic_0_Sda_O,
Sda_T => fmc_imageon_iic_0_Sda_T,
Scl_I => fmc_imageon_iic_0_Scl_I,
Scl_O => fmc_imageon_iic_0_Scl_O,
Scl_T => fmc_imageon_iic_0_Scl_T,
Gpo => fmc_imageon_iic_0_Gpo(0 to 0)
);
fmc_imageon_hdmi_out_0 : system_fmc_imageon_hdmi_out_0_wrapper
port map (
clk => fmc_imageon_video_clk1,
reset => net_gnd0,
oe => net_vcc0,
embed_syncs => net_vcc0,
audio_spdif => net_gnd0,
xsvi_vblank_i => v_axi4s_vid_out_0_video_vblank,
xsvi_hblank_i => v_axi4s_vid_out_0_video_hblank,
xsvi_active_video_i => v_axi4s_vid_out_0_video_de,
xsvi_video_data_i => v_axi4s_vid_out_0_video_data,
io_hdmio_spdif => fmc_imageon_hdmi_out_0_io_hdmio_spdif,
io_hdmio_video => fmc_imageon_hdmi_out_0_io_hdmio_video,
io_hdmio_clk => fmc_imageon_hdmi_out_0_io_hdmio_clk,
debug_o => open
);
v_vid_in_axi4s_0 : system_v_vid_in_axi4s_0_wrapper
port map (
vid_in_clk => net_fmc_imageon_hdmi_in_0_clk_pin,
rst => net_gnd0,
vid_de => fmc_imageon_hdmi_in_0_video_de,
vid_vblank => fmc_imageon_hdmi_in_0_video_vblank,
vid_hblank => fmc_imageon_hdmi_in_0_video_hblank,
vid_vsync => net_gnd0,
vid_hsync => net_gnd0,
vid_data => fmc_imageon_hdmi_in_0_video_data,
aclk => pgassign2(1),
aresetn => net_vcc0,
aclken => net_vcc0,
m_axis_video_tdata => v_vid_in_axi4s_0_M_AXIS_VIDEO_tdata,
m_axis_video_tvalid => v_vid_in_axi4s_0_M_AXIS_VIDEO_tvalid,
m_axis_video_tready => v_vid_in_axi4s_0_M_AXIS_VIDEO_tready,
m_axis_video_tuser => v_vid_in_axi4s_0_M_AXIS_VIDEO_tuser(0),
m_axis_video_tlast => v_vid_in_axi4s_0_M_AXIS_VIDEO_tlast,
vtd_active_video => v_vid_in_axi4s_0_VTIMING_OUT_active_video,
vtd_vblank => v_vid_in_axi4s_0_VTIMING_OUT_vblank,
vtd_hblank => v_vid_in_axi4s_0_VTIMING_OUT_hblank,
vtd_vsync => v_vid_in_axi4s_0_VTIMING_OUT_vsync,
vtd_hsync => v_vid_in_axi4s_0_VTIMING_OUT_hsync,
wr_error => open,
empty => open,
axis_enable => net_vcc0
);
v_axi4s_vid_out_0 : system_v_axi4s_vid_out_0_wrapper
port map (
aclk => pgassign2(1),
rst => net_gnd0,
aresetn => net_vcc0,
aclken => net_vcc0,
s_axis_video_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
s_axis_video_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
s_axis_video_tready => axi_vdma_0_M_AXIS_MM2S_tready,
s_axis_video_tuser => axi_vdma_0_M_AXIS_MM2S_tuser(0),
s_axis_video_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
video_out_clk => fmc_imageon_video_clk1,
video_de => v_axi4s_vid_out_0_video_de,
video_vsync => open,
video_hsync => open,
video_vblank => v_axi4s_vid_out_0_video_vblank,
video_hblank => v_axi4s_vid_out_0_video_hblank,
video_data => v_axi4s_vid_out_0_video_data,
vtg_vsync => v_tc_vid_out_0_VTIMING_OUT_vsync,
vtg_hsync => v_tc_vid_out_0_VTIMING_OUT_hsync,
vtg_vblank => v_tc_vid_out_0_VTIMING_OUT_vblank,
vtg_hblank => v_tc_vid_out_0_VTIMING_OUT_hblank,
vtg_act_vid => v_tc_vid_out_0_VTIMING_OUT_active_video,
vtg_ce => v_axi4s_vid_out_0_vtg_ce,
vtg_fsync => open,
locked => open,
wr_error => open,
empty => open
);
axi_vdma_0 : system_axi_vdma_0_wrapper
port map (
s_axi_lite_aclk => pgassign1(7),
m_axi_sg_aclk => net_gnd0,
m_axi_mm2s_aclk => pgassign2(1),
m_axi_s2mm_aclk => pgassign2(1),
m_axis_mm2s_aclk => pgassign2(1),
s_axis_s2mm_aclk => pgassign2(1),
axi_resetn => axi4lite_0_M_ARESETN(4),
s_axi_lite_awvalid => axi4lite_0_M_AWVALID(4),
s_axi_lite_awready => axi4lite_0_M_AWREADY(4),
s_axi_lite_awaddr => axi4lite_0_M_AWADDR(136 downto 128),
s_axi_lite_wvalid => axi4lite_0_M_WVALID(4),
s_axi_lite_wready => axi4lite_0_M_WREADY(4),
s_axi_lite_wdata => axi4lite_0_M_WDATA(159 downto 128),
s_axi_lite_bresp => axi4lite_0_M_BRESP(9 downto 8),
s_axi_lite_bvalid => axi4lite_0_M_BVALID(4),
s_axi_lite_bready => axi4lite_0_M_BREADY(4),
s_axi_lite_arvalid => axi4lite_0_M_ARVALID(4),
s_axi_lite_arready => axi4lite_0_M_ARREADY(4),
s_axi_lite_araddr => axi4lite_0_M_ARADDR(136 downto 128),
s_axi_lite_rvalid => axi4lite_0_M_RVALID(4),
s_axi_lite_rready => axi4lite_0_M_RREADY(4),
s_axi_lite_rdata => axi4lite_0_M_RDATA(159 downto 128),
s_axi_lite_rresp => axi4lite_0_M_RRESP(9 downto 8),
m_axi_sg_araddr => open,
m_axi_sg_arlen => open,
m_axi_sg_arsize => open,
m_axi_sg_arburst => open,
m_axi_sg_arprot => open,
m_axi_sg_arcache => open,
m_axi_sg_arvalid => open,
m_axi_sg_arready => net_gnd0,
m_axi_sg_rdata => net_gnd32,
m_axi_sg_rresp => net_gnd2,
m_axi_sg_rlast => net_gnd0,
m_axi_sg_rvalid => net_gnd0,
m_axi_sg_rready => open,
m_axi_mm2s_araddr => axi_interconnect_1_S_ARADDR(31 downto 0),
m_axi_mm2s_arlen => axi_interconnect_1_S_ARLEN(7 downto 0),
m_axi_mm2s_arsize => axi_interconnect_1_S_ARSIZE(2 downto 0),
m_axi_mm2s_arburst => axi_interconnect_1_S_ARBURST(1 downto 0),
m_axi_mm2s_arprot => axi_interconnect_1_S_ARPROT(2 downto 0),
m_axi_mm2s_arcache => axi_interconnect_1_S_ARCACHE(3 downto 0),
m_axi_mm2s_arvalid => axi_interconnect_1_S_ARVALID(0),
m_axi_mm2s_arready => axi_interconnect_1_S_ARREADY(0),
m_axi_mm2s_rdata => axi_interconnect_1_S_RDATA(63 downto 0),
m_axi_mm2s_rresp => axi_interconnect_1_S_RRESP(1 downto 0),
m_axi_mm2s_rlast => axi_interconnect_1_S_RLAST(0),
m_axi_mm2s_rvalid => axi_interconnect_1_S_RVALID(0),
m_axi_mm2s_rready => axi_interconnect_1_S_RREADY(0),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
m_axis_mm2s_tkeep => open,
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_tready,
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
m_axis_mm2s_tuser => axi_vdma_0_M_AXIS_MM2S_tuser(0 to 0),
m_axi_s2mm_awaddr => axi_interconnect_1_S_AWADDR(63 downto 32),
m_axi_s2mm_awlen => axi_interconnect_1_S_AWLEN(15 downto 8),
m_axi_s2mm_awsize => axi_interconnect_1_S_AWSIZE(5 downto 3),
m_axi_s2mm_awburst => axi_interconnect_1_S_AWBURST(3 downto 2),
m_axi_s2mm_awprot => axi_interconnect_1_S_AWPROT(5 downto 3),
m_axi_s2mm_awcache => axi_interconnect_1_S_AWCACHE(7 downto 4),
m_axi_s2mm_awvalid => axi_interconnect_1_S_AWVALID(1),
m_axi_s2mm_awready => axi_interconnect_1_S_AWREADY(1),
m_axi_s2mm_wdata => axi_interconnect_1_S_WDATA(127 downto 64),
m_axi_s2mm_wstrb => axi_interconnect_1_S_WSTRB(15 downto 8),
m_axi_s2mm_wlast => axi_interconnect_1_S_WLAST(1),
m_axi_s2mm_wvalid => axi_interconnect_1_S_WVALID(1),
m_axi_s2mm_wready => axi_interconnect_1_S_WREADY(1),
m_axi_s2mm_bresp => axi_interconnect_1_S_BRESP(3 downto 2),
m_axi_s2mm_bvalid => axi_interconnect_1_S_BVALID(1),
m_axi_s2mm_bready => axi_interconnect_1_S_BREADY(1),
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => v_vid_in_axi4s_0_M_AXIS_VIDEO_tdata,
s_axis_s2mm_tkeep => net_vcc2,
s_axis_s2mm_tvalid => v_vid_in_axi4s_0_M_AXIS_VIDEO_tvalid,
s_axis_s2mm_tready => v_vid_in_axi4s_0_M_AXIS_VIDEO_tready,
s_axis_s2mm_tlast => v_vid_in_axi4s_0_M_AXIS_VIDEO_tlast,
s_axis_s2mm_tuser => v_vid_in_axi4s_0_M_AXIS_VIDEO_tuser(0 to 0),
mm2s_fsync => net_gnd0,
mm2s_frame_ptr_in => net_gnd6,
mm2s_frame_ptr_out => open,
mm2s_fsync_out => open,
mm2s_prmtr_update => open,
mm2s_buffer_empty => open,
mm2s_buffer_almost_empty => open,
s2mm_fsync => net_gnd0,
s2mm_frame_ptr_in => net_gnd6,
s2mm_frame_ptr_out => open,
s2mm_fsync_out => open,
s2mm_buffer_full => open,
s2mm_buffer_almost_full => open,
s2mm_prmtr_update => open,
mm2s_introut => open,
s2mm_introut => open,
axi_vdma_tstvec => open
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => pgassign2(1),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N_0,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => pgassign2,
S_AXI_AWID => net_gnd2,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => net_gnd4,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => net_gnd8,
S_AXI_AWUSER => net_gnd2,
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID,
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY,
S_AXI_WID => net_gnd2,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST,
S_AXI_WUSER => net_gnd2,
S_AXI_WVALID => axi_interconnect_1_S_WVALID,
S_AXI_WREADY => axi_interconnect_1_S_WREADY,
S_AXI_BID => open,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID,
S_AXI_BREADY => axi_interconnect_1_S_BREADY,
S_AXI_ARID => net_gnd2,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => net_gnd4,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => net_gnd8,
S_AXI_ARUSER => net_gnd2,
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID,
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY,
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST,
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID,
S_AXI_RREADY => axi_interconnect_1_S_RREADY,
M_AXI_ACLK => pgassign2(1 downto 1),
M_AXI_AWID => axi_interconnect_1_M_AWID(0 to 0),
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_1_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_1_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_1_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_1_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_1_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_1_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_1_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_1_M_WID(0 to 0),
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => axi_interconnect_1_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_1_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_1_M_BID(0 to 0),
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_1_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_1_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_1_M_ARID(0 to 0),
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_1_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_1_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_1_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_1_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_1_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_1_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_1_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_1_M_RID(0 to 0),
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => axi_interconnect_1_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_1_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_1_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
led_pwm_0 : system_led_pwm_0_wrapper
port map (
led0 => led_pwm_0_led0,
led1 => led_pwm_0_led1,
led2 => led_pwm_0_led2,
led3 => led_pwm_0_led3,
led4 => led_pwm_0_led4,
led5 => led_pwm_0_led5,
led6 => led_pwm_0_led6,
led7 => led_pwm_0_led7,
led8 => led_pwm_0_led8,
led9 => led_pwm_0_led9,
led10 => led_pwm_0_led10,
led11 => led_pwm_0_led11,
led12 => led_pwm_0_led12,
led13 => led_pwm_0_led13,
led14 => led_pwm_0_led14,
led15 => led_pwm_0_led15,
led16 => led_pwm_0_led16,
led17 => led_pwm_0_led17,
led18 => led_pwm_0_led18,
led19 => led_pwm_0_led19,
led20 => led_pwm_0_led20,
led21 => led_pwm_0_led21,
led22 => led_pwm_0_led22,
led23 => led_pwm_0_led23,
led24 => led_pwm_0_led24,
led25 => led_pwm_0_led25,
led26 => led_pwm_0_led26,
led27 => led_pwm_0_led27,
led28 => led_pwm_0_led28,
led29 => led_pwm_0_led29,
S_AXI_ACLK => pgassign1(7),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(5),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(191 downto 160),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(5),
S_AXI_WDATA => axi4lite_0_M_WDATA(191 downto 160),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(23 downto 20),
S_AXI_WVALID => axi4lite_0_M_WVALID(5),
S_AXI_BREADY => axi4lite_0_M_BREADY(5),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(191 downto 160),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(5),
S_AXI_RREADY => axi4lite_0_M_RREADY(5),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(5),
S_AXI_RDATA => axi4lite_0_M_RDATA(191 downto 160),
S_AXI_RRESP => axi4lite_0_M_RRESP(11 downto 10),
S_AXI_RVALID => axi4lite_0_M_RVALID(5),
S_AXI_WREADY => axi4lite_0_M_WREADY(5),
S_AXI_BRESP => axi4lite_0_M_BRESP(11 downto 10),
S_AXI_BVALID => axi4lite_0_M_BVALID(5),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(5)
);
fmc_imageon_hdmi_in_0 : system_fmc_imageon_hdmi_in_0_wrapper
port map (
clk => net_fmc_imageon_hdmi_in_0_clk_pin,
io_hdmii_spdif => net_fmc_imageon_hdmi_in_0_io_hdmii_spdif_pin,
io_hdmii_video => net_fmc_imageon_hdmi_in_0_io_hdmii_video_pin,
video_vblank => fmc_imageon_hdmi_in_0_video_vblank,
video_hblank => fmc_imageon_hdmi_in_0_video_hblank,
video_de => fmc_imageon_hdmi_in_0_video_de,
video_data => fmc_imageon_hdmi_in_0_video_data,
audio_spdif => open,
debug_o => open
);
v_tc_vid_in_0 : system_v_tc_vid_in_0_wrapper
port map (
s_axi_aclk => pgassign1(7),
s_axi_aresetn => axi4lite_0_M_ARESETN(6),
s_axi_aclken => net_vcc0,
s_axi_awaddr => axi4lite_0_M_AWADDR(200 downto 192),
s_axi_awvalid => axi4lite_0_M_AWVALID(6),
s_axi_awready => axi4lite_0_M_AWREADY(6),
s_axi_wdata => axi4lite_0_M_WDATA(223 downto 192),
s_axi_wstrb => axi4lite_0_M_WSTRB(27 downto 24),
s_axi_wvalid => axi4lite_0_M_WVALID(6),
s_axi_wready => axi4lite_0_M_WREADY(6),
s_axi_bresp => axi4lite_0_M_BRESP(13 downto 12),
s_axi_bvalid => axi4lite_0_M_BVALID(6),
s_axi_bready => axi4lite_0_M_BREADY(6),
s_axi_araddr => axi4lite_0_M_ARADDR(200 downto 192),
s_axi_arvalid => axi4lite_0_M_ARVALID(6),
s_axi_arready => axi4lite_0_M_ARREADY(6),
s_axi_rdata => axi4lite_0_M_RDATA(223 downto 192),
s_axi_rresp => axi4lite_0_M_RRESP(13 downto 12),
s_axi_rvalid => axi4lite_0_M_RVALID(6),
s_axi_rready => axi4lite_0_M_RREADY(6),
irq => open,
intc_if => open,
clk => net_fmc_imageon_hdmi_in_0_clk_pin,
resetn => net_vcc0,
clken => net_vcc0,
det_clken => net_vcc0,
gen_clken => net_vcc0,
fsync_in => net_gnd0,
vblank_in => v_vid_in_axi4s_0_VTIMING_OUT_vblank,
vsync_in => v_vid_in_axi4s_0_VTIMING_OUT_vsync,
hblank_in => v_vid_in_axi4s_0_VTIMING_OUT_hblank,
hsync_in => v_vid_in_axi4s_0_VTIMING_OUT_hsync,
active_video_in => v_vid_in_axi4s_0_VTIMING_OUT_active_video,
active_chroma_in => net_gnd0,
vblank_out => open,
vsync_out => open,
hblank_out => open,
hsync_out => open,
active_video_out => open,
active_chroma_out => open,
fsync_out => open
);
v_tc_vid_out_0 : system_v_tc_vid_out_0_wrapper
port map (
s_axi_aclk => pgassign1(7),
s_axi_aresetn => axi4lite_0_M_ARESETN(7),
s_axi_aclken => net_vcc0,
s_axi_awaddr => axi4lite_0_M_AWADDR(232 downto 224),
s_axi_awvalid => axi4lite_0_M_AWVALID(7),
s_axi_awready => axi4lite_0_M_AWREADY(7),
s_axi_wdata => axi4lite_0_M_WDATA(255 downto 224),
s_axi_wstrb => axi4lite_0_M_WSTRB(31 downto 28),
s_axi_wvalid => axi4lite_0_M_WVALID(7),
s_axi_wready => axi4lite_0_M_WREADY(7),
s_axi_bresp => axi4lite_0_M_BRESP(15 downto 14),
s_axi_bvalid => axi4lite_0_M_BVALID(7),
s_axi_bready => axi4lite_0_M_BREADY(7),
s_axi_araddr => axi4lite_0_M_ARADDR(232 downto 224),
s_axi_arvalid => axi4lite_0_M_ARVALID(7),
s_axi_arready => axi4lite_0_M_ARREADY(7),
s_axi_rdata => axi4lite_0_M_RDATA(255 downto 224),
s_axi_rresp => axi4lite_0_M_RRESP(15 downto 14),
s_axi_rvalid => axi4lite_0_M_RVALID(7),
s_axi_rready => axi4lite_0_M_RREADY(7),
irq => open,
intc_if => open,
clk => fmc_imageon_video_clk1,
resetn => net_vcc0,
clken => net_vcc0,
det_clken => net_vcc0,
gen_clken => v_axi4s_vid_out_0_vtg_ce,
fsync_in => net_gnd0,
vblank_in => net_gnd0,
vsync_in => net_gnd0,
hblank_in => net_gnd0,
hsync_in => net_gnd0,
active_video_in => net_gnd0,
active_chroma_in => net_gnd0,
vblank_out => v_tc_vid_out_0_VTIMING_OUT_vblank,
vsync_out => v_tc_vid_out_0_VTIMING_OUT_vsync,
hblank_out => v_tc_vid_out_0_VTIMING_OUT_hblank,
hsync_out => v_tc_vid_out_0_VTIMING_OUT_hsync,
active_video_out => v_tc_vid_out_0_VTIMING_OUT_active_video,
active_chroma_out => open,
fsync_out => open
);
iobuf_0 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(7),
IO => SWs_8Bits_TRI_IO(7),
O => SWs_8Bits_TRI_IO_I(7),
T => SWs_8Bits_TRI_IO_T(7)
);
iobuf_1 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(6),
IO => SWs_8Bits_TRI_IO(6),
O => SWs_8Bits_TRI_IO_I(6),
T => SWs_8Bits_TRI_IO_T(6)
);
iobuf_2 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(5),
IO => SWs_8Bits_TRI_IO(5),
O => SWs_8Bits_TRI_IO_I(5),
T => SWs_8Bits_TRI_IO_T(5)
);
iobuf_3 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(4),
IO => SWs_8Bits_TRI_IO(4),
O => SWs_8Bits_TRI_IO_I(4),
T => SWs_8Bits_TRI_IO_T(4)
);
iobuf_4 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(3),
IO => SWs_8Bits_TRI_IO(3),
O => SWs_8Bits_TRI_IO_I(3),
T => SWs_8Bits_TRI_IO_T(3)
);
iobuf_5 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(2),
IO => SWs_8Bits_TRI_IO(2),
O => SWs_8Bits_TRI_IO_I(2),
T => SWs_8Bits_TRI_IO_T(2)
);
iobuf_6 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(1),
IO => SWs_8Bits_TRI_IO(1),
O => SWs_8Bits_TRI_IO_I(1),
T => SWs_8Bits_TRI_IO_T(1)
);
iobuf_7 : IOBUF
port map (
I => SWs_8Bits_TRI_IO_O(0),
IO => SWs_8Bits_TRI_IO(0),
O => SWs_8Bits_TRI_IO_I(0),
T => SWs_8Bits_TRI_IO_T(0)
);
iobuf_8 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(4),
IO => BTNs_5Bits_TRI_IO(4),
O => BTNs_5Bits_TRI_IO_I(4),
T => BTNs_5Bits_TRI_IO_T(4)
);
iobuf_9 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(3),
IO => BTNs_5Bits_TRI_IO(3),
O => BTNs_5Bits_TRI_IO_I(3),
T => BTNs_5Bits_TRI_IO_T(3)
);
iobuf_10 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(2),
IO => BTNs_5Bits_TRI_IO(2),
O => BTNs_5Bits_TRI_IO_I(2),
T => BTNs_5Bits_TRI_IO_T(2)
);
iobuf_11 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(1),
IO => BTNs_5Bits_TRI_IO(1),
O => BTNs_5Bits_TRI_IO_I(1),
T => BTNs_5Bits_TRI_IO_T(1)
);
iobuf_12 : IOBUF
port map (
I => BTNs_5Bits_TRI_IO_O(0),
IO => BTNs_5Bits_TRI_IO(0),
O => BTNs_5Bits_TRI_IO_I(0),
T => BTNs_5Bits_TRI_IO_T(0)
);
iobuf_13 : IOBUF
port map (
I => fmc_imageon_iic_0_Sda_O,
IO => fmc_imageon_iic_0_Sda_pin,
O => fmc_imageon_iic_0_Sda_I,
T => fmc_imageon_iic_0_Sda_T
);
iobuf_14 : IOBUF
port map (
I => fmc_imageon_iic_0_Scl_O,
IO => fmc_imageon_iic_0_Scl_pin,
O => fmc_imageon_iic_0_Scl_I,
T => fmc_imageon_iic_0_Scl_T
);
end architecture STRUCTURE;
|
gpl-3.0
|
1b1ca8ddc0f0308059a96d9a9a2c33f5
| 0.615156 | 2.80031 | false | false | false | false |
CprE488/Final
|
system/hdl/system_leds_8bits_wrapper.vhd
| 2 | 4,991 |
-------------------------------------------------------------------------------
-- system_leds_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_leds_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_leds_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_leds_8bits_wrapper;
architecture STRUCTURE of system_leds_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
LEDs_8Bits : axi_gpio
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "LEDs_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
gpl-3.0
|
9df0d7a65bcec74936e27fdbf5cffd19
| 0.585454 | 2.918713 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_2/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_tb.vhd
| 1 | 6,208 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_2_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-3.0
|
b118ffc1147e373ab1571658503e1ac8
| 0.626772 | 4.012928 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_s6/example_design/pulse_regen_s6_top_wrapper.vhd
| 1 | 19,614 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_s6_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_s6_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(1-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(1-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pulse_regen_s6_top_wrapper;
architecture xilinx of pulse_regen_s6_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_s6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pulse_regen_s6_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
3ee66b78951ccf18ce7c8409f5bec87d
| 0.475987 | 3.976079 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/communication/nmea_frame_extractor.vhd
| 2 | 5,275 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:30 03/24/2014
-- Design Name:
-- Module Name: nmea_frame_extractor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic;
frame_error : out std_logic
);
end nmea_frame_extractor;
architecture Behavioral of nmea_frame_extractor is
type parser_state is (CHECK_HEADER, RECEIVE_INFO, END_OF_DATA);
function headerEqVec(header : string; comp : slv8_array) return boolean is
variable eq : boolean := true ;
variable nmea_char : std_logic_vector(7 downto 0) ;
begin
for i in 0 to ((header'length)-1) loop
nmea_char := (std_logic_vector(to_unsigned( character'pos(header(i+1)), 8))) ;
eq := eq and (nmea_char = comp(i));
end loop ;
return eq ;
end headerEqVec ;
function validField(current : std_logic_vector; fields : slv8_array) return boolean is
variable eq : boolean := false ;
begin
for i in 0 to ((fields'length)-1) loop
eq := eq or (current = fields(i));
end loop ;
return eq ;
end validField ;
signal cur_state, next_state : parser_state ;
signal shift_reg : slv8_array(0 to nmea_header'length-1) ;
signal char_counter : std_logic_vector(7 downto 0) ;
signal compute_checksum : std_logic_vector(7 downto 0) ;
signal en_checksum, reset_checksum, checksum_good : std_logic ;
signal frame_checksum, frame_checksum_high, frame_checksum_low : std_logic_vector(7 downto 0) ;
begin
process(clk, reset)
begin
if reset = '1' then
shift_reg <= (others => (others => '0'));
elsif clk'event and clk = '1' then
if new_byte_in = '1' then
shift_reg(0 to 4) <= shift_reg(1 to 5) ;
shift_reg(5) <= nmea_byte_in ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= CHECK_HEADER;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, shift_reg)
begin
next_state <= cur_state;
case cur_state is
when CHECK_HEADER =>
if headerEqVec(nmea_header, shift_reg) then
next_state <= RECEIVE_INFO ;
end if ;
when RECEIVE_INFO =>
if checksum_good = '1' then -- buffer contains '*'
next_state <= END_OF_DATA ;
elsif shift_reg(0) = X"0D" or shift_reg(0) = X"0A" then -- buffer contains '\n' or '\t'
next_state <= CHECK_HEADER ;
end if ;
when END_OF_DATA =>
next_state <= CHECK_HEADER ;
when others =>
next_state <= CHECK_HEADER ;
end case ;
end process ;
process(clk, reset)
begin
if reset = '1'then
char_counter <= X"01" ;
elsif clk'event and clk = '1' then
if shift_reg(0) = X"24" then -- char is '$'
char_counter <= X"01";
elsif cur_state=RECEIVE_INFO and new_byte_in = '1' then -- counting char in frame
char_counter <= char_counter + 1 ;
end if ;
end if ;
end process ;
-- checksum handling ...
process(clk, reset)
begin
if reset = '1'then
compute_checksum <= X"00" ;
en_checksum <= '0' ;
elsif clk'event and clk = '1' then
-- $ is not in checksum
if new_byte_in = '1' and shift_reg(5) = X"24" then
compute_checksum <= X"00";
elsif en_checksum = '1' and new_byte_in = '1' and shift_reg(5) /= X"2A" then
compute_checksum <= compute_checksum xor shift_reg(5);
end if ;
if shift_reg(5) = X"24" then -- $ enables the checksum computation
en_checksum <= '1' ;
elsif shift_reg(5) = X"2A" then -- char is '*', end of
en_checksum <= '0' ;
end if ;
end if ;
end process ;
frame_checksum_high <= (shift_reg(1) - X"30") when shift_reg(1) < X"3A" else
(shift_reg(1) - X"37") ;
frame_checksum_low <= (shift_reg(2) - X"30") when shift_reg(2) < X"3A" else
(shift_reg(2) - X"37") ;
frame_checksum <= frame_checksum_high(3 downto 0) & frame_checksum_low(3 downto 0) ;
reset_checksum <= '1' when nmea_byte_in = X"24" else
'0' ;
checksum_good <= '1' when frame_checksum = compute_checksum and shift_reg(0) = X"2A" else
'0' ;
frame_error <= '1' when cur_state = RECEIVE_INFO and (shift_reg(0) = X"0D" or shift_reg(0) = X"0A") else
'0' ;
frame_size <= char_counter ;
end_of_frame <= '1' when cur_state = END_OF_DATA else
'0' ;
nmea_byte_out <= shift_reg(0) ;
new_byte_out <= new_byte_in when cur_state = RECEIVE_INFO else
'0' ;
end Behavioral;
|
lgpl-3.0
|
2735d8a5b87a942206474fe2f3c5c35a
| 0.629763 | 2.960157 | false | false | false | false |
CprE488/Final
|
system/hdl/system_v_tc_vid_in_0_wrapper.vhd
| 1 | 10,193 |
-------------------------------------------------------------------------------
-- system_v_tc_vid_in_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library v_tc_v5_01_a;
use v_tc_v5_01_a.all;
entity system_v_tc_vid_in_0_wrapper is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector(8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_v_tc_vid_in_0_wrapper : entity is "v_tc_v5_01_a";
end system_v_tc_vid_in_0_wrapper;
architecture STRUCTURE of system_v_tc_vid_in_0_wrapper is
component v_tc is
generic (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_AUTO_SWITCH : integer;
C_MAX_PIXELS : integer;
C_MAX_LINES : integer;
C_NUM_FSYNCS : integer;
C_DETECT_EN : integer;
C_GENERATE_EN : integer;
C_DET_HSYNC_EN : integer;
C_DET_VSYNC_EN : integer;
C_DET_HBLANK_EN : integer;
C_DET_VBLANK_EN : integer;
C_DET_AVIDEO_EN : integer;
C_DET_ACHROMA_EN : integer;
C_GEN_HSYNC_EN : integer;
C_GEN_VSYNC_EN : integer;
C_GEN_HBLANK_EN : integer;
C_GEN_VBLANK_EN : integer;
C_GEN_AVIDEO_EN : integer;
C_GEN_ACHROMA_EN : integer;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_CPARITY : integer;
C_SYNC_EN : integer;
C_GEN_VBLANK_POLARITY : integer;
C_GEN_HBLANK_POLARITY : integer;
C_GEN_VSYNC_POLARITY : integer;
C_GEN_HSYNC_POLARITY : integer;
C_GEN_AVIDEO_POLARITY : integer;
C_GEN_ACHROMA_POLARITY : integer;
C_GEN_VACTIVE_SIZE : integer;
C_GEN_HACTIVE_SIZE : integer;
C_GEN_HFRAME_SIZE : integer;
C_GEN_F0_VFRAME_SIZE : integer;
C_GEN_HSYNC_START : integer;
C_GEN_HSYNC_END : integer;
C_GEN_F0_VBLANK_HSTART : integer;
C_GEN_F0_VBLANK_HEND : integer;
C_GEN_F0_VSYNC_VSTART : integer;
C_GEN_F0_VSYNC_VEND : integer;
C_GEN_F0_VSYNC_HSTART : integer;
C_GEN_F0_VSYNC_HEND : integer;
C_FSYNC_HSTART0 : integer;
C_FSYNC_VSTART0 : integer;
C_FSYNC_HSTART1 : integer;
C_FSYNC_VSTART1 : integer;
C_FSYNC_HSTART2 : integer;
C_FSYNC_VSTART2 : integer;
C_FSYNC_HSTART3 : integer;
C_FSYNC_VSTART3 : integer;
C_FSYNC_HSTART4 : integer;
C_FSYNC_VSTART4 : integer;
C_FSYNC_HSTART5 : integer;
C_FSYNC_VSTART5 : integer;
C_FSYNC_HSTART6 : integer;
C_FSYNC_VSTART6 : integer;
C_FSYNC_HSTART7 : integer;
C_FSYNC_VSTART7 : integer;
C_FSYNC_HSTART8 : integer;
C_FSYNC_VSTART8 : integer;
C_FSYNC_HSTART9 : integer;
C_FSYNC_VSTART9 : integer;
C_FSYNC_HSTART10 : integer;
C_FSYNC_VSTART10 : integer;
C_FSYNC_HSTART11 : integer;
C_FSYNC_VSTART11 : integer;
C_FSYNC_HSTART12 : integer;
C_FSYNC_VSTART12 : integer;
C_FSYNC_HSTART13 : integer;
C_FSYNC_VSTART13 : integer;
C_FSYNC_HSTART14 : integer;
C_FSYNC_VSTART14 : integer;
C_FSYNC_HSTART15 : integer;
C_FSYNC_VSTART15 : integer;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_FAMILY : STRING
);
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_aclken : in std_logic;
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
irq : out std_logic;
intc_if : out std_logic_vector(31 downto 0);
clk : in std_logic;
resetn : in std_logic;
clken : in std_logic;
det_clken : in std_logic;
gen_clken : in std_logic;
fsync_in : in std_logic;
vblank_in : in std_logic;
vsync_in : in std_logic;
hblank_in : in std_logic;
hsync_in : in std_logic;
active_video_in : in std_logic;
active_chroma_in : in std_logic;
vblank_out : out std_logic;
vsync_out : out std_logic;
hblank_out : out std_logic;
hsync_out : out std_logic;
active_video_out : out std_logic;
active_chroma_out : out std_logic;
fsync_out : out std_logic_vector(C_NUM_FSYNCS-1 to 0)
);
end component;
begin
v_tc_vid_in_0 : v_tc
generic map (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_AUTO_SWITCH => 1,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_DETECT_EN => 1,
C_GENERATE_EN => 0,
C_DET_HSYNC_EN => 0,
C_DET_VSYNC_EN => 0,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_VIDEO_FORMAT => 0,
C_GEN_CPARITY => 0,
C_SYNC_EN => 0,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VACTIVE_SIZE => 720,
C_GEN_HACTIVE_SIZE => 1280,
C_GEN_HFRAME_SIZE => 1650,
C_GEN_F0_VFRAME_SIZE => 750,
C_GEN_HSYNC_START => 1390,
C_GEN_HSYNC_END => 1430,
C_GEN_F0_VBLANK_HSTART => 1280,
C_GEN_F0_VBLANK_HEND => 1280,
C_GEN_F0_VSYNC_VSTART => 724,
C_GEN_F0_VSYNC_VEND => 729,
C_GEN_F0_VSYNC_HSTART => 1280,
C_GEN_F0_VSYNC_HEND => 1280,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_FAMILY => "zynq"
)
port map (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aclken => s_axi_aclken,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
intc_if => intc_if,
clk => clk,
resetn => resetn,
clken => clken,
det_clken => det_clken,
gen_clken => gen_clken,
fsync_in => fsync_in,
vblank_in => vblank_in,
vsync_in => vsync_in,
hblank_in => hblank_in,
hsync_in => hsync_in,
active_video_in => active_video_in,
active_chroma_in => active_chroma_in,
vblank_out => vblank_out,
vsync_out => vsync_out,
hblank_out => hblank_out,
hsync_out => hsync_out,
active_video_out => active_video_out,
active_chroma_out => active_chroma_out,
fsync_out => fsync_out
);
end architecture STRUCTURE;
|
gpl-3.0
|
2c33782307506687bd74f3b9975e3086
| 0.568822 | 2.987397 | false | false | false | false |
fpga-logi/logi-hard
|
test_bench/cam_deser_4_to_pixels_tb.vhd
| 1 | 6,791 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:40:23 12/18/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/cam_deser_4_to_pixels_tb.vhd
-- Project Name: cam_deser
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cam_deser_4_to_pixels
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cam_deser_4_to_pixels_tb IS
END cam_deser_4_to_pixels_tb;
ARCHITECTURE behavior OF cam_deser_4_to_pixels_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cam_deser_4_to_pixels_v2
generic(INVERT_DATA : boolean := true);
PORT(
deser_clk : IN std_logic;
sys_clk : IN std_logic;
sys_reset : IN std_logic;
data_in_deser : IN std_logic_vector(3 downto 0);
pixel_out_clk : OUT std_logic;
pixel_out_hsync : OUT std_logic;
pixel_out_vsync : OUT std_logic;
pixel_out_data : OUT std_logic_vector(7 downto 0);
synced_out : OUT std_logic
);
END COMPONENT;
component deser_1_4
generic
(-- width of the data for the system
sys_w : integer := 1;
-- width of the data for the device
dev_w : integer := 4);
port
(
-- From the system into the device
DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0); -- User should tie it to '0' if not needed
-- Clock and reset signals
CLK_IN_P : in std_logic; -- Differential fast clock from IOB
CLK_IN_N : in std_logic;
CLK_DIV_OUT : out std_logic; -- Slow clock output
CLK_RESET : in std_logic; -- Reset signal for Clock circuit
IO_RESET : in std_logic); -- Reset signal for IO circuit
end component;
--Inputs
signal deser_clk : std_logic := '0';
signal sys_clk : std_logic := '0';
signal sys_reset : std_logic := '0';
signal data_in_deser : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal pixel_out_clk : std_logic;
signal pixel_out_hsync : std_logic;
signal pixel_out_vsync : std_logic;
signal pixel_out_data : std_logic_vector(7 downto 0);
signal synced_out : std_logic;
signal CLK_IN_P, CLK_IN_N, DATA_IN_FROM_PINS_P, DATA_IN_FROM_PINS_N : std_logic ;
-- Clock period definitions
constant ser_clk_period : time := 3 ns;
constant sys_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cam_deser_4_to_pixels_v2
generic map(INVERT_DATA => false)
PORT MAP (
deser_clk => deser_clk,
sys_clk => sys_clk,
sys_reset => sys_reset,
data_in_deser => data_in_deser,
pixel_out_clk => pixel_out_clk,
pixel_out_hsync => pixel_out_hsync,
pixel_out_vsync => pixel_out_vsync,
pixel_out_data => pixel_out_data,
synced_out => synced_out
);
uut2 : deser_1_4
port map
(
-- From the system into the device
DATA_IN_FROM_PINS_P(0) => DATA_IN_FROM_PINS_P, --Input pins
DATA_IN_FROM_PINS_N(0) => DATA_IN_FROM_PINS_N, --Input pins
DATA_IN_TO_DEVICE => data_in_deser, --Output pins
-- Clock and reset signals
CLK_IN_P => CLK_IN_P, -- Differential clock from IOB
CLK_IN_N => CLK_IN_N, -- Differential clock from IOB
CLK_DIV_OUT => deser_clk, -- Slow clock output
CLK_RESET => sys_reset, --clocking logic reset
IO_RESET => sys_reset
);
-- Clock process definitions
ser_clk_process :process
begin
CLK_IN_P <= '0';
CLK_IN_N <= '1' ;
wait for ser_clk_period/2;
CLK_IN_P <= '1';
CLK_IN_N <= '0' ;
wait for ser_clk_period/2;
end process;
sys_clk_process :process
begin
sys_clk <= '0';
wait for sys_clk_period/2;
sys_clk <= '1';
wait for sys_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable data : std_logic_vector(7 downto 0) ;
begin
-- hold reset state for 100 ns.
sys_reset <= '1' ;
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for 100 ns;
sys_reset <= '0' ;
wait until CLK_IN_P = '0'; --sync on clock
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
-- DATA_IN_FROM_PINS_P <= '0' ;
-- DATA_IN_FROM_PINS_N <= '1' ;
-- wait for ser_clk_period;
for j in 0 to 100 loop
data := std_logic_vector(to_unsigned(j, 8));
-- now issuing start bit
DATA_IN_FROM_PINS_P <= '1' ;
DATA_IN_FROM_PINS_N <= '0' ;
wait for ser_clk_period;
for i in 0 to 9 loop
if i < 8 then
DATA_IN_FROM_PINS_P <= data(i) ;
DATA_IN_FROM_PINS_N <= not data(i) ;
else
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
end if ;
wait for ser_clk_period;
end loop ;
-- now issuing stop bit
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
end loop ;
-- messing up with the sync
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
for j in 0 to 100 loop
-- now issuing start bit
DATA_IN_FROM_PINS_P <= '1' ;
DATA_IN_FROM_PINS_N <= '0' ;
wait for ser_clk_period;
for i in 0 to 9 loop
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
end loop ;
-- now issuing stop bit
DATA_IN_FROM_PINS_P <= '0' ;
DATA_IN_FROM_PINS_N <= '1' ;
wait for ser_clk_period;
end loop ;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
2becf0f39fb3c07011653e2bfb759ebf
| 0.575615 | 3.075634 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng.vhd
| 2 | 4,028 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
17f189a48cd05224c9e765700a7bfaa5
| 0.643992 | 4.266949 | false | false | false | false |
CprE488/Final
|
system/hdl/system_fmc_imageon_iic_0_wrapper.vhd
| 1 | 4,515 |
-------------------------------------------------------------------------------
-- system_fmc_imageon_iic_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_iic_v1_02_a;
use axi_iic_v1_02_a.all;
entity system_fmc_imageon_iic_0_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_fmc_imageon_iic_0_wrapper : entity is "axi_iic_v1_02_a";
end system_fmc_imageon_iic_0_wrapper;
architecture STRUCTURE of system_fmc_imageon_iic_0_wrapper is
component axi_iic is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector((C_GPO_WIDTH-1) to 0)
);
end component;
begin
fmc_imageon_iic_0 : axi_iic
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "fmc_imageon_iic_0",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2INTC_Irpt => IIC2INTC_Irpt,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
Sda_I => Sda_I,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => Scl_I,
Scl_O => Scl_O,
Scl_T => Scl_T,
Gpo => Gpo
);
end architecture STRUCTURE;
|
gpl-3.0
|
61edc5287f5ab108963a70b8a541b46a
| 0.569435 | 2.943286 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/alt_dfe/_primary.vhd
| 1 | 3,034 |
library verilog;
use verilog.vl_types.all;
entity alt_dfe is
generic(
channel_address_width: integer := 3;
lpm_type : string := "alt_dfe";
lpm_hint : string := "UNUSED";
avmm_slave_addr_width: integer := 16;
avmm_slave_rdata_width: integer := 16;
avmm_slave_wdata_width: integer := 16;
avmm_master_addr_width: integer := 16;
avmm_master_rdata_width: integer := 16;
avmm_master_wdata_width: integer := 16;
dprio_addr_width: integer := 16;
dprio_data_width: integer := 16;
ireg_chaddr_width: vl_notype;
ireg_wdaddr_width: integer := 2;
ireg_data_width : integer := 16;
ST_IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0);
ST_WRITE : vl_logic_vector(0 to 1) := (Hi0, Hi1);
ST_READ : vl_logic_vector(0 to 1) := (Hi1, Hi0)
);
port(
i_resetn : in vl_logic;
i_avmm_clk : in vl_logic;
i_avmm_saddress : in vl_logic_vector;
i_avmm_sread : in vl_logic;
i_avmm_swrite : in vl_logic;
i_avmm_swritedata: in vl_logic_vector;
o_avmm_sreaddata: out vl_logic_vector;
o_avmm_swaitrequest: out vl_logic;
i_remap_address : in vl_logic_vector(11 downto 0);
o_quad_address : out vl_logic_vector(8 downto 0);
o_reconfig_busy : out vl_logic;
i_dprio_busy : in vl_logic;
i_dprio_in : in vl_logic_vector;
o_dprio_wren : out vl_logic;
o_dprio_rden : out vl_logic;
o_dprio_addr : out vl_logic_vector;
o_dprio_data : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of avmm_slave_addr_width : constant is 1;
attribute mti_svvh_generic_type of avmm_slave_rdata_width : constant is 1;
attribute mti_svvh_generic_type of avmm_slave_wdata_width : constant is 1;
attribute mti_svvh_generic_type of avmm_master_addr_width : constant is 1;
attribute mti_svvh_generic_type of avmm_master_rdata_width : constant is 1;
attribute mti_svvh_generic_type of avmm_master_wdata_width : constant is 1;
attribute mti_svvh_generic_type of dprio_addr_width : constant is 1;
attribute mti_svvh_generic_type of dprio_data_width : constant is 1;
attribute mti_svvh_generic_type of ireg_chaddr_width : constant is 3;
attribute mti_svvh_generic_type of ireg_wdaddr_width : constant is 1;
attribute mti_svvh_generic_type of ireg_data_width : constant is 1;
attribute mti_svvh_generic_type of ST_IDLE : constant is 1;
attribute mti_svvh_generic_type of ST_WRITE : constant is 1;
attribute mti_svvh_generic_type of ST_READ : constant is 1;
end alt_dfe;
|
bsd-2-clause
|
ed54cdd8196d8542302dd4ca8669971a
| 0.617337 | 3.397536 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/encoder_interface.vhd
| 2 | 6,974 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:59 05/12/2014
-- Design Name:
-- Module Name: encoder_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder_interface is
generic(FREQ_DIV : positive := 100; SINGLE_CHANNEL : boolean := true);
port(
clk, reset : in std_logic ;
channel_a, channel_b : in std_logic;
period : out std_logic_vector(15 downto 0);
pv : out std_logic ;
count : out std_logic_vector(15 downto 0);
reset_count : in std_logic
);
end encoder_interface;
architecture Behavioral of encoder_interface is
constant DEBOUNCER_DIV : positive := 10 ;
type enc_states is (IDLE, A_H, B_H, A_L, B_L);
signal cur_state, next_state : enc_states ;
signal period_counter, period_latched, pulse_counter : std_logic_vector(15 downto 0);
signal divider_counter : std_logic_vector(15 downto 0);
signal end_div : std_logic ;
signal inc_counter, dec_counter, valid_cw, valid_ccw, latch_period : std_logic ;
signal channel_a_deb, channel_b_deb : std_logic ;
signal debouncer_counter : std_logic_vector(15 downto 0);
begin
-- simple debouncer
process(clk, reset)
begin
if reset = '1' then
debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ;
elsif clk'event and clk = '1' then
if debouncer_counter = 0 then
debouncer_counter <= std_logic_vector(to_unsigned(DEBOUNCER_DIV, 16)) ;
else
debouncer_counter <= debouncer_counter - 1 ;
end if ;
end if ;
end process;
gen_sing : if SINGLE_CHANNEL = true generate
process(clk, reset)
begin
if reset = '1' then
channel_b_deb <= '0' ;
channel_a_deb <= '0' ;
elsif clk'event and clk = '1' then
if debouncer_counter = 0 then
channel_a_deb <= channel_a ;
channel_b_deb <= channel_a_deb;
end if ;
end if ;
end process ;
end generate ;
gen_no_sing : if SINGLE_CHANNEL = false generate
process(clk, reset)
begin
if reset = '1' then
channel_b_deb <= '0' ;
channel_a_deb <= '0' ;
elsif clk'event and clk = '1' then
if debouncer_counter = 0 then
channel_a_deb <= channel_a ;
channel_b_deb <= channel_b;
end if ;
end if ;
end process ;
end generate ;
-- end of debouncer
process(clk, reset)
begin
if reset = '1' then
cur_state <= IDLE ;
elsif clk'event and clk='1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, channel_a_deb, channel_b_deb)
begin
next_state <= cur_state ;
case cur_state is
when IDLE =>
if channel_a_deb = '1' and channel_b_deb='0' then
next_state <= A_H ;
end if ;
if channel_b_deb = '1' and channel_a_deb='0' then
next_state <= A_L ;
end if ;
when A_H =>
if channel_a_deb = '1' and channel_b_deb = '1' then
next_state <= B_H ;
end if ;
if channel_a_deb = '0' and channel_b_deb = '0' then
next_state <= IDLE ;
end if ;
when B_H =>
if channel_a_deb = '0' and channel_b_deb = '1' then
next_state <= A_L ;
end if ;
if channel_b_deb = '0' and channel_a_deb = '1' then
next_state <= A_H ;
end if ;
when A_L =>
if channel_a_deb = '0' and channel_b_deb = '0' then
next_state <= IDLE ;
end if ;
if channel_a_deb = '1' and channel_b_deb = '1' then
next_state <= B_H ;
end if ;
when others => next_state <= IDLE ;
end case ;
end process ;
inc_counter <= '1' when cur_state = IDLE and next_state = A_H else
'0' ;
dec_counter <= '1' when cur_state = A_H and next_state = IDLE else
'0' ;
latch_period <= '1' when cur_state = IDLE and channel_a_deb = '1' else
'1' when cur_state = IDLE and channel_b_deb = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
valid_cw <= '0' ;
valid_ccw <= '0' ;
elsif clk'event and clk='1' then
if cur_state = IDLE and channel_a_deb='1' then
valid_cw <= '1' ;
elsif cur_state = A_H and channel_a_deb='0' then
valid_cw <= '0' ;
elsif cur_state = B_H and channel_b_deb='0' then
valid_cw <= '0' ;
elsif cur_state = A_L and channel_a_deb='1' then
valid_cw <= '0' ;
elsif cur_state = IDLE and channel_b_deb='1' then
valid_cw <= '0' ;
end if ;
if cur_state = IDLE and channel_b_deb='1' then
valid_ccw <= '1' ;
elsif cur_state = A_L and channel_b_deb='0' then
valid_ccw <= '0' ;
elsif cur_state = B_H and channel_a_deb='0' then
valid_ccw <= '0' ;
elsif cur_state = A_H and channel_b_deb='1' then
valid_ccw <= '0' ;
elsif cur_state = IDLE and channel_a_deb='1' then
valid_ccw <= '0' ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
divider_counter <= (others => '0') ;
elsif clk'event and clk='1' then
if end_div = '1' then
divider_counter <= std_logic_vector(to_unsigned(FREQ_DIV-1, 16)) ;
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
end_div <= '1' when divider_counter = 0 else
'0' ;
process(clk, reset)
begin
if reset = '1' then
period_counter <= (others => '0') ;
elsif clk'event and clk='1' then
if latch_period = '1' then
period_counter <= (others => '0') ;
elsif end_div = '1' and period_counter /= X"7FFF" and period_counter /= X"8000" then
period_counter <= period_counter + 1 ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
period_latched <= (others => '0') ;
pv <= '0' ;
elsif clk'event and clk='1' then
if latch_period = '1' and ((valid_ccw = '1' and channel_b_deb='1') or (valid_cw = '1' and channel_a_deb='1') ) then
if valid_ccw = '0' and valid_cw = '1' then
period_latched <= period_counter ;
else
period_latched <= (NOT period_counter) + 1 ;
end if;
pv <= '1' ;
elsif period_counter = X"7FFF" or period_counter = X"8000" then
period_latched <= X"8000" ;
pv <= '1' ;
else
pv <= '0' ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
pulse_counter <= (others => '0') ;
elsif clk'event and clk='1' then
if reset_count = '1' then
pulse_counter <= (others => '0') ;
elsif inc_counter = '1' then
pulse_counter <= pulse_counter + 1 ;
elsif dec_counter = '1' then
pulse_counter <= pulse_counter - 1 ;
end if ;
end if ;
end process ;
period <= period_latched ;
count <= pulse_counter ;
end Behavioral;
|
lgpl-3.0
|
69513f29461b333690eab42b5873bb97
| 0.602237 | 2.893776 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/mmcm_iserdes_divider_v6.vhd
| 1 | 8,503 |
-- file: mmcm_iserdes_divider_v6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- VITA ISERDES Divider MMCM
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___619.963______0.000______50.0_______94.974____122.782
-- CLK_OUT2____61.996______0.000______50.0______149.133____122.782
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________620.000____________0.005
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity mmcm_iserdes_divider_v6 is
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end mmcm_iserdes_divider_v6;
architecture xilinx of mmcm_iserdes_divider_v6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "mmcm_iserdes_divider_v6,clk_wiz_v3_2,{component_name=mmcm_iserdes_divider_v6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=1.613,clkin2_period=1.613,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN1_P,
IB => CLK_IN1_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 5.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 1.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 1.613,
REF_JITTER1 => 0.005)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
gpl-3.0
|
266efab49f521014ca471be09b3088ff
| 0.566976 | 4.060649 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/GenRegFalling.vhd
| 3 | 1,617 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 09:06:37 10/30/2009
-- Design Name:
-- Module Name: GenRegFalling - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-- Description: A generic, falling-edge register for use in the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.90 - File written and syntax checked. No need for simulation
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GenRegFalling is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end GenRegFalling;
architecture Behavioral of GenRegFalling is
begin
main: process (clock, reset) is
variable data_reg : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
if falling_edge(clock) then
if reset = '1' then
data_reg := (others => '0');
elsif enable = '1' then
data_reg := data;
end if;
end if;
output <= data_reg;
end process;
end Behavioral;
|
mit
|
353ac3c5598c871990d9316eb7f8014d
| 0.573284 | 3.675 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/spi_lowlevel.vhd
| 1 | 12,259 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (Fri, 02 Jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
--synopsys:
-----------
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--user:
-----------
--library work;
--use work.all;
--use work.app_pack.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity spi_lowlevel is
generic
(
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50; -- Clock Speed in MHz
gSpiClkSpeed : integer := 1000; -- SPI Clock Speed in kHz
gUseFixedSpeed : integer := 1; -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH : integer := 16;
gTxMSB_FIRST : integer := 1;
gRxMSB_FIRST : integer := 1;
gSCLK_POLARITY : std_logic := '0'; --'0': idle low, '1': idle high
gCS_POLARITY : std_logic := '1'; --'0': active high, '1': active low
gEN_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMOSI_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_SAMPLE : std_logic := '0'; --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK : std_logic := '0' --'0': clock out on rising edge, '1': clock out on falling edge
);
port
(
--
-- Control signals
--
CLK : in std_logic;
RESET : in std_logic;
START : in std_logic;
BUSY : out std_logic;
SPI_DATA_TX : in std_logic_Vector((gDATA_WIDTH-1) downto 0);
SPI_DATA_RX : out std_logic_vector((gDATA_WIDTH-1) downto 0);
TIMING : in std_logic_vector(15 downto 0);
--
-- SPI
--
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
CS : out std_logic;
EN : out std_logic
);
end spi_lowlevel;
---------------------------
-- BEHAVIOUR DESCRIPTION --
---------------------------
architecture rtl of spi_lowlevel is
----------------------------
-- COMPONENTS DEFINITIONS --
----------------------------
-- user components
-- none
-------------------------------
-- TYPE & SIGNAL DEFINITIONS --
-------------------------------
-- Objects for spi control
------------------------------------------------------------------
type clockstateTP is ( Idle, Bridge, CS_Active, First_Clk_Low, Clk_High, Clk_Low, Enable_Active);
signal clockstate : clockstateTP;
signal TxIndex : integer range 0 to gDATA_WIDTH;
signal RxIndex : integer range 0 to gDATA_WIDTH;
signal TxWord : std_logic_vector((gDATA_WIDTH-1) downto 0);
signal RxWord : std_logic_vector((gDATA_WIDTH-1) downto 0);
signal TimerCnt : std_logic_vector(16 downto 0);
signal Counter : std_logic_vector(16 downto 0);
signal ClockCounter : std_logic_vector(15 downto 0);
signal ClockOut : std_logic;
signal SampleIn : std_logic;
--------------------------
-- CONSTANT DEFINITION --
--------------------------
--------------------
-- MAIN BEHAVIOUR --
--------------------
begin
-- wiring:
variable_timing: if (gUseFixedSpeed = 0) generate
TimerCnt <= '0' & TIMING(15 downto 0);
end generate;
fixed_timing: if (gUseFixedSpeed > 0) generate
TimerCnt <= conv_std_logic_vector((integer(real(gSysClkSpeed*1000)/real(gSpiClkSpeed)) - 2),17);
end generate;
----------------------------------------------------------------------
-- CNTR process ------------------------------------------------------
----------------------------------------------------------------------
counterpr: Process(RESET,CLK)
begin
if (RESET='1') then
Counter <= "10000000000000000";
elsif (CLK'event and CLK='1') then
if Counter(16)='1' then
Counter <= TimerCnt;
else
Counter <= Counter - 1;
end if;
end if;
end process;
----------------------------------------------------------------------
-- CLOCK process -----------------------------------------------------
----------------------------------------------------------------------
clockpr: Process(RESET,CLK)
begin
if (RESET='1') then
BUSY <= '0';
SCLK <= gSCLK_POLARITY;
CS <= gCS_POLARITY;
EN <= gEN_POLARITY;
ClockOut <= '0';
SampleIn <= '0';
ClockCounter <= (others => '0');
ClockState <= Idle;
elsif (CLK'event and CLK='1') then
ClockOut <= '0';
SampleIn <= '0';
case clockstate is
when Idle =>
BUSY <= '0';
if (START = '1') then
ClockCounter <= conv_std_logic_vector((gDATA_WIDTH-2), (ClockCounter'high+1));
BUSY <= '1';
clockstate <= Bridge;
end if;
when Bridge =>
if (Counter(Counter'high) = '1') then
CS <= not gCS_POLARITY;
clockstate <= CS_Active;
end if;
when CS_Active =>
if (Counter(Counter'high) = '1') then
ClockOut <= not gMOSI_CLK;
SCLK <= gSCLK_POLARITY;
clockstate <= First_Clk_Low;
end if;
when First_Clk_Low =>
if (Counter(Counter'high) = '1') then
ClockOut <= gMOSI_CLK;
SCLK <= not gSCLK_POLARITY;
clockstate <= Clk_High;
end if;
when Clk_Low =>
if (Counter(Counter'high) = '1') then
ClockOut <= gMOSI_CLK;
SampleIn <= gMISO_SAMPLE;
SCLK <= not gSCLK_POLARITY;
clockstate <= Clk_High;
end if;
when Clk_High =>
if (Counter(Counter'high) = '1') then
if (ClockCounter(ClockCounter'high) = '1') then
SCLK <= gSCLK_POLARITY;
EN <= not gEN_POLARITY;
SampleIn <= not gMISO_SAMPLE;
clockstate <= Enable_Active;
else
ClockCounter <= ClockCounter - '1';
ClockOut <= not gMOSI_CLK;
SampleIn <= not gMISO_SAMPLE;
SCLK <= gSCLK_POLARITY;
clockstate <= Clk_Low;
end if;
end if;
when Enable_Active =>
if (Counter(Counter'high) = '1') then
EN <= gEN_POLARITY;
CS <= gCS_POLARITY;
SampleIn <= gMISO_SAMPLE;
clockstate <= Idle;
end if;
when others =>
end case;
end if;
end process;
TxMSBFirstGen: if (gTxMSB_FIRST > 0) generate
genloop: for i in 0 to (gDATA_WIDTH-1) generate
TxWord(i) <= SPI_DATA_TX((gDATA_WIDTH-1)-i);
end generate;
end generate;
TxMSBLastGen: if (gTxMSB_FIRST = 0) generate
TxWord <= SPI_DATA_TX;
end generate;
RxMSBFirstGen: if (gRxMSB_FIRST > 0) generate
genloop: for i in 0 to (gDATA_WIDTH-1) generate
SPI_DATA_RX(i) <= RxWord((gDATA_WIDTH-1)-i);
end generate;
end generate;
RxMSBLasttGen: if (gRxMSB_FIRST = 0) generate
SPI_DATA_RX <= RxWord;
end generate;
data_transfer: process(RESET,CLK)
begin
if (RESET='1') then
RxWord <= (others => '0');
TxIndex <= 0;
RxIndex <= 0;
MOSI <= '0';
elsif (CLK'event and CLK='1') then
if (START = '1') then
TxIndex <= 0;
elsif (ClockOut = '1') then
if (gMOSI_POLARITY = '0') then
MOSI <= TxWord(TxIndex);
else
MOSI <= not TxWord(TxIndex);
end if;
TxIndex <= TxIndex + 1;
end if;
if (START = '1') then
RxIndex <= 0;
elsif (SampleIn = '1') then
if gMISO_POLARITY = '0' then
RxWord(RxIndex) <= MISO;
else
RxWord(RxIndex) <= not MISO;
end if;
RxIndex <= RxIndex + 1;
end if;
end if;
end process data_transfer;
end rtl;
|
gpl-3.0
|
fe256fd78dde66ccea7366282c1b56ae
| 0.40819 | 4.911458 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/example_design/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes.vhd
| 1 | 5,073 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
8cb688301e65b97ad18c750026a0046e
| 0.542874 | 4.767857 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_servo.vhd
| 2 | 5,326 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:27:45 08/19/2013
-- Design Name:
-- Module Name: servo_controller_wb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_servo is
generic(NB_SERVOS : positive := 2;
wb_size : natural := 16 ; -- Data port size for wishbone
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
failsafe : in std_logic ;
servos : out std_logic_vector(NB_SERVOS-1 downto 0)
);
end wishbone_servo;
architecture Behavioral of wishbone_servo is
component servo_controller is
generic(
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port (clk : in std_logic;
rst : in std_logic;
servo_position : in std_logic_vector (pos_width-1 downto 0);
servo_out : out std_logic);
end component;
constant reset_pulse : std_logic_vector(15 downto 0) := X"8080";
type reg16_array is array (0 to (NB_SERVOS-1)) of std_logic_vector(15 downto 0) ;
signal pos_regs : reg16_array := (others => reset_pulse);
signal failsafe_regs : reg16_array := (others => reset_pulse);
signal servo_pos : reg16_array ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_readdata <= pos_regs(conv_integer(wbs_address)) ;
register_mngmt : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
pos_regs <= (others => reset_pulse) ;
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '0' then
pos_regs(conv_integer(wbs_address(15 downto 1))) <= wbs_writedata;
end if ;
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) and wbs_address(0) = '1' then
failsafe_regs(conv_integer(wbs_address(15 downto 1))) <= wbs_writedata;
end if ;
end if;
end process register_mngmt;
gen_servo_ctrl : for i in 0 to (NB_SERVOS-1) generate
servo_pos(i) <= pos_regs(i) when failsafe = '0' else
failsafe_regs(i) ;
servo_ctrl : servo_controller
generic map(
pos_width => pos_width,
clock_period => clock_period,
minimum_high_pulse_width => minimum_high_pulse_width,
maximum_high_pulse_width => maximum_high_pulse_width
)
port map(clk => gls_clk,
rst => gls_reset,
servo_position =>servo_pos(i)(pos_width-1 downto 0),
servo_out => servos(i)
);
end generate ;
end Behavioral;
|
lgpl-3.0
|
07a96d638214133e48a6c46016271e3b
| 0.602328 | 3.557782 | false | false | false | false |
fpga-logi/logi-hard
|
test_bench/servo_controller_tb.vhd
| 2 | 3,341 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:08:22 05/12/2013
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-projects/AVC2013/avc_platform/servo_controller_tb.vhd
-- Project Name: avc_platform
-- Target Device:
-- Tool versions: ISE 14.1
-- Description:
--
-- VHDL Test Bench Created by ISE for module: servo_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY servo_controller_tb IS
END servo_controller_tb;
ARCHITECTURE behavior OF servo_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT servo_controller
PORT(
clk : IN std_logic;
rst : IN std_logic;
servo_position : IN std_logic_vector(0 to 7);
servo_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal servo_position : std_logic_vector(0 to 7) := (others => '0');
--Outputs
signal servo_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: servo_controller PORT MAP (
clk => clk,
rst => rst,
servo_position => servo_position,
servo_out => servo_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1' ;
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0' ;
servo_position <= X"80";
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
4f9143de6aaa952a58f2effa75837e11
| 0.607603 | 4.140025 | false | false | false | false |
CprE488/Final
|
system/hdl/system_led_pwm_0_wrapper.vhd
| 1 | 6,046 |
-------------------------------------------------------------------------------
-- system_led_pwm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library led_pwm_v1_01_a;
use led_pwm_v1_01_a.all;
entity system_led_pwm_0_wrapper is
port (
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic;
led8 : out std_logic;
led9 : out std_logic;
led10 : out std_logic;
led11 : out std_logic;
led12 : out std_logic;
led13 : out std_logic;
led14 : out std_logic;
led15 : out std_logic;
led16 : out std_logic;
led17 : out std_logic;
led18 : out std_logic;
led19 : out std_logic;
led20 : out std_logic;
led21 : out std_logic;
led22 : out std_logic;
led23 : out std_logic;
led24 : out std_logic;
led25 : out std_logic;
led26 : out std_logic;
led27 : out std_logic;
led28 : out std_logic;
led29 : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end system_led_pwm_0_wrapper;
architecture STRUCTURE of system_led_pwm_0_wrapper is
component led_pwm is
generic (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : std_logic_vector;
C_USE_WSTRB : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_FAMILY : STRING;
C_NUM_REG : INTEGER;
C_NUM_MEM : INTEGER;
C_SLV_AWIDTH : INTEGER;
C_SLV_DWIDTH : INTEGER
);
port (
led0 : out std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic;
led5 : out std_logic;
led6 : out std_logic;
led7 : out std_logic;
led8 : out std_logic;
led9 : out std_logic;
led10 : out std_logic;
led11 : out std_logic;
led12 : out std_logic;
led13 : out std_logic;
led14 : out std_logic;
led15 : out std_logic;
led16 : out std_logic;
led17 : out std_logic;
led18 : out std_logic;
led19 : out std_logic;
led20 : out std_logic;
led21 : out std_logic;
led22 : out std_logic;
led23 : out std_logic;
led24 : out std_logic;
led25 : out std_logic;
led26 : out std_logic;
led27 : out std_logic;
led28 : out std_logic;
led29 : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end component;
begin
led_pwm_0 : led_pwm
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_MIN_SIZE => X"000001ff",
C_USE_WSTRB => 0,
C_DPHASE_TIMEOUT => 8,
C_BASEADDR => X"76600000",
C_HIGHADDR => X"7660ffff",
C_FAMILY => "zynq",
C_NUM_REG => 32,
C_NUM_MEM => 1,
C_SLV_AWIDTH => 32,
C_SLV_DWIDTH => 32
)
port map (
led0 => led0,
led1 => led1,
led2 => led2,
led3 => led3,
led4 => led4,
led5 => led5,
led6 => led6,
led7 => led7,
led8 => led8,
led9 => led9,
led10 => led10,
led11 => led11,
led12 => led12,
led13 => led13,
led14 => led14,
led15 => led15,
led16 => led16,
led17 => led17,
led18 => led18,
led19 => led19,
led20 => led20,
led21 => led21,
led22 => led22,
led23 => led23,
led24 => led24,
led25 => led25,
led26 => led26,
led27 => led27,
led28 => led28,
led29 => led29,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY
);
end architecture STRUCTURE;
|
gpl-3.0
|
b368abc6e6811a948004456ce39c01f4
| 0.555243 | 3.00796 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_led_matrix_ctrl.vhd
| 2 | 4,165 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:28:56 07/06/2014
-- Design Name:
-- Module Name: wishbone_led_matrix_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- This controller is based on Glen Atkins work (http://bikerglen.com/projects/lighting/led-panel-1up/)
-- Minor modification on controller behavior to adapt to wishbone bus
-- Major modification on coding style to meet XST guidelines
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
library work;
use work.logi_utils_pack.all ;
use work.control_pack.all ;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_led_matrix_ctrl is
generic(wb_size : positive := 16;
clk_div : positive := 10;
-- TODO: nb_panels is untested, still need to be validated
nb_panels : positive := 1 ;
bits_per_color : INTEGER RANGE 1 TO 4 := 4 ;
expose_step_cycle : positive := 1910
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
SCLK_OUT : out std_logic ;
BLANK_OUT : out std_logic ;
LATCH_OUT : out std_logic ;
A_OUT : out std_logic_vector(3 downto 0);
R_out : out std_logic_vector(1 downto 0);
G_out : out std_logic_vector(1 downto 0);
B_out : out std_logic_vector(1 downto 0)
);
end wishbone_led_matrix_ctrl;
architecture Behavioral of wishbone_led_matrix_ctrl is
signal read_ack : std_logic ;
signal write_ack, write_pixel: std_logic ;
signal pixel_addr : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
begin
-- wishbone related logic
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
-- ram buffer instanciation
write_pixel <= wbs_strobe and wbs_write and wbs_cycle ;
pixel_addr <= wbs_address(pixel_addr'high downto 0);
matrix_ctrl0 : rgb_32_32_matrix_ctrl
generic map(
clk_div => clk_div,
nb_panels => nb_panels,
expose_step_cycle => expose_step_cycle,
bits_per_color => bits_per_color
)
port map(
clk => gls_clk, reset => gls_reset,
pixel_addr => pixel_addr,
pixel_value_in => wbs_writedata((bits_per_color*3)-1 downto 0),
pixel_value_out => wbs_readdata((bits_per_color*3)-1 downto 0),
write_pixel => write_pixel,
SCLK_OUT => SCLK_OUT,
BLANK_OUT => BLANK_OUT,
LATCH_OUT => LATCH_OUT,
A_OUT => A_OUT,
R_out => R_OUT,
G_out => G_OUT,
B_out => B_OUT
);
wbs_readdata (15 downto (bits_per_color*3)) <= (others => '0');
end Behavioral;
|
lgpl-3.0
|
33ae56e9dfccd00a473331a7c5b3b0e6
| 0.583433 | 3.482441 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth.vhd
| 1 | 11,586 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(20-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(20-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(20-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(20-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 20,
C_DOUT_WIDTH => 20,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 20,
C_DIN_WIDTH => 20,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 20,
C_DIN_WIDTH => 20,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
59b21f9fab9a72f09ac24b060d2713b0
| 0.468496 | 3.876213 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
| 1 | 11,115 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(74-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 74,
C_DOUT_WIDTH => 74,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 74,
C_DIN_WIDTH => 74,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
3d672815bdb3b0b8dfe282914fae74b4
| 0.467476 | 4.04918 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/axi_tpg_v2_00_a/hdl/vhdl/zplate_top.vhd
| 1 | 5,424 |
LIBRARY ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library work;
use work.ZplateLib.all;
entity zplate is
generic
(
OutWidth : integer := 8;
DeltaWidth : integer := 17
);
port
(
clk : in std_logic;
HDeltaStart : in std_logic_vector((DeltaWidth - 1) downto 0);
HDelta2 : in std_logic_vector((DeltaWidth - 1) downto 0);
VDeltaStart : in std_logic_vector((DeltaWidth - 1) downto 0);
VDelta2 : in std_logic_vector((DeltaWidth - 1) downto 0);
ZPStart : in std_logic_vector((DeltaWidth - 1) downto 0);
de_in : in std_logic;
HSync : in std_logic;
VSync : in std_logic;
Dout : out std_logic_vector((OutWidth - 1) downto 0);
ZP_debug : out std_logic_vector(57 downto 0)
);
end zplate;
architecture rtl of zplate is
type SinTableNBits is array (0 to 2047) of std_logic_vector((OutWidth - 1) downto 0);
signal SinTableArray : SinTableNBits;
signal SinTableAddress : integer;
signal d_hsync, d2_hsync, re_hsync, fe_hsync : std_logic;
signal d_vsync, d2_vsync, re_vsync : std_logic;
signal d_de_in : std_logic;
signal d_HDelta2 : std_logic_vector((DeltaWidth - 1) downto 0);
signal d_VDelta2 : std_logic_vector((DeltaWidth - 1) downto 0);
signal NewHDelta : std_logic_vector((DeltaWidth - 1) downto 0);
signal NewVDelta : std_logic_vector((DeltaWidth - 1) downto 0);
signal d_NewHDelta : std_logic_vector((DeltaWidth - 1) downto 0);
signal d_NewVDelta : std_logic_vector((DeltaWidth - 1) downto 0);
signal CurrentHLUTAddr : std_logic_vector((DeltaWidth - 1) downto 0);
signal CurrentVLUTAddr : std_logic_vector((DeltaWidth - 1) downto 0);
signal d_CurrentHLUTAddr : std_logic_vector((DeltaWidth - 1) downto 0);
signal d_CurrentVLUTAddr : std_logic_vector((DeltaWidth - 1) downto 0);
signal AppliedRdAddr : std_logic_vector(10 downto 0);
signal VLUTOffset : std_logic_vector((DeltaWidth - 1) downto 0);
signal t_DOut : std_logic_vector(7 downto 0);
begin
-- Create NBit Sin table - hope it creates BROMs!
SinTableGen : for i in 0 to 2047 generate
-- SinTableArray(i) <= conv_std_logic_vector((SinTable(i)*((2**OutWidth)-3))/(2**(19-OutWidth)), OutWidth);
SinTableArray(i) <= conv_std_logic_vector(144+(SinTable(i)*((2**OutWidth)-35)/(2**(19-OutWidth)*(2**OutWidth))), OutWidth);
end generate;
VProc: process(clk)
begin
if (clk'event and clk = '1') then
d_de_in <= de_in;
d_vsync <= VSync;
d2_vsync <= d_vSync;
re_vsync <= d_vSync and not(d2_vsync);
if (re_vSync = '1') then
d_VDelta2 <= (others => '0');
NewVDelta <= VDeltaStart;
d_NewVDelta <= (others => '0');
CurrentVLUTAddr <= ZPStart;
elsif (re_hsync = '1') then
d_VDelta2 <= VDelta2;
NewVDelta <= NewVDelta + d_VDelta2; -- Every line, increase the amount by which we increase the Sine Table address
d_NewVDelta <= NewVDelta; -- Register it so it has a chance of getting across to another DSP48 if necessary.
CurrentVLUTAddr <= CurrentVLUTAddr + d_NewVDelta; -- Now add the increase to the Sine Table read address
-- VLUTOffset <= SinTableArray(conv_integer(CurrentVLUTAddr((DeltaWidth-1) downto (DeltaWidth - 12)))); -- ... and address the table.
end if;
end if;
end process;
HProc: process(clk)
begin
if (clk'event and clk = '1') then
d_hsync <= HSync;
d2_hsync <= d_hSync;
re_hsync <= d_hSync and not(d2_hsync);
fe_hsync <= d2_hSync and not(d_hsync);
if (d_hsync = '1') then
d_HDelta2 <= (others => '0');
NewHDelta <= HDeltaStart;
CurrentHLUTAddr <= CurrentVLUTAddr;
d_NewHDelta <= (others => '0');
elsif (d_de_in = '1') then
d_HDelta2 <= HDelta2;
NewHDelta <= NewHDelta + d_HDelta2; -- Every pixel, increase the amount by which we increase the Sine Table address
d_NewHDelta <= NewHDelta; -- Register it so it has a chance of getting across to another DSP48 if necessary.
CurrentHLUTAddr <= CurrentHLUTAddr + d_NewHDelta; -- Now add the increase to the Sine Table read address
d_CurrentHLUTAddr <= CurrentHLUTAddr; -- + CurrentVLUTAddr; -- Add Vertical offset.
t_DOut <= SinTableArray(conv_integer(AppliedRdAddr)); -- ... and address the table.
end if;
end if;
end process;
DOut <= t_DOut;
ZP_debug <= d_hSync & -- 1 bit
d_vsync & -- 1 bit
d_HDelta2 & -- 16 bits
d_NewHDelta & -- 16 bits
d_CurrentHLUTAddr & -- 16 bits
t_DOut; -- 8 bits
AppliedRdAddr <= d_CurrentHLUTAddr((DeltaWidth-1) downto (DeltaWidth - 11));
end rtl;
|
gpl-3.0
|
1f198597472ae6ea950c6bc96176d542
| 0.558444 | 3.606383 | false | false | false | false |
miguelgarcia/sase2017-hls-video
|
hdmi_in_hls/repo/sase/hdl/vhdl/my_video_filter.vhd
| 2 | 107,130 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_video_filter is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
src_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
src_TVALID : IN STD_LOGIC;
src_TREADY : OUT STD_LOGIC;
src_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0);
src_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0);
src_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
src_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
src_TID : IN STD_LOGIC_VECTOR (0 downto 0);
src_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
dest_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
dest_TVALID : OUT STD_LOGIC;
dest_TREADY : IN STD_LOGIC;
dest_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0);
dest_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0);
dest_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
dest_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
dest_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
dest_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of my_video_filter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"my_video_filter,hls_ip_2015_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.510000,HLS_SYN_LAT=6220809,HLS_SYN_TPT=none,HLS_SYN_MEM=12,HLS_SYN_DSP=1,HLS_SYN_FF=990,HLS_SYN_LUT=1001}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_pp0_stg1_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_pp0_stg2_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st11_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv14_780 : STD_LOGIC_VECTOR (13 downto 0) := "00011110000000";
constant ap_const_lv14_F00 : STD_LOGIC_VECTOR (13 downto 0) := "00111100000000";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_24 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal width : STD_LOGIC_VECTOR (15 downto 0);
signal height : STD_LOGIC_VECTOR (15 downto 0);
signal my_video_filter_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal indvar_flatten_reg_373 : STD_LOGIC_VECTOR (31 downto 0);
signal row_reg_384 : STD_LOGIC_VECTOR (15 downto 0);
signal col_assign_reg_395 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_100 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal exitcond_flatten_fu_506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_110 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal exitcond_flatten_reg_1562 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_dest_TREADY : STD_LOGIC;
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_sig_cseq_ST_pp0_stg2_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_132 : BOOLEAN;
signal ap_sig_bdd_137 : BOOLEAN;
signal height_read_reg_1361 : STD_LOGIC_VECTOR (15 downto 0);
signal width_read_reg_1366 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_434_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_cast_reg_1372 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_cast_fu_438_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_cast_reg_1377 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_442_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_163 : BOOLEAN;
signal tmp_9_fu_448_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_454_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_s_reg_1499 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_4_fu_459_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_4_reg_1504 : STD_LOGIC_VECTOR (16 downto 0);
signal bound_fu_1355_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal bound_reg_1509 : STD_LOGIC_VECTOR (31 downto 0);
signal window_val_0_1_0_1_load_reg_1514 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_1_1_load_reg_1519 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_2_1_load_reg_1524 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_0_1_load_reg_1529 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_1_1_load_reg_1534 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_2_1_load_reg_1539 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_0_1_load_reg_1544 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_1_1_load_reg_1550 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_2_1_load_reg_1556 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next_fu_511_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal indvar_flatten_next_reg_1566 : STD_LOGIC_VECTOR (31 downto 0);
signal row_mid2_fu_581_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal row_mid2_reg_1571 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_602_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_reg_1576 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_fu_608_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_reg_1581 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_31_cast_fu_618_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_cast_reg_1586 : STD_LOGIC_VECTOR (63 downto 0);
signal line_buffers_val_1_addr_reg_1591 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_1_addr_1_reg_1596 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_2_addr_reg_1602 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_2_addr_1_reg_1607 : STD_LOGIC_VECTOR (12 downto 0);
signal val_assign_2_fu_629_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal val_assign_2_reg_1613 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_val_assign_2_reg_1613_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_val_assign_2_reg_1613_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_fu_635_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal col_reg_1618 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_32_cast5_fu_646_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_32_cast5_reg_1623 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_pp0_stg1_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal line_buffers_val_1_addr_2_reg_1628 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_2_addr_2_reg_1633 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_2_0_reg_1638 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_fu_705_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_reg_1643 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_22_fu_727_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_22_reg_1648 : STD_LOGIC_VECTOR (9 downto 0);
signal window_val_2_2_1_reg_1653 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_2_1_reg_1661 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_2_1_reg_1667 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_2_load_reg_1673 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_2_load_reg_1678 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_24_fu_848_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_24_reg_1683 : STD_LOGIC_VECTOR (11 downto 0);
signal dx_1_fu_922_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal dx_1_reg_1688 : STD_LOGIC_VECTOR (10 downto 0);
signal dy_1_fu_984_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal dy_1_reg_1695 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_38_2_fu_1043_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_38_2_reg_1702 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_46_2_fu_1065_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_46_2_reg_1707 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_26_fu_1134_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_26_reg_1712 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp2_fu_1255_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp2_reg_1717 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp4_fu_1261_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp4_reg_1722 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_30_fu_1324_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_30_reg_1727 : STD_LOGIC_VECTOR (7 downto 0);
signal icmp_fu_1342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_reg_1732 : STD_LOGIC_VECTOR (0 downto 0);
signal p_1_fu_1348_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_1_reg_1737 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_0_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_0_ce0 : STD_LOGIC;
signal line_buffers_val_0_we0 : STD_LOGIC;
signal line_buffers_val_0_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_0_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_0_ce1 : STD_LOGIC;
signal line_buffers_val_0_we1 : STD_LOGIC;
signal line_buffers_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_1_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_1_ce0 : STD_LOGIC;
signal line_buffers_val_1_we0 : STD_LOGIC;
signal line_buffers_val_1_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_1_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_1_ce1 : STD_LOGIC;
signal line_buffers_val_1_we1 : STD_LOGIC;
signal line_buffers_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_2_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_2_ce0 : STD_LOGIC;
signal line_buffers_val_2_we0 : STD_LOGIC;
signal line_buffers_val_2_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal line_buffers_val_2_address1 : STD_LOGIC_VECTOR (12 downto 0);
signal line_buffers_val_2_ce1 : STD_LOGIC;
signal line_buffers_val_2_we1 : STD_LOGIC;
signal line_buffers_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_reg_362 : STD_LOGIC_VECTOR (1 downto 0);
signal indvar_flatten_phi_fu_377_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal row_phi_fu_388_p4 : STD_LOGIC_VECTOR (15 downto 0);
signal col_assign_phi_fu_399_p4 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_0_1_0_1_fu_140 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_1_1_fu_144 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_2_1_fu_148 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_0_fu_152 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_1_fu_156 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_2_fu_160 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_0_1_fu_164 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_1_1_fu_168 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_2_1_fu_172 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_0_fu_176 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_1_fu_180 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_2_fu_184 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_0_1_fu_188 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_1_1_fu_192 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_2_1_fu_196 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_0_fu_200 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_1_fu_204 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_2_fu_208 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ioackin_dest_TREADY : STD_LOGIC := '0';
signal exitcond_fu_568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal row_1_fu_562_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal row_cast_fu_589_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal col_assign_mid2_fu_573_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_fu_612_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal col_assign_cast_fu_598_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_fu_593_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_624_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_641_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_10_fu_659_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_670_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_20_cast_fu_655_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_cast_fu_652_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_689_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_27_cast_fu_695_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_22_cast_fu_666_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_24_cast_fu_678_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_13_fu_699_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_20_fu_711_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_cast_fu_717_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_25_cast1_fu_682_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_21_fu_721_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_26_cast_fu_685_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_25_cast_fu_743_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_16_fu_750_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_26_cast9_fu_746_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_17_fu_761_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_773_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_32_cast_fu_769_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_37_cast_fu_785_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_23_fu_788_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_34_cast_fu_781_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal dy_fu_794_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abscond_fu_806_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_fu_800_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abs_fu_812_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal dx_fu_755_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abscond1_fu_830_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg1_fu_824_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abs1_fu_836_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal abs1_cast_fu_844_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal abs_cast_fu_820_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_31_1_fu_860_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_1_fu_871_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_29_1_cast_fu_857_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_28_1_cast_fu_854_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_1_fu_894_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_1_cast_fu_900_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_31_1_cast_fu_867_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_33_1_cast_fu_878_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_37_1_fu_904_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_38_1_fu_910_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_34_1_cast_fu_885_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_39_1_fu_916_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_35_1_cast7_fu_888_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_41_1_fu_928_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_43_1_fu_940_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_44_1_fu_952_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_44_1_cast_fu_958_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_34_1_cast8_fu_882_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_45_1_fu_962_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_35_1_cast_fu_891_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_46_1_fu_968_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_41_1_cast_fu_936_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_46_1_cast_fu_974_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_47_1_fu_978_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_43_1_cast_fu_948_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_31_2_fu_997_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_2_fu_1008_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_29_2_cast_fu_993_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_28_2_cast_fu_990_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_2_fu_1027_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_2_cast_fu_1033_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_31_2_cast_fu_1004_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_33_2_cast_fu_1016_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_37_2_fu_1037_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_44_2_fu_1049_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_44_2_cast_fu_1055_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_34_2_cast6_fu_1020_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_45_2_fu_1059_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_35_2_cast_fu_1023_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal abscond_1_fu_1108_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_1_fu_1103_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_25_fu_1113_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal abscond1_1_fu_1129_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg1_1_fu_1124_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_34_2_cast_fu_1141_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_39_2_fu_1148_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_35_2_cast5_fu_1144_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_41_2_fu_1159_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_43_2_fu_1170_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_41_2_cast_fu_1166_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_46_2_cast_fu_1181_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_47_2_fu_1184_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_43_2_cast_fu_1177_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal dy_2_fu_1190_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abscond_2_fu_1202_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_2_fu_1196_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abs_2_fu_1208_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal dx_2_fu_1153_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abscond1_2_fu_1226_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg1_2_fu_1220_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal abs1_2_fu_1232_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_31_fu_1244_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal abs1_2_cast_fu_1240_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal abs_2_cast_fu_1216_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_13_cast_fu_1251_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal abs_1_cast_cast_fu_1120_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal abs1_1_cast_cast_fu_1267_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp3_fu_1273_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp2_cast_cast_fu_1270_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_15_fu_1278_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal p_neg_fu_1292_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_27_fu_1298_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_32_fu_1284_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_fu_1308_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_29_fu_1314_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_33_fu_1332_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal bound_fu_1355_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal bound_fu_1355_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st11_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_1030 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal bound_fu_1355_p00 : STD_LOGIC_VECTOR (31 downto 0);
signal bound_fu_1355_p10 : STD_LOGIC_VECTOR (31 downto 0);
component my_video_filter_mul_mul_16ns_16ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component my_video_filter_line_buffers_val_0 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (12 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
component my_video_filter_line_buffers_val_1 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (12 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0);
q1 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component my_video_filter_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
width : OUT STD_LOGIC_VECTOR (15 downto 0);
height : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
my_video_filter_AXILiteS_s_axi_U : component my_video_filter_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => my_video_filter_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
width => width,
height => height);
line_buffers_val_0_U : component my_video_filter_line_buffers_val_0
generic map (
DataWidth => 8,
AddressRange => 5760,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => line_buffers_val_0_address0,
ce0 => line_buffers_val_0_ce0,
we0 => line_buffers_val_0_we0,
d0 => line_buffers_val_0_d0,
address1 => line_buffers_val_0_address1,
ce1 => line_buffers_val_0_ce1,
we1 => line_buffers_val_0_we1,
d1 => line_buffers_val_0_d1);
line_buffers_val_1_U : component my_video_filter_line_buffers_val_1
generic map (
DataWidth => 8,
AddressRange => 5760,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => line_buffers_val_1_address0,
ce0 => line_buffers_val_1_ce0,
we0 => line_buffers_val_1_we0,
d0 => line_buffers_val_1_d0,
q0 => line_buffers_val_1_q0,
address1 => line_buffers_val_1_address1,
ce1 => line_buffers_val_1_ce1,
we1 => line_buffers_val_1_we1,
d1 => line_buffers_val_1_d1,
q1 => line_buffers_val_1_q1);
line_buffers_val_2_U : component my_video_filter_line_buffers_val_1
generic map (
DataWidth => 8,
AddressRange => 5760,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => line_buffers_val_2_address0,
ce0 => line_buffers_val_2_ce0,
we0 => line_buffers_val_2_we0,
d0 => line_buffers_val_2_d0,
q0 => line_buffers_val_2_q0,
address1 => line_buffers_val_2_address1,
ce1 => line_buffers_val_2_ce1,
we1 => line_buffers_val_2_we1,
d1 => line_buffers_val_2_d1,
q1 => line_buffers_val_2_q1);
my_video_filter_mul_mul_16ns_16ns_32_1_U1 : component my_video_filter_mul_mul_16ns_16ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 32)
port map (
din0 => bound_fu_1355_p0,
din1 => bound_fu_1355_p1,
dout => bound_fu_1355_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_dest_TREADY assign process. --
ap_reg_ioackin_dest_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_dest_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
ap_reg_ioackin_dest_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137)) and (ap_const_logic_1 = dest_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110)) and (ap_const_logic_1 = dest_TREADY)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137)) and (ap_const_logic_1 = dest_TREADY)))) then
ap_reg_ioackin_dest_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_flatten_fu_506_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY)))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY)))) and not((ap_const_lv1_0 = exitcond_flatten_reg_1562))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2)))) then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- col_assign_reg_395 assign process. --
col_assign_reg_395_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
col_assign_reg_395 <= col_reg_1618;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2)))) then
col_assign_reg_395 <= ap_const_lv16_0;
end if;
end if;
end process;
-- indvar_flatten_reg_373 assign process. --
indvar_flatten_reg_373_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
indvar_flatten_reg_373 <= indvar_flatten_next_reg_1566;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2)))) then
indvar_flatten_reg_373 <= ap_const_lv32_0;
end if;
end if;
end process;
-- row_reg_384 assign process. --
row_reg_384_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
row_reg_384 <= row_mid2_reg_1571;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2)))) then
row_reg_384 <= ap_const_lv16_0;
end if;
end if;
end process;
-- tmp_6_reg_362 assign process. --
tmp_6_reg_362_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
tmp_6_reg_362 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_9_fu_448_p2))) then
tmp_6_reg_362 <= tmp_7_fu_442_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1 <= exitcond_flatten_reg_1562;
ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2 <= ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1;
ap_reg_ppstg_val_assign_2_reg_1613_pp0_it1 <= val_assign_2_reg_1613;
ap_reg_ppstg_val_assign_2_reg_1613_pp0_it2 <= ap_reg_ppstg_val_assign_2_reg_1613_pp0_it1;
exitcond_flatten_reg_1562 <= exitcond_flatten_fu_506_p2;
window_val_0_1_0_1_load_reg_1514 <= window_val_0_1_0_1_fu_140;
window_val_0_1_1_1_load_reg_1519 <= window_val_0_1_1_1_fu_144;
window_val_0_1_2_1_load_reg_1524 <= window_val_0_1_2_1_fu_148;
window_val_1_1_0_1_load_reg_1529 <= window_val_1_1_0_1_fu_164;
window_val_1_1_1_1_load_reg_1534 <= window_val_1_1_1_1_fu_168;
window_val_1_1_2_1_load_reg_1539 <= window_val_1_1_2_1_fu_172;
window_val_2_1_0_1_load_reg_1544 <= window_val_2_1_0_1_fu_188;
window_val_2_1_1_1_load_reg_1550 <= window_val_2_1_1_1_fu_192;
window_val_2_1_2_1_load_reg_1556 <= window_val_2_1_2_1_fu_196;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_9_fu_448_p2)))) then
bound_reg_1509 <= bound_fu_1355_p2;
tmp_4_reg_1504 <= tmp_4_fu_459_p2;
tmp_s_reg_1499 <= tmp_s_fu_454_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond_flatten_fu_506_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
col_reg_1618 <= col_fu_635_p2;
row_mid2_reg_1571 <= row_mid2_fu_581_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY)))))) then
dx_1_reg_1688 <= dx_1_fu_922_p2;
dy_1_reg_1695 <= dy_1_fu_984_p2;
tmp_24_reg_1683 <= tmp_24_fu_848_p2;
tmp_38_2_reg_1702 <= tmp_38_2_fu_1043_p2;
tmp_46_2_reg_1707 <= tmp_46_2_fu_1065_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
height_read_reg_1361 <= height;
tmp_1_cast_reg_1377(15 downto 0) <= tmp_1_cast_fu_438_p1(15 downto 0);
tmp_cast_reg_1372(15 downto 0) <= tmp_cast_fu_434_p1(15 downto 0);
width_read_reg_1366 <= width;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))))) then
icmp_reg_1732 <= icmp_fu_1342_p2;
tmp_30_reg_1727 <= tmp_30_fu_1324_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
indvar_flatten_next_reg_1566 <= indvar_flatten_next_fu_511_p2;
window_val_0_1_0_1_fu_140 <= window_val_0_1_0_fu_152;
window_val_0_1_1_1_fu_144 <= window_val_0_1_1_fu_156;
window_val_0_1_2_1_fu_148 <= window_val_0_1_2_fu_160;
window_val_1_1_0_1_fu_164 <= window_val_1_1_0_fu_176;
window_val_1_1_1_1_fu_168 <= window_val_1_1_1_fu_180;
window_val_1_1_2_1_fu_172 <= window_val_1_1_2_fu_184;
window_val_2_1_0_1_fu_188 <= window_val_2_1_0_fu_200;
window_val_2_1_1_1_fu_192 <= window_val_2_1_1_fu_204;
window_val_2_1_2_1_fu_196 <= window_val_2_1_2_fu_208;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_flatten_fu_506_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
line_buffers_val_1_addr_1_reg_1596 <= tmp_31_cast_fu_618_p1(13 - 1 downto 0);
line_buffers_val_1_addr_reg_1591 <= tmp_3_fu_602_p1(13 - 1 downto 0);
line_buffers_val_2_addr_1_reg_1607 <= tmp_31_cast_fu_618_p1(13 - 1 downto 0);
line_buffers_val_2_addr_reg_1602 <= tmp_3_fu_602_p1(13 - 1 downto 0);
tmp_31_cast_reg_1586 <= tmp_31_cast_fu_618_p1;
tmp_3_reg_1576(15 downto 0) <= tmp_3_fu_602_p1(15 downto 0);
tmp_reg_1581 <= tmp_fu_608_p1;
val_assign_2_reg_1613 <= val_assign_2_fu_629_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))))) then
line_buffers_val_1_addr_2_reg_1628 <= tmp_32_cast5_fu_646_p1(13 - 1 downto 0);
line_buffers_val_2_addr_2_reg_1633 <= tmp_32_cast5_fu_646_p1(13 - 1 downto 0);
tmp_14_reg_1643 <= tmp_14_fu_705_p2;
tmp_22_reg_1648 <= tmp_22_fu_727_p2;
tmp_32_cast5_reg_1623 <= tmp_32_cast5_fu_646_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY)))))) then
p_1_reg_1737 <= p_1_fu_1348_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond_flatten_fu_506_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))))) then
reg_429 <= src_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
tmp2_reg_1717 <= tmp2_fu_1255_p2;
tmp4_reg_1722 <= tmp4_fu_1261_p2;
tmp_26_reg_1712 <= tmp_26_fu_1134_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY)))))) then
window_val_0_1_0_fu_152 <= window_val_0_2_0_reg_1638;
window_val_0_1_1_fu_156 <= window_val_0_2_1_reg_1661;
window_val_0_1_2_fu_160 <= line_buffers_val_1_q1;
window_val_0_1_2_load_reg_1673 <= window_val_0_1_2_fu_160;
window_val_1_1_2_fu_184 <= line_buffers_val_2_q1;
window_val_2_1_0_fu_200 <= reg_429;
window_val_2_1_1_fu_204 <= window_val_2_2_1_reg_1653;
window_val_2_1_2_fu_208 <= src_TDATA;
window_val_2_1_2_load_reg_1678 <= window_val_2_1_2_fu_208;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))))) then
window_val_0_2_0_reg_1638 <= line_buffers_val_1_q0;
window_val_0_2_1_reg_1661 <= line_buffers_val_1_q1;
window_val_1_1_0_fu_176 <= line_buffers_val_2_q0;
window_val_1_1_1_fu_180 <= line_buffers_val_2_q1;
window_val_1_2_1_reg_1667 <= line_buffers_val_2_q1;
window_val_2_2_1_reg_1653 <= src_TDATA;
end if;
end if;
end process;
tmp_cast_reg_1372(16) <= '0';
tmp_1_cast_reg_1377(16) <= '0';
tmp_3_reg_1576(63 downto 16) <= "000000000000000000000000000000000000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, exitcond_flatten_fu_506_p2, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_bdd_137, tmp_9_fu_448_p2, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_lv1_0 = tmp_9_fu_448_p2))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if ((not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_flatten_fu_506_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_3;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_flatten_fu_506_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st11_fsm_5;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg1_fsm_3 =>
if ((not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_4;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st11_fsm_5;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_3;
end if;
when ap_ST_pp0_stg2_fsm_4 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_4;
end if;
when ap_ST_st11_fsm_5 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
abs1_1_cast_cast_fu_1267_p1 <= std_logic_vector(resize(signed(tmp_26_reg_1712),14));
abs1_2_cast_fu_1240_p1 <= std_logic_vector(resize(signed(abs1_2_fu_1232_p3),12));
abs1_2_fu_1232_p3 <=
dx_2_fu_1153_p2 when (abscond1_2_fu_1226_p2(0) = '1') else
neg1_2_fu_1220_p2;
abs1_cast_fu_844_p1 <= std_logic_vector(resize(signed(abs1_fu_836_p3),12));
abs1_fu_836_p3 <=
dx_fu_755_p2 when (abscond1_fu_830_p2(0) = '1') else
neg1_fu_824_p2;
abs_1_cast_cast_fu_1120_p1 <= std_logic_vector(resize(signed(tmp_25_fu_1113_p3),14));
abs_2_cast_fu_1216_p1 <= std_logic_vector(resize(signed(abs_2_fu_1208_p3),12));
abs_2_fu_1208_p3 <=
dy_2_fu_1190_p2 when (abscond_2_fu_1202_p2(0) = '1') else
neg_2_fu_1196_p2;
abs_cast_fu_820_p1 <= std_logic_vector(resize(signed(abs_fu_812_p3),12));
abs_fu_812_p3 <=
dy_fu_794_p2 when (abscond_fu_806_p2(0) = '1') else
neg_fu_800_p2;
abscond1_1_fu_1129_p2 <= "1" when (signed(dx_1_reg_1688) > signed(ap_const_lv11_0)) else "0";
abscond1_2_fu_1226_p2 <= "1" when (signed(dx_2_fu_1153_p2) > signed(ap_const_lv11_0)) else "0";
abscond1_fu_830_p2 <= "1" when (signed(dx_fu_755_p2) > signed(ap_const_lv11_0)) else "0";
abscond_1_fu_1108_p2 <= "1" when (signed(dy_1_reg_1695) > signed(ap_const_lv11_0)) else "0";
abscond_2_fu_1202_p2 <= "1" when (signed(dy_2_fu_1190_p2) > signed(ap_const_lv11_0)) else "0";
abscond_fu_806_p2 <= "1" when (signed(dy_fu_794_p2) > signed(ap_const_lv11_0)) else "0";
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st11_fsm_5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_5)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st11_fsm_5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_5)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_100 assign process. --
ap_sig_bdd_100_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_100 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_1030 assign process. --
ap_sig_bdd_1030_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1030 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_110 assign process. --
ap_sig_bdd_110_assign_proc : process(src_TVALID, exitcond_flatten_fu_506_p2)
begin
ap_sig_bdd_110 <= ((src_TVALID = ap_const_logic_0) and (exitcond_flatten_fu_506_p2 = ap_const_lv1_0));
end process;
-- ap_sig_bdd_132 assign process. --
ap_sig_bdd_132_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_132 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_137 assign process. --
ap_sig_bdd_137_assign_proc : process(src_TVALID, exitcond_flatten_reg_1562)
begin
ap_sig_bdd_137 <= ((src_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_163 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_24 assign process. --
ap_sig_bdd_24_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_100)
begin
if (ap_sig_bdd_100) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_pp0_stg1_fsm_3 assign process. --
ap_sig_cseq_ST_pp0_stg1_fsm_3_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_pp0_stg1_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg1_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_pp0_stg2_fsm_4 assign process. --
ap_sig_cseq_ST_pp0_stg2_fsm_4_assign_proc : process(ap_sig_bdd_132)
begin
if (ap_sig_bdd_132) then
ap_sig_cseq_ST_pp0_stg2_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg2_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_5 assign process. --
ap_sig_cseq_ST_st11_fsm_5_assign_proc : process(ap_sig_bdd_1030)
begin
if (ap_sig_bdd_1030) then
ap_sig_cseq_ST_st11_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24)
begin
if (ap_sig_bdd_24) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_163)
begin
if (ap_sig_bdd_163) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_dest_TREADY assign process. --
ap_sig_ioackin_dest_TREADY_assign_proc : process(dest_TREADY, ap_reg_ioackin_dest_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_dest_TREADY)) then
ap_sig_ioackin_dest_TREADY <= dest_TREADY;
else
ap_sig_ioackin_dest_TREADY <= ap_const_logic_1;
end if;
end process;
bound_fu_1355_p0 <= bound_fu_1355_p00(16 - 1 downto 0);
bound_fu_1355_p00 <= std_logic_vector(resize(unsigned(width_read_reg_1366),32));
bound_fu_1355_p1 <= bound_fu_1355_p10(16 - 1 downto 0);
bound_fu_1355_p10 <= std_logic_vector(resize(unsigned(height_read_reg_1361),32));
col_assign_cast_fu_598_p1 <= std_logic_vector(resize(unsigned(col_assign_mid2_fu_573_p3),17));
col_assign_mid2_fu_573_p3 <=
ap_const_lv16_0 when (exitcond_fu_568_p2(0) = '1') else
col_assign_phi_fu_399_p4;
-- col_assign_phi_fu_399_p4 assign process. --
col_assign_phi_fu_399_p4_assign_proc : process(col_assign_reg_395, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, col_reg_1618)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
col_assign_phi_fu_399_p4 <= col_reg_1618;
else
col_assign_phi_fu_399_p4 <= col_assign_reg_395;
end if;
end process;
col_fu_635_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(col_assign_mid2_fu_573_p3));
-- dest_TDATA assign process. --
dest_TDATA_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3, p_1_fu_1348_p3, p_1_reg_1737)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137))))) then
dest_TDATA <= p_1_reg_1737;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137)))) then
dest_TDATA <= p_1_fu_1348_p3;
else
dest_TDATA <= "XXXXXXXX";
end if;
end process;
dest_TDEST <= ap_const_lv1_0;
dest_TID <= ap_const_lv1_0;
dest_TKEEP <= ap_const_lv1_1;
-- dest_TLAST assign process. --
dest_TLAST_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_reg_ppstg_val_assign_2_reg_1613_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137)))) then
dest_TLAST <= ap_reg_ppstg_val_assign_2_reg_1613_pp0_it2;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110))))) then
dest_TLAST <= ap_const_lv1_0;
else
dest_TLAST <= "X";
end if;
end process;
dest_TSTRB <= ap_const_lv1_0;
dest_TUSER <= ap_const_lv1_0;
-- dest_TVALID assign process. --
dest_TVALID_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3, ap_reg_ioackin_dest_TREADY)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137)) and (ap_const_logic_0 = ap_reg_ioackin_dest_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110)) and (ap_const_logic_0 = ap_reg_ioackin_dest_TREADY)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137)) and (ap_const_logic_0 = ap_reg_ioackin_dest_TREADY)))) then
dest_TVALID <= ap_const_logic_1;
else
dest_TVALID <= ap_const_logic_0;
end if;
end process;
dx_1_fu_922_p2 <= std_logic_vector(unsigned(tmp_39_1_fu_916_p2) + unsigned(tmp_35_1_cast7_fu_888_p1));
dx_2_fu_1153_p2 <= std_logic_vector(unsigned(tmp_39_2_fu_1148_p2) + unsigned(tmp_35_2_cast5_fu_1144_p1));
dx_fu_755_p2 <= std_logic_vector(unsigned(tmp_16_fu_750_p2) + unsigned(tmp_26_cast9_fu_746_p1));
dy_1_fu_984_p2 <= std_logic_vector(unsigned(tmp_47_1_fu_978_p2) - unsigned(tmp_43_1_cast_fu_948_p1));
dy_2_fu_1190_p2 <= std_logic_vector(unsigned(tmp_47_2_fu_1184_p2) - unsigned(tmp_43_2_cast_fu_1177_p1));
dy_fu_794_p2 <= std_logic_vector(unsigned(tmp_23_fu_788_p2) - unsigned(tmp_34_cast_fu_781_p1));
exitcond_flatten_fu_506_p2 <= "1" when (indvar_flatten_phi_fu_377_p4 = bound_reg_1509) else "0";
exitcond_fu_568_p2 <= "1" when (col_assign_phi_fu_399_p4 = width_read_reg_1366) else "0";
icmp_fu_1342_p2 <= "1" when (signed(tmp_33_fu_1332_p4) > signed(ap_const_lv4_0)) else "0";
indvar_flatten_next_fu_511_p2 <= std_logic_vector(unsigned(indvar_flatten_phi_fu_377_p4) + unsigned(ap_const_lv32_1));
-- indvar_flatten_phi_fu_377_p4 assign process. --
indvar_flatten_phi_fu_377_p4_assign_proc : process(indvar_flatten_reg_373, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, indvar_flatten_next_reg_1566)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
indvar_flatten_phi_fu_377_p4 <= indvar_flatten_next_reg_1566;
else
indvar_flatten_phi_fu_377_p4 <= indvar_flatten_reg_373;
end if;
end process;
-- line_buffers_val_0_address0 assign process. --
line_buffers_val_0_address0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, tmp_3_reg_1576, tmp_32_cast5_reg_1623, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_0_address0 <= tmp_32_cast5_reg_1623(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_0_address0 <= tmp_3_reg_1576(13 - 1 downto 0);
else
line_buffers_val_0_address0 <= "XXXXXXXXXXXXX";
end if;
else
line_buffers_val_0_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
line_buffers_val_0_address1 <= tmp_31_cast_reg_1586(13 - 1 downto 0);
-- line_buffers_val_0_ce0 assign process. --
line_buffers_val_0_ce0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_0_ce0 <= ap_const_logic_1;
else
line_buffers_val_0_ce0 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_0_ce1 assign process. --
line_buffers_val_0_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2)))))) then
line_buffers_val_0_ce1 <= ap_const_logic_1;
else
line_buffers_val_0_ce1 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_0_d0 assign process. --
line_buffers_val_0_d0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_cseq_ST_pp0_stg1_fsm_3, line_buffers_val_1_q0, line_buffers_val_1_q1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_0_d0 <= line_buffers_val_1_q1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_0_d0 <= line_buffers_val_1_q0;
else
line_buffers_val_0_d0 <= "XXXXXXXX";
end if;
else
line_buffers_val_0_d0 <= "XXXXXXXX";
end if;
end process;
line_buffers_val_0_d1 <= line_buffers_val_1_q1;
-- line_buffers_val_0_we0 assign process. --
line_buffers_val_0_we0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_0_we0 <= ap_const_logic_1;
else
line_buffers_val_0_we0 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_0_we1 assign process. --
line_buffers_val_0_we1_assign_proc : process(ap_reg_ppiten_pp0_it0, exitcond_flatten_reg_1562, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_0_we1 <= ap_const_logic_1;
else
line_buffers_val_0_we1 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_1_address0 assign process. --
line_buffers_val_1_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, tmp_3_fu_602_p1, line_buffers_val_1_addr_reg_1591, line_buffers_val_1_addr_1_reg_1596, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_1_address0 <= line_buffers_val_1_addr_1_reg_1596;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_1_address0 <= line_buffers_val_1_addr_reg_1591;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2)) then
line_buffers_val_1_address0 <= tmp_3_fu_602_p1(13 - 1 downto 0);
else
line_buffers_val_1_address0 <= "XXXXXXXXXXXXX";
end if;
else
line_buffers_val_1_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- line_buffers_val_1_address1 assign process. --
line_buffers_val_1_address1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, tmp_31_cast_fu_618_p1, tmp_32_cast5_fu_646_p1, ap_sig_cseq_ST_pp0_stg1_fsm_3, line_buffers_val_1_addr_2_reg_1628)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_1_address1 <= line_buffers_val_1_addr_2_reg_1628;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_1_address1 <= tmp_32_cast5_fu_646_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2)) then
line_buffers_val_1_address1 <= tmp_31_cast_fu_618_p1(13 - 1 downto 0);
else
line_buffers_val_1_address1 <= "XXXXXXXXXXXXX";
end if;
else
line_buffers_val_1_address1 <= "XXXXXXXXXXXXX";
end if;
end process;
-- line_buffers_val_1_ce0 assign process. --
line_buffers_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_1_ce0 <= ap_const_logic_1;
else
line_buffers_val_1_ce0 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_1_ce1 assign process. --
line_buffers_val_1_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_1_ce1 <= ap_const_logic_1;
else
line_buffers_val_1_ce1 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_1_d0 assign process. --
line_buffers_val_1_d0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_cseq_ST_pp0_stg1_fsm_3, window_val_1_2_1_reg_1667, line_buffers_val_2_q0)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_1_d0 <= window_val_1_2_1_reg_1667;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_1_d0 <= line_buffers_val_2_q0;
else
line_buffers_val_1_d0 <= "XXXXXXXX";
end if;
else
line_buffers_val_1_d0 <= "XXXXXXXX";
end if;
end process;
line_buffers_val_1_d1 <= line_buffers_val_2_q1;
-- line_buffers_val_1_we0 assign process. --
line_buffers_val_1_we0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_1_we0 <= ap_const_logic_1;
else
line_buffers_val_1_we0 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_1_we1 assign process. --
line_buffers_val_1_we1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))))) then
line_buffers_val_1_we1 <= ap_const_logic_1;
else
line_buffers_val_1_we1 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_2_address0 assign process. --
line_buffers_val_2_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, tmp_3_fu_602_p1, line_buffers_val_2_addr_reg_1602, line_buffers_val_2_addr_1_reg_1607, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_2_address0 <= line_buffers_val_2_addr_1_reg_1607;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_2_address0 <= line_buffers_val_2_addr_reg_1602;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2)) then
line_buffers_val_2_address0 <= tmp_3_fu_602_p1(13 - 1 downto 0);
else
line_buffers_val_2_address0 <= "XXXXXXXXXXXXX";
end if;
else
line_buffers_val_2_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- line_buffers_val_2_address1 assign process. --
line_buffers_val_2_address1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, tmp_31_cast_fu_618_p1, tmp_32_cast5_fu_646_p1, ap_sig_cseq_ST_pp0_stg1_fsm_3, line_buffers_val_2_addr_2_reg_1633)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_2_address1 <= line_buffers_val_2_addr_2_reg_1633;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_2_address1 <= tmp_32_cast5_fu_646_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2)) then
line_buffers_val_2_address1 <= tmp_31_cast_fu_618_p1(13 - 1 downto 0);
else
line_buffers_val_2_address1 <= "XXXXXXXXXXXXX";
end if;
else
line_buffers_val_2_address1 <= "XXXXXXXXXXXXX";
end if;
end process;
-- line_buffers_val_2_ce0 assign process. --
line_buffers_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_2_ce0 <= ap_const_logic_1;
else
line_buffers_val_2_ce0 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_2_ce1 assign process. --
line_buffers_val_2_ce1_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_2_ce1 <= ap_const_logic_1;
else
line_buffers_val_2_ce1 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_2_d0 assign process. --
line_buffers_val_2_d0_assign_proc : process(reg_429, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_cseq_ST_pp0_stg1_fsm_3, window_val_2_2_1_reg_1653)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4)) then
line_buffers_val_2_d0 <= window_val_2_2_1_reg_1653;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3)) then
line_buffers_val_2_d0 <= reg_429;
else
line_buffers_val_2_d0 <= "XXXXXXXX";
end if;
else
line_buffers_val_2_d0 <= "XXXXXXXX";
end if;
end process;
line_buffers_val_2_d1 <= src_TDATA;
-- line_buffers_val_2_we0 assign process. --
line_buffers_val_2_we0_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
line_buffers_val_2_we0 <= ap_const_logic_1;
else
line_buffers_val_2_we0 <= ap_const_logic_0;
end if;
end process;
-- line_buffers_val_2_we1 assign process. --
line_buffers_val_2_we1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))))) then
line_buffers_val_2_we1 <= ap_const_logic_1;
else
line_buffers_val_2_we1 <= ap_const_logic_0;
end if;
end process;
my_video_filter_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
neg1_1_fu_1124_p2 <= std_logic_vector(unsigned(ap_const_lv11_0) - unsigned(dx_1_reg_1688));
neg1_2_fu_1220_p2 <= std_logic_vector(unsigned(ap_const_lv11_0) - unsigned(dx_2_fu_1153_p2));
neg1_fu_824_p2 <= std_logic_vector(unsigned(ap_const_lv11_0) - unsigned(dx_fu_755_p2));
neg_1_fu_1103_p2 <= std_logic_vector(unsigned(ap_const_lv11_0) - unsigned(dy_1_reg_1695));
neg_2_fu_1196_p2 <= std_logic_vector(unsigned(ap_const_lv11_0) - unsigned(dy_2_fu_1190_p2));
neg_fu_800_p2 <= std_logic_vector(unsigned(ap_const_lv11_0) - unsigned(dy_fu_794_p2));
p_1_fu_1348_p3 <=
ap_const_lv8_FF when (icmp_reg_1732(0) = '1') else
tmp_30_reg_1727;
p_neg_fu_1292_p2 <= std_logic_vector(unsigned(ap_const_lv14_0) - unsigned(tmp_15_fu_1278_p2));
row_1_fu_562_p2 <= std_logic_vector(unsigned(ap_const_lv16_1) + unsigned(row_phi_fu_388_p4));
row_cast_fu_589_p1 <= std_logic_vector(resize(unsigned(row_mid2_fu_581_p3),17));
row_mid2_fu_581_p3 <=
row_1_fu_562_p2 when (exitcond_fu_568_p2(0) = '1') else
row_phi_fu_388_p4;
-- row_phi_fu_388_p4 assign process. --
row_phi_fu_388_p4_assign_proc : process(row_reg_384, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, row_mid2_reg_1571)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = exitcond_flatten_reg_1562))) then
row_phi_fu_388_p4 <= row_mid2_reg_1571;
else
row_phi_fu_388_p4 <= row_reg_384;
end if;
end process;
-- src_TREADY assign process. --
src_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_reg_ppiten_pp0_it0, exitcond_flatten_fu_506_p2, ap_sig_bdd_110, ap_reg_ppiten_pp0_it1, exitcond_flatten_reg_1562, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1, ap_sig_ioackin_dest_TREADY, ap_reg_ppiten_pp0_it2, ap_sig_cseq_ST_pp0_stg2_fsm_4, ap_sig_bdd_137, ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2, ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond_flatten_fu_506_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_110) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_4) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it1) and (ap_const_logic_0 = ap_sig_ioackin_dest_TREADY))))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_lv1_0 = exitcond_flatten_reg_1562) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_bdd_137) or ((ap_const_logic_0 = ap_sig_ioackin_dest_TREADY) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_flatten_reg_1562_pp0_it2))))))) then
src_TREADY <= ap_const_logic_1;
else
src_TREADY <= ap_const_logic_0;
end if;
end process;
tmp2_cast_cast_fu_1270_p1 <= std_logic_vector(resize(signed(tmp2_reg_1717),14));
tmp2_fu_1255_p2 <= std_logic_vector(signed(abs1_2_cast_fu_1240_p1) + signed(abs_2_cast_fu_1216_p1));
tmp3_fu_1273_p2 <= std_logic_vector(unsigned(tmp4_reg_1722) + unsigned(abs1_1_cast_cast_fu_1267_p1));
tmp4_fu_1261_p2 <= std_logic_vector(signed(tmp_13_cast_fu_1251_p1) + signed(abs_1_cast_cast_fu_1120_p1));
tmp_10_fu_659_p3 <= (window_val_1_1_0_1_load_reg_1529 & ap_const_lv1_0);
tmp_11_fu_670_p3 <= (line_buffers_val_2_q0 & ap_const_lv1_0);
tmp_12_fu_689_p2 <= std_logic_vector(unsigned(tmp_20_cast_fu_655_p1) - unsigned(tmp_19_cast_fu_652_p1));
tmp_13_cast_fu_1251_p1 <= std_logic_vector(resize(signed(tmp_31_fu_1244_p3),14));
tmp_13_fu_699_p2 <= std_logic_vector(signed(tmp_27_cast_fu_695_p1) - signed(tmp_22_cast_fu_666_p1));
tmp_14_fu_705_p2 <= std_logic_vector(unsigned(tmp_24_cast_fu_678_p1) + unsigned(tmp_13_fu_699_p2));
tmp_15_fu_1278_p2 <= std_logic_vector(unsigned(tmp3_fu_1273_p2) + unsigned(tmp2_cast_cast_fu_1270_p1));
tmp_16_fu_750_p2 <= std_logic_vector(unsigned(tmp_14_reg_1643) - unsigned(tmp_25_cast_fu_743_p1));
tmp_17_fu_761_p3 <= (window_val_0_1_0_fu_152 & ap_const_lv1_0);
tmp_18_fu_624_p2 <= "1" when (col_assign_cast_fu_598_p1 = tmp_4_reg_1504) else "0";
tmp_19_cast_fu_652_p1 <= std_logic_vector(resize(unsigned(window_val_0_1_0_1_load_reg_1514),9));
tmp_19_fu_773_p3 <= (window_val_2_1_0_fu_200 & ap_const_lv1_0);
tmp_1_cast_fu_438_p1 <= std_logic_vector(resize(unsigned(width),17));
tmp_1_fu_593_p2 <= "1" when (row_cast_fu_589_p1 = tmp_s_reg_1499) else "0";
tmp_20_cast_fu_655_p1 <= std_logic_vector(resize(unsigned(line_buffers_val_1_q0),9));
tmp_20_fu_711_p2 <= std_logic_vector(unsigned(tmp_19_cast_fu_652_p1) + unsigned(tmp_20_cast_fu_655_p1));
tmp_21_fu_721_p2 <= std_logic_vector(unsigned(tmp_35_cast_fu_717_p1) - unsigned(tmp_25_cast1_fu_682_p1));
tmp_22_cast_fu_666_p1 <= std_logic_vector(resize(unsigned(tmp_10_fu_659_p3),11));
tmp_22_fu_727_p2 <= std_logic_vector(unsigned(tmp_21_fu_721_p2) - unsigned(tmp_26_cast_fu_685_p1));
tmp_23_fu_788_p2 <= std_logic_vector(unsigned(tmp_32_cast_fu_769_p1) + unsigned(tmp_37_cast_fu_785_p1));
tmp_24_cast_fu_678_p1 <= std_logic_vector(resize(unsigned(tmp_11_fu_670_p3),11));
tmp_24_fu_848_p2 <= std_logic_vector(signed(abs1_cast_fu_844_p1) + signed(abs_cast_fu_820_p1));
tmp_25_cast1_fu_682_p1 <= std_logic_vector(resize(unsigned(window_val_2_1_0_1_load_reg_1544),10));
tmp_25_cast_fu_743_p1 <= std_logic_vector(resize(unsigned(window_val_2_1_0_1_load_reg_1544),11));
tmp_25_fu_1113_p3 <=
dy_1_reg_1695 when (abscond_1_fu_1108_p2(0) = '1') else
neg_1_fu_1103_p2;
tmp_26_cast9_fu_746_p1 <= std_logic_vector(resize(unsigned(reg_429),11));
tmp_26_cast_fu_685_p1 <= std_logic_vector(resize(unsigned(reg_429),10));
tmp_26_fu_1134_p3 <=
dx_1_reg_1688 when (abscond1_1_fu_1129_p2(0) = '1') else
neg1_1_fu_1124_p2;
tmp_27_cast_fu_695_p1 <= std_logic_vector(resize(signed(tmp_12_fu_689_p2),11));
tmp_27_fu_1298_p4 <= p_neg_fu_1292_p2(9 downto 2);
tmp_28_1_cast_fu_854_p1 <= std_logic_vector(resize(unsigned(window_val_0_1_1_1_load_reg_1519),9));
tmp_28_2_cast_fu_990_p1 <= std_logic_vector(resize(unsigned(window_val_0_1_2_1_load_reg_1524),9));
tmp_28_fu_1308_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(tmp_27_fu_1298_p4));
tmp_29_1_cast_fu_857_p1 <= std_logic_vector(resize(unsigned(window_val_0_2_1_reg_1661),9));
tmp_29_2_cast_fu_993_p1 <= std_logic_vector(resize(unsigned(line_buffers_val_1_q1),9));
tmp_29_fu_1314_p4 <= tmp_15_fu_1278_p2(9 downto 2);
tmp_30_fu_1324_p3 <=
tmp_28_fu_1308_p2 when (tmp_32_fu_1284_p3(0) = '1') else
tmp_29_fu_1314_p4;
tmp_31_1_cast_fu_867_p1 <= std_logic_vector(resize(unsigned(tmp_31_1_fu_860_p3),11));
tmp_31_1_fu_860_p3 <= (window_val_1_1_1_1_load_reg_1534 & ap_const_lv1_0);
tmp_31_2_cast_fu_1004_p1 <= std_logic_vector(resize(unsigned(tmp_31_2_fu_997_p3),11));
tmp_31_2_fu_997_p3 <= (window_val_1_1_2_1_load_reg_1539 & ap_const_lv1_0);
tmp_31_cast_fu_618_p1 <= std_logic_vector(resize(signed(tmp_5_fu_612_p2),64));
tmp_31_fu_1244_p3 <= (tmp_24_reg_1683 & ap_const_lv1_0);
tmp_32_cast5_fu_646_p1 <= std_logic_vector(resize(signed(tmp_8_fu_641_p2),64));
tmp_32_cast_fu_769_p1 <= std_logic_vector(resize(unsigned(tmp_17_fu_761_p3),11));
tmp_32_fu_1284_p3 <= tmp_15_fu_1278_p2(13 downto 13);
tmp_33_1_cast_fu_878_p1 <= std_logic_vector(resize(unsigned(tmp_33_1_fu_871_p3),11));
tmp_33_1_fu_871_p3 <= (window_val_1_2_1_reg_1667 & ap_const_lv1_0);
tmp_33_2_cast_fu_1016_p1 <= std_logic_vector(resize(unsigned(tmp_33_2_fu_1008_p3),11));
tmp_33_2_fu_1008_p3 <= (line_buffers_val_2_q1 & ap_const_lv1_0);
tmp_33_fu_1332_p4 <= tmp_15_fu_1278_p2(13 downto 10);
tmp_34_1_cast8_fu_882_p1 <= std_logic_vector(resize(unsigned(window_val_2_1_1_1_load_reg_1550),10));
tmp_34_1_cast_fu_885_p1 <= std_logic_vector(resize(unsigned(window_val_2_1_1_1_load_reg_1550),11));
tmp_34_2_cast6_fu_1020_p1 <= std_logic_vector(resize(unsigned(window_val_2_1_2_1_load_reg_1556),10));
tmp_34_2_cast_fu_1141_p1 <= std_logic_vector(resize(unsigned(window_val_2_1_2_1_load_reg_1556),11));
tmp_34_cast_fu_781_p1 <= std_logic_vector(resize(unsigned(tmp_19_fu_773_p3),11));
tmp_35_1_cast7_fu_888_p1 <= std_logic_vector(resize(unsigned(window_val_2_2_1_reg_1653),11));
tmp_35_1_cast_fu_891_p1 <= std_logic_vector(resize(unsigned(window_val_2_2_1_reg_1653),10));
tmp_35_2_cast5_fu_1144_p1 <= std_logic_vector(resize(unsigned(reg_429),11));
tmp_35_2_cast_fu_1023_p1 <= std_logic_vector(resize(unsigned(src_TDATA),10));
tmp_35_cast_fu_717_p1 <= std_logic_vector(resize(unsigned(tmp_20_fu_711_p2),10));
tmp_36_1_cast_fu_900_p1 <= std_logic_vector(resize(signed(tmp_36_1_fu_894_p2),11));
tmp_36_1_fu_894_p2 <= std_logic_vector(unsigned(tmp_29_1_cast_fu_857_p1) - unsigned(tmp_28_1_cast_fu_854_p1));
tmp_36_2_cast_fu_1033_p1 <= std_logic_vector(resize(signed(tmp_36_2_fu_1027_p2),11));
tmp_36_2_fu_1027_p2 <= std_logic_vector(unsigned(tmp_29_2_cast_fu_993_p1) - unsigned(tmp_28_2_cast_fu_990_p1));
tmp_37_1_fu_904_p2 <= std_logic_vector(signed(tmp_36_1_cast_fu_900_p1) - signed(tmp_31_1_cast_fu_867_p1));
tmp_37_2_fu_1037_p2 <= std_logic_vector(signed(tmp_36_2_cast_fu_1033_p1) - signed(tmp_31_2_cast_fu_1004_p1));
tmp_37_cast_fu_785_p1 <= std_logic_vector(resize(signed(tmp_22_reg_1648),11));
tmp_38_1_fu_910_p2 <= std_logic_vector(unsigned(tmp_33_1_cast_fu_878_p1) + unsigned(tmp_37_1_fu_904_p2));
tmp_38_2_fu_1043_p2 <= std_logic_vector(unsigned(tmp_33_2_cast_fu_1016_p1) + unsigned(tmp_37_2_fu_1037_p2));
tmp_39_1_fu_916_p2 <= std_logic_vector(unsigned(tmp_38_1_fu_910_p2) - unsigned(tmp_34_1_cast_fu_885_p1));
tmp_39_2_fu_1148_p2 <= std_logic_vector(unsigned(tmp_38_2_reg_1702) - unsigned(tmp_34_2_cast_fu_1141_p1));
tmp_3_fu_602_p1 <= std_logic_vector(resize(unsigned(col_assign_mid2_fu_573_p3),64));
tmp_41_1_cast_fu_936_p1 <= std_logic_vector(resize(unsigned(tmp_41_1_fu_928_p3),11));
tmp_41_1_fu_928_p3 <= (window_val_0_1_1_fu_156 & ap_const_lv1_0);
tmp_41_2_cast_fu_1166_p1 <= std_logic_vector(resize(unsigned(tmp_41_2_fu_1159_p3),11));
tmp_41_2_fu_1159_p3 <= (window_val_0_1_2_load_reg_1673 & ap_const_lv1_0);
tmp_43_1_cast_fu_948_p1 <= std_logic_vector(resize(unsigned(tmp_43_1_fu_940_p3),11));
tmp_43_1_fu_940_p3 <= (window_val_2_1_1_fu_204 & ap_const_lv1_0);
tmp_43_2_cast_fu_1177_p1 <= std_logic_vector(resize(unsigned(tmp_43_2_fu_1170_p3),11));
tmp_43_2_fu_1170_p3 <= (window_val_2_1_2_load_reg_1678 & ap_const_lv1_0);
tmp_44_1_cast_fu_958_p1 <= std_logic_vector(resize(unsigned(tmp_44_1_fu_952_p2),10));
tmp_44_1_fu_952_p2 <= std_logic_vector(unsigned(tmp_28_1_cast_fu_854_p1) + unsigned(tmp_29_1_cast_fu_857_p1));
tmp_44_2_cast_fu_1055_p1 <= std_logic_vector(resize(unsigned(tmp_44_2_fu_1049_p2),10));
tmp_44_2_fu_1049_p2 <= std_logic_vector(unsigned(tmp_28_2_cast_fu_990_p1) + unsigned(tmp_29_2_cast_fu_993_p1));
tmp_45_1_fu_962_p2 <= std_logic_vector(unsigned(tmp_44_1_cast_fu_958_p1) - unsigned(tmp_34_1_cast8_fu_882_p1));
tmp_45_2_fu_1059_p2 <= std_logic_vector(unsigned(tmp_44_2_cast_fu_1055_p1) - unsigned(tmp_34_2_cast6_fu_1020_p1));
tmp_46_1_cast_fu_974_p1 <= std_logic_vector(resize(signed(tmp_46_1_fu_968_p2),11));
tmp_46_1_fu_968_p2 <= std_logic_vector(unsigned(tmp_45_1_fu_962_p2) - unsigned(tmp_35_1_cast_fu_891_p1));
tmp_46_2_cast_fu_1181_p1 <= std_logic_vector(resize(signed(tmp_46_2_reg_1707),11));
tmp_46_2_fu_1065_p2 <= std_logic_vector(unsigned(tmp_45_2_fu_1059_p2) - unsigned(tmp_35_2_cast_fu_1023_p1));
tmp_47_1_fu_978_p2 <= std_logic_vector(unsigned(tmp_41_1_cast_fu_936_p1) + unsigned(tmp_46_1_cast_fu_974_p1));
tmp_47_2_fu_1184_p2 <= std_logic_vector(unsigned(tmp_41_2_cast_fu_1166_p1) + unsigned(tmp_46_2_cast_fu_1181_p1));
tmp_4_fu_459_p2 <= std_logic_vector(unsigned(tmp_1_cast_reg_1377) + unsigned(ap_const_lv17_1FFFF));
tmp_5_fu_612_p2 <= std_logic_vector(unsigned(ap_const_lv14_780) + unsigned(tmp_fu_608_p1));
tmp_7_fu_442_p2 <= std_logic_vector(unsigned(tmp_6_reg_362) + unsigned(ap_const_lv2_1));
tmp_8_fu_641_p2 <= std_logic_vector(unsigned(ap_const_lv14_F00) + unsigned(tmp_reg_1581));
tmp_9_fu_448_p2 <= "1" when (tmp_6_reg_362 = ap_const_lv2_2) else "0";
tmp_cast_fu_434_p1 <= std_logic_vector(resize(unsigned(height),17));
tmp_fu_608_p1 <= col_assign_mid2_fu_573_p3(14 - 1 downto 0);
tmp_s_fu_454_p2 <= std_logic_vector(unsigned(tmp_cast_reg_1372) + unsigned(ap_const_lv17_1FFFF));
val_assign_2_fu_629_p2 <= (tmp_1_fu_593_p2 and tmp_18_fu_624_p2);
end behav;
|
gpl-3.0
|
274b4dc7307d678df7a9a7648b7e50e4
| 0.628041 | 2.596776 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/sld_signaltap/_primary.vhd
| 1 | 7,403 |
library verilog;
use verilog.vl_types.all;
entity sld_signaltap is
generic(
SLD_CURRENT_RESOURCE_WIDTH: integer := 0;
SLD_INVERSION_MASK: string := "0";
SLD_POWER_UP_TRIGGER: integer := 0;
SLD_ADVANCED_TRIGGER_6: string := "NONE";
SLD_ADVANCED_TRIGGER_9: string := "NONE";
SLD_ADVANCED_TRIGGER_7: string := "NONE";
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY: string := "basic";
SLD_STORAGE_QUALIFIER_GAP_RECORD: integer := 0;
SLD_INCREMENTAL_ROUTING: integer := 0;
SLD_STORAGE_QUALIFIER_PIPELINE: integer := 0;
SLD_TRIGGER_IN_ENABLED: integer := 0;
SLD_STATE_BITS : integer := 11;
SLD_STATE_FLOW_USE_GENERATED: integer := 0;
SLD_INVERSION_MASK_LENGTH: integer := 1;
SLD_DATA_BITS : integer := 1;
SLD_BUFFER_FULL_STOP: integer := 1;
SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH: integer := 0;
SLD_ATTRIBUTE_MEM_MODE: string := "OFF";
SLD_STORAGE_QUALIFIER_MODE: string := "OFF";
SLD_STATE_FLOW_MGR_ENTITY: string := "state_flow_mgr_entity.vhd";
SLD_NODE_CRC_LOWORD: integer := 50132;
SLD_ADVANCED_TRIGGER_5: string := "NONE";
SLD_TRIGGER_BITS: integer := 1;
SLD_STORAGE_QUALIFIER_BITS: integer := 1;
SLD_ADVANCED_TRIGGER_10: string := "NONE";
SLD_MEM_ADDRESS_BITS: integer := 7;
SLD_ADVANCED_TRIGGER_ENTITY: string := "basic";
SLD_ADVANCED_TRIGGER_4: string := "NONE";
SLD_TRIGGER_LEVEL: integer := 10;
SLD_ADVANCED_TRIGGER_8: string := "NONE";
SLD_RAM_BLOCK_TYPE: string := "AUTO";
SLD_ADVANCED_TRIGGER_2: string := "NONE";
SLD_ADVANCED_TRIGGER_1: string := "NONE";
SLD_DATA_BIT_CNTR_BITS: integer := 4;
lpm_type : string := "sld_signaltap";
SLD_NODE_CRC_BITS: integer := 32;
SLD_SAMPLE_DEPTH: integer := 16;
SLD_ENABLE_ADVANCED_TRIGGER: integer := 0;
SLD_SEGMENT_SIZE: integer := 0;
SLD_NODE_INFO : integer := 0;
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION: integer := 0;
SLD_NODE_CRC_HIWORD: integer := 41394;
SLD_TRIGGER_LEVEL_PIPELINE: integer := 1;
SLD_ADVANCED_TRIGGER_3: string := "NONE";
ELA_STATUS_BITS : integer := 4;
N_ELA_INSTRS : integer := 8;
SLD_IR_BITS : vl_notype
);
port(
jtag_state_sdr : in vl_logic;
ir_out : out vl_logic_vector;
jtag_state_cdr : in vl_logic;
ir_in : in vl_logic_vector;
tdi : in vl_logic;
acq_trigger_out : out vl_logic_vector;
jtag_state_uir : in vl_logic;
acq_trigger_in : in vl_logic_vector;
trigger_out : out vl_logic;
storage_enable : in vl_logic;
acq_data_out : out vl_logic_vector;
acq_data_in : in vl_logic_vector;
acq_storage_qualifier_in: in vl_logic_vector;
jtag_state_udr : in vl_logic;
tdo : out vl_logic;
crc : in vl_logic_vector;
jtag_state_e1dr : in vl_logic;
raw_tck : in vl_logic;
usr1 : in vl_logic;
acq_clk : in vl_logic;
shift : in vl_logic;
ena : in vl_logic;
clr : in vl_logic;
trigger_in : in vl_logic;
update : in vl_logic;
rti : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SLD_CURRENT_RESOURCE_WIDTH : constant is 1;
attribute mti_svvh_generic_type of SLD_INVERSION_MASK : constant is 1;
attribute mti_svvh_generic_type of SLD_POWER_UP_TRIGGER : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_6 : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_9 : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_7 : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_GAP_RECORD : constant is 1;
attribute mti_svvh_generic_type of SLD_INCREMENTAL_ROUTING : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_PIPELINE : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_IN_ENABLED : constant is 1;
attribute mti_svvh_generic_type of SLD_STATE_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_STATE_FLOW_USE_GENERATED : constant is 1;
attribute mti_svvh_generic_type of SLD_INVERSION_MASK_LENGTH : constant is 1;
attribute mti_svvh_generic_type of SLD_DATA_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_BUFFER_FULL_STOP : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : constant is 1;
attribute mti_svvh_generic_type of SLD_ATTRIBUTE_MEM_MODE : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_MODE : constant is 1;
attribute mti_svvh_generic_type of SLD_STATE_FLOW_MGR_ENTITY : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_CRC_LOWORD : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_5 : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_10 : constant is 1;
attribute mti_svvh_generic_type of SLD_MEM_ADDRESS_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_ENTITY : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_4 : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_LEVEL : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_8 : constant is 1;
attribute mti_svvh_generic_type of SLD_RAM_BLOCK_TYPE : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_2 : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_1 : constant is 1;
attribute mti_svvh_generic_type of SLD_DATA_BIT_CNTR_BITS : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_CRC_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_SAMPLE_DEPTH : constant is 1;
attribute mti_svvh_generic_type of SLD_ENABLE_ADVANCED_TRIGGER : constant is 1;
attribute mti_svvh_generic_type of SLD_SEGMENT_SIZE : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_INFO : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_CRC_HIWORD : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_LEVEL_PIPELINE : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_3 : constant is 1;
attribute mti_svvh_generic_type of ELA_STATUS_BITS : constant is 1;
attribute mti_svvh_generic_type of N_ELA_INSTRS : constant is 1;
attribute mti_svvh_generic_type of SLD_IR_BITS : constant is 3;
end sld_signaltap;
|
bsd-2-clause
|
0d9a9d96b965a6aedab8aa13694294bd
| 0.642847 | 3.569431 | false | false | false | false |
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