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CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_v6/example_design/pulse_regen_v6_top_wrapper.vhd
| 1 | 19,614 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_v6_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_v6_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(1-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(1-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pulse_regen_v6_top_wrapper;
architecture xilinx of pulse_regen_v6_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_v6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pulse_regen_v6_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
52d7f9358044ba63990a338c63636b0f
| 0.475987 | 3.976079 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/alt_eyemon/_primary.vhd
| 1 | 3,086 |
library verilog;
use verilog.vl_types.all;
entity alt_eyemon is
generic(
channel_address_width: integer := 3;
lpm_type : string := "alt_eyemon";
lpm_hint : string := "UNUSED";
avmm_slave_addr_width: integer := 16;
avmm_slave_rdata_width: integer := 16;
avmm_slave_wdata_width: integer := 16;
avmm_master_addr_width: integer := 16;
avmm_master_rdata_width: integer := 16;
avmm_master_wdata_width: integer := 16;
dprio_addr_width: integer := 16;
dprio_data_width: integer := 16;
ireg_chaddr_width: vl_notype;
ireg_wdaddr_width: integer := 2;
ireg_data_width : integer := 16;
ST_IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0);
ST_WRITE : vl_logic_vector(0 to 1) := (Hi0, Hi1);
ST_READ : vl_logic_vector(0 to 1) := (Hi1, Hi0)
);
port(
i_resetn : in vl_logic;
i_avmm_clk : in vl_logic;
i_avmm_saddress : in vl_logic_vector;
i_avmm_sread : in vl_logic;
i_avmm_swrite : in vl_logic;
i_avmm_swritedata: in vl_logic_vector;
o_avmm_sreaddata: out vl_logic_vector;
o_avmm_swaitrequest: out vl_logic;
i_remap_phase : in vl_logic;
i_remap_address : in vl_logic_vector(11 downto 0);
o_quad_address : out vl_logic_vector(8 downto 0);
o_reconfig_busy : out vl_logic;
i_dprio_busy : in vl_logic;
i_dprio_in : in vl_logic_vector;
o_dprio_wren : out vl_logic;
o_dprio_rden : out vl_logic;
o_dprio_addr : out vl_logic_vector;
o_dprio_data : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of avmm_slave_addr_width : constant is 1;
attribute mti_svvh_generic_type of avmm_slave_rdata_width : constant is 1;
attribute mti_svvh_generic_type of avmm_slave_wdata_width : constant is 1;
attribute mti_svvh_generic_type of avmm_master_addr_width : constant is 1;
attribute mti_svvh_generic_type of avmm_master_rdata_width : constant is 1;
attribute mti_svvh_generic_type of avmm_master_wdata_width : constant is 1;
attribute mti_svvh_generic_type of dprio_addr_width : constant is 1;
attribute mti_svvh_generic_type of dprio_data_width : constant is 1;
attribute mti_svvh_generic_type of ireg_chaddr_width : constant is 3;
attribute mti_svvh_generic_type of ireg_wdaddr_width : constant is 1;
attribute mti_svvh_generic_type of ireg_data_width : constant is 1;
attribute mti_svvh_generic_type of ST_IDLE : constant is 1;
attribute mti_svvh_generic_type of ST_WRITE : constant is 1;
attribute mti_svvh_generic_type of ST_READ : constant is 1;
end alt_eyemon;
|
bsd-2-clause
|
1f81f1bddece799aa07921c5c70a7e8f
| 0.616332 | 3.402426 | false | false | false | false |
fpga-logi/logi-hard
|
test_bench/dram_fifo_tb.vhd
| 1 | 13,290 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:31:50 10/29/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/dram_fifo_tb.vhd
-- Project Name: logibone_cam_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dram_fifo
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY dram_fifo_tb IS
END dram_fifo_tb;
ARCHITECTURE behavior OF dram_fifo_tb IS
-- Component Declaration for the Unit Under Test (UUT)
constant test_frequency : natural := 100_000_000 ;
constant test_frequency_mhz : natural := test_frequency/1_000_000;
constant low_speed_test : natural := 0 ;
constant sdram_address_width : natural := 24;
constant sdram_column_bits : natural := 9;
constant sdram_startup_cycles: natural := 10100; -- 100us, plus a little more
constant cycles_per_refresh : natural := (64000*test_frequency_mhz)/8192-1;
constant test_width : natural := sdram_address_width-1; -- each 32-bit word is two 16-bit SDRAM addresses
COMPONENT dram_fifo
generic(CACHE_SIZE : positive := 2048;
FIFO_SIZE : positive := 16_777_216;
sdram_address_width : positive := 24;
SYNC_READ : boolean := true;
SYNC_WRITE : boolean := true;
CACHE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'));
PORT(
clk : IN std_logic;
reset : IN std_logic;
write_fifo : IN std_logic;
read_fifo : IN std_logic;
nb_available : OUT std_logic_vector(31 downto 0);
data_out : OUT std_logic_vector(15 downto 0);
data_in : IN std_logic_vector(15 downto 0);
reset_fifo : IN std_logic;
cmd_ready : IN std_logic;
cmd_enable : OUT std_logic;
cmd_wr : OUT std_logic;
cmd_address : OUT std_logic_vector(22 downto 0);
cmd_byte_enable : OUT std_logic_vector(3 downto 0);
cmd_data_in : OUT std_logic_vector(31 downto 0);
sdram_data_out : IN std_logic_vector(31 downto 0);
sdram_data_ready : IN std_logic
);
END COMPONENT;
component SDRAM_Controller is
generic (
sdram_address_width : natural;
sdram_column_bits : natural;
sdram_startup_cycles: natural;
cycles_per_refresh : natural
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Interface to issue reads or write data
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC; -- is new data ready?
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
end component;
component SDRAM_Controller_v2 is
generic (
sdram_address_width : natural;
sdram_column_bits : natural;
sdram_startup_cycles: natural;
cycles_per_refresh : natural
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Interface to issue reads or write data
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC; -- is new data ready?
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
end component;
component sdram_model is
Port ( CLK : in STD_LOGIC;
CKE : in STD_LOGIC;
CS_N : in STD_LOGIC;
RAS_N : in STD_LOGIC;
CAS_N : in STD_LOGIC;
WE_N : in STD_LOGIC;
BA : in STD_LOGIC_VECTOR (1 downto 0);
DQM : in STD_LOGIC_VECTOR (1 downto 0);
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
DQ : inout STD_LOGIC_VECTOR (15 downto 0));
end component;
component mt48lc16m16a2 is
Port ( Clk : in STD_LOGIC;
Cke : in STD_LOGIC;
Cs_n : in STD_LOGIC;
Ras_n : in STD_LOGIC;
Cas_n : in STD_LOGIC;
We_n : in STD_LOGIC;
Ba : in STD_LOGIC_VECTOR (1 downto 0);
Dqm : in STD_LOGIC_VECTOR (1 downto 0);
Addr : in STD_LOGIC_VECTOR (12 downto 0);
Dq : inout STD_LOGIC_VECTOR (15 downto 0));
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal write_fifo : std_logic := '0';
signal read_fifo : std_logic := '0';
signal data_in, data_out : std_logic_vector(15 downto 0) := (others => '0');
signal reset_fifo : std_logic := '0';
signal sdram_data_in : std_logic_vector(31 downto 0) := (others => '0');
signal sdram_data_ready : std_logic := '0';
--Outputs
signal nb_available : std_logic_vector(31 downto 0);
signal cmd_address : std_logic_vector(sdram_address_width-2 downto 0) := (others => '0');
signal cmd_wr : std_logic := '1';
signal cmd_enable : std_logic;
signal cmd_byte_enable : std_logic_vector(3 downto 0);
signal cmd_data_in : std_logic_vector(31 downto 0);
signal cmd_ready : std_logic;
signal sdram_data_out : std_logic_vector(31 downto 0);
signal data_out_ready : std_logic;
--SDRAM
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CS : std_logic;
signal SDRAM_RAS : std_logic;
signal SDRAM_CAS : std_logic;
signal SDRAM_WE : std_logic;
signal SDRAM_DQM : std_logic_vector(1 downto 0);
signal SDRAM_ADDR : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(15 downto 0) ;
signal sdram_ready : std_logic ;
signal clock_divider : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dram_fifo
GENERIC MAP(CACHE_ADDRESS => X"00000000", FIFO_SIZE => 8_000_000)
PORT MAP (
clk => clk,
reset => reset,
write_fifo => write_fifo,
read_fifo => read_fifo,
nb_available => nb_available,
data_out => data_out,
data_in => data_in,
reset_fifo => reset_fifo,
cmd_ready => cmd_ready,
cmd_enable => cmd_enable,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable => cmd_byte_enable,
cmd_data_in => cmd_data_in,
sdram_data_out => sdram_data_out,
sdram_data_ready => sdram_data_ready
);
ctrl_0 : SDRAM_Controller
generic map(
sdram_address_width => sdram_address_width,
sdram_column_bits => sdram_column_bits,
sdram_startup_cycles=> sdram_startup_cycles,
cycles_per_refresh => cycles_per_refresh
)
Port map( clk => clk,
reset => reset,
-- Interface to issue reads or write data
cmd_ready => cmd_ready, -- '1' when a new command will be acted on
cmd_enable => cmd_enable, -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr => cmd_wr, -- Is this a write?
cmd_address => cmd_address, -- address to read/write
cmd_byte_enable => cmd_byte_enable, -- byte masks for the write command
cmd_data_in => cmd_data_in, -- data for the write command
data_out => sdram_data_out, -- word read from SDRAM
data_out_ready => sdram_data_ready, -- is new data ready?
-- SDRAM signals
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CS => SDRAM_CS,
SDRAM_RAS => SDRAM_RAS,
SDRAM_CAS => SDRAM_CAS,
SDRAM_WE => SDRAM_WE,
SDRAM_DQM => SDRAM_DQM,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_BA => SDRAM_BA,
SDRAM_DATA => SDRAM_DQ
);
sdram_0 : sdram_model
Port map( CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
CS_N => SDRAM_CS,
RAS_N => SDRAM_RAS,
CAS_N => SDRAM_CAS,
WE_N => SDRAM_WE,
BA => SDRAM_BA,
DQM => SDRAM_DQM,
ADDR => SDRAM_ADDR,
DQ => SDRAM_DQ
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process(clk, reset)
begin
if reset = '1' then
write_fifo <= '0' ;
data_in <= (others => '0');
clock_divider <= "0001" ;
elsif clk'event and clk = '1' then
clock_divider(3 downto 1) <= clock_divider(2 downto 0);
clock_divider(0) <= clock_divider(1);
if sdram_ready = '1' and clock_divider(0) = '1' then
write_fifo <= '1' ;
else
write_fifo <= '0' ;
end if ;
if write_fifo = '1' then
data_in <= data_in + 1 ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
sdram_ready <= '0' ;
elsif clk'event and clk = '1' then
if cmd_ready = '1' then
sdram_ready <= '1' ;
end if ;
end if ;
end process ;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1' ;
read_fifo <= '0' ;
wait for 100 ns;
reset <= '0' ;
wait for 200 us;
wait until clk = '0' ;
for i in 0 to 320*10 loop
--data_in <= std_logic_vector(to_unsigned(i, 16));
--write_fifo <= '1' ;
wait until clk = '1' ;
--write_fifo <= '0' ;
wait for 80 ns ;
wait until clk = '0' ;
end loop ;
--write_fifo <= '0' ;
for i in 0 to 320*10 loop
read_fifo <= '1' ;
wait until clk = '1' ;
read_fifo <= '0' ;
wait for 30 ns ;
wait until clk = '0' ;
end loop ;
read_fifo <= '0' ;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
385aa7db4e77154fcc3ddc3eb94a9210
| 0.532506 | 3.597726 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_mem.vhd
| 1 | 3,965 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:35:25 10/04/2013
-- Design Name:
-- Module Name: wishbone_mem - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_mem is
generic( mem_size : positive := 3;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic
);
end wishbone_mem;
architecture Behavioral of wishbone_mem is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal write_mem : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
write_mem <= wbs_strobe and wbs_write and wbs_cycle ;
ram0 : dpram_NxN
generic map(SIZE => mem_size, NBIT => wb_size, ADDR_WIDTH=> wb_addr_size)
port map(
clk => gls_clk,
we => write_mem ,
di => wbs_writedata,
a => wbs_address ,
dpra => (others => '0'),
spo => wbs_readdata,
dpo => open
);
end Behavioral;
|
lgpl-3.0
|
1c2a54548792d1a40f81d43dd5866e11
| 0.590416 | 3.591486 | false | false | false | false |
ricardo-jasinski/vhdl-csv-file-reader
|
hdl/testbench/testbench_utils.vhd
| 1 | 4,616 |
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package with a series of routines useful when writing testbenches. Includes
-- formatted print output and assertions.
package testbench_utils is
procedure puts(text: string);
procedure puts(value: integer);
procedure puts(value: real);
procedure puts(value: boolean);
procedure puts(str: string; val: integer);
procedure puts(str1: string; val1: integer; str2: string; val2: integer);
procedure puts(str: string; val: real);
procedure puts(str: string; val: bit);
procedure puts(str: string; val: boolean);
procedure puts(str: string; val: string);
procedure print_unsigned(value: unsigned; tag: string := "");
procedure print_std_logic_vector(vector: std_logic_vector; tag: string := "");
procedure print_bit_vector(vector: bit_vector; tag: string := "");
procedure describe(function_name: string);
procedure should(msg: string; expr: boolean);
procedure assert_that(msg: string; expr: boolean);
procedure assert_that(msg: string; sig: bit);
procedure assert_that(expr: boolean);
procedure done;
procedure delta_cycle;
procedure wait_tests_finished;
end package testbench_utils;
package body testbench_utils is
procedure puts(text: string) is
variable s: line;
begin
write(s, text);
writeline(output,s);
end procedure;
procedure puts(value: integer) is
variable text: line;
begin
write(text, value);
writeline(output, text);
end procedure;
procedure puts(value: real) is
variable text: line;
begin
write(text, value);
writeline(output, text);
end procedure;
procedure puts(value: boolean) is
variable text: line;
begin
write(text, value);
writeline(output, text);
end procedure;
procedure puts(str: string; val: integer) is
variable l: line;
begin
write(l, str);
write(l, val);
writeline(output, l);
end procedure;
procedure puts(str1: string; val1: integer; str2: string; val2: integer) is begin
puts(str1 & integer'image(val1) & str2 & integer'image(val2));
end;
procedure puts(str: string; val: real) is
variable l: line;
begin
write(l, str);
write(l, val);
writeline(output, l);
end procedure;
procedure puts(str: string; val: bit) is
variable l: line;
begin
write(l, str);
write(l, val);
writeline(output, l);
end procedure;
procedure puts(str: string; val: boolean) is
variable l: line;
begin
write(l, str);
write(l, val);
writeline(output, l);
end procedure;
procedure puts(str: string; val: string) is
variable l: line;
begin
write(l, str);
write(l, val);
writeline(output, l);
end procedure;
procedure prepend_tag(tag: string; variable text: inout line) is begin
if tag /= "" then
write(text, tag & " ");
end if;
end procedure;
procedure print_std_logic_vector(vector: std_logic_vector; tag: string := "") is
variable text: line;
variable char: character;
begin
prepend_tag(tag, text);
for i in vector'range loop
if vector(i) = '0' then
char := '0';
elsif vector(i) = '1' then
char := '1';
else
char := '?';
end if;
write(text, char);
end loop;
writeline(output, text);
end procedure;
procedure print_bit_vector(vector: bit_vector; tag: string := "") is
variable text: line;
begin
prepend_tag(tag, text);
for i in vector'range loop
write(text, vector(i));
end loop;
writeline(output, text);
end procedure;
procedure print_unsigned(value: unsigned; tag: string := "") is begin
print_std_logic_vector(std_logic_vector(value), tag);
end procedure;
procedure describe(function_name: string) is begin
puts("Function " & function_name & " should:");
end procedure;
procedure should(msg: string; expr: boolean) is begin
assert expr report "error in test case '" & msg & "'" severity failure;
puts("- " & msg);
end procedure;
procedure assert_that(msg: string; sig: bit) is begin
should(msg, sig = '1');
end procedure;
procedure assert_that(msg: string; expr: boolean) is begin
should(msg, expr);
end procedure;
procedure assert_that(expr: boolean) is begin
assert expr severity failure;
end procedure;
procedure delta_cycle is begin
wait for 0 ns;
end procedure;
procedure done is begin
wait;
end procedure;
procedure wait_tests_finished is begin
wait for 10 ns;
puts("All tests ran ok.");
wait;
end procedure;
end package body testbench_utils;
|
unlicense
|
df05309dd4907970d23e5f30c2757468
| 0.664211 | 3.707631 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/primitive/logi_primitive_pack.vhd
| 2 | 1,778 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package logi_primitive_pack is
component MAC16 is
port(clk, sraz : in std_logic;
add_subb, reset_acc : in std_logic;
A, B : in signed(15 downto 0);
RES : out signed(31 downto 0)
);
end component;
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
component tdp_bram is
generic (
DATA_A : integer := 16;
ADDR_A : integer := 10;
DATA_B : integer := 16;
ADDR_B : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_A-1 downto 0);
a_din : in std_logic_vector(DATA_A-1 downto 0);
a_dout : out std_logic_vector(DATA_A-1 downto 0);
-- Port B
b_clk : in std_logic;
b_wr : in std_logic;
b_addr : in std_logic_vector(ADDR_B-1 downto 0);
b_din : in std_logic_vector(DATA_B-1 downto 0);
b_dout : out std_logic_vector(DATA_B-1 downto 0)
);
end component;
end logi_primitive_pack;
package body logi_primitive_pack is
end logi_primitive_pack;
|
lgpl-3.0
|
e568f69f3539b19bb9b45fe9fbcdaa5b
| 0.597863 | 2.943709 | false | false | false | false |
CprE488/Final
|
system/hdl/system_sws_8bits_wrapper.vhd
| 3 | 4,984 |
-------------------------------------------------------------------------------
-- system_sws_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_sws_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_sws_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_sws_8bits_wrapper;
architecture STRUCTURE of system_sws_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
SWs_8Bits : axi_gpio
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "SWs_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
gpl-3.0
|
834a1fd48cf109d8065417b21c0086e4
| 0.584872 | 2.912916 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altddio_in/_primary.vhd
| 1 | 1,270 |
library verilog;
use verilog.vl_types.all;
entity altddio_in is
generic(
width : integer := 1;
power_up_high : string := "OFF";
invert_input_clocks: string := "OFF";
intended_device_family: string := "Stratix";
lpm_type : string := "altddio_in";
lpm_hint : string := "UNUSED"
);
port(
datain : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
aset : in vl_logic;
aclr : in vl_logic;
sset : in vl_logic;
sclr : in vl_logic;
dataout_h : out vl_logic_vector;
dataout_l : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_high : constant is 1;
attribute mti_svvh_generic_type of invert_input_clocks : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end altddio_in;
|
bsd-2-clause
|
3c4ff89fc118865df56ca0226a33c2e6
| 0.553543 | 3.791045 | false | false | false | false |
gw0/rs-skip-gram-in-myhdl
|
ex-target/DotProduct.vhd
| 1 | 1,939 |
-- File: ./ex-target/DotProduct.vhd
-- Generated by MyHDL 1.0dev
-- Date: Tue Oct 6 16:32:07 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity DotProduct is
port (
y: out signed (15 downto 0);
y_da_vec: out unsigned(47 downto 0);
y_db_vec: out unsigned(47 downto 0);
a_vec: inout unsigned(47 downto 0);
b_vec: inout unsigned(47 downto 0)
);
end entity DotProduct;
-- Vector dot product and derivative model using fixbv type.
--
-- :param y: return dot(a_vec, b_vec) as fixbv
-- :param y_da_vec: return d/da dot(a_vec, b_vec) as vector of fixbv
-- :param y_db_vec: return d/db dot(a_vec, b_vec) as vector of fixbv
-- :param a_vec: vector of fixbv
-- :param b_vec: vector of fixbv
-- :param dim: vector dimensionality
-- :param fix_min: fixbv min value
-- :param fix_max: fixbv max value
-- :param fix_res: fixbv resolution
architecture MyHDL of DotProduct is
type t_array_a_list is array(0 to 3-1) of signed (15 downto 0);
signal a_list: t_array_a_list;
type t_array_b_list is array(0 to 3-1) of signed (15 downto 0);
signal b_list: t_array_b_list;
begin
b_vec(48-1 downto 32) <= None;
b_vec(32-1 downto 16) <= None;
b_vec(16-1 downto 0) <= None;
a_vec(48-1 downto 32) <= None;
a_vec(32-1 downto 16) <= None;
a_vec(16-1 downto 0) <= None;
a_list(0) <= a_vec(16-1 downto 0);
a_list(1) <= a_vec(32-1 downto 16);
a_list(2) <= a_vec(48-1 downto 32);
b_list(0) <= b_vec(16-1 downto 0);
b_list(1) <= b_vec(32-1 downto 16);
b_list(2) <= b_vec(48-1 downto 32);
DOTPRODUCT_DOT: process (a_list, b_list) is
variable y_sum: signed(31 downto 0);
begin
y_sum := to_signed(0.0, 32);
for j in 0 to 3-1 loop
y_sum := (y_sum + (a_list(j) * b_list(j)));
end loop;
y <= to_signed(y_sum, 16);
end process DOTPRODUCT_DOT;
y_da_vec <= b_vec;
y_db_vec <= a_vec;
end architecture MyHDL;
|
agpl-3.0
|
abef1125d758fc14828af3f8f21c6f85
| 0.638989 | 2.638095 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng.vhd
| 2 | 4,028 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
219061d3d67e2072af35e084f80d2782
| 0.643992 | 4.266949 | false | false | false | false |
db-electronics/MDFlashCart
|
VHDL/MDHomebrew.vhd
| 1 | 4,988 |
--*************************************************************
--
-- $Rev:: 305 $: Revision of last commit
-- $Author:: reneleonrichard $: Author of last commit
-- $Date:: 2014-10-09 20:11:27 -0400 (Thu, 09 Oct 2014) $: Date of last commit
-- $HeadURL: https://subversion.assembla.com/svn/db_repository/trunk/FPGAProjects/SMSCart/src/SMSCart.vhd $
--
--*************************************************************
-- db MD Mapper
-- Copyright 2014 Rene Richard
-- DEVICE : EPM3064ATC100-10
--*************************************************************
-- db MD Mapper supports a face-melting 256 MEGA POWER
--*************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library altera;
use altera.altera_primitives_components.all;
entity MDHomebrew is
generic (
MAPPER_SIZE_g : integer := 6
);
port (
--input from Genesis
ADDRLO_p : in std_logic_vector(2 downto 0); --Address 3,2,1
ADDRHI_p : in std_logic_vector(2 downto 0); --Address 21,20,19
DATA_p : in std_logic_vector(MAPPER_SIZE_g-1 downto 0);
nRST_p : in std_logic;
nTIME_p : in std_logic;
nCE_p : in std_logic;
nLWR_p : in std_logic;
nUWR_p : in std_logic;
nOE_p : in std_logic;
--output to ROM
DIR_p : out std_logic;
nROMCE_p : out std_logic;
--ROM A19 and up
ROMADDR_p : out std_logic_vector(MAPPER_SIZE_g-1 downto 0);
--output to SRAM
nSRAMCE_p : out std_logic;
SRAMWE_p : out std_logic;
nLBS_p : out std_logic;
nUBS_p : out std_logic
);
end entity;
architecture MDHomebrew_a of MDHomebrew is
--Mapper slot registers, fitter will optimize any unused bits
signal romSlot1_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot2_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot3_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot4_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot5_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot6_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot7_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal ramEn_s : std_logic;
begin
--what little level conversion I can do is handled here
SRAMWE_p <= '1' when (nLWR_p = '0' or nUWR_p = '0') else '0';
nLBS_p <= '0' when (nLWR_p = '0' or nOE_p = '0') else '1';
nUBS_p <= '0' when (nUWR_p = '0' or nOE_p = '0') else '1';
DIR_p <= '1' when (nOE_p = '0' and nCE_p = '0') else '0';
--drive CE depending on ramEn_s
--RAM, when enabled, appears at 0x200000
chipselects: process ( ADDRHI_p, nCE_p, ramEn_s)
begin
case ADDRHI_p(2) is --Address 21
when '0' =>
nSRAMCE_p <= '1';
nROMCE_p <= nCE_p;
when '1' =>
if ramEn_s = '1' then
nSRAMCE_p <= nCE_p;
nROMCE_p <= '1';
else
nSRAMCE_p <= '1';
nROMCE_p <= nCE_p;
end if;
end case;
end process;
--mapper registers
mappers: process( nRST_p, nTIME_p, ADDRLO_p)
begin
if nRST_p = '0' then
ramEn_s <= '0';
romSlot1_s <= std_logic_vector(to_unsigned(1, romSlot1_s'length));
romSlot2_s <= std_logic_vector(to_unsigned(2, romSlot2_s'length));
romSlot3_s <= std_logic_vector(to_unsigned(3, romSlot3_s'length));
romSlot4_s <= std_logic_vector(to_unsigned(4, romSlot4_s'length));
romSlot5_s <= std_logic_vector(to_unsigned(5, romSlot5_s'length));
romSlot6_s <= std_logic_vector(to_unsigned(6, romSlot6_s'length));
romSlot3_s <= std_logic_vector(to_unsigned(7, romSlot7_s'length));
elsif rising_edge(nTIME_p) then
--no address(0) from genesis, but I append it here for clarity
case (ADDRLO_p & '1') is
when x"1" =>
ramEn_s <= DATA_p(0);
when x"3" =>
romSlot1_s <= DATA_p;
when x"5" =>
romSlot2_s <= DATA_p;
when x"7" =>
romSlot3_s <= DATA_p;
when x"9" =>
romSlot4_s <= DATA_p;
when x"B" =>
romSlot5_s <= DATA_p;
when x"D" =>
romSlot6_s <= DATA_p;
when x"F" =>
romSlot7_s <= DATA_p;
when others =>
null;
end case;
end if;
end process;
--banking select
--only looks at address, this way the address setup and hold times can be respected
banking: process( ADDRHI_p )
begin
ROMADDR_p <= (others=>'0');
if ramEn_s = '0' then
case ADDRHI_p is --address 21,20 and 19
when "000" =>
-- first bank is always from lowest 512K of ROM
ROMADDR_p <= (others=>'0');
when "001" =>
ROMADDR_p <= romSlot1_s;
when "010" =>
ROMADDR_p <= romSlot2_s;
when "011" =>
ROMADDR_p <= romSlot3_s;
when "100" =>
ROMADDR_p <= romSlot4_s;
when "101" =>
ROMADDR_p <= romSlot5_s;
when "110" =>
ROMADDR_p <= romSlot6_s;
when "111" =>
ROMADDR_p <= romSlot7_s;
when others =>
ROMADDR_p <= (others=>'0');
end case;
end if;
end process;
end MDHomebrew_a;
|
gpl-2.0
|
3a4d53e7a14ec8424d089dd76a0104e6
| 0.575381 | 2.69476 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/communication/i2c_master.vhd
| 2 | 8,283 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:28:10 07/01/2014
-- Design Name:
-- Module Name: i2c_master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end i2c_master;
architecture Behavioral of i2c_master is
constant clk_div : positive := ((clk_freq_hz/i2c_freq_hz)/4)-1 ;
TYPE master_state IS (IDLE, I2C_START, TX_ADDR, ACK_ADDR, TX_BYTE, RX_BYTE, ACK_BYTE, HOLDING, I2C_STOP) ;
signal cur_state, next_state : master_state ;
signal modulo_counter : std_logic_vector(15 downto 0);
signal end_modulo : std_logic ;
signal cycle_counter : std_logic_vector(1 downto 0);
signal quarter, half, full : std_logic ;
signal transmit_buffer, receive_buffer, addr_buffer : std_logic_vector(7 downto 0);
signal bit_counter : std_logic_vector(2 downto 0);
signal write_mode : std_logic ;
signal sda_unbuf, sda_latched : std_logic ;
signal sda_shift_reg : std_logic_vector(5 downto 0);
signal is_acked : std_logic ;
begin
process(clk, reset)
begin
if reset = '1' then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif clk'event and clk = '1' then
if cur_state = IDLE then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif modulo_counter = 0 then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= cycle_counter + 1;
else
modulo_counter <= modulo_counter - 1 ;
end if ;
end if ;
end process ;
end_modulo <= '1' when modulo_counter = 0 else
'0' ;
quarter <= '1' when cycle_counter = 1 else
'1' when cycle_counter = 3 else
'0' ;
half <= '1' when cycle_counter = 2 else
'0' ;
full <= '1' when cycle_counter = 3 and end_modulo = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= IDLE ;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, bit_counter, write_mode, cycle_counter, end_modulo, quarter, half, full, i2c_write, i2c_read, sda)
begin
next_state <= cur_state ;
case (cur_state) is
when IDLE =>
if i2c_write = '1' then
next_state <= I2C_START ;
elsif i2c_read = '1' then
next_state <= I2C_START ;
end if ;
when I2C_START =>
if full = '1' then
next_state <= TX_ADDR ;
end if ;
when TX_ADDR =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_ADDR ;
end if ;
when ACK_ADDR =>
if full = '1' and is_acked = '1' and write_mode = '1' then
next_state <= TX_BYTE ;
elsif full = '1' and is_acked = '1' and write_mode = '0' then
next_state <= RX_BYTE ;
elsif full = '1' and is_acked = '0' then
next_state <= I2C_STOP ;
end if ;
when TX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when RX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when ACK_BYTE =>
if full = '1' and i2c_write = '1' and is_acked = '1' then --
next_state <= TX_BYTE ;
elsif full = '1' and i2c_read = '1' then
next_state <= RX_BYTE ;
elsif full = '1' then
next_state <= I2C_STOP ;
end if ;
when I2C_STOP =>
if full = '1' then
next_state <= IDLE ;
end if ;
when others =>
end case ;
end process ;
scl <= 'Z' when cur_state = I2C_START and cycle_counter < 2 else
'0' when cur_state = I2C_START and cycle_counter >= 2 else
'Z' when cur_state = IDLE else
'0' when cycle_counter < 2 else
'Z' ;
sda_unbuf <= '0' when cur_state = I2C_START else
'0' when cur_state = I2C_STOP and cycle_counter <= 2 else
'1' when cur_state = I2C_STOP and cycle_counter > 2 else -- need to make sure its enough ...
'1' when cur_state = IDLE else
'1' when cur_state = TX_ADDR and addr_buffer(7) = '1' else
'0' when cur_state = TX_ADDR and addr_buffer(7) = '0' else
'1' when cur_state = TX_BYTE and transmit_buffer(7) = '1' else
'0' when cur_state = TX_BYTE and transmit_buffer(7) = '0' else
'0' when cur_state = ACK_BYTE and write_mode = '0' and i2c_read = '1' else
'1' ;
process(clk, reset)
begin
if reset = '1' then
sda_shift_reg <= (others => '1');
elsif clk'event and clk = '1' then
sda_shift_reg(0) <= sda_unbuf ;
sda_shift_reg(sda_shift_reg'high downto 1) <= sda_shift_reg(sda_shift_reg'high-1 downto 0);
end if ;
end process ;
sda <= 'Z' when cur_state = ACK_BYTE and write_mode = '1' else
'0' when sda_shift_reg(sda_shift_reg'high) = '0' else
'Z' ;
process(clk, reset)
begin
if reset = '1' then
is_acked <= '0' ;
elsif clk'event and clk = '1' then
if (cur_state = ACK_BYTE or cur_state = ACK_ADDR ) and sda = '0' then
is_acked <= '1' ;
elsif cur_state /= ACK_BYTE then
is_acked <= '0' ;
end if ;
end if ;
end process ;
ack <= '1' when cur_state = ACK_BYTE and is_acked = '1' and full = '1' else
'1' when cur_state = ACK_BYTE and next_state = RX_BYTE else
'1' when cur_state = ACK_ADDR and is_acked = '1' and full = '1' else
'0' ;
nack <= '1' when cur_state = ACK_BYTE and write_mode = '1' and full='1' and is_acked = '0' else
'1' when cur_state = ACK_ADDR and full='1' and is_acked = '0' else
'0' ;
busy <= '0' when cur_state = IDLE else
'1' ;
new_data <= '1' when cur_state = ACK_BYTE and write_mode = '0' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
transmit_buffer <= (others => '0') ;
receive_buffer <= (others => '0') ;
addr_buffer <= (others => '0') ;
bit_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if (cur_state = IDLE and i2c_write = '1') or i2c_read = '1' then
addr_buffer <= slave_addr & i2c_read ;
elsif cur_state = TX_ADDR and full = '1' then
addr_buffer(7 downto 1) <= addr_buffer(6 downto 0);
end if;
if cur_state = IDLE and i2c_write = '1' then
transmit_buffer <= data_in ;
elsif cur_state = TX_BYTE and full = '1' then
transmit_buffer(7 downto 1) <= transmit_buffer(6 downto 0);
transmit_buffer(0) <= '0' ;
elsif cur_state = ACK_BYTE and i2c_write = '1' and is_acked = '1' then
transmit_buffer <= data_in;
end if;
if cur_state = IDLE then
receive_buffer <= (others => '0') ;
elsif cur_state = RX_BYTE and half = '1' then
receive_buffer(7 downto 1) <= receive_buffer(6 downto 0);
receive_buffer(0) <= sda ;
end if;
if cur_state = IDLE or cur_state = ACK_BYTE or cur_state = ACK_ADDR then
bit_counter <= (others => '0') ;
elsif (cur_state = TX_ADDR or cur_state = TX_BYTE) and full = '1' then
bit_counter <= bit_counter + 1 ;
end if;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
write_mode <= '0' ;
elsif clk'event and clk = '1' then
if cur_state = IDLE and i2c_write = '1' then
write_mode <= '1' ;
elsif cur_state = I2C_STOP then
write_mode <= '0' ;
end if;
end if ;
end process ;
end Behavioral;
|
lgpl-3.0
|
7125ab54392211815f6761bf6ce7e649
| 0.589038 | 2.880042 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_register.vhd
| 1 | 3,801 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:34 07/31/2013
-- Design Name:
-- Module Name: wishbone_register - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_peripherals_pack.all ;
entity wishbone_register is
generic(
wb_addr_size : natural := 16; -- Address port size for wishbone
wb_size : natural := 16; -- Data port size for wishbone
nb_regs : natural := 1
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reg_out : out slv16_array(0 to nb_regs-1);
reg_in : in slv16_array(0 to nb_regs-1)
);
end wishbone_register;
architecture Behavioral of wishbone_register is
signal reg_in_d, reg_out_d : slv16_array(0 to nb_regs-1) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others =>(others => '0'));
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d(conv_integer(wbs_address)) <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
reg_out <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
reg_in_d <= reg_in ; -- latching inputs
wbs_readdata <= reg_in_d(conv_integer(wbs_address)) ; -- this is not clear if this should only happen in the read part
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
lgpl-3.0
|
f5cf2833587cd56e586ce0a5f38008eb
| 0.596159 | 3.704678 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/OZ3_System.vhd
| 2 | 14,329 |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3, a 32-bit processor
--
--Module Title: OZ3_System
--Module Description:
-- This is the module that brings all of the pieces together; the OZ-3, the
-- clock generator, and the memory bus controller. Other pieces of hardware
-- can be added to expand the system, such as a 7-segment decoder or VGA
-- controller.
--
--Notes:
-- Nomenclature for signals: OZ3_dRAM_data_to_MC
-- |^| |---^---| |-^-|
-- | | |
-- sending module | receiving module
-- signal name/content
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OZ3_System is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
--For the keyboard interface
key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
--Pushbuttons
button_0 : in STD_LOGIC;
button_1 : in STD_LOGIC;
button_2 : in STD_LOGIC;
--Switches
switches : in STD_LOGIC_VECTOR(7 downto 0);
--Control signals for the 4-digit, 7-segment display
anodes : out STD_LOGIC_VECTOR(3 downto 0);
decoder_out : out STD_LOGIC_VECTOR(6 downto 0);
--Outputs for the LCD
LCD_data_bus_out : out STD_LOGIC_VECTOR(7 downto 0);
LCD_RW : out STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_E : out STD_LOGIC;
--Output to the LEDs
LEDs : out STD_LOGIC_VECTOR(7 downto 0);
--Memory data and address buses
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
--Data RAM control signals
dRAM_ce : out STD_LOGIC;
dRAM_lb : out STD_LOGIC;
dRAM_ub : out STD_LOGIC;
dRAM_adv : out STD_LOGIC;
dRAM_cre : out STD_LOGIC;
dRAM_clk : out STD_LOGIC;
--Instruction Flash control signals
flash_ce : out STD_LOGIC;
flash_rp : out STD_LOGIC;
--Shared memory signals
mem_oe : out STD_LOGIC;
mem_we : out STD_LOGIC);
end OZ3_System;
architecture Behavioral of OZ3_System is
--//Components\\--
--The OZ-3
component OZ3 is
Port ( main_clock : in STD_LOGIC;
dbl_clock : in STD_LOGIC;
inv_clock : in STD_LOGIC;
reset : in STD_LOGIC;
input_pins : in STD_LOGIC_VECTOR(15 downto 0);
input_port : in STD_LOGIC_VECTOR(31 downto 0);
instruction_from_iROM : in STD_LOGIC_VECTOR(15 downto 0);
data_from_dRAM : in STD_LOGIC_VECTOR(15 downto 0);
output_pins : out STD_LOGIC_VECTOR(15 downto 0);
output_port : out STD_LOGIC_VECTOR(31 downto 0);
output_port_enable : out STD_LOGIC;
addr_to_iROM : out STD_LOGIC_VECTOR(22 downto 0);
data_to_dRAM : out STD_LOGIC_VECTOR(15 downto 0);
addr_to_dRAM : out STD_LOGIC_VECTOR(22 downto 0);
WR_to_dRAM : out STD_LOGIC);
end component;
--The memory bus controller
component Mem_Ctrl is
Port ( flash_address_from_OZ3 : in STD_LOGIC_VECTOR(22 downto 0);
dbl_clk_from_OZ3 : in STD_LOGIC;
dRAM_WR_from_OZ3 : in STD_LOGIC;
dRAM_address_from_OZ3 : in STD_LOGIC_VECTOR(22 downto 0);
dRAM_data_from_OZ3 : in STD_LOGIC_VECTOR(15 downto 0);
data_bus : in STD_LOGIC_VECTOR(15 downto 0);
dRAM_ce : out STD_LOGIC;
dRAM_lb : out STD_LOGIC;
dRAM_ub : out STD_LOGIC;
dRAM_adv : out STD_LOGIC;
dRAM_cre : out STD_LOGIC;
dRAM_clk : out STD_LOGIC;
flash_ce : out STD_LOGIC;
flash_rp : out STD_LOGIC;
mem_oe : out STD_LOGIC;
mem_we : out STD_LOGIC;
address_bus : out STD_LOGIC_VECTOR(22 downto 0);
dRAM_data_to_OZ3 : out STD_LOGIC_VECTOR(15 downto 0);
instruction_to_OZ3 : out STD_LOGIC_VECTOR(15 downto 0));
end component;
--The clock manager/generator
component Clock_Mgt is
Port ( board_clock : in STD_LOGIC;
clock1_out : out STD_LOGIC;
clock2_out : out STD_LOGIC;
clock3_out : out STD_LOGIC;
clock4_out : out STD_LOGIC);
end component;
--The 4-digit, 7-segment decoder
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
--An input port extender for the OZ-3
component Input_Port_MUX is
Port ( input0 : in STD_LOGIC_VECTOR (31 downto 0);
input1 : in STD_LOGIC_VECTOR (31 downto 0);
input2 : in STD_LOGIC_VECTOR (31 downto 0);
input3 : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (31 downto 0));
end component;
--An output port extender for the OZ-3
component Output_Port_MUX is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output0 : out STD_LOGIC_VECTOR (31 downto 0);
output1 : out STD_LOGIC_VECTOR (31 downto 0);
output2 : out STD_LOGIC_VECTOR (31 downto 0);
output3 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
--A simple debouncer for inputs
component Debouncer is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end component;
--A keyboard interface controller
component Keyboard is
Port ( key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
acknowledge : in STD_LOGIC;
scan_code : out STD_LOGIC_VECTOR (0 to 7);
code_ready : out STD_LOGIC);
end component;
--\\Components//--
--//Signals\\--
--These signals cary the four clock signals from the clock manager
--to other parts of the system
signal clock_1 : STD_LOGIC;
signal clock_2 : STD_LOGIC;
signal clock_3 : STD_LOGIC;
signal clock_4 : STD_LOGIC;
----Signals between the MC and OZ3
signal OZ3_instruction_addr_to_MC : STD_LOGIC_VECTOR(22 downto 0); --Signals used to send data from OZ-3 to the
signal OZ3_dRAM_data_to_MC : STD_LOGIC_VECTOR(15 downto 0); --memory controller
signal OZ3_dRAM_addr_to_MC : STD_LOGIC_VECTOR(22 downto 0);
signal OZ3_dRAM_WR_to_MC : STD_LOGIC;
signal MC_instruction_to_OZ3 : STD_LOGIC_VECTOR(15 downto 0); --Signals used to send data from the memory
signal MC_dRAM_data_to_OZ3 : STD_LOGIC_VECTOR(15 downto 0); --controller to the OZ-3
--OZ3 I/O bus signals
--These are the signals that the OZ-3 directly takes input from and outputs to.
--Simply use them to connect to peripheral hardware
signal OZ3_input_pins_sig : STD_LOGIC_VECTOR(15 downto 0);
signal OZ3_input_port_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_output_pins_sig : STD_LOGIC_VECTOR(15 downto 0);
signal OZ3_output_port_sig : STD_LOGIC_VECTOR(31 downto 0);
--Port extension signals
signal OZ3_ex_oport_0_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_oport_1_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_oport_2_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_oport_3_sig : STD_LOGIC_VECTOR(31 downto 0);
signal output_port_MUX_sel : STD_LOGIC_VECTOR(1 downto 0);
signal output_port_MUX_data : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_output_port_enable : STD_LOGIC;
signal OZ3_ex_iport_0_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_iport_1_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_iport_2_sig : STD_LOGIC_VECTOR(31 downto 0);
signal OZ3_ex_iport_3_sig : STD_LOGIC_VECTOR(31 downto 0);
signal input_port_MUX_sel : STD_LOGIC_VECTOR(1 downto 0);
signal input_port_MUX_out : STD_LOGIC_VECTOR(31 downto 0);
--Keyboard signals
signal key_scan_code_sig : STD_LOGIC_VECTOR(7 downto 0); --The code ready signal from the keyboard interface
signal key_acknowledge : STD_LOGIC; --Carries the acknowledgment signal to the keyboard module
signal key_code_ready : STD_LOGIC; --Carries the code ready signal to the OZ-3
--Debounced buttons
signal button_0_debnc : STD_LOGIC;
signal button_1_debnc : STD_LOGIC;
signal button_2_debnc : STD_LOGIC;
--Other signals
signal display_data : STD_LOGIC_VECTOR(15 downto 0); --Carries display data to the 7-segment display decoder
--\\Signals//--
begin
--OZ-3 instantiation
OZ3_inst : OZ3 port map (main_clock => clock_1,
dbl_clock => clock_2,
inv_clock => clock_3,
reset => reset,
input_pins => OZ3_input_pins_sig,
input_port => OZ3_input_port_sig,
instruction_from_iROM => MC_instruction_to_OZ3,
data_from_dRAM => MC_dRAM_data_to_OZ3,
output_pins => OZ3_output_pins_sig,
output_port => OZ3_output_port_sig,
output_port_enable => OZ3_output_port_enable,
addr_to_iROM => OZ3_instruction_addr_to_MC,
data_to_dRAM => OZ3_dRAM_data_to_MC,
addr_to_dRAM => OZ3_dRAM_addr_to_MC,
WR_to_dRAM => OZ3_dRAM_WR_to_MC);
--Memory bus controller instantiation
mem_ctrl_inst : Mem_Ctrl port map (flash_address_from_OZ3 => OZ3_instruction_addr_to_MC,
dbl_clk_from_OZ3 => clock_4,
dRAM_WR_from_OZ3 => OZ3_dRAM_WR_to_MC,
dRAM_address_from_OZ3 => OZ3_dRAM_addr_to_MC,
dRAM_data_from_OZ3 => OZ3_dRAM_data_to_MC,
data_bus => memory_data_bus,
dRAM_ce => dRAM_ce,
dRAM_lb => dRAM_lb,
dRAM_ub => dRAM_ub,
dRAM_adv => dRAM_adv,
dRAM_cre => dRAM_cre,
dRAM_clk => dRAM_clk,
flash_ce => flash_ce,
flash_rp => flash_rp,
mem_oe => mem_oe,
mem_we => mem_we,
address_bus => memory_address_bus,
dRAM_data_to_OZ3 => MC_dRAM_data_to_OZ3,
instruction_to_OZ3 => MC_instruction_to_OZ3);
--Clock manager instantiation
clk_mgt : Clock_Mgt port map (clock,
clock_1,
clock_2,
clock_3,
clock_4);
--7-segment display decoder instantiation
--This is an example of peripheral hardware that can be added to the system
Decoder: four_dig_7seg port map (clock => clock,
display_data => display_data,
anodes => anodes,
to_display => decoder_out);
Input_Extender: Input_Port_MUX port map (input0 => OZ3_ex_iport_0_sig,
input1 => OZ3_ex_iport_1_sig,
input2 => OZ3_ex_iport_2_sig,
input3 => OZ3_ex_iport_3_sig,
sel => input_port_MUX_sel,
output => input_port_MUX_out);
Output_Extender: Output_Port_MUX port map (clock => clock_1,
reset => reset,
enable => OZ3_output_port_enable,
data => output_port_MUX_data,
sel => output_port_MUX_sel,
output0 => OZ3_ex_oport_0_sig,
output1 => OZ3_ex_oport_1_sig,
output2 => OZ3_ex_oport_2_sig,
output3 => OZ3_ex_oport_3_sig);
--The debouncers for the pushbuttons
Debounce1: Debouncer port map (clock => clock,
reset => reset,
input => button_0,
output => button_0_debnc);
Debounce2: Debouncer port map (clock => clock,
reset => reset,
input => button_1,
output => button_1_debnc);
Debounce3: Debouncer port map (clock => clock,
reset => reset,
input => button_2,
output => button_2_debnc);
--The keyboard controller
keyboard_cntl : Keyboard port map (key_clock => key_clock,
key_data => key_data,
acknowledge => key_acknowledge,
scan_code => key_scan_code_sig,
code_ready => key_code_ready);
--Assigning the OZ-3 I/O
--Main input and output ports
OZ3_input_port_sig <= input_port_MUX_out;
output_port_MUX_data <= OZ3_output_port_sig;
--The input pins
OZ3_input_pins_sig(0) <= button_2_debnc;
OZ3_input_pins_sig(1) <= button_1_debnc;
OZ3_input_pins_sig(2) <= button_0_debnc;
OZ3_input_pins_sig(3) <= '0';
OZ3_input_pins_sig(4) <= '0';
OZ3_input_pins_sig(5) <= '0';
OZ3_input_pins_sig(6) <= '0';
OZ3_input_pins_sig(7) <= '0';
OZ3_input_pins_sig(8) <= '0';
OZ3_input_pins_sig(9) <= '0';
OZ3_input_pins_sig(10) <= '0';
OZ3_input_pins_sig(11) <= '0';
OZ3_input_pins_sig(12) <= '0';
OZ3_input_pins_sig(13) <= '0';
OZ3_input_pins_sig(14) <= '0';
OZ3_input_pins_sig(15) <= key_code_ready;
-- --The output pins
-- ? <= OZ3_output_pins_sig(0);
-- ? <= OZ3_output_pins_sig(1);
-- ? <= OZ3_output_pins_sig(2);
-- ? <= OZ3_output_pins_sig(3);
-- ? <= OZ3_output_pins_sig(4);
-- ? <= OZ3_output_pins_sig(5);
-- ? <= OZ3_output_pins_sig(6);
-- ? <= OZ3_output_pins_sig(7);
LCD_E <= OZ3_output_pins_sig(8);
LCD_RS <= OZ3_output_pins_sig(9);
LCD_RW <= OZ3_output_pins_sig(10);
key_acknowledge <= OZ3_output_pins_sig(11);
input_port_MUX_sel(0) <= OZ3_output_pins_sig(12);
input_port_MUX_sel(1) <= OZ3_output_pins_sig(13);
output_port_MUX_sel(0) <= OZ3_output_pins_sig(14);
output_port_MUX_sel(1) <= OZ3_output_pins_sig(15);
--The input ports
--Keyboard scan code
OZ3_ex_iport_0_sig <= x"000000" & key_scan_code_sig;
--Switches
OZ3_ex_iport_1_sig <= x"000000" & switches;
--Blank
OZ3_ex_iport_2_sig <= x"00000000";
--Blank
OZ3_ex_iport_3_sig <= x"00000000";
--The output ports
--LCD data bus
LCD_data_bus_out <= OZ3_ex_oport_0_sig(7 downto 0);
--LEDs
LEDs <= OZ3_ex_oport_1_sig(7 downto 0);
--Data to the 7-segment display
display_data <= OZ3_ex_oport_2_sig(15 downto 0);
--Output port 3 is blank
-- ? <= OZ3_ex_oport_3_sig
end Behavioral;
|
mit
|
f895be3c6f6d20a2b083fe50c7a1afdb
| 0.595087 | 3.171536 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/spi_seq.vhd
| 1 | 12,313 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (Fri, 02 Jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
--library work;
--use work.all;
--use work.app_pack.all;
entity spi_seq is
generic (
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50;
gDATA_WIDTH : integer := 26;
gSyncTriggerWidth : integer := 1; -- min 1, max 15
gRWbitposition : integer := 0; -- seen from LSB, when > 32
gRWbitpolarity : integer := 0 -- '0': On SPI channel write = 1, read = 0. '1': inverse
);
port (
-- system:
CLK : in std_logic;
RESET : in std_logic;
BUSY : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
SPI_START : out std_logic;
SPI_BUSY : in std_logic;
SPI_DATA_TX : out std_logic_Vector(gDATA_WIDTH-1 downto 0);
SPI_DATA_RX : in std_logic_vector(gDATA_WIDTH-1 downto 0)
);
end spi_seq;
Architecture behaviour of spi_seq is
----------------------
--constant definition:
----------------------
type spi_seqtp is (
Idle,
WaitSync1,
WaitSync1First,
WaitSync2,
Check_Fifo_Empty,
Read_En_Active,
Read_En_Active2,
GetFifoValue,
DoSpiComm,
Wait_spi_comm_busy,
Wait_spi_comm_busy_off
);
---------------------
-- signal definition:
---------------------
signal spi_seq : spi_seqtp;
signal SpiRw : std_logic; --'0' = write, '1' = read
signal Sync1_rising : std_logic;
signal Sync2_rising : std_logic;
signal synctriggers_prev : std_logic_vector(gSyncTriggerWidth-1 downto 0);
begin
--------------------------
-- default values --
--------------------------
APP_RDFIFO_CLK <= CLK;
APP_WRFIFO_CLK <= CLK;
--------------------------
-- Process definition: --
--------------------------
-- APP_RDFIFO_DATA_OUT bit assignments
-- bit 31 sync 2
-- bit 30 sync 1
-- bit 29 NOP bit
-- bits 28 RW (W = 0, R = 1)
-- bits 27 dt 0: address + data
spi_sequencer: Process (CLK, RESET)
variable RWbit : std_logic;
begin
if (RESET='1') then
BUSY <= '0';
SPI_START <= '0';
SPI_DATA_TX <= (others => '0');
SpiRw <= '0';
RWbit := '0';
APP_RDFIFO_EN <= '0';
APP_WRFIFO_EN <= '0';
APP_WRFIFO_DATA_IN <= (others => '0');
ERROR <= '0';
spi_seq <= Idle;
elsif (CLK'event and CLK='1') then
SPI_START <= '0';
APP_RDFIFO_EN <= '0';
APP_WRFIFO_EN <= '0';
Case spi_seq is
when Idle =>
BUSY <= '0';
if (APP_RDFIFO_EMPTY = '0') then
APP_RDFIFO_EN <= '1';
spi_seq <= Read_En_Active;
end if;
when Check_Fifo_Empty =>
if (APP_RDFIFO_EMPTY = '0') then
APP_RDFIFO_EN <= '1';
spi_seq <= Read_En_Active;
else
spi_seq <= Idle;
end if;
when Read_En_Active =>
spi_seq <= Read_En_Active2;
when Read_En_Active2 =>
spi_seq <= GetFifoValue;
when GetFifoValue =>
case APP_RDFIFO_DATA_OUT(31 downto 30) is
when "00" => --Immediate =>
spi_seq <= DoSpiComm;
when "01" => --Sync1 =>
spi_seq <= WaitSync1;
when "10" => --Sync2 =>
spi_seq <= WaitSync2;
when "11" => --FirstSync1ThenSync2 =>
spi_seq <= WaitSync1First;
when others =>
spi_seq <= DoSpiComm;
end case;
when WaitSync1 =>
if (Sync1_rising = '1') then
spi_seq <= DoSpiComm;
end if;
when WaitSync1First =>
if (Sync1_rising = '1') then
spi_seq <= WaitSync2;
end if;
when WaitSync2 =>
if (Sync2_rising = '1') then
spi_seq <= DoSpiComm;
end if;
when DoSpiComm =>
if (APP_RDFIFO_DATA_OUT(29) = '0') then
SpiRw <= APP_RDFIFO_DATA_OUT(28);
SPI_START <= '1';
--
--
if (gRWbitpolarity > 0) then
RWbit := APP_RDFIFO_DATA_OUT(28);
else
RWbit := not APP_RDFIFO_DATA_OUT(28);
end if;
if (gRWbitposition = 0) then
SPI_DATA_TX <= APP_RDFIFO_DATA_OUT(gDATA_WIDTH-2 downto 0) & RWbit;
elsif (gRWbitposition = 27) then
SPI_DATA_TX <= RWbit & APP_RDFIFO_DATA_OUT(gDATA_WIDTH-2 downto 0);
elsif (gRWbitposition > 32) then
SPI_DATA_TX <= APP_RDFIFO_DATA_OUT(gDATA_WIDTH-1 downto 0);
else
SPI_DATA_TX <= APP_RDFIFO_DATA_OUT(gDATA_WIDTH-2 downto gRWbitposition) & RWbit & APP_RDFIFO_DATA_OUT(gRWbitposition-1 downto 0);
end if;
spi_seq <= Wait_spi_comm_busy;
else --NOP bit set
spi_seq <= Check_Fifo_Empty;
end if;
when Wait_spi_comm_busy =>
if (SPI_BUSY = '1') then
spi_seq <= Wait_spi_comm_busy_off;
end if;
when Wait_spi_comm_busy_off =>
if (SPI_BUSY = '0') then
if (SpiRw = '1') then --a read was performed, so write the result to FIFO
APP_WRFIFO_DATA_IN(31 downto gDATA_WIDTH) <= (others => '0');
APP_WRFIFO_DATA_IN(gDATA_WIDTH-1 downto 0) <= SPI_DATA_RX;
APP_WRFIFO_EN <= '1';
ERROR <= APP_WRFIFO_FULL;
end if;
spi_seq <= Check_Fifo_Empty;
end if;
when others =>
spi_seq <= Idle;
end case;
end if;
end process;
spi_triggerselector: Process (CLK, RESET)
begin
if (RESET='1') then
Sync1_rising <= '0';
Sync2_rising <= '0';
synctriggers_prev <= (others => '0');
elsif (CLK'event and CLK='1') then
synctriggers_prev <= synctriggers;
for i in 0 to gSyncTriggerWidth-1 loop
if (TO_INTEGER(UNSIGNED(sync1_select)) = i) then
Sync1_rising <= synctriggers_prev(i) and not synctriggers(i);
end if;
if (TO_INTEGER(UNSIGNED(sync2_select)) = i) then
Sync2_rising <= synctriggers_prev(i) and not synctriggers(i);
end if;
end loop;
end if;
end process;
end behaviour;
|
gpl-3.0
|
d9feac35b1fb0a9e8f9544c45b62312d
| 0.389751 | 4.84573 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altsqrt/_primary.vhd
| 1 | 1,085 |
library verilog;
use verilog.vl_types.all;
entity altsqrt is
generic(
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt"
);
port(
radical : in vl_logic_vector;
clk : in vl_logic;
ena : in vl_logic;
aclr : in vl_logic;
q : out vl_logic_vector;
remainder : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of q_port_width : constant is 1;
attribute mti_svvh_generic_type of r_port_width : constant is 1;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of pipeline : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end altsqrt;
|
bsd-2-clause
|
eee5b6fa1ba72352f4314362a09c7053
| 0.549309 | 3.807018 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg.vhd
| 1 | 11,934 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(75-1 DOWNTO 0);
DOUT : OUT std_logic_vector(75-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg;
|
gpl-3.0
|
4ac485b113c90b5f50055b0082724074
| 0.513658 | 3.860886 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/ID.vhd
| 2 | 13,633 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:55:38 10/26/2009
-- Design Name:
-- Module Name: ID - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Description: The instruction decoder of the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Ports written in
-- Revision 0.15 - Main process outlines written
-- Revision 0.30 - Control and Arithmetic/Logic decoding sections first draft done
-- Revision 0.31 - Memory and I/O decoding sections first draft complete, need to include the register file
-- and output process to handle forwarding
-- Revision 0.32 - Output/forward logic process done, need to do all of the ORing of data lines, add
-- the register file, and OR all of its address lines
-- Revision 0.33 - Register file component instantiated, ports mapped; need to OR all the signals and such
-- Revision 0.40 - First draft of module complete, syntax errors corrected; need to simulate
-- Revision 0.50 - Simulation and testing of all instruction complete, need to test forwarding
-- Revision 0.55 - Forwarding logic tested
-- Revision 0.56 - Added forwarding logic for the third address port of the register file
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ID is
Port ( --Inputs--
--Main inputs
clock : in STD_LOGIC;
reset : in STD_LOGIC;
instruction_from_IF : in STD_LOGIC_VECTOR(31 downto 0);
--Register file inputs
rfile_read_addr3_from_MEMIO : in STD_LOGIC_VECTOR(4 downto 0); --AKA RAM reg addr
rfile_write_addr_from_WB : in STD_LOGIC_VECTOR(4 downto 0);
rfile_write_data_from_WB : in STD_LOGIC_VECTOR(31 downto 0);
rfile_write_e_from_WB : in STD_LOGIC;
--Forwarding logic inptus
forward_addr_EX : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_EX : in STD_LOGIC_VECTOR(31 downto 0);
forward_addr_MEMIO : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_MEMIO : in STD_LOGIC_VECTOR(31 downto 0);
forward_addr_WB : in STD_LOGIC_VECTOR(4 downto 0);
forward_data_WB : in STD_LOGIC_VECTOR(31 downto 0);
--Outputs--
--EX Control
ALU_A_to_EX : out STD_LOGIC_VECTOR(31 downto 0);
ALU_B_to_EX : out STD_LOGIC_VECTOR(31 downto 0);
EX_control : out STD_LOGIC_VECTOR(11 downto 0);
--MEMIO Control
RAM_reg_data_to_MEMIO : out STD_LOGIC_VECTOR(31 downto 0);
MEMIO_control : out STD_LOGIC_VECTOR(20 downto 0);
--WB Control
WB_control : out STD_LOGIC_VECTOR(5 downto 0));
end ID;
architecture Behavioral of ID is
--//Components\\--
component RegFile is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
write_e : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
r_addr1 : in STD_LOGIC_VECTOR(4 downto 0);
r_addr2 : in STD_LOGIC_VECTOR(4 downto 0);
r_addr3 : in STD_LOGIC_VECTOR(4 downto 0);
w_addr1 : in STD_LOGIC_VECTOR(4 downto 0);
data_out_1 : out STD_LOGIC_VECTOR(31 downto 0);
data_out_2 : out STD_LOGIC_VECTOR(31 downto 0);
data_out_3 : out STD_LOGIC_VECTOR(31 downto 0));
end component;
component GenReg is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal rfile_read_addr1_cntl : STD_LOGIC_VECTOR(4 downto 0); --These will get ORed before going to
signal rfile_read_addr1_arith_logic : STD_LOGIC_VECTOR(4 downto 0); --the register file
signal rfile_read_addr1_MEMIO : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr1 : STD_LOGIC_VECTOR(4 downto 0);
signal rfile_read_addr2 : STD_LOGIC_VECTOR(4 downto 0); --This goes straight to the register file
--and forwarding logic
signal RAM_reg_data_from_rfile : STD_LOGIC_VECTOR(31 downto 0); --This signal carries the rfile's
--third output to the output logic
signal WB_WE_arith_logic : STD_LOGIC; --These will get ORed before going to WB
signal WB_WE_MEMIO : STD_LOGIC;
signal result_reg_arith_logic : STD_LOGIC_VECTOR(4 downto 0); --These will get ORed before going out
signal result_reg_MEMIO : STD_LOGIC_VECTOR(4 downto 0); --to the stages as a single result_reg
signal result_reg : STD_LOGIC_VECTOR(4 downto 0);
signal instruction : STD_LOGIC_VECTOR(31 downto 0);
--All of this has to do with the output to the ALU.
--It'll mostly get handled by tricky ORing, due to the
--fact that the "do nothing" state for the drivers of these signals
--is all zeros, so I can OR them to allow the only used value through
signal rfile_out_1 : STD_LOGIC_VECTOR(31 downto 0);
signal rfile_out_2 : STD_LOGIC_VECTOR(31 downto 0);
signal arith_immediate : STD_LOGIC_VECTOR(31 downto 0);
signal MEMIO_immediate : STD_LOGIC_VECTOR(31 downto 0);
signal displacement : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_B : STD_LOGIC_VECTOR(31 downto 0);
--\\Signals//--
begin
--This process takes care of control instructions
control: process (instruction) is
begin
--Signals to initialize to zero
EX_control(6 downto 4) <= b"000";
rfile_read_addr1_cntl <= b"00000";
displacement <= x"00000000";
if instruction(31) = '1' then
EX_control(6 downto 4) <= instruction(28 downto 26);
rfile_read_addr1_cntl <= instruction(25 downto 21);
if (instruction(20) = '0') then --Sign extension of the displacement value
displacement <= b"00000000000" & instruction(20 downto 0);
else
displacement <= b"11111111111" & instruction(20 downto 0);
end if;
end if;
end process;
--This process decodes memory and I/O instructions
MEMIO: process (instruction) is
begin
--Signals to initialize as zero
MEMIO_immediate <= x"00000000";
MEMIO_control(20 downto 18) <= b"000";
MEMIO_control(12 downto 0) <= b"0000000000000";
rfile_read_addr1_MEMIO <= b"00000";
result_reg_MEMIO <= b"00000";
WB_WE_MEMIO <= '0';
if instruction(30) = '1' then --Need to finish this section, don't forget section cntl
--The immediate value from MEMIO sign extension
if instruction(15) = '0' then
MEMIO_immediate <= (x"0000" & instruction(15 downto 0));
else
MEMIO_immediate <= (x"FFFF" & instruction(15 downto 0));
end if;
--If it's a store/load instruction
if instruction(29) = '1' then
--Control signal for the RAM section
MEMIO_control(2) <= '1';
--Detect load or store
if instruction(27) = '0' then
--Load
result_reg_MEMIO <= instruction(25 downto 21); --result register
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --the register specified
MEMIO_control(12 downto 8) <= instruction(25 downto 21); --dest/data register for RAM operations
MEMIO_control(19 downto 18) <= b"10"; --MUX control
WB_WE_MEMIO <= '1'; --write enable
else
--Store
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --register specified
MEMIO_control(12 downto 8) <= instruction(25 downto 21); --dest/data register for RAM operations
MEMIO_control(7) <= '1'; --change the dRAM write/read signal
end if;
--Upper/lower control signal
MEMIO_control(20) <= instruction(26);
end if;
--If it's a port instruction
if instruction(29 downto 27) = b"001" then
--Control signal for the port section
MEMIO_control(1) <= '1';
--Detect input/output with the ports
if instruction(26) = '0' then --Input
result_reg_MEMIO <= instruction(25 downto 21); --result register
WB_WE_MEMIO <= '1'; --write enable
MEMIO_control(19 downto 18) <= b"01"; --set select for MUX to iprt data
else --Output
rfile_read_addr1_MEMIO <= instruction(20 downto 16); --data register
MEMIO_control(6) <= '1'; --enable the oprt register clock
end if;
end if;
--If it's a pin instruction
if instruction(29 downto 28) = b"01" then
--Control signal for the pin section
MEMIO_control(0) <= '1';
--Detect if it's an output or inpupt pin instruction
if instruction(27) = '0' then --Output
MEMIO_control(5) <= instruction(26); --Opin 1/0 select
MEMIO_control(4) <= '1'; --Opin register clock enable
else --Input
MEMIO_control(3) <= '1'; --pin check enable
end if;
end if;
end if;
end process;
--This process decodes arithmetic and logic instructions
arith_logic: process (instruction) is --I think this is done, but recheck
begin
--Signals to initialize as zero
EX_control(3 downto 0) <= b"0000";
arith_immediate <= x"00000000";
result_reg_arith_logic <= b"00000";
rfile_read_addr1_arith_logic <= b"00000";
rfile_read_addr2 <= b"00000";
WB_WE_arith_logic <= '0';
if instruction(30 downto 29) = b"01" then
result_reg_arith_logic <= instruction(25 downto 21);
rfile_read_addr1_arith_logic <= instruction(20 downto 16);
WB_WE_arith_logic <= '1'; --write enable
--Detecting a register verus immediate addressing mode instruction
if instruction(28 downto 26) = b"111" then
--This is getting the ALU select value
EX_control(3 downto 0) <= instruction(3 downto 0);
--Register file source 2 address
rfile_read_addr2 <= instruction(15 downto 11);
else
--ALU select value if the instruction is in the immediate addressing mode
EX_control(3 downto 0) <= ('0' & instruction(28 downto 26));
--Immediate value sign extension
if instruction(15) = '0' then
arith_immediate <= (x"0000" & instruction(15 downto 0));
else
arith_immediate <= (x"FFFF" & instruction(15 downto 0));
end if;
end if;
end if;
end process;
--This process handles the main outputs, along with
--forwarding logic (ALU A and B already ORed n such)
output: process (rfile_out_1, ALU_B, forward_data_EX, forward_data_MEMIO, forward_data_WB,
forward_addr_EX, forward_addr_MEMIO, forward_addr_WB, rfile_read_addr1,
rfile_read_addr2, rfile_read_addr3_from_MEMIO, RAM_reg_data_from_rfile) is
begin
--Logic for ALU_A/src1
if rfile_read_addr1 /= b"00000" then
--if the source register is EX's result register
if rfile_read_addr1 = forward_addr_EX then
ALU_A_to_EX <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_read_addr1 = forward_addr_MEMIO then
ALU_A_to_EX <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr1 = forward_addr_WB then
ALU_A_to_EX <= forward_data_WB;
else
ALU_A_to_EX <= rfile_out_1;
end if;
else
ALU_A_to_EX <= rfile_out_1;
end if;
--Logic for ALU_B/src2
--if the source register is EX's result register
if rfile_read_addr2 /= b"00000" then
if rfile_read_addr2 = forward_addr_EX then
ALU_B_to_EX <= forward_data_EX;
--if the source register is MEMIO's result register
elsif rfile_read_addr2 = forward_addr_MEMIO then
ALU_B_to_EX <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr2 = forward_addr_WB then
ALU_B_to_EX <= forward_data_WB;
else
ALU_B_to_EX <= ALU_B;
end if;
else
ALU_B_to_EX <= ALU_B;
end if;
--Logic for the RAM register
--if the source register is EX's RAM register
if rfile_read_addr3_from_MEMIO /= b"00000" then
if rfile_read_addr3_from_MEMIO = forward_addr_EX then
RAM_reg_data_to_MEMIO <= forward_data_EX;
--if the source register is MEMIO's result register
-- elsif rfile_read_addr3_from_MEMIO = forward_addr_MEMIO then
-- RAM_reg_data_to_MEMIO <= forward_data_MEMIO;
--if the source register is WB's result register
elsif rfile_read_addr3_from_MEMIO = forward_addr_WB then
RAM_reg_data_to_MEMIO <= forward_data_WB;
else
RAM_reg_data_to_MEMIO <= (others => '0');
end if;
else
RAM_reg_data_to_MEMIO <= RAM_reg_data_from_rfile; --new sig like above
end if;
end process;
--Signals getting combined (I know this adds a lot of excess logic, will optimize later)
rfile_read_addr1 <= (rfile_read_addr1_cntl or rfile_read_addr1_MEMIO or rfile_read_addr1_arith_logic);
result_reg <= (result_reg_MEMIO or result_reg_arith_logic);
WB_control(0) <= (WB_WE_MEMIO or WB_WE_arith_logic);
ALU_B <= (rfile_out_2 or arith_immediate or MEMIO_immediate or displacement);
--Finishing up the control signals
MEMIO_control(17 downto 13) <= result_reg;
EX_control(11 downto 7) <= result_reg;
WB_control(5 downto 1) <= result_reg;
--Register file
rfile: RegFile port map (clock, reset, rfile_write_e_from_WB, rfile_write_data_from_WB, rfile_read_addr1,
rfile_read_addr2, rfile_read_addr3_from_MEMIO, rfile_write_addr_from_WB, rfile_out_1,
rfile_out_2, RAM_reg_data_from_rfile);
--Input register
inst_reg : GenReg generic map (32)
port map (clock, '1', reset, instruction_from_IF, instruction);
end Behavioral;
|
mit
|
6b0f54f06cdb947d259fe86249e9771c
| 0.652168 | 3.383718 | false | false | false | false |
CprE488/Final
|
system/hdl/system_fmc_imageon_hdmi_in_0_wrapper.vhd
| 1 | 1,876 |
-------------------------------------------------------------------------------
-- system_fmc_imageon_hdmi_in_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library fmc_imageon_hdmi_in_v2_01_a;
use fmc_imageon_hdmi_in_v2_01_a.all;
entity system_fmc_imageon_hdmi_in_0_wrapper is
port (
clk : in std_logic;
io_hdmii_spdif : in std_logic;
io_hdmii_video : in std_logic_vector(15 downto 0);
video_vblank : out std_logic;
video_hblank : out std_logic;
video_de : out std_logic;
video_data : out std_logic_vector(15 downto 0);
audio_spdif : out std_logic;
debug_o : out std_logic_vector(23 downto 0)
);
end system_fmc_imageon_hdmi_in_0_wrapper;
architecture STRUCTURE of system_fmc_imageon_hdmi_in_0_wrapper is
component fmc_imageon_hdmi_in is
generic (
C_FAMILY : STRING;
C_DATA_WIDTH : INTEGER
);
port (
clk : in std_logic;
io_hdmii_spdif : in std_logic;
io_hdmii_video : in std_logic_vector(15 downto 0);
video_vblank : out std_logic;
video_hblank : out std_logic;
video_de : out std_logic;
video_data : out std_logic_vector((C_DATA_WIDTH-1) downto 0);
audio_spdif : out std_logic;
debug_o : out std_logic_vector(23 downto 0)
);
end component;
begin
fmc_imageon_hdmi_in_0 : fmc_imageon_hdmi_in
generic map (
C_FAMILY => "zynq",
C_DATA_WIDTH => 16
)
port map (
clk => clk,
io_hdmii_spdif => io_hdmii_spdif,
io_hdmii_video => io_hdmii_video,
video_vblank => video_vblank,
video_hblank => video_hblank,
video_de => video_de,
video_data => video_data,
audio_spdif => audio_spdif,
debug_o => debug_o
);
end architecture STRUCTURE;
|
gpl-3.0
|
e88154f0f97bf4343889c8c445ecc561
| 0.577825 | 3.417122 | false | false | false | false |
gbraad/minimig-de1
|
rtl/tg68k/TG68KdotC_Kernel.vhd
| 2 | 99,206 |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- bugfix session 07/08.Feb.2013
-- movem ,-(an)
-- movem (an)+, - thanks Gerhard Suttner
-- btst dn,#data - thanks Peter Graf
-- movep - thanks Till Harbaum
-- IPL vector - thanks Till Harbaum
--
-- optimize Register file
-- to do 68010:
-- (MOVEC)
-- BKPT
-- RTD
-- MOVES
--
-- to do 68020:
-- (CALLM)
-- (RETM)
-- CAS, CAS2
-- CHK2
-- CMP2
-- cpXXX Coprozessor stuff
-- PACK
-- TRAPcc
-- UNPK
-- done 020:
-- Bitfields
-- address modes
-- long bra
-- DIVS.L, DIVU.L
-- LINK long
-- MULS.L, MULU.L
-- extb.l
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.TG68K_Pack.all;
entity TG68KdotC_Kernel is
generic(
SR_Read : integer:= 0; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 0; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
addr : buffer std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
-- for debug
skipFetch : out std_logic;
regin : buffer std_logic_vector(31 downto 0);
VBR_out : out std_logic_vector(31 downto 0)
);
end TG68KdotC_Kernel;
architecture logic of TG68KdotC_Kernel is
signal syncReset : std_logic_vector(3 downto 0);
signal Reset : std_logic;
signal clkena_lw : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal tmp_TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal PC_dataa : std_logic_vector(31 downto 0);
signal PC_datab : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal state : std_logic_vector(1 downto 0);
signal datatype : std_logic_vector(1 downto 0);
signal set_datatype : std_logic_vector(1 downto 0);
signal exe_datatype : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal exe_opcode : std_logic_vector(15 downto 0);
signal sndOPC : std_logic_vector(15 downto 0);
signal last_opc_read : std_logic_vector(15 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Wwrena,Lwrena : bit;
signal Bwrena : bit;
signal Regwrena_now : bit;
signal rf_dest_addr : std_logic_vector(3 downto 0);
signal rf_source_addr : std_logic_vector(3 downto 0);
signal rf_source_addrd : std_logic_vector(3 downto 0);
type regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);
signal regfile : regfile_t;
signal RDindex_A : integer range 0 to 15;
signal RDindex_B : integer range 0 to 15;
signal WR_AReg : std_logic;
signal memaddr_reg : std_logic_vector(31 downto 0);
signal memaddr_delta : std_logic_vector(31 downto 0);
signal use_base : bit;
signal ea_data : std_logic_vector(31 downto 0);
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal ALUout : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal data_write_muxin : std_logic_vector(31 downto 0);
signal data_write_mux : std_logic_vector(47 downto 0);
signal nextpass : bit;
signal setnextpass : bit;
signal setdispbyte : bit;
signal setdisp : bit;
signal regdirectsource :bit; -- checken !!!
signal addsub_q : std_logic_vector(31 downto 0);
signal briefdata : std_logic_vector(31 downto 0);
-- signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal TG68_PC_brw : bit;
signal TG68_PC_word : bit;
signal getbrief : bit;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : bit;
signal store_in_tmp : bit;
signal write_back : bit;
signal exec_write_back: bit;
signal setstackaddr : bit;
signal writePC : bit;
signal writePCbig : bit;
signal set_writePCbig : bit;
signal setopcode : bit;
signal decodeOPC : bit;
signal execOPC : bit;
signal setexecOPC : bit;
signal endOPC : bit;
signal setendOPC : bit;
signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC
signal FlagsSR : std_logic_vector(7 downto 0); -- T.S..III
signal SRin : std_logic_vector(7 downto 0);
signal exec_DIRECT : bit;
signal exec_tas : std_logic;
signal set_exec_tas : std_logic;
signal exe_condition : std_logic;
signal ea_only : bit;
signal source_lowbits : bit;
signal source_2ndHbits : bit;
signal source_2ndLbits : bit;
signal dest_2ndHbits : bit;
signal dest_hbits : bit;
signal rot_bits : std_logic_vector(1 downto 0);
signal set_rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_actiond : bit;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mux : std_logic_vector(3 downto 0);
signal movem_presub : bit;
signal movem_run : bit;
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_direct_data: bit;
signal use_direct_data: bit;
signal direct_data : bit;
signal set_V_Flag : bit;
signal set_vectoraddr : bit;
signal writeSR : bit;
signal trap_illegal : bit;
signal trap_addr_error : bit;
signal trap_priv : bit;
signal trap_trace : bit;
signal trap_1010 : bit;
signal trap_1111 : bit;
signal trap_trap : bit;
signal trap_trapv : bit;
signal trap_interrupt : bit;
signal trapmake : bit;
signal trapd : bit;
signal trap_SR : std_logic_vector(7 downto 0);
signal make_trace : std_logic;
signal set_stop : bit;
signal stop : bit;
signal trap_vector : std_logic_vector(31 downto 0);
signal trap_vector_vbr : std_logic_vector(31 downto 0);
signal USP : std_logic_vector(31 downto 0);
signal illegal_write_mode : bit;
signal illegal_read_mode : bit;
signal illegal_byteaddr : bit;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal IPL_vec : std_logic_vector(7 downto 0);
signal interrupt : bit;
signal setinterrupt : bit;
signal SVmode : std_logic;
signal preSVmode : std_logic;
signal Suppress_Base : bit;
signal set_Suppress_Base : bit;
signal set_Z_error : bit;
signal Z_error : bit;
signal ea_build_now : bit;
signal build_logical : bit;
signal build_bcd : bit;
signal data_read : std_logic_vector(31 downto 0);
signal bf_ext_in : std_logic_vector(7 downto 0);
signal bf_ext_out : std_logic_vector(7 downto 0);
signal byte : bit;
signal long_start : bit;
signal long_start_alu : bit;
signal long_done : bit;
signal memmask : std_logic_vector(5 downto 0);
signal set_memmask : std_logic_vector(5 downto 0);
signal memread : std_logic_vector(3 downto 0);
signal wbmemmask : std_logic_vector(5 downto 0);
signal memmaskmux : std_logic_vector(5 downto 0);
signal oddout : std_logic;
signal set_oddout : std_logic;
signal PCbase : std_logic;
signal set_PCbase : std_logic;
signal last_data_read : std_logic_vector(31 downto 0);
signal last_data_in : std_logic_vector(31 downto 0);
signal bf_offset : std_logic_vector(5 downto 0);
signal bf_width : std_logic_vector(5 downto 0);
signal bf_bhits : std_logic_vector(5 downto 0);
signal bf_shift : std_logic_vector(5 downto 0);
signal alu_width : std_logic_vector(5 downto 0);
signal alu_bf_shift : std_logic_vector(5 downto 0);
signal bf_loffset : std_logic_vector(5 downto 0);
signal alu_bf_loffset : std_logic_vector(5 downto 0);
signal movec_data : std_logic_vector(31 downto 0);
signal VBR : std_logic_vector(31 downto 0);
signal CACR : std_logic_vector(3 downto 0);
signal DFC : std_logic_vector(2 downto 0);
signal SFC : std_logic_vector(2 downto 0);
signal set : bit_vector(lastOpcBit downto 0);
signal set_exec : bit_vector(lastOpcBit downto 0);
signal exec : bit_vector(lastOpcBit downto 0);
signal micro_state : micro_states;
signal next_micro_state : micro_states;
BEGIN
ALU: TG68K_ALU
generic map(
MUL_Mode => MUL_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode => DIV_Mode --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
)
port map(
clk => clk, --: in std_logic;
Reset => Reset, --: in std_logic;
clkena_lw => clkena_lw, --: in std_logic:='1';
execOPC => execOPC, --: in bit;
exe_condition => exe_condition, --: in std_logic;
exec_tas => exec_tas, --: in std_logic;
long_start => long_start_alu, --: in bit;
movem_presub => movem_presub, --: in bit;
set_stop => set_stop, --: in bit;
Z_error => Z_error, --: in bit;
rot_bits => rot_bits, --: in std_logic_vector(1 downto 0);
exec => exec, --: in bit_vector(lastOpcBit downto 0);
OP1out => OP1out, --: in std_logic_vector(31 downto 0);
OP2out => OP2out, --: in std_logic_vector(31 downto 0);
reg_QA => reg_QA, --: in std_logic_vector(31 downto 0);
reg_QB => reg_QB, --: in std_logic_vector(31 downto 0);
opcode => opcode, --: in std_logic_vector(15 downto 0);
datatype => datatype, --: in std_logic_vector(1 downto 0);
exe_opcode => exe_opcode, --: in std_logic_vector(15 downto 0);
exe_datatype => exe_datatype, --: in std_logic_vector(1 downto 0);
sndOPC => sndOPC, --: in std_logic_vector(15 downto 0);
last_data_read => last_data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
data_read => data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
FlagsSR => FlagsSR, --: in std_logic_vector(7 downto 0);
micro_state => micro_state, --: in micro_states;
bf_ext_in => bf_ext_in,
bf_ext_out => bf_ext_out,
bf_shift => alu_bf_shift,
bf_width => alu_width,
bf_loffset => alu_bf_loffset(4 downto 0),
set_V_Flag => set_V_Flag, --: buffer bit;
Flags => Flags, --: buffer std_logic_vector(8 downto 0);
c_out => c_out, --: buffer std_logic_vector(2 downto 0);
addsub_q => addsub_q, --: buffer std_logic_vector(31 downto 0);
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
);
long_start_alu <= to_bit(NOT memmaskmux(3));
-----------------------------------------------------------------------------
-- Bus control
-----------------------------------------------------------------------------
nWr <= '0' WHEN state="11" ELSE '1';
busstate <= state;
nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';
memmaskmux <= memmask WHEN addr(0)='1' ELSE memmask(4 downto 0)&'1';
nUDS <= memmaskmux(5);
nLDS <= memmaskmux(4);
clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';
PROCESS (clk, nReset)
BEGIN
IF nReset='0' THEN
syncReset <= "0000";
Reset <= '1';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
syncReset <= syncReset(2 downto 0)&'1';
Reset <= NOT syncReset(3);
END IF;
END IF;
END PROCESS;
PROCESS (clk, long_done, last_data_in, data_in, byte, addr, long_start, memmaskmux, memread, memmask, data_read)
BEGIN
IF memmaskmux(4)='0' THEN
data_read <= last_data_in(15 downto 0)&data_in;
ELSE
data_read <= last_data_in(23 downto 0)&data_in(15 downto 8);
END IF;
IF memread(0)='1' OR (memread(1 downto 0)="10" AND memmaskmux(4)='1')THEN
data_read(31 downto 16) <= (OTHERS=>data_read(15));
END IF;
IF rising_edge(clk) THEN
IF clkena_lw='1' AND state="10" THEN
IF memmaskmux(4)='0' THEN
bf_ext_in <= last_data_in(23 downto 16);
ELSE
bf_ext_in <= last_data_in(31 downto 24);
END IF;
END IF;
IF Reset='1' THEN
last_data_read <= (OTHERS => '0');
ELSIF clkena_in='1' THEN
IF state="00" OR exec(update_ld)='1' THEN
last_data_read <= data_read;
IF state(1)='0' AND memmask(1)='0' THEN
last_data_read(31 downto 16) <= last_opc_read;
ELSIF state(1)='0' OR memread(1)='1' THEN
last_data_read(31 downto 16) <= (OTHERS=>data_in(15));
END IF;
END IF;
last_data_in <= last_data_in(15 downto 0)&data_in(15 downto 0);
END IF;
END IF;
long_start <= to_bit(NOT memmask(1));
long_done <= to_bit(NOT memread(1));
END PROCESS;
PROCESS (byte, long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out,
data_write_muxin, memmask, oddout, addr)
BEGIN
IF exec(write_reg)='1' THEN
data_write_muxin <= reg_QB;
ELSE
data_write_muxin <= data_write_tmp;
END IF;
IF BitField=0 THEN
IF oddout=addr(0) THEN
data_write_mux <= "XXXXXXXX"&"XXXXXXXX"&data_write_muxin;
ELSE
data_write_mux <= "XXXXXXXX"&data_write_muxin&"XXXXXXXX";
END IF;
ELSE
IF oddout=addr(0) THEN
data_write_mux <= "XXXXXXXX"&bf_ext_out&data_write_muxin;
ELSE
data_write_mux <= bf_ext_out&data_write_muxin&"XXXXXXXX";
END IF;
END IF;
IF memmaskmux(1)='0' THEN
data_write <= data_write_mux(47 downto 32);
ELSIF memmaskmux(3)='0' THEN
data_write <= data_write_mux(31 downto 16);
ELSE
data_write <= data_write_mux(15 downto 0);
END IF;
IF exec(mem_byte)='1' THEN --movep
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
PROCESS (clk, regfile, RDindex_A, RDindex_B, exec)
BEGIN
reg_QA <= regfile(RDindex_A);
reg_QB <= regfile(RDindex_B);
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
rf_source_addrd <= rf_source_addr;
WR_AReg <= rf_dest_addr(3);
RDindex_A <= conv_integer(rf_dest_addr(3 downto 0));
RDindex_B <= conv_integer(rf_source_addr(3 downto 0));
IF Wwrena='1' THEN
regfile(RDindex_A) <= regin;
END IF;
IF exec(to_USP)='1' THEN
USP <= reg_QA;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data)
BEGIN
regin <= ALUout;
IF exec(save_memaddr)='1' THEN
regin <= memaddr;
ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN
regin <= memaddr_a;
ELSIF exec(from_USP)='1' THEN
regin <= USP;
ELSIF exec(movec_rd)='1' THEN
regin <= movec_data;
END IF;
IF Bwrena='1' THEN
regin(15 downto 8) <= reg_QA(15 downto 8);
END IF;
IF Lwrena='0' THEN
regin(31 downto 16) <= reg_QA(31 downto 16);
END IF;
Bwrena <= '0';
Wwrena <= '0';
Lwrena <= '0';
IF exec(presub)='1' OR exec(postadd)='1' OR exec(changeMode)='1' THEN -- -(An)+
Wwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena_now='1' THEN --dbcc
Wwrena <= '1';
ELSIF exec(Regwrena)='1' THEN --read (mem)
Wwrena <= '1';
CASE exe_datatype IS
WHEN "00" => --BYTE
Bwrena <= '1';
WHEN "01" => --WORD
IF WR_AReg='1' OR movem_actiond='1' THEN
Lwrena <='1';
END IF;
WHEN OTHERS => --LONG
Lwrena <= '1';
END CASE;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)
BEGIN
IF exec(movem_action) ='1' THEN
rf_dest_addr <= rf_source_addrd;
ELSIF set(briefext)='1' THEN
rf_dest_addr <= brief(15 downto 12);
ELSIF set(get_bfoffset)='1' THEN
rf_dest_addr <= sndOPC(9 downto 6);
ELSIF dest_2ndHbits='1' THEN
rf_dest_addr <= sndOPC(15 downto 12);
ELSIF set(write_reminder)='1' THEN
rf_dest_addr <= sndOPC(3 downto 0);
ELSIF setstackaddr='1' THEN
rf_dest_addr <= "1111";
ELSIF dest_hbits='1' THEN
rf_dest_addr <= dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr <= dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr <= '1'&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits)
BEGIN
IF exec(movem_action)='1' OR set(movem_action) ='1' THEN
IF movem_presub='1' THEN
rf_source_addr <= movem_regaddr XOR "1111";
ELSE
rf_source_addr <= movem_regaddr;
END IF;
ELSIF source_2ndLbits='1' THEN
rf_source_addr <= sndOPC(3 downto 0);
ELSIF source_2ndHbits='1' THEN
rf_source_addr <= sndOPC(15 downto 12);
ELSIF source_lowbits='1' THEN
rf_source_addr <= source_areg&opcode(2 downto 0);
ELSIF exec(linksp)='1' THEN
rf_source_addr <= "1111";
ELSE
rf_source_addr <= source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1out
-----------------------------------------------------------------------------
PROCESS (reg_QA, store_in_tmp, ea_data, long_start, addr, exec, memmaskmux)
BEGIN
OP1out <= reg_QA;
IF exec(OP1out_zero)='1' THEN
OP1out <= (OTHERS => '0');
ELSIF exec(ea_data_OP1)='1' AND store_in_tmp='1' THEN
OP1out <= ea_data;
ELSIF exec(movem_action)='1' OR memmaskmux(3)='0' OR exec(OP1addr)='1' THEN
OP1out <= addr;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2out
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_data,
store_in_tmp, data_write_tmp, ea_data)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF exec(OP2out_one)='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec(opcEXT)='1' THEN
IF exe_opcode(6)='0' OR exe_opcode(8)='1' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN
OP2out <= data_write_tmp;
ELSIF (exec(ea_data_OP1)='0' AND store_in_tmp='1') OR exec(ea_data_OP2)='1' THEN
OP2out <= ea_data;
ELSIF exec(opcMOVEQ)='1' THEN
OP2out(7 downto 0) <= exe_opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => exe_opcode(7));
ELSIF exec(opcADDQ)='1' THEN
OP2out(2 downto 0) <= exe_opcode(11 downto 9);
IF exe_opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF exe_datatype="10" THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- handle EA_data, data_write
-----------------------------------------------------------------------------
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF Reset = '1' THEN
store_in_tmp <='0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF clkena_lw='1' THEN
direct_data <= '0';
IF state="11" THEN
exec_write_back <= '0';
ELSIF setstate="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
ELSIF endOPC='1' THEN
use_direct_data <= '0';
END IF;
exec_DIRECT <= set_exec(opcMOVE);
IF endOPC='1' THEN
store_in_tmp <='0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
IF set_exec(opcMOVE)='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF state="10" THEN
store_in_tmp <= '1';
END IF;
IF direct_data='1' AND state="00" THEN
store_in_tmp <= '1';
END IF;
END IF;
IF state="10" THEN
ea_data <= data_read;
ELSIF exec(get_2ndOPC)='1' THEN
ea_data <= addr;
ELSIF exec(store_ea_data)='1' OR (direct_data='1' AND state="00") THEN
ea_data <= last_data_read;
END IF;
IF writePC='1' THEN
data_write_tmp <= TG68_PC;
ELSIF exec(writePC_add)='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF micro_state=trap0 THEN
data_write_tmp(15 downto 0) <= trap_vector(15 downto 0);
ELSIF exec(hold_dwr)='1' THEN
data_write_tmp <= data_write_tmp;
ELSIF exec(exg)='1' THEN
data_write_tmp <= OP1out;
ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN -- ist for pea
data_write_tmp <= addr;
ELSIF execOPC='1' THEN
data_write_tmp <= ALUout;
ELSIF (exec_DIRECT='1' AND state="10") THEN
data_write_tmp <= data_read;
IF exec(movepl)='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF exec(movepl)='1' THEN
data_write_tmp(15 downto 0) <= reg_QB(31 downto 16);
ELSIF direct_data='1' THEN
data_write_tmp <= last_data_read;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(7 downto 0)& Flags(7 downto 0);
ELSE
data_write_tmp <= OP2out;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
PROCESS (brief, OP1out, OP1outbrief, cpu)
BEGIN
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
briefdata <= OP1outbrief&OP1out(15 downto 0);
IF extAddr_Mode=1 OR (cpu(1)='1' AND extAddr_Mode=2) THEN
CASE brief(10 downto 9) IS
WHEN "00" => briefdata <= OP1outbrief&OP1out(15 downto 0);
WHEN "01" => briefdata <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
WHEN "10" => briefdata <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
WHEN "11" => briefdata <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec,
memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
IF trap_addr_error='1' THEN
trap_vector(7 downto 0) <= X"0C";
END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
IF exec(trap_chk)='1' THEN
trap_vector(7 downto 0) <= X"18";
END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
IF trap_trace='1' THEN
trap_vector(7 downto 0) <= X"24";
END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF trap_interrupt='1' THEN
trap_vector(9 downto 2) <= IPL_vec; --TH
END IF;
-- TH TODO: non-autovector IRQs
END IF;
END IF;
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
trap_vector_vbr <= trap_vector;
ELSE
trap_vector_vbr <= trap_vector+VBR;
END IF;
memaddr_a(4 downto 0) <= "00000";
memaddr_a(7 downto 5) <= (OTHERS=>memaddr_a(4));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF setdisp='1' THEN
IF exec(briefext)='1' THEN
memaddr_a <= briefdata+memaddr_delta;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= last_data_read(7 downto 0);
ELSE
memaddr_a <= last_data_read;
END IF;
ELSIF set(presub)='1' THEN
IF set(longaktion)='1' THEN
memaddr_a(4 downto 0) <= "11100";
ELSIF datatype="00" AND set(use_SP)='0' THEN
memaddr_a(4 downto 0) <= "11111";
ELSE
memaddr_a(4 downto 0) <= "11110";
END IF;
ELSIF interrupt='1' THEN
memaddr_a(4 downto 0) <= '1'&rIPL_nr&'0';
END IF;
IF rising_edge(clk) THEN
IF clkena_in='1' THEN
IF exec(get_2ndOPC)='1' OR (state="10" AND memread(0)='1') THEN
tmp_TG68_PC <= addr;
END IF;
use_base <= '0';
IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN
memaddr_delta <= addsub_q;
ELSIF state="01" AND exec_write_back='1' THEN
memaddr_delta <= tmp_TG68_PC;
ELSIF exec(direct_delta)='1' THEN
memaddr_delta <= data_read;
ELSIF exec(ea_to_pc)='1' AND setstate="00" THEN
memaddr_delta <= addr;
ELSIF set(addrlong)='1' THEN
memaddr_delta <= last_data_read;
ELSIF setstate="00" THEN
memaddr_delta <= TG68_PC_add;
ELSIF exec(dispouter)='1' THEN
memaddr_delta <= ea_data+memaddr_a;
ELSIF set_vectoraddr='1' THEN
memaddr_delta <= trap_vector_vbr;
ELSE
memaddr_delta <= memaddr_a;
IF interrupt='0' AND Suppress_Base='0' THEN
-- IF interrupt='0' AND Suppress_Base='0' AND setstate(1)='1' THEN
use_base <= '1';
END IF;
END IF;
-- IF clkena_in THEN
IF (long_done='0' AND state(1)='1') OR movem_presub='0' THEN
memaddr <= addr;
END IF;
-- END IF;
END IF;
END IF;
addr <= memaddr_reg+memaddr_delta;
IF use_base='0' THEN
memaddr_reg <= (others=>'0');
ELSE
memaddr_reg <= reg_QA;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
BEGIN
PC_dataa <= TG68_PC;
IF TG68_PC_brw = '1' THEN
PC_dataa <= tmp_TG68_PC;
END IF;
PC_datab(2 downto 0) <= (others => '0');
PC_datab(3) <= PC_datab(2);
PC_datab(7 downto 4) <= (others => PC_datab(3));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF interrupt='1' THEN
PC_datab(2 downto 1) <= "11";
END IF;
IF exec(writePC_add) ='1' THEN
IF writePCbig='1' THEN
PC_datab(3) <= '1';
PC_datab(1) <= '1';
ELSE
PC_datab(2) <= '1';
END IF;
IF trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1' THEN
PC_datab(1) <= '1';
END IF;
ELSIF state="00" THEN
PC_datab(1) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
IF TG68_PC_word='1' THEN
PC_datab <= last_data_read;
ELSE
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
setopcode <= '0';
setendOPC <= '0';
setinterrupt <= '0';
IF setstate="00" AND next_micro_state=idle AND setnextpass='0' AND (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" AND set_exec(opcCHK)='0'THEN
setendOPC <= '1';
IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111" OR make_trace='1' THEN
setinterrupt <= '1';
ELSIF stop='0' THEN
setopcode <= '1';
END IF;
END IF;
setexecOPC <= '0';
IF setstate="00" AND next_micro_state=idle AND set_direct_data='0' AND (exec_write_back='0' OR state="10") THEN
setexecOPC <= '1';
END IF;
IPL_nr <= NOT IPL;
IF rising_edge(clk) THEN
IF Reset = '1' THEN
state <= "01";
opcode <= X"2E79"; --move $0,a7
trap_interrupt <= '0';
interrupt <= '0';
last_opc_read <= X"4EF9"; --jmp nn.l
TG68_PC <= X"00000004";
decodeOPC <= '0';
endOPC <= '0';
TG68_PC_word <= '0';
execOPC <= '0';
stop <= '0';
rot_cnt <="000001";
byte <= '0';
-- IPL_nr <= "000";
trap_trace <= '0';
writePCbig <= '0';
-- recall_last <= '0';
Suppress_Base <= '0';
memmask <= "111111";
ELSE
-- IPL_nr <= NOT IPL;
IF clkena_in='1' THEN
memmask <= memmask(3 downto 0)&"11";
memread <= memread(1 downto 0)&memmaskmux(5 downto 4);
-- IF wbmemmask(5 downto 4)="11" THEN
-- wbmemmask <= memmask;
-- END IF;
IF exec(directPC)='1' THEN
TG68_PC <= data_read;
ELSIF exec(ea_to_pc)='1' THEN
TG68_PC <= addr;
ELSIF (state ="00" OR TG68_PC_brw = '1') AND stop='0' THEN
TG68_PC <= TG68_PC_add;
END IF;
END IF;
IF clkena_lw='1' THEN
interrupt <= setinterrupt;
decodeOPC <= setopcode;
endOPC <= setendOPC;
execOPC <= setexecOPC;
exe_datatype <= set_datatype;
exe_opcode <= opcode;
stop <= set_stop OR (stop AND NOT setinterrupt);
IF setinterrupt='1' THEN
IF make_trace='1' THEN
trap_trace <= '1';
ELSE
rIPL_nr <= IPL_nr;
IPL_vec <= "00011"&IPL_nr; -- TH
trap_interrupt <= '1';
END IF;
END IF;
IF micro_state=trap0 AND IPL_autovector='0' THEN
IPL_vec <= last_data_read(7 downto 0); -- TH
END IF;
IF state="00" THEN
last_opc_read <= data_read(15 downto 0);
END IF;
IF setopcode='1' THEN
trap_interrupt <= '0';
trap_trace <= '0';
TG68_PC_word <= '0';
ELSIF opcode(7 downto 0)="00000000" OR opcode(7 downto 0)="11111111" OR data_is_source='1' THEN
TG68_PC_word <= '1';
END IF;
IF exec(get_bfoffset)='1' THEN
alu_width <= bf_width;
alu_bf_shift <= bf_shift;
alu_bf_loffset <= bf_loffset;
END IF;
byte <= '0';
memread <= "1111";
FC(1) <= NOT setstate(1) OR (PCbase AND NOT setstate(0));
FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
IF interrupt='1' THEN
FC(1 downto 0) <= "11";
END IF;
IF (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
state <= "01";
memmask <= "111111";
ELSIF execOPC='1' AND exec_write_back='1' THEN
state <= "11";
FC(1 downto 0) <= "01";
memmask <= wbmemmask;
IF datatype="00" THEN
byte <= '1';
END IF;
ELSE
state <= setstate;
IF setstate="01" THEN
memmask <= "111111";
wbmemmask <= "111111";
ELSIF exec(get_bfoffset)='1' THEN
memmask <= set_memmask;
wbmemmask <= set_memmask;
oddout <= set_oddout;
ELSIF set(longaktion)='1' THEN
memmask <= "100001";
wbmemmask <= "100001";
oddout <= '0';
ELSIF set_datatype="00" AND setstate(1)='1' THEN
memmask <= "101111";
wbmemmask <= "101111";
IF set(mem_byte)='1' THEN
oddout <= '0';
ELSE
oddout <= '1';
END IF;
ELSE
memmask <= "100111";
wbmemmask <= "100111";
oddout <= '0';
END IF;
END IF;
IF decodeOPC='1' THEN
rot_bits <= set_rot_bits;
writePCbig <= '0';
ELSE
writePCbig <= set_writePCbig OR writePCbig;
END IF;
IF decodeOPC='1' OR exec(ld_rot_cnt)='1' OR rot_cnt/="000001" THEN
rot_cnt <= set_rot_cnt;
END IF;
IF setstate(1)='1' AND set_datatype="00" THEN
byte <= '1';
END IF;
IF set_Suppress_Base='1' THEN
Suppress_Base <= '1';
ELSIF setstate(1)='1' OR (ea_only='1' AND set(get_ea_now)='1') THEN
Suppress_Base <= '0';
END IF;
IF getbrief='1' THEN
IF state(1)='1' THEN
brief <= last_opc_read(15 downto 0);
ELSE
brief <= data_read(15 downto 0);
END IF;
END IF;
IF setopcode='1' THEN
IF state="00" THEN
opcode <= data_read(15 downto 0);
ELSE
opcode <= last_opc_read(15 downto 0);
END IF;
nextpass <= '0';
ELSIF setinterrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "001"; --word
nextpass <= '0';
ELSE
-- IF setnextpass='1' OR (regdirectsource='1' AND state="00") THEN
IF setnextpass='1' OR regdirectsource='1' THEN
nextpass <= '1';
END IF;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= FlagsSR;
END IF;
END IF;
END IF;
END IF;
IF rising_edge(clk) THEN
IF Reset = '1' THEN
PCbase <= '1';
ELSIF clkena_lw='1' THEN
PCbase <= set_PCbase OR PCbase;
IF setexecOPC='1' OR (state(1)='1' AND movem_run='0') THEN
PCbase <= '0';
END IF;
END IF;
IF clkena_lw='1' THEN
exec <= set;
exec_tas <= '0';
exec(subidx) <= set(presub) or set(subidx);
IF setexecOPC='1' THEN
exec <= set_exec OR set;
exec_tas <= set_exec_tas;
END IF;
exec(get_2ndOPC) <= set(get_2ndOPC) OR setopcode;
END IF;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--prepare Bitfield Parameters
------------------------------------------------------------------------------
PROCESS (clk, Reset, sndOPC, reg_QA, reg_QB, bf_width, bf_offset, bf_bhits, opcode, setstate, bf_shift)
BEGIN
IF sndOPC(11)='1' THEN
bf_offset <= '0'®_QA(4 downto 0);
ELSE
bf_offset <= '0'&sndOPC(10 downto 6);
END IF;
bf_width(5) <= '0';
IF sndOPC(5)='1' THEN
bf_width(4 downto 0) <= reg_QB(4 downto 0)-1;
ELSE
bf_width(4 downto 0) <= sndOPC(4 downto 0)-1;
END IF;
bf_bhits <= bf_width+bf_offset;
set_oddout <= NOT bf_bhits(3);
IF opcode(10 downto 8)="111" THEN --INS
bf_loffset <= 32-bf_shift;
ELSE
bf_loffset <= bf_shift;
END IF;
bf_loffset(5) <= '0';
IF opcode(4 downto 3)="00" THEN
IF opcode(10 downto 8)="111" THEN --INS
bf_shift <= bf_bhits+1;
ELSE
bf_shift <= 31-bf_bhits;
END IF;
bf_shift(5) <= '0';
ELSE
IF opcode(10 downto 8)="111" THEN --INS
bf_shift <= "011"&("001"+bf_bhits(2 downto 0));
ELSE
bf_shift <= "000"&("111"-bf_bhits(2 downto 0));
END IF;
bf_offset(4 downto 3) <= "00";
END IF;
CASE bf_bhits(5 downto 3) IS
WHEN "000" =>
set_memmask <= "101111";
WHEN "001" =>
set_memmask <= "100111";
WHEN "010" =>
set_memmask <= "100011";
WHEN "011" =>
set_memmask <= "100001";
WHEN OTHERS =>
set_memmask <= "100000";
END CASE;
IF setstate="00" THEN
set_memmask <= "100111";
END IF;
END PROCESS;
------------------------------------------------------------------------------
--SR op
------------------------------------------------------------------------------
PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
BEGIN
IF exec(andiSR)='1' THEN
SRin <= FlagsSR AND last_data_read(15 downto 8);
ELSIF exec(eoriSR)='1' THEN
SRin <= FlagsSR XOR last_data_read(15 downto 8);
ELSIF exec(oriSR)='1' THEN
SRin <= FlagsSR OR last_data_read(15 downto 8);
ELSE
SRin <= OP2out(15 downto 8);
END IF;
IF rising_edge(clk) THEN
IF Reset='1' THEN
FlagsSR(5) <= '1';
FC(2) <= '1';
SVmode <= '1';
preSVmode <= '1';
FlagsSR(2 downto 0) <= "111";
make_trace <= '0';
ELSIF clkena_lw = '1' THEN
IF setopcode='1' THEN
make_trace <= FlagsSR(7);
IF set(changeMode)='1' THEN
SVmode <= NOT SVmode;
ELSE
SVmode <= preSVmode;
END IF;
END IF;
IF set(changeMode)='1' THEN
preSVmode <= NOT preSVmode;
FlagsSR(5) <= NOT preSVmode;
FC(2) <= NOT preSVmode;
END IF;
IF micro_state=trap3 THEN
FlagsSR(7) <= '0';
END IF;
IF trap_trace='1' AND state="10" THEN
make_trace <= '0';
END IF;
IF exec(directSR)='1' OR set_stop='1' THEN
FlagsSR <= data_read(15 downto 8);
END IF;
IF interrupt='1' AND trap_interrupt='1' THEN
FlagsSR(2 downto 0) <=rIPL_nr;
END IF;
-- IF exec(to_CCR)='1' AND exec(to_SR)='1' THEN
IF exec(to_SR)='1' THEN
FlagsSR(7 downto 0) <= SRin; --SR
FC(2) <= SRin(5);
-- END IF;
ELSIF exec(update_FC)='1' THEN
FC(2) <= FlagsSR(5);
END IF;
IF interrupt='1' THEN
FC(2) <= '1';
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- decode opcode
-----------------------------------------------------------------------------
PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr,
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB)
BEGIN
TG68_PC_brw <= '0';
setstate <= "00";
Regwrena_now <= '0';
movem_presub <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
getbrief <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
ea_build_now <= '0';
set_rot_bits <= "XX";
set_rot_cnt <= "000001";
dest_hbits <= '0';
source_lowbits <= '0';
source_2ndHbits <= '0';
source_2ndLbits <= '0';
dest_2ndHbits <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_exec_tas <= '0';
trap_illegal <='0';
trap_addr_error <= '0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_stop <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
set_Z_error <= '0';
next_micro_state <= idle;
build_logical <= '0';
build_bcd <= '0';
skipFetch <= '0';
set_writePCbig <= '0';
-- set_recall_last <= '0';
set_Suppress_Base <= '0';
set_PCbase <= '0';
IF rot_cnt/="000001" THEN
set_rot_cnt <= rot_cnt-1;
END IF;
set_datatype <= datatype;
set <= (OTHERS=>'0');
set_exec <= (OTHERS=>'0');
set(update_ld) <= '0';
-- odd_start <= '0';
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap0;
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
set(writePC_add) <= '1';
-- set_datatype <= "10";
END IF;
IF preSVmode='0' THEN
set(changeMode) <= '1';
END IF;
setstate <= "01";
END IF;
IF micro_state=int1 OR (interrupt='1' AND trap_trace='1') THEN
next_micro_state <= trap0;
-- IF cpu(0)='0' THEN
-- set_datatype <= "10";
-- END IF;
IF preSVmode='0' THEN
set(changeMode) <= '1';
END IF;
setstate <= "01";
END IF;
IF setexecOPC='1' AND FlagsSR(5)/=preSVmode THEN
set(changeMode) <= '1';
-- setstate <= "01";
-- next_micro_state <= nop;
END IF;
IF interrupt='1' AND trap_interrupt='1'THEN
-- skipFetch <= '1';
next_micro_state <= int1;
set(update_ld) <= '1';
setstate <= "10";
END IF;
IF set(changeMode)='1' THEN
set(to_USP) <= '1';
set(from_USP) <= '1';
setstackaddr <='1';
END IF;
IF ea_only='0' AND set(get_ea_now)='1' THEN
setstate <= "10";
-- set_recall_last <= '1';
-- set(update_ld) <= '0';
END IF;
IF setstate(1)='1' AND set_datatype(1)='1' THEN
set(longaktion) <= '1';
END IF;
IF (ea_build_now='1' AND decodeOPC='1') OR exec(ea_build)='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
set(get_ea_now) <='1';
setnextpass <= '1';
IF opcode(3)='1' THEN --(An)+
set(postadd) <= '1';
IF opcode(2 downto 0)="111" THEN
set(use_SP) <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
set(presub) <= '1';
IF opcode(2 downto 0)="111" THEN
set(use_SP) <= '1';
END IF;
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
getbrief <='1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
set(longaktion) <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
set(dispouter) <= '1';
set_Suppress_Base <= '1';
set_PCbase <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
getbrief <= '1';
set(dispouter) <= '1';
set_Suppress_Base <= '1';
set_PCbase <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
set(longaktion) <= '1';
END IF;
WHEN OTHERS => NULL;
END CASE;
WHEN OTHERS => NULL;
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
set(use_SP) <= '1'; --addr+2
set(no_Flags) <='1';
IF opcode(7)='0' THEN --to register
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <= '1';
set(movepl) <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(6)='1' THEN
set(movepl) <= '1';
END IF;
IF opcode(7)='0' THEN
set_direct_data <= '1'; -- to register
END IF;
next_micro_state <= movep1;
END IF;
IF setexecOPC='1' THEN
dest_hbits <='1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN --Bits
set_exec(opcBITS) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(7 downto 6)/="00" THEN
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
write_back <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
END IF;
IF opcode(8)='0' THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
ELSE
ea_build_now <= '1';
END IF;
ELSIF opcode(11 downto 9)="111" THEN --MOVES not in 68000
trap_illegal <= '1';
-- trap_addr_error <= '1';
trapmake <= '1';
ELSE --andi, ...xxxi
IF opcode(11 downto 9)="000" THEN --ORI
set_exec(opcOR) <= '1';
END IF;
IF opcode(11 downto 9)="001" THEN --ANDI
set_exec(opcAND) <= '1';
END IF;
IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN --SUBI, ADDI
set_exec(opcADD) <= '1';
END IF;
IF opcode(11 downto 9)="101" THEN --EORI
set_exec(opcEOR) <= '1';
END IF;
IF opcode(11 downto 9)="110" THEN --CMPI
set_exec(opcCMP) <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN --SR
IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
set(no_Flags) <= '1';
IF decodeOPC='1' THEN
IF opcode(6)='1' THEN
set(to_SR) <= '1';
END IF;
set(to_CCR) <= '1';
set(andiSR) <= set_exec(opcAND);
set(eoriSR) <= set_exec(opcEOR);
set(oriSR) <= set_exec(opcOR);
setstate <= "01";
next_micro_state <= nopnop;
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
next_micro_state <= andi;
set(ea_build) <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
set(longaktion) <= '1';
END IF;
END IF;
IF opcode(5 downto 4)/="00" THEN
set_exec(ea_data_OP1) <= '1';
END IF;
IF opcode(11 downto 9)/="110" THEN --CMPI
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
write_back <= '1';
END IF;
IF opcode(10 downto 9)="10" THEN --CMPI, SUBI
set(addsub) <= '1';
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec(opcMOVE) <= '1';
ea_build_now <= '1';
IF opcode(8 downto 6)="001" THEN
set(no_Flags) <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
IF opcode(8 downto 7)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF nextpass='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
-- IF setstate="10" THEN
-- set(update_ld) <= '0';
-- END IF;
--
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
WHEN "000"|"001" => --Dn,An
set_exec(Regwrena) <= '1';
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(6)='1' THEN --(An)+
set(postadd) <= '1';
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
set(presub) <= '1';
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
END IF;
END IF;
setstate <= "11";
next_micro_state <= nop;
IF nextpass='0' THEN
set(write_reg) <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
-- getbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
getbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
set(longaktion) <= '1';
next_micro_state <= st_nn;
WHEN OTHERS => NULL;
END CASE;
WHEN OTHERS => NULL;
END CASE;
END IF;
---- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
source_lowbits <= '1';
-- IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
IF opcode(5 downto 4)="00" THEN --extb.l
set_exec(opcEXT) <= '1';
set_exec(opcMOVE) <= '1';
set_exec(Regwrena) <= '1';
-- IF opcode(6)='0' THEN
-- datatype <= "01"; --WORD
-- END IF;
ELSE
source_areg <= '1';
ea_only <= '1';
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <='1';
set(no_Flags) <='1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
dest_areg <= '1';
dest_hbits <= '1';
ELSE
ea_build_now <= '1';
END IF;
IF set(get_ea_now)='1' THEN
setstate <= "01";
set_direct_data <= '1';
END IF;
IF setexecOPC='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
datatype <= "01"; --Word
set(trap_chk) <= '1';
IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
END IF;
ELSIF cpu(1)='1' THEN --chk long for 68020
datatype <= "10"; --Long
set(trap_chk) <= '1';
IF (c_out(2)='1' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
IF opcode(7)='1' OR cpu(1)='1' THEN
IF (nextpass='1' OR opcode(5 downto 4)="00") AND exec(opcCHK)='0' AND micro_state=idle THEN
set_exec(opcCHK) <= '1';
END IF;
ea_build_now <= '1';
set(addsub) <= '1';
IF setexecOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
END IF;
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF opcode(7 downto 6)="11" THEN --move from SR
IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1' THEN
-- IF SVmode='1' THEN
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --negx
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "00";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --clr
ea_build_now <= '1';
write_back <='1';
set_exec(opcAND) <= '1';
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
WHEN "010"=>
ea_build_now <= '1';
IF opcode(7 downto 6)="11" THEN --move to CCR
datatype <= "01";
source_lowbits <= '1';
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
set(to_CCR) <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
ea_build_now <= '1';
datatype <= "01";
source_lowbits <= '1';
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
set(to_SR) <= '1';
set(to_CCR) <= '1';
END IF;
IF exec(to_SR)='1' OR (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
setstate <="01";
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
ea_build_now <= '1';
write_back <='1';
set_exec(opcEOR) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(5 downto 3)="000" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP2out_one) <= '1';
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
set_exec(opcEXT) <= '1';
set_exec(opcMOVE) <= '1';
set_exec(Regwrena) <= '1';
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
set(no_Flags) <= '1';
IF opcode(6)='0' THEN
datatype <= "01"; --Word transfer
END IF;
IF (opcode(5 downto 3)="100" OR opcode(5 downto 3)="011") AND state="01" THEN -- -(An), (An)+
set_exec(save_memaddr) <= '1';
set_exec(Regwrena) <= '1';
END IF;
IF opcode(5 downto 3)="100" THEN -- -(An)
movem_presub <= '1';
set(subidx) <= '1';
END IF;
IF state="10" THEN
set(Regwrena) <= '1';
set(opcMOVE) <= '1';
END IF;
IF decodeOPC='1' THEN
set(get_2ndOPC) <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
next_micro_state <= movem1;
ELSE
next_micro_state <= nop;
set(ea_build) <= '1';
END IF;
END IF;
IF set(get_ea_now)='1' THEN
IF movem_run='1' THEN
set(movem_action) <= '1';
IF opcode(10)='0' THEN
setstate <="11";
set(write_reg) <= '1';
ELSE
setstate <="10";
END IF;
next_micro_state <= movem2;
set(mem_addsub) <= '1';
ELSE
setstate <="01";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL.L, DIV.L 68020
-- IF cpu(1)='1' THEN
IF (opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
(opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1')THEN
setstate <="01";
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
IF opcode(6)='1' THEN
next_micro_state <= div1;
ELSE
next_micro_state <= mul1;
set(ld_rot_cnt) <= '1';
END IF;
END IF;
IF z_error='0' AND set_V_Flag='0' AND set(opcDIVU)='1' THEN
set(Regwrena) <= '1';
END IF;
source_lowbits <='1';
IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
dest_hbits <= '1';
END IF;
datatype <= "10";
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
set_exec(opcSWAP) <= '1';
set_exec(Regwrena) <= '1';
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
ea_build_now <= '1';
IF nextpass='1' AND micro_state=idle THEN
set(presub) <= '1';
setstackaddr <='1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF set(get_ea_now)='1' THEN
setstate <="01";
END IF;
END IF;
ELSE
IF opcode(5 downto 3)="001" THEN --link.l
datatype <= "10";
set_exec(opcADD) <= '1'; --for displacement
set_exec(Regwrena) <= '1';
set(no_Flags) <= '1';
IF decodeOPC='1' THEN
set(linksp) <= '1';
set(longaktion) <= '1';
next_micro_state <= link1;
set(presub) <= '1';
setstackaddr <='1';
set(mem_addsub) <= '1';
source_lowbits <= '1';
source_areg <= '1';
set(store_ea_data) <= '1';
END IF;
ELSE --nbcd
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
--
WHEN "101"=> --tst, tas 4aFC - illegal
IF opcode(7 downto 2)="111111" THEN --illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
ea_build_now <= '1';
IF setexecOPC='1' THEN
source_lowbits <= '1';
IF opcode(3)='1' THEN --MC68020...
source_areg <= '1';
END IF;
END IF;
set_exec(opcMOVE) <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
END IF;
---- WHEN "110"=>
WHEN "111"=> --4EXX
--
-- ea_only <= '1';
-- ea_build_now <= '1';
-- IF nextpass='1' AND micro_state=idle THEN
-- set(presub) <= '1';
-- setstackaddr <='1';
-- set(mem_addsub) <= '1';
-- setstate <="11";
-- next_micro_state <= nop;
-- END IF;
-- IF set(get_ea_now)='1' THEN
-- setstate <="01";
-- END IF;
--
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
ea_build_now <= '1';
IF exec(ea_to_pc)='1' THEN
next_micro_state <= nop;
END IF;
IF nextpass='1' AND micro_state=idle AND opcode(6)='0' THEN
set(presub) <= '1';
setstackaddr <='1';
setstate <="11";
next_micro_state <= nopnop;
END IF;
-- achtung buggefahr
IF micro_state=ld_AnXn1 AND brief(8)='0'THEN --JMP/JSR n(Ax,Dn)
skipFetch <= '1';
END IF;
IF state="00" THEN
writePC <= '1';
END IF;
set(hold_dwr) <= '1';
IF set(get_ea_now)='1' THEN --jsr
IF exec(longaktion)='0' OR long_done='1' THEN
skipFetch <= '1';
END IF;
setstate <="01";
set(ea_to_pc) <= '1';
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=> --link
datatype <= "10";
set_exec(opcADD) <= '1'; --for displacement
set_exec(Regwrena) <= '1';
set(no_Flags) <= '1';
IF decodeOPC='1' THEN
next_micro_state <= link1;
set(presub) <= '1';
setstackaddr <='1';
set(mem_addsub) <= '1';
source_lowbits <= '1';
source_areg <= '1';
set(store_ea_data) <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <= '1';
set(no_Flags) <= '1';
IF decodeOPC='1' THEN
setstate <= "01";
next_micro_state <= unlink1;
set(opcMOVE) <= '1';
set(Regwrena) <= '1';
setstackaddr <='1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
-- set(no_Flags) <= '1';
set(to_USP) <= '1';
source_lowbits <= '1';
source_areg <= '1';
datatype <= "10";
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
-- set(no_Flags) <= '1';
set(from_USP) <= '1';
datatype <= "10";
set_exec(Regwrena) <= '1';
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
set(opcRESET) <= '1';
IF decodeOPC='1' THEN
set(ld_rot_cnt) <= '1';
set_rot_cnt <= "000000";
END IF;
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_stop <= '1';
END IF;
IF stop='1' THEN
skipFetch <= '1';
END IF;
END IF;
WHEN "1110011"|"1110111" => --rte/rtr
IF SVmode='1' OR opcode(2)='1' THEN
IF decodeOPC='1' THEN
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
IF opcode(2)='1' THEN
set(directCCR) <= '1';
ELSE
set(directSR) <= '1';
END IF;
next_micro_state <= rte1;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
set(direct_delta) <= '1';
set(directPC) <= '1';
next_micro_state <= nopnop;
END IF;
WHEN "1110110" => --trapv
IF decodeOPC='1' THEN
setstate <= "01";
END IF;
IF Flags(1)='1' AND state="01" THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1111010"|"1111011" => --movec
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
trap_illegal <= '1';
trapmake <= '1';
ELSIF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
datatype <= "10"; --Long
IF last_data_read(11 downto 0)=X"800" THEN
set(from_USP) <= '1';
IF opcode(0)='1' THEN
set(to_USP) <= '1';
END IF;
END IF;
IF opcode(0)='0' THEN
set_exec(movec_rd) <= '1';
ELSE
set_exec(movec_wr) <= '1';
END IF;
IF decodeOPC='1' THEN
next_micro_state <= movec1;
getbrief <='1';
END IF;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
--
---- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
IF decodeOPC='1' THEN
next_micro_state <= dbcc1;
set(OP2out_one) <= '1';
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
ea_build_now <= '1';
write_back <= '1';
set_exec(opcScc) <= '1';
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
ELSE --addq, subq
ea_build_now <= '1';
IF opcode(5 downto 3)="001" THEN
set(no_Flags) <= '1';
END IF;
IF opcode(8)='1' THEN
set(addsub) <= '1';
END IF;
write_back <= '1';
set_exec(opcADDQ) <= '1';
set_exec(opcADD) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
--
---- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
set(presub) <= '1';
setstackaddr <='1';
IF opcode(7 downto 0)="11111111" THEN
next_micro_state <= bsr2;
set(longaktion) <= '1';
ELSIF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr2;
ELSE
next_micro_state <= bsr1;
setstate <= "11";
writePC <= '1';
END IF;
ELSE --bra
IF opcode(7 downto 0)="11111111" THEN
next_micro_state <= bra1;
set(longaktion) <= '1';
ELSIF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
ELSE
setstate <= "01";
next_micro_state <= bra1;
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
-- IF opcode(8)='0' THEN -- Cloanto's Amiga Forver ROMs have mangled movq instructions with a 1 here...
IF trap_interrupt='0' AND trap_trace='0' THEN
datatype <= "10"; --Long
set_exec(Regwrena) <= '1';
set_exec(opcMOVEQ) <= '1';
set_exec(opcMOVE) <= '1';
dest_hbits <= '1';
END IF;
-- ELSE
-- trap_illegal <= '1';
-- trapmake <= '1';
-- END IF;
---- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF DIV_Mode/=3 THEN
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
setstate <="01";
next_micro_state <= div1;
END IF;
ea_build_now <= '1';
IF z_error='0' AND set_V_Flag='0' THEN
set_exec(Regwrena) <= '1';
END IF;
source_lowbits <='1';
IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
dest_hbits <= '1';
END IF;
datatype <= "01";
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
build_bcd <= '1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec(opcOR) <= '1';
build_logical <= '1';
END IF;
---- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec(opcADD) <= '1';
ea_build_now <= '1';
IF opcode(14)='0' THEN
set(addsub) <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN -- --adda, suba
IF opcode(8)='0' THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
set_exec(Regwrena) <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
set(no_Flags) <= '1';
IF setexecOPC='1' THEN
dest_areg <='1';
dest_hbits <= '1';
END IF;
ELSE
IF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --addx, subx
build_bcd <= '1';
ELSE --sub, add
build_logical <= '1';
END IF;
END IF;
--
---- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
---- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
ea_build_now <= '1';
IF opcode(7 downto 6)="11" THEN --CMPA
IF opcode(8)='0' THEN --cmpa.w
datatype <= "01"; --Word
set_exec(opcCPMAW) <= '1';
END IF;
set_exec(opcCMP) <= '1';
IF setexecOPC='1' THEN
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
dest_areg <='1';
dest_hbits <= '1';
END IF;
set(addsub) <= '1';
ELSE
IF opcode(8)='1' THEN
IF opcode(5 downto 3)="001" THEN --cmpm
set_exec(opcCMP) <= '1';
IF decodeOPC='1' THEN
setstate <= "10";
set(update_ld) <= '1';
set(postadd) <= '1';
next_micro_state <= cmpm;
END IF;
set_exec(ea_data_OP1) <= '1';
set(addsub) <= '1';
ELSE --EOR
build_logical <= '1';
set_exec(opcEOR) <= '1';
END IF;
ELSE --CMP
build_logical <= '1';
set_exec(opcCMP) <= '1';
set(addsub) <= '1';
END IF;
END IF;
--
---- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF MUL_Mode/=3 THEN
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
setstate <="01";
set(ld_rot_cnt) <= '1';
next_micro_state <= mul1;
END IF;
ea_build_now <= '1';
set_exec(Regwrena) <= '1';
source_lowbits <='1';
IF (nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
dest_hbits <= '1';
END IF;
datatype <= "01";
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
build_bcd <= '1';
set_exec(opcADD) <= '1';
set_exec(opcABCD) <= '1';
ELSE --exg
datatype <= "10";
set(Regwrena) <= '1';
set(exg) <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
setstate <= "01";
ELSE
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec(opcAND) <= '1';
build_logical <= '1';
END IF;
--
---- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation / bitfield
IF opcode(7 downto 6)="11" THEN
IF opcode(11)='0' THEN
set_exec(opcROT) <= '1';
ea_build_now <= '1';
datatype <= "01";
set_rot_bits <= opcode(10 downto 9);
set_exec(ea_data_OP1) <= '1';
write_back <= '1';
ELSE --bitfield
IF BitField=0 OR (cpu(1)='0' AND BitField=2) THEN
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
set_exec(opcBF) <= '1';
IF opcode(10)='1' OR opcode(8)='0' THEN
set_exec(opcBFwb) <= '1';
-- END IF;
-- IF opcode(10 downto 8)="111" THEN
set_exec(ea_data_OP1) <= '1';
END IF;
IF opcode(10 downto 8)="010" OR opcode(10 downto 8)="100" OR opcode(10 downto 8)="110" OR opcode(10 downto 8)="111" THEN
write_back <= '1';
END IF;
ea_only <= '1';
IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN
set_exec(Regwrena) <= '1';
END IF;
IF opcode(4 downto 3)="00" THEN
set_exec(Regwrena) <= '1';
IF exec(ea_build)='1' THEN
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
set(get_bfoffset) <='1';
setstate <= "01";
END IF;
END IF;
IF set(get_ea_now)='1' THEN
setstate <= "01";
END IF;
IF exec(get_ea_now)='1' THEN
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
set(get_bfoffset) <='1';
setstate <= "01";
set(mem_addsub) <='1';
next_micro_state <= bf1;
END IF;
-- BFINS D1,D0 s2ndHbits <<D1 -> D0
-- BFEXT D0,D1 sLbits >>D0 -> D1 d2ndHbits
-- BFINS D1,(A0) s2ndHbits <<D1 -> (A0)
-- BFEXT (A0),D1 >>(A0) -> D1 d2ndHbits
IF setexecOPC='1' THEN
IF opcode(10 downto 8)="111" THEN --BFINS
source_2ndHbits <= '1';
ELSE
source_lowbits <= '1';
dest_2ndHbits <= '1';
END IF;
END IF;
END IF;
END IF;
ELSE
set_exec(opcROT) <= '1';
set_rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
set_exec(Regwrena) <= '1';
IF decodeOPC='1' THEN
IF opcode(5)='1' THEN
next_micro_state <= rota1;
set(ld_rot_cnt) <= '1';
setstate <= "01";
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
--
---- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- use for AND, OR, EOR, CMP
IF build_logical='1' THEN
ea_build_now <= '1';
IF set_exec(opcCMP)='0' AND (opcode(8)='0' OR opcode(5 downto 4)="00" ) THEN
set_exec(Regwrena) <= '1';
END IF;
IF opcode(8)='1' THEN
write_back <= '1';
set_exec(ea_data_OP1) <= '1';
ELSE
source_lowbits <='1';
IF opcode(3)='1' THEN --use for cmp
source_areg <= '1';
END IF;
IF setexecOPC='1' THEN
dest_hbits <= '1';
END IF;
END IF;
END IF;
-- use for ABCD, SBCD
IF build_bcd='1' THEN
set_exec(use_XZFlag) <= '1';
set_exec(ea_data_OP1) <= '1';
write_back <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
IF decodeOPC='1' THEN
setstate <= "10";
set(update_ld) <= '1';
set(presub) <= '1';
next_micro_state <= op_AxAy;
dest_areg <= '1'; --???
END IF;
ELSE
dest_hbits <= '1';
set_exec(Regwrena) <= '1';
END IF;
END IF;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
IF set_Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig for USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
IF rising_edge(clk) THEN
IF Reset='1' THEN
micro_state <= ld_nn;
ELSIF clkena_lw='1' THEN
trapd <= trapmake;
micro_state <= next_micro_state;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
set(get_ea_now) <='1';
setnextpass <= '1';
set(addrlong) <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
set(addrlong) <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
set(get_ea_now) <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
IF brief(8)='0' OR extAddr_Mode=0 OR (cpu(1)='0' AND extAddr_Mode=2) THEN
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
set(briefext) <= '1';
next_micro_state <= ld_AnXn2;
ELSE
IF brief(7)='1'THEN --suppress Base
set_suppress_base <= '1';
ELSIF exec(dispouter)='1' THEN
set(dispouter) <= '1';
END IF;
IF brief(5)='0' THEN --NULL Base Displacement
setstate <= "01";
ELSE --WORD Base Displacement
IF brief(4)='1' THEN
set(longaktion) <= '1'; --LONG Base Displacement
END IF;
END IF;
next_micro_state <= ld_229_1;
END IF;
WHEN ld_AnXn2 =>
set(get_ea_now) <='1';
setdisp <= '1'; --brief
setnextpass <= '1';
-------------------------------------------------------------------------------------
WHEN ld_229_1 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
IF brief(5)='1' THEN --Base Displacement
setdisp <= '1'; --add last_data_read
END IF;
IF brief(6)='0' AND brief(2)='0' THEN --Preindex or Index
set(briefext) <= '1';
setstate <= "01";
IF brief(1 downto 0)="00" THEN
next_micro_state <= ld_AnXn2;
ELSE
next_micro_state <= ld_229_2;
END IF;
ELSE
IF brief(1 downto 0)="00" THEN
set(get_ea_now) <='1';
setnextpass <= '1';
ELSE
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= ld_229_3;
END IF;
END IF;
WHEN ld_229_2 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
setdisp <= '1'; -- add Index
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= ld_229_3;
WHEN ld_229_3 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
set_suppress_base <= '1';
set(dispouter) <= '1';
IF brief(1)='0' THEN --NULL Outer Displacement
setstate <= "01";
ELSE --WORD Outer Displacement
IF brief(0)='1' THEN
set(longaktion) <= '1'; --LONG Outer Displacement
END IF;
END IF;
next_micro_state <= ld_229_4;
WHEN ld_229_4 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
IF brief(1)='1' THEN -- Outer Displacement
setdisp <= '1'; --add last_data_read
END IF;
IF brief(6)='0' AND brief(2)='1' THEN --Postindex
set(briefext) <= '1';
setstate <= "01";
next_micro_state <= ld_AnXn2;
ELSE
set(get_ea_now) <='1';
setnextpass <= '1';
END IF;
----------------------------------------------------------------------------------------
WHEN st_dAn1 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
IF brief(8)='0' OR extAddr_Mode=0 OR (cpu(1)='0' AND extAddr_Mode=2) THEN
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
set(briefext) <= '1';
next_micro_state <= st_AnXn2;
ELSE
IF brief(7)='1'THEN --suppress Base
set_suppress_base <= '1';
-- ELSIF exec(dispouter)='1' THEN
-- set(dispouter) <= '1';
END IF;
IF brief(5)='0' THEN --NULL Base Displacement
setstate <= "01";
ELSE --WORD Base Displacement
IF brief(4)='1' THEN
set(longaktion) <= '1'; --LONG Base Displacement
END IF;
END IF;
next_micro_state <= st_229_1;
END IF;
WHEN st_AnXn2 =>
setstate <= "11";
setdisp <= '1'; --brief
next_micro_state <= nop;
-------------------------------------------------------------------------------------
WHEN st_229_1 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
IF brief(5)='1' THEN --Base Displacement
setdisp <= '1'; --add last_data_read
END IF;
IF brief(6)='0' AND brief(2)='0' THEN --Preindex or Index
set(briefext) <= '1';
setstate <= "01";
IF brief(1 downto 0)="00" THEN
next_micro_state <= st_AnXn2;
ELSE
next_micro_state <= st_229_2;
END IF;
ELSE
IF brief(1 downto 0)="00" THEN
setstate <= "11";
next_micro_state <= nop;
ELSE
set(hold_dwr) <= '1';
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= st_229_3;
END IF;
END IF;
WHEN st_229_2 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
setdisp <= '1'; -- add Index
set(hold_dwr) <= '1';
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= st_229_3;
WHEN st_229_3 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
set(hold_dwr) <= '1';
set_suppress_base <= '1';
set(dispouter) <= '1';
IF brief(1)='0' THEN --NULL Outer Displacement
setstate <= "01";
ELSE --WORD Outer Displacement
IF brief(0)='1' THEN
set(longaktion) <= '1'; --LONG Outer Displacement
END IF;
END IF;
next_micro_state <= st_229_4;
WHEN st_229_4 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
set(hold_dwr) <= '1';
IF brief(1)='1' THEN -- Outer Displacement
setdisp <= '1'; --add last_data_read
END IF;
IF brief(6)='0' AND brief(2)='1' THEN --Postindex
set(briefext) <= '1';
setstate <= "01";
next_micro_state <= st_AnXn2;
ELSE
setstate <= "11";
next_micro_state <= nop;
END IF;
----------------------------------------------------------------------------------------
WHEN bra1 => --bra
IF exe_condition='1' THEN
TG68_PC_brw <= '1'; --pc+0000
next_micro_state <= nop;
skipFetch <= '1';
END IF;
WHEN bsr1 => --bsr short
TG68_PC_brw <= '1';
next_micro_state <= nop;
WHEN bsr2 => --bsr
IF long_start='0' THEN
TG68_PC_brw <= '1';
END IF;
skipFetch <= '1';
set(longaktion) <= '1';
writePC <= '1';
setstate <= "11";
next_micro_state <= nopnop;
setstackaddr <='1';
WHEN nopnop => --bsr
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
IF exe_condition='0' THEN
Regwrena_now <= '1';
IF c_out(1)='1' THEN
skipFetch <= '1';
next_micro_state <= nop;
TG68_PC_brw <= '1';
END IF;
END IF;
WHEN movem1 => --movem
IF last_data_read(15 downto 0)/=X"0000" THEN
setstate <="01";
IF opcode(5 downto 3)="100" THEN
set(mem_addsub) <= '1';
END IF;
next_micro_state <= movem2;
END IF;
WHEN movem2 => --movem
IF movem_run='0' THEN
setstate <="01";
ELSE
set(movem_action) <= '1';
set(mem_addsub) <= '1';
next_micro_state <= movem2;
IF opcode(10)='0' THEN
setstate <="11";
set(write_reg) <= '1';
ELSE
setstate <="10";
END IF;
END IF;
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
set_direct_data <= '1';
set(presub) <= '1';
dest_hbits <= '1';
dest_areg <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
set_direct_data <= '1';
set(postadd) <= '1';
dest_hbits <= '1';
dest_areg <= '1';
setstate <= "10";
WHEN link1 => -- link
setstate <="11";
source_areg <= '1';
set(opcMOVE) <= '1';
set(Regwrena) <= '1';
next_micro_state <= link2;
WHEN link2 => -- link
setstackaddr <='1';
set(ea_data_OP2) <= '1';
WHEN unlink1 => -- unlink
setstate <="10";
setstackaddr <='1';
set(postadd) <= '1';
next_micro_state <= unlink2;
WHEN unlink2 => -- unlink
set(ea_data_OP2) <= '1';
WHEN trap0 => -- TRAP
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN --68010
set(writePC_add) <= '1';
datatype <= "01";
-- set_datatype <= "10";
next_micro_state <= trap1;
ELSE
IF trap_interrupt='1' OR trap_trace='1' THEN
writePC <= '1';
END IF;
datatype <= "10";
next_micro_state <= trap2;
END IF;
WHEN trap1 => -- TRAP
IF trap_interrupt='1' OR trap_trace='1' THEN
writePC <= '1';
END IF;
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
datatype <= "10";
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set(direct_delta) <= '1';
set(directPC) <= '1';
setstate <= "10";
next_micro_state <= nopnop;
WHEN rte1 => -- RTE
datatype <= "10";
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
set(direct_delta) <= '1';
END IF;
set(directPC) <= '1';
next_micro_state <= rte2;
WHEN rte2 => -- RTE
datatype <= "01";
set(update_FC) <= '1';
IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
next_micro_state <= rte3;
ELSE
next_micro_state <= nop;
END IF;
WHEN rte3 => -- RTE
next_micro_state <= nop;
-- set(update_FC) <= '1';
WHEN movec1 => -- MOVEC
set(briefext) <= '1';
set_writePCbig <='1';
IF (brief(11 downto 0)=X"000" OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"800" OR brief(11 downto 0)=X"801") OR
(cpu(1)='1' AND (brief(11 downto 0)=X"002" OR brief(11 downto 0)=X"802" OR brief(11 downto 0)=X"803" OR brief(11 downto 0)=X"804")) THEN
IF opcode(0)='0' THEN
set(Regwrena) <= '1';
END IF;
-- ELSIF brief(11 downto 0)=X"800"OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"000" THEN
-- trap_addr_error <= '1';
-- trapmake <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
WHEN movep1 => -- MOVEP d(An)
setdisp <= '1';
set(mem_addsub) <= '1';
set(mem_byte) <= '1';
set(OP1addr) <= '1';
IF opcode(6)='1' THEN
set(movepl) <= '1';
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
IF opcode(6)='1' THEN
set(mem_addsub) <= '1';
set(OP1addr) <= '1';
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set(mem_addsub) <= '1';
set(OP1addr) <= '1';
set(mem_byte) <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
next_micro_state <= movep4;
ELSE
datatype <= "01"; --Word
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
datatype <= "10"; --Long
WHEN mul1 => -- mulu
IF opcode(15)='1' OR MUL_Mode=0 THEN
set_rot_cnt <= "001110";
ELSE
set_rot_cnt <= "011110";
END IF;
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
setstate <="01";
IF rot_cnt="00001" THEN
next_micro_state <= mul_end1;
ELSE
next_micro_state <= mul2;
END IF;
WHEN mul_end1 => -- mulu
datatype <= "10";
set(opcMULU) <= '1';
IF opcode(15)='0' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
dest_2ndHbits <= '1';
source_2ndLbits <= '1';--???
set(write_lowlong) <= '1';
IF sndOPC(10)='1' THEN
setstate <="01";
next_micro_state <= mul_end2;
END IF;
set(Regwrena) <= '1';
END IF;
datatype <= "10";
WHEN mul_end2 => -- divu
set(write_reminder) <= '1';
set(Regwrena) <= '1';
set(opcMULU) <= '1';
WHEN div1 => -- divu
setstate <="01";
next_micro_state <= div2;
WHEN div2 => -- divu
IF (OP2out(31 downto 16)=x"0000" OR opcode(15)='1' OR DIV_Mode=0) AND OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
next_micro_state <= div3;
END IF;
set(ld_rot_cnt) <= '1';
setstate <="01";
WHEN div3 => -- divu
IF opcode(15)='1' OR DIV_Mode=0 THEN
set_rot_cnt <= "001101";
ELSE
set_rot_cnt <= "011101";
END IF;
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
setstate <="01";
IF rot_cnt="00001" THEN
next_micro_state <= div_end1;
ELSE
next_micro_state <= div4;
END IF;
WHEN div_end1 => -- divu
IF opcode(15)='0' AND (DIV_Mode=1 OR DIV_Mode=2) THEN
set(write_reminder) <= '1';
next_micro_state <= div_end2;
setstate <="01";
END IF;
set(opcDIVU) <= '1';
datatype <= "10";
WHEN div_end2 => -- divu
dest_2ndHbits <= '1';
source_2ndLbits <= '1';--???
set(opcDIVU) <= '1';
WHEN rota1 =>
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_exec(rot_nop) <= '1';
END IF;
WHEN bf1 =>
setstate <="10";
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- MOVEC
-----------------------------------------------------------------------------
PROCESS (clk, VBR, CACR, brief)
BEGIN
IF rising_edge(clk) THEN
IF Reset = '1' THEN
VBR <= (OTHERS => '0');
CACR <= (OTHERS => '0');
ELSIF clkena_lw='1' AND exec(movec_wr)='1' THEN
CASE brief(11 downto 0) IS
WHEN X"002" => CACR <= reg_QA(3 downto 0);
WHEN X"801" => VBR <= reg_QA;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
movec_data <= (OTHERS=>'0');
CASE brief(11 downto 0) IS
WHEN X"002" => movec_data(3 downto 0) <= CACR;
WHEN X"801" => --IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN
movec_data <= VBR;
--END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
VBR_out <= VBR;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (exe_opcode, Flags)
BEGIN
CASE exe_opcode(11 downto 8) IS
WHEN X"0" => exe_condition <= '1';
WHEN X"1" => exe_condition <= '0';
WHEN X"2" => exe_condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => exe_condition <= Flags(0) OR Flags(2);
WHEN X"4" => exe_condition <= NOT Flags(0);
WHEN X"5" => exe_condition <= Flags(0);
WHEN X"6" => exe_condition <= NOT Flags(2);
WHEN X"7" => exe_condition <= Flags(2);
WHEN X"8" => exe_condition <= NOT Flags(1);
WHEN X"9" => exe_condition <= Flags(1);
WHEN X"a" => exe_condition <= NOT Flags(3);
WHEN X"b" => exe_condition <= Flags(3);
WHEN X"c" => exe_condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => exe_condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => exe_condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => exe_condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
movem_actiond <= exec(movem_action);
IF decodeOPC='1' THEN
sndOPC <= data_read(15 downto 0);
ELSIF exec(movem_action)='1' OR set(movem_action) ='1' THEN
CASE movem_regaddr IS
WHEN "0000" => sndOPC(0) <= '0';
WHEN "0001" => sndOPC(1) <= '0';
WHEN "0010" => sndOPC(2) <= '0';
WHEN "0011" => sndOPC(3) <= '0';
WHEN "0100" => sndOPC(4) <= '0';
WHEN "0101" => sndOPC(5) <= '0';
WHEN "0110" => sndOPC(6) <= '0';
WHEN "0111" => sndOPC(7) <= '0';
WHEN "1000" => sndOPC(8) <= '0';
WHEN "1001" => sndOPC(9) <= '0';
WHEN "1010" => sndOPC(10) <= '0';
WHEN "1011" => sndOPC(11) <= '0';
WHEN "1100" => sndOPC(12) <= '0';
WHEN "1101" => sndOPC(13) <= '0';
WHEN "1110" => sndOPC(14) <= '0';
WHEN "1111" => sndOPC(15) <= '0';
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (sndOPC, movem_mux)
BEGIN
movem_regaddr <="0000";
movem_run <= '1';
IF sndOPC(3 downto 0)="0000" THEN
IF sndOPC(7 downto 4)="0000" THEN
movem_regaddr(3) <= '1';
IF sndOPC(11 downto 8)="0000" THEN
IF sndOPC(15 downto 12)="0000" THEN
movem_run <= '0';
END IF;
movem_regaddr(2) <= '1';
movem_mux <= sndOPC(15 downto 12);
ELSE
movem_mux <= sndOPC(11 downto 8);
END IF;
ELSE
movem_mux <= sndOPC(7 downto 4);
movem_regaddr(2) <= '1';
END IF;
ELSE
movem_mux <= sndOPC(3 downto 0);
END IF;
IF movem_mux(1 downto 0)="00" THEN
movem_regaddr(1) <= '1';
IF movem_mux(2)='0' THEN
movem_regaddr(0) <= '1';
END IF;
ELSE
IF movem_mux(0)='0' THEN
movem_regaddr(0) <= '1';
END IF;
END IF;
END PROCESS;
END;
|
gpl-3.0
|
e92a524861587fcf6b4f0e387f3fc84b
| 0.489376 | 3.099316 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/IF.vhd
| 2 | 5,729 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:55:24 10/26/2009
-- Design Name:
-- Module Name: IF - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Description: The instruction fetch stage of the OZ-3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.30 - File written and checked for syntax
-- Need to check, strange results during simulation
-- Revision 0.90 - Successfully simulated, changed instruction registers to falling edge triggered
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity IFetch is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
condition_flag_from_EX : in STD_LOGIC;
PC_new_addr_from_EX : in STD_LOGIC_VECTOR(31 downto 0);
iROM_data : in STD_LOGIC_VECTOR(15 downto 0);
iROM_addr : out STD_LOGIC_VECTOR(22 downto 0);
dbl_clk : out STD_LOGIC;
instruction_to_ID : out STD_LOGIC_VECTOR(31 downto 0));
end IFetch;
architecture Behavioral of IFetch is
--//Component Declarations\\--
component GenReg is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
component GenRegFalling is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Component Declarations//--
--//Signal Declarations\\--
signal double_clk : STD_LOGIC;
signal buf_double_clk : STD_LOGIC;
signal PC_addr_to_load : STD_LOGIC_VECTOR(22 downto 0);
signal incremented_addr : STD_LOGIC_VECTOR(22 downto 0);
signal PC_out : STD_LOGIC_VECTOR(22 downto 0);
signal inst_reg2_e : STD_LOGIC;
signal instruction_1 : STD_LOGIC_VECTOR(15 downto 0);
signal instruction_2 : STD_LOGIC_VECTOR(15 downto 0);
signal alt_addr_reg_sig : STD_LOGIC_VECTOR(32 downto 0);
signal alt_addr_reg_out : STD_LOGIC_VECTOR(32 downto 0);
signal alt_addr_reg_e : STD_LOGIC;
signal alt_addr_reg_r : STD_LOGIC;
--\\Signal Declarations//--
begin
--//Clock Management\\--
DCM_CPU_clk : DCM --Doubles the main CPU clock
-- The following generics are only necessary if you wish to change the default behavior.
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 3200.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => double_clk, -- DCM CLK synthesis out (M/D)
CLKIN => clock -- Clock input (from IBUFG, BUFG or DCM)
);
BUFG_double_clk : BUFG
port map (
O => buf_double_clk,
I => double_clk
);
--\\Clock Management//--
PC_new_addr_cntl: process (alt_addr_reg_out, incremented_addr) is
begin
if (alt_addr_reg_out(32) = '1') then
PC_addr_to_load <= alt_addr_reg_out(22 downto 0);
else
PC_addr_to_load <= incremented_addr;
end if;
end process;
PC: GenReg generic map (23)
port map (buf_double_clk, '1', reset, PC_addr_to_load, PC_out);
--I threw this register in to delay the new address by one half-cycle, so the instructions don't
--get garbled
AltAddrReg : GenRegFalling generic map (33)
port map (buf_double_clk, alt_addr_reg_e, alt_addr_reg_r, alt_addr_reg_sig, alt_addr_reg_out);
Inst_reg_1 : GenRegFalling generic map (16)
port map (buf_double_clk, inst_reg2_e, reset, iROM_data, instruction_1);
Inst_reg_2 : GenRegFalling generic map (16)
port map (buf_double_clk, clock, reset, iROM_data, instruction_2);
alt_addr_reg_r <= (reset or clock);
alt_addr_reg_e <= (not clock);
alt_addr_reg_sig <= (condition_flag_from_EX & PC_new_addr_from_EX);
iROM_addr <= PC_out;
instruction_to_ID <= (instruction_2 & instruction_1);
dbl_clk <= buf_double_clk;
incremented_addr <= (PC_out + b"00000000000000000000001");
inst_reg2_e <= (not clock);
end Behavioral;
|
mit
|
b2010fe8326370a0c227ab12ffb8ecb1
| 0.611974 | 3.40404 | false | false | false | false |
fpga-logi/logi-hard
|
test_bench/sseg_tb.vhd
| 2 | 3,487 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:59:38 03/26/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/sseg_tb.vhd
-- Project Name: logi_edu_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: wishbone_7seg4x
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sseg_tb IS
END sseg_tb;
ARCHITECTURE behavior OF sseg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wishbone_7seg4x
PORT(
gls_reset : IN std_logic;
gls_clk : IN std_logic;
wbs_address : IN std_logic_vector(15 downto 0);
wbs_writedata : IN std_logic_vector(15 downto 0);
wbs_readdata : OUT std_logic_vector(15 downto 0);
wbs_strobe : IN std_logic;
wbs_cycle : IN std_logic;
wbs_write : IN std_logic;
wbs_ack : OUT std_logic;
sseg_edu_cathode_out : OUT std_logic_vector(4 downto 0);
sseg_edu_anode_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal gls_reset : std_logic := '0';
signal gls_clk : std_logic := '0';
signal wbs_address : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_strobe : std_logic := '0';
signal wbs_cycle : std_logic := '0';
signal wbs_write : std_logic := '0';
--Outputs
signal wbs_readdata : std_logic_vector(15 downto 0);
signal wbs_ack : std_logic;
signal sseg_edu_cathode_out : std_logic_vector(4 downto 0);
signal sseg_edu_anode_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant gls_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: wishbone_7seg4x PORT MAP (
gls_reset => gls_reset,
gls_clk => gls_clk,
wbs_address => wbs_address,
wbs_writedata => wbs_writedata,
wbs_readdata => wbs_readdata,
wbs_strobe => wbs_strobe,
wbs_cycle => wbs_cycle,
wbs_write => wbs_write,
wbs_ack => wbs_ack,
sseg_edu_cathode_out => sseg_edu_cathode_out,
sseg_edu_anode_out => sseg_edu_anode_out
);
-- Clock process definitions
gls_clk_process :process
begin
gls_clk <= '0';
wait for gls_clk_period/2;
gls_clk <= '1';
wait for gls_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
gls_reset <= '1' ;
wait for 100 ns;
gls_reset <= '0' ;
wait for gls_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
855d66b144d6f4daf979cee3e29b9ce7
| 0.596215 | 3.62474 | false | true | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altfp_mult/_primary.vhd
| 1 | 1,963 |
library verilog;
use verilog.vl_types.all;
entity altfp_mult is
generic(
width_exp : integer := 8;
width_man : integer := 23;
dedicated_multiplier_circuitry: string := "AUTO";
reduced_functionality: string := "NO";
pipeline : integer := 5;
denormal_support: string := "YES";
exception_handling: string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult";
LATENCY : vl_notype;
WIDTH_MAN_EXP : vl_notype
);
port(
clock : in vl_logic;
clk_en : in vl_logic;
aclr : in vl_logic;
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
result : out vl_logic_vector;
overflow : out vl_logic;
underflow : out vl_logic;
zero : out vl_logic;
denormal : out vl_logic;
indefinite : out vl_logic;
nan : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_exp : constant is 1;
attribute mti_svvh_generic_type of width_man : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of reduced_functionality : constant is 1;
attribute mti_svvh_generic_type of pipeline : constant is 1;
attribute mti_svvh_generic_type of denormal_support : constant is 1;
attribute mti_svvh_generic_type of exception_handling : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of LATENCY : constant is 3;
attribute mti_svvh_generic_type of WIDTH_MAN_EXP : constant is 3;
end altfp_mult;
|
bsd-2-clause
|
014e7d08703e2b28605461ae39ecc12a
| 0.57514 | 3.965657 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_v6/example_design/pulse_regen_v6_top.vhd
| 1 | 5,367 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_v6_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_v6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pulse_regen_v6_top;
architecture xilinx of pulse_regen_v6_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_v6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pulse_regen_v6 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
e225cb1372cc19238fee9f4f7cbe01c7
| 0.498044 | 4.618761 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altddio_bidir/_primary.vhd
| 1 | 2,017 |
library verilog;
use verilog.vl_types.all;
entity altddio_bidir is
generic(
width : integer := 1;
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable: string := "UNUSED";
implement_input_in_lcell: string := "UNUSED";
invert_output : string := "OFF";
intended_device_family: string := "Stratix";
lpm_type : string := "altddio_bidir";
lpm_hint : string := "UNUSED"
);
port(
datain_h : in vl_logic_vector;
datain_l : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
outclock : in vl_logic;
outclocken : in vl_logic;
aset : in vl_logic;
aclr : in vl_logic;
sset : in vl_logic;
sclr : in vl_logic;
oe : in vl_logic;
dataout_h : out vl_logic_vector;
dataout_l : out vl_logic_vector;
combout : out vl_logic_vector;
oe_out : out vl_logic_vector;
dqsundelayedout : out vl_logic_vector;
padio : inout vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_high : constant is 1;
attribute mti_svvh_generic_type of oe_reg : constant is 1;
attribute mti_svvh_generic_type of extend_oe_disable : constant is 1;
attribute mti_svvh_generic_type of implement_input_in_lcell : constant is 1;
attribute mti_svvh_generic_type of invert_output : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end altddio_bidir;
|
bsd-2-clause
|
8917a4e4aa6b2d0a012cbe0f63710e7b
| 0.549331 | 3.80566 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/peripheral_template.vhd
| 2 | 3,222 |
-- add you license code here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.logi_utils_pack.all ;
entity <component_name> is
generic(wb_size : positive := 16 ;
memory_size : positive := <your component size in memory>
-- add your component generic parameters starting from here
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- add your component interfaces starting from here
);
end <component_name>;
architecture RTL of <component_name>
signal read_ack : std_logic ;
signal write_ack: std_logic ;
signal component_write, component_read : std_logic ;
signal component_addr : std_logic_vector(nbit(memory_size)-1 downto 0);
signal component_write_data, component_read_data: std_logic_vector(wb_size-1 downto 0);
--declare your component signals here
begin
wbs_ack <= read_ack or write_ack;
component_write <= wbs_strobe and wbs_write and wbs_cycle ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if (component_write = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
component_read <= (wbs_strobe and (not wbs_write) and wbs_cycle) ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0' ;
wbs_readdata <= (others => '0');
elsif rising_edge(gls_clk) then
wbs_readdata <= component_read_data ;
if component_read = '1' then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
component_addr <= wbs_address(nbit(memory_size)-1 downto 0);
component_write_data <= wbs_writedata;
-- insert your component code starting from here
-- use the signal component to control your logic
-- here is an example of a 32bit counter that is controlled by the wishbone bus
-- writing at address 0 will change the value of the 16 lower bits while writing to address
-- will change the 16 upper bits
--counter_bloc : process(gls_clk, gls_reset)
--begin
-- if gls_reset = '1' then
-- component_count_low <= (others => '0');
-- component_count_high <= (others => '0');
-- elsif rising_edge(gls_clk) then
-- if write_component = '1' and component_addr = 0 then
-- component_count_high <= component_write_data ;
-- else
-- component_count_high <= component_count_high + 1 ;
-- end if ;
-- if write_component = '1' and component_addr = 1 then
-- component_count_high <= component_write_data ;
-- elsif component_count_high = X"FFFF" then
-- component_count_high <= component_count_high + 1 ;
-- end if ;
-- end if;
--end process counter_bloc;
--component_read_data <= component_count ;
end RTL ;
|
lgpl-3.0
|
213bd20833dbde0ea9524a6dd8e4fbf7
| 0.641837 | 3.370293 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.vhd
| 1 | 11,934 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(74-1 DOWNTO 0);
DOUT : OUT std_logic_vector(74-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg;
|
gpl-3.0
|
6c5f679ab3dc65ade251ee2dc5e68c46
| 0.513658 | 3.860886 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_control.vhd
| 1 | 33,800 |
-- *********************************************************************
-- Copyright 2011, ON Semiconductor Corporation.
--
-- This software is owned by ON Semiconductor Corporation (ON)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of ON.
--
-- Disclaimer: ON makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. ON reserves the right to make changes without further
-- notice to the materials described herein. ON does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. ON's products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the ON Software License Agreement.
--
-- *********************************************************************
-- File : $URL: http://whatever.euro.cypress.com/repos/ff_te/VHDL/LIB/modules/Iserdes/trunk/iserdes_control.vhd $
-- Author : $Author: bert.dewil $
-- Department : CISP
-- Date : $Date: 2011-05-02 09:00:53 +0200 (ma, 02 mei 2011) $
-- Revision : $Revision: 917 $
-- *********************************************************************
-- Description
--
-- This code controls the training of the individual SERDES modules
--
-- *********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
library work;
use work.all;
--xilinx:
---------
-- synopsys translate_off
Library XilinxCoreLib;
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity iserdes_control is
generic (
NROF_CONN : integer; --16 bits
DATAWIDTH : integer;
RETRY_MAX : integer; --16 bits, global
STABLE_COUNT : integer; -- x bits,
TAP_COUNT_MAX : integer;
INVERSE_BITORDER : boolean
);
port(
CLOCK : in std_logic;
RESET : in std_logic;
ALIGN_START : in std_logic;
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
AUTOALIGN : in std_logic; --when 0 use manual tap setting as an override for the bitalign/wordalign
--when 1
TRAINING : in std_logic_vector(DATAWIDTH-1 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
-- status info
EDGE_DETECT : out std_logic_vector(NROF_CONN-1 downto 0);
TRAINING_DETECT : out std_logic_vector(NROF_CONN-1 downto 0);
STABLE_DETECT : out std_logic_vector(NROF_CONN-1 downto 0);
FIRST_EDGE_FOUND : out std_logic_vector(NROF_CONN-1 downto 0);
SECOND_EDGE_FOUND : out std_logic_vector(NROF_CONN-1 downto 0);
NROF_RETRIES : out std_logic_vector((16*NROF_CONN)-1 downto 0);
TAP_SETTING : out std_logic_vector((10*NROF_CONN)-1 downto 0);
BIT_WIDTH : out std_logic_vector((10*NROF_CONN)-1 downto 0);
WINDOW_WIDTH : out std_logic_vector((10*NROF_CONN)-1 downto 0);
WORD_ALIGN : out std_logic_vector(NROF_CONN-1 downto 0);
TIMEOUTONACK : out std_logic;
-- to sync
REQ : out std_logic;
ACK : in std_logic;
CTRL_SEL : out std_logic_vector(15 downto 0);
CTRL_RESET : out std_logic;
CTRL_INC : out std_logic;
CTRL_CE : out std_logic;
CTRL_BITSLIP : out std_logic;
CTRL_DATA : in std_logic_vector(DATAWIDTH-1 downto 0);
CTRL_SAMPLEINFIRSTBIT : out std_logic_vector(NROF_CONN-1 downto 0);
CTRL_SAMPLEINLASTBIT : out std_logic_vector(NROF_CONN-1 downto 0);
CTRL_SAMPLEINOTHERBIT : out std_logic_vector(NROF_CONN-1 downto 0);
CTRL_FIFO_RESET : out std_logic
);
end iserdes_control;
architecture rtl of iserdes_control is
type handshakestatetp is ( Idle,
WaitAckHigh,
WaitAckLow
);
signal handshakestate : handshakestatetp;
type serdesseqstatetp is ( --ResetFifo,
Idle,
TrainSerdes,
WaitTrainSerdesBusyOn,
WaitTrainSerdesBusyOff
);
signal serdesseqstate : serdesseqstatetp;
type alignstatetp is ( Idle,
Reset_Delay,
Wait_Reset_Delay,
Get_Edge,
Check_Edge,
Wait_Sample_Stable,
Compare_Training,
Valid_Begin_Found,
CheckFirstEdgeChanged,
CheckFirstEdgeStable,
CheckSecondEdgeChanged,
WindowFound,
Reset_Delay_Man,
Start_Word_Align,
Do_Word_Align,
Alignment_Done
);
signal alignstate : alignstatetp;
signal edge_int : std_logic_vector(DATAWIDTH-1 downto 0);
signal edge_init : std_logic_vector(DATAWIDTH-1 downto 0);
signal data_init : std_logic_vector(DATAWIDTH-1 downto 0);
signal edge_int_or : std_logic;
type comparetp is array (0 to DATAWIDTH-1) of std_logic_vector(DATAWIDTH-1 downto 0);
signal compare : comparetp;
signal Maxcount : std_logic_vector(10 downto 0);
signal tapcount : std_logic_vector(9 downto 0);
signal windowcount : std_logic_vector(9 downto 0);
signal bitcount : std_logic_vector(9 downto 0);
signal start_align_i : std_logic;
signal done_align_i : std_logic;
signal busy_align_i : std_logic;
signal SerdesCntr : std_logic_vector(15 downto 0);
signal selector : std_logic_vector(15 downto 0);
signal CTRL_SAMPLEINFIRSTBIT_i : std_logic;
signal CTRL_SAMPLEINLASTBIT_i : std_logic;
signal CTRL_SAMPLEINOTHERBIT_i : std_logic;
signal start_handshake : std_logic;
signal end_handshake : std_logic;
signal retrycntr : std_logic_vector(15 downto 0);
signal retries : std_logic_vector(15 downto 0);
constant retry_count_load : std_logic_vector(15 downto 0) := std_logic_vector(TO_UNSIGNED((RETRY_MAX-2),(retrycntr'high+1)));
signal GenCntr : std_logic_vector(15 downto 0);
constant StableCntrLoad : std_logic_vector(GenCntr'high downto 0) := std_logic_vector(TO_UNSIGNED((STABLE_COUNT-2),(GenCntr'high+1)));
constant TimeOutCntrLd : std_logic_vector(5 downto 0) := "011111" ;
signal TimeOutCntr : std_logic_vector(5 downto 0);
begin
gen_edge_detect: for i in 0 to (DATAWIDTH-2) generate
edge_int(i) <= CTRL_DATA(i) xor CTRL_DATA(i+1);
end generate;
edge_int(DATAWIDTH-1) <= CTRL_DATA(0) xor CTRL_DATA(DATAWIDTH-1);
edgeprocess: process(CLOCK)
variable edge_tmp : std_logic := '0';
begin
if (CLOCK'event and CLOCK = '1') then
-- funny workaround to make OR-ing of parametrisable signals into one signal work
if (start_handshake = '1') then
edge_tmp := '0';
else
for i in 0 to DATAWIDTH-1 loop
edge_tmp := edge_tmp or edge_int(i);
end loop;
edge_int_or <= edge_tmp;
end if;
end if;
end process;
handshaker: process(RESET, CLOCK)
begin
if (RESET = '1') then
REQ <= '0';
end_handshake <= '0';
handshakestate <= Idle;
TIMEOUTONACK <= '0';
TimeOutCntr <= TimeOutCntrLd;
elsif (CLOCK'EVENT and CLOCK = '1') then
-- defaults
end_handshake <= '0';
case handshakestate is
when Idle =>
if ALIGN_START='1'then
TIMEOUTONACK <= '0';
TimeOutCntr <= TimeOutCntrLd;
end if;
if (start_handshake = '1') then
REQ <= '1';
handshakestate <= WaitAckHigh;
end if;
when WaitAckHigh =>
if (ACK = '1') then
REQ <= '0';
handshakestate <= WaitAckLow;
TimeOutCntr <= TimeOutCntrLd;
elsif(TimeOutCntr(TimeOutCntr'high) = '1') then
TIMEOUTONACK <= '1';
handshakestate <= Idle;
TimeOutCntr <= TimeOutCntrLd;
end_handshake <= '1';
else
TimeOutCntr <= TimeOutCntr - '1' ;
end if;
when WaitAckLow =>
if (ACK = '0') then
end_handshake <= '1';
handshakestate <= Idle;
TimeOutCntr <= TimeOutCntrLd;
elsif(TimeOutCntr(TimeOutCntr'high) = '1') then
TIMEOUTONACK <= '1';
handshakestate <= Idle;
TimeOutCntr <= TimeOutCntrLd;
end_handshake <= '1';
else
TimeOutCntr <= TimeOutCntr - '1';
end if;
when others =>
handshakestate <= Idle;
end case;
end if;
end process handshaker;
CTRL_SEL <= selector;
alignsequencer: process(RESET, CLOCK)
begin
if (RESET = '1') then
selector <= (others => '0');
SerdesCntr <= std_logic_vector(TO_SIGNED(3,(SerdesCntr'high+1)));
ALIGN_BUSY <= '0';
ALIGNED <= '0';
start_align_i <= '0';
CTRL_FIFO_RESET <= '1';
CTRL_SAMPLEINFIRSTBIT <= (others => '0');
CTRL_SAMPLEINLASTBIT <= (others => '0');
CTRL_SAMPLEINOTHERBIT <= (others => '0');
serdesseqstate <= Idle;
elsif (CLOCK'EVENT and CLOCK = '1') then
start_align_i <= '0';
case serdesseqstate is
when Idle =>
--CTRL_FIFO_RESET <= '0';
if (ALIGN_START = '1') then
CTRL_FIFO_RESET <= '1';
ALIGN_BUSY <= '1';
start_align_i <= '1';
SerdesCntr <= std_logic_vector(TO_SIGNED((NROF_CONN-2),(SerdesCntr'high+1)));
selector <= (others => '0');
serdesseqstate <= TrainSerdes;
end if;
when TrainSerdes =>
serdesseqstate <= WaitTrainSerdesBusyOn;
when WaitTrainSerdesBusyOn =>
if (busy_align_i = '1') then
serdesseqstate <= WaitTrainSerdesBusyOff;
end if;
when WaitTrainSerdesBusyOff =>
if (busy_align_i = '0') then
CTRL_SAMPLEINFIRSTBIT(TO_INTEGER(UNSIGNED(selector))) <= CTRL_SAMPLEINFIRSTBIT_i;
CTRL_SAMPLEINLASTBIT(TO_INTEGER(UNSIGNED(selector))) <= CTRL_SAMPLEINLASTBIT_i;
CTRL_SAMPLEINOTHERBIT(TO_INTEGER(UNSIGNED(selector))) <= CTRL_SAMPLEINOTHERBIT_i;
if (SerdesCntr(SerdesCntr'high) = '1') then
ALIGNED <= '1';
ALIGN_BUSY <= '0';
CTRL_FIFO_RESET <= '0';
serdesseqstate <= Idle;
else
start_align_i <= '1';
selector <= selector + '1';
SerdesCntr <= SerdesCntr - '1';
serdesseqstate <= TrainSerdes;
end if;
end if;
when others =>
serdesseqstate <= Idle;
end case;
end if;
end process alignsequencer;
aligning: process(RESET, CLOCK)
variable index : integer range 0 to 65535;
begin
if (RESET = '1') then
done_align_i <= '0';
busy_align_i <= '0';
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
CTRL_BITSLIP <= '0';
CTRL_SAMPLEINFIRSTBIT_i <= '0';
CTRL_SAMPLEINLASTBIT_i <= '0';
CTRL_SAMPLEINOTHERBIT_i <= '0';
edge_init <= (others => '0');
data_init <= (others => '0');
EDGE_DETECT <= (others => '0');
TRAINING_DETECT <= (others => '0');
STABLE_DETECT <= (others => '0');
FIRST_EDGE_FOUND <= (others => '0');
SECOND_EDGE_FOUND <= (others => '0');
WORD_ALIGN <= (others => '0');
NROF_RETRIES <= (others => '0');
TAP_SETTING <= (others => '0');
WINDOW_WIDTH <= (others => '0');
start_handshake <= '0';
maxcount <= (others => '1');
tapcount <= (others => '0');
windowcount <= (others => '0');
bitcount <= (others => '0');
retries <= (others => '0');
compare <= (others => (others => '0'));
RetryCntr <= (others => '1');
GenCntr <= (others => '1');
index := 0;
alignstate <= Idle;
elsif (CLOCK'event and CLOCK = '1') then
--defaults
done_align_i <= '0';
start_handshake <= '0';
index := TO_INTEGER(UNSIGNED(selector));
-- generate compare words
-- the 2 last versions will be the 'special' words that when stable sampling
-- occurs on both of them the resulting parallel words will be skewed.
-- In this case the data written into the FIFO has to be compensated for the skew
--
for i in 0 to (DATAWIDTH-1) loop
compare(i) <= STD_LOGIC_VECTOR(UNSIGNED(TRAINING) ROL (i+6));
end loop;
case alignstate is
when Idle =>
busy_align_i <= '0';
if (start_align_i = '1') then
busy_align_i <= '1';
--reset status words
EDGE_DETECT(index) <= '0';
TRAINING_DETECT(index) <= '0';
STABLE_DETECT(index) <= '0';
FIRST_EDGE_FOUND(index) <= '0';
SECOND_EDGE_FOUND(index) <= '0';
WORD_ALIGN(index) <= '0';
NROF_RETRIES((16*index)+15 downto 16*index) <= (others => '0');
TAP_SETTING((10*index)+9 downto 10*index) <= (others => '0');
WINDOW_WIDTH((10*index)+9 downto 10*index) <= (others => '0');
tapcount <= (others => '0');
windowcount <= (others => '0');
bitcount <= (others => '0');
Maxcount <= std_logic_vector(TO_UNSIGNED((TAP_COUNT_MAX-1),(Maxcount'high+1)));
retries <= (others => '0');
RetryCntr <= retry_count_load;
if (AUTOALIGN = '1') then -- use training algorithm
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
start_handshake <= '1';
CTRL_SAMPLEINFIRSTBIT_i <= '0';
CTRL_SAMPLEINLASTBIT_i <= '0';
CTRL_SAMPLEINOTHERBIT_i <= '0';
alignstate <= Reset_Delay;
else -- manually set tapcount
start_handshake <= '1';
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
GenCntr <= "000000" & MANUAL_TAP;
CTRL_SAMPLEINFIRSTBIT_i <= '0';
CTRL_SAMPLEINLASTBIT_i <= '0';
CTRL_SAMPLEINOTHERBIT_i <= '0';
alignstate <= Reset_Delay_Man;
end if;
end if;
when Reset_Delay =>
GenCntr <= std_logic_vector(TO_UNSIGNED((STABLE_COUNT-1),(GenCntr'high+1)));
if (end_handshake = '1') then
alignstate <= Wait_Reset_Delay;
end if;
when Wait_Reset_Delay =>
start_handshake <= '1';
--do nothing
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
alignstate <= Get_Edge;
when Get_Edge =>
if (end_handshake = '1') then
EDGE_DETECT(index) <= edge_int_or;
alignstate <= Check_Edge;
end if;
when Check_Edge =>
if (RetryCntr(RetryCntr'high) = '1') then -- no stable edge found within retry limit
NROF_RETRIES((16*index)+15 downto 16*index) <= retries;
TAP_SETTING((10*index)+9 downto 10*index) <= tapcount;
alignstate <= Idle;
else
RetryCntr <= RetryCntr - '1';
if (edge_int_or = '1') then -- edge found, check stability
DATA_init <= CTRL_DATA; -- memorize data
edge_init <= edge_int; -- memorize data edges
start_handshake <= '1';
--do nothing
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
alignstate <= Wait_Sample_Stable;
else
start_handshake <= '1'; -- no edge found but retrylimit not yet reached, increment tap and try again
if (Maxcount(Maxcount'high) = '1') then
retries <= retries + '1';
RetryCntr <= RetryCntr - '1';
tapcount <= (others => '0');
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
Maxcount <= std_logic_vector(TO_UNSIGNED((TAP_COUNT_MAX-1),(Maxcount'high+1)));
alignstate <= Reset_Delay;
else
retries <= retries + '1';
RetryCntr <= RetryCntr - '1';
tapcount <= tapcount + '1';
Maxcount <= Maxcount - '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
alignstate <= Get_Edge;
end if;
end if;
end if;
when Wait_Sample_Stable =>
if (end_handshake = '1') then
if (GenCntr(GenCntr'high) = '1') then -- sampled x times the same edge data
STABLE_DETECT(index) <= '1';
GenCntr <= std_logic_vector(TO_UNSIGNED((DATAWIDTH-1),(GenCntr'high+1))); --recycle stablecounter for compare purposes
alignstate <= Compare_Training;
else
if (edge_init /= edge_int) then -- data not the same, increment tab and try again
start_handshake <= '1';
retries <= retries + '1';
RetryCntr <= RetryCntr - '1';
if (Maxcount(Maxcount'high) = '1') then
tapcount <= (others => '0');
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
Maxcount <= std_logic_vector(TO_UNSIGNED((TAP_COUNT_MAX-1),(Maxcount'high+1)));
alignstate <= Reset_Delay;
else
tapcount <= tapcount + '1';
Maxcount <= Maxcount - '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
GenCntr <= StableCntrLoad;
alignstate <= Get_Edge;
end if;
else
GenCntr <= GenCntr - '1';
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
start_handshake <= '1';
end if;
end if;
end if;
-- the data detected as 'stable' in the previous state should be the training word.
-- therefore no new data is 'grabbed' from the serdes module
when Compare_Training =>
if (GenCntr(GenCntr'high) = '1') then
start_handshake <= '1';
if (Maxcount(Maxcount'high) = '1') then
tapcount <= (others => '0');
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
Maxcount <= std_logic_vector(TO_UNSIGNED((TAP_COUNT_MAX-1),(Maxcount'high+1)));
alignstate <= Reset_Delay;
else
retries <= retries + '1';
RetryCntr <= RetryCntr - '1';
tapcount <= tapcount + '1';
Maxcount <= Maxcount - '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
GenCntr <= StableCntrLoad;
alignstate <= Get_Edge;
end if;
else
if (CTRL_DATA = compare(TO_INTEGER(UNSIGNED(GenCntr)))) then
TRAINING_DETECT(index) <= '1';
if (GenCntr = DATAWIDTH-1) then
CTRL_SAMPLEINFIRSTBIT_i <= '0';
CTRL_SAMPLEINLASTBIT_i <= '1';
CTRL_SAMPLEINOTHERBIT_i <= '0';
elsif (GenCntr = DATAWIDTH-2) then
CTRL_SAMPLEINFIRSTBIT_i <= '1';
CTRL_SAMPLEINLASTBIT_i <= '0';
CTRL_SAMPLEINOTHERBIT_i <= '0';
else
CTRL_SAMPLEINFIRSTBIT_i <= '0';
CTRL_SAMPLEINLASTBIT_i <= '0';
CTRL_SAMPLEINOTHERBIT_i <= '1';
end if;
alignstate <= Valid_Begin_Found;
end if;
GenCntr <= GenCntr - '1';
end if;
when Valid_Begin_Found =>
start_handshake <= '1';
Maxcount <= Maxcount - '1';
tapcount <= tapcount + '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
alignstate <= CheckFirstEdgeChanged;
when CheckFirstEdgeChanged =>
if (end_handshake = '1') then
IF (
((CTRL_DATA = STD_LOGIC_VECTOR(UNSIGNED(DATA_init) ROR 1)) and (INVERSE_BITORDER = FALSE)) or
((CTRL_DATA = STD_LOGIC_VECTOR(UNSIGNED(DATA_init) ROL 1)) and (INVERSE_BITORDER = TRUE))
) THEN --edge found (1 time)
start_handshake <= '1';
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
GenCntr <= std_logic_vector(TO_UNSIGNED((STABLE_COUNT-1),(GenCntr'high+1)));
alignstate <= CheckFirstEdgeStable;
else
start_handshake <= '1';
if (Maxcount(Maxcount'high) = '1') then
tapcount <= (others => '0');
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
Maxcount <= std_logic_vector(TO_UNSIGNED((TAP_COUNT_MAX-1),(Maxcount'high+1)));
alignstate <= Reset_Delay;
else
Maxcount <= Maxcount - '1';
tapcount <= tapcount + '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
end if;
end if;
end if;
when CheckFirstEdgeStable =>
if (end_handshake = '1') then
start_handshake <= '1';
if (GenCntr(GenCntr'high) = '1') then -- edge detected ok
windowcount <= windowcount + '1';
bitcount <= bitcount + '1';
tapcount <= tapcount + '1';
Maxcount <= Maxcount - '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
FIRST_EDGE_FOUND(index) <= '1';
alignstate <= CheckSecondEdgeChanged;
else
GenCntr <= GenCntr - '1';
IF (
((CTRL_DATA = STD_LOGIC_VECTOR(UNSIGNED(DATA_init) ROR 1)) and (INVERSE_BITORDER = FALSE)) or
((CTRL_DATA = STD_LOGIC_VECTOR(UNSIGNED(DATA_init) ROL 1)) and (INVERSE_BITORDER = TRUE))
) THEN
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
else -- edge changed during stability test
GenCntr <= std_logic_vector(TO_UNSIGNED((STABLE_COUNT-1),(GenCntr'high+1)));
tapcount <= tapcount + '1'; -- increment tapcount by one and try again
bitcount <= bitcount + '1';
Maxcount <= Maxcount - '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
alignstate <= CheckFirstEdgeChanged;
end if;
end if;
end if;
when CheckSecondEdgeChanged =>
if (end_handshake = '1') then
IF (
((CTRL_DATA = STD_LOGIC_VECTOR(UNSIGNED(DATA_init) ROR 2)) and (INVERSE_BITORDER = FALSE)) or
((CTRL_DATA = STD_LOGIC_VECTOR(UNSIGNED(DATA_init) ROL 2)) and (INVERSE_BITORDER = TRUE))
) THEN -- 2nd edge found, window found
SECOND_EDGE_FOUND(index) <= '1';
WINDOW_WIDTH((10*index)+9 downto 10*index) <= windowcount;
BIT_WIDTH((10*index)+9 downto 10*index) <= bitcount;
GenCntr <= ("0000000" & windowcount(9 downto 1)) - "10"; --divide by 2
start_handshake <= '1';
tapcount <= tapcount - '1';
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '1';
alignstate <= WindowFound;
else
start_handshake <= '1';
if (Maxcount(Maxcount'high) = '1') then --overrun tapcount
CTRL_RESET <= '1';
CTRL_INC <= '0';
CTRL_CE <= '0';
alignstate <= Reset_Delay;
else
windowcount <= windowcount + '1';
bitcount <= bitcount + '1';
Maxcount <= Maxcount - '1';
tapcount <= tapcount + '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
end if;
end if;
end if;
when WindowFound =>
if (end_handshake = '1') then
if (GenCntr(GenCntr'high) = '1') then
--TAP_SETTING((10*index)+9 downto 10*index) <= tapcount;
alignstate <= Start_Word_Align;
else
start_handshake <= '1';
tapcount <= tapcount - '1';
GenCntr <= GenCntr - '1';
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '1';
end if;
end if;
when Reset_Delay_Man =>
if (end_handshake = '1') then
if (GenCntr(GenCntr'high) = '1') then
alignstate <= Start_Word_Align;
--TAP_SETTING((10*index)+9 downto 10*index) <= tapcount;
else
GenCntr <= GenCntr - '1';
start_handshake <= '1';
tapcount <= tapcount + '1';
CTRL_RESET <= '0';
CTRL_INC <= '1';
CTRL_CE <= '1';
end if;
end if;
-- wordalignment, can fail in manual tap mode, or when bitalign algorithm fails
when Start_Word_Align =>
if (CTRL_DATA = TRAINING) then
WORD_ALIGN(index) <= '1';
alignstate <= Alignment_Done;
else
start_handshake <= '1';
GenCntr <= std_logic_vector(TO_UNSIGNED((DATAWIDTH-2),(GenCntr'high+1)));
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
CTRL_BITSLIP <= '1';
alignstate <= Do_Word_Align;
end if;
when Do_Word_Align =>
if (end_handshake = '1') then
if (CTRL_DATA = TRAINING) then
WORD_ALIGN(index) <= '1';
alignstate <= Alignment_Done;
else
if (GenCntr(GenCntr'high) = '1') then --alignment failed
TAP_SETTING((10*index)+9 downto 10*index) <= tapcount;
NROF_RETRIES((16*index)+15 downto 16*index) <= retries;
alignstate <= Idle;
else
start_handshake <= '1';
CTRL_BITSLIP <= '1';
GenCntr <= GenCntr - '1';
end if;
end if;
end if;
when Alignment_Done =>
done_align_i <= '1';
CTRL_RESET <= '0';
CTRL_INC <= '0';
CTRL_CE <= '0';
CTRL_BITSLIP <= '0';
NROF_RETRIES((16*index)+15 downto 16*index) <= retries;
TAP_SETTING((10*index)+9 downto 10*index) <= tapcount;
alignstate <= Idle;
when others =>
alignstate <= Idle;
end case;
end if;
end process;
end rtl;
|
gpl-3.0
|
db01061b8cc42b5581d9307131a569e4
| 0.417751 | 4.765933 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/flexible_lvds_rx/_primary.vhd
| 1 | 2,016 |
library verilog;
use verilog.vl_types.all;
entity flexible_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_extra_ddio_register: string := "YES";
use_extra_pll_clk: string := "NO";
buffer_implementation: string := "RAM";
registered_data_align_input: string := "OFF";
use_external_pll: string := "OFF";
registered_output: string := "ON";
add_latency : string := "YES";
REGISTER_WIDTH : vl_notype;
LATENCY : vl_notype;
NUM_OF_SYNC_STAGES: vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_slowclk : in vl_logic;
rx_syncclk : in vl_logic;
pll_areset : in vl_logic;
rx_data_align : in vl_logic_vector;
rx_cda_reset : in vl_logic_vector;
rx_locked : in vl_logic;
rx_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of use_extra_ddio_register : constant is 1;
attribute mti_svvh_generic_type of use_extra_pll_clk : constant is 1;
attribute mti_svvh_generic_type of buffer_implementation : constant is 1;
attribute mti_svvh_generic_type of registered_data_align_input : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of add_latency : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of LATENCY : constant is 3;
attribute mti_svvh_generic_type of NUM_OF_SYNC_STAGES : constant is 3;
end flexible_lvds_rx;
|
bsd-2-clause
|
d68eacbe6b7e5885c54c8898459fda84
| 0.624504 | 3.678832 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/spi_top.vhd
| 1 | 14,767 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (Fri, 02 Jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--user:
-----------
--library work;
--use work.all;
--use work.app_pack.all;
entity spi_top is
generic
(
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50;
--LowLevel SPI settings
gSpiClkSpeed : integer := 1000; -- SPI Clock Speed in kHz
gUseFixedSpeed : integer := 1; -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH : integer := 26;
gTxMSB_FIRST : integer := 1;
gRxMSB_FIRST : integer := 1;
gSCLK_POLARITY : std_logic := '0'; --'0': idle low, '1': idle high
gCS_POLARITY : std_logic := '1'; --'0': active high, '1': active low
gEN_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMOSI_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_SAMPLE : std_logic := '1'; --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK : std_logic := '0'; --'0': clock out on rising edge, '1': clock out on falling edge
--Seq SPI settings
gSyncTriggerWidth : integer; -- min 1, max 15
gRWbitposition : integer := 0 --seen from LSB
);
Port (
CLOCK : in std_logic;
RESET : in std_logic;
TIMING : in std_logic_vector(15 downto 0);
BUSY : out std_logic;
--START_READ : in std_logic;
--BUSY_READ : out std_logic;
--START_WRITE : in std_logic;
--BUSY_WRITE : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
--
-- SPI
--
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
CS : out std_logic;
EN : out std_logic
);
end spi_top;
Architecture structure of spi_top is
-------------------------
-- component declaration:
-------------------------
component spi_seq
generic (
gSIMULATION : integer;
gSysClkSpeed : integer;
gDATA_WIDTH : integer;
gSyncTriggerWidth : integer; -- min 1, max 15
gRWbitposition : integer --seen from LSB
);
port (
-- system:
CLK : in std_logic;
RESET : in std_logic;
BUSY : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
SPI_START : out std_logic;
SPI_BUSY : in std_logic;
SPI_DATA_TX : out std_logic_Vector(gDATA_WIDTH-1 downto 0);
SPI_DATA_RX : in std_logic_vector(gDATA_WIDTH-1 downto 0)
);
end component;
component spi_lowlevel
generic
(
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50; -- Clock Speed in MHz
gSpiClkSpeed : integer := 1000; -- SPI Clock Speed in kHz
gUseFixedSpeed : integer := 1; -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH : integer := 26;
gTxMSB_FIRST : integer := 1;
gRxMSB_FIRST : integer := 1;
gSCLK_POLARITY : std_logic := '0'; --'0': idle low, '1': idle high
gCS_POLARITY : std_logic := '1'; --'0': active high, '1': active low
gEN_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMOSI_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_SAMPLE : std_logic := '1'; --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK : std_logic := '0' --'0': clock out on rising edge, '1': clock out on falling edge
);
port
(
--
-- Control signals
--
CLK : in std_logic;
RESET : in std_logic;
START : in std_logic;
BUSY : out std_logic;
SPI_DATA_TX : in std_logic_Vector((gDATA_WIDTH-1) downto 0);
SPI_DATA_RX : out std_logic_vector((gDATA_WIDTH-1) downto 0);
TIMING : in std_logic_vector(15 downto 0);
--
-- SPI
--
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
CS : out std_logic;
EN : out std_logic
);
end component;
----------------------
-- signal declaration:
----------------------
signal SPI_START : std_logic;
signal SPI_BUSY : std_logic;
signal SPI_DATA_TX : std_Logic_vector(gDATA_WIDTH-1 downto 0);
signal SPI_DATA_RX : std_logic_vector(gDATA_WIDTH-1 downto 0);
begin
---------------------------
-- component instantiation:
---------------------------
the_spi_seq: spi_seq
generic map (
gSIMULATION => gSIMULATION ,
gSysClkSpeed => gSysClkSpeed ,
gDATA_WIDTH => gDATA_WIDTH ,
gSyncTriggerWidth => gSyncTriggerWidth ,
gRWbitposition => gRWbitposition
)
port map (
-- system:
CLK => CLOCK ,
RESET => RESET ,
BUSY => BUSY ,
synctriggers => synctriggers ,
sync1_select => sync1_select ,
sync2_select => sync2_select ,
-- Fifo signals
APP_RDFIFO_CLK => APP_RDFIFO_CLK ,
APP_RDFIFO_EN => APP_RDFIFO_EN ,
APP_RDFIFO_DATA_OUT => APP_RDFIFO_DATA_OUT ,
APP_RDFIFO_EMPTY => APP_RDFIFO_EMPTY ,
APP_WRFIFO_CLK => APP_WRFIFO_CLK ,
APP_WRFIFO_EN => APP_WRFIFO_EN ,
APP_WRFIFO_DATA_IN => APP_WRFIFO_DATA_IN ,
APP_WRFIFO_FULL => APP_WRFIFO_FULL ,
ERROR => ERROR ,
SPI_START => SPI_START ,
SPI_BUSY => SPI_BUSY ,
SPI_DATA_TX => SPI_DATA_TX ,
SPI_DATA_RX => SPI_DATA_RX
);
the_spi_lowlevel: spi_lowlevel
generic map
(
gSIMULATION => gSIMULATION ,
gSysClkSpeed => gSysClkSpeed , -- Clock Speed in MHz
gSpiClkSpeed => 1000 , -- SPI Clock Speed in kHz
gUseFixedSpeed => 0 , -- 0: use timing input 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH => 26 ,
gTxMSB_FIRST => 1 ,
gRxMSB_FIRST => 1 ,
gSCLK_POLARITY => '0' , --'0': idle low, '1': idle high
gCS_POLARITY => '1' , --'0': active high, '1': active low
gEN_POLARITY => '0' , --'0': normal, '1': invert
gMOSI_POLARITY => '0' , --'0': normal, '1': invert
gMISO_POLARITY => '0' , --'0': normal, '1': invert
gMISO_SAMPLE => '0' , --'0': sample on rising edge, '1': sample on falling edge
gMOSI_CLK => '0' --'0': clock out on rising edge, '1': clock out on falling edge
)
port map
(
--
-- Control signals
--
CLK => CLOCK ,
RESET => RESET ,
START => SPI_START ,
BUSY => SPI_BUSY ,
SPI_DATA_TX => SPI_DATA_TX ,
SPI_DATA_RX => SPI_DATA_RX ,
TIMING => TIMING ,
--
-- SPI
--
SCLK => SCLK ,
MOSI => MOSI ,
MISO => MISO ,
CS => CS ,
EN => EN
);
end STRUCTURE ;
|
gpl-3.0
|
eb18bb1001b07d53679cd2e22fcfc283
| 0.388231 | 4.902722 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/pck_crc8_d8.vhd
| 1 | 3,320 |
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 2 3 6 8)
-- * data width: 8
--
-- Info : [email protected]
-- http://www.easics.com
--------------------------------------------------------------------------------
--
-- *********************************************************************
-- File : $RCSfile: pck_crc8_d8.vhd.rca $
-- Author : $Author: fec $
-- Author's Email : [email protected]
-- Department : MPD_BE
-- Date : $Date: Thu Oct 8 18:40:45 2009 $
-- Revision : $Revision: 1.1 $
-- *********************************************************************
-- Modification History Summary
-- Date By Version Change Description
-- *********************************************************************
-- $Log: pck_crc8_d8.vhd.rca $
--
-- Revision: 1.1 Thu Oct 8 18:40:45 2009 fec
-- {CRC 8 polynome}
--
-- *********************************************************************
-- Description
--
-- *********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PCK_CRC8_D8 is
-- polynomial: (0 2 3 6 8)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC8_D8
(data: unsigned(7 downto 0);
crc: unsigned(7 downto 0))
return unsigned;
end PCK_CRC8_D8;
package body PCK_CRC8_D8 is
-- polynomial: (0 2 3 6 8)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC8_D8
(data: unsigned(7 downto 0);
crc: unsigned(7 downto 0))
return unsigned is
variable d: unsigned(7 downto 0);
variable c: unsigned(7 downto 0);
variable newcrc: unsigned(7 downto 0);
begin
d := data;
c := crc;
newcrc(0) := d(5) xor d(4) xor d(2) xor d(0) xor c(0) xor c(2) xor
c(4) xor c(5);
newcrc(1) := d(6) xor d(5) xor d(3) xor d(1) xor c(1) xor c(3) xor
c(5) xor c(6);
newcrc(2) := d(7) xor d(6) xor d(5) xor d(0) xor c(0) xor c(5) xor
c(6) xor c(7);
newcrc(3) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor
d(0) xor c(0) xor c(1) xor c(2) xor c(4) xor c(5) xor
c(6) xor c(7);
newcrc(4) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor
c(1) xor c(2) xor c(3) xor c(5) xor c(6) xor c(7);
newcrc(5) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(2) xor
c(3) xor c(4) xor c(6) xor c(7);
newcrc(6) := d(7) xor d(3) xor d(2) xor d(0) xor c(0) xor c(2) xor
c(3) xor c(7);
newcrc(7) := d(4) xor d(3) xor d(1) xor c(1) xor c(3) xor c(4);
return newcrc;
end nextCRC8_D8;
end PCK_CRC8_D8;
|
gpl-3.0
|
757f59044a4128e573088d6048cb74db
| 0.487048 | 3.32999 | false | false | false | false |
CprE488/Final
|
system/hdl/system_btns_5bits_wrapper.vhd
| 3 | 4,991 |
-------------------------------------------------------------------------------
-- system_btns_5bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_btns_5bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(4 downto 0);
GPIO_IO_O : out std_logic_vector(4 downto 0);
GPIO_IO_T : out std_logic_vector(4 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_btns_5bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_btns_5bits_wrapper;
architecture STRUCTURE of system_btns_5bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
BTNs_5Bits : axi_gpio
generic map (
C_FAMILY => "zynq",
C_INSTANCE => "BTNs_5Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
gpl-3.0
|
28cec8bd2402d2e1c4d72c29a268ca84
| 0.585454 | 2.917008 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.vhdl
| 1 | 7,552 |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Mon Aug 14 17:02:30 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.vhdl
-- Design : clk_wiz_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1_clk_wiz_1_clk_wiz is
port (
clk_txd : out STD_LOGIC;
clk_rxd : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_1_clk_wiz_1_clk_wiz : entity is "clk_wiz_1_clk_wiz";
end clk_wiz_1_clk_wiz_1_clk_wiz;
architecture STRUCTURE of clk_wiz_1_clk_wiz_1_clk_wiz is
signal clk_in1_clk_wiz_1 : STD_LOGIC;
signal clk_rxd_clk_wiz_1 : STD_LOGIC;
signal clk_txd_clk_wiz_1 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_1 : STD_LOGIC;
signal clkfbout_clk_wiz_1 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_1,
O => clkfbout_buf_clk_wiz_1
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_1
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_txd_clk_wiz_1,
O => clk_txd
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_rxd_clk_wiz_1,
O => clk_rxd
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 10,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_1,
CLKFBOUT => clkfbout_clk_wiz_1,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_1,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_txd_clk_wiz_1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_rxd_clk_wiz_1,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1 is
port (
clk_txd : out STD_LOGIC;
clk_rxd : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_1 : entity is true;
end clk_wiz_1;
architecture STRUCTURE of clk_wiz_1 is
begin
inst: entity work.clk_wiz_1_clk_wiz_1_clk_wiz
port map (
clk_in1 => clk_in1,
clk_rxd => clk_rxd,
clk_txd => clk_txd,
locked => locked,
resetn => resetn
);
end STRUCTURE;
|
gpl-3.0
|
40e679f34cf9642096bb9651cfc2d0a3
| 0.629237 | 3.340115 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/MEMIO.vhd
| 2 | 7,819 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 11:55:51 10/26/2009
-- Design Name:
-- Module Name: MEMIO - Behavioral
-- Project Name: OZ-3
-- Target Devices:
-- Tool versions:
-- Description: The memory and I/O stage of the OZ-3 pipeline
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Ports written in
-- Revision 0.20 - Four main processes written, need code to handle dRAM data in
-- Revision 0.50 - First two sections simulated successfully, need to make a dRAM bus handler
-- Revision 0.55 - Did some optimization, re-did dRAM interface: it now has dedicated input and output
-- ports. The rest will be handled by the memory controller. Need to re-do all simulations
-- Revision 0.70 - Simulations complete, renamed some signals
-- Revision 0.80 - Added a new falling-edge register between the dRAM_data_in input and the rest of the stage to aid
-- in a timing issue with the memory bus controller
-- Additional Comments: This stage is easily the most complex stage of the processor,
-- so I will code it much more behaviorally than the other pieces.
-- Control signal catalog:
-- 0. Pin cntl e
-- 1. Port cntl e
-- 2. RAM cntl e
-- 3. pchk e
-- 4. opin clk e
-- 5. opin 1/0
-- 6. oprt clk e
-- 7. dRAM W/R
-- 8-12. dest/data reg adr
-- 13-17. result reg adr
-- 18-19. output MUX sel
-- 20. dRAM lower/upper write/read
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEMIO is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
cntl_from_ID : in STD_LOGIC_VECTOR(20 downto 0);
ALU_result_from_EX_in : in STD_LOGIC_VECTOR(31 downto 0);
RAM_reg_data_from_ID : in STD_LOGIC_VECTOR(31 downto 0);
ipin_reg_data : in STD_LOGIC_VECTOR(15 downto 0);
iprt_data : in STD_LOGIC_VECTOR(31 downto 0);
dRAM_data_in: in STD_LOGIC_VECTOR(15 downto 0);
dRAM_data_out : out STD_LOGIC_VECTOR(15 downto 0);
dRAM_WR : out STD_LOGIC;
dRAM_addr : out STD_LOGIC_VECTOR(22 downto 0);
forward_addr_to_ID : out STD_LOGIC_VECTOR(4 downto 0);
pflag_to_EX : out STD_LOGIC;
opin_clk_e : out STD_LOGIC;
opin_select : out STD_LOGIC_VECTOR(3 downto 0);
opin_1_0 : out STD_LOGIC;
oprt_data : out STD_LOGIC_VECTOR(31 downto 0);
oprt_reg_clk_e : out STD_LOGIC;
RAM_reg_addr_to_ID : out STD_LOGIC_VECTOR(4 downto 0);
data_to_WB : out STD_LOGIC_VECTOR(31 downto 0));
end MEMIO;
architecture Behavioral of MEMIO is
--//Components\\--
component GenReg is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
component GenRegFalling is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal cntl_buffer_1_2 : STD_LOGIC_VECTOR(20 downto 0); --control line buffer signals
signal cntl_buffer_2_out : STD_LOGIC_VECTOR(20 downto 0);
signal dRAM_data_reg_out : STD_LOGIC_VECTOR(15 downto 0);
signal mixed_dRAM_data : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_result_from_EX : STD_LOGIC_VECTOR(31 downto 0);
--\\Signals//--
begin
pins: process (ALU_result_from_EX, cntl_buffer_2_out, ipin_reg_data) is --This process controls the I/O pins
begin
pflag_to_EX <= '0';
opin_select <= b"0000";
opin_clk_e <= '0';
opin_1_0 <= '0';
if cntl_buffer_2_out(0) = '1' then --If this section is active
pflag_to_EX <= (ipin_reg_data(conv_integer(unsigned(ALU_result_from_EX(3 downto 0)))) and cntl_buffer_2_out(3)); --Figure out the pflag
opin_clk_e <= cntl_buffer_2_out(4); --clock the output pins if it's an opin instruction
opin_select <= ALU_result_from_EX(3 downto 0); --other opin control
opin_1_0 <= cntl_buffer_2_out(5);
end if;
end process;
ports: process (ALU_result_from_EX, cntl_buffer_2_out, clock) is --This process controls the data ports
begin
oprt_data <= x"00000000";
oprt_reg_clk_e <= '0';
if cntl_buffer_2_out(1) = '1' then --If it's active, send data out. The input port is always taking input, no matter what
oprt_data <= ALU_result_from_EX;
oprt_reg_clk_e <= (clock and cntl_buffer_2_out(6));
end if;
end process;
RAM: process (ALU_result_from_EX, cntl_buffer_2_out, RAM_reg_data_from_ID) is --This one controls everything having to do with the RAM
begin
dRAM_data_out <= x"0000";
dRAM_WR <= '0'; --set up to default to read operation
dRAM_addr <= b"00000000000000000000000";
if cntl_buffer_2_out(2) = '1' then --If this process is active
if cntl_buffer_2_out(7) = '1' then --If the instruction is a write operation
if cntl_buffer_2_out(20) = '0' then --Test to see if it's writing the upper or lower half
dRAM_data_out <= RAM_reg_data_from_ID(15 downto 0);
else
dRAM_data_out <= RAM_reg_data_from_ID(31 downto 16);
end if;
dRAM_WR <= '1'; --set to write
end if;
dRAM_addr <= ALU_result_from_EX(22 downto 0);
end if;
end process;
MUX: process (ALU_result_from_EX, mixed_dRAM_data, iprt_data, cntl_buffer_2_out) is --This models the MUX at the end of the stage
begin --that decides what data from where goes to WB
case cntl_buffer_2_out(19 downto 18) is
when b"00" =>
data_to_WB <= ALU_result_from_EX;
when b"01" =>
data_to_WB <= iprt_data;
when b"10" =>
data_to_WB <= mixed_dRAM_data;
when others =>
data_to_WB <= x"00000000";
end case;
end process;
mix_dRAM_data: process (dRAM_data_reg_out, cntl_buffer_2_out, RAM_reg_data_from_ID) is --This process takes the dRAM_data_in signal and mixes it
begin --with the data from the register that's being read into
if cntl_buffer_2_out(20) = '0' then --so that it can put the new data in the upper or lower half
mixed_dRAM_data <= (RAM_reg_data_from_ID(31 downto 16) & dRAM_data_reg_out);
else
mixed_dRAM_data <= (dRAM_data_reg_out & RAM_reg_data_from_ID(15 downto 0));
end if;
end process;
buf_1: GenReg generic map (21) --These registers make up the two-stage buffer for the control
port map (clock, '1', reset, cntl_from_ID, cntl_buffer_1_2); --signals thatget sent out by the instruction decoder
buf_2: GenReg generic map (21)
port map (clock, '1', reset, cntl_buffer_1_2, cntl_buffer_2_out);
input_reg: GenReg generic map (32)
port map (clock, '1', reset, ALU_result_from_EX_in, ALU_result_from_EX); --This register is the buffer between the EX and MEMIO stages
dRAM_data_reg : GenRegFalling generic map (16)
port map (clock, '1', reset, dRAM_data_in, dRAM_data_reg_out);
RAM_reg_addr_to_ID <= cntl_buffer_2_out(12 downto 8);
forward_addr_to_ID <= cntl_buffer_2_out(17 downto 13);
end Behavioral;
|
mit
|
4e5a032c4811886b29445a5d22c8190e
| 0.612482 | 3.233664 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_hdmi_in_v2_01_a/hdl/vhdl/fmc_imageon_hdmi_in.vhd
| 7 | 9,295 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Aug 31, 2011
-- Design Name: FMC-IMAGEON
-- Module Name: fmc_imageon_hdmi_in.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Spartan-6, Virtex-6
-- Artix-7, Kintex-7, Virtex-7, Zynq
-- Avnet Boards: FMC-IMAGEON
--
-- Tool versions: ISE 14.3
--
-- Description: FMC-IMAGEON HDMI input interface.
--
-- Dependencies:
--
-- Revision: Aug 31, 2011: 1.01 Initial version
-- Nov 11, 2011: 1.02 Add CCIR656 decode logic
-- Remove VSYNC/HSYNC ports
-- Feb 06, 2012: 1.03 Fix sync de-embed logic
-- Change IOB attribute from "TRUE" to "FORCE"
-- Oct 19, 2012: 2.01a Remove XSVI bus interface
-- Remove xsvi_ prefixes to video_
-- Rename active_video to de
-- Change IP_GROUP to FMC-IMAGEON
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fmc_imageon_hdmi_in is
Generic
(
C_DATA_WIDTH : integer := 16;
C_FAMILY : string := "virtex6"
);
Port
(
clk : in std_logic;
-- IO Pins
io_hdmii_spdif : in std_logic;
io_hdmii_video : in std_logic_vector(15 downto 0);
-- Audio Port
audio_spdif : out std_logic;
-- Video Ports
-- video_vsync : out std_logic;
-- video_hsync : out std_logic;
video_vblank : out std_logic;
video_hblank : out std_logic;
video_de : out std_logic;
video_data : out std_logic_vector((C_DATA_WIDTH-1) downto 0);
-- Debug Port
debug_o : out std_logic_vector(23 downto 0)
);
end fmc_imageon_hdmi_in;
architecture rtl of fmc_imageon_hdmi_in is
--
-- IOB registers
--
signal spdif_r : std_logic;
signal video_r : std_logic_vector (15 downto 0);
attribute IOB : string;
attribute IOB of spdif_r: signal is "FORCE";
attribute IOB of video_r: signal is "FORCE";
--
-- Input Delay
--
signal video_d1 : std_logic_vector(15 downto 0);
signal video_d2 : std_logic_vector(15 downto 0);
signal video_d3 : std_logic_vector(15 downto 0);
signal video_d4 : std_logic_vector(15 downto 0);
--
-- CCIR656 Decode Logic
--
signal sc : std_logic;
signal sav_va : std_logic;
signal eav_va : std_logic;
signal sav_vb : std_logic;
signal eav_vb : std_logic;
signal sav_va_d1 : std_logic;
signal sav_va_d2 : std_logic;
signal sav_va_d3 : std_logic;
signal sav_va_d4 : std_logic;
signal sav_vb_d1 : std_logic;
signal sav_vb_d2 : std_logic;
signal sav_vb_d3 : std_logic;
signal sav_vb_d4 : std_logic;
signal sync_code : std_logic;
signal vblank : std_logic;
signal hblank : std_logic;
signal de : std_logic;
begin
--
-- IOB registers
--
io_iregs_l : process (clk)
begin
if Rising_Edge(clk) then
spdif_r <= io_hdmii_spdif;
video_r <= io_hdmii_video;
end if;
end process;
--
-- Input Delay
--
input_delay_l : process (clk)
begin
if Rising_Edge(clk) then
-- Delay DATA by 4 cycles to have a 4 cycle view of data
video_d1 <= video_r;
video_d2 <= video_d1;
video_d3 <= video_d2;
video_d4 <= video_d3;
end if;
end process;
--
-- CCIR656 Decode Logic
--
ccir656_decode_l : process ( video_r, video_d1, video_d2, video_d3, video_d4 )
begin
-- Sync Code
sc <= '0';
if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") ) then
sc <= '1';
end if;
-- Start of Active Video (active line)
sav_va <= '0';
if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"8080") ) then
sav_va <= '1';
end if;
-- End of Active Video (active line)
eav_va <= '0';
if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"9D9D") ) then
eav_va <= '1';
end if;
-- Start of Inactive Video (blank line)
sav_vb <= '0';
if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"ABAB") ) then
sav_vb <= '1';
end if;
-- End of Inactive Video (blank line)
eav_vb <= '0';
if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d2 = X"0000") and (video_r = X"B6B6") ) then
eav_vb <= '1';
end if;
end process;
ccir656_syncgen_l : process (clk)
begin
if Rising_Edge(clk) then
-- Delay SAV by 4 cycles
sav_va_d1 <= sav_va;
sav_va_d2 <= sav_va_d1;
sav_va_d3 <= sav_va_d2;
sav_va_d4 <= sav_va_d3;
--
sav_vb_d1 <= sav_vb;
sav_vb_d2 <= sav_vb_d1;
sav_vb_d3 <= sav_vb_d2;
sav_vb_d4 <= sav_vb_d3;
-- Create generic Sync Code event indicator (for use with ChipScope)
sync_code <= sc;
-- Create DE strobe based on SAV/EAV events
if ( sav_va_d4 = '1' ) then
de <= '1';
end if;
if ( eav_va = '1' or eav_vb = '1' ) then
de <= '0';
end if;
-- Create VBLANK strobes based on SAV events
--if ( sav_vb = '1' ) then
if ( sav_vb = '1' or eav_vb = '1' ) then
vblank <= '1';
end if;
if ( sav_va = '1' ) then
vblank <= '0';
end if;
-- Create HBLANK strobes based on SAV/EAV events
if ( sav_va_d4 = '1' or sav_vb_d4 = '1' ) then
hblank <= '0';
end if;
if ( eav_va = '1' or eav_vb = '1' ) then
hblank <= '1';
end if;
end if;
end process;
--
-- Video Ports
--
VIDEO_PORTS_16BIT_GEN : if (C_DATA_WIDTH = 16) generate
video_ports_16bit_oregs_l : process (clk)
begin
if rising_edge( clk ) then
-- video_vsync <= '0';
-- video_hsync <= '0';
video_vblank <= vblank;
video_hblank <= hblank;
video_de <= de;
video_data <= video_d4;
end if;
end process;
end generate VIDEO_PORTS_16BIT_GEN;
--
-- Audio Port
--
audio_spdif <= spdif_r;
--
-- Debug Port
-- Can be used to connect to ChipScope for debugging.
-- Having a port makes these signals accessible for debug via EDK.
--
debug_l : process (clk)
begin
if Rising_Edge(clk) then
debug_o(15 downto 0) <= video_r;
debug_o( 16) <= spdif_r;
debug_o( 17) <= de;
debug_o( 18) <= hblank;
debug_o( 19) <= vblank;
debug_o( 20) <= sav_va;
debug_o( 21) <= sav_vb;
debug_o( 22) <= eav_va or eav_vb;
debug_o( 23) <= sync_code;
end if;
end process;
end rtl;
|
gpl-3.0
|
77107c3220a5bab7068d51c0be2c2af2
| 0.454223 | 3.666667 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_32_s6.vhd
| 1 | 10,439 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file afifo_32_s6.vhd when simulating
-- the core, afifo_32_s6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY afifo_32_s6 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END afifo_32_s6;
ARCHITECTURE afifo_32_s6_a OF afifo_32_s6 IS
-- synthesis translate_off
COMPONENT wrapped_afifo_32_s6
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_afifo_32_s6 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 4,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 2,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 13,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 12,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 4,
c_rd_depth => 16,
c_rd_freq => 1,
c_rd_pntr_width => 4,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 4,
c_wr_depth => 16,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 4,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_afifo_32_s6
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END afifo_32_s6_a;
|
gpl-3.0
|
d7ffb7aef2733c1eb0ab189c6187c0b3
| 0.520835 | 3.345833 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/spi_wishbone_wrapper.vhd
| 2 | 5,674 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
entity spi_wishbone_wrapper is
-- ----------------------------------------------------------------------------
generic(BIG_ENDIAN : boolean := true);
port
(
-- SPI SIGNALS
mosi, ss, sck : in std_logic;
miso : out std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of spi_wishbone_wrapper is
-- ----------------------------------------------------------------------------
signal bit_count : std_logic_vector(3 downto 0) ;
signal data_byte : std_logic ;
signal data_in_sr, data_out_sr, addr_bus_latched : std_logic_vector(15 downto 0);
signal data_in_latched : std_logic_vector(15 downto 0);
signal data_out_temp : std_logic_vector(15 downto 0);
signal auto_inc, rd_wrn, data_confn : std_logic ;
signal wr_latched, rd_latched : std_logic ;
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(15 downto 0);
begin
process(sck, ss)
begin
if ss = '1' then
data_in_sr <= (others => '0') ;
bit_count <= (others => '0') ;
elsif sck'event and sck = '1' then
data_in_sr(0) <= mosi ;
data_in_sr(15 downto 1) <= data_in_sr(14 downto 0) ;
bit_count <= bit_count + 1 ;
end if ;
end process ;
process(sck, ss)
begin
if ss = '1' then
data_out_sr <= (others => '0') ;
elsif sck'event and sck = '1' then -- data change should only occur on falling edge ...
if bit_count = 0 then
data_out_sr(15 downto 1) <= data_out_temp(14 downto 0) ;
data_out_sr(0) <= '0' ;
else
data_out_sr(15 downto 1) <= data_out_sr(14 downto 0) ;
data_out_sr(0) <= '0' ;
end if ;
end if ;
end process ;
miso <= data_out_temp(15) when bit_count = 0 else
data_out_sr(15);
process(sck, ss)
begin
if ss = '1' then
data_confn <= '0' ;
auto_inc <= '0' ;
rd_wrn <= '0' ;
rd_latched <= '0' ;
elsif sck'event and sck = '1' then
if data_confn = '0' and bit_count = 14 then
addr_bus_latched <= "00" & data_in_sr(13 downto 0);-- getting address ready as early as possible to ease on reads ...
elsif data_confn = '0' and bit_count = 15 then
--addr_bus_latched <= "00" & data_in_sr(14 downto 1);
auto_inc <= data_in_sr(0) ;
rd_wrn <= mosi ;
data_confn <= '1' ;
elsif data_confn = '1' and bit_count = 15 then
data_in_latched <= data_in_sr(14 downto 0) & mosi;
end if ;
if auto_inc = '1' and data_confn = '1' and bit_count = 7 then
if rd_wrn = '1' or (rd_wrn = '0' and data_byte = '1') then
addr_bus_latched <= addr_bus_latched + 1 ;
end if;
end if ;
if bit_count = 15 and data_confn = '0' then
rd_latched <= mosi ;
elsif data_confn = '1' and bit_count = 0 and rd_wrn = '1' then
rd_latched <= '1' ;
else
rd_latched <= '0' ;
end if ;
end if ;
end process ;
-- write occurs only when in data mode
process(sck, ss)
begin
if ss = '1' then
data_byte <= '0' ;
wr_latched <= '0' ;
elsif sck'event and sck = '1' then
if data_confn = '1' and rd_wrn = '0' and bit_count = 15 then
wr_latched <= '1' ;
data_byte <= '1' ;
else
wr_latched <= '0' ;
end if ;
end if ;
end process ;
gen_le : if (NOT BIG_ENDIAN) generate
data_out_temp <= wbm_readdata ;
writedata <= data_in_latched ;
end generate ;
gen_be : if BIG_ENDIAN generate
data_out_temp <= wbm_readdata(7 downto 0) & wbm_readdata(15 downto 8) ;
writedata <= data_in_latched(7 downto 0) & data_in_latched(15 downto 8);
end generate ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
write <= '0' ;
read <= '0' ;
strobe <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
write <= wr_latched ;
read <= rd_latched ;
strobe <= wr_latched OR rd_latched;
end if ;
end process ;
address <= addr_bus_latched ;
wbm_address <= address ;
wbm_writedata <= writedata ;
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
end architecture RTL;
|
lgpl-3.0
|
abfb84fe1e6f3f17ce5e912cfb3ea357
| 0.573317 | 3.25344 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_s6/example_design/pulse_regen_s6_top.vhd
| 1 | 5,367 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_s6_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_s6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pulse_regen_s6_top;
architecture xilinx of pulse_regen_s6_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_s6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pulse_regen_s6 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
d595d6131c9bd668f1636d5d10f9e826
| 0.498044 | 4.618761 | false | false | false | false |
CprE488/Final
|
system/pcores/led_pwm_v1_01_a/hdl/vhdl/pwm.vhd
| 2 | 1,862 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:52:27 11/19/2014
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
top : in STD_LOGIC_VECTOR (31 downto 0);
duty_cycle : in STD_LOGIC_VECTOR (31 downto 0);
output : out STD_LOGIC);
end pwm;
architecture Behavioral of pwm is
signal timer_count : unsigned(31 downto 0);
signal out_signal : std_logic;
begin
pwm_proc: process(clk, rst)
begin
if(rst = '1') then
timer_count <= (others => '0');
out_signal <= '1';
elsif(rising_edge(clk)) then
if(enable = '1') then
timer_count <= timer_count + 1;
end if;
if(timer_count > unsigned(top)) then
timer_count <= (others => '0');
end if;
if(timer_count < unsigned(duty_cycle)) then
out_signal <= '0';
else
out_signal <= '1';
end if;
end if;
end process;
output <= out_signal;
end Behavioral;
|
gpl-3.0
|
af734591ccbfe2560a67b9ca01fe99b0
| 0.510741 | 4.110375 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/fifo_EEPROM/fifo_EEPROM_sim_netlist.vhdl
| 1 | 197,215 |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Thu Aug 24 05:36:23 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/fifo_EEPROM/fifo_EEPROM_sim_netlist.vhdl
-- Design : fifo_EEPROM
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_EEPROM_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_EEPROM_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13 downto 11) => B"000",
ADDRARDADDR(10 downto 5) => ADDRARDADDR(5 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 11) => B"000",
ADDRBWRADDR(10 downto 5) => Q(5 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15 downto 10) => B"000000",
DIADI(9 downto 8) => din(3 downto 2),
DIADI(7 downto 2) => B"000000",
DIADI(1 downto 0) => din(1 downto 0),
DIBDI(15 downto 10) => B"000000",
DIBDI(9 downto 8) => din(7 downto 6),
DIBDI(7 downto 2) => B"000000",
DIBDI(1 downto 0) => din(5 downto 4),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4\,
DOADO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5\,
DOADO(9 downto 8) => dout(3 downto 2),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12\,
DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13\,
DOADO(1 downto 0) => dout(1 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20\,
DOBDO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21\,
DOBDO(9 downto 8) => dout(7 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28\,
DOBDO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29\,
DOBDO(1 downto 0) => dout(5 downto 4),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => \out\(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_EEPROM_rd_bin_cntr;
architecture STRUCTURE of fifo_EEPROM_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ram_empty_i_i_5_n_0 : STD_LOGIC;
signal ram_empty_i_i_6_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of ram_empty_i_i_5 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of ram_empty_i_i_6 : label is "soft_lutpair6";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(4 downto 0);
Q(5 downto 0) <= \^q\(5 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \^q\(3),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(0),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(1),
O => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(1),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(2),
O => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(2),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(3),
O => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(3),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(4),
O => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(4),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
O => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
ram_empty_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8200008200000000"
)
port map (
I0 => ram_empty_i_i_5_n_0,
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(0),
I2 => \gnxpm_cdc.wr_pntr_bin_reg[5]\(0),
I3 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(1),
I4 => \gnxpm_cdc.wr_pntr_bin_reg[5]\(1),
I5 => ram_empty_i_i_6_n_0,
O => ram_empty_fb_i_reg
);
ram_empty_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[5]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[5]\(3),
O => ram_empty_i_i_5_n_0
);
ram_empty_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram_0\(4),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[5]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[5]\(5),
O => ram_empty_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_EEPROM_rd_status_flags_as;
architecture STRUCTURE of fifo_EEPROM_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
I2 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
O => tmp_ram_rd_en
);
\gc0.count_d1[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gc0.count_reg[0]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gc0.count_reg[0]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_synchronizer_ff : entity is "synchronizer_ff";
end fifo_EEPROM_synchronizer_ff;
architecture STRUCTURE of fifo_EEPROM_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_EEPROM_synchronizer_ff_0;
architecture STRUCTURE of fifo_EEPROM_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_EEPROM_synchronizer_ff_1;
architecture STRUCTURE of fifo_EEPROM_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_EEPROM_synchronizer_ff_2;
architecture STRUCTURE of fifo_EEPROM_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_EEPROM_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_EEPROM_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \fifo_EEPROM_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \fifo_EEPROM_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
begin
D(5 downto 0) <= Q_reg(5 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_EEPROM_synchronizer_ff__parameterized0_3\ is
port (
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_EEPROM_synchronizer_ff__parameterized0_3\ : entity is "synchronizer_ff";
end \fifo_EEPROM_synchronizer_ff__parameterized0_3\;
architecture STRUCTURE of \fifo_EEPROM_synchronizer_ff__parameterized0_3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
begin
D(5 downto 0) <= Q_reg(5 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_EEPROM_synchronizer_ff__parameterized0_4\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Q_reg_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_EEPROM_synchronizer_ff__parameterized0_4\ : entity is "synchronizer_ff";
end \fifo_EEPROM_synchronizer_ff__parameterized0_4\;
architecture STRUCTURE of \fifo_EEPROM_synchronizer_ff__parameterized0_4\ is
signal Q_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
begin
\out\(5 downto 0) <= Q_reg(5 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[5]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[5]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[5]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[5]_0\(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[5]_0\(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[5]_0\(5),
Q => Q_reg(5)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(5),
O => D(0)
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(5),
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_EEPROM_synchronizer_ff__parameterized0_5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Q_reg_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_EEPROM_synchronizer_ff__parameterized0_5\ : entity is "synchronizer_ff";
end \fifo_EEPROM_synchronizer_ff__parameterized0_5\;
architecture STRUCTURE of \fifo_EEPROM_synchronizer_ff__parameterized0_5\ is
signal Q_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
begin
\out\(5 downto 0) <= Q_reg(5 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[5]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[5]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[5]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[5]_0\(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[5]_0\(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[5]_0\(5),
Q => Q_reg(5)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(5),
O => D(0)
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(5),
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_full_i_reg : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_EEPROM_wr_bin_cntr;
architecture STRUCTURE of fifo_EEPROM_wr_bin_cntr is
signal \gwas.wsts/comp1\ : STD_LOGIC;
signal \gwas.wsts/comp2\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal ram_full_i_i_7_n_0 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[1]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ram_full_i_i_4 : label is "soft_lutpair10";
begin
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
I4 => wr_pntr_plus2(4),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
I5 => wr_pntr_plus2(5),
O => \plusOp__0\(5)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_13_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_13_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_13_out(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(4),
Q => p_13_out(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(5),
Q => p_13_out(5)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => Q(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => Q(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => Q(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => Q(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(4),
Q => Q(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(5),
Q => Q(5)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => wr_pntr_plus2(5)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55550400"
)
port map (
I0 => wr_rst_busy,
I1 => \gwas.wsts/comp2\,
I2 => \out\,
I3 => wr_en,
I4 => \gwas.wsts/comp1\,
O => ram_full_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000009009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(5),
I1 => wr_pntr_plus2(5),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(4),
I3 => wr_pntr_plus2(4),
I4 => ram_full_i_i_4_n_0,
I5 => ram_full_i_i_5_n_0,
O => \gwas.wsts/comp2\
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000009009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(5),
I1 => p_13_out(5),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(4),
I3 => p_13_out(4),
I4 => ram_full_i_i_6_n_0,
I5 => ram_full_i_i_7_n_0,
O => \gwas.wsts/comp1\
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(1),
I2 => wr_pntr_plus2(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(0),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(3),
I2 => wr_pntr_plus2(2),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(2),
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_13_out(1),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(1),
I2 => p_13_out(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(0),
O => ram_full_i_i_6_n_0
);
ram_full_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_13_out(3),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(3),
I2 => p_13_out(2),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[5]\(2),
O => ram_full_i_i_7_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_EEPROM_wr_status_flags_as;
architecture STRUCTURE of fifo_EEPROM_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \grstd1.grst_full.grst_f.rst_d3_reg\,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \grstd1.grst_full.grst_f.rst_d3_reg\,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_EEPROM_blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_EEPROM_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_EEPROM_blk_mem_gen_prim_wrapper
port map (
ADDRARDADDR(5 downto 0) => ADDRARDADDR(5 downto 0),
Q(5 downto 0) => Q(5 downto 0),
WEBWE(0) => WEBWE(0),
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_empty_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gc0.count_d1_reg[0]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d2_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_EEPROM_clk_x_pntrs;
architecture STRUCTURE of fifo_EEPROM_clk_x_pntrs is
signal \__2_n_0\ : STD_LOGIC;
signal \__3_n_0\ : STD_LOGIC;
signal \__4_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 5 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \__4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair2";
begin
\out\(5 downto 0) <= \^out\(5 downto 0);
ram_empty_fb_i_reg_0(5 downto 0) <= \^ram_empty_fb_i_reg_0\(5 downto 0);
\__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \^out\(3),
I1 => \^out\(1),
I2 => \^out\(2),
I3 => \^out\(5),
I4 => \^out\(4),
O => gray2bin(1)
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^out\(3),
I1 => \^out\(2),
I2 => \^out\(5),
I3 => \^out\(4),
O => gray2bin(2)
);
\__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(0),
I2 => p_6_out(1),
I3 => p_6_out(5),
I4 => p_6_out(3),
I5 => p_6_out(4),
O => \__2_n_0\
);
\__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_6_out(3),
I1 => p_6_out(1),
I2 => p_6_out(2),
I3 => p_6_out(5),
I4 => p_6_out(4),
O => \__3_n_0\
);
\__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(3),
I1 => p_6_out(2),
I2 => p_6_out(5),
I3 => p_6_out(4),
O => \__4_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\fifo_EEPROM_synchronizer_ff__parameterized0\
port map (
D(5 downto 0) => p_3_out(5 downto 0),
Q(5 downto 0) => wr_pntr_gc(5 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\fifo_EEPROM_synchronizer_ff__parameterized0_3\
port map (
AR(0) => AR(0),
D(5 downto 0) => p_4_out(5 downto 0),
Q(5 downto 0) => rd_pntr_gc(5 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\fifo_EEPROM_synchronizer_ff__parameterized0_4\
port map (
D(1) => p_0_out,
D(0) => gray2bin(3),
\Q_reg_reg[5]_0\(5 downto 0) => p_3_out(5 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(5 downto 0) => \^out\(5 downto 0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\fifo_EEPROM_synchronizer_ff__parameterized0_5\
port map (
AR(0) => AR(0),
D(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\Q_reg_reg[5]_0\(5 downto 0) => p_4_out(5 downto 0),
\out\(5 downto 0) => p_6_out(5 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => ram_full_i_reg(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \__3_n_0\,
Q => ram_full_i_reg(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \__4_n_0\,
Q => ram_full_i_reg(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => ram_full_i_reg(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => ram_full_i_reg(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(5),
Q => ram_full_i_reg(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[5]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[5]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[5]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[5]\(3),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[5]\(4),
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[5]\(5),
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^ram_empty_fb_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^ram_empty_fb_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => \^ram_empty_fb_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => \^ram_empty_fb_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => \^ram_empty_fb_i_reg_0\(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(5),
Q => \^ram_empty_fb_i_reg_0\(5)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[5]\(0),
I1 => \gic0.gc0.count_d2_reg[5]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[5]\(1),
I1 => \gic0.gc0.count_d2_reg[5]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[5]\(2),
I1 => \gic0.gc0.count_d2_reg[5]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[5]\(3),
I1 => \gic0.gc0.count_d2_reg[5]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[5]\(4),
I1 => \gic0.gc0.count_d2_reg[5]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[5]\(5),
Q => wr_pntr_gc(5)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF82000082"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => Q(0),
I2 => \^ram_empty_fb_i_reg_0\(0),
I3 => Q(1),
I4 => \^ram_empty_fb_i_reg_0\(1),
I5 => \gc0.count_d1_reg[0]\,
O => ram_empty_fb_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00008200"
)
port map (
I0 => ram_empty_i_i_4_n_0,
I1 => \^ram_empty_fb_i_reg_0\(5),
I2 => Q(5),
I3 => rd_en,
I4 => ram_empty_fb_i_reg_1,
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_fb_i_reg_0\(4),
I1 => Q(4),
I2 => \^ram_empty_fb_i_reg_0\(3),
I3 => Q(3),
I4 => Q(2),
I5 => \^ram_empty_fb_i_reg_0\(2),
O => ram_empty_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
\gc0.count_reg[0]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_rd_logic : entity is "rd_logic";
end fifo_EEPROM_rd_logic;
architecture STRUCTURE of fifo_EEPROM_rd_logic is
signal p_7_out : STD_LOGIC;
begin
\gras.rsts\: entity work.fifo_EEPROM_rd_status_flags_as
port map (
E(0) => p_7_out,
empty => empty,
\gc0.count_reg[0]\ => \gc0.count_reg[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0),
\out\ => \out\,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
rpntr: entity work.fifo_EEPROM_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0),
E(0) => p_7_out,
Q(5 downto 0) => Q(5 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[5]\(5 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[5]\(5 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1),
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_EEPROM_reset_blk_ramfifo;
architecture STRUCTURE of fifo_EEPROM_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
wr_rst_busy <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.fifo_EEPROM_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.fifo_EEPROM_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.fifo_EEPROM_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.fifo_EEPROM_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_wr_logic is
port (
full : out STD_LOGIC;
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_rst_busy : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_wr_logic : entity is "wr_logic";
end fifo_EEPROM_wr_logic;
architecture STRUCTURE of fifo_EEPROM_wr_logic is
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal wpntr_n_6 : STD_LOGIC;
begin
WEBWE(0) <= \^webwe\(0);
\gwas.wsts\: entity work.fifo_EEPROM_wr_status_flags_as
port map (
E(0) => \^webwe\(0),
full => full,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => wpntr_n_6,
\out\ => \gwas.wsts_n_1\,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.fifo_EEPROM_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^webwe\(0),
Q(5 downto 0) => Q(5 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[5]\(5 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[5]\(5 downto 0),
\out\ => \gwas.wsts_n_1\,
ram_full_i_reg => wpntr_n_6,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_EEPROM_blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_EEPROM_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_EEPROM_blk_mem_gen_prim_width
port map (
ADDRARDADDR(5 downto 0) => ADDRARDADDR(5 downto 0),
Q(5 downto 0) => Q(5 downto 0),
WEBWE(0) => WEBWE(0),
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_EEPROM_blk_mem_gen_top;
architecture STRUCTURE of fifo_EEPROM_blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_EEPROM_blk_mem_gen_generic_cstr
port map (
ADDRARDADDR(5 downto 0) => ADDRARDADDR(5 downto 0),
Q(5 downto 0) => Q(5 downto 0),
WEBWE(0) => WEBWE(0),
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_blk_mem_gen_v8_3_6_synth is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_blk_mem_gen_v8_3_6_synth : entity is "blk_mem_gen_v8_3_6_synth";
end fifo_EEPROM_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of fifo_EEPROM_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.fifo_EEPROM_blk_mem_gen_top
port map (
ADDRARDADDR(5 downto 0) => ADDRARDADDR(5 downto 0),
Q(5 downto 0) => Q(5 downto 0),
WEBWE(0) => WEBWE(0),
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_blk_mem_gen_v8_3_6 is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_v8_3_6";
end fifo_EEPROM_blk_mem_gen_v8_3_6;
architecture STRUCTURE of fifo_EEPROM_blk_mem_gen_v8_3_6 is
begin
inst_blk_mem_gen: entity work.fifo_EEPROM_blk_mem_gen_v8_3_6_synth
port map (
ADDRARDADDR(5 downto 0) => ADDRARDADDR(5 downto 0),
Q(5 downto 0) => Q(5 downto 0),
WEBWE(0) => WEBWE(0),
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_memory is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRARDADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_memory : entity is "memory";
end fifo_EEPROM_memory;
architecture STRUCTURE of fifo_EEPROM_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.fifo_EEPROM_blk_mem_gen_v8_3_6
port map (
ADDRARDADDR(5 downto 0) => ADDRARDADDR(5 downto 0),
Q(5 downto 0) => Q(5 downto 0),
WEBWE(0) => WEBWE(0),
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_EEPROM_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_EEPROM_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_10\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_11\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_13\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_EEPROM_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(5 downto 0) => rd_pntr_plus1(5 downto 0),
\gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_20\,
\gc0.count_d1_reg[5]\(5) => p_0_out_0(5),
\gc0.count_d1_reg[5]\(4) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\gc0.count_d1_reg[5]\(3) => \gntv_or_sync_fifo.gl0.rd_n_11\,
\gc0.count_d1_reg[5]\(2) => \gntv_or_sync_fifo.gl0.rd_n_12\,
\gc0.count_d1_reg[5]\(1) => \gntv_or_sync_fifo.gl0.rd_n_13\,
\gc0.count_d1_reg[5]\(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
\gic0.gc0.count_d2_reg[5]\(5 downto 0) => p_12_out(5 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(5 downto 0) => p_5_out(5 downto 0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_fb_i_reg_0(5 downto 0) => p_22_out(5 downto 0),
ram_empty_fb_i_reg_1 => p_2_out,
ram_full_i_reg(5 downto 0) => p_23_out(5 downto 0),
rd_clk => rd_clk,
rd_en => rd_en,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => p_5_out(2),
I1 => p_5_out(0),
I2 => p_5_out(1),
I3 => p_5_out(5),
I4 => p_5_out(3),
I5 => p_5_out(4),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_EEPROM_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5) => p_0_out_0(5),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(3) => \gntv_or_sync_fifo.gl0.rd_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(2) => \gntv_or_sync_fifo.gl0.rd_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(1) => \gntv_or_sync_fifo.gl0.rd_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0\(4 downto 0) => p_0_out_0(4 downto 0),
Q(5 downto 0) => rd_pntr_plus1(5 downto 0),
empty => empty,
\gc0.count_reg[0]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[5]\(5 downto 0) => p_22_out(5 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1) => rd_rst_i(2),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(0),
\out\ => p_2_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_20\,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_EEPROM_wr_logic
port map (
AR(0) => wr_rst_i(1),
Q(5 downto 0) => p_12_out(5 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
full => full,
\gnxpm_cdc.rd_pntr_bin_reg[5]\(5 downto 0) => p_23_out(5 downto 0),
\out\ => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.fifo_EEPROM_memory
port map (
ADDRARDADDR(5 downto 0) => p_0_out_0(5 downto 0),
Q(5 downto 0) => p_12_out(5 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_1\,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.fifo_EEPROM_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
rd_clk => rd_clk,
rst => rst,
wr_clk => wr_clk,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_fifo_generator_top : entity is "fifo_generator_top";
end fifo_EEPROM_fifo_generator_top;
architecture STRUCTURE of fifo_EEPROM_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_EEPROM_fifo_generator_ramfifo
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_fifo_generator_v13_1_4_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_fifo_generator_v13_1_4_synth : entity is "fifo_generator_v13_1_4_synth";
end fifo_EEPROM_fifo_generator_v13_1_4_synth;
architecture STRUCTURE of fifo_EEPROM_fifo_generator_v13_1_4_synth is
begin
\gconvfifo.rf\: entity work.fifo_EEPROM_fifo_generator_top
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM_fifo_generator_v13_1_4 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 5 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 61;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 60;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 64;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 6;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 64;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 6;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_EEPROM_fifo_generator_v13_1_4 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_EEPROM_fifo_generator_v13_1_4 : entity is "fifo_generator_v13_1_4";
end fifo_EEPROM_fifo_generator_v13_1_4;
architecture STRUCTURE of fifo_EEPROM_fifo_generator_v13_1_4 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_EEPROM_fifo_generator_v13_1_4_synth
port map (
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_EEPROM is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_EEPROM : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_EEPROM : entity is "fifo_EEPROM,fifo_generator_v13_1_4,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_EEPROM : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_EEPROM : entity is "fifo_generator_v13_1_4,Vivado 2017.1";
end fifo_EEPROM;
architecture STRUCTURE of fifo_EEPROM is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 61;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 60;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 64;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 6;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 64;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 6;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.fifo_EEPROM_fifo_generator_v13_1_4
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(5 downto 0) => B"000000",
prog_empty_thresh_assert(5 downto 0) => B"000000",
prog_empty_thresh_negate(5 downto 0) => B"000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(5 downto 0) => B"000000",
prog_full_thresh_assert(5 downto 0) => B"000000",
prog_full_thresh_negate(5 downto 0) => B"000000",
rd_clk => rd_clk,
rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
e9d9a54f33df6f349cc416de913031ef
| 0.62801 | 2.894262 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/alt_aeq_s4/_primary.vhd
| 1 | 2,503 |
library verilog;
use verilog.vl_types.all;
entity alt_aeq_s4 is
generic(
show_errors : string := "NO";
radce_hflck : vl_logic_vector(0 to 14) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
radce_lflck : vl_logic_vector(0 to 14) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
use_hw_conv_det : vl_logic := Hi0;
number_of_channels: integer := 5;
channel_address_width: integer := 3;
lpm_type : string := "alt_aeq_s4";
lpm_hint : string := "UNUSED"
);
port(
reconfig_clk : in vl_logic;
aclr : in vl_logic;
calibrate : in vl_logic;
shutdown : in vl_logic;
all_channels : in vl_logic;
logical_channel_address: in vl_logic_vector;
remap_address : in vl_logic_vector(11 downto 0);
quad_address : out vl_logic_vector(8 downto 0);
adce_done : in vl_logic_vector;
busy : out vl_logic;
adce_standby : out vl_logic_vector;
adce_continuous : in vl_logic;
adce_cal_busy : out vl_logic;
dprio_busy : in vl_logic;
dprio_in : in vl_logic_vector(15 downto 0);
dprio_wren : out vl_logic;
dprio_rden : out vl_logic;
dprio_addr : out vl_logic_vector(15 downto 0);
dprio_data : out vl_logic_vector(15 downto 0);
eqout : out vl_logic_vector(3 downto 0);
timeout : out vl_logic;
testbuses : in vl_logic_vector;
testbus_sels : out vl_logic_vector;
conv_error : out vl_logic_vector;
error : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of show_errors : constant is 1;
attribute mti_svvh_generic_type of radce_hflck : constant is 1;
attribute mti_svvh_generic_type of radce_lflck : constant is 1;
attribute mti_svvh_generic_type of use_hw_conv_det : constant is 1;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end alt_aeq_s4;
|
bsd-2-clause
|
6596527daafa946908210ea3c46944ca
| 0.557331 | 3.284777 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/afifo_32.vhd
| 1 | 4,056 |
library ieee;
use ieee.std_logic_1164.all;
entity afifo_32 is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(31 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(31 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end entity afifo_32;
architecture rtl of afifo_32 is
--
-- Device specific FIFOs
--
component afifo_32_s6
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(31 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(31 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
component afifo_32_v6
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(31 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(31 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
component afifo_32_k7
port (
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(31 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(31 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
begin
S6_GEN : if (C_FAMILY = "spartan6") generate
afifo_32_s6_l : afifo_32_s6
port map (
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty
);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6") generate
afifo_32_v6_l : afifo_32_v6
port map (
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty
);
end generate V6_GEN;
K7_GEN : if (C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
afifo_32_v6_l : afifo_32_k7
port map (
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
din => din,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
dout => dout,
empty => empty
);
end generate K7_GEN;
end rtl;
|
gpl-3.0
|
35c666c00867db54a8c4ed33f1ddf30c
| 0.338511 | 4.462046 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_watchdog.vhd
| 2 | 4,536 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, <names> All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_wishbone_peripherals_pack.all ;
use work.logi_utils_pack.all ;
entity wishbone_watchdog is
generic(
wb_size : natural := 16; -- Data port size for wishbone
watchdog_timeout_ms : positive := 1000;
clock_period_ns : positive := 10
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reset_out : out std_logic
);
end wishbone_watchdog;
architecture RTL of wishbone_watchdog is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- declare your signals here
constant DIVIDER : positive := 1_000_000/clock_period_ns;
signal enable_watchdog : std_logic ;
signal count_divider : std_logic_vector(nbit(DIVIDER)-1 downto 0);
signal count_timeout : std_logic_vector(nbit(watchdog_timeout_ms)-1 downto 0);
signal reset_watchdog, reset_watchdog_old, reset_watchdog_rising_edge : std_logic ;
signal enable, enable_count : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
enable_watchdog <= '0' ;
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
-- complete with what to do on a write
enable_watchdog <= wbs_writedata(0) ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
-- complete with what to do on a read
wbs_readdata(0) <= enable_watchdog ;
wbs_readdata(15 downto 1) <= (others => '0');
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
--- watchdog logic
reset_watchdog <= write_ack ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
reset_watchdog_old <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
reset_watchdog_old <= reset_watchdog;
end if;
end process ;
reset_watchdog_rising_edge <= (NOT reset_watchdog_old) and reset_watchdog ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
count_divider <= std_logic_vector(to_unsigned(DIVIDER, nbit(DIVIDER))) ;
elsif gls_clk'event and gls_clk = '1' then
if count_divider /= 0 then
count_divider <= count_divider - 1 ;
else
count_divider <= std_logic_vector(to_unsigned(DIVIDER, nbit(DIVIDER))) ;
end if ;
end if;
end process ;
enable_count <= '1' when count_divider = 0 else
'0' ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
count_timeout <= std_logic_vector(to_unsigned(watchdog_timeout_ms, nbit(watchdog_timeout_ms))) ;
elsif gls_clk'event and gls_clk = '1' then
if reset_watchdog_rising_edge = '1' then
count_timeout <= std_logic_vector(to_unsigned(watchdog_timeout_ms, nbit(watchdog_timeout_ms))) ;
elsif count_timeout /= 0 and enable_count = '1' then
count_timeout <= count_timeout - 1 ;
end if ;
end if;
end process ;
reset_out <= '1' when count_timeout = 0 and enable_watchdog = '1' else
'0' ;
end RTL;
|
lgpl-3.0
|
4a6b3825375e874cb5f1f746e4996823
| 0.634921 | 3.39267 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/Mem_Ctrl.vhd
| 2 | 4,648 |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Mem_Ctrl
--Module Description:
-- This module interfaces with the memory resources on the Nexys-2 board. Namely,
-- the Micron RAM and Intel StrataFlash. They share address and data buses,
-- and I wanted to make that transparent to the OZ-3 so I wouldn't have to
-- pull my hair out restructuring the OZ-3 to interface with both memory modules.
-- This works, essentially, by following a clock signal that is twice the
-- frequency of the main clock, and shifted 90 degrees. When that clock signal
-- is high, the Flash has control over the buses, and the RAM when it's low.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mem_Ctrl is
Port ( flash_address_from_OZ3 : in STD_LOGIC_VECTOR(22 downto 0);
dbl_clk_from_OZ3 : in STD_LOGIC;
dRAM_WR_from_OZ3 : in STD_LOGIC;
dRAM_address_from_OZ3 : in STD_LOGIC_VECTOR(22 downto 0);
dRAM_data_from_OZ3 : in STD_LOGIC_VECTOR(15 downto 0);
data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
dRAM_ce : out STD_LOGIC;
dRAM_lb : out STD_LOGIC;
dRAM_ub : out STD_LOGIC;
dRAM_adv : out STD_LOGIC;
dRAM_cre : out STD_LOGIC;
dRAM_clk : out STD_LOGIC;
flash_ce : out STD_LOGIC;
flash_rp : out STD_LOGIC;
mem_oe : out STD_LOGIC;
mem_we : out STD_LOGIC;
address_bus : out STD_LOGIC_VECTOR(22 downto 0);
dRAM_data_to_OZ3 : out STD_LOGIC_VECTOR(15 downto 0);
instruction_to_OZ3 : out STD_LOGIC_VECTOR(15 downto 0));
end Mem_Ctrl;
architecture Behavioral of Mem_Ctrl is
--//Signals\\--
--The main process of the memory bus controller uses these for interfacing with
--the bidirectional memory data bus, and then the 3-state buffer deals with
--using them and actually dealing with the bus
signal data_bus_in : STD_LOGIC_VECTOR(15 downto 0);
signal data_bus_out : STD_LOGIC_VECTOR(15 downto 0);
--\\Signals//--
begin
--Main process of the memory controller
main : process (dbl_clk_from_OZ3, data_bus, flash_address_from_OZ3, dRAM_address_from_OZ3, dRAM_data_from_OZ3) is
begin
--Default values are set for Flash control of the buses
flash_ce <= '0';
dRAM_ce <= '1';
mem_oe <= '0';
mem_we <= '1';
--These inputs that go to the OZ-3 never have to change or be disabled,
--since other logic takes care of using them at the proper times. Therefore,
--placing more logic for that purpose here would be redundant
instruction_to_OZ3 <= data_bus_in;
dRAM_data_to_OZ3 <= data_bus_in;
--If the dRAM needs control, though...
if dbl_clk_from_OZ3 = '0' then
--Everything needed to be set for a RAM read operation by default
flash_ce <= '1';
dRAM_ce <= '0';
--Things need to change a bit for write operations, though. And the
--output bus needs to be driven
if dRAM_WR_from_OZ3 = '1' then
mem_oe <= '1';
mem_we <= '0';
data_bus_out <= dRAM_data_from_OZ3;
end if;
end if;
end process;
--This models a 3-state buffer for using the bidirectional data bus
buffer3 : process (dRAM_WR_from_OZ3, data_bus, data_bus_out) is
begin
--If the OZ-3 needs to drive the bus
if dRAM_WR_from_OZ3 = '1' then
data_bus <= data_bus_out;
--Otherwise, don't drive the bus
else
data_bus <= "ZZZZZZZZZZZZZZZZ";
end if;
data_bus_in <= data_bus;
end process;
--This process multiplexes the Flash and RAM addresses when they
--need to be switched. I would have normally placed this in the main process,
--but something weird was happening at higher frequencies that I can
--only assume has to do with skew due to the other logic in the main
--process. So I just took it out and now it's able to run parallel, and it works
address_MUX : process (dbl_clk_from_OZ3) is
begin
if dbl_clk_from_OZ3 = '1' then --When the Flash has control
address_bus <= flash_address_from_OZ3;
elsif dbl_clk_from_OZ3 = '0' then --When the RAM has control
address_bus <= dRAM_address_from_OZ3;
end if;
end process;
--All of the outputs that remain constant
dRAM_lb <= '0';
dRAM_ub <= '0';
dRAM_adv <= '0';
dRAM_cre <= '0';
dRAM_clk <= '0';
flash_rp <= '1';
end Behavioral;
|
mit
|
f586e851deeeab5dee336a6481358c33
| 0.634251 | 3.425203 | false | false | false | false |
NixOS/nixpkgs
|
pkgs/development/compilers/ghdl/simple-tb.vhd
| 1 | 1,462 |
library ieee;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library STD;
use STD.textio.all;
entity tb is
end tb;
architecture beh of tb is
component simple
port (
CLK, RESET : in std_ulogic;
DATA_OUT : out std_ulogic_vector(7 downto 0);
DONE_OUT : out std_ulogic
);
end component;
signal data : std_ulogic_vector(7 downto 0) := "00100000";
signal clk : std_ulogic;
signal RESET : std_ulogic := '0';
signal done : std_ulogic := '0';
signal cyclecount : integer := 0;
constant cycle_time_c : time := 200 ms;
constant maxcycles : integer := 100;
begin
simple1 : simple
port map (
CLK => clk,
RESET => RESET,
DATA_OUT => data,
DONE_OUT => done
);
clk_process : process
begin
clk <= '0';
wait for cycle_time_c/2;
clk <= '1';
wait for cycle_time_c/2;
end process;
count_process : process(CLK)
begin
if (CLK'event and CLK ='1') then
if (RESET = '1') then
cyclecount <= 0;
else
cyclecount <= cyclecount + 1;
end if;
end if;
end process;
test : process
begin
RESET <= '1';
wait until (clk'event and clk='1');
wait until (clk'event and clk='1');
RESET <= '0';
wait until (clk'event and clk='1');
for cyclecnt in 1 to maxcycles loop
exit when done = '1';
wait until (clk'event and clk='1');
report integer'image(to_integer(unsigned(data)));
end loop;
wait until (clk'event and clk='1');
report "All tests passed." severity NOTE;
wait;
end process;
end beh;
|
mit
|
9c250320094c108f411b291bebb5c33b
| 0.640903 | 3.110638 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen.vhd
| 1 | 4,721 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
gpl-3.0
|
9565e96b36b3568ae9ac1cb4e7f1bedf
| 0.60771 | 4.08391 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_32_v6_ste/example_design/afifo_32_v6_top.vhd
| 1 | 19,612 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_32_v6_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_32_v6_top;
architecture xilinx of afifo_32_v6_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_32_v6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_32_v6
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
gpl-3.0
|
53033ddc3cadc91b88c6281386573b08
| 0.475117 | 3.96042 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth.vhd
| 1 | 10,215 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 5,
C_DOUT_WIDTH => 5,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
1cdbb434e55453828d6513fd7e182e65
| 0.474107 | 4.087635 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_dgen.vhd
| 1 | 4,720 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
gpl-3.0
|
6c660016bcdc172765122b81b6bc9b38
| 0.607627 | 4.083045 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/dcfifo_sync/_primary.vhd
| 1 | 1,796 |
library verilog;
use verilog.vl_types.all;
entity dcfifo_sync is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
intended_device_family: string := "Stratix";
lpm_showahead : string := "OFF";
underflow_checking: string := "ON";
overflow_checking: string := "ON";
use_eab : string := "ON";
add_ram_output_register: string := "OFF"
);
port(
data : in vl_logic_vector;
rdclk : in vl_logic;
wrclk : in vl_logic;
aclr : in vl_logic;
rdreq : in vl_logic;
wrreq : in vl_logic;
rdfull : out vl_logic;
wrfull : out vl_logic;
rdempty : out vl_logic;
wrempty : out vl_logic;
rdusedw : out vl_logic_vector;
wrusedw : out vl_logic_vector;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_width : constant is 1;
attribute mti_svvh_generic_type of lpm_widthu : constant is 1;
attribute mti_svvh_generic_type of lpm_numwords : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_showahead : constant is 1;
attribute mti_svvh_generic_type of underflow_checking : constant is 1;
attribute mti_svvh_generic_type of overflow_checking : constant is 1;
attribute mti_svvh_generic_type of use_eab : constant is 1;
attribute mti_svvh_generic_type of add_ram_output_register : constant is 1;
end dcfifo_sync;
|
bsd-2-clause
|
c132318c6d9eeeef056325f862ddd10a
| 0.55902 | 3.929978 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/mmcm_iserdes_divider_v6/simulation/mmcm_iserdes_divider_v6_tb.vhd
| 1 | 5,850 |
-- file: mmcm_iserdes_divider_v6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity mmcm_iserdes_divider_v6_tb is
end mmcm_iserdes_divider_v6_tb;
architecture test of mmcm_iserdes_divider_v6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 1.613 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
signal CLK_IN1_P : std_logic := '1';
signal CLK_IN1_N : std_logic := '0';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
component mmcm_iserdes_divider_v6_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
CLK_IN1_P <= CLK_IN1;
CLK_IN1_N <= not CLK_IN1;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*COUNT_PHASE);
simtimeprint;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : mmcm_iserdes_divider_v6_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1_P => CLK_IN1_P,
CLK_IN1_N => CLK_IN1_N,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
end test;
|
gpl-3.0
|
88485b620aa5ab67841008fc750069a1
| 0.617607 | 4.16074 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/small_fifo.vhd
| 2 | 2,306 |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end small_fifo;
architecture Behavioral of small_fifo is
type mem_array is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
signal fifo : mem_array ;
signal rd_ptr, wr_ptr : integer range 0 to DEPTH-1 ;
signal full_t, empty_t : std_logic ;
signal nb_available : integer range 0 to DEPTH-1 ;
begin
process(clk, resetn)
begin
if resetn = '0' then
rd_ptr <= 0 ;
wr_ptr <= 0 ;
nb_available <= 0 ;
elsif clk'event and clk = '1' then
if push = '1' and full_t = '0' then
wr_ptr <= (wr_ptr + 1) ;
fifo(wr_ptr) <= data_in ;
if pop = '0' then
nb_available <= nb_available + 1 ;
end if ;
end if ;
if pop = '1' and empty_t = '0' then
rd_ptr <= rd_ptr + 1 ;
if push = '0' then
nb_available <= nb_available - 1 ;
end if ;
end if ;
end if ;
end process ;
full_t <= '1' when nb_available = DEPTH-1 else
'0' ;
empty_t <= '1' when nb_available = 0 else
'0' ;
data_out <= fifo(rd_ptr) when empty_t = '0' else
(others => '0');
limit <= '1' when nb_available >= THRESHOLD else
'0' ;
empty <= empty_t ;
full <= full_t ;
end Behavioral;
|
lgpl-3.0
|
a3c4aa64a805656c1ba56d9ccff1dac2
| 0.590199 | 3.22067 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_tb.vhd
| 1 | 6,399 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 30
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-3.0
|
516722ec9122d5f4defee4c2ecc7fb29
| 0.623691 | 3.942699 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_k7/simulation/fg_tb_pkg.vhd
| 1 | 11,733 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pulse_regen_k7_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-3.0
|
5539bdebc755b73164b944a3555c3b3c
| 0.48777 | 3.959838 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altsquare/_primary.vhd
| 1 | 1,174 |
library verilog;
use verilog.vl_types.all;
entity altsquare is
generic(
data_width : integer := 1;
result_width : integer := 1;
pipeline : integer := 0;
representation : string := "UNSIGNED";
result_alignment: string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
data : in vl_logic_vector;
clock : in vl_logic;
ena : in vl_logic;
aclr : in vl_logic;
result : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of data_width : constant is 1;
attribute mti_svvh_generic_type of result_width : constant is 1;
attribute mti_svvh_generic_type of pipeline : constant is 1;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of result_alignment : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end altsquare;
|
bsd-2-clause
|
9fce9957deb78c6725a3d28fc2193151
| 0.582624 | 3.979661 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_32_k7_ste/example_design/afifo_32_k7_top.vhd
| 1 | 19,612 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_32_k7_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_32_k7_top;
architecture xilinx of afifo_32_k7_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_32_k7 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_32_k7
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
gpl-3.0
|
03e0b0dc9516dbaddda0bf74558a6bf3
| 0.475117 | 3.96042 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl.vhd
| 1 | 15,657 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-3.0
|
393ec833c295086a336004ff78035d02
| 0.525133 | 3.364926 | false | false | false | false |
diedricm/prMagicTutorial
|
src/myTopEntity.vhd
| 1 | 930 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity myTopEntity is
Port (
clk : in STD_LOGIC;
rst : in std_logic;
leds : out STD_LOGIC_VECTOR (7 downto 0));
end myTopEntity;
architecture Behavioral of myTopEntity is
component rshiftLEDs is
Port ( trigger : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (7 downto 0));
end component rshiftLEDs;
component upcounter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rst_val : in STD_LOGIC_VECTOR (15 downto 0);
trigger : out STD_LOGIC);
end component upcounter;
signal itrigger : std_logic;
begin
leddriver: rshiftLEDs
port map(
trigger => itrigger,
leds => leds
);
triggercounter: upcounter
port map(
clk => clk,
rst => rst,
rst_val => X"DEAD",
trigger => itrigger
);
end Behavioral;
|
gpl-3.0
|
9691de47e4d8a2dd23020c56748f5f9b
| 0.572043 | 4.043478 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes.vhd
| 1 | 5,718 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(20-1 DOWNTO 0);
DOUT : OUT std_logic_vector(20-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1_1 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(20-1 DOWNTO 0);
DOUT : OUT std_logic_vector(20-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_1
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
0190daa074845a336adddde9a7068394
| 0.527282 | 4.509464 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/syncchanneldecoder.vhd
| 1 | 37,489 |
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2010-07-02 09:41:24 +0200 (vr, 02 jul 2010) $
-- Revision : $Revision: 531 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
library work;
use work.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity syncchanneldecoder is
generic (
NROF_CONN : integer;
DATAWIDTH : integer;
NROF_WINDOWS : integer
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
-- Internal signaling
en_decoder : in std_logic;
--busy_decoder : out std_logic;
PAR_DATA_RDEN : out std_logic;
PAR_DATA_EMPTY : in std_logic;
PAR_DATAIN : in std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0);
PAR_SYNCOUT : out std_logic_vector((DATAWIDTH)-1 downto 0);
PAR_DATAOUT : out std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID : out std_logic;
PAR_DATA_BLACKVALID : out std_logic;
PAR_DATA_LINE : out std_logic;
PAR_DATA_FRAME : out std_logic;
KERNEL_ODD_EVEN : out std_logic;
START_KERNEL : out std_logic;
StartOddEven : in std_logic_vector(31 downto 0);
LS_value : in std_logic_vector(9 downto 0);
LE_value : in std_logic_vector(9 downto 0);
FS_value : in std_logic_vector(9 downto 0);
FE_value : in std_logic_vector(9 downto 0);
BL_value : in std_logic_vector(9 downto 0);
IMG_value : in std_logic_vector(9 downto 0);
TR_value : in std_logic_vector(9 downto 0);
CRC_value : in std_logic_vector(9 downto 0);
-- synchro signals
framestart : out std_logic;
windowstart : out std_logic;
windowend : out std_logic;
linestart : out std_logic;
lineend : out std_logic;
blacklinestart : out std_logic;
blacklineend : out std_logic;
imagelinestart : out std_logic;
imagelineend : out std_logic;
validcrc : out std_logic;
-- counters
FramesCnt : out std_logic_vector(31 downto 0);
-- lines/frame counter
BlackLinesCnt : out std_logic_vector(31 downto 0);
ImgLinesCnt : out std_logic_vector(31 downto 0);
-- pixels/frame counter
BlackPixelCnt : out std_logic_vector(31 downto 0);
ImgPixelCnt : out std_logic_vector(31 downto 0);
-- windows/frame counter
WindowsCnt : out std_logic_vector(31 downto 0);
-- clocks/frame counter -> fps
ClocksCnt : out std_logic_vector(31 downto 0);
StartLineCnt : out std_logic_vector(31 downto 0);
EndLineCnt : out std_logic_vector(31 downto 0);
-- monitors
MONITOR : in std_logic_vector(1 downto 0);
Monitor0HighCnt : out std_logic_vector(31 downto 0);
Monitor0LowCnt : out std_logic_vector(31 downto 0);
Monitor1HighCnt : out std_logic_vector(31 downto 0);
Monitor1LowCnt : out std_logic_vector(31 downto 0)
);
end syncchanneldecoder;
---------------------------
-- BEHAVIOUR DESCRIPTION --
---------------------------
architecture rtl of syncchanneldecoder is
alias SyncChannel : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1) downto 0);
alias DataChannels : std_logic_vector(((NROF_CONN-1)*DATAWIDTH-1) downto 0) is PAR_DATAIN((NROF_CONN*DATAWIDTH-1) downto DATAWIDTH);
--debug only
--inp
alias DataChannel0 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+1*DATAWIDTH downto 1*DATAWIDTH);
alias DataChannel1 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+2*DATAWIDTH downto 2*DATAWIDTH);
alias DataChannel2 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+3*DATAWIDTH downto 3*DATAWIDTH);
alias DataChannel3 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAIN((DATAWIDTH-1)+4*DATAWIDTH downto 4*DATAWIDTH);
--outp
alias ParOutChannel0 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+0*DATAWIDTH downto 0*DATAWIDTH);
alias ParOutChannel1 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+1*DATAWIDTH downto 1*DATAWIDTH);
alias ParOutChannel2 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+2*DATAWIDTH downto 2*DATAWIDTH);
alias ParOutChannel3 : std_logic_vector((DATAWIDTH-1) downto 0) is PAR_DATAOUT((DATAWIDTH-1)+3*DATAWIDTH downto 3*DATAWIDTH);
type SyncDelayPipetp is array (0 to 5) of std_logic_vector((DATAWIDTH-1) downto 0);
signal SyncDelayPipe : SyncDelayPipetp;
type DataDelayPipetp is array (0 to SyncDelayPipe'high) of std_logic_vector(((NROF_CONN-1)*DATAWIDTH-1) downto 0);
signal DataDelayPipe : DataDelayPipetp;
signal DataValidPipe : std_logic_vector(0 to 5);
constant zeros : std_logic_vector((DATAWIDTH-1) downto 0) := (others => '0');
--signal extstartframe : std_logic;
--signal intstartframe : std_logic;
signal startframe : std_logic;
signal startwindow : std_logic;
signal endwindow : std_logic;
signal startwindowid : std_logic_vector(1023 downto 0);
signal endwindowid : std_logic_vector(1023 downto 0);
signal windowid : std_logic_vector((DATAWIDTH-1) downto 0);
signal startline : std_logic;
signal endline : std_logic;
signal startblackline : std_logic;
signal endblackline : std_logic;
signal startimageline : std_logic;
signal endimageline : std_logic;
signal blackdatavalid : std_logic;
signal imgdatavalid : std_logic;
signal datavalid : std_logic;
signal crcvalid : std_logic;
signal en_valid : std_logic;
--signal firststartframe : std_logic;
--signal nextstartframe : std_logic;
signal StartLineCntr : std_logic_vector(31 downto 0);
signal EndLineCntr : std_logic_vector(31 downto 0);
signal rst_cntrs : std_logic;
signal decode : std_logic;
--signal dec : std_logic;
signal enpipe : std_logic_vector(15 downto 0);
signal syncvalid : std_logic;
signal syncvalid_r : std_logic;
-- framescounter
signal FramesCntr : std_logic_vector(31 downto 0);
-- lines/frame counter
signal BlackLinesCntr : std_logic_vector(31 downto 0);
signal ImgLinesCntr : std_logic_vector(31 downto 0);
-- pixels/frame counter
signal BlackPixelCntr : std_logic_vector(31 downto 0);
signal ImgPixelCntr : std_logic_vector(31 downto 0);
-- windows/frame counter
signal WindowsCntr : std_logic_vector(31 downto 0);
-- clocks/frame counter -> fps
signal ClocksCntr : std_logic_vector(31 downto 0);
--signal ClocksCnt : std_logic_vector(31 downto 0);
type DataStatetp is (
Idle,
Valid
);
signal BlackDataState : DataStatetp;
signal ImgDataState : DataStatetp;
type DecoderEnablerStatetp is (
Idle,
DetectEnableStart,
--DetectFirstFrameStart,
Enabled
);
signal DecoderEnablerState : DecoderEnablerStatetp;
type blacklinecntstatetp is (
WaitFirstBlackLine,
CountBlackLines
);
signal blacklinecntstate : blacklinecntstatetp;
signal Monitor0HighCntr : std_logic_vector(31 downto 0);
signal Monitor0LowCntr : std_logic_vector(31 downto 0);
signal Monitor1HighCntr : std_logic_vector(31 downto 0);
signal Monitor1LowCntr : std_logic_vector(31 downto 0);
signal monitor_rising : std_logic_vector(1 downto 0);
signal monitor_falling : std_logic_vector(1 downto 0);
type Monitor_synctp is array (2 downto 0) of std_logic_vector(1 downto 0);
signal Monitor_sync : Monitor_synctp;
begin
PAR_DATA_RDEN <= enpipe(4);
en_valid <= enpipe(15) and en_decoder;
syncvalid <= not PAR_DATA_EMPTY;
syncvalid_r <= DataValidPipe(0);
EnPipePr: process(RESET, CLOCK)
begin
if (RESET = '1') then
enpipe <= (others => '0');
elsif (CLOCK'event and CLOCK = '1') then
enpipe(0) <= en_decoder;
for i in 0 to enpipe'high-1 loop
enpipe(i+1) <= enpipe(i);
end loop;
end if;
end process;
DataPipe: process(RESET, CLOCK)
begin
if (RESET = '1') then
SyncDelayPipe <= (others => (others => '0'));
PAR_SYNCOUT <= (others => '0');
-- DataDelayPipe doesnt need reset state
DataValidPipe <= (others => '0');
PAR_DATA_LINE <= '0';
PAR_DATA_FRAME <= '0';
elsif (CLOCK'event and CLOCK = '1') then
PAR_DATA_LINE <= (startimageline or startblackline) and syncvalid_r; --needs one cycle delay
PAR_DATA_FRAME <= startframe and syncvalid_r;
if (PAR_DATA_EMPTY = '0') then
SyncDelayPipe(0) <= SyncChannel;
DataDelayPipe(0) <= DataChannels;
for i in 0 to (SyncDelayPipe'high-1) loop
SyncDelayPipe(i+1) <= SyncDelayPipe(i);
DataDelayPipe(i+1) <= DataDelayPipe(i);
end loop;
end if;
PAR_DATAOUT <= DataDelayPipe(3);
PAR_SYNCOUT <= SyncDelayPipe(3);
for i in 0 to (DataValidPipe'high-1) loop
DataValidPipe(i+1) <= DataValidPipe(i);
end loop;
DataValidPipe(0) <= not PAR_DATA_EMPTY;
end if;
end process;
PAR_DATA_IMGVALID <= imgdatavalid and DataValidPipe(1);
PAR_DATA_BLACKVALID <= blackdatavalid and DataValidPipe(1);
framestart <= startframe;
windowstart <= startwindow;
windowend <= endwindow;
linestart <= startline;
lineend <= endline;
blacklinestart <= startblackline;
blacklineend <= endblackline;
imagelinestart <= startimageline;
imagelineend <= endimageline;
validcrc <= crcvalid and DataValidPipe(1);
-- counters
FramesCnt <= FramesCntr;
-- lines/frame count
BlackLinesCnt <= BlackLinesCntr;
ImgLinesCnt <= ImgLinesCntr;
-- pixels/frame count
BlackPixelCnt <= BlackPixelCntr;
ImgPixelCnt <= ImgPixelCntr;
-- windows/frame count
WindowsCnt <= WindowsCntr;
--
StartLineCnt <= StartLineCntr;
EndLineCnt <= EndLineCntr;
--extstartframe <= nextstartframe or firststartframe;
Decoder: process(RESET, CLOCK)
begin
if (RESET = '1') then
startframe <= '0';
startwindow <= '0';
endwindow <= '0';
startline <= '0';
startblackline <= '0';
startimageline <= '0';
endline <= '0';
endblackline <= '0';
endimageline <= '0';
datavalid <= '0';
blackdatavalid <= '0';
imgdatavalid <= '0';
crcvalid <= '0';
-- StartFrameState <= Idle;
BlackDataState <= Idle;
windowid <= (others => '0');
startwindowid <= (others => '0');
endwindowid <= (others => '0');
-- firststartframe <= '0';
-- nextstartframe <= '0';
decode <= '0';
elsif (CLOCK'event and CLOCK = '1') then
-- detect framestart by:
-- 1. first looking for a linestart from a blackline
-- 2. then look for the first framestart available
--framedetection for decoder enabler
-- startframe is detected 2 clks before internal startframe, should be enough
--firststartframe <= '0';
if (en_valid = '1') then
--if (syncvalid = '1') then
case DecoderEnablerState is
when Idle =>
decode <= '0';
if (SyncDelayPipe(2) = LS_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(0) = BL_value(9 downto (10-DATAWIDTH))) then
DecoderEnablerState <= DetectEnableStart;
end if;
when DetectEnableStart =>
if (SyncDelayPipe(0) = FS_value(9 downto (10-DATAWIDTH))) then
decode <= '1';
--firststartframe <= '1';
DecoderEnablerState <= Enabled;
end if;
when Enabled =>
decode <= '1';
when others =>
DecoderEnablerState <= Idle;
end case;
--end if;
else
decode <= '0';
DecoderEnablerState <= Idle;
end if;
if (decode = '1') then
startframe <= '0';
if (SyncDelayPipe(2) = FS_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(1) = zeros(9 downto (10-DATAWIDTH) )) then
startframe <= '1';
end if;
else
startframe <= '0';
end if;
-- frameend detect, not feasible without software...
--start window detection
if (decode = '1') then
startwindow <= '0';
startwindowid <= (others => '0');
if (SyncDelayPipe(2) = FS_value(9 downto (10-DATAWIDTH))) then
startwindow <= '1';
startwindowid( TO_INTEGER(UNSIGNED(SyncDelayPipe(1))) ) <= '1';
windowid <= SyncDelayPipe(1);
end if;
else
startwindow <= '0';
startwindowid <= (others => '0');
end if;
--end window detection
if (decode = '1') then
endwindow <= '0';
endwindowid <= (others => '0');
if (SyncDelayPipe(4) = FE_value(9 downto (10-DATAWIDTH))) then
endwindow <= '1';
endwindowid(TO_INTEGER(UNSIGNED(SyncDelayPipe(3))) ) <= '1';
end if;
else
endwindowid <= (others => '0');
endwindow <= '0';
end if;
-- start line pulse generation
--startline is detected every startline code passes
if (decode = '1') then
startline <= '0';
if (SyncDelayPipe(2) = LS_value(9 downto (10-DATAWIDTH))) then
startline <= '1';
end if;
else
startline <= '0';
end if;
--startblackline is detected after every combination of LS + dontcare + BL
if (decode = '1') then
startblackline <= '0';
if (SyncDelayPipe(2) = LS_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(0) = BL_value(9 downto (10-DATAWIDTH))) then
startblackline <= '1';
end if;
else
startblackline <= '0';
end if;
--startimageline is detected after either:
-- 1. LS + dontcare + IMG (a normal line without a funny windowing exception)
-- 2. LS + LS + dontcare (2 linestarts right after eachother -> 2 startimagelines will be detected)
-- 3. LS + dontcare + LS (2 linestarts almost right after eachother -> 2 startimagelines will be detected
-- 4. in theory 3 linestarts could follow eachother, this is not supported for now.
-- 5. the same with FS in place of LS (ignore MSB)
-- note: case 2 and case 4 are probably not possible
if (decode = '1') then
startimageline <= '0';
if ((SyncDelayPipe(2)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(0) = IMG_value(9 downto (10-DATAWIDTH))) or
(SyncDelayPipe(2)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(1)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH))) or
(SyncDelayPipe(2)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(0)(DATAWIDTH-2 downto 0) = LS_value(8 downto (10-DATAWIDTH)))
) then
startimageline <= '1';
end if;
else
startimageline <= '0';
end if;
-- end line pulse generation
-- endline is detected every endline code passes
if (decode = '1') then
endline <= '0';
if (SyncDelayPipe(4) = LE_value(9 downto (10-DATAWIDTH))) then
endline <= '1';
end if;
else
endline <= '0';
end if;
-- endblackline is detected after BL + LE
if (decode = '1') then
endblackline <= '0';
if (SyncDelayPipe(5) = BL_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(4) = LE_value(9 downto (10-DATAWIDTH))) then
endblackline <= '1';
end if;
else
endblackline <= '0';
end if;
-- endimageline is detected after either
-- 1. IMG + LE
-- 2. LE + LE
-- 3 the same with frameend
if (decode = '1') then
endimageline <= '0';
if (SyncDelayPipe(5) = IMG_value(9 downto (10-DATAWIDTH)) and SyncDelayPipe(4)(DATAWIDTH-2 downto 0) = LE_value(8 downto (10-DATAWIDTH))) or
(SyncDelayPipe(5)(DATAWIDTH-2 downto 0) = LE_value(8 downto (10-DATAWIDTH)) and SyncDelayPipe(4)(DATAWIDTH-2 downto 0) = LE_value(8 downto (10-DATAWIDTH)))
then
endimageline <= '1';
end if;
else
endimageline <= '0';
end if;
-- data valid generation
-- simple valid data, independant of black or img
-- always valid except when TR and CRC are present
datavalid <= '0';
if (decode = '1') then
if (SyncDelayPipe(3) = TR_value(9 downto (10-DATAWIDTH)) or
SyncDelayPipe(3) = CRC_value(9 downto (10-DATAWIDTH))
) then
datavalid <= '0';
else
datavalid <= '1';
end if;
end if;
--black data valid
-- black lines are non overlapping with other windows -> all blackline start/ blackline end pulses should be present
if (decode = '1') then
case BlackDataState is
when Idle =>
if (startblackline = '1' and syncvalid_r = '1') then
blackdatavalid <= '1';
BlackDataState <= Valid;
else
blackdatavalid <= '0';
end if;
when Valid =>
if (endblackline = '1' and syncvalid_r = '1') then
blackdatavalid <= '0';
BlackDataState <= Idle;
else
blackdatavalid <= '1';
end if;
end case;
else
blackdatavalid <= '0';
BlackDataState <= Idle;
end if;
-- image data valid -> valid data and not black data = img data
--img data valid
--imgdatavalid <= datavalid and not blackdatavalid;
if (decode = '1') then
case ImgDataState is
when Idle =>
if (startimageline = '1' and syncvalid_r = '1') then
imgdatavalid <= '1';
ImgDataState <= Valid;
else
imgdatavalid <= '0';
end if;
when Valid =>
if (endimageline = '1' and startimageline = '0' and syncvalid_r = '1') then
imgdatavalid <= '0';
ImgDataState <= Idle;
else
imgdatavalid <= '1';
end if;
end case;
else
imgdatavalid <= '0';
ImgDataState <= Idle;
end if;
-- CRC
if (decode = '1') then
crcvalid <= '0';
if (SyncDelayPipe(3) = CRC_value(9 downto (10-DATAWIDTH))) then
crcvalid <= '1';
end if;
else
crcvalid <= '0';
end if;
end if;
end process;
Counters: process(RESET, CLOCK)
begin
if (RESET = '1') then
StartLineCntr <= (others => '0');
EndLineCntr <= (others => '0');
rst_cntrs <= '0';
FramesCntr <= (others => '0');
BlackLinesCntr <= (others => '0');
ImgLinesCntr <= (others => '0');
BlackPixelCntr <= (others => '0');
ImgPixelCntr <= (others => '0');
WindowsCntr <= (others => '0');
ClocksCntr <= (others => '0');
ClocksCnt <= (others => '0');
elsif (CLOCK'event and CLOCK = '1') then
-- counter rst logic
if (enpipe(0) = '1' and enpipe(1) = '0') then --rising edge
rst_cntrs <= '1';
else
rst_cntrs <= '0';
end if;
-- startlinecounter (/readout) (including black lines)
if (rst_cntrs = '1' ) then
StartLineCntr <= (others => '0');
EndLineCntr <= (others => '0');
else
if (syncvalid_r = '1') then
if (startline = '1' and decode = '1') then
StartLineCntr <= StartLineCntr + '1';
end if;
if (endline = '1' and decode = '1') then
EndLineCntr <= EndLineCntr + '1';
end if;
end if;
end if;
-- framescounter
if (rst_cntrs = '1') then
FramesCntr <= (others => '0');
else
if (syncvalid_r = '1') then
if (startframe = '1' and decode = '1') then
FramesCntr <= FramesCntr + '1';
end if;
end if;
end if;
-- lines/frame counter
-- counts total amount of blacklines
if (rst_cntrs = '1') then
BlackLinesCntr <= (others => '0');
blacklinecntstate <= WaitFirstBlackLine;
else
if (syncvalid_r = '1') then
case blacklinecntstate is
when WaitFirstBlackLine =>
if (startblackline = '1') then
BlackLinesCntr <= X"00000001";
blacklinecntstate <= CountBlackLines;
end if;
when CountBlackLines =>
if (startblackline = '1') then
BlackLinesCntr <= BlackLinesCntr + '1';
elsif (startimageline = '1') then
blacklinecntstate <= WaitFirstBlackLine;
end if;
when others =>
blacklinecntstate <= WaitFirstBlackLine;
end case;
end if;
end if;
if (rst_cntrs = '1' or (startframe = '1' and decode = '1')) then
ImgLinesCntr <= (others => '0');
else
if (syncvalid_r = '1' and decode = '1') then
if (startimageline = '1') then
ImgLinesCntr <= ImgLinesCntr + '1';
end if;
end if;
end if;
-- pixels/frame counter
if (rst_cntrs = '1' or startblackline = '1') then
BlackPixelCntr <= (others => '0');
else
if (syncvalid_r = '1') then
if (blackdatavalid = '1') then
BlackPixelCntr <= BlackPixelCntr + '1';
end if;
end if;
end if;
if (rst_cntrs = '1' or (startimageline = '1' and decode = '1')) then
ImgPixelCntr <= (others => '0');
else
if (syncvalid_r = '1' and decode = '1') then
if (imgdatavalid = '1') then
ImgPixelCntr <= ImgPixelCntr + '1';
end if;
end if;
end if;
-- windows/frame counter
if (rst_cntrs = '1') then
WindowsCntr <= (others => '0');
elsif (startframe = '1' and decode = '1') then --equal to the first window start
WindowsCntr <= X"00000001";
else
if (syncvalid_r = '1' and decode = '1') then
if (startwindow = '1') then
WindowsCntr <= WindowsCntr + '1';
end if;
end if;
end if;
-- clocks/frame counter -> fps
if (startframe = '1' and syncvalid_r = '1') then
ClocksCntr <= (others => '0');
ClocksCnt <= ClocksCntr;
else
ClocksCntr <= ClocksCntr + '1';
end if;
end if;
end process;
-- should run sync to data
Odd_Even_indication: process(RESET, CLOCK)
begin
if (RESET = '1') then
KERNEL_ODD_EVEN <= '0';
START_KERNEL <= '0';
elsif(CLOCK = '1' and CLOCK'event) then
START_KERNEL <= '0';
if (startwindow = '1') then
KERNEL_ODD_EVEN <= StartOddEven(to_integer(unsigned(windowid(4 downto 0))));
START_KERNEL <= '1';
end if;
end if;
end process;
-- monitor parser
-- also used for lightsource triggering
monitor_parser: process(RESET, CLOCK)
begin
if (RESET = '1') then
Monitor0HighCntr <= (others => '0');
Monitor0LowCntr <= (others => '0');
Monitor1HighCntr <= (others => '0');
Monitor1LowCntr <= (others => '0');
Monitor0HighCnt <= (others => '0');
Monitor0LowCnt <= (others => '0');
Monitor1HighCnt <= (others => '0');
Monitor1LowCnt <= (others => '0');
for i in 0 to 1 loop
monitor_rising(i) <= '0';
monitor_falling(i) <= '0';
end loop;
Monitor_sync <= (others => (others => '0'));
elsif(CLOCK = '1' and CLOCK'event) then
--defaults
Monitor_sync(0)(0) <= MONITOR(0);
Monitor_sync(0)(1) <= MONITOR(1);
for i in 0 to (Monitor_sync'high - 1) loop
Monitor_sync(i+1) <= Monitor_sync(i);
end loop;
-- monitor counters
for i in 0 to 1 loop
--defaults
monitor_rising(i) <= '0';
monitor_falling(i) <= '0';
if (decode = '1') then
if (Monitor_sync(2)(i) = '0' and Monitor_sync(1)(i) = '1') then --rising edge
monitor_rising(i) <= '1';
elsif (Monitor_sync(2)(0) = '1' and Monitor_sync(1)(i) = '0') then --falling edge
monitor_falling(i) <= '1';
end if;
end if;
end loop;
if (decode = '1') then
if (monitor_rising(0) = '1') then
Monitor0HighCnt <= Monitor0HighCntr;
Monitor0HighCntr <= (others => '0');
elsif (Monitor_sync(2)(0) = '1') then
Monitor0HighCntr <= Monitor0HighCntr + '1';
end if;
if (monitor_falling(0) = '1') then
Monitor0LowCnt <= Monitor0LowCntr;
Monitor0LowCntr <= (others => '0');
elsif (Monitor_sync(2)(0) = '0') then
Monitor0LowCntr <= Monitor0LowCntr + '1';
end if;
if (monitor_rising(1) = '1') then
Monitor1HighCnt <= Monitor1HighCntr;
Monitor1HighCntr <= (others => '0');
elsif (Monitor_sync(2)(1) = '1') then
Monitor1HighCntr <= Monitor1HighCntr + '1';
end if;
if (monitor_falling(1) = '1') then
Monitor1LowCnt <= Monitor1LowCntr;
Monitor1LowCntr <= (others => '0');
elsif (Monitor_sync(2)(1) = '0') then
Monitor1LowCntr <= Monitor1LowCntr + '1';
end if;
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
fe987883966583cf31dc44a05f5029a8
| 0.42135 | 5.071564 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/stratixiii_lvds_rx_dpa/_primary.vhd
| 1 | 1,633 |
library verilog;
use verilog.vl_types.all;
entity stratixiii_lvds_rx_dpa is
generic(
enable_soft_cdr_mode: string := "OFF";
sim_dpa_is_negative_ppm_drift: string := "OFF";
sim_dpa_net_ppm_variation: integer := 0;
enable_dpa_align_to_rising_edge_only: string := "OFF";
enable_dpa_initial_phase_selection: string := "OFF";
dpa_initial_phase_value: integer := 0;
INITIAL_PHASE_SELECT: vl_notype;
PHASE_NUM : integer := 8
);
port(
rx_in : in vl_logic;
rx_fastclk : in vl_logic;
rx_enable : in vl_logic;
rx_dpa_reset : in vl_logic;
rx_dpa_hold : in vl_logic;
rx_out : out vl_logic;
rx_dpa_clk : out vl_logic;
rx_dpa_loaden : out vl_logic;
rx_dpa_locked : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1;
attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1;
attribute mti_svvh_generic_type of INITIAL_PHASE_SELECT : constant is 3;
attribute mti_svvh_generic_type of PHASE_NUM : constant is 1;
end stratixiii_lvds_rx_dpa;
|
bsd-2-clause
|
31d40ae8124bf6f2642bcf4a61bc276d
| 0.619718 | 3.42348 | false | false | false | false |
miguelgarcia/sase2017-hls-video
|
hdmi_in_hls/repo/sase/hdl/vhdl/my_video_filter_mul_16ns_32ns_48_3.vhd
| 2 | 2,737 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(48 - 1 downto 0));
end entity;
architecture behav of my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
signal tmp_product : std_logic_vector(48 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(48 - 1 downto 0);
signal a_reg0 : std_logic_vector(16 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(48 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 48));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity my_video_filter_mul_16ns_32ns_48_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of my_video_filter_mul_16ns_32ns_48_3 is
component my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
my_video_filter_mul_16ns_32ns_48_3_Mul3S_0_U : component my_video_filter_mul_16ns_32ns_48_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
gpl-3.0
|
72aedc6f42fe9441763d4a762c8b8248
| 0.553891 | 3.193699 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/RegFile_TB.vhd
| 2 | 3,668 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:50:46 10/30/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/OZ-3/RegFile_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegFile
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY RegFile_TB IS
END RegFile_TB;
ARCHITECTURE behavior OF RegFile_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegFile
PORT(
clock : IN std_logic;
reset : IN std_logic;
write_e : IN std_logic;
data_in : IN std_logic_vector(31 downto 0);
r_addr1 : IN std_logic_vector(4 downto 0);
r_addr2 : IN std_logic_vector(4 downto 0);
r_addr3 : IN std_logic_vector(4 downto 0);
w_addr1 : IN std_logic_vector(4 downto 0);
data_out_1 : OUT std_logic_vector(31 downto 0);
data_out_2 : OUT std_logic_vector(31 downto 0);
data_out_3 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal write_e : std_logic := '0';
signal data_in : std_logic_vector(31 downto 0) := (others => '0');
signal r_addr1 : std_logic_vector(4 downto 0) := (others => '0');
signal r_addr2 : std_logic_vector(4 downto 0) := (others => '0');
signal r_addr3 : std_logic_vector(4 downto 0) := (others => '0');
signal w_addr1 : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal data_out_1 : std_logic_vector(31 downto 0);
signal data_out_2 : std_logic_vector(31 downto 0);
signal data_out_3 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegFile PORT MAP (
clock => clock,
reset => reset,
write_e => write_e,
data_in => data_in,
r_addr1 => r_addr1,
r_addr2 => r_addr2,
r_addr3 => r_addr3,
w_addr1 => w_addr1,
data_out_1 => data_out_1,
data_out_2 => data_out_2,
data_out_3 => data_out_3
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 20 ns;
w_addr1 <= b"00001";
data_in <= x"00000001";
write_e <= '1';
wait for 10 ns;
w_addr1 <= b"00010";
data_in <= x"00000002";
write_e <= '1';
wait for 10 ns;
w_addr1 <= b"00011";
data_in <= x"00000003";
write_e <= '1';
wait for 10 ns;
r_addr1 <= b"00001";
r_addr2 <= b"00010";
r_addr3 <= b"00011";
wait;
end process;
END;
|
mit
|
8d85908246f4b0ba97f91c5ce3cb930a
| 0.550436 | 3.365138 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/gpmc_wishbone_wrapper_aad.vhd
| 1 | 10,178 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:26 12/01/2015
-- Design Name:
-- Module Name: gpmc_wishbone_wrapper_aad - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Recommended GPMC settings:
-- gpmc,sync-read;
-- gpmc,sync-write;
-- gpmc,burst-length = <16>;
-- gpmc,mux-add-data = <1>;
-- gpmc,sync-clk-ps = <20000>;
-- gpmc,clk-activation-ns = <0>;
-- gpmc,cs-on-ns = <0>;
-- gpmc,cs-rd-off-ns = <160>;
-- gpmc,cs-wr-off-ns = <80>;
-- gpmc,adv-aadmux-on-ns = <0>;
-- gpmc,adv-aadmux-rd-off-ns = <20>;
-- gpmc,adv-aadmux-wr-off-ns = <20>;
-- gpmc,adv-on-ns = <40>;
-- gpmc,adv-rd-off-ns = <60>;
-- gpmc,adv-wr-off-ns = <60>;
-- gpmc,we-on-ns = <60>;
-- gpmc,we-off-ns = <80>;
-- gpmc,oe-aadmux-on-ns = <0>;
-- gpmc,oe-aadmux-off-ns = <20>;
-- gpmc,oe-on-ns = <60>;
-- gpmc,oe-off-ns = <160>;
-- gpmc,page-burst-access-ns = <20>;
-- gpmc,access-ns = <140>;
-- gpmc,rd-cycle-ns = <180>;
-- gpmc,wr-cycle-ns = <100>;
-- gpmc,wr-access-ns = <70>;
-- gpmc,wr-data-mux-bus-ns = <60>;
-- gpmc,bus-turnaround-ns = <40>;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.logi_utils_pack.all;
-- ----------------------------------------------------------------------------
entity gpmc_wishbone_wrapper_aad is
generic(
sync : boolean := true;
burst : boolean := false;
addr_width : natural := 28
);
port (
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone master interface signals
wbm_address : out std_logic_vector(addr_width-1 downto 0);
wbm_readdata : in std_logic_vector(15 downto 0);
wbm_writedata : out std_logic_vector(15 downto 0);
wbm_strobe : out std_logic;
wbm_write : out std_logic;
wbm_ack : in std_logic;
wbm_cycle : out std_logic
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of gpmc_wishbone_wrapper_aad is
-- New types
type buffer_t is array (0 to 15) of std_logic_vector(15 downto 0);
-- IOBUF signals for gpmc_ad port
signal gpmc_ad_iob_hiz : std_logic;
signal gpmc_ad_iob_in : std_logic_vector(15 downto 0);
-- IOB signals (input signals registered at falling edge of GPMC clock)
signal iob_ad_in : std_logic_vector(15 downto 0) := (others => '1');
signal iob_ad_out : std_logic_vector(15 downto 0) := (others => '1');
signal iob_csn : std_logic := '1';
signal iob_advn : std_logic := '1';
signal iob_oen : std_logic := '1';
signal iob_wen : std_logic := '1';
-- Use the IOB flip-flop for the GPMC signals
attribute IOB : string;
attribute IOB of iob_ad_in : signal is "FORCE";
attribute IOB of iob_ad_out : signal is "FORCE";
attribute IOB of iob_csn : signal is "FORCE";
attribute IOB of iob_advn : signal is "FORCE";
attribute IOB of iob_oen : signal is "FORCE";
attribute IOB of iob_wen : signal is "FORCE";
-- Auxiliary signals to indicate a read or write phase
signal iob_read : std_logic;
signal iob_write : std_logic;
-- Base address
signal reg_addr : std_logic_vector(addr_width-1 downto 0) := (others => '0');
-- The read and write signals are crossed to the GLS clock domain and will
-- indicate the beginning of a new transaction on the WBM side
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal gls_read : std_logic := '0';
signal gls_write : std_logic := '0';
-- Use a write buffer to avoid coherency issues in the CDC. Each data in
-- the burst is stored in a different location in the buffer, so when the
-- data is read by the WBM interface its value is stable.
signal write_buf : buffer_t;
-- These counters are used to index the write buffer during a write
-- operation and to generate the WBM addresses during a burst. The counter
-- value is CDC using a Gray encoder to prevent bus coherency issues.
signal gpmc_counter : std_logic_vector(3 downto 0) := (others => '0');
signal gpmc_counter_1 : std_logic_vector(3 downto 0);
signal gpmc_gray_counter : std_logic_vector(3 downto 0) := (others => '0');
signal gls_counter : std_logic_vector(3 downto 0) := (others => '0');
signal gls_gray_counter : std_logic_vector(3 downto 0) := (others => '0');
begin
-- IOBUF cells
gpmc_ad_iob_hiz <= iob_csn or iob_oen or not iob_advn;
iob_gpmc_ad : for i in 0 to 15 generate
begin
iob_dq_iob: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (
O => gpmc_ad_iob_in(i),
IO => gpmc_ad(i),
I => iob_ad_out(i),
T => gpmc_ad_iob_hiz
);
end generate;
-- Input signals are registered in the falling edge of the GPMC clock.
-- Since they are generated by the GPMC master in the rising edge, their
-- value should be stable
gpmc_iob_input: process
begin
wait until falling_edge(gpmc_clk);
iob_ad_in <= gpmc_ad_iob_in;
iob_csn <= gpmc_csn;
iob_advn <= gpmc_advn;
iob_wen <= gpmc_wen;
iob_oen <= gpmc_oen;
end process;
-- GPMC output is registered in the falling edge (empirically, this
-- results in more stable signals at the master end)
gpmc_iob_output: process
begin
wait until falling_edge(gpmc_clk);
if (gls_reset = '1') then
iob_ad_out <= (others => '1');
else
iob_ad_out <= wbm_readdata;
end if;
end process;
-- Auxiliary signals to indicate a read or write access
iob_write <= (not iob_csn) and iob_advn and (not iob_wen);
iob_read <= (not iob_csn) and iob_advn and (not iob_oen);
-- Same signals registered in the rising edge of the GPMC clock
process
begin
wait until rising_edge(gpmc_clk);
if (gls_reset = '1') then
reg_write <= '0';
reg_read <= '0';
else
reg_write <= iob_write;
reg_read <= iob_read;
end if;
end process;
-- Demultiplex the GPMC address
demux_addr: process
begin
wait until rising_edge(gpmc_clk);
if (gls_reset = '1') then
reg_addr <= (others => '0');
else
if ((iob_csn = '0') and (iob_advn = '0')) then
if (iob_oen = '0') then
reg_addr(addr_width-1 downto 16) <= iob_ad_in(addr_width-17 downto 0);
else
reg_addr(15 downto 0) <= iob_ad_in;
end if;
end if;
end if;
end process;
-- Process to increment the burst counter
gen_burst: if burst = true generate
process
begin
wait until rising_edge(gpmc_clk);
if (gls_reset = '1') then
gpmc_counter <= (others => '0');
else
if (iob_csn = '0') then
if (iob_advn = '1') then
if ((iob_oen and iob_wen) = '0') then
gpmc_counter <= gpmc_counter + '1';
end if;
end if;
else
gpmc_counter <= (others => '0');
end if;
end if;
end process;
-- The GPMC counter is used to index the write buffer input, so we
-- cannot use the same value to index the output at the WBM interface.
-- The output index should be one less than the input index in order
-- to guarantee a stable value in the buffer while reading it.
gpmc_counter_1 <= gpmc_counter - 1;
end generate;
gen_no_burst: if burst = false generate
-- In this case, both indexes (input and output) are zero
gpmc_counter <= (others => '0');
gpmc_counter_1 <= (others => '0');
end generate;
-- Store the incoming data into the write buffer. The position in the
-- buffer is given by the GPMC counter.
process
begin
wait until rising_edge(gpmc_clk);
if (gls_reset = '1') then
else
if ((iob_csn = '0') and (iob_advn = '1') and (iob_wen = '0')) then
write_buf(conv_integer(gpmc_counter)) <= iob_ad_in;
end if;
end if;
end process;
-- Control signals CDC (read/write)
read_sync: ff_sync
port map(
clk => gls_clk,
reset => gls_reset,
din(0) => reg_read,
dout(0) => gls_read
);
write_sync: ff_sync
port map(
clk => gls_clk,
reset => gls_reset,
din(0) => reg_write,
dout(0) => gls_write
);
-- Convert the counter to gray
bin2gray: bin2gray4
port map (
bin => gpmc_counter_1,
gray => gpmc_gray_counter
);
-- Counter CDC
counter_sync: ff_sync
generic map(
WIDTH => 4
)
port map(
clk => gls_clk,
reset => gls_reset,
din => gpmc_gray_counter,
dout => gls_gray_counter
);
-- Convert back to binary
gray2bin: gray2bin4
port map (
gray => gls_gray_counter,
bin => gls_counter
);
-- ------------------------------------------------------------------------
-- Whisbone Master Interface
--
-- Following the Wishbone rules and recommendations, the WBM signals are
-- all registered and respond to a synchronous reset.
-- ------------------------------------------------------------------------
-- WBM address
process
begin
wait until rising_edge(gls_clk);
if (gls_reset = '1') then
wbm_address <= (others => '0');
else
if ((gls_write or gls_read) = '1') then
wbm_address <= reg_addr + gls_counter;
end if;
end if;
end process;
-- WBM write process
process
begin
wait until rising_edge(gls_clk);
if (gls_reset = '1') then
wbm_writedata <= (others => '0');
else
if (gls_write = '1') then
wbm_writedata <= write_buf(conv_integer(gls_counter));
end if;
end if;
end process;
-- Control signals
process
begin
wait until rising_edge(gls_clk);
if (gls_reset = '1') then
wbm_cycle <= '0';
wbm_strobe <= '0';
wbm_write <= '0';
else
wbm_cycle <= gls_read or gls_write;
wbm_strobe <= gls_read or gls_write;
wbm_write <= gls_write;
end if;
end process;
end architecture RTL;
|
lgpl-3.0
|
7a6ca05942c26c71492c453144a3bc2b
| 0.601788 | 3.032777 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb.vhd
| 1 | 6,128 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth_inst:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 40
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-3.0
|
8abf841bcc2a7f3b2e3fbe9f37c5d227
| 0.63267 | 4.050231 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/pid_controller.vhd
| 2 | 6,003 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 16:24:43 05/12/2013
-- Design Name:
-- Module Name: pid_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.utils_pack.all ;
-- gain are fixed point values 8 bit integer part, 8 bit fractionnal part
entity pid_controller is
generic(CLK_PERIOD_NS : positive := 10;
CTRL_PERIOD_NS : positive := 1000000;
CMD_WIDTH : positive := 8;
CMD_OFFSET : positive := 127);
port(clk, resetn : in std_logic ;
en, reset : in std_logic ;
speed_input : in signed(15 downto 0);
P, I, D : in signed(15 downto 0);
ENC_A : in std_logic ;
ENC_B : in std_logic ;
encoder_count : out signed(15 downto 0);
command : out std_logic_vector(CMD_WIDTH-1 downto 0)
);
end pid_controller;
architecture Behavioral of pid_controller is
constant clk_tick_per_period : integer := CTRL_PERIOD_NS/CLK_PERIOD_NS;
constant command_max : integer := (2**command'length)-1 ;
signal clk_tick_counter : std_logic_vector(nbit(clk_tick_per_period) downto 0);
signal speed_input_latched, encoder_value, encoder_value_latched : signed(15 downto 0) ;
signal error, error_grad, error_sum, last_error : signed(15 downto 0) ;
signal error_sum_enlarged : signed(31 downto 0) ;
signal std_encoder_value : std_logic_vector(15 downto 0) ;
signal command_temp, command_offset : signed(31 downto 0);
signal P_contrib, I_contrib, D_contrib : signed(31 downto 0);
signal reset_encoder : std_logic ;
signal ENC_A_OLD, ENC_A_RE : std_logic ;
signal error_32, error_sum_32 : signed(31 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
ENC_A_OLD <= '0';
elsif clk'event and clk = '1' then
ENC_A_OLD <= ENC_A ;
end if ;
end process ;
ENC_A_RE <= (ENC_A and (NOT ENC_A_OLD)) and en;
encoder_chan0 : up_down_counter
generic map(NBIT => 16)
port map( clk => clk,
resetn => resetn,
sraz => reset_encoder,
en => ENC_A_RE , -- must detect rising edge
load => '0',
up_downn => ENC_B,
E => (others => '0'),
Q => std_encoder_value
);
encoder_value <= signed(std_encoder_value) ;
process(clk, resetn)
begin
if resetn = '0' then
clk_tick_counter <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = clk_tick_per_period then
clk_tick_counter <= (others => '0');
else
clk_tick_counter <= clk_tick_counter + 1 ;
end if ;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
encoder_value_latched <= (others => '0');
speed_input_latched <= (others => '0');
last_error <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = clk_tick_per_period then
encoder_value_latched <= encoder_value ;
speed_input_latched <= speed_input ;
last_error <= error ;
end if ;
end if ;
end process ;
reset_encoder <= '1' when clk_tick_counter = clk_tick_per_period else
'0' ;
error <= speed_input_latched - encoder_value_latched ;
-- derivative term
error_grad <= error - last_error ;
error_32 <= RESIZE(error, 32) ;
error_sum_32 <= RESIZE(error_sum, 32) ;
error_sum_enlarged <= error_sum_32 + error_32 ;
integral_term_latch:process(clk, resetn)
begin
if resetn = '0' then
error_sum <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = 0 then
if error_sum_enlarged > (2**15 - 1) then -- handling saturation
error_sum <= X"7FFF" ;
elsif error_sum_enlarged < (-(2**15)) then
error_sum <= X"8000" ;
else
error_sum <= error_sum + error ;
end if ;
end if ;
end if ;
end process ;
contrib_latch :process(clk, resetn)
begin
if resetn = '0' then
P_contrib <= (others => '0');
I_contrib <= (others => '0');
D_contrib <= (others => '0');
elsif clk'event and clk = '1' then
P_contrib <= P*error ;
I_contrib <= I*error_sum ;
D_contrib <= D*error_grad ;
end if ;
end process ;
command_temp <= P_contrib + I_contrib + D_contrib ; -- need adder tree
command_offset <= command_temp + to_signed((CMD_OFFSET*(2**16)), 32) ;
command <= (others => '1') when command_offset(31 downto 16) > command_max else
(others => '0') when command_offset(31 downto 16) < 0 else
std_logic_vector(command_offset((15+CMD_WIDTH) downto 16));
end Behavioral;
|
lgpl-3.0
|
07f92660b1d7c9f6a632e45c2e433f44
| 0.62019 | 3.355506 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/ff_sync.vhd
| 1 | 2,019 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:44:13 12/01/2015
-- Design Name:
-- Module Name: ff_sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ff_sync is
generic(
STAGES : integer := 1;
WIDTH : integer := 1;
RESET_VAL : std_logic := '0'
);
port(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(WIDTH-1 downto 0);
dout : out std_logic_vector(WIDTH-1 downto 0)
);
end ff_sync;
architecture Behavioral of ff_sync is
subtype dsync_t is std_logic_vector(WIDTH-1 downto 0);
type dsync_array_t is array (0 to STAGES) of dsync_t;
-- Chain of flip-flops
signal dsync : dsync_array_t := (others => (others => RESET_VAL));
-- Do not use shift registers as synchronizers
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of dsync : signal is "NO";
attribute ASYNC_REG : string;
attribute ASYNC_REG of dsync : signal is "TRUE";
begin
dout <= dsync(STAGES);
stage_0 : process
begin
wait until rising_edge(clk);
if (reset = '1') then
dsync(0) <= (others => RESET_VAL);
else
dsync(0) <= din;
end if;
end process;
synchronizer : for i in 1 to STAGES generate
begin
process
begin
wait until rising_edge(clk);
if (reset = '1') then
dsync(i) <= (others => RESET_VAL);
else
dsync(i) <= dsync(i-1);
end if;
end process;
end generate;
end Behavioral;
|
lgpl-3.0
|
8f804cafa52946d3c8168ea459debc1f
| 0.609708 | 3.342715 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altddio_out/_primary.vhd
| 1 | 1,589 |
library verilog;
use verilog.vl_types.all;
entity altddio_out is
generic(
width : integer := 1;
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable: string := "UNUSED";
intended_device_family: string := "Stratix";
invert_output : string := "OFF";
lpm_type : string := "altddio_out";
lpm_hint : string := "UNUSED"
);
port(
datain_h : in vl_logic_vector;
datain_l : in vl_logic_vector;
outclock : in vl_logic;
outclocken : in vl_logic;
aset : in vl_logic;
aclr : in vl_logic;
sset : in vl_logic;
sclr : in vl_logic;
oe : in vl_logic;
dataout : out vl_logic_vector;
oe_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_high : constant is 1;
attribute mti_svvh_generic_type of oe_reg : constant is 1;
attribute mti_svvh_generic_type of extend_oe_disable : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of invert_output : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end altddio_out;
|
bsd-2-clause
|
d2c23ef84e8870a103e2f063535be1cb
| 0.548773 | 3.792363 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altlvds_tx/_primary.vhd
| 1 | 7,787 |
library verilog;
use verilog.vl_types.all;
entity altlvds_tx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_input: string := "ON";
multi_clock : string := "OFF";
inclock_period : integer := 10000;
outclock_divide_by: vl_notype;
inclock_boost : vl_notype;
center_align_msb: string := "OFF";
intended_device_family: string := "Stratix";
output_data_rate: integer := 0;
inclock_data_alignment: string := "EDGE_ALIGNED";
outclock_alignment: string := "EDGE_ALIGNED";
common_rx_tx_pll: string := "ON";
outclock_resource: string := "AUTO";
use_external_pll: string := "OFF";
implement_in_les: string := "OFF";
preemphasis_setting: integer := 0;
vod_setting : integer := 0;
differential_drive: integer := 0;
outclock_multiply_by: integer := 1;
coreclock_divide_by: integer := 2;
outclock_duty_cycle: integer := 50;
inclock_phase_shift: integer := 0;
outclock_phase_shift: integer := 0;
use_no_phase_shift: string := "ON";
pll_self_reset_on_loss_lock: string := "OFF";
refclk_frequency: string := "UNUSED";
enable_clock_pin_mode: string := "UNUSED";
data_rate : string := "UNUSED";
lpm_type : string := "altlvds_tx";
lpm_hint : string := "UNUSED";
clk_src_is_pll : string := "off";
STRATIX_TX_STYLE: vl_notype;
STRATIXII_TX_STYLE: vl_notype;
CYCLONE_TX_STYLE: vl_notype;
CYCLONEII_TX_STYLE: vl_notype;
STRATIXIII_TX_STYLE: vl_notype;
CYCLONEIII_TX_STYLE: vl_notype;
MAXV_TX_STYLE : vl_notype;
FAMILY_HAS_FLEXIBLE_LVDS: vl_notype;
FAMILY_HAS_STRATIX_STYLE_PLL: vl_notype;
FAMILY_HAS_STRATIXII_STYLE_PLL: vl_notype;
FAMILY_HAS_STRATIXIII_STYLE_PLL: vl_notype;
INT_CLOCK_BOOST : vl_notype;
PLL_M_VALUE : vl_notype;
PLL_D_VALUE : vl_notype;
STRATIX_INCLOCK_BOOST: vl_notype;
PHASE_INCLOCK : vl_notype;
STXII_PHASE_INCLOCK: vl_notype;
PHASE_OUTCLOCK : vl_notype;
STX_PHASE_OUTCLOCK: vl_notype;
STXII_PHASE_OUTCLOCK: vl_notype;
STXII_LE_PHASE_INCLOCK: vl_notype;
STXII_LE_PHASE_OUTCLOCK: vl_notype;
STXIII_LE_PHASE_INCLOCK: vl_notype;
STXIII_LE_PHASE_OUTCLOCK: vl_notype;
REGISTER_WIDTH : vl_notype;
FAST_CLK_ENA_PHASE_SHIFT: vl_notype;
CLOCK_PERIOD : vl_notype;
USE_NEW_CORECLK_CKT: vl_notype
);
port(
tx_in : in vl_logic_vector;
tx_inclock : in vl_logic;
tx_syncclock : in vl_logic;
tx_enable : in vl_logic;
sync_inclock : in vl_logic;
tx_pll_enable : in vl_logic;
pll_areset : in vl_logic;
tx_data_reset : in vl_logic;
tx_out : out vl_logic_vector;
tx_outclock : out vl_logic;
tx_coreclock : out vl_logic;
tx_locked : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of registered_input : constant is 1;
attribute mti_svvh_generic_type of multi_clock : constant is 1;
attribute mti_svvh_generic_type of inclock_period : constant is 1;
attribute mti_svvh_generic_type of outclock_divide_by : constant is 3;
attribute mti_svvh_generic_type of inclock_boost : constant is 3;
attribute mti_svvh_generic_type of center_align_msb : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of output_data_rate : constant is 1;
attribute mti_svvh_generic_type of inclock_data_alignment : constant is 1;
attribute mti_svvh_generic_type of outclock_alignment : constant is 1;
attribute mti_svvh_generic_type of common_rx_tx_pll : constant is 1;
attribute mti_svvh_generic_type of outclock_resource : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of implement_in_les : constant is 1;
attribute mti_svvh_generic_type of preemphasis_setting : constant is 1;
attribute mti_svvh_generic_type of vod_setting : constant is 1;
attribute mti_svvh_generic_type of differential_drive : constant is 1;
attribute mti_svvh_generic_type of outclock_multiply_by : constant is 1;
attribute mti_svvh_generic_type of coreclock_divide_by : constant is 1;
attribute mti_svvh_generic_type of outclock_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of inclock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of outclock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of use_no_phase_shift : constant is 1;
attribute mti_svvh_generic_type of pll_self_reset_on_loss_lock : constant is 1;
attribute mti_svvh_generic_type of refclk_frequency : constant is 1;
attribute mti_svvh_generic_type of enable_clock_pin_mode : constant is 1;
attribute mti_svvh_generic_type of data_rate : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of clk_src_is_pll : constant is 1;
attribute mti_svvh_generic_type of STRATIX_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of STRATIXII_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of CYCLONE_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of CYCLONEII_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of STRATIXIII_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of CYCLONEIII_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of MAXV_TX_STYLE : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_FLEXIBLE_LVDS : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIX_STYLE_PLL : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXII_STYLE_PLL : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXIII_STYLE_PLL : constant is 3;
attribute mti_svvh_generic_type of INT_CLOCK_BOOST : constant is 3;
attribute mti_svvh_generic_type of PLL_M_VALUE : constant is 3;
attribute mti_svvh_generic_type of PLL_D_VALUE : constant is 3;
attribute mti_svvh_generic_type of STRATIX_INCLOCK_BOOST : constant is 3;
attribute mti_svvh_generic_type of PHASE_INCLOCK : constant is 3;
attribute mti_svvh_generic_type of STXII_PHASE_INCLOCK : constant is 3;
attribute mti_svvh_generic_type of PHASE_OUTCLOCK : constant is 3;
attribute mti_svvh_generic_type of STX_PHASE_OUTCLOCK : constant is 3;
attribute mti_svvh_generic_type of STXII_PHASE_OUTCLOCK : constant is 3;
attribute mti_svvh_generic_type of STXII_LE_PHASE_INCLOCK : constant is 3;
attribute mti_svvh_generic_type of STXII_LE_PHASE_OUTCLOCK : constant is 3;
attribute mti_svvh_generic_type of STXIII_LE_PHASE_INCLOCK : constant is 3;
attribute mti_svvh_generic_type of STXIII_LE_PHASE_OUTCLOCK : constant is 3;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of FAST_CLK_ENA_PHASE_SHIFT : constant is 3;
attribute mti_svvh_generic_type of CLOCK_PERIOD : constant is 3;
attribute mti_svvh_generic_type of USE_NEW_CORECLK_CKT : constant is 3;
end altlvds_tx;
|
bsd-2-clause
|
3d32e588d1a49c2e8fc1be0985f7d6c7
| 0.664826 | 3.611781 | false | false | false | false |
gbraad/minimig-de1
|
rtl/tg68/TG68.vhd
| 3 | 7,888 |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- --
-- Copyright (c) 2007-2008 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.02 2008/01/23
-- bugfix Timing
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68 is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
addr : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
drive_data : out std_logic; --enable for data_out driver
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68;
ARCHITECTURE logic OF TG68 IS
COMPONENT TG68_fast
PORT (
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0);
test_IPL : in std_logic;
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
decodeOPC : buffer std_logic;
-- decodeOPC : out std_logic;
wr : out std_logic;
UDS, LDS : out std_logic;
enaRDreg : in std_logic;
enaWRreg : in std_logic
);
END COMPONENT;
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
-- SIGNAL n_clk : std_logic;
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
BEGIN
-- n_clk <= NOT clk;
TG68_fast_inst: TG68_fast
PORT MAP (
-- originally n_clk was used
-- clk => n_clk, -- : in std_logic;
clk => clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);
-- originally cpuIPL was used
-- IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);
IPL => IPL, -- : in std_logic_vector(2 downto 0);
test_IPL => '0', -- : in std_logic;
address => addr, -- : out std_logic_vector(31 downto 0);
data_write => data_out, -- : out std_logic_vector(15 downto 0);
state_out => state, -- : out std_logic_vector(1 downto 0);
decodeOPC => decode, -- : buffer std_logic;
wr => wr, -- : out std_logic;
UDS => uds_in, -- : out std_logic;
LDS => lds_in, -- : out std_logic;
enaRDreg => enaWRreg,
enaWRreg => enaRDreg
);
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN -- TODO new version is not edge sensitive (try to remove this)
IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= as_s AND as_e;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF reset='0' THEN
S_state <= "11";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN -- enaWRreg added
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
IF state/="01" OR decode='1' THEN
CASE S_state IS
WHEN "00" => as_s <= '0';
rw_s <= wr;
IF wr='1' THEN
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
S_state <= "01";
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
rw_s <= wr;
IF waitm='0' THEN
S_state <= "11";
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
cpuIPL <= "111";
drive_data <= '0';
ELSIF rising_edge(clk) THEN
-- originally it was falling_edge sensitive
-- ELSIF falling_edge(clk) THEN
IF clkena_in='1' AND enaRDreg='1' THEN -- enaRDreg added
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
drive_data <= '0';
CASE S_state IS
WHEN "00" => null;
WHEN "01" => drive_data <= NOT wr;
WHEN "10" => as_e <= '0';
uds_e <= uds_in;
lds_e <= lds_in;
cpuIPL <= IPL;
drive_data <= NOT wr;
IF state="01" THEN
clkena_e <= '1';
waitm <= '0';
ELSE
clkena_e <= NOT dtack;
waitm <= dtack;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END PROCESS;
END;
|
gpl-3.0
|
e1e7d81e93a37b1bd1a152bf32a98381
| 0.469194 | 3.438535 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng.vhd
| 1 | 4,004 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
2087780e3ab54bc3142c37fba811255d
| 0.641858 | 4.241525 | false | false | false | false |
gw0/rs-skip-gram-in-myhdl
|
ex-target/pck_myhdl_10.vhd
| 1 | 4,358 |
-- File: ./ex-target/pck_myhdl_10.vhd
-- Generated by MyHDL 1.0dev
-- Date: Tue Oct 6 16:32:07 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_10 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed;
end pck_myhdl_10;
package body pck_myhdl_10 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
function tern_op(cond: boolean; if_true: std_logic; if_false: std_logic) return std_logic is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: unsigned; if_false: unsigned) return unsigned is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
function tern_op(cond: boolean; if_true: signed; if_false: signed) return signed is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function tern_op;
end pck_myhdl_10;
|
agpl-3.0
|
b09b6b748398d9dc8fc58f2852388f3b
| 0.60257 | 3.976277 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_2/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng.vhd
| 1 | 4,004 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
38ea720d947221575f174c3fac475db7
| 0.641858 | 4.241525 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altclklock/_primary.vhd
| 1 | 3,662 |
library verilog;
use verilog.vl_types.all;
entity altclklock is
generic(
inclock_period : integer := 10000;
inclock_settings: string := "UNUSED";
valid_lock_cycles: integer := 5;
invalid_lock_cycles: integer := 5;
valid_lock_multiplier: integer := 5;
invalid_lock_multiplier: integer := 5;
operation_mode : string := "NORMAL";
clock0_boost : integer := 1;
clock0_divide : integer := 1;
clock0_settings : string := "UNUSED";
clock0_time_delay: string := "0";
clock1_boost : integer := 1;
clock1_divide : integer := 1;
clock1_settings : string := "UNUSED";
clock1_time_delay: string := "0";
clock2_boost : integer := 1;
clock2_divide : integer := 1;
clock2_settings : string := "UNUSED";
clock2_time_delay: string := "0";
clock_ext_boost : integer := 1;
clock_ext_divide: integer := 1;
clock_ext_settings: string := "UNUSED";
clock_ext_time_delay: string := "0";
outclock_phase_shift: integer := 0;
intended_device_family: string := "Stratix";
lpm_type : string := "altclklock";
lpm_hint : string := "UNUSED"
);
port(
inclock : in vl_logic;
inclocken : in vl_logic;
fbin : in vl_logic;
clock0 : out vl_logic;
clock1 : out vl_logic;
clock2 : out vl_logic;
clock_ext : out vl_logic;
locked : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of inclock_period : constant is 1;
attribute mti_svvh_generic_type of inclock_settings : constant is 1;
attribute mti_svvh_generic_type of valid_lock_cycles : constant is 1;
attribute mti_svvh_generic_type of invalid_lock_cycles : constant is 1;
attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1;
attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of clock0_boost : constant is 1;
attribute mti_svvh_generic_type of clock0_divide : constant is 1;
attribute mti_svvh_generic_type of clock0_settings : constant is 1;
attribute mti_svvh_generic_type of clock0_time_delay : constant is 1;
attribute mti_svvh_generic_type of clock1_boost : constant is 1;
attribute mti_svvh_generic_type of clock1_divide : constant is 1;
attribute mti_svvh_generic_type of clock1_settings : constant is 1;
attribute mti_svvh_generic_type of clock1_time_delay : constant is 1;
attribute mti_svvh_generic_type of clock2_boost : constant is 1;
attribute mti_svvh_generic_type of clock2_divide : constant is 1;
attribute mti_svvh_generic_type of clock2_settings : constant is 1;
attribute mti_svvh_generic_type of clock2_time_delay : constant is 1;
attribute mti_svvh_generic_type of clock_ext_boost : constant is 1;
attribute mti_svvh_generic_type of clock_ext_divide : constant is 1;
attribute mti_svvh_generic_type of clock_ext_settings : constant is 1;
attribute mti_svvh_generic_type of clock_ext_time_delay : constant is 1;
attribute mti_svvh_generic_type of outclock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
end altclklock;
|
bsd-2-clause
|
7ec73438a8ca344113055247d236a031
| 0.638449 | 3.744376 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth.vhd
| 1 | 10,215 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 1,
C_DOUT_WIDTH => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-3.0
|
379f239c2eae33ca1e8dbaca21238d56
| 0.474107 | 4.087635 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_2/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif.vhd
| 1 | 5,696 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
gpl-3.0
|
7c9fb34356831c6fd95efad5f119e260
| 0.582338 | 3.99439 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/control/pwm.vhd
| 2 | 3,650 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:57:26 04/20/2013
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work ;
use work.control_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm is
generic(NB_CHANNEL : positive := 3);
port(
clk, resetn : in std_logic ;
divider : in std_logic_vector(15 downto 0);
period : in std_logic_vector(15 downto 0);
pulse_width : in slv16_array(0 to NB_CHANNEL-1) ;
pwm : out std_logic_vector(0 to NB_CHANNEL-1)
);
end pwm;
architecture Behavioral of pwm is
signal end_div : std_logic ;
signal divider_counter, period_counter: std_logic_vector(15 downto 0);
signal period_q : std_logic_vector(15 downto 0);
signal pulse_width_q : slv16_array(0 to NB_CHANNEL-1);
signal en_period_count : std_logic ;
signal pwm_d : std_logic_vector(0 to NB_CHANNEL-1) ;
begin
process(clk, resetn)
begin
if resetn = '0' then
divider_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if divider_counter = 0 then
divider_counter <= divider ;
else
divider_counter <= divider_counter - 1 ;
end if ;
end if ;
end process ;
en_period_count <= '1' when divider_counter = 0 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
period_q <= (others => '0');
pulse_width_q <= (others => (others => '0'));
elsif clk'event and clk = '1' then
if period_counter = 0 then
period_q <= period ;
pulse_width_q <= pulse_width ;
end if ;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
period_counter <= (others => '0');
elsif clk'event and clk = '1' then
if en_period_count = '1' then
if period_counter = period_q then
period_counter <= (others => '0');
else
period_counter <= period_counter + 1 ;
end if ;
end if ;
end if ;
end process ;
gen_outs : for i in 0 to NB_CHANNEL-1 generate
pwm_d(i) <= '1' when period_counter < pulse_width_q(i) else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
pwm(i) <= '0';
elsif clk'event and clk = '1' then
pwm(i) <= pwm_d(i) ;
end if ;
end process ;
end generate ;
end Behavioral;
|
lgpl-3.0
|
a76efd48e767e90701d3b891b2df5a21
| 0.620822 | 3.449905 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_gpio.vhd
| 2 | 3,321 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_gpio is
generic(
wb_size : natural := 16
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
gpio: inout std_logic_vector(15 downto 0)
);
end wishbone_gpio;
architecture Behavioral of wishbone_gpio is
signal dir : std_logic_vector(15 downto 0) ;
signal input : std_logic_vector(15 downto 0) ;
signal output : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
dir <= (others => '0');
output <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1') and wbs_address(0) = '1' then
dir <= wbs_writedata;
write_ack <= '1';
elsif ((wbs_strobe and wbs_write and wbs_cycle) = '1') and wbs_address(0) = '0' then
output <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
gen_tristate : for i in gpio'range generate
gpio(i) <= output(i) when dir(i) = '1' else
'Z' ;
end generate ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
input <= gpio ; -- latching inputs
if wbs_address(0) = '0' then
wbs_readdata <= input ;
else
wbs_readdata <= dir ;
end if ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) and wbs_address(0)='0' then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
lgpl-3.0
|
abb9a25d0610d0870f88a10380837b0b
| 0.607648 | 3.657489 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/stratixiii_lvds_rx/_primary.vhd
| 1 | 3,826 |
library verilog;
use verilog.vl_types.all;
entity stratixiii_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
enable_dpa_mode : string := "OFF";
data_align_rollover: vl_notype;
lose_lock_on_one_change: string := "OFF";
reset_fifo_at_first_lock: string := "ON";
x_on_bitslip : string := "ON";
rx_align_data_reg: string := "RISING_EDGE";
enable_soft_cdr_mode: string := "OFF";
sim_dpa_output_clock_phase_shift: integer := 0;
sim_dpa_is_negative_ppm_drift: string := "OFF";
sim_dpa_net_ppm_variation: integer := 0;
enable_dpa_align_to_rising_edge_only: string := "OFF";
enable_dpa_initial_phase_selection: string := "OFF";
dpa_initial_phase_value: integer := 0;
registered_output: string := "ON";
use_external_pll: string := "OFF";
use_dpa_calibration: integer := 0;
enable_clock_pin_mode: string := "UNUSED";
ARRIAII_RX_STYLE: integer := 0;
STRATIXV_RX_STYLE: integer := 0;
REGISTER_WIDTH : vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_reset : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_slowclk : in vl_logic;
rx_enable : in vl_logic;
rx_dpll_reset : in vl_logic_vector;
rx_dpll_hold : in vl_logic_vector;
rx_dpll_enable : in vl_logic_vector;
rx_fifo_reset : in vl_logic_vector;
rx_channel_data_align: in vl_logic_vector;
rx_cda_reset : in vl_logic_vector;
rx_out : out vl_logic_vector;
rx_dpa_locked : out vl_logic_vector;
rx_cda_max : out vl_logic_vector;
rx_divfwdclk : out vl_logic_vector;
rx_locked : in vl_logic;
rx_dpa_lock_reset: in vl_logic_vector;
rx_dpaclock : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1;
attribute mti_svvh_generic_type of data_align_rollover : constant is 3;
attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1;
attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1;
attribute mti_svvh_generic_type of x_on_bitslip : constant is 1;
attribute mti_svvh_generic_type of rx_align_data_reg : constant is 1;
attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_output_clock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1;
attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of use_dpa_calibration : constant is 1;
attribute mti_svvh_generic_type of enable_clock_pin_mode : constant is 1;
attribute mti_svvh_generic_type of ARRIAII_RX_STYLE : constant is 1;
attribute mti_svvh_generic_type of STRATIXV_RX_STYLE : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
end stratixiii_lvds_rx;
|
bsd-2-clause
|
dc61b458b5ff77499d86371b6d9015b5
| 0.634867 | 3.462443 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/primitive/dpram_NxN.vhd
| 2 | 949 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end dpram_NxN;
architecture behavioral of dpram_NxN is
type ram_type is array (0 to (SIZE - 1)) of std_logic_vector(NBIT-1 downto 0 );
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
spo <= RAM(conv_integer(a));
dpo <= RAM(conv_integer(dpra));
end if;
end process;
end behavioral ;
|
lgpl-3.0
|
368b850b5fd75802adb3025d68ba551d
| 0.60274 | 2.956386 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/@m@f_stratix_pll/_primary.vhd
| 1 | 23,619 |
library verilog;
use verilog.vl_types.all;
entity MF_stratix_pll is
generic(
operation_mode : string := "normal";
qualify_conf_done: string := "off";
compensate_clock: string := "clk0";
pll_type : string := "auto";
scan_chain : string := "long";
clk0_multiply_by: integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift: integer := 0;
clk0_time_delay : integer := 0;
clk0_duty_cycle : integer := 50;
clk1_multiply_by: integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift: integer := 0;
clk1_time_delay : integer := 0;
clk1_duty_cycle : integer := 50;
clk2_multiply_by: integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift: integer := 0;
clk2_time_delay : integer := 0;
clk2_duty_cycle : integer := 50;
clk3_multiply_by: integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift: integer := 0;
clk3_time_delay : integer := 0;
clk3_duty_cycle : integer := 50;
clk4_multiply_by: integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift: integer := 0;
clk4_time_delay : integer := 0;
clk4_duty_cycle : integer := 50;
clk5_multiply_by: integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift: integer := 0;
clk5_time_delay : integer := 0;
clk5_duty_cycle : integer := 50;
extclk0_multiply_by: integer := 1;
extclk0_divide_by: integer := 1;
extclk0_phase_shift: integer := 0;
extclk0_time_delay: integer := 0;
extclk0_duty_cycle: integer := 50;
extclk1_multiply_by: integer := 1;
extclk1_divide_by: integer := 1;
extclk1_phase_shift: integer := 0;
extclk1_time_delay: integer := 0;
extclk1_duty_cycle: integer := 50;
extclk2_multiply_by: integer := 1;
extclk2_divide_by: integer := 1;
extclk2_phase_shift: integer := 0;
extclk2_time_delay: integer := 0;
extclk2_duty_cycle: integer := 50;
extclk3_multiply_by: integer := 1;
extclk3_divide_by: integer := 1;
extclk3_phase_shift: integer := 0;
extclk3_time_delay: integer := 0;
extclk3_duty_cycle: integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency: integer := 10000;
inclk1_input_frequency: integer := 10000;
gate_lock_signal: string := "no";
gate_lock_counter: integer := 1;
valid_lock_multiplier: integer := 5;
invalid_lock_multiplier: integer := 5;
switch_over_on_lossclk: string := "off";
switch_over_on_gated_lock: string := "off";
switch_over_counter: integer := 1;
enable_switch_over_counter: string := "off";
feedback_source : string := "extclk0";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
spread_frequency: integer := 0;
common_rx_tx : string := "off";
rx_outclock_resource: string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current: integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
pll_compensation_delay: integer := 0;
simulation_type : string := "timing";
down_spread : string := "0.0";
clk0_phase_shift_num: integer := 0;
clk1_phase_shift_num: integer := 0;
clk2_phase_shift_num: integer := 0;
family_name : string := "Stratix";
skip_vco : string := "off";
clk0_use_even_counter_mode: string := "off";
clk1_use_even_counter_mode: string := "off";
clk2_use_even_counter_mode: string := "off";
clk3_use_even_counter_mode: string := "off";
clk4_use_even_counter_mode: string := "off";
clk5_use_even_counter_mode: string := "off";
extclk0_use_even_counter_mode: string := "off";
extclk1_use_even_counter_mode: string := "off";
extclk2_use_even_counter_mode: string := "off";
extclk3_use_even_counter_mode: string := "off";
clk0_use_even_counter_value: string := "off";
clk1_use_even_counter_value: string := "off";
clk2_use_even_counter_value: string := "off";
clk3_use_even_counter_value: string := "off";
clk4_use_even_counter_value: string := "off";
clk5_use_even_counter_value: string := "off";
extclk0_use_even_counter_value: string := "off";
extclk1_use_even_counter_value: string := "off";
extclk2_use_even_counter_value: string := "off";
extclk3_use_even_counter_value: string := "off";
scan_chain_mif_file: string := "";
EGPP_SCAN_CHAIN : integer := 289;
GPP_SCAN_CHAIN : integer := 193;
TRST : integer := 5000;
TRSTCLK : integer := 5000
);
port(
inclk : in vl_logic_vector(1 downto 0);
fbin : in vl_logic;
ena : in vl_logic;
clkswitch : in vl_logic;
areset : in vl_logic;
pfdena : in vl_logic;
clkena : in vl_logic_vector(5 downto 0);
extclkena : in vl_logic_vector(3 downto 0);
scanclk : in vl_logic;
scanaclr : in vl_logic;
scandata : in vl_logic;
clk : out vl_logic_vector(5 downto 0);
extclk : out vl_logic_vector(3 downto 0);
clkbad : out vl_logic_vector(1 downto 0);
activeclock : out vl_logic;
locked : out vl_logic;
clkloss : out vl_logic;
scandataout : out vl_logic;
comparator : in vl_logic;
enable0 : out vl_logic;
enable1 : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of qualify_conf_done : constant is 1;
attribute mti_svvh_generic_type of compensate_clock : constant is 1;
attribute mti_svvh_generic_type of pll_type : constant is 1;
attribute mti_svvh_generic_type of scan_chain : constant is 1;
attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk0_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk0_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk1_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk1_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk2_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk2_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk3_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk3_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk4_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk4_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk5_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk5_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk0_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk0_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk0_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk0_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk0_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk1_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk1_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk1_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk1_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk1_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk2_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk2_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk2_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk2_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk2_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk3_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk3_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk3_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk3_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk3_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of primary_clock : constant is 1;
attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1;
attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1;
attribute mti_svvh_generic_type of gate_lock_signal : constant is 1;
attribute mti_svvh_generic_type of gate_lock_counter : constant is 1;
attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1;
attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1;
attribute mti_svvh_generic_type of switch_over_on_lossclk : constant is 1;
attribute mti_svvh_generic_type of switch_over_on_gated_lock : constant is 1;
attribute mti_svvh_generic_type of switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of feedback_source : constant is 1;
attribute mti_svvh_generic_type of bandwidth : constant is 1;
attribute mti_svvh_generic_type of bandwidth_type : constant is 1;
attribute mti_svvh_generic_type of spread_frequency : constant is 1;
attribute mti_svvh_generic_type of common_rx_tx : constant is 1;
attribute mti_svvh_generic_type of rx_outclock_resource : constant is 1;
attribute mti_svvh_generic_type of use_vco_bypass : constant is 1;
attribute mti_svvh_generic_type of use_dc_coupling : constant is 1;
attribute mti_svvh_generic_type of pfd_min : constant is 1;
attribute mti_svvh_generic_type of pfd_max : constant is 1;
attribute mti_svvh_generic_type of vco_min : constant is 1;
attribute mti_svvh_generic_type of vco_max : constant is 1;
attribute mti_svvh_generic_type of vco_center : constant is 1;
attribute mti_svvh_generic_type of m_initial : constant is 1;
attribute mti_svvh_generic_type of m : constant is 1;
attribute mti_svvh_generic_type of n : constant is 1;
attribute mti_svvh_generic_type of m2 : constant is 1;
attribute mti_svvh_generic_type of n2 : constant is 1;
attribute mti_svvh_generic_type of ss : constant is 1;
attribute mti_svvh_generic_type of l0_high : constant is 1;
attribute mti_svvh_generic_type of l0_low : constant is 1;
attribute mti_svvh_generic_type of l0_initial : constant is 1;
attribute mti_svvh_generic_type of l0_mode : constant is 1;
attribute mti_svvh_generic_type of l0_ph : constant is 1;
attribute mti_svvh_generic_type of l0_time_delay : constant is 1;
attribute mti_svvh_generic_type of l1_high : constant is 1;
attribute mti_svvh_generic_type of l1_low : constant is 1;
attribute mti_svvh_generic_type of l1_initial : constant is 1;
attribute mti_svvh_generic_type of l1_mode : constant is 1;
attribute mti_svvh_generic_type of l1_ph : constant is 1;
attribute mti_svvh_generic_type of l1_time_delay : constant is 1;
attribute mti_svvh_generic_type of g0_high : constant is 1;
attribute mti_svvh_generic_type of g0_low : constant is 1;
attribute mti_svvh_generic_type of g0_initial : constant is 1;
attribute mti_svvh_generic_type of g0_mode : constant is 1;
attribute mti_svvh_generic_type of g0_ph : constant is 1;
attribute mti_svvh_generic_type of g0_time_delay : constant is 1;
attribute mti_svvh_generic_type of g1_high : constant is 1;
attribute mti_svvh_generic_type of g1_low : constant is 1;
attribute mti_svvh_generic_type of g1_initial : constant is 1;
attribute mti_svvh_generic_type of g1_mode : constant is 1;
attribute mti_svvh_generic_type of g1_ph : constant is 1;
attribute mti_svvh_generic_type of g1_time_delay : constant is 1;
attribute mti_svvh_generic_type of g2_high : constant is 1;
attribute mti_svvh_generic_type of g2_low : constant is 1;
attribute mti_svvh_generic_type of g2_initial : constant is 1;
attribute mti_svvh_generic_type of g2_mode : constant is 1;
attribute mti_svvh_generic_type of g2_ph : constant is 1;
attribute mti_svvh_generic_type of g2_time_delay : constant is 1;
attribute mti_svvh_generic_type of g3_high : constant is 1;
attribute mti_svvh_generic_type of g3_low : constant is 1;
attribute mti_svvh_generic_type of g3_initial : constant is 1;
attribute mti_svvh_generic_type of g3_mode : constant is 1;
attribute mti_svvh_generic_type of g3_ph : constant is 1;
attribute mti_svvh_generic_type of g3_time_delay : constant is 1;
attribute mti_svvh_generic_type of e0_high : constant is 1;
attribute mti_svvh_generic_type of e0_low : constant is 1;
attribute mti_svvh_generic_type of e0_initial : constant is 1;
attribute mti_svvh_generic_type of e0_mode : constant is 1;
attribute mti_svvh_generic_type of e0_ph : constant is 1;
attribute mti_svvh_generic_type of e0_time_delay : constant is 1;
attribute mti_svvh_generic_type of e1_high : constant is 1;
attribute mti_svvh_generic_type of e1_low : constant is 1;
attribute mti_svvh_generic_type of e1_initial : constant is 1;
attribute mti_svvh_generic_type of e1_mode : constant is 1;
attribute mti_svvh_generic_type of e1_ph : constant is 1;
attribute mti_svvh_generic_type of e1_time_delay : constant is 1;
attribute mti_svvh_generic_type of e2_high : constant is 1;
attribute mti_svvh_generic_type of e2_low : constant is 1;
attribute mti_svvh_generic_type of e2_initial : constant is 1;
attribute mti_svvh_generic_type of e2_mode : constant is 1;
attribute mti_svvh_generic_type of e2_ph : constant is 1;
attribute mti_svvh_generic_type of e2_time_delay : constant is 1;
attribute mti_svvh_generic_type of e3_high : constant is 1;
attribute mti_svvh_generic_type of e3_low : constant is 1;
attribute mti_svvh_generic_type of e3_initial : constant is 1;
attribute mti_svvh_generic_type of e3_mode : constant is 1;
attribute mti_svvh_generic_type of e3_ph : constant is 1;
attribute mti_svvh_generic_type of e3_time_delay : constant is 1;
attribute mti_svvh_generic_type of m_ph : constant is 1;
attribute mti_svvh_generic_type of m_time_delay : constant is 1;
attribute mti_svvh_generic_type of n_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk0_counter : constant is 1;
attribute mti_svvh_generic_type of extclk1_counter : constant is 1;
attribute mti_svvh_generic_type of extclk2_counter : constant is 1;
attribute mti_svvh_generic_type of extclk3_counter : constant is 1;
attribute mti_svvh_generic_type of clk0_counter : constant is 1;
attribute mti_svvh_generic_type of clk1_counter : constant is 1;
attribute mti_svvh_generic_type of clk2_counter : constant is 1;
attribute mti_svvh_generic_type of clk3_counter : constant is 1;
attribute mti_svvh_generic_type of clk4_counter : constant is 1;
attribute mti_svvh_generic_type of clk5_counter : constant is 1;
attribute mti_svvh_generic_type of enable0_counter : constant is 1;
attribute mti_svvh_generic_type of enable1_counter : constant is 1;
attribute mti_svvh_generic_type of charge_pump_current : constant is 1;
attribute mti_svvh_generic_type of loop_filter_r : constant is 1;
attribute mti_svvh_generic_type of loop_filter_c : constant is 1;
attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1;
attribute mti_svvh_generic_type of simulation_type : constant is 1;
attribute mti_svvh_generic_type of down_spread : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of family_name : constant is 1;
attribute mti_svvh_generic_type of skip_vco : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk0_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk1_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk2_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk3_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk0_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk1_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk2_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk3_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1;
attribute mti_svvh_generic_type of EGPP_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of TRST : constant is 1;
attribute mti_svvh_generic_type of TRSTCLK : constant is 1;
end MF_stratix_pll;
|
bsd-2-clause
|
253d43516b31b606f562259d7d8cab1e
| 0.629366 | 3.506384 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_pmic.vhd
| 2 | 4,314 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity wishbone_pmic is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
sample_rate : positive := 48_000;
sclk_period_ns : positive := 80
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
ss, sck : out std_logic ;
miso : in std_logic
);
end wishbone_pmic;
architecture Behavioral of wishbone_pmic is
component ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833
);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
constant time_between_sample_ns : positive := (1_000_000_000/sample_rate);
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- fifo signals
signal reset_fifo : std_logic ;
signal fifo_empty, fifo_full, pop_fifo, push_fifo : std_logic ;
signal fifo_out : std_logic_vector(15 downto 0);
signal fifo_in : std_logic_vector(15 downto 0);
signal enable_fifo, sample_valid : std_logic ;
signal read_ack_old : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
reset_fifo <= wbs_writedata(0);
enable_fifo <= wbs_writedata(1);
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0' ;
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1') then
read_ack <= '1';
else
read_ack <= '0';
end if;
read_ack_old <= read_ack ;
end if;
end process read_bloc;
wbs_readdata <= (NOT fifo_empty) & fifo_full & "00" & fifo_out(11 downto 0);
pop_fifo <= '1' when read_ack = '0' and read_ack_old = '1' else
'0' ;
mi_0 : ADCS7476_ctrl
generic map(clk_period_ns => 10,
sclk_period_ns => sclk_period_ns,
time_between_sample_ns => time_between_sample_ns
)
port map(
clk => gls_clk,
resetn => reset_fifo,
sclk => sck,
ss => ss,
miso => miso,
sample_out => fifo_in(11 downto 0),
sample_valid => sample_valid
);
push_fifo <= enable_fifo and sample_valid ;
fifo0 : small_fifo
generic map( WIDTH => 16, DEPTH => 512)
port map(clk => gls_clk,
resetn => reset_fifo,
empty => fifo_empty,
full => fifo_full,
push => push_fifo, pop => pop_fifo,
data_in => fifo_in,
data_out => fifo_out
);
end Behavioral;
|
lgpl-3.0
|
22228adb4ddd0a8436aadf30e294ddb0
| 0.608484 | 3.207435 | false | false | false | false |
miguelgarcia/sase2017-hls-video
|
hdmi_in_hls/repo/digilent/ip/dvi2rgb_v1_6/src/PhaseAlign.vhd
| 7 | 14,462 |
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
gpl-3.0
|
32641579ea627c1722266bb25a71be11
| 0.639192 | 4.411836 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/mmcm_iserdes_divider_v6/simulation/timing/mmcm_iserdes_divider_v6_tb.vhd
| 1 | 6,693 |
-- file: mmcm_iserdes_divider_v6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity mmcm_iserdes_divider_v6_tb is
end mmcm_iserdes_divider_v6_tb;
architecture test of mmcm_iserdes_divider_v6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 1.613 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
signal CLK_IN1_P : std_logic := '1';
signal CLK_IN1_N : std_logic := '0';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
component mmcm_iserdes_divider_v6_exdes
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
CLK_IN1_P <= CLK_IN1;
CLK_IN1_N <= not CLK_IN1;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : mmcm_iserdes_divider_v6_exdes
port map
(-- Clock in ports
CLK_IN1_P => CLK_IN1_P,
CLK_IN1_N => CLK_IN1_N,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
end test;
|
gpl-3.0
|
e601553cf5e1ee54c01ba07194cd10bc
| 0.615419 | 4.141708 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altshift_taps/_primary.vhd
| 1 | 1,469 |
library verilog;
use verilog.vl_types.all;
entity altshift_taps is
generic(
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_type : string := "altshift_taps";
intended_device_family: string := "Stratix";
lpm_hint : string := "UNUSED";
RAM_WIDTH : vl_notype;
TOTAL_TAP_DISTANCE: vl_notype
);
port(
shiftin : in vl_logic_vector;
clock : in vl_logic;
clken : in vl_logic;
aclr : in vl_logic;
shiftout : out vl_logic_vector;
taps : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_taps : constant is 1;
attribute mti_svvh_generic_type of tap_distance : constant is 1;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of power_up_state : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of RAM_WIDTH : constant is 3;
attribute mti_svvh_generic_type of TOTAL_TAP_DISTANCE : constant is 3;
end altshift_taps;
|
bsd-2-clause
|
f1d2220be410b7d899a1db63ec0dacff
| 0.594282 | 3.77635 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/pulse_regen_k7/example_design/pulse_regen_k7_top.vhd
| 1 | 5,367 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_k7_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_k7_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pulse_regen_k7_top;
architecture xilinx of pulse_regen_k7_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_k7 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pulse_regen_k7 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-3.0
|
089df1c9d278ddc3e1c854dbdfffbdf4
| 0.498044 | 4.618761 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/netlist/afifo_64i_16o_v6_ste/example_design/afifo_64i_16o_v6_top.vhd
| 1 | 19,646 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_64i_16o_v6_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(14-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(16-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(14-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_64i_16o_v6_top;
architecture xilinx of afifo_64i_16o_v6_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_64i_16o_v6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_64i_16o_v6
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
gpl-3.0
|
1b1eb0d6ab62d8fcc95c49549a5801c7
| 0.475771 | 3.951327 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3_System/Keyboard.vhd
| 2 | 2,616 |
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: Keyboard
--Module Description:
-- This is a simple module that eases the interface with a keyboard. It takes the
-- PS/2 bus clock and data pins as inputs, as well as an acknowledgment signal. The
-- outputs are the 8-bit scan code and a signal that tells the host device that
-- the scan code is ready. Every 11 clock cycles, when the entire packet has been sent,
-- the code_ready output is driven high, and stays high until the acknowledgement
-- input is raised to '1'. It doesn't take scan codes while the code_ready output
-- is high.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
Port ( key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
acknowledge : in STD_LOGIC;
scan_code : out STD_LOGIC_VECTOR (7 downto 0);
code_ready : out STD_LOGIC);
end Keyboard;
architecture Behavioral of Keyboard is
--//Components\\--
component Gen_Shift_Reg_Falling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR ((size-1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal code_ready_sig : STD_LOGIC;
signal enable : STD_LOGIC;
signal reg_out : STD_LOGIC_VECTOR(10 downto 0);
--\\Signals//--
begin
count_chk : process (key_clock, acknowledge, enable) is
variable count : integer := 0;
variable ready : STD_LOGIC := '0';
begin
if enable = '1' then
if falling_edge(key_clock) then
count := count + 1;
if count = 11 then
count := 0;
ready := '1';
end if;
end if;
end if;
if (ready = '1') and (acknowledge = '1') then
ready := '0';
end if;
code_ready_sig <= ready;
end process;
shift_reg : Gen_Shift_Reg_Falling generic map (size => 11)
port map (clock => key_clock,
enable => enable,
reset => '0',
data_in => key_data,
data_out => reg_out);
enable <= (not (key_clock and code_ready_sig));
code_ready <= code_ready_sig;
scan_code <= reg_out(2) & reg_out(3) & reg_out(4) & reg_out(5) & reg_out(6) & reg_out(7) & reg_out(8) & reg_out(9);
end Behavioral;
|
mit
|
69c295ff07bad9045d78fce10bfaa433
| 0.556193 | 3.568895 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/triggergenerator.vhd
| 1 | 10,415 |
-- *********************************************************************
-- Copyright 2011, ON Semiconductor Corporation.
--
-- This software is owned by ON Semiconductor Corporation (ON)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of ON.
--
-- Disclaimer: ON makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. ON reserves the right to make changes without further
-- notice to the materials described herein. ON does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. ON's products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the ON Software License Agreement.
--
-- *********************************************************************
-- File : $URL: http://whatever.euro.cypress.com/repos/vita1300/RefKitAltera/VHDL/trunk/CY_VITA/triggergenerator.vhd $
-- Author : $Author: bert.dewil $
-- Department : CISP
-- Date : $Date: 2011-03-22 08:58:11 +0100 (di, 22 mrt 2011) $
-- Revision : $Revision: 1091 $
-- *********************************************************************
-- Description
--
-- Generates trigger to VITA to make the sensor work in triggered mode.
-- Can be used to control integration time
--
-- *********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--user:
-----------
library work;
use work.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity triggergenerator is
port (
-- Control signals
csi_clockreset_clk : in std_logic;
csi_clockreset_reset_n : in std_logic;
coe_external_trigger_in : in std_logic;
readouttrigger : in std_logic;
ENABLETRIGGER : in std_logic_vector(2 downto 0); --what trigger should be used 0 simple mode + 1 and 2 for multislope
SYNCTOREADOUT_OR_EXT : in std_logic_vector(2 downto 0); --(0): enable timeout default frequency
--(1): trigger on readout input trigger
--(2): trigger on external input trigger
--Note: (0) can be combined with (1) xor (2), (1) and (2) can be combined but it is prob not usefull
DEFAULTFREQ : in std_logic_vector(31 downto 0); --acutally an interval
TRIGGERLENGTHLOW0 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHHIGH0 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHLOW1 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHHIGH1 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHLOW2 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHHIGH2 : in std_logic_vector(31 downto 0);
EXTERNAL_TRIGGER_DEB : in std_logic_vector(31 downto 0);
EXTERNAL_TRIGGER_POL : in std_logic; --0 is active low 1 is active high
coe_vita_TRIGGER : out std_logic_vector(2 downto 0)
);
end triggergenerator;
architecture rtl of triggergenerator is
signal trigger_0 : std_logic;
signal trigger_1 : std_logic;
signal trigger_2 : std_logic;
signal TriggerCntr : std_logic_vector(32 downto 0);
signal FPScounter : std_logic_vector(32 downto 0);
signal starttrigger : std_logic;
signal ext_trigger_deb : std_logic;
signal coe_external_trigger_in_d : std_logic;
signal DebCntr : std_logic_vector(32 downto 0);
type TriggerStatetp is ( Idle,
Trig0High,
Trig0Low,
Trig1High,
Trig1Low,
Trig2High,
Trig2Low
);
signal TriggerState : TriggerStatetp;
begin
coe_vita_TRIGGER(0) <= trigger_0;
coe_vita_TRIGGER(1) <= trigger_1;
coe_vita_TRIGGER(2) <= trigger_2;
--Debounce external trigger: trigger is accepted if input signal does not change for EXTERNAL_TRIGGER_DEB and has right polarity
debounce : process(csi_clockreset_clk, csi_clockreset_reset_n)
begin
if (csi_clockreset_reset_n = '0') then
coe_external_trigger_in_d<='0';
ext_trigger_deb <= '0';
DebCntr <= (others => '1');
elsif (csi_clockreset_clk'event and csi_clockreset_clk= '1') then
coe_external_trigger_in_d <=coe_external_trigger_in;
if ((coe_external_trigger_in xor coe_external_trigger_in_d) = '1') then --if change restart
DebCntr <= '0' & EXTERNAL_TRIGGER_DEB;
elsif DebCntr(DebCntr'high)='0' then
DebCntr <= DebCntr - '1';
end if;
ext_trigger_deb <= '0';
if(unsigned(DebCntr)=0 and coe_external_trigger_in_d=EXTERNAL_TRIGGER_POL) then --trigger when change is stable and correct pol
ext_trigger_deb <='1';
end if;
end if;
end process;
--Start trigger generation depending on SYNCTOREADOUT_OR_EXT, input triggers and DEFAULT PERIOD/FREQ
fpsgenerator : process(csi_clockreset_clk, csi_clockreset_reset_n)
begin
if (csi_clockreset_reset_n = '0') then
starttrigger <= '0';
FPScounter <= (others => '1');
elsif (csi_clockreset_clk'event and csi_clockreset_clk= '1') then
starttrigger <= '0';
if (readouttrigger = '1' and SYNCTOREADOUT_OR_EXT(1) = '1') then
starttrigger <= '1';
FPScounter <= '0' & DEFAULTFREQ;
elsif (ext_trigger_deb = '1' and SYNCTOREADOUT_OR_EXT(2) = '1') then
starttrigger <= '1';
FPScounter <= '0' & DEFAULTFREQ;
elsif (FPScounter(FPScounter'high) = '1' ) then --default frequency
starttrigger <= SYNCTOREADOUT_OR_EXT(0);
FPScounter <= '0' & DEFAULTFREQ;
else
FPScounter <= FPScounter - '1';
end if;
end if;
end process;
--On starttrigger start player (once)
triggerprocess : process(csi_clockreset_clk, csi_clockreset_reset_n)
begin
if (csi_clockreset_reset_n = '0') then
trigger_0 <= '0';
trigger_1 <= '0';
trigger_2 <= '0';
TriggerCntr <= (others => '1');
TriggerState <= Idle;
elsif (csi_clockreset_clk'event and csi_clockreset_clk= '1') then
case TriggerState is
when Idle => --holdoff system Trigger is only accepted when system was idle
if starttrigger = '1' and ENABLETRIGGER(0) = '1' then
trigger_0 <= '1';
TriggerCntr <= '0' & TRIGGERLENGTHHIGH0;
TriggerState <= Trig0High;
end if;
when Trig0High =>
if (TriggerCntr(TriggerCntr'high) = '1') then
TriggerCntr <= '0' & TRIGGERLENGTHLOW0;
trigger_0 <= '0';
TriggerState <= Trig0Low;
else
TriggerCntr <= TriggerCntr - '1';
end if;
when Trig0Low =>
if (TriggerCntr(TriggerCntr'high) = '1') then
if (ENABLETRIGGER(1) = '1') then
trigger_1 <= '1';
TriggerCntr <= '0' & TRIGGERLENGTHHIGH1;
TriggerState <= Trig1High;
else
TriggerState <= Idle;
end if;
else
TriggerCntr <= TriggerCntr - '1';
end if;
when Trig1High =>
if (TriggerCntr(TriggerCntr'high) = '1') then
TriggerCntr <= '0' & TRIGGERLENGTHLOW1;
trigger_1 <= '0';
TriggerState <= Trig1Low;
else
TriggerCntr <= TriggerCntr - '1';
end if;
when Trig1Low =>
if (TriggerCntr(TriggerCntr'high) = '1') then
if (ENABLETRIGGER(2) = '1') then
trigger_2 <= '1';
TriggerCntr <= '0' & TRIGGERLENGTHHIGH2;
TriggerState <= Trig2High;
else
TriggerState <= Idle;
end if;
else
TriggerCntr <= TriggerCntr - '1';
end if;
when Trig2High =>
if (TriggerCntr(TriggerCntr'high) = '1') then
TriggerCntr <= '0' & TRIGGERLENGTHLOW2;
trigger_2 <= '0';
TriggerState <= Trig2Low;
else
TriggerCntr <= TriggerCntr - '1';
end if;
when Trig2Low =>
if (TriggerCntr(TriggerCntr'high) = '1') then
TriggerState <= Idle;
else
TriggerCntr <= TriggerCntr - '1';
end if;
when others =>
TriggerState <= Idle;
end case;
end if;
end process;
end rtl;
|
gpl-3.0
|
c21ac63932be0e723915b71ce210af8f
| 0.51397 | 4.47957 | false | false | false | false |
cpulabs/mist1032sa
|
sim/inst_level/work/altdpram/_primary.vhd
| 1 | 4,228 |
library verilog;
use verilog.vl_types.all;
entity altdpram is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
lpm_type : string := "altdpram";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
maximum_depth : integer := 2048;
intended_device_family: string := "Stratix";
ram_block_type : string := "AUTO";
width_byteena : integer := 1;
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
i_byte_size : vl_notype;
is_lutram : vl_notype;
i_width_byteena : vl_notype;
i_read_during_write: vl_notype;
write_at_low_clock: vl_notype
);
port(
wren : in vl_logic;
data : in vl_logic_vector;
wraddress : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
rden : in vl_logic;
rdaddress : in vl_logic_vector;
wraddressstall : in vl_logic;
rdaddressstall : in vl_logic;
byteena : in vl_logic_vector;
outclock : in vl_logic;
outclocken : in vl_logic;
aclr : in vl_logic;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of widthad : constant is 1;
attribute mti_svvh_generic_type of numwords : constant is 1;
attribute mti_svvh_generic_type of lpm_file : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of use_eab : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of indata_reg : constant is 1;
attribute mti_svvh_generic_type of indata_aclr : constant is 1;
attribute mti_svvh_generic_type of wraddress_reg : constant is 1;
attribute mti_svvh_generic_type of wraddress_aclr : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_reg : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_aclr : constant is 1;
attribute mti_svvh_generic_type of rdaddress_reg : constant is 1;
attribute mti_svvh_generic_type of rdaddress_aclr : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_reg : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_aclr : constant is 1;
attribute mti_svvh_generic_type of outdata_reg : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr : constant is 1;
attribute mti_svvh_generic_type of maximum_depth : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of width_byteena : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_mixed_ports : constant is 1;
attribute mti_svvh_generic_type of i_byte_size : constant is 3;
attribute mti_svvh_generic_type of is_lutram : constant is 3;
attribute mti_svvh_generic_type of i_width_byteena : constant is 3;
attribute mti_svvh_generic_type of i_read_during_write : constant is 3;
attribute mti_svvh_generic_type of write_at_low_clock : constant is 3;
end altdpram;
|
bsd-2-clause
|
da901f3a6f102b81252f86378d95bea0
| 0.605014 | 3.795332 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/simple_counter.vhd
| 2 | 1,776 |
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 19:21:07 04/14/2012
-- Design Name:
-- Module Name: simple_counter - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity simple_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sreset : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end simple_counter;
architecture Behavioral of simple_counter is
signal Qp : std_logic_vector(NBIT - 1 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0') ;
elsif clk'event and clk = '1' then
if sreset = '1' then
Qp <= (others => '0') ;
elsif load = '1' then
Qp <= E ;
elsif en = '1' then
Qp <= Qp + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Qp;
end Behavioral;
|
lgpl-3.0
|
0ec77ab7cb6817ec1da5996f88e27ac8
| 0.555743 | 3.646817 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/blk_mem_gen_0/misc/blk_mem_gen_v8_3.vhd
| 1 | 8,325 |
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_6 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_6;
architecture xilinx of blk_mem_gen_v8_3_6 is
begin
end
architecture xilinx;
|
gpl-3.0
|
9fd0543539195bec4f6a4f69dfd25ab2
| 0.42967 | 3.611714 | false | false | false | false |
CprE488/Final
|
system/pcores/led_pwm_v1_00_a/devl/projnav/vens_counter.vhd
| 1 | 1,904 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:33:37 11/19/2014
-- Design Name:
-- Module Name: pwm_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm_generator is
Port ( clk : in STD_LOGIC;
top : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
duty_cycle : in STD_LOGIC_VECTOR (31 downto 0);
enable : in STD_LOGIC;
output : out STD_LOGIC);
end pwm_generator;
architecture Behavioral of pwm_generator is
signal timer_count : unsigned(31 downto 0);
signal out_signal : std_logic;
begin
pwm_proc: process(clk, rst)
begin
if(rst = '1') then
timer_count <= (others => '0');
out_signal <= '1';
elsif(rising_edge(Clock)) then
if(enable = '1') then
timer_count <= timer_count + 1;
end if;
if(timer_count > unsigned(top)) then
timer_count <= (others => '0');
end if;
if(timer_count < unsigned(duty_cycle)) then
out_signal <= '0';
else
out_signal <= '1';
end if;
end if;
end process;
output <= out_signal;
end Behavioral;
|
gpl-3.0
|
3f2ff2acf14b9c51702914a6eaefabf3
| 0.519433 | 4.130152 | false | false | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/ALU_TB.vhd
| 2 | 2,530 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:19:09 10/27/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3/ALU_TB.vhd
-- Project Name: OZ-3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_TB IS
END ALU_TB;
ARCHITECTURE behavior OF ALU_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
A : IN std_logic_vector(31 downto 0);
B : IN std_logic_vector(31 downto 0);
sel : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(31 downto 0);
cond_bits : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(31 downto 0) := (others => '0');
signal B : std_logic_vector(31 downto 0) := (others => '0');
signal sel : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal output : std_logic_vector(31 downto 0);
signal cond_bits : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
A => A,
B => B,
sel => sel,
output => output,
cond_bits => cond_bits
);
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
A <= x"80000001";
B <= x"80000001";
sel <= "0000";
wait for 10 ns;
A <= x"00000001";
wait for 10 ns;
A <= x"80000002";
sel <= "0001";
wait for 10 ns;
A <= x"80000001";
sel <= "0110";
wait for 10 ns;
sel <= "0111";
wait for 10 ns;
sel <= "1000";
wait for 10 ns;
sel <= "1001";
wait;
end process;
END;
|
mit
|
c2a2e4b3127753bee673acd47e004b7c
| 0.547826 | 3.553371 | false | true | false | false |
boztalay/OZ-3
|
FPGA/OZ-3/ConditionBlock.vhd
| 2 | 2,192 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 09:13:21 10/30/2009
-- Design Name:
-- Module Name: ConditionBlock - Behavioral
-- Project Name: OZ-3
-- Target Devices: Xilinx XC3S500E-4FG320
-- Tool versions:
-- Description: The condition block of the OZ-3; handles the condition flags
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.30 - File written and syntax checked
-- Revision 0.90 - Successfully simulated
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ConditionBlock is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(2 downto 0);
flags : in STD_LOGIC_VECTOR(4 downto 0);
cond_out : out STD_LOGIC);
end ConditionBlock;
architecture Behavioral of ConditionBlock is
component GenReg is
generic (size: integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
signal flags_reg_out : STD_LOGIC_VECTOR(3 downto 0);
begin
main: process (sel, flags_reg_out, flags(4)) is
begin
case (sel) is
when b"001" =>
cond_out <= flags_reg_out(0);
when b"010" =>
cond_out <= flags_reg_out(1);
when b"011" =>
cond_out <= flags_reg_out(2);
when b"100" =>
cond_out <= flags_reg_out(3);
when b"101" =>
cond_out <= flags(4);
when b"110" =>
cond_out <= '1';
when others =>
cond_out <= '0';
end case;
end process;
flags_reg: GenReg generic map (size => 4)
port map (clock, '1', reset, flags(3 downto 0), flags_reg_out);
end Behavioral;
|
mit
|
45b2b7b86ff6dbaf911f4747a98484fe
| 0.569799 | 3.425 | false | false | false | false |
victor1994y/BipedRobot_byFPGA
|
Project_BipedRobot.srcs/sources_1/ip/clk_bluetooth/clk_bluetooth_sim_netlist.vhdl
| 1 | 7,684 |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
-- Date : Tue Aug 15 11:27:48 2017
-- Host : ACER-BLUES running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/clk_bluetooth/clk_bluetooth_sim_netlist.vhdl
-- Design : clk_bluetooth
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_bluetooth_clk_bluetooth_clk_wiz is
port (
clk_txd : out STD_LOGIC;
clk_rxd : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_bluetooth_clk_bluetooth_clk_wiz : entity is "clk_bluetooth_clk_wiz";
end clk_bluetooth_clk_bluetooth_clk_wiz;
architecture STRUCTURE of clk_bluetooth_clk_bluetooth_clk_wiz is
signal clk_in1_clk_bluetooth : STD_LOGIC;
signal clk_rxd_clk_bluetooth : STD_LOGIC;
signal clk_txd_clk_bluetooth : STD_LOGIC;
signal clkfbout_buf_clk_bluetooth : STD_LOGIC;
signal clkfbout_clk_bluetooth : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_bluetooth,
O => clkfbout_buf_clk_bluetooth
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_bluetooth
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_txd_clk_bluetooth,
O => clk_txd
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_rxd_clk_bluetooth,
O => clk_rxd
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 20.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 20,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_bluetooth,
CLKFBOUT => clkfbout_clk_bluetooth,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_bluetooth,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_txd_clk_bluetooth,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_rxd_clk_bluetooth,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_bluetooth is
port (
clk_txd : out STD_LOGIC;
clk_rxd : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_bluetooth : entity is true;
end clk_bluetooth;
architecture STRUCTURE of clk_bluetooth is
begin
inst: entity work.clk_bluetooth_clk_bluetooth_clk_wiz
port map (
clk_in1 => clk_in1,
clk_rxd => clk_rxd,
clk_txd => clk_txd,
locked => locked,
resetn => resetn
);
end STRUCTURE;
|
gpl-3.0
|
8bf022b0a2a7f4bb8c76661e8b525045
| 0.639901 | 3.500683 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/axi_tpg_v2_00_a/hdl/vhdl/AWGN.vhd
| 1 | 515 |
Generation_WGN:process
variable seed11:integer:=2000;
variable seed12:integer:=10000;
variable x,y::real;
begin
uniform(seed11, seed12, x1);
uniform(seed11, seed12, x2);
noise <=sqrt(-2.0*log(x1))*cos(2.0*math_pi*x2);
wait for 1 ns;
level <= (ve_db SNR);
noise_generator_out <= 10.0 **(level/20.0)*noise;
end process Generation_WGN;
break on noise_generator_out;
vo==ve DELAYED (T1) + noise_generator_out;
//vo = receiver input et ve=transmitter_output
end architecture arch;
|
gpl-3.0
|
ab9508f3233c4c4e3740edc3a0c7b944
| 0.675728 | 2.845304 | false | false | false | false |
CprE488/Final
|
repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/vhdl/iserdes_datadeser_s6.vhd
| 1 | 8,853 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2012 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Apr 23, 2012
-- Design Name: FMC-IMAGEON
-- Module Name: iserdes_datadeser_s6.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Spartan 6
-- Avnet Boards: FMC-IMAGEON
-- Tool versions: ISE 13.4
-- Description: Spartan 6 10:1 iSerDes Datapath
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
library work;
use work.all;
--xilinx:
---------
-- synopsys translate_off
Library XilinxCoreLib;
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity iserdes_datadeser_s6 is
port (
RESET : in std_logic;
CLOCK : in std_logic;
PCLK01x : in std_logic;
PCLK02x : in std_logic;
PCLK10x : in std_logic;
STROBE : in std_logic;
SDATAP : in std_logic;
SDATAN : in std_logic;
ALIGN_START : in std_logic;
FIFO_EN : in std_logic;
TRAINING : in std_logic_vector(9 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector(9 downto 0)
);
end iserdes_datadeser_s6;
architecture rtl of iserdes_datadeser_s6 is
component serdes_1_to_5_diff_data is
generic (
DIFF_TERM : string;
BITSLIP_ENABLE : string
);
port (
reset : in std_logic;
gclk : in std_logic;
rxioclk : in std_logic;
rxserdesstrobe : in std_logic;
bitslip : in std_logic;
use_phase_detector : in std_logic;
datain_p : in std_logic;
datain_n : in std_logic;
data_out : out std_logic_vector(4 downto 0)
);
end component;
component phsaligner is
port (
rst : in std_logic;
clk : in std_logic;
training : in std_logic_vector(9 downto 0);
sdata : in std_logic_vector(9 downto 0);
bitslip : out std_logic;
flipgear : out std_logic;
psaligned : out std_logic
);
end component;
component FIFO18_s6 is
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
signal ALIGNED_o : std_logic;
signal RAWBYTE : std_logic_vector(4 downto 0);
signal RAWBYTE_q : std_logic_vector(4 downto 0);
signal RAWWORD : std_logic_vector(9 downto 0);
signal RX_TOGGLE : std_logic;
signal RX_TOGGLE_q : std_logic;
signal BITSLIP : std_logic;
signal BITSLIP_d : std_logic;
signal BITSLIP_p : std_logic;
signal FLIPGEAR : std_logic;
signal FLIPGEAR_s : std_logic;
signal FIFO_EN_d0 : std_logic;
signal FIFO_EN_d1 : std_logic;
signal FIFO_DI : std_logic_vector(15 downto 0);
signal FIFO_DO : std_logic_vector(15 downto 0);
signal FIFO_FULL : std_logic;
begin
ALIGNED <= ALIGNED_o;
-- Align Busy
process (CLOCK)
begin
if (RESET = '1') then
ALIGN_BUSY <= '0';
elsif (CLOCK'event and CLOCK = '1') then
if (ALIGN_START = '1') then
ALIGN_BUSY <= '1';
elsif (ALIGNED_o = '1') then
ALIGN_BUSY <= '0';
end if;
end if;
end process;
-- SerDes Core
SERDES_CORE : serdes_1_to_5_diff_data
generic map (
DIFF_TERM => "FALSE" ,
BITSLIP_ENABLE => "TRUE"
)
port map (
reset => RESET ,
gclk => PCLK02x ,
rxioclk => PCLK10x ,
rxserdesstrobe => STROBE ,
bitslip => BITSLIP_p ,
use_phase_detector => '1' ,
datain_p => SDATAP ,
datain_n => SDATAN ,
data_out => RAWBYTE
);
process (PCLK02x)
begin
if (RESET = '1') then
BITSLIP_d <= '0';
elsif (PCLK02x'event and PCLK02x = '1') then
BITSLIP_d <= BITSLIP;
end if;
end process;
process (PCLK02x)
begin
if (RESET = '1') then
BITSLIP_p <= '0';
elsif (PCLK02x'event and PCLK02x = '1') then
BITSLIP_p <= (not BITSLIP_d) and BITSLIP;
end if;
end process;
-- BitSlip Control
BITSLIP_CTRL : phsaligner
port map (
rst => RESET ,
clk => PCLK01x ,
training => TRAINING ,
sdata => RAWWORD ,
bitslip => BITSLIP ,
flipgear => FLIPGEAR ,
psaligned => ALIGNED_o
);
-- GearBox
RX_TOGGLE <= RX_TOGGLE_q xor FLIPGEAR_s;
process (PCLK02x)
begin
if (RESET = '1') then
FLIPGEAR_s <= '0';
elsif (PCLK02x'event and PCLK02x = '1') then
FLIPGEAR_s <= FLIPGEAR;
end if;
end process;
process (PCLK02x)
begin
if (RESET = '1') then
RX_TOGGLE_q <= '0';
elsif (PCLK02x'event and PCLK02x = '1') then
RX_TOGGLE_q <= not RX_TOGGLE_q;
end if;
end process;
process (PCLK02x)
begin
if (RESET = '1') then
RAWBYTE_q <= (others => '0');
elsif (PCLK02x'event and PCLK02x = '1') then
RAWBYTE_q <= RAWBYTE;
end if;
end process;
process (PCLK02x)
begin
if (RESET = '1') then
RAWWORD <= (others => '0');
elsif (PCLK02x'event and PCLK02x = '1') then
if (RX_TOGGLE = '1') then
RAWWORD <= RAWBYTE_q & RAWBYTE;
end if;
end if;
end process;
-- FIFO18
blockramgen_s6 : FIFO18_s6
port map (
rst => RESET ,
wr_clk => PCLK01x ,
rd_clk => CLOCK ,
din => FIFO_DI ,
wr_en => FIFO_EN_d1 ,
rd_en => FIFO_RDEN ,
dout => FIFO_DO ,
full => FIFO_FULL ,
empty => FIFO_EMPTY
);
FIFO_DI(15 downto 10) <= (others => '0');
FIFO_DI( 9 downto 0) <= RAWWORD;
FIFO_DATAOUT <= FIFO_DO( 9 downto 0);
process (PCLK01x)
begin
if (RESET = '1') then
FIFO_EN_d0 <= '0';
FIFO_EN_d1 <= '0';
elsif (PCLK01x'event and PCLK01x = '1') then
FIFO_EN_d0 <= FIFO_EN;
FIFO_EN_d1 <= FIFO_EN_d0;
end if;
end process;
end rtl;
|
gpl-3.0
|
95b8246343e400729ba2a130957aef84
| 0.441771 | 3.905161 | false | false | false | false |
CprE488/Final
|
system/implementation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif.vhd
| 2 | 5,736 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
gpl-3.0
|
0a01e34e8895b9d06947aa8153cd98ee
| 0.585251 | 4.02244 | false | false | false | false |
fpga-logi/logi-hard
|
hdl/utils/logi_utils_pack.vhd
| 1 | 5,338 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.log2;
use IEEE.MATH_REAL.ceil;
package logi_utils_pack is
function nbit(max : integer) return integer;
function count_ones(slv : std_logic_vector) return natural;
function max(LEFT : integer ; RIGHT: integer) return integer ;
type fifo16_bus is
record
fifo_data_in : std_logic_vector(15 downto 0);
fifo_data_out : std_logic_vector(15 downto 0);
fifo_wr : std_logic ;
fifo_rd : std_logic ;
fifo_full : std_logic ;
fifo_empty : std_logic ;
fifo_nb_free : std_logic_vector(15 downto 0);
fifo_nb_available : std_logic_vector(15 downto 0);
end record;
type slv8_array is array (natural range <>) of std_logic_vector(7 downto 0);
type slv16_array is array (natural range <>) of std_logic_vector(15 downto 0);
type slv32_array is array (natural range <>) of std_logic_vector(31 downto 0);
component simple_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sreset : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end component;
component up_down_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en, load : in STD_LOGIC;
up_downn : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end component;
component generic_latch is
generic(NBIT : positive := 8);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end component;
component edge_triggered_latch is
generic(NBIT : positive := 8; POL : std_logic :='1');
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end component;
component generic_delay is
generic( WIDTH : positive := 1; DELAY : positive := 1);
port(
clk, resetn : std_logic ;
input : in std_logic_vector((WIDTH - 1) downto 0);
output : out std_logic_vector((WIDTH - 1) downto 0)
);
end component;
component dp_fifo is
generic(N : natural := 128 ;
W : positive := 16;
SYNC_WR : boolean := false;
SYNC_RD : boolean := false);
port(
clk, resetn, sraz : in std_logic;
wr, rd : in std_logic;
empty, full : out std_logic ;
data_out : out std_logic_vector((W - 1) downto 0 );
data_in : in std_logic_vector((W - 1) downto 0 );
nb_available : out unsigned(nbit(N) downto 0 )
);
end component;
component small_stack is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component generic_rs_latch is
port(clk, resetn : in std_logic ;
s, r : in std_logic ;
q : out std_logic );
end component;
component detect_value is
generic(to_be_detected : integer := 16;
nbit : positive := 32);
port(
value : in std_logic_vector(nbit-1 downto 0);
detected : out std_logic
);
end component;
component ff_sync is
generic(
STAGES : integer := 1;
WIDTH : integer := 1;
RESET_VAL : std_logic := '0'
);
port(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(WIDTH-1 downto 0);
dout : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component bin2gray4 is
port(
bin : in std_logic_vector(3 downto 0);
gray : out std_logic_vector(3 downto 0)
);
end component;
component gray2bin4 is
port(
gray : in std_logic_vector(3 downto 0);
bin : out std_logic_vector(3 downto 0)
);
end component;
end logi_utils_pack;
package body logi_utils_pack is
function nbit (max : integer) return integer is
begin
if max = 0 then
return 1 ;
end if;
return (integer(ceil(log2(real(max)))));
end nbit;
function count_ones(slv : std_logic_vector) return natural is
variable n_ones : natural := 0;
begin
for i in slv'range loop
if slv(i) ='1' then
n_ones := n_ones + 1;
end if;
end loop;
return n_ones;
end function count_ones;
function max(LEFT : integer; RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
end logi_utils_pack;
|
lgpl-3.0
|
6c6b6c236cc9bcf8a292e11b5884b90d
| 0.634507 | 3.107101 | false | false | false | false |
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