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int64 1
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int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
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float64 1.51
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bool 1
class | config_or_test
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classes | has_no_keywords
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class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/simulation/fifo_dgen.vhd
| 1 | 4,628 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
mit
|
9306a41f087f5a4e5c0e434e702ce1df
| 0.582973 | 4.113778 | false | false | false | false |
plorefice/freon
|
tests/hdl/core/alu_tb.vhdl
| 1 | 11,405 |
-- Design:
-- Testbench for the Arithmetic Logic Unit of the Freon core.
-- Tests taken from: https://github.com/riscv/riscv-tests
--
-- Authors:
-- Pietro Lorefice <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_tb is
end entity; -- alu_tb
architecture tb of alu_tb is
constant T : time := 1 ns; -- arbitrary test time
signal opsel : std_logic_vector(2 downto 0) := (others => '0');
signal ctrl : std_logic := '0';
signal op1, op2, res : std_logic_vector(31 downto 0) := (others => '0');
begin
-- unit under test
uut : entity work.alu
generic map (XLEN => 32)
port map (
opsel => opsel,
ctrl => ctrl,
op1 => op1,
op2 => op2,
res => res
);
-- testbench process
tb_proc : process
begin
--##############################################################
-- [ADD]
--##############################################################
opsel <= "000"; ctrl <= '0';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[ADD] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000002" report "[ADD] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"0000000A" report "[ADD] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"ffff8000" report "[ADD] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"80000000" report "[ADD] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"7fff8000" report "[ADD] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00007fff" report "[ADD] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"7fffffff" report "[ADD] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"80007ffe" report "[ADD] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"80007fff" report "[ADD] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"7fff7fff" report "[ADD] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"ffffffff" report "[ADD] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[ADD] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"fffffffe" report "[ADD] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"7fffffff"; wait for T;
assert res = X"80000000" report "[ADD] Wrong result" severity failure;
--##############################################################
-- [SUB]
--##############################################################
opsel <= "000"; ctrl <= '1';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SUB] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SUB] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"fffffffc" report "[SUB] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00008000" report "[SUB] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"80000000" report "[SUB] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"80008000" report "[SUB] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"ffff8001" report "[SUB] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"7fffffff" report "[SUB] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"7fff8000" report "[SUB] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"7fff8001" report "[SUB] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"80007fff" report "[SUB] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000001" report "[SUB] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"fffffffe" report "[SUB] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SUB] Wrong result" severity failure;
--##############################################################
-- [SLT]
--##############################################################
opsel <= "010"; ctrl <= '0';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"00000007"; op2 <= X"00000003"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
--##############################################################
-- [SLTU]
--##############################################################
opsel <= "011"; ctrl <= '0';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000007"; op2 <= X"00000003"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
--##############################################################
-- [AND]
--##############################################################
opsel <= "111"; ctrl <= '0';
op1 <= X"ff00ff00"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"0f000f00" report "[AND] Wrong result" severity failure;
op1 <= X"0ff00ff0"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"00f000f0" report "[AND] Wrong result" severity failure;
op1 <= X"00ff00ff"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"000f000f" report "[AND] Wrong result" severity failure;
op1 <= X"f00ff00f"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"f000f000" report "[AND] Wrong result" severity failure;
--##############################################################
-- [OR]
--##############################################################
opsel <= "110"; ctrl <= '0';
op1 <= X"ff00ff00"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"ff0fff0f" report "[OR] Wrong result" severity failure;
op1 <= X"0ff00ff0"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"fff0fff0" report "[OR] Wrong result" severity failure;
op1 <= X"00ff00ff"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"0fff0fff" report "[OR] Wrong result" severity failure;
op1 <= X"f00ff00f"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"f0fff0ff" report "[OR] Wrong result" severity failure;
--##############################################################
-- [XOR]
--##############################################################
opsel <= "100"; ctrl <= '0';
op1 <= X"ff00ff00"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"f00ff00f" report "[XOR] Wrong result" severity failure;
op1 <= X"0ff00ff0"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"ff00ff00" report "[XOR] Wrong result" severity failure;
op1 <= X"00ff00ff"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"0ff00ff0" report "[XOR] Wrong result" severity failure;
op1 <= X"f00ff00f"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"00ff00ff" report "[XOR] Wrong result" severity failure;
wait; -- Terminate testbench
end process; -- tb_proc
end architecture; -- tb
|
mit
|
a76ddc42f172bf6ec514e32c73c85543
| 0.589215 | 3.294339 | false | false | false | false |
jpendlum/crash
|
fpga/src/common/edge_detect.vhd
| 2 | 2,635 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: edge_detect.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Reports a change in the input vector.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity edge_detect is
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end entity;
architecture RTL of edge_detect is
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal input_detect_dly1 : std_logic;
begin
proc_edge_detect : process(clk,reset)
begin
if (reset = '1') then
input_detect_dly1 <= '0';
edge_detect_stb <= '0';
else
if rising_edge(clk) then
input_detect_dly1 <= input_detect;
-- Ensure strobe is 1 clock cycle long
edge_detect_stb <= '0';
-- Rising edge detected
if (EDGE(EDGE'left) = 'R' AND input_detect = '1' AND input_detect_dly1 = '0') then
edge_detect_stb <= '1';
end if;
-- Falling edge detected
if (EDGE(EDGE'left) = 'F' AND input_detect = '0' AND input_detect_dly1 = '1') then
edge_detect_stb <= '1';
end if;
-- Either edge detected
if (EDGE(EDGE'left) = 'B' AND input_detect /= input_detect_dly1) then
edge_detect_stb <= '1';
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
f758e85a2a43ebdd7f49c677454c4723
| 0.529791 | 4.066358 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo.vhd
| 1 | 10,441 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synthesis translate_off
COMPONENT wrapped_fifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 6,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 1,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 62,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 61,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 6,
c_rd_depth => 64,
c_rd_freq => 1,
c_rd_pntr_width => 6,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 6,
c_wr_depth => 64,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 6,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
data_count => data_count
);
-- synthesis translate_on
END fifo_a;
|
mit
|
ede1558d417128622e3116800730be80
| 0.520831 | 3.384441 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx.vhd
| 1 | 8,096 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx
---- Version: 1.0.0
---- Description:
---- CCSDS compliant TX
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/19: rework
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx external physical inputs and outputs
--=============================================================================
entity ccsds_tx is
generic (
constant CCSDS_TX_BITS_PER_SYMBOL: integer := 1;
constant CCSDS_TX_BUFFER_SIZE: integer := 16; -- max number of words stored for burst write at full speed when datalinklayer is full
constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=QAM/QPSK / 2=BPSK
constant CCSDS_TX_DATA_BUS_SIZE: integer;
constant CCSDS_TX_OVERSAMPLING_RATIO: integer := 4; -- symbols to samples over-sampling ratio
constant CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
);
port(
-- inputs
clk_i: in std_logic; -- transmitted samples clock
dat_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0); -- transmitted parallel data input
dat_ser_i: in std_logic; -- transmitted serial data input
dat_val_i: in std_logic; -- transmitted data valid input
ena_i: in std_logic; -- system enable input
in_sel_i: in std_logic; -- parallel / serial input selection
rst_i: in std_logic; -- system reset input
-- outputs
buf_ful_o: out std_logic; -- buffer full indicator
clk_o: out std_logic; -- output samples clock
ena_o: out std_logic; -- enabled status indicator
idl_o: out std_logic; -- idle data insertion indicator
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0) -- quadrature-phased parallel complex samples
);
end ccsds_tx;
--=============================================================================
-- architecture declaration / internal connections
--=============================================================================
architecture structure of ccsds_tx is
component ccsds_tx_manager is
generic(
CCSDS_TX_MANAGER_BITS_PER_SYMBOL: integer;
CCSDS_TX_MANAGER_MODULATION_TYPE: integer;
CCSDS_TX_MANAGER_DATA_BUS_SIZE : integer;
CCSDS_TX_MANAGER_OVERSAMPLING_RATIO: integer
);
port(
clk_i: in std_logic;
clk_bit_o: out std_logic;
clk_dat_o: out std_logic;
clk_sam_o: out std_logic;
clk_sym_o: out std_logic;
rst_i: in std_logic;
ena_i: in std_logic;
ena_o: out std_logic;
in_sel_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
dat_ser_i: in std_logic;
dat_val_i: in std_logic;
dat_val_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0)
);
end component;
component ccsds_rxtx_buffer is
generic(
constant CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer;
constant CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_nxt_i: in std_logic;
rst_i: in std_logic;
buf_emp_o: out std_logic;
buf_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_datalink_layer is
generic(
CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer;
CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer
);
port(
clk_bit_i: in std_logic;
clk_dat_i: in std_logic;
rst_i: in std_logic;
dat_val_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_tx_physical_layer is
generic(
CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL: integer;
CCSDS_TX_PHYSICAL_MODULATION_TYPE: integer;
CCSDS_TX_PHYSICAL_DATA_BUS_SIZE: integer;
CCSDS_TX_PHYSICAL_OVERSAMPLING_RATIO: integer;
CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH: integer
);
port(
clk_sam_i: in std_logic;
clk_sym_i: in std_logic;
rst_i: in std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
dat_i: in std_logic_vector(CCSDS_TX_PHYSICAL_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic
);
end component;
signal wire_dat_nxt_buf: std_logic;
signal wire_dat_val_buf: std_logic;
signal wire_dat_val_dat: std_logic;
signal wire_dat_val_man: std_logic;
signal wire_dat_buf: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_dat_dat: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_dat_man: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_clk_dat: std_logic;
signal wire_clk_sam: std_logic;
signal wire_clk_sym: std_logic;
signal wire_clk_bit: std_logic;
signal wire_rst_man: std_logic;
begin
tx_manager_0: ccsds_tx_manager
generic map(
CCSDS_TX_MANAGER_BITS_PER_SYMBOL => CCSDS_TX_BITS_PER_SYMBOL,
CCSDS_TX_MANAGER_MODULATION_TYPE => CCSDS_TX_MODULATION_TYPE,
CCSDS_TX_MANAGER_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_TX_MANAGER_OVERSAMPLING_RATIO => CCSDS_TX_OVERSAMPLING_RATIO
)
port map(
clk_i => clk_i,
clk_bit_o => wire_clk_bit,
clk_dat_o => wire_clk_dat,
clk_sam_o => wire_clk_sam,
clk_sym_o => wire_clk_sym,
rst_i => rst_i,
ena_i => ena_i,
ena_o => ena_o,
in_sel_i => in_sel_i,
dat_val_i => dat_val_i,
dat_par_i => dat_par_i,
dat_ser_i => dat_ser_i,
dat_val_o => wire_dat_val_man,
dat_o => wire_dat_man
);
tx_buffer_0: ccsds_rxtx_buffer
generic map(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_RXTX_BUFFER_SIZE => CCSDS_TX_BUFFER_SIZE
)
port map(
clk_i => wire_clk_dat,
rst_i => rst_i,
dat_nxt_i => wire_dat_nxt_buf,
dat_val_i => wire_dat_val_man,
dat_i => wire_dat_man,
dat_val_o => wire_dat_val_buf,
-- buf_emp_o => ,
buf_ful_o => buf_ful_o,
dat_o => wire_dat_buf
);
tx_datalink_layer_0: ccsds_tx_datalink_layer
generic map(
CCSDS_TX_DATALINK_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_BITS_PER_SYMBOL
)
port map(
clk_dat_i => wire_clk_dat,
clk_bit_i => wire_clk_bit,
rst_i => rst_i,
dat_val_i => wire_dat_val_buf,
dat_i => wire_dat_buf,
dat_val_o => wire_dat_val_dat,
dat_nxt_o => wire_dat_nxt_buf,
dat_o => wire_dat_dat,
idl_o => idl_o
);
tx_physical_layer_0: ccsds_tx_physical_layer
generic map(
CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH => CCSDS_TX_PHYS_SIG_QUANT_DEPTH,
CCSDS_TX_PHYSICAL_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_TX_PHYSICAL_MODULATION_TYPE => CCSDS_TX_MODULATION_TYPE,
CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL => CCSDS_TX_BITS_PER_SYMBOL,
CCSDS_TX_PHYSICAL_OVERSAMPLING_RATIO => CCSDS_TX_OVERSAMPLING_RATIO
)
port map(
clk_sym_i => wire_clk_sym,
clk_sam_i => wire_clk_sam,
rst_i => rst_i,
sam_i_o => sam_i_o,
sam_q_o => sam_q_o,
dat_i => wire_dat_dat,
dat_val_i => wire_dat_val_dat
);
clk_o <= wire_clk_sam;
end structure;
|
mit
|
c59d0b902b8b24b8489e7697724edb5c
| 0.600049 | 3.22293 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/lcd/lcd.vhd
| 1 | 6,348 |
library ieee;
use ieee.std_logic_1164.all;
package lcd_types is
subtype char is std_logic_vector(7 downto 0);
type char_vector is array(natural range <>) of char;
subtype char_graphics is std_logic_vector(39 downto 0);
type char_graphics_vector is array(natural range <>) of char_graphics;
end package lcd_types;
library ieee;
use ieee.std_logic_1164.all;
use work.lcd_types.all;
package lcd_components is
component lcd is
port(
reset, clock : IN STD_LOGIC;
dd : IN CHAR_VECTOR(0 to 31);
cg : IN CHAR_GRAPHICS_VECTOR(0 to 7);
LCD_ON : OUT STD_LOGIC; -- LCD Power ON/OFF
LCD_BLON : OUT STD_LOGIC; -- LCD Back Light ON/OFF
LCD_RW : OUT STD_LOGIC; -- LCD Read/Write Select; 0 = Write; 1 = Read
LCD_EN : OUT STD_LOGIC; -- LCD Enable
LCD_RS : OUT STD_LOGIC; -- LCD Command/Data Select; 0 = Command; 1 = Data
LCD_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- LCD Data bus 8 bits
);
end component lcd;
end package lcd_components;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.lcd_types.all;
ENTITY lcd IS
PORT(
reset, clock : IN STD_LOGIC;
dd : IN CHAR_VECTOR(0 to 31);
cg : IN CHAR_GRAPHICS_VECTOR(0 to 7);
LCD_ON : OUT STD_LOGIC; -- LCD Power ON/OFF
LCD_BLON : OUT STD_LOGIC; -- LCD Back Light ON/OFF
LCD_RW : OUT STD_LOGIC; -- LCD Read/Write Select; 0 = Write; 1 = Read
LCD_EN : OUT STD_LOGIC; -- LCD Enable
LCD_RS : OUT STD_LOGIC; -- LCD Command/Data Select; 0 = Command; 1 = Data
LCD_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- LCD Data bus 8 bits
);
END ENTITY lcd;
ARCHITECTURE lcd of lcd is
SIGNAL wait_counter : INTEGER := 0;
SIGNAL timing_counter : INTEGER := 0;
TYPE timing_states IS (idle, setup, hold);
SIGNAL timing_state : timing_states := idle;
TYPE timing_modes IS (idle, read_cmd, read_data, write_cmd, write_data);
SIGNAL timing_mode : timing_modes := idle;
SIGNAL timing_done : STD_LOGIC := '1';
CONSTANT init_cmds_count : INTEGER := 4;
CONSTANT init_cmds : CHAR_VECTOR(0 to init_cmds_count - 1) := (
x"38", -- set up interface
x"0C", -- set up display
x"01", -- clear screen
x"06" -- set up entry mode
);
CONSTANT init_cmds_wait : INTEGER := 100000; -- wait 2 ms for each init command
TYPE states IS (
init,
init_cmd,
init_cmd_complete,
update_cg,
update_cg_addr,
update_cg_addr_complete,
update_cg_data,
update_cg_data_complete,
update_dd,
update_dd_addr,
update_dd_addr_complete,
update_dd_data,
update_dd_data_complete
);
SIGNAL state : states := init;
SIGNAL i, j : INTEGER := 0;
BEGIN
LCD_ON <= '1';
LCD_BLON <= '1';
timing: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
timing_state <= idle;
timing_counter <= 0;
timing_done <= '1';
ELSIF (clock = '1' AND clock'event) THEN
IF (timing_counter > 0) THEN
timing_counter <= timing_counter - 1;
ELSE
CASE timing_state IS
WHEN idle =>
CASE timing_mode IS
WHEN idle =>
LCD_RS <= '0';
LCD_RW <= '1';
timing_done <= '1';
timing_state <= idle;
WHEN read_cmd =>
LCD_RS <= '0';
LCD_RW <= '1';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
WHEN read_data =>
LCD_RS <= '1';
LCD_RW <= '1';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
WHEN write_cmd =>
LCD_RS <= '0';
LCD_RW <= '0';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
WHEN write_data =>
LCD_RS <= '1';
LCD_RW <= '0';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
END CASE;
WHEN setup =>
LCD_EN <= '1';
timing_counter <= 30;
timing_state <= hold;
WHEN hold =>
LCD_EN <= '0';
timing_counter <= 3000; -- a 60 microsecond wait guarantees operation execution
timing_state <= idle;
WHEN others =>
timing_state <= idle;
END CASE;
END IF;
END IF;
END PROCESS;
fsm: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
timing_mode <= idle;
state <= init;
ELSIF (clock = '1' AND clock'event) THEN
IF (timing_mode /= idle) THEN
timing_mode <= idle;
ELSIF (timing_done /= '1') THEN
ELSIF (wait_counter > 0) THEN
wait_counter <= wait_counter - 1;
ELSE
CASE state IS
WHEN init =>
i <= 0;
timing_mode <= idle;
wait_counter <= init_cmds_wait;
state <= init_cmd;
WHEN init_cmd =>
LCD_DATA <= init_cmds(i);
timing_mode <= write_cmd;
wait_counter <= init_cmds_wait;
state <= init_cmd_complete;
WHEN init_cmd_complete =>
IF (i = init_cmds_count - 1) THEN
state <= update_cg;
ELSE
i <= i + 1;
state <= init_cmd;
END IF;
WHEN update_cg =>
i <= 0;
j <= 0;
state <= update_cg_addr;
WHEN update_cg_addr =>
LCD_DATA <= "01" & std_logic_vector(to_unsigned(i, 3)) & std_logic_vector(to_unsigned(j, 3));
timing_mode <= write_cmd;
state <= update_cg_addr_complete;
WHEN update_cg_addr_complete =>
state <= update_cg_data;
WHEN update_cg_data =>
LCD_DATA <= "000" & cg(i)(39 - j * 5 downto 35 - j * 5);
timing_mode <= write_data;
state <= update_cg_data_complete;
WHEN update_cg_data_complete =>
IF (j = 7) THEN
IF (i = 7) THEN
state <= update_dd;
ELSE
j <= 0;
i <= i + 1;
state <= update_cg_addr;
END IF;
ELSE
j <= j + 1;
state <= update_cg_addr;
END IF;
WHEN update_dd =>
i <= 0;
j <= 0;
state <= update_dd_addr;
WHEN update_dd_addr =>
LCD_DATA <= "1" & std_logic_vector(to_unsigned(i, 1)) & "00" & std_logic_vector(to_unsigned(j, 4));
timing_mode <= write_cmd;
state <= update_dd_addr_complete;
WHEN update_dd_addr_complete =>
state <= update_dd_data;
WHEN update_dd_data =>
LCD_DATA <= dd(i * 16 + j);
timing_mode <= write_data;
state <= update_dd_data_complete;
WHEN update_dd_data_complete =>
IF (j = 15) THEN
IF (i = 1) THEN
state <= update_cg;
ELSE
j <= 0;
i <= i + 1;
state <= update_dd_addr;
END IF;
ELSE
j <= j + 1;
state <= update_dd_addr;
END IF;
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE lcd;
|
mit
|
9621478e59d28915b6c13f304816916f
| 0.588689 | 2.849192 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/DMA.vhd
| 1 | 5,404 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:37 11/17/2016
-- Design Name:
-- Module Name: DMA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.PIC_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
RCVD_Data : in STD_LOGIC_VECTOR (7 downto 0);
RX_Full : in STD_LOGIC;
RX_Empty : in STD_LOGIC;
Data_Read : out STD_LOGIC;
ACK_out : in STD_LOGIC;
TX_RDY : in STD_LOGIC;
Valid_D : out STD_LOGIC;
TX_Data : out STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Write_en : out STD_LOGIC;
OE : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
Send_comm : in STD_LOGIC;
READY : out STD_LOGIC;
FF_Count : in STD_LOGIC_VECTOR(5 downto 0));
end DMA;
architecture Behavioral of DMA is
type State is
(Idle, Tx, Wait_Buses, Rx);
signal current_state, next_state : State;
signal end_reception : STD_LOGIC;
signal begin_tx : STD_LOGIC;
component data_counter
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(2 downto 0));
end component;
signal reset_counter : STD_LOGIC;
signal enable_counter : STD_LOGIC;
signal count : STD_LOGIC_VECTOR (2 downto 0);
begin
-- Contador de bytes a transmitir o recibir
BitCounter: data_counter
port map (
clk => Clk,
reset => reset_counter,
enable => enable_counter,
count => count);
clock : process (Reset, Clk)
begin
if Reset = '0' then
current_state <= Idle;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
changes : process (clk, current_state, RX_Empty, Send_comm, DMA_ACK, end_reception, begin_tx, FF_Count)
begin
case current_state is
when Idle =>
-- Cuando hay tres bytes en la fifo, tomamos los buses y los guardamos en la ram
if FF_Count = "000011" then
next_state <= Wait_Buses;
elsif Send_comm = '1' then
next_state <= Tx;
else
next_state <= Idle;
end if;
-- Reception --
when Wait_Buses =>
if DMA_ACK = '1' then
next_state <= Rx;
else
next_state <= Wait_Buses;
end if;
when Rx =>
if DMA_ACK = '0' then
next_state <= Idle;
else
next_state <= Rx;
end if;
-- Transmission --
when Tx =>
if Send_comm = '0' then
next_state <= Idle;
else
next_State <= Tx;
end if;
end case;
end process;
outputs : process (current_state, RCVD_Data, Databus, Send_comm, count)
begin
Data_Read <= '0';
Valid_D <= '1';
Address <= (others => 'Z');
Databus <= (others => 'Z');
TX_Data <= (others => '0');
Write_en <= 'Z';
OE <= 'Z';
READY <= '1';
enable_counter <= '0';
reset_counter <= '1';
case current_state is
-- Reception --
when Idle =>
DMA_RQ <= '0';
if Send_comm = '1' then
READY <= not Send_comm;
end if;
when Wait_Buses =>
DMA_RQ <= '1';
when Rx =>
Databus <= RCVD_Data;
enable_counter <= '1';
reset_counter <= '0';
case count is
when "000" =>
Data_Read <= '1';
when "001" =>
Address <= DMA_RX_BUFFER_MSB;
DMA_RQ <= '1';
Data_Read <= '1';
Write_en <= '1';
when "010" =>
Address <= DMA_RX_BUFFER_MID;
DMA_RQ <= '1';
Data_Read <= '1';
Write_en <= '1';
when "011" =>
Address <= DMA_RX_BUFFER_LSB;
DMA_RQ <= '0';
Data_Read <= '1';
Write_en <= '1';
when others =>
enable_counter <= '0';
DMA_RQ <= '0';
end case;
--Transmission --
when Tx =>
Valid_D <= '0';
OE <= '0';
enable_counter <= '1';
reset_counter <= '0';
DMA_RQ <= '0';
case count is
when "000" =>
TX_Data <= Databus;
Address <= DMA_TX_BUFFER_MSB;
READY <= not Send_comm;
when "001" =>
TX_Data <= Databus;
Address <= DMA_TX_BUFFER_LSB;
READY <= '1';
when others =>
enable_counter <= '0';
end case;
when others =>
Data_Read <= '0';
Valid_D <= '1';
Address <= (others => 'Z');
Databus <= (others => 'Z');
TX_Data <= (others => '0');
Write_en <= 'Z';
OE <= 'Z';
DMA_RQ <= '0';
READY <= '1';
enable_counter <= '0';
reset_counter <= '1';
end case;
end process;
end Behavioral;
|
mit
|
9f3ebca4a16b427efe94e7c95198137b
| 0.512028 | 3.184443 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/tb_Comunicador.vhd
| 1 | 3,788 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:51:33 11/29/2016
-- Design Name:
-- Module Name: C:/Users/dsed12/Desktop/DSED/Practica 3/PIC/tb_Comunicador.vhd
-- Project Name: PIC
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Comunicador
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
LIBRARY RS232_test;
USE RS232_test.RS232_test.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_Comunicador IS
END tb_Comunicador;
ARCHITECTURE behavior OF tb_Comunicador IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Comunicador
PORT(
Reset : IN std_logic;
Clk : IN std_logic;
RS232_RX : IN std_logic;
RS232_TX : OUT std_logic;
SEND : IN std_logic;
DMA_ACK : IN std_logic;
READY : OUT std_logic;
DMA_RQ : OUT std_logic;
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_H : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal Reset : std_logic := '0';
signal Clk : std_logic := '0';
signal RS232_RX : std_logic := '0';
signal SEND : std_logic := '0';
signal DMA_ACK : std_logic := '0';
--Outputs
signal RS232_TX : std_logic;
signal READY : std_logic;
signal DMA_RQ : std_logic;
signal Switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
-- Clock period definitions
constant Clk_period : time := 50 ns;
-- Recepcion
signal data_rx: std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Comunicador PORT MAP (
Reset => Reset,
Clk => Clk,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX,
SEND => SEND,
DMA_ACK => DMA_ACK,
READY => READY,
DMA_RQ => DMA_RQ,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
Recepcion: process
begin
Reset <= '0', '1' after 100 ns;
RS232_RX <= '1';
-- wait for 40 us;
-- Transmit(RS232_RX, X"49");
-- wait for 40 us;
-- Transmit(RS232_RX, X"34");
-- wait for 40 us;
-- Transmit(RS232_RX, X"31");
wait;
end process;
Transmision: process
begin
SEND <= '0', '1' after 200 ns, '0' after 550 ns;
data_rx <= (others => '0');
Receive(RS232_TX, data_rx);
Receive(RS232_TX, data_rx);
wait;
end process;
DMA_ACK <= '1' when DMA_RQ = '1' else
'0' when DMA_RQ = '0';
--SEND <= '0' when READY = '1';
END;
|
mit
|
73996d8381b1a429568f3f1b6557fec8
| 0.558606 | 3.43427 | false | true | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_mapper_bits_symbols.vhd
| 1 | 5,024 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_mapper_bits_symbols
---- Version: 1.0.0
---- Description:
---- Map input bits to complex I&Q symbols depending on modulation type
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx bits to symbols mapper inputs and outputs
--=============================================================================
entity ccsds_tx_mapper_bits_symbols is
generic(
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer := 1; -- For QAM - 1 bit/symbol <=> QPSK/4-QAM - 2 bits/symbol <=> 16-QAM - 3 bits/symbol <=> 64-QAM - ... - N bits/symbol <=> 2^(N*2)-QAM
constant CCSDS_TX_MAPPER_GRAY_CODER: std_logic := '1'; -- Gray coder activation
constant CCSDS_TX_MAPPER_MODULATION_TYPE: integer := 1; -- 1=QPSK/QAM - 2=BPSK
constant CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_MAPPER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
sym_val_o: out std_logic;
sym_i_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_q_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0)
);
end ccsds_tx_mapper_bits_symbols;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_mapper_bits_symbols is
-- internal constants
constant MAPPER_SYMBOL_NUMBER_PER_CHANNEL: integer := CCSDS_TX_MAPPER_DATA_BUS_SIZE*CCSDS_TX_MAPPER_MODULATION_TYPE/(2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKMAPPERP0 : if (CCSDS_TX_MAPPER_DATA_BUS_SIZE mod (CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2*CCSDS_TX_MAPPER_MODULATION_TYPE) /= 0) generate
process
begin
report "ERROR: DATA BUS SIZE HAS TO BE A MULTIPLE OF 2*BITS PER SYMBOLS (EXCEPT FOR BPSK MODULATION)" severity failure;
wait;
end process;
end generate CHKMAPPERP0;
CHKMAPPERP1: if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL /= 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) generate
process
begin
report "ERROR: BPSK MODULATION REQUIRES 1 BIT PER SYMBOL" severity failure;
wait;
end process;
end generate CHKMAPPERP1;
CHKMAPPERP2 : if (CCSDS_TX_MAPPER_MODULATION_TYPE /= 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE /= 2) generate
process
begin
report "ERROR: UNKNOWN MODULATION TYPE - 1=QPSK/QAM / 2=BPSK" severity failure;
wait;
end process;
end generate CHKMAPPERP2;
-- internal processing
--=============================================================================
-- Begin of mapperp
-- Map bits to symbols
--=============================================================================
-- read: rst_i, dat_i, dat_val_i
-- write: sym_i_o, sym_q_o, sym_val_o
-- r/w:
MAPPERP: process (clk_i)
variable symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sym_i_o <= (others => '0');
sym_q_o <= (others => '0');
symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
sym_val_o <= '0';
else
if (dat_val_i = '1') then
sym_val_o <= '1';
-- BPSK mapping
if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
sym_q_o(0) <= '0';
sym_i_o(0) <= dat_i(symbol_counter-1);
-- QPSK/QAM mapping
else
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
if (symbol_counter = 1) then
symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
else
symbol_counter := symbol_counter - 1;
end if;
else
sym_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
mit
|
e5868b40db500977fe5528790e31f87b
| 0.55215 | 3.86759 | false | false | false | false |
jpendlum/crash
|
fpga/src/common/synchronizer_slv.vhd
| 2 | 4,207 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: synchronizer_slv.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Sychronizer to cross clock domains using two registers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer_slv is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic_vector := "0"); -- Can either set everything to the same value or individualize each bit
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic_vector; -- Asynchronous input
sync : out std_logic_vector); -- Synchronized output
end entity;
architecture RTL of synchronizer_slv is
component synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end component;
begin
-- The default outputs are all the same
gen_same_default_output : if RESET_OUTPUT'length = 1 generate
gen_synchronizers : for i in 0 to async'length-1 generate
inst_synchronizer : synchronizer
generic map (
STROBE_EDGE => STROBE_EDGE,
RESET_OUTPUT => RESET_OUTPUT(0))
port map (
clk => clk,
reset => reset,
async => async(i),
sync => sync(i));
end generate;
end generate;
-- The outputs are individualized and async was declared using 'downto' orientation.
-- This kludge is necessary (as far as I know), because I could not think of another
-- way to deal with the fact that RESET_OUTPUT and async could have different
-- orientations, i.e. '0 to n' vs 'n downto 0'.
gen_individualized_default_output : if ((RESET_OUTPUT'length /= 1) AND (RESET_OUTPUT'left = async'left)) generate
gen_synchronizers : for i in 0 to async'length-1 generate
inst_synchronizer : synchronizer
generic map (
STROBE_EDGE => STROBE_EDGE,
RESET_OUTPUT => RESET_OUTPUT(i))
port map (
clk => clk,
reset => reset,
async => async(i),
sync => sync(i));
end generate;
end generate;
gen_individualized_default_output_inverted : if ((RESET_OUTPUT'length /= 1) AND (RESET_OUTPUT'left /= async'left)) generate
gen_synchronizers : for i in 0 to async'length-1 generate
inst_synchronizer : synchronizer
generic map (
STROBE_EDGE => STROBE_EDGE,
RESET_OUTPUT => RESET_OUTPUT(async'length-1-i))
port map (
clk => clk,
reset => reset,
async => async(i),
sync => sync(i));
end generate;
end generate;
end RTL;
|
gpl-3.0
|
5ed86cd2a8af32aea313890a3aebdeeb
| 0.535536 | 4.423764 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
logic_32_bit.vhd
| 1 | 1,401 |
-- 32-bit logical operation circuit
-- this circuit performs various different logical operations on one or two operands
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity logic_32_bit is
port (
-- inputs
a_32 : in std_logic_vector(31 downto 0);
b_32 : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(1 downto 0);
enable : in std_logic;
--outputs
result_32 : out std_logic_vector(31 downto 0)
);
end entity logic_32_bit;
architecture logic_32_bit_arch of logic_32_bit is
-- this circuit doesn't require any internal signals
begin
logic : process(enable, opcode, a_32, b_32)
begin
-- if logic block has been enabled
if enable = '1' then
-- opcode 00 is logical OR
if opcode = "00" then
result_32 <= a_32 or b_32;
-- opcode 01 is logical AND
elsif opcode = "01" then
result_32 <= a_32 and b_32;
-- opcode 10 is logical XOR
elsif opcode = "10" then
result_32 <= a_32 xor b_32;
-- opcode 11 is logical NOT of A (B is ignored)
elsif opcode = "11" then
result_32 <= not a_32;
-- otherwise invalid opcode, output is 0
else
result_32 <= (others => '0');
end if;
-- otherwise logic block disabled, output is 0
else
result_32 <= (others => '0');
end if;
end process logic;
end architecture logic_32_bit_arch;
|
mit
|
331f434e38dcd9eb048ec6c26a3e6503
| 0.657388 | 3 | false | false | false | false |
ziyan/altera-de2-ann
|
src/de2.vhd
| 1 | 12,160 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE work.float_types.all;
USE work.float_components.all;
USE work.float_constants.all;
USE work.sram_types.all;
USE work.sram_components.all;
USE work.lfsr_components.all;
USE work.ann_types.all;
USE work.ann_components.all;
USE work.pr_types.all;
USE work.pr_components.all;
USE work.display_types.all;
USE work.display_components.all;
USE work.lcd_types.all;
USE work.lcd_components.all;
USE work.pattern_constants.all;
ENTITY de2 IS
PORT (
-------------------- Clock Input --------------------
CLOCK_27 : IN STD_LOGIC; -- On Board 27 MHz
CLOCK_50 : IN STD_LOGIC; -- On Board 50 MHz
EXT_CLOCK : IN STD_LOGIC; -- External Clock
-------------------- Push Button --------------------
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Pushbutton[3:0]
-------------------- DPDT Switch --------------------
SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); -- Toggle Switch[17:0]
-------------------- 7-SEG Dispaly --------------------
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 0
HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 1
HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 2
HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 3
HEX4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 4
HEX5 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 5
HEX6 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 6
HEX7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- Seven Segment Digit 7
------------------------ LED ------------------------
LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); -- LED Green[8:0]
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- LED Red[17:0]
------------------------ UART ------------------------
UART_TXD : OUT STD_LOGIC; -- UART Transmitter
UART_RXD : IN STD_LOGIC; -- UART Receiver
------------------------ IRDA ------------------------
IRDA_TXD : OUT STD_LOGIC; -- IRDA Transmitter
IRDA_RXD : IN STD_LOGIC; -- IRDA Receiver
--------------------/ SDRAM Interface ----------------
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SDRAM Data bus 16 Bits
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- SDRAM Address bus 12 Bits
DRAM_LDQM : OUT STD_LOGIC; -- SDRAM Low-byte Data Mask
DRAM_UDQM : OUT STD_LOGIC; -- SDRAM High-byte Data Mask
DRAM_WE_N : OUT STD_LOGIC; -- SDRAM Write Enable
DRAM_CAS_N : OUT STD_LOGIC; -- SDRAM Column Address Strobe
DRAM_RAS_N : OUT STD_LOGIC; -- SDRAM Row Address Strobe
DRAM_CS_N : OUT STD_LOGIC; -- SDRAM Chip Select
DRAM_BA_0 : OUT STD_LOGIC; -- SDRAM Bank Address 0
DRAM_BA_1 : OUT STD_LOGIC; -- SDRAM Bank Address 1
DRAM_CLK : OUT STD_LOGIC; -- SDRAM Clock
DRAM_CKE : OUT STD_LOGIC; -- SDRAM Clock Enable
-------------------- Flash Interface ----------------
FL_DQ : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- FLASH Data bus 8 Bits
FL_ADDR : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); -- FLASH Address bus 20 Bits
FL_WE_N : OUT STD_LOGIC; -- FLASH Write Enable
FL_RST_N : OUT STD_LOGIC; -- FLASH Reset
FL_OE_N : OUT STD_LOGIC; -- FLASH Output Enable
FL_CE_N : OUT STD_LOGIC; -- FLASH Chip Enable
-------------------- SRAM Interface ----------------
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SRAM Data bus 16 Bits
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- SRAM Address bus 18 Bits
SRAM_UB_N : OUT STD_LOGIC; -- SRAM High-byte Data Mask
SRAM_LB_N : OUT STD_LOGIC; -- SRAM Low-byte Data Mask
SRAM_WE_N : OUT STD_LOGIC; -- SRAM Write Enable
SRAM_CE_N : OUT STD_LOGIC; -- SRAM Chip Enable
SRAM_OE_N : OUT STD_LOGIC; -- SRAM Output Enable
-------------------- ISP1362 Interface ----------------
OTG_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- ISP1362 Data bus 16 Bits
OTG_ADDR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- ISP1362 Address 2 Bits
OTG_CS_N : OUT STD_LOGIC; -- ISP1362 Chip Select
OTG_RD_N : OUT STD_LOGIC; -- ISP1362 Write
OTG_WR_N : OUT STD_LOGIC; -- ISP1362 Read
OTG_RST_N : OUT STD_LOGIC; -- ISP1362 Reset
OTG_FSPEED : OUT STD_LOGIC; -- USB Full Speed; 0 = Enable; Z = Disable
OTG_LSPEED : OUT STD_LOGIC; -- USB Low Speed; 0 = Enable; Z = Disable
OTG_INT0 : IN STD_LOGIC; -- ISP1362 Interrupt 0
OTG_INT1 : IN STD_LOGIC; -- ISP1362 Interrupt 1
OTG_DREQ0 : IN STD_LOGIC; -- ISP1362 DMA Request 0
OTG_DREQ1 : IN STD_LOGIC; -- ISP1362 DMA Request 1
OTG_DACK0_N : OUT STD_LOGIC; -- ISP1362 DMA Acknowledge 0
OTG_DACK1_N : OUT STD_LOGIC; -- ISP1362 DMA Acknowledge 1
-------------------- LCD Module 16X2 ----------------
LCD_ON : OUT STD_LOGIC; -- LCD Power ON/OFF
LCD_BLON : OUT STD_LOGIC; -- LCD Back Light ON/OFF
LCD_RW : OUT STD_LOGIC; -- LCD Read/Write Select; 0 = Write; 1 = Read
LCD_EN : OUT STD_LOGIC; -- LCD Enable
LCD_RS : OUT STD_LOGIC; -- LCD Command/Data Select; 0 = Command; 1 = Data
LCD_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- LCD Data bus 8 bits
-------------------- SD_Card Interface ----------------
SD_DAT : INOUT STD_LOGIC; -- SD Card Data
SD_DAT3 : INOUT STD_LOGIC; -- SD Card Data 3
SD_CMD : INOUT STD_LOGIC; -- SD Card Command Signal
SD_CLK : OUT STD_LOGIC; -- SD Card Clock
-------------------- USB JTAG link --------------------
TDI : IN STD_LOGIC; -- CPLD -> FPGA (Data in)
TCK : IN STD_LOGIC; -- CPLD -> FPGA (Clock)
TCS : IN STD_LOGIC; -- CPLD -> FPGA (CS)
TDO : OUT STD_LOGIC; -- FPGA -> CPLD (Data out)
-------------------- I2C ----------------------------
I2C_SDAT : INOUT STD_LOGIC; -- I2C Data
I2C_SCLK : OUT STD_LOGIC; -- I2C Clock
-------------------- PS2 ----------------------------
PS2_DAT : IN STD_LOGIC; -- PS2 Data
PS2_CLK : IN STD_LOGIC; -- PS2 Clock
-------------------- VGA ----------------------------
VGA_CLK : OUT STD_LOGIC; -- VGA Clock
VGA_HS : OUT STD_LOGIC; -- VGA H_SYNC
VGA_VS : OUT STD_LOGIC; -- VGA V_SYNC
VGA_BLANK : OUT STD_LOGIC; -- VGA BLANK
VGA_SYNC : OUT STD_LOGIC; -- VGA SYNC
VGA_R : OUT STD_LOGIC_VECTOR(9 downto 0); -- VGA Red[9:0]
VGA_G : OUT STD_LOGIC_VECTOR(9 downto 0); -- VGA Green[9:0]
VGA_B : OUT STD_LOGIC_VECTOR(9 downto 0); -- VGA Blue[9:0]
------------ Ethernet Interface ------------------------
ENET_DATA : INOUT STD_LOGIC_VECTOR(15 downto 0);-- DM9000A DATA bus 16Bits
ENET_CMD : OUT STD_LOGIC; -- DM9000A Command/Data Select; 0 = Command; 1 = Data
ENET_CS_N : OUT STD_LOGIC; -- DM9000A Chip Select
ENET_WR_N : OUT STD_LOGIC; -- DM9000A Write
ENET_RD_N : OUT STD_LOGIC; -- DM9000A Read
ENET_RST_N : OUT STD_LOGIC; -- DM9000A Reset
ENET_INT : IN STD_LOGIC; -- DM9000A Interrupt
ENET_CLK : OUT STD_LOGIC; -- DM9000A Clock 25 MHz
---------------- Audio CODEC ------------------------
AUD_ADCLRCK : INOUT STD_LOGIC; -- Audio CODEC ADC LR Clock
AUD_ADCDAT : IN STD_LOGIC; -- Audio CODEC ADC Data
AUD_DACLRCK : INOUT STD_LOGIC; -- Audio CODEC DAC LR Clock
AUD_DACDAT : OUT STD_LOGIC; -- Audio CODEC DAC Data
AUD_BCLK : INOUT STD_LOGIC; -- Audio CODEC Bit-Stream Clock
AUD_XCK : OUT STD_LOGIC; -- Audio CODEC Chip Clock
---------------- TV Decoder ------------------------
TD_DATA : IN STD_LOGIC_VECTOR(7 downto 0); -- TV Decoder Data bus 8 bits
TD_HS : IN STD_LOGIC; -- TV Decoder H_SYNC
TD_VS : IN STD_LOGIC; -- TV Decoder V_SYNC
TD_RESET : OUT STD_LOGIC; -- TV Decoder Reset
-------------------- GPIO ----------------------------
GPIO_0 : INOUT STD_LOGIC_VECTOR(35 downto 0); -- GPIO Connection 0
GPIO_1 : INOUT STD_LOGIC_VECTOR(35 downto 0) -- GPIO Connection 1
);
END ENTITY de2;
ARCHITECTURE de2 OF de2 IS
constant PATTERN_SIZE : integer := PATTERN_SIZE;
constant PATTERN_CLASS_COUNT : integer := PATTERN_CLASS_COUNT;
constant PATTERN_TRAINING_COUNT : integer := PATTERN_TRAINING_COUNT;
-- pattern recognizer
signal pr_ready : std_logic := '0';
signal pr_inputs : std_logic_vector(PATTERN_SIZE - 1 downto 0) := (others => '0');
signal pr_output : integer := 0;
signal pr_training_mse : float := float_half;
signal pr_training_mse_sel : std_logic_vector(1 downto 0) := "00";
-- ann
signal ann_alpha : float := float_one;
signal ann_inputs : float_vector(PATTERN_SIZE - 1 downto 0) := (others => float_zero);
signal ann_outputs : float_vector(PATTERN_CLASS_COUNT - 1 downto 0) := (others => float_zero);
signal ann_targets : float_vector(PATTERN_CLASS_COUNT - 1 downto 0) := (others => float_zero);
signal ann_ready : std_logic := '0';
signal ann_mse : float := float_zero;
signal ann_mode : ann_mode := idle;
-- alu
SIGNAL float_alu_ready : STD_LOGIC := '0';
SIGNAL float_alu_a, float_alu_b, float_alu_c : float := float_zero;
SIGNAL float_alu_mode : float_alu_mode := idle;
-- sram
signal sram_address : sram_address := (others=>'0');
signal sram_input : sram_data := (others=>'0');
signal sram_output : sram_data := (others=>'0');
signal sram_mode : sram_mode := read;
signal sram_ready : std_logic := '0';
-- lfsr
signal lfsr_output : std_logic_vector(15 downto 0) := (others=>'0');
-- lcd
signal lcd_dd : CHAR_VECTOR(0 to 31) := (others => x"00");
signal lcd_cg : CHAR_GRAPHICS_VECTOR(0 to 7) := (others => (others => '0'));
-- display
signal display_mode : display_mode := training;
signal display_mode_sel : STD_LOGIC_VECTOR(2 downto 0) := "000";
BEGIN
-- alu
float_alu0 : float_alu
port map (
NOT KEY(0),
CLOCK_50,
float_alu_a,
float_alu_b,
float_alu_c,
float_alu_mode,
float_alu_ready
);
-- SRAM
sram0 : sram
port map (
NOT KEY(0),
CLOCK_50,
sram_address,
sram_input,
sram_output,
sram_mode,
sram_ready,
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N
);
-- LFSR
lfsr0 : lfsr
port map(
NOT KEY(0),
CLOCK_50,
lfsr_output
);
-- ann
ann0 : ann
generic map (
PATTERN_SIZE,
PATTERN_SIZE + PATTERN_CLASS_COUNT,
PATTERN_CLASS_COUNT
)
port map (
NOT KEY(0) OR NOT KEY(1),
CLOCK_50,
ann_mode,
ann_alpha,
ann_inputs,
ann_targets,
ann_outputs,
ann_mse,
ann_ready,
float_alu_a,
float_alu_b,
float_alu_c,
float_alu_mode,
float_alu_ready,
sram_address,
sram_input,
sram_output,
sram_mode,
sram_ready,
lfsr_output
);
-- pr
pr0 : pr
generic map (
PATTERN_SIZE,
PATTERN_CLASS_COUNT,
PATTERN_TRAINING_COUNT
)
port map (
NOT KEY(0) OR NOT KEY(1),
CLOCK_50,
NOT KEY(3),
PATTERN_TRAINING_DATA,
PATTERN_TRAINING_CLASS,
pr_training_mse,
pr_inputs,
pr_output,
pr_ready,
ann_mode,
ann_alpha,
ann_inputs,
ann_targets,
ann_outputs,
ann_mse,
ann_ready,
lfsr_output
);
-- lcd
lcd0 : lcd
port map (
NOT KEY(0),
CLOCK_50,
lcd_dd,
lcd_cg,
LCD_ON,
LCD_BLON,
LCD_RW,
LCD_EN,
LCD_RS,
LCD_DATA
);
-- display
display0 : display
port map (
NOT KEY(0),
CLOCK_50,
display_mode,
pr_inputs,
PATTERN_DISPLAY(pr_output),
lcd_dd,
lcd_cg
);
-- display mode select
display_mode_sel <= pr_ready & ann_ready & not KEY(3);
with display_mode_sel select
display_mode <=
training when "000"|"001"|"010"|"011",
running when "100"|"101"|"111",
idle when "110";
-- pattern input
pr_inputs <= SW(17 downto 2);
-- bist indicator
LEDG(8) <= pr_ready;
-- mean squared error display
LEDR <= ann_mse(31 downto 14);
-- training accuracy select
pr_training_mse_sel <= SW(1 downto 0);
with pr_training_mse_sel select
pr_training_mse <=
float_half when "00",
float_1_10 when "01",
float_1_20 when "10",
float_1_100 when "11";
-- output class display
LEDG(7 downto 0) <= std_logic_vector(to_unsigned(pr_output, 8));
-- power off the 7 segment displays
HEX0 <= (others => '1');
HEX1 <= (others => '1');
HEX2 <= (others => '1');
HEX3 <= (others => '1');
HEX4 <= (others => '1');
HEX5 <= (others => '1');
HEX6 <= (others => '1');
HEX7 <= (others => '1');
END ARCHITECTURE de2;
|
mit
|
4a06f6044d1818bad1e188dbd0f46c3d
| 0.588322 | 2.88699 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/Comunicador.vhd
| 1 | 5,389 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:47:20 11/29/2016
-- Design Name:
-- Module Name: Comunicador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.PIC_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comunicador is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
RS232_RX : in STD_LOGIC;
RS232_TX : out STD_LOGIC;
SEND : in STD_LOGIC;
DMA_ACK : in STD_LOGIC;
READY : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
Switches : out STD_LOGIC_VECTOR (7 downto 0);
Temp_L : out STD_LOGIC_VECTOR (6 downto 0);
Temp_H : out STD_LOGIC_VECTOR (6 downto 0));
end Comunicador;
architecture Behavioral of Comunicador is
-----------------------------------------------------------------------------------
-- Módulos de comunicación
-----------------------------------------------------------------------------------
component RS232top
port (
Reset : in std_logic;
Clk : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Valid_D : in std_logic;
Ack_in : out std_logic;
TX_RDY : out std_logic;
TD : out std_logic;
RD : in std_logic;
Data_out : out std_logic_vector(7 downto 0);
Data_read : in std_logic;
Full : out std_logic;
Empty : out std_logic;
FF_Count : out std_logic_vector(5 downto 0));
end component;
component DMA
Port (
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
RCVD_Data : in STD_LOGIC_VECTOR (7 downto 0);
RX_Full : in STD_LOGIC;
RX_Empty : in STD_LOGIC;
Data_Read : out STD_LOGIC;
ACK_out : in STD_LOGIC;
TX_RDY : in STD_LOGIC;
Valid_D : out STD_LOGIC;
TX_Data : out STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Write_en : out STD_LOGIC;
OE : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
Send_comm : in STD_LOGIC;
READY : out STD_LOGIC;
FF_Count : in std_logic_vector(5 downto 0));
end component;
-------------------------------------------------------------------------------
-- Memoria RAM
-------------------------------------------------------------------------------
component ram
PORT (
Clk : in std_logic;
Reset : in std_logic;
write_en : in std_logic;
oe : in std_logic;
address : in std_logic_vector(7 downto 0);
databus : inout std_logic_vector(7 downto 0);
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
END component;
---------------------------------------------------------------------
-- Señales internas
---------------------------------------------------------------------
signal Valid_D : STD_LOGIC;
signal Ack_out : STD_LOGIC;
signal TX_RDY : STD_LOGIC;
signal Data_Read : STD_LOGIC;
signal RX_Full : STD_LOGIC;
signal RX_Empty : STD_LOGIC;
signal Write_en : STD_LOGIC;
signal OE : STD_LOGIC;
signal TX_Data : STD_LOGIC_VECTOR (7 downto 0);
signal Address : STD_LOGIC_VECTOR (7 downto 0);
signal Databus : STD_LOGIC_VECTOR (7 downto 0);
signal RCVD_Data : STD_LOGIC_VECTOR (7 downto 0);
signal fifo_count : STD_LOGIC_VECTOR (5 downto 0);
begin -- behavior
RS232_PHY: RS232top
port map (
Reset => Reset,
Clk => Clk,
Data_in => TX_Data,
Valid_D => Valid_D,
Ack_in => Ack_out,
TX_RDY => TX_RDY,
TD => RS232_TX,
RD => RS232_RX,
Data_out => RCVD_Data,
Data_read => Data_Read,
Full => RX_Full,
Empty => RX_Empty,
FF_Count => fifo_count);
DMA_Unit: DMA
port map (
Reset => Reset,
Clk => Clk,
RCVD_Data => RCVD_Data,
RX_Full => RX_Full,
RX_Empty => RX_Empty,
Data_Read => Data_Read,
ACK_out => ACK_out,
TX_RDY => TX_RDY,
Valid_D => Valid_D,
TX_Data => TX_Data,
Address => Address,
Databus => Databus,
Write_en => Write_en,
OE => OE,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
Send_comm => SEND,
READY => READY,
FF_Count => fifo_count);
RAM_Unit: RAM
port map (
Clk => Clk,
Reset => Reset,
write_en => Write_en,
oe => OE,
address => Address,
databus => Databus,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H);
end behavioral;
|
mit
|
66a8c8256ed78d74304ae2398b6f0d45
| 0.48766 | 3.256193 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_synchronizer.vhd
| 1 | 3,314 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_synchronizer
---- Version: 1.0.0
---- Description:
---- Add an Attached Synchronization Marker to an input frame
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx synchronizer inputs and outputs
--=============================================================================
entity ccsds_tx_synchronizer is
generic(
constant CCSDS_TX_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_ASM_PATTERN: std_logic_vector := "00011010110011111111110000011101"; -- ASM Pattern used
constant CCSDS_TX_ASM_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_synchronizer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_synchronizer is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKSYNCHRONIZERP0 : if ((CCSDS_TX_ASM_LENGTH*8) /= CCSDS_TX_ASM_PATTERN'length) generate
process
begin
report "ERROR: SYNCHRONIZER ASM LENGTH IS DIFFERENT FROM PATTERN SIZE" severity failure;
wait;
end process;
end generate CHKSYNCHRONIZERP0;
-- internal processing
--=============================================================================
-- Begin of asmp
-- Apped ASM sequence to frame
--=============================================================================
-- read: rst_i, dat_val_i, dat_i
-- write: dat_o, dat_val_o
-- r/w:
ASMP: process (clk_i)
variable data_synchronized: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
data_synchronized := '0';
dat_val_o <= '0';
else
if (dat_val_i = '1') then
dat_o(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto CCSDS_TX_ASM_DATA_BUS_SIZE) <= CCSDS_TX_ASM_PATTERN;
dat_o(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0) <= dat_i;
data_synchronized := '1';
dat_val_o <= '1';
else
dat_val_o <= '0';
if (data_synchronized = '0') then
dat_o <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end structure;
|
mit
|
d197eda951b26d1b563ea02b14ae5fba
| 0.502716 | 4.315104 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_srrc.vhd
| 1 | 13,357 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_srrc
---- Version: 1.0.0
---- Description:
---- Squared Raised Root Cosine FIR filter (pipelined systolic symetric architecture)
---- Input: 1 clk / sam_val_i <= '1' / sam_i <= "SAMPLESDATATOBEFILTERED"
---- Timing requirements: 1 clock cycle for valid output sample / delay = (6*CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO+1) / impulse response time = (6*CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO*2+1)
---- Output: sam_val_o <= "1" / sam_o <= "FILTEREDSAMPLES"
---- Ressources requirements: pipelined samples registers + fir coefficients registers + input adders registers + output adders registers + multipliers registers = ((FilterCoefficientsNumber - 1) * 2 + 1) * QuantizationDepth + FilterCoefficientsNumber * QuantizationDepth + FilterCoefficientsNumber * (QuantizationDepth + 1) + (2 * FilterCoefficientsNumber) * (QuantizationDepth * 2 + 1) registers
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- Filter impulse response - SRRC(t):
-- t = 0 => SRRC(0) = (1-B + 4*B/PI)
-- t = +/-Ts/(4*B) => SRRC(+/-Ts/(4*B)) = (B/racine(2) * (1+2/PI) * sin(PI/(4*B)) + (1-2/PI) * cos(PI/(4*B)))
-- t /= 0 and t /= Ts/(4*B) => SRRC(t) = (sin(PI.t.(1-B)/Ts) + 4.B.t.cos(PI.t.(1+B)/Ts)/Ts) / (PI.t.(1-((4.B.t)/Ts)^2)/Ts)
-- t: time
-- Ts: symbol period
-- B: filter roll-off
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary rxtx srrc inputs and outputs
--=============================================================================
entity ccsds_rxtx_srrc is
generic(
constant CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE: integer range 0 to 2 := 1; -- 0=Dirichlet (Rectangular) / 1=Hamming / 2=Bartlett (Triangular)
constant CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO: integer;
constant CCSDS_RXTX_SRRC_ROLL_OFF: real := 0.5;
constant CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH: integer
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
-- outputs
sam_o: out std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end ccsds_rxtx_srrc;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_rxtx_srrc is
-- internal constants
constant CCSDS_RXTX_SRRC_RESPONSE_SYMBOL_CYCLES: integer:= 6; -- in symbol Time
constant CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER: integer := CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO*CCSDS_RXTX_SRRC_RESPONSE_SYMBOL_CYCLES+1;
constant CCSDS_RXTX_SRRC_SAMPLES_NUMBER: integer := (CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1)*2+1;
constant CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_T0: real := (1.0 - CCSDS_RXTX_SRRC_ROLL_OFF + 4.0 * CCSDS_RXTX_SRRC_ROLL_OFF / MATH_PI);
constant CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_TS: real := (CCSDS_RXTX_SRRC_ROLL_OFF / sqrt(2.0) * (1.0 + 2.0 / MATH_PI) * sin (MATH_PI / (4.0 * CCSDS_RXTX_SRRC_ROLL_OFF)) + (1.0 - 2.0 / MATH_PI) * cos (MATH_PI / (4.0 * CCSDS_RXTX_SRRC_ROLL_OFF)));
constant CCSDS_RXTX_SRRC_NORMALIZATION_GAIN: real := (2.0**(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH - 1) - 1.0) / CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_T0; -- Exact value should be FIR coefficients RMS Gain / T0 Gain = Sqrt(Sum(Pow(coef,2)))) * Full Scale Value
constant CCSDS_RXTX_SRRC_SIG_IN_ADD_SIZE: integer := CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH+1;
constant CCSDS_RXTX_SRRC_SIG_MUL_SIZE: integer := CCSDS_RXTX_SRRC_SIG_IN_ADD_SIZE+CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH;
constant CCSDS_RXTX_SRRC_SIG_OUT_ADD_SIZE: integer := CCSDS_RXTX_SRRC_SIG_MUL_SIZE;
-- internal variable signals
type samples_array is array(CCSDS_RXTX_SRRC_SAMPLES_NUMBER-1 downto 0) of signed(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
type srrc_tap_array is array(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1 downto 0) of signed(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
type srrc_multiplier_array is array(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1 downto 0) of signed(CCSDS_RXTX_SRRC_SIG_MUL_SIZE-1 downto 0);
type srrc_input_adder_array is array(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1 downto 0) of signed(CCSDS_RXTX_SRRC_SIG_IN_ADD_SIZE-1 downto 0);
type srrc_output_adder_array is array(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1 downto 0) of signed(CCSDS_RXTX_SRRC_SIG_OUT_ADD_SIZE-1 downto 0);
signal sam_i_pipeline_registers: samples_array := (others => (others => '0'));
signal srrc_coefficients: srrc_tap_array;
signal srrc_multipliers_registers: srrc_multiplier_array := (others => (others => '0'));
signal srrc_input_adders_registers: srrc_input_adder_array := (others => (others => '0'));
signal srrc_output_adders_registers: srrc_output_adder_array := (others => (others => '0'));
-- components instanciation and mapping
begin
-- SRRC coefficients generation
-- At t = 0
srrc_coefficients(0) <= to_signed(integer(CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_T0),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
-- Coefficients are symetrical / they are computed only for positive time response
SRRC_COEFS_GENERATOR: for coefficient_counter in 1 to CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO*CCSDS_RXTX_SRRC_RESPONSE_SYMBOL_CYCLES generate
-- At t = Ts/(4*B)
SRRC_SPECIFIC_COEFS: if (real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO)/real(coefficient_counter) = 4.0*CCSDS_RXTX_SRRC_ROLL_OFF) generate
SRRC_COEFS_WINDOW_DIRICHLET: if (CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE = 0) generate
srrc_coefficients(coefficient_counter) <= to_signed(integer(CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_TS),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
end generate SRRC_COEFS_WINDOW_DIRICHLET;
SRRC_COEFS_WINDOW_HAMMING: if (CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE = 1) generate
srrc_coefficients(coefficient_counter) <= to_signed(integer((0.53836 + 0.46164 * cos(2.0 * MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1))) * CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_TS),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
end generate SRRC_COEFS_WINDOW_HAMMING;
SRRC_COEFS_WINDOW_BARTLETT: if (CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE = 2) generate
srrc_coefficients(0) <= to_signed(integer(CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_T0),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
srrc_coefficients(coefficient_counter) <= to_signed(integer((1.0 - abs((real(coefficient_counter) - real(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1)/2.0) / real(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1)/2.0)) * CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * CCSDS_RXTX_SRRC_SPECIFIC_COEFFICIENT_VALUE_TS),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
end generate SRRC_COEFS_WINDOW_BARTLETT;
end generate SRRC_SPECIFIC_COEFS;
-- At t > 0 and t /= Ts/(4*B)
SRRC_GENERIC_COEFS: if (real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO)/real(coefficient_counter) /= 4.0*CCSDS_RXTX_SRRC_ROLL_OFF) generate
SRRC_COEFS_WINDOW_DIRICHLET: if (CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE = 0) generate
srrc_coefficients(coefficient_counter) <= to_signed(integer(CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * (sin(MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 - CCSDS_RXTX_SRRC_ROLL_OFF)) + 4.0 * CCSDS_RXTX_SRRC_ROLL_OFF * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * cos(MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 + CCSDS_RXTX_SRRC_ROLL_OFF))) / (MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 - (4.0 * CCSDS_RXTX_SRRC_ROLL_OFF * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO))**2))),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
end generate SRRC_COEFS_WINDOW_DIRICHLET;
SRRC_COEFS_WINDOW_HAMMING: if (CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE = 1) generate
srrc_coefficients(coefficient_counter) <= to_signed(integer((0.53836 + 0.46164 * cos(2.0 * MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1))) * CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * (sin(MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 - CCSDS_RXTX_SRRC_ROLL_OFF)) + 4.0 * CCSDS_RXTX_SRRC_ROLL_OFF * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * cos(MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 + CCSDS_RXTX_SRRC_ROLL_OFF))) / (MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 - (4.0 * CCSDS_RXTX_SRRC_ROLL_OFF * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO))**2))),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
end generate SRRC_COEFS_WINDOW_HAMMING;
SRRC_COEFS_WINDOW_BARTLETT: if (CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE = 2) generate
srrc_coefficients(coefficient_counter) <= to_signed(integer((1.0 - abs((real(coefficient_counter) - real(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1)/2.0) / real(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1)/2.0)) * CCSDS_RXTX_SRRC_NORMALIZATION_GAIN * (sin(MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 - CCSDS_RXTX_SRRC_ROLL_OFF)) + 4.0 * CCSDS_RXTX_SRRC_ROLL_OFF * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * cos(MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 + CCSDS_RXTX_SRRC_ROLL_OFF))) / (MATH_PI * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO) * (1.0 - (4.0 * CCSDS_RXTX_SRRC_ROLL_OFF * real(coefficient_counter) / real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO))**2))),CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH);
end generate SRRC_COEFS_WINDOW_BARTLETT;
end generate SRRC_GENERIC_COEFS;
end generate SRRC_COEFS_GENERATOR;
-- presynthesis checks
CHKSRRCP0: if CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO mod 2 /= 0 generate
process
begin
report "ERROR: SRRC OVERSAMPLING RATIO MUST BE A MULTIPLE OF 2" severity failure;
wait;
end process;
end generate CHKSRRCP0;
CHKSRRCP1: if CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO = 0 generate
process
begin
report "ERROR: SRRC OVERSAMPLING RATIO CANNOT BE NULL" severity failure;
wait;
end process;
end generate CHKSRRCP1;
CHKSRRCP2: if (CCSDS_RXTX_SRRC_ROLL_OFF < 0.0) or (CCSDS_RXTX_SRRC_ROLL_OFF > 1.0) generate
process
begin
report "ERROR: SRRC ROLL OFF HAS TO BE BETWEEN 0.0 AND 1.0" severity failure;
wait;
end process;
end generate CHKSRRCP2;
-- internal processing
--=============================================================================
-- Begin of srrcp
-- FIR filter coefficients
--=============================================================================
-- read: rst_i, sam_val_i, sam_i
-- write: sam_o, sam_val_o
-- r/w: sam_i_memory, sam_i_pipeline_registers, srrc_adders_registers, srrc_multipliers_registers
SRRCP: process (clk_i)
variable srrc_zero_in: signed(CCSDS_RXTX_SRRC_SIG_IN_ADD_SIZE-1 downto 0) := (others => '0');
variable srrc_zero_out: signed(CCSDS_RXTX_SRRC_SIG_OUT_ADD_SIZE-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sam_o <= (others => '0');
sam_val_o <= '0';
else
if (sam_val_i = '1') then
sam_val_o <= '1';
sam_i_pipeline_registers(0) <= signed(sam_i);
sam_i_pipeline_registers(CCSDS_RXTX_SRRC_SAMPLES_NUMBER-1 downto 1) <= sam_i_pipeline_registers(CCSDS_RXTX_SRRC_SAMPLES_NUMBER-2 downto 0);
for i in 0 to CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1 loop
srrc_multipliers_registers(i) <= srrc_input_adders_registers(i) * srrc_coefficients(i);
if (i = 0) then
srrc_input_adders_registers(i) <= sam_i_pipeline_registers(0) + srrc_zero_in;
srrc_output_adders_registers(i) <= srrc_multipliers_registers(i) + srrc_zero_out;
else
srrc_input_adders_registers(i) <= sam_i_pipeline_registers(0) + srrc_zero_in + sam_i_pipeline_registers(i*2);
srrc_output_adders_registers(i) <= srrc_multipliers_registers(i) + srrc_output_adders_registers(i-1);
end if;
end loop;
sam_o <= std_logic_vector(srrc_output_adders_registers(CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER-1)(CCSDS_RXTX_SRRC_SIG_OUT_ADD_SIZE-1 downto CCSDS_RXTX_SRRC_SIG_OUT_ADD_SIZE-CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH));
else
sam_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
mit
|
99c8e9f98a1b467e0e0506ef4e9728b3
| 0.661226 | 3.371277 | false | false | false | false |
stratfob/childServiceDatabase
|
application/views/pages/this.vhdl
| 1 | 756 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder3to8 is
Port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
Q4 : out std_logic;
Q5 : out std_logic;
Q6 : out std_logic;
Q7 : out std_logic
);
end Decoder3to8;
architecture Behavioral of Decoder3to8 is
begin
Q0<= ((not A0) and (not A1) and (not A2)) after 5 ns;
Q1<= (A0 and (not A1) and (not A2)) after 5 ns;
Q2<= ((not A0) and A1 and (not A2)) after 5 ns;
Q3<= (A0 and A1 and (not A2)) after 5 ns;
Q4<= ((not A0) and (not A1) and A2) after 5 ns;
Q5<= (A0 and (not A1) and A2) after 5 ns;
Q6<= ((not A0) and A1 and A2) after 5 ns;
Q7<= (A0 and A1 and A2) after 5 ns;
end Behavioral;
|
mit
|
f9feb0b8cd3146ade52c46f7dfd548d8
| 0.630952 | 2.204082 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/simulation/fifo_synth.vhd
| 1 | 10,151 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo_inst : fifo_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
mit
|
90d1e1cc090f3ea52050b6f4a8f0deb9
| 0.445375 | 4.179086 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ipcore_dir/fifo/simulation/fifo_tb.vhd
| 1 | 5,872 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_tb IS
END ENTITY;
ARCHITECTURE fifo_arch OF fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fifo_synth
fifo_synth_inst:fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 75
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
mit
|
d9954477f1c61981ebffe228b840f374
| 0.597071 | 4.164539 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rx.vhd
| 1 | 4,025 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rx
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary rx external physical inputs and outputs
entity ccsds_rx is
generic (
CCSDS_RX_PHYS_SIG_QUANT_DEPTH : integer := 16;
CCSDS_RX_DATA_BUS_SIZE: integer := 32
);
port(
-- inputs
clk_i: in std_logic; -- input samples clock
dat_nxt_i: in std_logic; -- next data
ena_i: in std_logic; -- system enable input
rst_i: in std_logic; -- system reset input
sam_i_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
-- outputs
buf_bit_ful_o: out std_logic; -- bits buffer status indicator
buf_dat_ful_o: out std_logic; -- data buffer status indicator
buf_fra_ful_o: out std_logic; -- frames buffer status indicator
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
dat_val_o: out std_logic; -- data valid
ena_o: out std_logic; -- enabled status indicator
irq_o: out std_logic -- data ready to be read / IRQ signal
);
end ccsds_rx;
architecture structure of ccsds_rx is
component ccsds_rx_datalink_layer is
generic(
CCSDS_RX_DATALINK_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
buf_dat_ful_o: out std_logic;
buf_fra_ful_o: out std_logic;
buf_bit_ful_o: out std_logic
);
end component;
component ccsds_rx_physical_layer is
generic(
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH : integer;
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
sam_i_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
sam_q_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0)
);
end component;
signal wire_data_m: std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
signal wire_clk_m: std_logic;
signal wire_clk_i: std_logic;
begin
rx_datalink_layer_1: ccsds_rx_datalink_layer
generic map(
CCSDS_RX_DATALINK_DATA_BUS_SIZE => CCSDS_RX_DATA_BUS_SIZE
)
port map(
clk_i => wire_clk_m,
rst_i => rst_i,
dat_i => wire_data_m,
dat_o => dat_o,
buf_dat_ful_o => buf_dat_ful_o,
buf_fra_ful_o => buf_fra_ful_o,
buf_bit_ful_o => buf_bit_ful_o
);
rx_physical_layer_1: ccsds_rx_physical_layer
generic map(
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH => CCSDS_RX_PHYS_SIG_QUANT_DEPTH,
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE => CCSDS_RX_DATA_BUS_SIZE
)
port map(
clk_i => wire_clk_i,
clk_o => wire_clk_m,
rst_i => rst_i,
sam_i_i => sam_i_i,
sam_q_i => sam_q_i,
dat_o => wire_data_m
);
--=============================================================================
-- Begin of enablep
-- Enable/disable clk forwarding
--=============================================================================
-- read: clk_i, ena_i
-- write: wire_clk_i
-- r/w:
ENABLEP : process (clk_i, ena_i)
begin
if (ena_i = '1') then
wire_clk_i <= clk_i;
ena_o <= '1';
else
wire_clk_i <= '0';
ena_o <= '0';
end if;
end process;
end structure;
|
mit
|
cfc8a1159460c36954a672d25ac62e71
| 0.56323 | 3.285714 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/comparator.vhd
| 1 | 3,980 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/30 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Compares a the look ahead buffer to a candidate and returns the number of bytes before the first
--* non-matching pair. The counting starts at the least significant end of the look ahead and the candidate
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity comparator is
port (
-- ClkxCI : in std_logic;
-- RstxRI : in std_logic;
-- EnxSI : in std_logic;
LookAheadxDI : in std_logic_vector(16*8-1 downto 0);
LookAheadLenxDI : in integer range 0 to 16; -- how many bytes of LookAheadxDI are valid
CandidatexDI : in std_logic_vector(16*8-1 downto 0);
CandidateLenxDI : in integer range 0 to 16; -- how many bytes of CandidatexDI are valid
MatchLenxDO : out integer range 0 to 16); -- length of the match in bytes
end comparator;
architecture Behavioral of comparator is
signal MatchVectorxS : std_logic_vector(15 downto 0); -- match signals for the individual bytes
signal RawMatchLenxD : integer range 0 to 16; -- number of matching bytes (before further processing)
signal MaxLengthxD : integer range 0 to 16; -- smaller of the two input signal length;
begin
-- implement 16 byte wide comparators
genByteComps : for i in 0 to 15 generate
MatchVectorxS(i) <= '1' when CandidatexDI((i+1)*8-1 downto i*8) = LookAheadxDI((i+1)*8-1 downto i*8) else '0';
end generate genByteComps;
-- count the number of leading bytes to determine the match length
process (MatchVectorxS)
variable cnt : integer range 0 to 16 := 0;
begin -- process
cnt := 0;
cntLoop : for i in 0 to 15 loop
if MatchVectorxS(i) = '1' then
cnt := cnt + 1;
else
exit cntLoop;
end if;
end loop; -- i
RawMatchLenxD <= cnt;
end process;
-- the match length can not be longer than the shorter of the two data inputs
MaxLengthxD <= CandidateLenxDI when CandidateLenxDI < LookAheadLenxDI else LookAheadLenxDI;
-- make sure the match length is not bigger than the max length
MatchLenxDO <= RawMatchLenxD when RawMatchLenxD <= MaxLengthxD else MaxLengthxD;
end Behavioral;
|
gpl-2.0
|
46c2ed81ed19a9f90256f74830023031
| 0.581407 | 4.364035 | false | false | false | false |
ziyan/altera-de2-ann
|
src/pr/patterns.vhd
| 1 | 1,484 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.pr_types.all;
USE work.lcd_types.all;
package pattern_constants is
constant PATTERN_SIZE : integer := 16;
constant PATTERN_CLASS_COUNT : integer := 16;
constant PATTERN_TRAINING_COUNT : integer := 16;
constant PATTERN_TRAINING_DATA : std_logic_vector(PATTERN_SIZE * PATTERN_TRAINING_COUNT - 1 downto 0) :=
-- A
"0110" &
"1001" &
"1111" &
"1001" &
-- C
"1111" &
"1000" &
"1000" &
"1111" &
-- D
"1110" &
"1001" &
"1001" &
"1110" &
-- F
"1111" &
"1000" &
"1111" &
"1000" &
-- H
"1001" &
"1111" &
"1111" &
"1001" &
-- I
"1111" &
"0110" &
"0110" &
"1111" &
-- J
"1111" &
"0001" &
"1001" &
"0110" &
-- L
"1000" &
"1000" &
"1000" &
"1111" &
-- N
"1001" &
"1101" &
"1011" &
"1001" &
-- O
"1111" &
"1001" &
"1001" &
"1111" &
-- P
"1111" &
"1001" &
"1111" &
"1000" &
-- T
"1111" &
"0110" &
"0110" &
"0110" &
-- U
"1001" &
"1001" &
"1001" &
"1111" &
-- X
"1001" &
"0110" &
"0110" &
"1001" &
-- Y
"1001" &
"1001" &
"0110" &
"0110" &
-- Z
"1111" &
"0010" &
"0100" &
"1111";
constant PATTERN_TRAINING_CLASS : integer_vector(PATTERN_TRAINING_COUNT - 1 downto 0) := (15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0);
constant PATTERN_DISPLAY : char_vector(PATTERN_CLASS_COUNT - 1 downto 0) := (
(x"41"), -- A
(x"43"), -- C
(x"44"), -- D
(x"46"), -- F
(x"48"), -- H
(x"49"), -- I
(x"4A"), -- J
(x"4C"), -- L
(x"4E"), -- N
(x"4F"), -- O
(x"50"), -- P
(x"54"), -- T
(x"55"), -- U
(x"58"), -- X
(x"59"), -- Y
(x"5A") -- Z
);
end package pattern_constants;
|
mit
|
f9d3361040bc43e78a57a00247fa181d
| 0.526954 | 2.129125 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/LZRWcompressorTb.vhd
| 1 | 6,816 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/9/16 - LS
--* started file
--*
--* Version 1.0 - 2013/4/5 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* This is a file based testbench for the LZRW1 compressor core. It reads data
--* binary from a configured file, and feeds it int the core. The compressed data
--* is stored in a second file for verifycation. (Use the two java programs
--* provided with this project to create and verify test vectors)
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use std.textio.all;
-------------------------------------------------------------------------------
entity LZRWcompressor_tb is
end LZRWcompressor_tb;
-------------------------------------------------------------------------------
architecture tb of LZRWcompressor_tb is
component LZRWcompressor
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DataInxDI : in std_logic_vector(7 downto 0);
StrobexSI : in std_logic;
FlushBufxSI : in std_logic;
BusyxSO : out std_logic;
DonexSO : out std_logic;
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024);
end component;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal DInxDI : std_logic_vector(7 downto 0) := (others => '0');
signal StrobexSI : std_logic := '0';
signal FlushBufxSI : std_logic := '0';
signal BusyxSO : std_logic;
signal DonexSO : std_logic;
signal BufOutxDO : std_logic_vector(7 downto 0);
signal OutputValidxSO : std_logic;
signal RdStrobexSI : std_logic := '0';
signal LengthxDO : integer range 0 to 1024;
-- clock
signal Clk : std_logic := '1';
signal TbDone : std_logic := '0';
-- configuration
constant DATA_IN_FILE_NAME : string := "../../test files/TVect1.bin"; -- file with stimuli which will be compressed (relative to XST directroy)
constant DATA_OUT_FILE_NAME : string := "../../test files/TVect1.cmp"; -- filename for compressed data
constant PERIOD : time := 20 ns;
type binFileType is file of character;
begin -- tb
-- component instantiation
DUT : LZRWcompressor
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
DataInxDI => DInxDI,
StrobexSI => StrobexSI,
FlushBufxSI => FlushBufxSI,
BusyxSO => BusyxSO,
DonexSO => DonexSO,
BufOutxDO => BufOutxDO,
OutputValidxSO => OutputValidxSO,
RdStrobexSI => RdStrobexSI,
LengthxDO => LengthxDO
);
-- clock generation
Clk <= not Clk after (PERIOD / 2);
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
file srcFile : binFileType is in DATA_IN_FILE_NAME; -- uncompressed data input in file
variable srcChar : character;
variable l : line;
begin
wait for PERIOD;
wait until Clk'event and Clk = '1';
RstxRI <= '0';
while not endfile(srcFile) loop
read(srcFile, srcChar);
-- write(l, "found char ");
-- write(l, character'image(srcChar));
-- write(l, " ");
-- write(l, character'pos(srcChar));
-- writeline(OUTPUT, l);
wait until Clk'event and Clk = '1';
if BusyxSO = '0' then
DInxDI <= std_logic_vector(to_unsigned(character'pos(srcChar), 8));
StrobexSI <= '1';
end if;
wait until Clk'event and Clk = '1';
StrobexSI <= '0';
DInxDI <= "--------";
end loop;
StrobexSI <= '0';
for i in 0 to 10 loop
wait until Clk'event and Clk = '1';
end loop;
--wait until Clk'event and Clk = '1';
FlushBufxSI <= '1';
wait until Clk'event and Clk = '1';
FlushBufxSI <= '0';
file_close(srcFile);
for i in 0 to 10 loop
wait until Clk'event and Clk = '1';
end loop;
TbDone <= '1';
wait;
end process WaveGen_Proc;
-- process to receive compressed data from the core and store it in a file
pickupPrcs : process
file destFile : binFileType is out DATA_OUT_FILE_NAME; -- receives compressed data
variable destChar : character;
variable l : line;
begin
while true loop
wait until Clk'event and Clk = '1';
if LengthxDO > 0 then
RdStrobexSI <= '1';
else
RdStrobexSI <= '0';
end if;
if OutputValidxSO = '1' then
-- wait until Clk'event and Clk = '1';
destChar := character'val(to_integer(unsigned(BufOutxDO)));
write(destFile, destChar);
end if;
end loop;
file_close(destFile);
wait;
end process;
end tb;
-------------------------------------------------------------------------------
configuration LZRWcompressor_tb_tb_cfg of LZRWcompressor_tb is
for tb
end for;
end LZRWcompressor_tb_tb_cfg;
-------------------------------------------------------------------------------
|
gpl-2.0
|
2cd9ecc325fa58a3a68979bcd55be3e4
| 0.523914 | 4.451992 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/RAM.vhd
| 1 | 7,013 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
ENTITY ram IS
PORT (
Clk : in std_logic;
Reset : in std_logic;
write_en : in std_logic;
oe : in std_logic;
address : in std_logic_vector(7 downto 0);
databus : inout std_logic_vector(7 downto 0);
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
END ram;
ARCHITECTURE behavior OF ram IS
SIGNAL contents_ram_general : array8_ram(191 downto 0); -- 192 posiciones de memoria desde X"40" hasta X"FF"
SIGNAL contents_ram_specific : array8_ram(63 downto 0); -- 64 posiciones de memoria desde X"00" hasta X"3F"
SIGNAL valor_Switch : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL memory_election : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- Eleccion de Memoria
-------------------------------------------------------------------------
election : process (address)
begin
--if clk'event and clk = '1' then
if address > X"3F" then -- Memoria general
memory_election <= '0';
elsif address < X"40" then -- Memoria específica
memory_election <= '1';
end if;
--end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Memoria de propósito general
-------------------------------------------------------------------------
p_ram : process (clk) -- no reset
begin
if clk'event and clk = '1' then
if write_en = '1' and memory_election = '0' then
contents_ram_general(conv_Integer(address)) <= databus;
end if;
end if;
end process;
databus <= contents_ram_general(conv_integer(address)) when (oe = '0' and memory_election = '0') else
contents_ram_specific(conv_integer(address)) when (oe = '0' and memory_election = '1') else (others => 'Z');
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Memoria de propósito específico
-------------------------------------------------------------------------
pe_ram : process (clk, Reset)
begin
if reset = '0' then
contents_ram_specific(conv_Integer(DMA_RX_BUFFER_MSB)) <= (others => '0'); -- Valor de la instrucción Rx
contents_ram_specific(conv_Integer(DMA_RX_BUFFER_MID)) <= (others => '0'); -- Valor del parámetro 1 Rx
contents_ram_specific(conv_Integer(DMA_RX_BUFFER_LSB)) <= (others => '0'); -- Valor del parámetro 2 Rx
contents_ram_specific(conv_Integer(NEW_INST)) <= (others => '0'); -- Flag que indica llegada de un nuevo comando
contents_ram_specific(conv_Integer(DMA_TX_BUFFER_MSB)) <= (others => '0'); -- Valor 1 de la Tx
contents_ram_specific(conv_Integer(DMA_TX_BUFFER_LSB)) <= (others => '0'); -- Valor 2 de la Tx
contents_ram_specific(conv_Integer(SWITCH_BASE)) <= (others => '0'); -- Valores de control de los interruptores
contents_ram_specific(conv_Integer(SWITCH_BASE+1)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+2)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+3)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+4)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+5)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+6)) <= (others => '0');
contents_ram_specific(conv_Integer(SWITCH_BASE+7)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE)) <= (others => '0'); -- Valores de control de los actuadores
contents_ram_specific(conv_Integer(LEVER_BASE+1)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+2)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+3)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+4)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+5)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+6)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+7)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+8)) <= (others => '0');
contents_ram_specific(conv_Integer(LEVER_BASE+9)) <= (others => '0');
contents_ram_specific(conv_Integer(T_STAT)) <= "00100000"; -- Valor de la temperatura en BCD
elsif reset = '1' then
if clk'event and clk = '1' then
if write_en = '1' and memory_election = '1' then
contents_ram_specific(conv_Integer(address)) <= databus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Decodificador de BCD a 7 segmentos
-------------------------------------------------------------------------
temp : process(clk)
begin
if clk'event and clk='1' then
case contents_ram_specific(conv_Integer(T_STAT))(7 downto 4) is
when "0001" => Temp_H <= "0000110"; -- 1
when "0010" => Temp_H <= "1011011"; -- 2
when "0011" => Temp_H <= "1001111"; -- 3
when "0100" => Temp_H <= "1100110"; -- 4
when "0101" => Temp_H <= "1101101"; -- 5
when "0110" => Temp_H <= "1111101"; -- 6
when "0111" => Temp_H <= "0000111"; -- 7
when "1000" => Temp_H <= "1111111"; -- 8
when "1001" => Temp_H <= "1101111"; -- 9
when "1010" => Temp_H <= "1110111"; -- A
when "1011" => Temp_H <= "1111100"; -- B
when "1100" => Temp_H <= "0111001"; -- C
when "1101" => Temp_H <= "1011110"; -- D
when "1110" => Temp_H <= "1111001"; -- E
when "1111" => Temp_H <= "1110001"; -- F
when others => Temp_H <= "0111111"; -- 0
end case;
case contents_ram_specific(conv_Integer(T_STAT))(3 downto 0) is
when "0001" => Temp_L <= "0000110"; -- 1
when "0010" => Temp_L <= "1011011"; -- 2
when "0011" => Temp_L <= "1001111"; -- 3
when "0100" => Temp_L <= "1100110"; -- 4
when "0101" => Temp_L <= "1101101"; -- 5
when "0110" => Temp_L <= "1111101"; -- 6
when "0111" => Temp_L <= "0000111"; -- 7
when "1000" => Temp_L <= "1111111"; -- 8
when "1001" => Temp_L <= "1101111"; -- 9
when "1010" => Temp_L <= "1110111"; -- A
when "1011" => Temp_L <= "1111100"; -- B
when "1100" => Temp_L <= "0111001"; -- C
when "1101" => Temp_L <= "1011110"; -- D
when "1110" => Temp_L <= "1111001"; -- E
when "1111" => Temp_L <= "1110001"; -- F
when others => Temp_L <= "0111111"; -- 0
end case;
for i in 0 to 7 loop
valor_Switch(i) <= contents_ram_specific(conv_Integer(SWITCH_BASE+i))(0);
end loop;
Switches <= valor_Switch;
end if;
end process;
-------------------------------------------------------------------------
END behavior;
|
mit
|
385e4703e93052507e4141653d6d23f0
| 0.523599 | 3.431018 | false | false | false | false |
xuefei1/ElectronicEngineControl
|
vhd/freq_divider_ref_50MHz_clk.vhd
| 1 | 1,301 |
-- freq_16kHz_clk.vhd
-- Author: Fred
-- Status: Tested and passed
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity freq_divider_ref_50MHz_clk is
port (
clock_in : in std_logic := '0'; -- 50 MHz clk in
clock_out : out std_logic := '0'; -- 16 kHz clk out
write_enable : in std_logic := '0';
freq_in : in std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; -- in terms of # of 50MHz clk in
reset : in std_logic := '0' -- reset
);
end entity freq_divider_ref_50MHz_clk;
architecture clk_out of freq_divider_ref_50MHz_clk is
signal clk_out : std_logic := '0';
begin
inc: process(clock, reset)
variable limit : integer range 0 to 4294967295;
variable count : integer range 0 to 4294967295;
begin
if(reset = '1') then
limit := 0; -- 50MHz -> 20ns period, for example, 16kHz -> 62500ns period, so every 3125 clk in, we flip clk out
count := 0;
elsif(rising_edge(clock)) then
if(write_enable = '1') then
limit := unsigned(freq_in);
count := 0;
end if;
if(count = limit - 1) then
clock_out <= NOT(clk_out);
count := 0;
else
count := count + 1;
end if;
end if;
end process;
end architecture clk_out;
|
apache-2.0
|
bbc325df7bb4b1a537aedb69d110c70e
| 0.602613 | 2.89755 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
reg_32_bit.vhd
| 1 | 1,192 |
-- 32-bit register, can be used for many purposes
-- has write enable, synchronous clear, asynchronous reset inputs
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity reg_32_bit is
port (
-- 32-bit input
in_32 : in std_logic_vector(31 downto 0);
-- clock, async reset, sync clear
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
-- write enable
wr_en : in std_logic;
-- 32-bit output
out_32 : out std_logic_vector(31 downto 0)
);
end entity reg_32_bit;
architecture reg_32_bit_arch of reg_32_bit is
-- this circuit does not require any internal signals
begin
wrt : process(rst, clk)
begin
-- on async reset high, register contents set to 0
if rst = '1' then
out_32 <= (others => '0');
-- otherwise on rising clock edge and write enable high, transfer input to output
-- or if clr high, zero output
else
if rising_edge(clk) then
if clr = '1' then
out_32 <= (others => '0');
else
if wr_en = '1' then
out_32 <= in_32;
end if;
end if;
end if;
end if;
end process wrt;
end architecture reg_32_bit_arch;
|
mit
|
1a670659fec348f604ae88c71fe09bc6
| 0.644295 | 2.872289 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/RS232top.vhd
| 1 | 4,912 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top is
port (
Reset : in std_logic; -- Low_level-active asynchronous reset
Clk : in std_logic; -- System clock (20MHz), rising edge used
Data_in : in std_logic_vector(7 downto 0); -- Data to be sent
Valid_D : in std_logic; -- Handshake signal
-- from guest system, low when data is valid
Ack_in : out std_logic; -- ACK for data received, low once data
-- has been stored
TX_RDY : out std_logic; -- System ready to transmit
TD : out std_logic; -- RS232 Transmission line
RD : in std_logic; -- RS232 Reception line
Data_out : out std_logic_vector(7 downto 0); -- Received data
Data_read : in std_logic; -- Data read for guest system
Full : out std_logic; -- Full internal memory
Empty : out std_logic; -- Empty internal memory
FF_Count : out std_logic_vector(5 downto 0)); -- Number of bytes in fifo
end RS232top;
architecture RTL of RS232top is
------------------------------------------------------------------------
-- Components for Transmitter Block
------------------------------------------------------------------------
component RS232_TX
port (
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Data : in std_logic_vector(7 downto 0);
EOT : out std_logic;
TX : out std_logic);
end component;
------------------------------------------------------------------------
-- Components for Receiver Block
------------------------------------------------------------------------
component ShiftRegister
port (
Reset : in std_logic;
Clk : in std_logic;
Enable : in std_logic;
D : in std_logic;
Q : out std_logic_vector(7 downto 0));
end component;
component RS232_RX
port (
Clk : in std_logic;
Reset : in std_logic;
LineRD_in : in std_logic;
Valid_out : out std_logic;
Code_out : out std_logic;
Store_out : out std_logic);
end component;
component fifo
port (
clk : IN std_logic;
rst : IN std_logic;
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
data_count : OUT std_logic_VECTOR(5 downto 0));
end component;
------------------------------------------------------------------------
-- Internal Signals
------------------------------------------------------------------------
signal Data_FF : std_logic_vector(7 downto 0);
signal StartTX : std_logic; -- start signal for transmitter
signal LineRD_in : std_logic; -- internal RX line
signal Valid_out : std_logic; -- valid bit @ receiver
signal Code_out : std_logic; -- bit @ receiver output
signal sinit : std_logic; -- fifo reset
signal Fifo_in : std_logic_vector(7 downto 0);
signal Fifo_write : std_logic;
signal TX_RDY_i : std_logic;
begin -- RTL
Transmitter: RS232_TX
port map (
Clk => Clk,
Reset => Reset,
Start => StartTX,
Data => Data_FF,
EOT => TX_RDY_i,
TX => TD);
Receiver: RS232_RX
port map (
Clk => Clk,
Reset => Reset,
LineRD_in => LineRD_in,
Valid_out => Valid_out,
Code_out => Code_out,
Store_out => Fifo_write);
Shift: ShiftRegister
port map (
Reset => Reset,
Clk => Clk,
Enable => Valid_Out,
D => Code_Out,
Q => Fifo_in);
sinit <= not reset;
Internal_memory: fifo
port map (
clk => clk,
rst => sinit,
din => Fifo_in,
wr_en => Fifo_write,
rd_en => Data_read,
dout => Data_out,
full => Full,
empty => Empty,
data_count => FF_Count);
-- purpose: Clocking process for input protocol
Clocking : process (Clk, Reset)
begin
if Reset = '0' then -- asynchronous reset (active low)
Data_FF <= (others => '0');
LineRD_in <= '1';
Ack_in <= '1';
elsif Clk'event and Clk = '1' then -- rising edge clock
LineRD_in <= RD;
if Valid_D = '0' and TX_RDY_i = '1' then
Data_FF <= Data_in;
Ack_in <= '0';
StartTX <= '1';
else
Ack_in <= '1';
StartTX <= '0';
end if;
end if;
end process Clocking;
TX_RDY <= TX_RDY_i;
end RTL;
|
mit
|
adba2c47b207b9f1a2df1839f6d90349
| 0.47842 | 3.822568 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
adder_32_bit.vhd
| 1 | 4,153 |
-- 32-bit adder circuit
-- this circuit adds two 32-bit unsigned numbers together, and supports previous-carry addition and subtraction
-- all code (c) 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity adder_32_bit is
port (
-- inputs
a_32 : in std_logic_vector(31 downto 0);
b_32 : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(1 downto 0);
enable : in std_logic;
-- outputs
sum_32 : out std_logic_vector(31 downto 0);
carry : out std_logic;
overflow : out std_logic
);
end entity adder_32_bit;
architecture adder_32_bit_arch of adder_32_bit is
-- signed values
signal a_signed : signed(31 downto 0);
signal b_signed : signed(31 downto 0);
signal sum_signed : signed(31 downto 0);
-- unsigned values
signal a_unsigned : unsigned(32 downto 0);
signal b_unsigned : unsigned(32 downto 0);
signal sum_unsigned : unsigned(32 downto 0);
begin
-- design implementation
add : process(enable, opcode, a_32, b_32, a_signed, b_signed, sum_signed, a_unsigned, b_unsigned, sum_unsigned)
begin
if enable = '1' then
-- converting inputs to signed vectors
a_signed <= signed(a_32);
b_signed <= signed(b_32);
-- converting inputs to unsigned vectors
a_unsigned <= '0' & unsigned(a_32);
b_unsigned <= '0' & unsigned(b_32);
-- performing addition/subtraction
-- opcode 00 is add signed
if opcode = "00" then
-- calculating signed sum
sum_signed <= a_signed + b_signed;
-- set unsigned sum to 0
sum_unsigned <= (others => '0');
-- if sign bit of sum is not the same as the sign bits of the two operands, set overflow flag
if a_signed(31) = '1' and b_signed(31) = '1' and sum_signed(31) = '0' then
overflow <= '1';
elsif a_signed(31) = '0' and b_signed(31) = '0' and sum_signed(31) = '1' then
overflow <= '1';
else
overflow <= '0';
end if;
-- carry out set to 0
carry <= '0';
-- opcode 01 is add unsigned
elsif opcode = "01" then
-- set signed sum to 0
sum_signed <= (others => '0');
-- calculating unsigned sum
sum_unsigned <= a_unsigned + b_unsigned;
-- msb of sum is carry out
carry <= sum_unsigned(32);
-- overflow flag set to 0
overflow <= '0';
-- opcode 10 is subtract signed
elsif opcode = "10" then
-- calculate signed sum
sum_signed <= a_signed - b_signed;
-- set unsigned sum to 0
sum_unsigned <= (others => '0');
-- if sign bit of sum is not the same as the sign bits of the two operands, set overflow flag
if a_signed(31) = '0' and b_signed(31) = '1' and sum_signed(31) = '1' then
overflow <= '1';
elsif a_signed(31) = '1' and b_signed(31) = '0' and sum_signed(31) = '0' then
overflow <= '1';
else
overflow <= '0';
end if;
-- carry out set to 0
carry <= '0';
-- opcode 11 is subtract unsigned
elsif opcode = "11" then
-- set signed sum to 0
sum_signed <= (others => '0');
-- calculate unsigned sum
sum_unsigned <= a_unsigned - b_unsigned;
-- if b > a set carry to 1
if b_unsigned > a_unsigned then
carry <= '1';
else
carry <= '0';
end if;
-- overflow set to 0
overflow <= '0';
-- otherwise error case, output 0
else
sum_signed <= (others => '0');
sum_unsigned <= (others => '0');
overflow <= '0';
carry <= '0';
end if;
if opcode(0) = '0' then
sum_32 <= std_logic_vector(sum_signed);
elsif opcode(0) = '1' then
sum_32 <= std_logic_vector(sum_unsigned(31 downto 0));
else
sum_32 <= (others => '0');
end if;
-- adder disabled, all outputs and signals 0
else
-- resetting internal signals
a_signed <= (others => '0');
b_signed <= (others => '0');
sum_signed <= (others => '0');
a_unsigned <= (others => '0');
b_unsigned <= (others => '0');
sum_unsigned <= (others => '0');
-- resetting outputs
carry <= '0';
overflow <= '0';
sum_32 <= (others => '0');
end if;
end process add;
end architecture adder_32_bit_arch;
|
mit
|
59768b63ef38a66b212196e2b2d8c4b9
| 0.595473 | 3.031387 | false | false | false | false |
jpendlum/crash
|
fpga/src/accelerator/accelerator.vhd
| 2 | 7,316 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: accelerator.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Template file for custom accelerators.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accelerator is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic;
-- AXIS Stream Master Interface
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic;
-- Sideband signals
example_sideband_signals : out std_logic_vector(7 downto 0));
end entity;
architecture RTL of spectrum_sense is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component fifo_axis_64x4096
port (
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(63 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(63 downto 0);
m_axis_tlast : out std_logic;
axis_data_count : out std_logic_vector(12 downto 0);
axis_overflow : out std_logic;
axis_underflow : out std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal ctrl_stb_dly : std_logic;
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal rst : std_logic;
signal reset_fifo : std_logic;
signal reset_fifo_n : std_logic;
signal axis_data_count : std_logic_vector(12 downto 0);
begin
rst <= NOT(rst_n);
reset_fifo_n <= NOT(reset_fifo_n) AND rst_n;
-- Interrupt signals trigger on a rising edge
axis_slave_irq <= '0';
axis_master_irq <= '0';
-- Loopback FIFO.
example_fifo_axis_64x4096 : fifo_axis_64x4096
port map (
s_aclk => clk,
s_aresetn => reset_fifo_n,
s_axis_tvalid => axis_slave_tvalid,
s_axis_tready => axis_slave_tready,
s_axis_tdata => axis_slave_tdata,
s_axis_tlast => axis_slave_tlast,
m_axis_tvalid => axis_master_tvalid,
m_axis_tready => axis_master_tready,
m_axis_tdata => axis_master_tdata,
m_axis_tlast => axis_master_tlast,
axis_data_count => axis_data_count,
axis_overflow => open,
axis_underflow => open);
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
ctrl_reg <= (others=>(others=>'0'));
status_data <= (others=>'0');
axis_master_tdest_safe <= (others=>'0');
else
if rising_edge(clk) then
-- Update control registers only when the accelerator is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register when selected
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination should only update when no data is being transmitted over the AXI bus.
if (reset_fifo = '1') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0
reset_fifo <= ctrl_reg(0)(0);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1
example_sideband_signals <= ctrl_reg(1)(7 downto 0);
-- Status Registers
-- Bank 0
status_reg(0)(0) <= reset_fifo;
status_reg(0)(31 downto 29) <= axis_master_tdest_safe;
-- Bank 1
status_reg(1)(7 downto 0) <= example_sideband_signals;
-- Bank 2
status_reg(2)(12 downto 0) <= axis_data_count;
end architecture;
|
gpl-3.0
|
d6ecfff56cfbb8c81fcae457d6375a9c
| 0.471843 | 4.362552 | false | false | false | false |
koolatron/hackrf
|
firmware/cpld/sgpio_if/top.vhd
| 1 | 5,046 |
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
q_invert_mask <= X"80" when q_invert = '1' else X"7f";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
dac_data_o <= (data_from_host_i xor X"7f") & "11";
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
3d502b54ec354d43ae23b4b79bf551f7
| 0.536663 | 3.732249 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_filter.vhd
| 1 | 7,812 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_filter
---- Version: 1.0.0
---- Description:
---- Transform symbols to samples, oversample signal and filter it with SRRC filter
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx filter inputs and outputs
--=============================================================================
entity ccsds_tx_filter is
generic(
constant CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer; -- in bits
constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_FILTER_OFFSET_IQ: boolean := true;
constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
constant CCSDS_TX_FILTER_TARGET_SNR: real := 40.0
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sym_i_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_q_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
-- outputs
sam_i_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end ccsds_tx_filter;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_filter is
component ccsds_tx_mapper_symbols_samples is
generic(
constant CCSDS_TX_MAPPER_TARGET_SNR: real;
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer;
constant CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
sam_val_o: out std_logic;
sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
);
end component;
component ccsds_rxtx_oversampler is
generic(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: boolean;
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
rst_i: in std_logic;
sam_o: out std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
component ccsds_rxtx_srrc is
generic(
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
sam_o: out std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal wire_sam_i: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_q: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_i_val: std_logic := '0';
signal wire_sam_q_val: std_logic := '0';
signal wire_sam_i_osr: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_q_osr: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_i_osr_val: std_logic;
signal wire_sam_q_osr_val: std_logic;
signal wire_sam_i_srrc_val: std_logic;
signal wire_sam_q_srrc_val: std_logic;
-- components instanciation and mapping
begin
tx_mapper_symbols_samples_i_0: ccsds_tx_mapper_symbols_samples
generic map(
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH,
CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_TX_FILTER_TARGET_SNR,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_FILTER_BITS_PER_SYMBOL
)
port map(
clk_i => clk_i,
sym_i => sym_i_i,
sym_val_i => sym_val_i,
rst_i => rst_i,
sam_o => wire_sam_i,
sam_val_o => wire_sam_i_val
);
tx_oversampler_i_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_IQ,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_i,
sam_val_i => wire_sam_i_val,
rst_i => rst_i,
sam_val_o => wire_sam_i_osr_val,
sam_o => wire_sam_i_osr
);
tx_srrc_i_0: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_i_osr,
sam_val_i => wire_sam_i_osr_val,
rst_i => rst_i,
sam_o => sam_i_o,
sam_val_o => wire_sam_i_srrc_val
);
-- BPSK
BPSK_GENERATION: if (CCSDS_TX_FILTER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_FILTER_MODULATION_TYPE = 2) generate
sam_q_o <= (others => '0');
wire_sam_q_srrc_val <= '1';
end generate BPSK_GENERATION;
-- nPSK
NPSK_GENERATION: if (CCSDS_TX_FILTER_MODULATION_TYPE /= 2) or (CCSDS_TX_FILTER_BITS_PER_SYMBOL /= 1) generate
tx_mapper_symbols_samples_q_0: ccsds_tx_mapper_symbols_samples
generic map(
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH,
CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_TX_FILTER_TARGET_SNR,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_FILTER_BITS_PER_SYMBOL
)
port map(
clk_i => clk_i,
sym_i => sym_q_i,
sym_val_i => sym_val_i,
rst_i => rst_i,
sam_o => wire_sam_q,
sam_val_o => wire_sam_q_val
);
tx_oversampler_q_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => false,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_q,
sam_val_i => wire_sam_q_val,
rst_i => rst_i,
sam_val_o => wire_sam_q_osr_val,
sam_o => wire_sam_q_osr
);
tx_srrc_q_0: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_q_osr,
sam_val_i => wire_sam_q_osr_val,
rst_i => rst_i,
sam_o => sam_q_o,
sam_val_o => wire_sam_q_srrc_val
);
end generate NPSK_GENERATION;
--Valid samples indicator
sam_val_o <= wire_sam_i_srrc_val and wire_sam_q_srrc_val;
-- presynthesis checks
CHKFILTERP0: if (CCSDS_TX_FILTER_BITS_PER_SYMBOL > 2*(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1)) generate
process
begin
report "ERROR: BITS PER SYMBOL CANNOT BE HIGHER THAN 2*(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1)" severity failure;
wait;
end process;
end generate CHKFILTERP0;
end structure;
|
mit
|
1f44fffbc405e630c3079f0313eb2d1d
| 0.606119 | 3.297594 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_serdes.vhd
| 1 | 6,618 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_serdes
---- Version: 1.0.0
---- Description:
---- Constant rate data serialiser/deserialiser
---- Input: 1 clk / [SER2PAR: dat_ser_val_i <= '1' / dat_ser_i <= 'NEXTSERIALDATA' ] / [PAR2SER: dat_par_val_i <= '1' / dat_par_i <= "PARALLELDATA"]
---- Timing requirements: SER2PAR: 1 clock cycle - PAR2SER: CCSDS_RXTX_SERDES_DEPTH clock cycles
---- Output: [SER2PAR: dat_par_val_o <= "1" / dat_par_o <= "PARALLELIZEDDATA"] / [PAR2SER: dat_ser_val_o <= "1" / dat_ser_o <= "SERIALIZEDDATA"]
---- Ressources requirements: CCSDS_RXTX_SERDES_DEPTH + 2*|log(CCSDS_RXTX_SERDES_DEPTH-1)/log(2)| + 2 registers
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/18: initial release
---- 2016/10/27: review + add ser2par
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ccsds_rxtx_parameters.all;
--=============================================================================
-- Entity declaration for ccsds_rxtx_serdes / data serialiser/deserialiser
--=============================================================================
entity ccsds_rxtx_serdes is
generic (
constant CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
-- inputs
clk_i: in std_logic; -- parallel input data clock
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel input data
dat_par_val_i: in std_logic; -- parallel data valid indicator
dat_ser_i: in std_logic; -- serial input data
dat_ser_val_i: in std_logic; -- serial data valid indicator
rst_i: in std_logic; -- system reset input
-- outputs
bus_o: out std_logic; -- par2ser busy indicator
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel output data
dat_par_val_o: out std_logic; -- parallel output data valid indicator
dat_ser_o: out std_logic; -- serial output data
dat_ser_val_o: out std_logic -- serial output data valid indicator
);
end ccsds_rxtx_serdes;
--=============================================================================
-- architecture declaration / internal processing
--=============================================================================
architecture rtl of ccsds_rxtx_serdes is
-- internal variable signals
signal wire_busy: std_logic := '0';
signal wire_data_par_valid: std_logic := '0';
signal wire_data_ser_valid: std_logic := '0';
signal serial_data_pointer: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
signal parallel_data_pointer: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
begin
-- components instanciation and mapping
bus_o <= wire_busy;
dat_par_val_o <= wire_data_par_valid;
dat_ser_val_o <= wire_data_ser_valid;
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of par2serp
-- Serialization of parallel data received starting with MSB
--=============================================================================
-- read: clk_i, rst_i, dat_par_i, dat_par_val_i
-- write: dat_ser_o, wire_data_ser_valid, wire_busy
-- r/w: parallel_data_pointer
PAR2SERP : process (clk_i)
variable serdes_memory: std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- reset all
wire_busy <= '0';
dat_ser_o <= '0';
wire_data_ser_valid <= '0';
parallel_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
-- serdes_memory := (others => '0');
else
if (dat_par_val_i = '1') and (parallel_data_pointer = CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
serdes_memory := dat_par_i;
-- serialise data on output_bus
dat_ser_o <= dat_par_i(parallel_data_pointer);
-- decrement position pointer
parallel_data_pointer <= (parallel_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
wire_data_ser_valid <= '1';
else
if (parallel_data_pointer /= CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
-- serialise data on output_bus
dat_ser_o <= serdes_memory(parallel_data_pointer);
-- decrement position pointer
parallel_data_pointer <= (parallel_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
wire_data_ser_valid <= '1';
else
-- nothing to do
wire_busy <= '0';
wire_data_ser_valid <= '0';
end if;
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of ser2parp
-- Parallelization of serial data received
--=============================================================================
-- read: clk_i, rst_i, dat_ser_i, dat_ser_val_i
-- write: dat_par_o, wire_data_par_valid
-- r/w: serial_data_pointer
SER2PARP : process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- reset all
dat_par_o <= (others => '0');
wire_data_par_valid <= '0';
serial_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
else
if (dat_ser_val_i = '1') then
-- serialise data on output_bus
dat_par_o(serial_data_pointer) <= dat_ser_i;
if (serial_data_pointer = 0) then
wire_data_par_valid <= '1';
else
wire_data_par_valid <= '0';
end if;
-- decrement position pointer
serial_data_pointer <= (serial_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
else
wire_data_par_valid <= '0';
end if;
end if;
end if;
end process;
end rtl;
--=============================================================================
-- architecture end
--=============================================================================
|
mit
|
183e76ab518a9199fc5399c13368cc93
| 0.502871 | 4.085185 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
instruction_decoder.vhd
| 1 | 6,281 |
-- instruction decoder for VRISC architecture
-- converts 32-bit instruction code into control signals required for specified function
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
-- instructions not given here as there are too many to list concisely
-- instead they can be found in the README in the GitHub repository for this project
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity instruction_decoder is
port (
-- 32-bit instruction bus input
instr : in std_logic_vector(31 downto 0);
-- register address outputs
reg_addr_a : out std_logic_vector(4 downto 0);
reg_addr_b : out std_logic_vector(4 downto 0);
-- operand select signals
op_select_a : out std_logic; -- 0: prev_result, 1: reg_data_a
op_select_b : out std_logic; -- 0: reg_data_b, 1: imm_16_bit
-- immediate value from instruction
imm_16_bit : out std_logic_vector(15 downto 0);
-- offset value for program counter
offset : out std_logic_vector(25 downto 0);
-- external memory opcode
mem_opcode : out std_logic_vector(2 downto 0);
-- ALU control signals
alu_en : out std_logic;
alu_opcode : out std_logic_vector(3 downto 0);
-- register writeback control signals
wb_en : out std_logic; -- 0: reg_file will write on next clk, 1: reg_file will not write on next clk
wb_addr : out std_logic_vector(4 downto 0);
wb_select : out std_logic; -- 0: select ALU result for wb, 1: select mem_read for wb
-- pc value select signal
pc_select : out std_logic_vector(1 downto 0); -- 00: reg_data_a, 01: imm_16_bit, 11: offset
-- pc opcode
pc_opcode : out std_logic_vector(2 downto 0);
-- conditional jump test opcode
cond_opcode : out std_logic_vector(1 downto 0)
);
end entity instruction_decoder;
architecture instruction_decoder_arch of instruction_decoder is
-- internal signal declarations
-- register address stack signals
-- this is a stack of depth 2 which stores the register addresses of operand a
-- if the bottom value of this stack is the current reg_addr_a, then prev_result needs to be selected
-- and not reg_data_a as this will be the wrong value (reg[a] will soon change on writeback)
signal reg_stack_top : std_logic_vector(4 downto 0);
signal reg_stack_bottom : std_logic_vector(4 downto 0);
begin
-- design implementation
-- process to define decoding of instruction
decode : process(clk)
begin
-- decode on rising edge of clk
if rising_edge(clk) then
-- first check bottom of stack
-- if current reg_addr_a value is equal to reg_stack_bottom
-- op_select_a <= 0 because previous result must be used (current value of reg[a] is out of date)
if reg_addr_a = reg_stack_bottom then
op_select_a <= '0';
else
op_select_a <= '1';
end if;
-- update register addresses from instr
reg_addr_a <= instr(20 downto 16);
reg_addr_b <= instr(15 downto 11);
-- update immediate value
imm_16_bit <= instr(15 downto 0);
-- update offset value
offset <= instr(25 downto 0);
-- update wr_addr value
wr_addr <= instr(25 downto 21);
-- *** INCOMPLETE DEFINITION ***
-- add definitions for outputs based on opcode
-- after opcodes have been defined
-- case statement for assigning values to outputs
-- based on opcode
case instr(31 downto 26) is
-- 0x00 NO OPERATION
-- ALU addition with no wb
when "000000" =>
op_select_b <= '0';
alu_en <= '0';
alu_opcode <= "0000";
mem_opcode <= "000";
wb_en <= '0';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x01 ADD REGISTER SIGNED
when "000001" =>
op_select_b <= '0';
alu_en <= '1';
alu_opcode <= "0000";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x02 ADD IMMEDIATE SIGNED
when "000010" =>
op_select_b <= '1';
alu_en <= '1';
alu_opcode <= "0000";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x03 ADD REGISTER UNSIGNED
when "000011" =>
op_select_b <= '0';
alu_en <= '1';
alu_opcode <= "0001";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x04 ADD IMMEDIATE UNSIGNED
when "000100" =>
op_select_b <= '1';
alu_en <= '1';
alu_opcode <= "0001";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x05 SUB REGISTER SIGNED
when "000101" =>
op_select_b <= '0';
alu_en <= '1';
alu_opcode <= "0010";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x06 SUB IMMEDIATE SIGNED
when "000110" =>
op_select_b <= '1';
alu_en <= '1';
alu_opcode <= "0010";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x07 SUB REGISTER UNSIGNED
when "000111" =>
op_select_b <= '0';
alu_en <= '1';
alu_opcode <= "0011";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
-- 0x08 SUB IMMEDIATE UNSIGNED
when "001000" =>
op_select_b <= '1';
alu_en <= '1';
alu_opcode <= "0011";
mem_opcode <= "000";
wb_en <= '1';
wb_select <= '0';
pc_select <= "00";
pc_opcode <= "000";
cond_opcode <= "00";
end case;
-- push stack down
reg_stack_bottom <= reg_stack_top;
reg_stack_top <= reg_addr_a;
end if;
end process decode;
end architecture instruction_decoder_arch;
|
mit
|
3e63c886f684c5768a43ce0944598f2b
| 0.561535 | 3.157868 | false | false | false | false |
jpendlum/crash
|
fpga/src/toplevel_testbench/axis_interconnect_8x8.vhd
| 2 | 17,404 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: axis_interconnect_8x8_dummy.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Simplified version of AXI-Stream interconnect made for
-- simulation purposes only.
--
-------------------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axis_interconnect_8x8 is
port (
aclk : in std_logic;
aresetn : in std_logic;
s00_axis_aclk : in std_logic;
s01_axis_aclk : in std_logic;
s02_axis_aclk : in std_logic;
s03_axis_aclk : in std_logic;
s04_axis_aclk : in std_logic;
s05_axis_aclk : in std_logic;
s06_axis_aclk : in std_logic;
s07_axis_aclk : in std_logic;
s00_axis_aresetn : in std_logic;
s01_axis_aresetn : in std_logic;
s02_axis_aresetn : in std_logic;
s03_axis_aresetn : in std_logic;
s04_axis_aresetn : in std_logic;
s05_axis_aresetn : in std_logic;
s06_axis_aresetn : in std_logic;
s07_axis_aresetn : in std_logic;
s00_axis_tvalid : in std_logic;
s01_axis_tvalid : in std_logic;
s02_axis_tvalid : in std_logic;
s03_axis_tvalid : in std_logic;
s04_axis_tvalid : in std_logic;
s05_axis_tvalid : in std_logic;
s06_axis_tvalid : in std_logic;
s07_axis_tvalid : in std_logic;
s00_axis_tready : out std_logic;
s01_axis_tready : out std_logic;
s02_axis_tready : out std_logic;
s03_axis_tready : out std_logic;
s04_axis_tready : out std_logic;
s05_axis_tready : out std_logic;
s06_axis_tready : out std_logic;
s07_axis_tready : out std_logic;
s00_axis_tdata : in std_logic_vector(63 downto 0);
s01_axis_tdata : in std_logic_vector(63 downto 0);
s02_axis_tdata : in std_logic_vector(63 downto 0);
s03_axis_tdata : in std_logic_vector(63 downto 0);
s04_axis_tdata : in std_logic_vector(63 downto 0);
s05_axis_tdata : in std_logic_vector(63 downto 0);
s06_axis_tdata : in std_logic_vector(63 downto 0);
s07_axis_tdata : in std_logic_vector(63 downto 0);
s00_axis_tlast : in std_logic;
s01_axis_tlast : in std_logic;
s02_axis_tlast : in std_logic;
s03_axis_tlast : in std_logic;
s04_axis_tlast : in std_logic;
s05_axis_tlast : in std_logic;
s06_axis_tlast : in std_logic;
s07_axis_tlast : in std_logic;
s00_axis_tdest : in std_logic_vector(2 downto 0);
s01_axis_tdest : in std_logic_vector(2 downto 0);
s02_axis_tdest : in std_logic_vector(2 downto 0);
s03_axis_tdest : in std_logic_vector(2 downto 0);
s04_axis_tdest : in std_logic_vector(2 downto 0);
s05_axis_tdest : in std_logic_vector(2 downto 0);
s06_axis_tdest : in std_logic_vector(2 downto 0);
s07_axis_tdest : in std_logic_vector(2 downto 0);
s00_axis_tid : in std_logic_vector(2 downto 0);
s01_axis_tid : in std_logic_vector(2 downto 0);
s02_axis_tid : in std_logic_vector(2 downto 0);
s03_axis_tid : in std_logic_vector(2 downto 0);
s04_axis_tid : in std_logic_vector(2 downto 0);
s05_axis_tid : in std_logic_vector(2 downto 0);
s06_axis_tid : in std_logic_vector(2 downto 0);
s07_axis_tid : in std_logic_vector(2 downto 0);
m00_axis_aclk : in std_logic;
m01_axis_aclk : in std_logic;
m02_axis_aclk : in std_logic;
m03_axis_aclk : in std_logic;
m04_axis_aclk : in std_logic;
m05_axis_aclk : in std_logic;
m06_axis_aclk : in std_logic;
m07_axis_aclk : in std_logic;
m00_axis_aresetn : in std_logic;
m01_axis_aresetn : in std_logic;
m02_axis_aresetn : in std_logic;
m03_axis_aresetn : in std_logic;
m04_axis_aresetn : in std_logic;
m05_axis_aresetn : in std_logic;
m06_axis_aresetn : in std_logic;
m07_axis_aresetn : in std_logic;
m00_axis_tvalid : out std_logic;
m01_axis_tvalid : out std_logic;
m02_axis_tvalid : out std_logic;
m03_axis_tvalid : out std_logic;
m04_axis_tvalid : out std_logic;
m05_axis_tvalid : out std_logic;
m06_axis_tvalid : out std_logic;
m07_axis_tvalid : out std_logic;
m00_axis_tready : in std_logic;
m01_axis_tready : in std_logic;
m02_axis_tready : in std_logic;
m03_axis_tready : in std_logic;
m04_axis_tready : in std_logic;
m05_axis_tready : in std_logic;
m06_axis_tready : in std_logic;
m07_axis_tready : in std_logic;
m00_axis_tdata : out std_logic_vector(63 downto 0);
m01_axis_tdata : out std_logic_vector(63 downto 0);
m02_axis_tdata : out std_logic_vector(63 downto 0);
m03_axis_tdata : out std_logic_vector(63 downto 0);
m04_axis_tdata : out std_logic_vector(63 downto 0);
m05_axis_tdata : out std_logic_vector(63 downto 0);
m06_axis_tdata : out std_logic_vector(63 downto 0);
m07_axis_tdata : out std_logic_vector(63 downto 0);
m00_axis_tlast : out std_logic;
m01_axis_tlast : out std_logic;
m02_axis_tlast : out std_logic;
m03_axis_tlast : out std_logic;
m04_axis_tlast : out std_logic;
m05_axis_tlast : out std_logic;
m06_axis_tlast : out std_logic;
m07_axis_tlast : out std_logic;
m00_axis_tdest : out std_logic_vector(2 downto 0);
m01_axis_tdest : out std_logic_vector(2 downto 0);
m02_axis_tdest : out std_logic_vector(2 downto 0);
m03_axis_tdest : out std_logic_vector(2 downto 0);
m04_axis_tdest : out std_logic_vector(2 downto 0);
m05_axis_tdest : out std_logic_vector(2 downto 0);
m06_axis_tdest : out std_logic_vector(2 downto 0);
m07_axis_tdest : out std_logic_vector(2 downto 0);
m00_axis_tid : out std_logic_vector(2 downto 0);
m01_axis_tid : out std_logic_vector(2 downto 0);
m02_axis_tid : out std_logic_vector(2 downto 0);
m03_axis_tid : out std_logic_vector(2 downto 0);
m04_axis_tid : out std_logic_vector(2 downto 0);
m05_axis_tid : out std_logic_vector(2 downto 0);
m06_axis_tid : out std_logic_vector(2 downto 0);
m07_axis_tid : out std_logic_vector(2 downto 0);
s00_decode_err : out std_logic;
s01_decode_err : out std_logic;
s02_decode_err : out std_logic;
s03_decode_err : out std_logic;
s04_decode_err : out std_logic;
s05_decode_err : out std_logic;
s06_decode_err : out std_logic;
s07_decode_err : out std_logic;
s00_fifo_data_count : out std_logic_vector(31 downto 0);
m00_fifo_data_count : out std_logic_vector(31 downto 0));
end entity;
architecture RTL of axis_interconnect_8x8 is
component fifo_axis_64x4096
port (
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(63 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(63 downto 0);
m_axis_tlast : out std_logic;
axis_overflow : out std_logic;
axis_underflow : out std_logic);
end component;
type int_arr_8 is array(0 to 7) of integer;
type slv_8x64 is array(0 to 7) of std_logic_vector(63 downto 0);
type slv_8x3 is array(0 to 7) of std_logic_vector(2 downto 0);
signal m_axis_map : int_arr_8 := (0,0,0,0,0,0,0,0);
signal m_axis_busy : std_logic_vector(7 downto 0);
signal s_axis_tvalid : std_logic_vector(7 downto 0);
signal s_axis_tready : std_logic_vector(7 downto 0);
signal s_axis_tlast : std_logic_vector(7 downto 0);
signal s_axis_tdata : slv_8x64;
signal s_axis_tdest : slv_8x3;
signal s_axis_tid : slv_8x3;
signal m_axis_tvalid : std_logic_vector(7 downto 0);
signal m_axis_tready : std_logic_vector(7 downto 0);
signal m_axis_tlast : std_logic_vector(7 downto 0);
signal m_axis_tdata : slv_8x64;
signal m_axis_tdest : slv_8x3;
signal m_axis_tid : slv_8x3;
begin
gen_all : for i in 0 to 7 generate
proc_round_robin : process(aclk,aresetn)
begin
if (aresetn = '0') then
m_axis_map(i) <= 0;
m_axis_busy(i) <= '0';
else
if rising_edge(aclk) then
if (s_axis_tdest(m_axis_map(i)) = std_logic_vector(to_unsigned(i,3)) AND
s_axis_tvalid(m_axis_map(i)) = '1' AND m_axis_busy(i) = '0') then
m_axis_busy(i) <= '1';
else
if (m_axis_busy(i) = '0') then
if (m_axis_map(i) = 7) then
m_axis_map(i) <= 0;
else
m_axis_map(i) <= m_axis_map(i) + 1;
end if;
end if;
end if;
if (m_axis_busy(i) = '1' AND s_axis_tlast(m_axis_map(i)) = '1' AND s_axis_tvalid(m_axis_map(i)) = '1') then
m_axis_busy(i) <= '0';
if (m_axis_map(i) = 7) then
m_axis_map(i) <= 0;
else
m_axis_map(i) <= m_axis_map(i) + 1;
end if;
end if;
end if;
end if;
end process;
m_axis_tdest(i) <= (others=>'0') when m_axis_busy(i) = '0' else
s_axis_tdest(m_axis_map(i));
m_axis_tid(i) <= (others=>'0') when m_axis_busy(i) = '0' else
s_axis_tid(m_axis_map(i));
m_axis_tdata(i) <= (others=>'0') when m_axis_busy(i) = '0' else
s_axis_tdata(m_axis_map(i));
m_axis_tvalid(i) <= '0' when m_axis_busy(i) = '0' else
s_axis_tvalid(m_axis_map(i));
m_axis_tlast(i) <= '0' when m_axis_busy(i) = '0' else
s_axis_tlast(m_axis_map(i));
s_axis_tready(i) <= m_axis_tready(0) when m_axis_map(0) = i AND m_axis_busy(0) = '1' else
m_axis_tready(1) when m_axis_map(1) = i AND m_axis_busy(1) = '1' else
m_axis_tready(2) when m_axis_map(2) = i AND m_axis_busy(2) = '1' else
m_axis_tready(3) when m_axis_map(3) = i AND m_axis_busy(3) = '1' else
m_axis_tready(4) when m_axis_map(4) = i AND m_axis_busy(4) = '1' else
m_axis_tready(5) when m_axis_map(5) = i AND m_axis_busy(5) = '1' else
m_axis_tready(6) when m_axis_map(6) = i AND m_axis_busy(6) = '1' else
m_axis_tready(7) when m_axis_map(7) = i AND m_axis_busy(7) = '1' else '0';
end generate;
slave_fifo_axis_64x4096 : fifo_axis_64x4096
port map (
s_aclk => aclk,
s_aresetn => aresetn,
s_axis_tvalid => s00_axis_tvalid,
s_axis_tready => s00_axis_tready,
s_axis_tdata => s00_axis_tdata,
s_axis_tlast => s00_axis_tlast,
m_axis_tvalid => s_axis_tvalid(0),
m_axis_tready => s_axis_tready(0),
m_axis_tdata => s_axis_tdata(0),
m_axis_tlast => s_axis_tlast(0),
axis_overflow => open,
axis_underflow => open);
--s_axis_tvalid(0) <= s00_axis_tvalid;
--s_axis_tlast(0) <= s00_axis_tlast;
--s_axis_tdata(0) <= s00_axis_tdata;
s_axis_tdest(0) <= s00_axis_tdest;
s_axis_tid(0) <= s00_axis_tid;
--s00_axis_tready <= s_axis_tready(0);
s_axis_tvalid(1) <= s01_axis_tvalid;
s_axis_tlast(1) <= s01_axis_tlast;
s_axis_tdata(1) <= s01_axis_tdata;
s_axis_tdest(1) <= s01_axis_tdest;
s_axis_tid(1) <= s01_axis_tid;
s01_axis_tready <= s_axis_tready(1);
s_axis_tvalid(2) <= s02_axis_tvalid;
s_axis_tlast(2) <= s02_axis_tlast;
s_axis_tdata(2) <= s02_axis_tdata;
s_axis_tdest(2) <= s02_axis_tdest;
s_axis_tid(2) <= s02_axis_tid;
s02_axis_tready <= s_axis_tready(2);
s_axis_tvalid(3) <= s03_axis_tvalid;
s_axis_tlast(3) <= s03_axis_tlast;
s_axis_tdata(3) <= s03_axis_tdata;
s_axis_tdest(3) <= s03_axis_tdest;
s_axis_tid(3) <= s03_axis_tid;
s03_axis_tready <= s_axis_tready(3);
s_axis_tvalid(4) <= s04_axis_tvalid;
s_axis_tlast(4) <= s04_axis_tlast;
s_axis_tdata(4) <= s04_axis_tdata;
s_axis_tdest(4) <= s04_axis_tdest;
s_axis_tid(4) <= s04_axis_tid;
s04_axis_tready <= s_axis_tready(4);
s_axis_tvalid(5) <= s05_axis_tvalid;
s_axis_tlast(5) <= s05_axis_tlast;
s_axis_tdata(5) <= s05_axis_tdata;
s_axis_tdest(5) <= s05_axis_tdest;
s_axis_tid(5) <= s05_axis_tid;
s05_axis_tready <= s_axis_tready(5);
s_axis_tvalid(6) <= s06_axis_tvalid;
s_axis_tlast(6) <= s06_axis_tlast;
s_axis_tdata(6) <= s06_axis_tdata;
s_axis_tdest(6) <= s06_axis_tdest;
s_axis_tid(6) <= s06_axis_tid;
s06_axis_tready <= s_axis_tready(6);
s_axis_tvalid(7) <= s07_axis_tvalid;
s_axis_tlast(7) <= s07_axis_tlast;
s_axis_tdata(7) <= s07_axis_tdata;
s_axis_tdest(7) <= s07_axis_tdest;
s_axis_tid(7) <= s07_axis_tid;
s07_axis_tready <= s_axis_tready(7);
m00_axis_tvalid <= m_axis_tvalid(0);
m00_axis_tlast <= m_axis_tlast(0);
m00_axis_tdata <= m_axis_tdata(0);
m00_axis_tdest <= m_axis_tdest(0);
m00_axis_tid <= m_axis_tid(0);
m_axis_tready(0) <= m00_axis_tready;
m01_axis_tvalid <= m_axis_tvalid(1);
m01_axis_tlast <= m_axis_tlast(1);
m01_axis_tdata <= m_axis_tdata(1);
m01_axis_tdest <= m_axis_tdest(1);
m01_axis_tid <= m_axis_tid(1);
m_axis_tready(1) <= m01_axis_tready;
m02_axis_tvalid <= m_axis_tvalid(2);
m02_axis_tlast <= m_axis_tlast(2);
m02_axis_tdata <= m_axis_tdata(2);
m02_axis_tdest <= m_axis_tdest(2);
m02_axis_tid <= m_axis_tid(2);
m_axis_tready(2) <= m02_axis_tready;
m03_axis_tvalid <= m_axis_tvalid(3);
m03_axis_tlast <= m_axis_tlast(3);
m03_axis_tdata <= m_axis_tdata(3);
m03_axis_tdest <= m_axis_tdest(3);
m03_axis_tid <= m_axis_tid(3);
m_axis_tready(3) <= m03_axis_tready;
m04_axis_tvalid <= m_axis_tvalid(4);
m04_axis_tlast <= m_axis_tlast(4);
m04_axis_tdata <= m_axis_tdata(4);
m04_axis_tdest <= m_axis_tdest(4);
m04_axis_tid <= m_axis_tid(4);
m_axis_tready(4) <= m04_axis_tready;
m05_axis_tvalid <= m_axis_tvalid(5);
m05_axis_tlast <= m_axis_tlast(5);
m05_axis_tdata <= m_axis_tdata(5);
m05_axis_tdest <= m_axis_tdest(5);
m05_axis_tid <= m_axis_tid(5);
m_axis_tready(5) <= m05_axis_tready;
m06_axis_tvalid <= m_axis_tvalid(6);
m06_axis_tlast <= m_axis_tlast(6);
m06_axis_tdata <= m_axis_tdata(6);
m06_axis_tdest <= m_axis_tdest(6);
m06_axis_tid <= m_axis_tid(6);
m_axis_tready(6) <= m06_axis_tready;
m07_axis_tvalid <= m_axis_tvalid(7);
m07_axis_tlast <= m_axis_tlast(7);
m07_axis_tdata <= m_axis_tdata(7);
m07_axis_tdest <= m_axis_tdest(7);
m07_axis_tid <= m_axis_tid(7);
m_axis_tready(7) <= m07_axis_tready;
end RTL;
|
gpl-3.0
|
afc6a5b31272c0d0278dbd145ed78a17
| 0.52465 | 2.996556 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_top.vhd
| 1 | 14,279 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_top
---- Version: 1.0.0
---- Description: CCSDS compliant RX/TX for space communications
---- TX Modulations: BPSK, QPSK, Offset-QPSK, QAM, Offset-QAM
---- RX Performances: QAM: min Eb/N0 = XdB, max frequency shift = X Hz (Doppler + speed), max frequency shift rate = X Hz / secs (Doppler + acceleration), synchronisation, agc / dynamic range, filters capabilities, multipaths, ...
---- This is the entry point / top level entity
---- WB slave interface, RX/TX external inputs/outputs
---- Synchronized with rising edge of clocks
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/26: initial release - only basic RX-TX capabilities through direct R/W on WB Bus / no dynamic configuration capabilities
---- 2016/10/18: major rework / implementation of new architecture
-------------------------------
-- TODO: additionnal modulations: ASK, FSK, GMSK, OFDM, CDMA
-- TODO: dynamic modulation and coding
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ccsds_rxtx_parameters.all;
use work.ccsds_rxtx_functions.all;
--use work.ccsds_rxtx_constants.all;
--=============================================================================
-- Entity declaration for ccsds_rxtx_top / overall rx-tx external physical inputs and outputs
--=============================================================================
entity ccsds_rxtx_top is
generic (
CCSDS_RXTX_RX_AUTO_ENABLED: boolean := RX_SYSTEM_AUTO_ENABLED;
CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH: integer := RX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_TX_AUTO_ENABLED: boolean := TX_SYSTEM_AUTO_ENABLED;
CCSDS_RXTX_TX_AUTO_EXTERNAL: boolean := TX_SYSTEM_AUTO_EXTERNAL;
CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH: integer := TX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_WB_ADDR_BUS_SIZE: integer := RXTX_SYSTEM_WB_ADDR_BUS_SIZE;
CCSDS_RXTX_WB_DATA_BUS_SIZE: integer := RXTX_SYSTEM_WB_DATA_BUS_SIZE
);
port(
-- system wide inputs
--rst_i: in std_logic; -- implement external system reset port?
-- system wide outputs
-- wishbone slave bus connections / to the master CPU
-- wb inputs
wb_adr_i: in std_logic_vector(CCSDS_RXTX_WB_ADDR_BUS_SIZE-1 downto 0); -- address input array
wb_clk_i: in std_logic; -- clock input / wb operations are always on rising edge of clk
wb_cyc_i: in std_logic; -- cycle input / valid bus cycle in progress
wb_dat_i: in std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0); -- data input array
--wb_lock_i: out std_logic; -- lock input / current bus cycle is uninterruptible
wb_rst_i: in std_logic; -- reset input
--wb_sel_i: in std_logic_vector(3 downto 0); -- select input array / related to wb_dat_i + wb_dat_o / indicates where valid data is placed on the array / provide data granularity
wb_stb_i: in std_logic; -- strobe input / slave is selected
--wb_tga_i: in std_logic; -- address tag type / related to wb_adr_i / qualified by wb_stb_i / TBD
--wb_tgc_i: in std_logic; -- cycle tag type / qualified by wb_cyc_i / TBD
--wb_tgd_i: in std_logic; -- data tag type / related to wb_dat_i / ex: parity protection, ecc, timestamps
wb_we_i: in std_logic; -- write enable input / indicates if cycle is of write or read type
-- wb outputs
wb_ack_o: out std_logic; -- acknowledge output / normal bus cycle termination
wb_dat_o: out std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0); -- data output array
wb_err_o: out std_logic; -- error output / abnormal bus cycle termination
wb_rty_o: out std_logic; -- retry output / not ready - retry bus cycle
--wb_tgd_o: out std_logic; -- data tag type / related to wb_dat_o / ex: parity protection, ecc, timestamps
-- RX connections
-- rx inputs
rx_clk_i: in std_logic; -- received samples clock
rx_sam_i_i: in std_logic_vector(CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- i samples
rx_sam_q_i: in std_logic_vector(CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- q samples
-- rx outputs
rx_ena_o: out std_logic; -- rx enabled status indicator
rx_irq_o: out std_logic; -- interrupt request output / data received indicator
-- TX connections
-- tx inputs
tx_clk_i: in std_logic; -- output samples clock
tx_dat_ser_i: in std_logic; -- direct data serial input
-- tx outputs
tx_buf_ful_o: out std_logic; -- buffer full / data overflow indicator
tx_clk_o: out std_logic; -- emitted samples clock
tx_ena_o: out std_logic; -- tx enabled status indicator
tx_idl_o: out std_logic; -- idle status / data-padding indicator
tx_sam_i_o: out std_logic_vector(CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- i samples
tx_sam_q_o: out std_logic_vector(CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0) -- q samples
);
end ccsds_rxtx_top;
--=============================================================================
-- architecture declaration / internal connections
--=============================================================================
architecture structure of ccsds_rxtx_top is
-- components declaration
component ccsds_rx is
generic (
CCSDS_RX_PHYS_SIG_QUANT_DEPTH : integer;
CCSDS_RX_DATA_BUS_SIZE: integer
);
port(
rst_i: in std_logic; -- system reset
ena_i: in std_logic; -- system enable
clk_i: in std_logic; -- input samples clock
sam_i_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
dat_nxt_i: in std_logic; -- next data
irq_o: out std_logic; -- data ready to be read / IRQ signal
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
dat_val_o: out std_logic; -- data valid
buf_dat_ful_o: out std_logic; -- data buffer status indicator
buf_fra_ful_o: out std_logic; -- frames buffer status indicator
buf_bit_ful_o: out std_logic; -- bits buffer status indicator
ena_o: out std_logic -- enabled status indicator
);
end component;
component ccsds_tx is
generic (
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer;
CCSDS_TX_DATA_BUS_SIZE: integer
);
port(
rst_i: in std_logic;
ena_i: in std_logic;
clk_i: in std_logic;
in_sel_i: in std_logic;
dat_val_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
dat_ser_i: in std_logic;
buf_ful_o: out std_logic;
clk_o: out std_logic;
idl_o: out std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
ena_o: out std_logic
);
end component;
signal wire_rst: std_logic;
signal wire_rx_ena: std_logic := convert_boolean_to_std_logic(CCSDS_RXTX_RX_AUTO_ENABLED);
signal wire_rx_data_valid: std_logic;
signal wire_rx_data_next: std_logic := '0';
signal wire_rx_buffer_data_full: std_logic;
signal wire_rx_buffer_frames_full: std_logic;
signal wire_rx_buffer_bits_full: std_logic;
signal wire_tx_clk: std_logic;
signal wire_tx_ena: std_logic := convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_ENABLED);
signal wire_tx_ext: std_logic := convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_EXTERNAL);
signal wire_tx_data_valid: std_logic := '0';
signal wire_tx_buf_ful: std_logic;
signal wire_rx_data: std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0);
signal wire_tx_data: std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0) := (others => '0');
--=============================================================================
-- architecture begin
--=============================================================================
begin
-- components entities instantiation
rx_001: ccsds_rx
generic map(
CCSDS_RX_PHYS_SIG_QUANT_DEPTH => CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH,
CCSDS_RX_DATA_BUS_SIZE => CCSDS_RXTX_WB_DATA_BUS_SIZE
)
port map(
rst_i => wb_rst_i,
ena_i => wire_rx_ena,
clk_i => rx_clk_i,
sam_i_i => rx_sam_i_i,
sam_q_i => rx_sam_q_i,
dat_nxt_i => wire_rx_data_next,
irq_o => rx_irq_o,
dat_o => wire_rx_data,
dat_val_o => wire_rx_data_valid,
buf_dat_ful_o => wire_rx_buffer_data_full,
buf_fra_ful_o => wire_rx_buffer_frames_full,
buf_bit_ful_o => wire_rx_buffer_bits_full,
ena_o => rx_ena_o
);
tx_001: ccsds_tx
generic map(
CCSDS_TX_PHYS_SIG_QUANT_DEPTH => CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH,
CCSDS_TX_DATA_BUS_SIZE => CCSDS_RXTX_WB_DATA_BUS_SIZE
)
port map(
clk_i => tx_clk_i,
rst_i => wb_rst_i,
ena_i => wire_tx_ena,
in_sel_i => wire_tx_ext,
dat_val_i => wire_tx_data_valid,
dat_par_i => wire_tx_data,
dat_ser_i => tx_dat_ser_i,
buf_ful_o => wire_tx_buf_ful,
clk_o => tx_clk_o,
idl_o => tx_idl_o,
sam_i_o => tx_sam_i_o,
sam_q_o => tx_sam_q_o,
ena_o => tx_ena_o
);
tx_buf_ful_o <= wire_tx_buf_ful;
--=============================================================================
-- Begin of wbstartp
-- In charge of wishbone bus interactions + rx/tx management through it
--=============================================================================
-- read: wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_dat_i
-- write: wb_ack_o, wb_err_o, wb_rty_o, (rx_/tx_XXX:rst_i), wb_dat_o, wire_rst, wire_irq, wire_rx_ena, wire_tx_ena
-- r/w: wire_tx_ext
WBSTARTP : process (wb_clk_i)
variable ack_state: std_logic := '0';
-- variables instantiation
begin
-- on each wb clock rising edge
if rising_edge(wb_clk_i) then
-- wb reset signal received
if (wb_rst_i = '1') then
-- reinitialize all dyn elements to default value
ack_state := '0';
wire_rx_ena <= convert_boolean_to_std_logic(CCSDS_RXTX_RX_AUTO_ENABLED);
wire_tx_ena <= convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_ENABLED);
-- reinitialize all outputs
wire_tx_ext <= convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_EXTERNAL);
if (CCSDS_RXTX_TX_AUTO_EXTERNAL = false) then
wire_tx_data_valid <= '0';
else
wire_tx_data_valid <= '1';
end if;
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
else
if (wb_cyc_i = '1') and (wb_stb_i = '1') then
-- single classic standard read cycle
if (wb_we_i = '0') then
if (wb_adr_i = "0000") then
-- classic rx cycle - forward data from rx to master
if (ack_state = '0') then
wb_dat_o <= wire_rx_data;
wb_ack_o <= '0';
ack_state := '1';
else
wb_dat_o <= (others => '0');
wb_ack_o <= '1';
ack_state := '0';
end if;
else
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
-- single write cycle
else
wb_dat_o <= (others => '0');
-- classic tx cycle - store and forward data from master to tx
if (wb_adr_i = "0000") then
-- check internal configuration
if (wire_tx_ext = '0') then
if (wire_tx_buf_ful = '0') and (ack_state = '0') then
wb_ack_o <= '1';
ack_state := '1';
wire_tx_data <= wb_dat_i;
wire_tx_data_valid <= '1';
else
if (ack_state = '1') then
wire_tx_data_valid <= '0';
wb_ack_o <= '0';
ack_state := '0';
else
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
end if;
else
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
-- RX configuration cycle - set general rx parameters
elsif (wb_adr_i = "0001") then
if (ack_state = '0') then
wire_rx_ena <= wb_dat_i(0);
wb_ack_o <= '1';
ack_state := '1';
else
wb_ack_o <= '0';
ack_state := '0';
end if;
-- TX configuration cycle - set general tx parameters
elsif (wb_adr_i = "0010") then
if (ack_state = '0') then
wire_tx_ena <= wb_dat_i(0);
wire_tx_ext <= wb_dat_i(1);
wb_ack_o <= '1';
ack_state := '1';
else
wb_ack_o <= '0';
ack_state := '0';
end if;
else
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
end if;
else
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
ack_state := '0';
if (wire_tx_ext = '0') then
wire_tx_data_valid <= '0';
else
wire_tx_data_valid <= '1';
end if;
end if;
end if;
end if;
end process;
end structure;
--=============================================================================
-- architecture end
--=============================================================================
|
mit
|
eff1855c613ea1caa157569f639f7d59
| 0.524967 | 3.573323 | false | false | false | false |
ziyan/altera-de2-ann
|
src/display/display.vhd
| 1 | 2,298 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package display_types is
type display_mode is (training, running, idle);
end package display_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.display_types.all;
USE work.lcd_types.all;
package display_components is
component display is
PORT (
reset, clock : IN STD_LOGIC;
mode : IN display_mode;
inputs : IN STD_LOGIC_VECTOR(15 downto 0);
class : IN CHAR;
lcd_dd : OUT CHAR_VECTOR(0 to 31);
lcd_cg : OUT CHAR_GRAPHICS_VECTOR(0 to 7)
);
end component;
end package;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE work.display_types.all;
USE work.lcd_types.all;
ENTITY display IS
PORT (
reset, clock : IN STD_LOGIC;
mode : IN display_mode;
inputs : IN STD_LOGIC_VECTOR(15 downto 0);
class : IN CHAR;
lcd_dd : OUT CHAR_VECTOR(0 to 31);
lcd_cg : OUT CHAR_GRAPHICS_VECTOR(0 to 7)
);
END ENTITY display;
ARCHITECTURE display OF display IS
BEGIN
-- character graphics
lcd_cg(0) <=
"00000"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000";
lcd_cg(1) <=
"00000"&
"00000"&
"00000"&
"00000"&
"11111"&
"11111"&
"11111"&
"00000";
lcd_cg(2) <=
"11111"&
"11111"&
"11111"&
"00000"&
"00000"&
"00000"&
"00000"&
"00000";
lcd_cg(3) <=
"11111"&
"11111"&
"11111"&
"00000"&
"11111"&
"11111"&
"11111"&
"00000";
-- switch pattern display
lcd_dd(0) <= "000000" & inputs(15) & inputs(11);
lcd_dd(1) <= "000000" & inputs(14) & inputs(10);
lcd_dd(2) <= "000000" & inputs(13) & inputs(9);
lcd_dd(3) <= "000000" & inputs(12) & inputs(8);
lcd_dd(16) <= "000000" & inputs(7) & inputs(3);
lcd_dd(17) <= "000000" & inputs(6) & inputs(2);
lcd_dd(18) <= "000000" & inputs(5) & inputs(1);
lcd_dd(19) <= "000000" & inputs(4) & inputs(0);
-- NERUAL NET
lcd_dd(4 to 15) <= (x"20", x"4e", x"45", x"55", x"52", x"41", x"4c", x"20", x"4e", x"45", x"54", x"20");
with mode select lcd_dd(20 to 31) <=
-- Training...
(x"20", x"74", x"72", x"61", x"69", x"6e", x"69", x"6e", x"67", x"2e", x"2e", x"2e") when training,
-- Running...
(x"20", x"72", x"75", x"6e", x"6e", x"69", x"6e", x"67", x"2e", x"2e", x"2e", x"20") when running,
-- Pattern:
(x"20", x"70", x"61", x"74", x"74", x"65", x"72", x"6e", x"3a", x"20", class, x"20") when idle;
END ARCHITECTURE display;
|
mit
|
cae8bd0fd18bbf2bbeb19cc35c09d761
| 0.614447 | 2.381347 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
mux_2_32_bit.vhd
| 1 | 1,018 |
-- 2-input 32-bit multiplexer
-- this circuit takes 2 32-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
-- select signal
input_select : in std_logic;
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end entity mux_2_32_bit;
architecture mux_2_32_bit_arch of mux_2_32_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(input_select, in_32_0, in_32_1)
begin
-- select 0 is input 0
if input_select = '0' then
out_32 <= in_32_0;
-- select 1 is input 1
elsif input_select = '1' then
out_32 <= in_32_1;
-- otherwise invalid input signal, output 0
else
out_32 <= (others => '0');
end if;
end process mux;
end architecture mux_2_32_bit_arch;
|
mit
|
1a283118d1057bd408bcf5f94dd862bc
| 0.666012 | 2.773842 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_randomizer.vhd
| 1 | 3,416 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_randomizer
---- Version: 1.0.0
---- Description:
---- Randomize input data with LFSR output sequence
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx randomizer inputs and outputs
--=============================================================================
entity ccsds_tx_randomizer is
generic(
constant CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_randomizer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_randomizer is
component ccsds_rxtx_lfsr is
generic(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal randomizer_sequence: std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
signal wire_lfsr_valid: std_logic;
-- components instanciation and mapping
begin
tx_randomizer_lfsr: ccsds_rxtx_lfsr
generic map(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE => CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_o => wire_lfsr_valid,
dat_o => randomizer_sequence
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of randp
-- Randomize data using LFSR register
--=============================================================================
-- read: rst_i, dat_val_i, dat_i, randomizer_sequence, wire_lfsr_valid
-- write: dat_o, dat_val_o
-- r/w:
RANDP: process (clk_i)
variable data_randomized: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
data_randomized := '0';
dat_val_o <= '0';
else
if (dat_val_i = '1') and (wire_lfsr_valid = '1') then
dat_val_o <= '1';
dat_o <= dat_i xor randomizer_sequence;
data_randomized := '1';
else
dat_val_o <= '0';
if (data_randomized = '0') then
dat_o <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end structure;
|
mit
|
a7cfd297220cc06a34fc04c710c28e4e
| 0.493852 | 4.150668 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
program_counter.vhd
| 1 | 6,520 |
-- program counter circuit
-- combines a register and a call/return stack into a program counter with 6 modes
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
-- 000 - increment by constant value (4)
-- 001 - set to value
-- 010 - offset by value
-- 100 - push to stack and set to value
-- 101 - push to stack and offset by value
-- 110 - pop top value from stack
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity program_counter is
port (
-- value for set/offset
val_32 : in std_logic_vector(31 downto 0);
-- clock, rst, clr, en inputs
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
en : in std_logic;
-- opcode
opcode : in std_logic_vector(2 downto 0);
-- address out
addr_32 : out std_logic_vector(31 downto 0)
);
end entity program_counter;
architecture program_counter_arch of program_counter is
-- component declarations
-- controller component
component pc_controller is
port (
-- opcode
opcode : in std_logic_vector(2 downto 0);
-- control signals
stack_push : out std_logic;
pc_value_select : out std_logic_vector(1 downto 0);
inc_select : out std_logic;
stack_clk_enable : out std_logic
);
end component;
-- register component
component reg_32_bit is
port (
-- input
in_32 : in std_logic_vector(31 downto 0);
-- clk, rst, clr
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
-- write enable
wr_en : in std_logic;
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- stack component
component stack_32_bit is
port (
-- top of stack write
stack_top_write : in std_logic_vector(31 downto 0);
-- push, clk, clk_en, rst
push : in std_logic;
clk : in std_logic;
clk_enable : in std_logic;
rst : in std_logic;
-- top of stack read
stack_top_read : out std_logic_vector(31 downto 0)
);
end component;
-- incrementer component
component incrementer_32_bit is
port (
-- inputs
a_32 : in std_logic_vector(31 downto 0);
b_32 : in std_logic_vector(31 downto 0);
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- 4-input 32-bit mux component
component mux_4_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
in_32_2 : in std_logic_vector(31 downto 0);
in_32_3 : in std_logic_vector(31 downto 0);
-- input select
input_select : in std_logic_vector(1 downto 0);
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- 2-input 32-bit mux component
component mux_2_32_bit is
port (
-- inputs
in_32_0 : in std_logic_vector(31 downto 0);
in_32_1 : in std_logic_vector(31 downto 0);
-- input select
input_select : in std_logic;
-- output
out_32 : out std_logic_vector(31 downto 0)
);
end component;
-- signal declarations
-- pc output signal
signal reg_out : std_logic_vector(31 downto 0);
-- pc reg input
signal reg_in : std_logic_vector(31 downto 0);
-- control signals from controller
signal val_select : std_logic_vector(1 downto 0);
signal offset_select : std_logic;
signal stack_push : std_logic;
signal stack_clk_en : std_logic;
-- stack top in and out
signal stack_top_in : std_logic_vector(31 downto 0);
signal stack_top_out : std_logic_vector(31 downto 0);
-- offset result signal
signal offset_result : std_logic_vector(31 downto 0);
-- offset input a signal
signal offset_inc_a : std_logic_vector(31 downto 0);
begin
-- design implementation
-- controller instantiation
controller : pc_controller
port map (
-- opcode mapped to opcode input
opcode => opcode,
-- stack push mapped to stack push signal
stack_push => stack_push,
-- pc val select mapped to val select signal
pc_value_select => val_select,
-- inc select mapped to offset select signal
inc_select => offset_select,
-- stack clock enable mapped to stack clock enable signal
stack_clk_enable => stack_clk_en
);
-- register insantiation
reg : reg_32_bit
port map (
-- input mapped to reg in signal
in_32 => reg_in,
-- clk, rst and clr inputs mapped to clk, rst and clr inputs
clk => clk,
rst => rst,
clr => clr,
-- wr en mapped to en input
wr_en => en,
-- output mapped to reg out signal
out_32 => reg_out
);
-- stack instantiation
stack : stack_32_bit
port map (
-- stack top write mapped to stack top in signal
stack_top_write => stack_top_in,
-- push mapped to stack_push signal
push => stack_push,
-- clk mapped to clk input
clk => clk,
-- clk_enable mapped to stack_clk_en signal
clk_enable => stack_clk_en,
-- rst mapped to rst input
rst => rst,
-- stack top read mapped to stack top out signal
stack_top_read => stack_top_out
);
-- 4-input set mux instantiation
set_mux : mux_4_32_bit
port map (
-- input 0 is offset result
in_32_0 => offset_result,
-- input 1 is set value
in_32_1 => val_32,
-- input 2 is top of stack
in_32_2 => stack_top_out,
-- input 3 is 0
in_32_3 => (others => '0'),
-- input select mapped to val select signal
input_select => val_select,
-- output mapped to reg in signal
out_32 => reg_in
);
-- 2-input offset mux instantiation
offset_mux : mux_2_32_bit
port map (
-- input 0 is constant 4
in_32_0 => (2 => '1', others => '0'),
-- input 1 is input value
in_32_1 => val_32,
-- input select mapped to offset select signal
input_select => offset_select,
-- output mapped to offset operand a
out_32 => offset_inc_a
);
-- offset incrementer instantiation
offset_inc : incrementer_32_bit
port map (
-- operand a is offset operand a from mux
a_32 => offset_inc_a,
-- operand b is current value of register
b_32 => reg_out,
-- result mapped to offset result signal
out_32 => offset_result
);
-- stack top write incrementer instantiation
stack_top_inc : incrementer_32_bit
port map (
-- operand a is current value of register
a_32 => reg_out,
-- operand b is constant 4
b_32 => (2 => '1', others => '0'),
-- output mapped to stack top in
out_32 => stack_top_in
);
-- set address output to current register value
addr_32 <= reg_out;
end architecture program_counter_arch;
|
mit
|
c5baedc273914df64912bcb71b132884
| 0.632209 | 2.792291 | false | false | false | false |
jpendlum/crash
|
fpga/src/ps_pl_interface/axi_lite_to_parallel_bus.vhd
| 2 | 7,545 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: axi_lite_to_parallel_bus.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Converts a AXI-4 Lite slave interface to a simple parallel
-- address + data interface.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity axi_lite_to_parallel_bus is
generic (
-- 32K word address space
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
read_addr : out std_logic_vector(14 downto 0);
read_data : in std_logic_vector(31 downto 0);
read_stb : out std_logic;
write_addr : out std_logic_vector(14 downto 0);
write_data : out std_logic_vector(31 downto 0);
write_stb : out std_logic);
end entity;
architecture RTL of axi_lite_to_parallel_bus is
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
type read_state_type is (READ_IDLE,WAIT_FOR_READ_DATA,SET_READ_DATA_VALID);
type write_state_type is (WRITE_IDLE,WAIT_FOR_WVALID,WAIT_TO_WRITE_DATA);
signal read_state : read_state_type;
signal write_state : write_state_type;
begin
-----------------------------------------------------------------------------
-- State machine for Read Interface
-----------------------------------------------------------------------------
proc_read_state_machine : process(S_AXI_ACLK,S_AXI_ARESETN)
begin
if (S_AXI_ARESETN = '0') then
S_AXI_ARREADY <= '0';
S_AXI_RVALID <= '0';
S_AXI_RDATA <= (others=>'0');
read_addr <= (others=>'0');
read_stb <= '0';
read_state <= READ_IDLE;
else
if rising_edge(S_AXI_ACLK) then
case read_state is
when READ_IDLE =>
read_stb <= '0';
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
if (S_AXI_ARVALID = '1') then
-- ARREADY is held low until ARVALID is asserted.
-- This may seem a little backwards, but this is similar to Xilinx's
-- AXI4-Lite IPIF LogiCore documentation.
S_AXI_ARREADY <= '1';
-- Bus access is assumed to be by words so the lower 2 bits are not needed.
read_addr <= S_AXI_ARADDR(16 downto 2) - C_BASEADDR(16 downto 2);
read_stb <= '1';
read_state <= WAIT_FOR_READ_DATA;
end if;
-- Wait a single cycle for the strobe signal to propagate and
-- read_data to update
when WAIT_FOR_READ_DATA =>
S_AXI_ARREADY <= '0';
read_stb <= '0';
read_state <= SET_READ_DATA_VALID;
when SET_READ_DATA_VALID =>
if (S_AXI_RREADY = '1') then
S_AXI_RVALID <= '1';
S_AXI_RDATA <= read_data;
read_state <= READ_IDLE;
end if;
when others =>
read_state <= READ_IDLE;
end case;
end if;
end if;
end process;
S_AXI_RRESP <= "00";
-----------------------------------------------------------------------------
-- State machine for Write Interface
-----------------------------------------------------------------------------
proc_write_state_machine : process(S_AXI_ACLK,S_AXI_ARESETN)
begin
if (S_AXI_ARESETN = '0') then
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_addr <= (others=>'0');
write_data <= (others=>'0');
write_stb <= '0';
write_state <= WRITE_IDLE;
else
if rising_edge(S_AXI_ACLK) then
case write_state is
when WRITE_IDLE =>
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_stb <= '0';
if (S_AXI_AWVALID = '1') then
S_AXI_AWREADY <= '1';
write_addr <= S_AXI_AWADDR(16 downto 2) - C_BASEADDR(16 downto 2);
if (S_AXI_WVALID = '1') then
S_AXI_WREADY <= '1';
write_data <= S_AXI_WDATA;
write_stb <= '1';
write_state <= WAIT_TO_WRITE_DATA;
else
write_state <= WAIT_FOR_WVALID;
end if;
end if;
when WAIT_FOR_WVALID =>
S_AXI_AWREADY <= '0';
if (S_AXI_WVALID = '1') then
S_AXI_WREADY <= '1';
write_data <= S_AXI_WDATA;
write_stb <= '1';
write_state <= WAIT_TO_WRITE_DATA;
end if;
when WAIT_TO_WRITE_DATA =>
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
write_stb <= '0';
write_state <= WRITE_IDLE;
when others =>
write_state <= WRITE_IDLE;
end case;
end if;
end if;
end process;
S_AXI_BRESP <= "00";
S_AXI_BVALID <= S_AXI_BREADY;
end architecture;
|
gpl-3.0
|
645d703969e8523abf8c4fd1a80b2b6e
| 0.444798 | 4.145604 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/InputFIFOTb.vhd
| 1 | 4,797 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/7/22 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* released
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Simple testbench for manual signal inspection of inputFIFO.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity InputFIFO_tb is
end InputFIFO_tb;
-------------------------------------------------------------------------------
architecture tb of InputFIFO_tb is
component InputFIFO
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DInxDI : in std_logic_vector(31 downto 0);
WExSI : in std_logic;
StopOutputxSI : in std_logic;
BusyxSO : out std_logic;
DOutxDO : out std_logic_vector(7 downto 0);
OutStrobexSO : out std_logic;
LengthxDO : out integer range 0 to 2048);
end component;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal DInxDI : std_logic_vector(31 downto 0) := (others => '0');
signal WExSI : std_logic := '0';
signal StopOutputxSI : std_logic := '0';
signal BusyxSO : std_logic;
signal DOutxDO : std_logic_vector(7 downto 0);
signal OutStrobexSO : std_logic;
signal LengthxDO : integer range 0 to 2048;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : InputFIFO
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
DInxDI => DInxDI,
WExSI => WExSI,
StopOutputxSI => StopOutputxSI,
BusyxSO => BusyxSO,
DOutxDO => DOutxDO,
OutStrobexSO => OutStrobexSO,
LengthxDO => LengthxDO);
-- clock generation
Clk <= not Clk after 10 ns;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
begin
wait for 10 ns;
RstxRI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
DInxDI <= x"03020100";
WExSI <= '1';
StopOutputxSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
DInxDI <= x"07060504";
WExSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
DInxDI <= x"0b0a0908";
WExSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
DInxDI <= x"0f0e0d0c";
WExSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
DInxDI <= x"00000000";
WExSI <= '0';
-- tell DUT to send one byte every second cycle
for i in 0 to 15 loop
wait until ClkxCI'event and ClkxCI = '1';
StopOutputxSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
StopOutputxSI <= '1';
end loop;
wait;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration InputFIFO_tb_tb_cfg of InputFIFO_tb is
for tb
end for;
end InputFIFO_tb_tb_cfg;
-------------------------------------------------------------------------------
|
gpl-2.0
|
7873293986ce818414e8987732252075
| 0.476548 | 4.666342 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/sram/sram.vhd
| 1 | 3,812 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package sram_types is
subtype sram_address is std_logic_vector(16 downto 0);
subtype sram_data is std_logic_vector(31 downto 0);
type sram_mode is ( idle, read, write );
end package sram_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sram_types.all;
package sram_components is
component sram is
PORT (
reset, clock : IN STD_LOGIC;
addr : IN sram_address;
input : IN sram_data;
output : OUT sram_data;
mode : IN sram_mode;
ready : OUT STD_LOGIC;
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SRAM Data bus 16 Bits
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- SRAM Address bus 18 Bits
SRAM_UB_N : OUT STD_LOGIC; -- SRAM High-byte Data Mask
SRAM_LB_N : OUT STD_LOGIC; -- SRAM Low-byte Data Mask
SRAM_WE_N : OUT STD_LOGIC; -- SRAM Write Enable
SRAM_CE_N : OUT STD_LOGIC; -- SRAM Chip Enable
SRAM_OE_N : OUT STD_LOGIC -- SRAM Output Enable
);
end component;
end package sram_components;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE work.sram_types.all;
ENTITY sram IS
PORT (
reset, clock : IN STD_LOGIC;
addr : IN sram_address;
input : IN sram_data;
output : OUT sram_data;
mode : IN sram_mode;
ready : OUT STD_LOGIC;
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- SRAM Data bus 16 Bits
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- SRAM Address bus 18 Bits
SRAM_UB_N : OUT STD_LOGIC; -- SRAM High-byte Data Mask
SRAM_LB_N : OUT STD_LOGIC; -- SRAM Low-byte Data Mask
SRAM_WE_N : OUT STD_LOGIC; -- SRAM Write Enable
SRAM_CE_N : OUT STD_LOGIC; -- SRAM Chip Enable
SRAM_OE_N : OUT STD_LOGIC -- SRAM Output Enable
);
END ENTITY sram;
ARCHITECTURE sram OF sram IS
TYPE states IS (init, idle, read_low, read_high, write_low, write_high, write_complete);
SIGNAL state : states := idle;
SIGNAL sram_address : sram_address := (others => '0');
SIGNAL sram_word, sram_we : std_logic := '0';
SIGNAL sram_input : sram_data := (others => '0');
SIGNAL sram_output : sram_data := (others => '0');
BEGIN
output <= sram_output;
SRAM_UB_N <= not sram_word;
SRAM_LB_N <= not sram_word;
SRAM_WE_N <= not sram_we;
SRAM_CE_N <= '0';
SRAM_OE_N <= '0';
fsm: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
sram_we <= '0'; sram_word <= '0';
state <= init;
ELSIF (clock = '1' AND clock'event) THEN
CASE state IS
WHEN init =>
ready <= '0';
sram_we <= '0'; sram_word <= '0';
state <= idle;
WHEN idle =>
CASE mode IS
WHEN idle =>
ready <= '1';
sram_we <= '0'; sram_word <= '0';
state <= idle;
WHEN read =>
ready <= '0';
sram_address <= addr;
SRAM_ADDR <= sram_address & "0";
sram_word <= '1';
state <= read_low;
WHEN write =>
ready <= '0';
sram_input <= input;
sram_address <= addr;
SRAM_ADDR <= sram_address & "0";
SRAM_DQ <= sram_input(15 downto 0);
sram_we <= '1'; sram_word <= '1';
state <= write_low;
WHEN others =>
state <= idle;
END CASE;
WHEN read_low =>
SRAM_DQ <= (others => 'Z');
sram_output(15 downto 0) <= SRAM_DQ;
SRAM_ADDR <= sram_address & "1";
state <= read_high;
WHEN read_high =>
SRAM_DQ <= (others => 'Z');
sram_output(31 downto 16) <= SRAM_DQ;
sram_word <= '0';
ready <= '1';
state <= idle;
WHEN write_low =>
sram_word <= '0';
state <= write_high;
WHEN write_high =>
SRAM_ADDR <= sram_address & "1";
SRAM_DQ <= sram_input(31 downto 16);
sram_word <= '1';
state <= write_complete;
WHEN write_complete =>
sram_word <= '0';
sram_we <= '0';
ready <= '1';
state <= idle;
WHEN others =>
state <= init;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE sram;
|
mit
|
99ff3a6c5021eddbe22cc47da5c65716
| 0.609391 | 2.809138 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
register_file.vhd
| 1 | 7,113 |
-- register file circuit
-- contains 31 32-bit general-purpose registers, plus 1 register that is always hardcoded to 0
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity register_file is
port (
-- read addresses
a_addr : in std_logic_vector(4 downto 0);
b_addr : in std_logic_vector(4 downto 0);
-- read data
a_data : out std_logic_vector(31 downto 0);
b_data : out std_logic_vector(31 downto 0);
-- write address, enable, clock and data
wr_addr : in std_logic_vector(4 downto 0);
wr_data : in std_logic_vector(31 downto 0);
wr_enable : in std_logic;
wr_clk : in std_logic;
-- async reset
rst : in std_logic
);
end entity register_file;
architecture register_file_arch of register_file is
-- signal declarations
-- registers
signal r01 : std_logic_vector(31 downto 0);
signal r02 : std_logic_vector(31 downto 0);
signal r03 : std_logic_vector(31 downto 0);
signal r04 : std_logic_vector(31 downto 0);
signal r05 : std_logic_vector(31 downto 0);
signal r06 : std_logic_vector(31 downto 0);
signal r07 : std_logic_vector(31 downto 0);
signal r08 : std_logic_vector(31 downto 0);
signal r09 : std_logic_vector(31 downto 0);
signal r10 : std_logic_vector(31 downto 0);
signal r11 : std_logic_vector(31 downto 0);
signal r12 : std_logic_vector(31 downto 0);
signal r13 : std_logic_vector(31 downto 0);
signal r14 : std_logic_vector(31 downto 0);
signal r15 : std_logic_vector(31 downto 0);
signal r16 : std_logic_vector(31 downto 0);
signal r17 : std_logic_vector(31 downto 0);
signal r18 : std_logic_vector(31 downto 0);
signal r19 : std_logic_vector(31 downto 0);
signal r20 : std_logic_vector(31 downto 0);
signal r21 : std_logic_vector(31 downto 0);
signal r22 : std_logic_vector(31 downto 0);
signal r23 : std_logic_vector(31 downto 0);
signal r24 : std_logic_vector(31 downto 0);
signal r25 : std_logic_vector(31 downto 0);
signal r26 : std_logic_vector(31 downto 0);
signal r27 : std_logic_vector(31 downto 0);
signal r28 : std_logic_vector(31 downto 0);
signal r29 : std_logic_vector(31 downto 0);
signal r30 : std_logic_vector(31 downto 0);
signal r31 : std_logic_vector(31 downto 0);
-- constant r0 which is hardcoded 0
constant r00 : std_logic_vector(31 downto 0) := (others => '0');
begin
-- design implementation
registers : process(a_addr, b_addr, wr_clk, rst)
begin
-- if reset high, clear all registers
if rst = '1' then
r01 <= r00;
r02 <= r00;
r03 <= r00;
r04 <= r00;
r05 <= r00;
r06 <= r00;
r07 <= r00;
r08 <= r00;
r09 <= r00;
r10 <= r00;
r11 <= r00;
r12 <= r00;
r13 <= r00;
r14 <= r00;
r15 <= r00;
r16 <= r00;
r17 <= r00;
r18 <= r00;
r19 <= r00;
r20 <= r00;
r21 <= r00;
r22 <= r00;
r23 <= r00;
r24 <= r00;
r25 <= r00;
r26 <= r00;
r27 <= r00;
r28 <= r00;
r29 <= r00;
r30 <= r00;
r31 <= r00;
else
-- reading from registers, outputting to ports a and b
-- case statements for a
case a_addr is
-- 32 register cases, including r00
when "00000" => a_data <= r00;
when "00001" => a_data <= r01;
when "00010" => a_data <= r02;
when "00011" => a_data <= r03;
when "00100" => a_data <= r04;
when "00101" => a_data <= r05;
when "00110" => a_data <= r06;
when "00111" => a_data <= r07;
when "01000" => a_data <= r08;
when "01001" => a_data <= r09;
when "01010" => a_data <= r10;
when "01011" => a_data <= r11;
when "01100" => a_data <= r12;
when "01101" => a_data <= r13;
when "01110" => a_data <= r14;
when "01111" => a_data <= r15;
when "10000" => a_data <= r16;
when "10001" => a_data <= r17;
when "10010" => a_data <= r18;
when "10011" => a_data <= r19;
when "10100" => a_data <= r20;
when "10101" => a_data <= r21;
when "10110" => a_data <= r22;
when "10111" => a_data <= r23;
when "11000" => a_data <= r24;
when "11001" => a_data <= r25;
when "11010" => a_data <= r26;
when "11011" => a_data <= r27;
when "11100" => a_data <= r28;
when "11101" => a_data <= r29;
when "11110" => a_data <= r30;
when "11111" => a_data <= r31;
-- exception case
when others => a_data <= r00;
end case;
-- case statements for b
case b_addr is
-- 32 register cases, including r00
when "00000" => b_data <= r00;
when "00001" => b_data <= r01;
when "00010" => b_data <= r02;
when "00011" => b_data <= r03;
when "00100" => b_data <= r04;
when "00101" => b_data <= r05;
when "00110" => b_data <= r06;
when "00111" => b_data <= r07;
when "01000" => b_data <= r08;
when "01001" => b_data <= r09;
when "01010" => b_data <= r10;
when "01011" => b_data <= r11;
when "01100" => b_data <= r12;
when "01101" => b_data <= r13;
when "01110" => b_data <= r14;
when "01111" => b_data <= r15;
when "10000" => b_data <= r16;
when "10001" => b_data <= r17;
when "10010" => b_data <= r18;
when "10011" => b_data <= r19;
when "10100" => b_data <= r20;
when "10101" => b_data <= r21;
when "10110" => b_data <= r22;
when "10111" => b_data <= r23;
when "11000" => b_data <= r24;
when "11001" => b_data <= r25;
when "11010" => b_data <= r26;
when "11011" => b_data <= r27;
when "11100" => b_data <= r28;
when "11101" => b_data <= r29;
when "11110" => b_data <= r30;
when "11111" => b_data <= r31;
-- exception case
when others => b_data <= r00;
end case;
-- writing to registers
if rising_edge(wr_clk) then
if wr_enable = '1' then
-- case statement for writing to register
case wr_addr is
-- note exclusion of address 00000, r00 cannot be written to
when "00001" => r01 <= wr_data;
when "00010" => r02 <= wr_data;
when "00011" => r03 <= wr_data;
when "00100" => r04 <= wr_data;
when "00101" => r05 <= wr_data;
when "00110" => r06 <= wr_data;
when "00111" => r07 <= wr_data;
when "01000" => r08 <= wr_data;
when "01001" => r09 <= wr_data;
when "01010" => r10 <= wr_data;
when "01011" => r11 <= wr_data;
when "01100" => r12 <= wr_data;
when "01101" => r13 <= wr_data;
when "01110" => r14 <= wr_data;
when "01111" => r15 <= wr_data;
when "10000" => r16 <= wr_data;
when "10001" => r17 <= wr_data;
when "10010" => r18 <= wr_data;
when "10011" => r19 <= wr_data;
when "10100" => r20 <= wr_data;
when "10101" => r21 <= wr_data;
when "10110" => r22 <= wr_data;
when "10111" => r23 <= wr_data;
when "11000" => r24 <= wr_data;
when "11001" => r25 <= wr_data;
when "11010" => r26 <= wr_data;
when "11011" => r27 <= wr_data;
when "11100" => r28 <= wr_data;
when "11101" => r29 <= wr_data;
when "11110" => r30 <= wr_data;
when "11111" => r31 <= wr_data;
end case;
end if;
end if;
end if;
end process registers;
end architecture register_file_arch;
|
mit
|
2e34e8b736e229e8466d3c4328bd5be2
| 0.567412 | 2.516095 | false | false | false | false |
xuefei1/ElectronicEngineControl
|
niosII_system/synthesis/submodules/solenoid_controller.vhd
| 2 | 2,625 |
-- solenoid_controller.vhd
-- Author: Fred
-- Status: Tested and passed
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity solenoid_controller is
port (
clock : in std_logic := '0'; -- clock
status : out std_logic_vector(7 downto 0) := "00000000"; -- read
control : in std_logic_vector(7 downto 0) := "00000000"; -- write
chip_select : in std_logic := '0'; -- cs
write_enable : in std_logic := '0'; -- write enable
btn_shift_up_in : in std_logic := '0'; -- conduit_end.export
btn_shift_down_in : in std_logic := '0'; -- conduit_end.export
sol_shift_up_out : out std_logic := '0'; -- conduit_end.export
sol_shift_down_out : out std_logic := '0'; -- conduit_end.export
irq_btn_out : out std_logic := '0'; -- conduit_end.export
reset : in std_logic := '0' -- reset
);
end entity solenoid_controller;
architecture ctrl of solenoid_controller is
signal handling_btn : std_logic := '0';
signal handling_control : std_logic := '0';
signal tmp_control : std_logic_vector(7 downto 0) := "00000000";
begin
process(clock, reset)
begin
if(reset = '1') then
irq_btn_out <= '0';
status <= "00000000";
sol_shift_up_out <= '0';
sol_shift_down_out <= '0';
handling_btn <= '0';
handling_control <= '0';
elsif(rising_edge(clock)) then
if(btn_shift_up_in = '1' and handling_btn = '0') then
handling_btn <= '1';
status <= "00000001";
irq_btn_out <= '1';
elsif (btn_shift_down_in = '1' and handling_btn = '0') then
handling_btn <= '1';
status <= "00000010";
irq_btn_out <= '1';
elsif(btn_shift_up_in = '0' and btn_shift_down_in = '0') then
handling_btn <= '0';
status <= "00000000";
end if;
if(write_enable = '1' and chip_select = '1') then
tmp_control <= control;
end if;
if(tmp_control = "00000000") then
sol_shift_up_out <= '0';
sol_shift_down_out <= '0';
elsif(unsigned(tmp_control AND "10000000") = 128) then
irq_btn_out <= '0';
status <= "00000000";
elsif(unsigned(tmp_control AND "00000001") = 1) then
sol_shift_up_out <= '1';
sol_shift_down_out <= '0';
elsif(unsigned(tmp_control AND "00000010") = 2) then
sol_shift_up_out <= '0';
sol_shift_down_out <= '1';
end if;
end if;
end process;
end architecture ctrl; -- of solenoid_controller
|
apache-2.0
|
9ba7205453b4b884e9cd9b2db15f7136
| 0.540571 | 2.979569 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/lfsr/lfsr.vhd
| 1 | 865 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package lfsr_components is
component lfsr is
PORT (
reset, clock : IN STD_LOGIC;
output : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end component;
end package;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY lfsr IS
PORT (
reset, clock : IN STD_LOGIC;
output : OUT STD_LOGIC_VECTOR(15 downto 0)
);
END ENTITY lfsr;
ARCHITECTURE lfsr OF lfsr IS
SIGNAL data : STD_LOGIC_VECTOR(15 downto 0) := x"ACE1";
BEGIN
output <= data;
PROCESS(reset, clock) IS
BEGIN
IF (reset = '1') THEN
data <= x"ACE1";
ELSIF (clock = '1' AND clock'event) THEN
data(15 downto 0) <= data(0 downto 0) & data(15 downto 1);
data(10) <= data(10) xor data(15);
data(12) <= data(12) xor data(15);
data(13) <= data(13) xor data(15);
END IF;
END PROCESS;
output <= data;
END ARCHITECTURE lfsr;
|
mit
|
978d1f5524168d5013d9d96a313e1101
| 0.675145 | 2.772436 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ShiftRegister.vhd
| 1 | 1,633 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:10 10/20/2016
-- Design Name:
-- Module Name: ShiftRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Enable : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal salida : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
Q <= salida;
Registro : process (Clk, Reset, Enable)
begin
if Reset = '0' then
salida <= (others => '0');
elsif Clk'event and Clk = '1' then
if Enable = '1' then
salida (6 downto 0) <= salida (7 downto 1);
salida(7) <= D;
end if;
end if;
end process;
end Behavioral;
|
mit
|
986fa5254887cd90325f52c64b77633a
| 0.551133 | 3.797674 | false | false | false | false |
plorefice/freon
|
src/hdl/core/reg_file.vhdl
| 1 | 1,463 |
-- Design:
-- Dual-port input, single-port output register file for the Freon core.
--
-- Authors:
-- Pietro Lorefice <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg_file is
generic (
XLEN : integer := 32; -- # data bits
ALEN : integer := 5 -- # address bits (log2(#regs))
);
port (
clk, arst : in std_logic;
w_en : in std_logic;
w_addr : in std_logic_vector(ALEN-1 downto 0);
w_data : in std_logic_vector(XLEN-1 downto 0);
r_addr_1, r_addr_2 : in std_logic_vector(ALEN-1 downto 0);
r_data_1, r_data_2 : out std_logic_vector(XLEN-1 downto 0)
);
end entity; -- reg_file
architecture beh of reg_file is
-- Type for the register file itself (array of registers)
type reg_file_type is array (integer range 2**ALEN-1 downto 0) of
std_logic_vector(XLEN-1 downto 0);
signal array_reg : reg_file_type;
begin
-- hard-wire r0 to zero
--array_reg(0) <= (others => '0');
-- synchronous process
process (clk, arst)
variable idx : integer;
begin
if (arst = '1') then
array_reg <= (others => (others => '0'));
elsif rising_edge(clk) then
-- synchronous write
idx := to_integer(unsigned(w_addr));
if (w_en = '1' and idx /= 0) then
array_reg(idx) <= w_data;
end if;
end if;
end process;
-- asynchronous reads
r_data_1 <= array_reg(to_integer(unsigned(r_addr_1)));
r_data_2 <= array_reg(to_integer(unsigned(r_addr_2)));
end architecture; -- beh
|
mit
|
3e7d4c7a74aec84e75dd84cf80a81bd0
| 0.647984 | 2.674589 | false | false | false | false |
ziyan/altera-de2-ann
|
src/ann/ann.vhd
| 1 | 22,714 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package ann_types is
type ann_mode is ( idle, run, learn );
end package ann_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.sram_types.all;
USE work.ann_types.all;
PACKAGE ann_components IS
COMPONENT ann IS
GENERIC (
N_I : INTEGER := 2; -- number of perceptrons at input layer
N_H : INTEGER := 3; -- number of perceptrons at hidden layer
N_O : INTEGER := 1 -- number of perceptrons at output layer
);
PORT (
reset, clock : IN STD_LOGIC;
mode : IN ann_mode;
alpha : IN float;
inputs : IN float_vector(N_I-1 downto 0);
targets : IN float_vector(N_O-1 downto 0);
outputs : OUT float_vector(N_O-1 downto 0);
mse : OUT float;
ready : OUT STD_LOGIC;
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode;
float_alu_ready : IN STD_LOGIC;
sram_addr : OUT sram_address;
sram_input : OUT sram_data;
sram_output : IN sram_data;
sram_mode : INOUT sram_mode;
sram_ready : IN STD_LOGIC;
lfsr_output : IN STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT ann;
END PACKAGE ann_components;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE work.float_types.all;
USE work.float_constants.all;
USE work.sram_types.all;
USE work.ann_types.all;
ENTITY ann IS
GENERIC (
N_I : INTEGER := 2; -- number of perceptrons at input layer
N_H : INTEGER := 3; -- number of perceptrons at hidden layer
N_O : INTEGER := 1 -- number of perceptrons at output layer
);
PORT (
reset, clock : IN STD_LOGIC;
mode : IN ann_mode;
alpha : IN float;
inputs : IN float_vector(N_I-1 downto 0);
targets : IN float_vector(N_O-1 downto 0);
outputs : OUT float_vector(N_O-1 downto 0);
mse : OUT float;
ready : OUT STD_LOGIC;
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode;
float_alu_ready : IN STD_LOGIC;
sram_addr : OUT sram_address;
sram_input : OUT sram_data;
sram_output : IN sram_data;
sram_mode : INOUT sram_mode;
sram_ready : IN STD_LOGIC;
lfsr_output : IN STD_LOGIC_VECTOR(15 downto 0)
);
END ENTITY ann;
ARCHITECTURE ann OF ann IS
-- outputs for each peceptron
SIGNAL hidden_outputs : float_vector(N_H - 1 downto 0) := (others => float_zero);
SIGNAL output_outputs : float_vector(N_O - 1 downto 0) := (others => float_zero);
-- deltas for back propagation
SIGNAL hidden_deltas : float_vector(N_H - 1 downto 0) := (others => float_zero);
SIGNAL output_deltas : float_vector(N_O - 1 downto 0) := (others => float_zero);
-- state machine
TYPE states IS (
init,
init_weight,
init_weight_complete,
run, -- resets all outputs of hidden layer and output layer to 0
hidden_weighted_bias_load,
hidden_weighted_bias_load_complete,
hidden_weighted_value_load,
hidden_weighted_value_load_complete,
hidden_weighted_value_mul, -- calculate one weighted value for one hidden layer's perceptron
hidden_weighted_value_mul_complete,
hidden_weighted_value_add, -- sum one weighted value for one hidden layer's perceptron
hidden_weighted_value_add_complete,
hidden_sig_neg,
hidden_sig_exp, -- calculate exponential for sigmoid function for one hidden layer's perceptron
hidden_sig_exp_complete,
hidden_sig_add, -- calculate add 1 for sigmoid function for one hidden layer's perceptron
hidden_sig_add_complete,
hidden_sig_div, -- calculate 1 over for sigmoid function for one hidden layer's perceptron
hidden_sig_div_complete,
output_weighted_bias_load,
output_weighted_bias_load_complete,
output_weighted_value_load,
output_weighted_value_load_complete,
output_weighted_value_mul, -- calculate one weighted value for one output layer's perceptron
output_weighted_value_mul_complete,
output_weighted_value_add, -- sum one weighted value for one output layer's perceptron
output_weighted_value_add_complete,
output_sig_neg,
output_sig_exp, -- calculate exponential for sigmoid function for one output layer's perceptron
output_sig_exp_complete,
output_sig_add, -- calculate add 1 for sigmoid function for one output layer's perceptron
output_sig_add_complete,
output_sig_div, -- calculate 1 over for sigmoid function for one output layer's perceptron
output_sig_div_complete,
learn,
output_err_sub,
output_err_sub_complete,
output_err_mul,
output_err_mul_complete,
output_err_add,
output_err_add_complete,
output_delta_sub,
output_delta_sub_complete,
output_delta_mul,
output_delta_mul_complete,
output_delta_err_mul,
output_delta_err_mul_complete,
output_alpha_delta_mul,
output_alpha_delta_mul_complete,
output_update_weight_mul,
output_update_weight_mul_complete,
output_update_weight_load,
output_update_weight_load_complete,
output_update_weight_add,
output_update_weight_add_complete,
output_update_weight_save,
output_update_weight_save_complete,
output_update_bias_load,
output_update_bias_load_complete,
output_update_bias_add,
output_update_bias_add_complete,
output_update_bias_save,
output_update_bias_save_complete,
hidden_err_load,
hidden_err_load_complete,
hidden_err_mul,
hidden_err_mul_complete,
hidden_err_add,
hidden_err_add_complete,
hidden_delta_sub,
hidden_delta_sub_complete,
hidden_delta_mul,
hidden_delta_mul_complete,
hidden_delta_err_mul,
hidden_delta_err_mul_complete,
hidden_alpha_delta_mul,
hidden_alpha_delta_mul_complete,
hidden_update_weight_mul,
hidden_update_weight_mul_complete,
hidden_update_weight_load,
hidden_update_weight_load_complete,
hidden_update_weight_add,
hidden_update_weight_add_complete,
hidden_update_weight_save,
hidden_update_weight_save_complete,
hidden_update_bias_load,
hidden_update_bias_load_complete,
hidden_update_bias_add,
hidden_update_bias_add_complete,
hidden_update_bias_save,
hidden_update_bias_save_complete,
idle
);
SIGNAL state : states := init;
-- squared error
SIGNAL se : float := float_zero;
-- learning flag
SIGNAL learning : STD_LOGIC := '0';
-- temp signals
SIGNAL i, h, o : INTEGER := 0;
SIGNAL f, e, a : float := float_zero;
SIGNAL weight : float := float_zero;
SIGNAL addr : INTEGER := 0;
BEGIN
outputs <= output_outputs;
-- flying spaghetti monster (fsm) triggered at rising edge
fsm: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
float_alu_mode <= idle;
sram_mode <= idle;
ELSIF (clock = '1' AND clock'event) THEN
IF (float_alu_mode /= idle) THEN
float_alu_mode <= idle;
ELSIF (sram_mode /= idle) THEN
sram_mode <= idle;
ELSIF (float_alu_ready = '0' OR sram_ready = '0' ) THEN
ELSE
CASE state IS
WHEN init =>
addr <= 0;
ready <= '0';
state <= init_weight;
mse <= float_zero;
WHEN init_weight =>
sram_addr <= std_logic_vector(to_unsigned(addr, 17));
sram_input <= lfsr_output(15 downto 15) & "011" & lfsr_output(14 downto 11) & "0" & lfsr_output(10 downto 0) & "000000000000";
sram_mode <= write;
state <= init_weight_complete;
WHEN init_weight_complete =>
if( addr = ((N_I + 1) * N_H + (N_H + 1) * N_O) - 1 ) then
state <= idle;
else
addr <= addr + 1;
state <= init_weight;
end if;
--
-- normal run operation start here
--
WHEN run =>
ready <= '0';
-- initialize perceptrons to have a zero output
hidden_outputs <= (others => float_zero);
output_outputs <= (others => float_zero);
h <= 0;
state <= hidden_weighted_bias_load;
-- first load bias weight into sum
WHEN hidden_weighted_bias_load =>
sram_mode <= read;
sram_addr <= std_logic_vector(to_unsigned((N_I * N_H + h), 17));
state <= hidden_weighted_bias_load_complete;
WHEN hidden_weighted_bias_load_complete =>
hidden_outputs(h) <= sram_output;
i <= 0;
state <= hidden_weighted_value_load;
-- sum up all weighted input to the hidden layer
WHEN hidden_weighted_value_load =>
sram_mode <= read;
sram_addr <= std_logic_vector(to_unsigned((i * N_H + h), 17));
state <= hidden_weighted_value_load_complete;
WHEN hidden_weighted_value_load_complete =>
weight <= sram_output;
state <= hidden_weighted_value_mul;
WHEN hidden_weighted_value_mul =>
-- weighted value = weight * value
float_alu_a <= weight;
float_alu_b <= inputs(i);
float_alu_mode <= mul;
state <= hidden_weighted_value_mul_complete;
WHEN hidden_weighted_value_mul_complete =>
f <= float_alu_c;
state <= hidden_weighted_value_add;
WHEN hidden_weighted_value_add =>
-- sum += weighted value
float_alu_a <= hidden_outputs(h);
float_alu_b <= f;
float_alu_mode <= add;
state <= hidden_weighted_value_add_complete;
WHEN hidden_weighted_value_add_complete =>
hidden_outputs(h) <= float_alu_c;
IF (i = N_I - 1) THEN
state <= hidden_sig_neg;
ELSE
i <= i + 1;
state <= hidden_weighted_value_load;
END IF;
-- start sigmoid calculation
WHEN hidden_sig_neg =>
-- sum = -sum
hidden_outputs(h)(31) <= not hidden_outputs(h)(31);
state <= hidden_sig_exp;
WHEN hidden_sig_exp =>
-- output = exp(-sum)
float_alu_a <= hidden_outputs(h);
float_alu_mode <= exp;
state <= hidden_sig_exp_complete;
WHEN hidden_sig_exp_complete =>
hidden_outputs(h) <= float_alu_c;
state <= hidden_sig_add;
WHEN hidden_sig_add =>
-- output = exp(-sum) + 1.0
float_alu_a <= hidden_outputs(h);
float_alu_b <= float_one;
float_alu_mode <= add;
state <= hidden_sig_add_complete;
WHEN hidden_sig_add_complete =>
hidden_outputs(h) <= float_alu_c;
state <= hidden_sig_div;
WHEN hidden_sig_div =>
-- output = 1.0 / (exp(-sum) + 1.0)
float_alu_a <= float_one;
float_alu_b <= hidden_outputs(h);
float_alu_mode <= div;
state <= hidden_sig_div_complete;
WHEN hidden_sig_div_complete =>
hidden_outputs(h) <= float_alu_c;
IF (h = N_H - 1) THEN
o <= 0;
state <= output_weighted_bias_load;
ELSE
h <= h + 1;
state <= hidden_weighted_bias_load;
END IF;
-- load bias for output layer
WHEN output_weighted_bias_load =>
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * N_H + o), 17));
sram_mode <= read;
state <= output_weighted_bias_load_complete;
WHEN output_weighted_bias_load_complete =>
output_outputs(o) <= sram_output;
h <= 0;
state <= output_weighted_value_load;
-- sum up all weighted value from hidden layer
WHEN output_weighted_value_load =>
sram_mode <= read;
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * h + o), 17));
state <= output_weighted_value_load_complete;
WHEN output_weighted_value_load_complete =>
weight <= sram_output;
state <= output_weighted_value_mul;
WHEN output_weighted_value_mul =>
-- weighted value = weight * value
float_alu_a <= weight;
float_alu_b <= hidden_outputs(h);
float_alu_mode <= mul;
state <= output_weighted_value_mul_complete;
WHEN output_weighted_value_mul_complete =>
f <= float_alu_c;
state <= output_weighted_value_add;
WHEN output_weighted_value_add =>
-- sum += weighted value
float_alu_a <= output_outputs(o);
float_alu_b <= f;
float_alu_mode <= add;
state <= output_weighted_value_add_complete;
WHEN output_weighted_value_add_complete =>
output_outputs(o) <= float_alu_c;
IF (h = N_H - 1) THEN
state <= output_sig_neg;
ELSE
h <= h + 1;
state <= output_weighted_value_load;
END IF;
-- start sigmoid calculation for output layer
WHEN output_sig_neg =>
-- sum = -sum
output_outputs(o)(31) <= not output_outputs(o)(31);
state <= output_sig_exp;
WHEN output_sig_exp =>
-- output = exp(-sum)
float_alu_a <= output_outputs(o);
float_alu_mode <= exp;
state <= output_sig_exp_complete;
WHEN output_sig_exp_complete =>
output_outputs(o) <= float_alu_c;
state <= output_sig_add;
WHEN output_sig_add =>
-- output = exp(-sum) + 1.0
float_alu_a <= output_outputs(o);
float_alu_b <= float_one;
float_alu_mode <= add;
state <= output_sig_add_complete;
WHEN output_sig_add_complete =>
output_outputs(o) <= float_alu_c;
state <= output_sig_div;
WHEN output_sig_div =>
-- output = 1.0 / (exp(-sum) + 1.0)
float_alu_a <= float_one;
float_alu_b <= output_outputs(o);
float_alu_mode <= div;
state <= output_sig_div_complete;
WHEN output_sig_div_complete =>
output_outputs(o) <= float_alu_c;
IF (o = N_O - 1) THEN
IF (learning = '1') THEN
state <= learn;
ELSE
state <= idle;
END IF;
ELSE
o <= o + 1;
state <= output_weighted_bias_load;
END IF;
--
-- learn operation here
--
WHEN learn =>
se <= float_zero;
-- init deltas to zeros
hidden_deltas <= (others => float_zero);
output_deltas <= (others => float_zero);
o <= 0;
state <= output_err_sub;
-- output layer error
WHEN output_err_sub =>
-- error = target - output
float_alu_a <= targets(o);
float_alu_b <= output_outputs(o);
float_alu_mode <= sub;
state <= output_err_sub_complete;
WHEN output_err_sub_complete =>
f <= float_alu_c;
state <= output_err_mul;
WHEN output_err_mul =>
-- error^2 = error * error
float_alu_a <= f;
float_alu_b <= f;
float_alu_mode <= mul;
state <= output_err_mul_complete;
WHEN output_err_mul_complete =>
e <= float_alu_c;
state <= output_err_add;
WHEN output_err_add =>
-- se += error^2
float_alu_a <= se;
float_alu_b <= e;
float_alu_mode <= add;
state <= output_err_add_complete;
WHEN output_err_add_complete =>
se <= float_alu_c;
state <= output_delta_sub;
-- calculate delta for output layer
WHEN output_delta_sub =>
-- delta = 1.0 - output
float_alu_a <= float_one;
float_alu_b <= output_outputs(o);
float_alu_mode <= sub;
state <= output_delta_sub_complete;
WHEN output_delta_sub_complete =>
output_deltas(o) <= float_alu_c;
state <= output_delta_mul;
WHEN output_delta_mul =>
-- delta = output * (1.0 - output)
float_alu_a <= output_outputs(o);
float_alu_b <= output_deltas(o);
float_alu_mode <= mul;
state <= output_delta_mul_complete;
WHEN output_delta_mul_complete =>
output_deltas(o) <= float_alu_c;
state <= output_delta_err_mul;
WHEN output_delta_err_mul =>
-- delta = error * output * (1.0 - output)
float_alu_a <= f;
float_alu_b <= output_deltas(o);
float_alu_mode <= mul;
state <= output_delta_err_mul_complete;
WHEN output_delta_err_mul_complete =>
output_deltas(o) <= float_alu_c;
state <= output_alpha_delta_mul;
WHEN output_alpha_delta_mul =>
-- alpha * delta
float_alu_a <= alpha;
float_alu_b <= output_deltas(o);
float_alu_mode <= mul;
state <= output_alpha_delta_mul_complete;
WHEN output_alpha_delta_mul_complete =>
a <= float_alu_c;
h <= 0;
state <= output_update_weight_mul;
-- update weight of each input connection
WHEN output_update_weight_mul =>
-- alpha * delta * connection value
float_alu_a <= a;
float_alu_b <= hidden_outputs(h);
float_alu_mode <= mul;
state <= output_update_weight_mul_complete;
WHEN output_update_weight_mul_complete =>
f <= float_alu_c;
state <= output_update_weight_load;
WHEN output_update_weight_load =>
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * h + o), 17));
sram_mode <= read;
state <= output_update_weight_load_complete;
WHEN output_update_weight_load_complete =>
weight <= sram_output;
state <= output_update_weight_add;
WHEN output_update_weight_add =>
-- weight += alpha * delta * connection value
float_alu_a <= weight;
float_alu_b <= f;
float_alu_mode <= add;
state <= output_update_weight_add_complete;
WHEN output_update_weight_add_complete =>
weight <= float_alu_c;
state <= output_update_weight_save;
WHEN output_update_weight_save =>
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * h + o), 17));
sram_mode <= write;
sram_input <= weight;
state <= output_update_weight_save_complete;
WHEN output_update_weight_save_complete =>
IF (h = N_H - 1) THEN
state <= output_update_bias_load;
ELSE
h <= h + 1;
state <= output_update_weight_mul;
END IF;
-- update bias weight
WHEN output_update_bias_load =>
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * N_H + o), 17));
sram_mode <= read;
state <= output_update_bias_load_complete;
WHEN output_update_bias_load_complete =>
weight <= sram_output;
state <= output_update_bias_add;
WHEN output_update_bias_add =>
-- weight += alpha * delta
float_alu_a <= weight;
float_alu_b <= a;
float_alu_mode <= add;
state <= output_update_bias_add_complete;
WHEN output_update_bias_add_complete =>
weight <= float_alu_c;
state <= output_update_bias_save;
WHEN output_update_bias_save =>
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * N_H + o), 17));
sram_mode <= write;
sram_input <= weight;
state <= output_update_bias_save_complete;
WHEN output_update_bias_save_complete =>
IF (o = N_O - 1) THEN
mse <= se;
h <= 0;
o <= 0;
e <= float_zero;
state <= hidden_err_load;
ELSE
o <= o + 1;
state <= output_err_sub;
END IF;
-- hidden layer error
WHEN hidden_err_load =>
sram_addr <= std_logic_vector(to_unsigned(((N_I + 1) * N_H + N_O * h + o), 17));
sram_mode <= read;
state <= hidden_err_load_complete;
WHEN hidden_err_load_complete =>
weight <= sram_output;
state <= hidden_err_mul;
WHEN hidden_err_mul =>
-- delta * weight
float_alu_a <= output_deltas(o);
float_alu_b <= weight;
float_alu_mode <= mul;
state <= hidden_err_mul_complete;
WHEN hidden_err_mul_complete =>
f <= float_alu_c;
state <= hidden_err_add;
WHEN hidden_err_add =>
-- error += delta * weight
float_alu_a <= e;
float_alu_b <= f;
float_alu_mode <= add;
state <= hidden_err_add_complete;
WHEN hidden_err_add_complete =>
e <= float_alu_c;
IF (o = N_O - 1) THEN
state <= hidden_delta_sub;
ELSE
o <= o + 1;
state <= hidden_err_load;
END IF;
-- calculate delta
WHEN hidden_delta_sub =>
-- delta = 1.0 - output
float_alu_a <= float_one;
float_alu_b <= hidden_outputs(h);
float_alu_mode <= sub;
state <= hidden_delta_sub_complete;
WHEN hidden_delta_sub_complete =>
hidden_deltas(h) <= float_alu_c;
state <= hidden_delta_mul;
WHEN hidden_delta_mul =>
-- delta = output * (1.0 - output)
float_alu_a <= hidden_outputs(h);
float_alu_b <= hidden_deltas(h);
float_alu_mode <= mul;
state <= hidden_delta_mul_complete;
WHEN hidden_delta_mul_complete =>
hidden_deltas(h) <= float_alu_c;
state <= hidden_delta_err_mul;
WHEN hidden_delta_err_mul =>
-- delta = error * output * (1.0 - output)
float_alu_a <= e;
float_alu_b <= hidden_deltas(h);
float_alu_mode <= mul;
state <= hidden_delta_err_mul_complete;
WHEN hidden_delta_err_mul_complete =>
hidden_deltas(h) <= float_alu_c;
state <= hidden_alpha_delta_mul;
WHEN hidden_alpha_delta_mul =>
-- alpha * delta
float_alu_a <= alpha;
float_alu_b <= hidden_deltas(h);
float_alu_mode <= mul;
state <= hidden_alpha_delta_mul_complete;
WHEN hidden_alpha_delta_mul_complete =>
a <= float_alu_c;
i <= 0;
state <= hidden_update_weight_mul;
-- update input weights
WHEN hidden_update_weight_mul =>
-- alpha * delta * connection value
float_alu_a <= a;
float_alu_b <= inputs(i);
float_alu_mode <= mul;
state <= hidden_update_weight_mul_complete;
WHEN hidden_update_weight_mul_complete =>
f <= float_alu_c;
state <= hidden_update_weight_load;
WHEN hidden_update_weight_load =>
sram_addr <= std_logic_vector(to_unsigned((i * N_H + h), 17));
sram_mode <= read;
state <= hidden_update_weight_load_complete;
WHEN hidden_update_weight_load_complete =>
weight <= sram_output;
state <= hidden_update_weight_add;
WHEN hidden_update_weight_add =>
-- weight += alpha * delta * connection value
float_alu_a <= weight;
float_alu_b <= f;
float_alu_mode <= add;
state <= hidden_update_weight_add_complete;
WHEN hidden_update_weight_add_complete =>
weight <= float_alu_c;
state <= hidden_update_weight_save;
WHEN hidden_update_weight_save =>
sram_addr <= std_logic_vector(to_unsigned((i * N_H + h), 17));
sram_input <= weight;
sram_mode <= write;
state <= hidden_update_weight_save_complete;
WHEN hidden_update_weight_save_complete =>
weight <= sram_output;
IF (i = N_I - 1) THEN
state <= hidden_update_bias_load;
ELSE
i <= i + 1;
state <= hidden_update_weight_mul;
END IF;
-- update hidden layer bias weight
WHEN hidden_update_bias_load =>
sram_addr <= std_logic_vector(to_unsigned((N_I * N_H + h), 17));
sram_mode <= read;
state <= hidden_update_bias_load_complete;
WHEN hidden_update_bias_load_complete =>
weight <= sram_output;
state <= hidden_update_bias_add;
WHEN hidden_update_bias_add =>
-- weight += alpha * delta
float_alu_a <= weight;
float_alu_b <= a;
float_alu_mode <= add;
state <= hidden_update_bias_add_complete;
WHEN hidden_update_bias_add_complete =>
weight <= float_alu_c;
state <= hidden_update_bias_save;
WHEN hidden_update_bias_save =>
sram_addr <= std_logic_vector(to_unsigned((N_I * N_H + h), 17));
sram_mode <= write;
sram_input <= weight;
state <= hidden_update_bias_save_complete;
WHEN hidden_update_bias_save_complete =>
IF (h = N_H - 1) THEN
state <= idle;
ELSE
h <= h + 1;
o <= 0;
state <= hidden_err_load;
END IF;
WHEN idle =>
ready <= '1';
CASE mode IS
WHEN idle =>
state <= idle;
WHEN run =>
ready <= '0';
learning <= '0';
state <= run;
WHEN learn =>
ready <= '0';
learning <= '1';
state <= run;
WHEN others =>
state <= idle;
END CASE;
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ann;
|
mit
|
ebab294d9743f0667559196a43205be6
| 0.628247 | 2.968374 | false | false | false | false |
quicky2000/top_test_rom
|
testbench/testbench_top_test_rom.vhd
| 1 | 2,841 |
--
-- This file is part of top_test_rom
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench_top_test_rom IS
END testbench_top_test_rom;
ARCHITECTURE behavior OF testbench_top_test_rom IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_test_rom
PORT(
clk : IN std_logic;
w1a : INOUT std_logic_vector(15 downto 0);
w1b : INOUT std_logic_vector(15 downto 0);
w2c : INOUT std_logic_vector(15 downto 0);
rx : IN std_logic;
tx : INOUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--BiDirs
signal w1a : std_logic_vector(15 downto 0);
signal w1b : std_logic_vector(15 downto 0);
signal w2c : std_logic_vector(15 downto 0);
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_test_rom PORT MAP (
clk => clk,
w1a => w1a,
w1b => w1b,
w2c => w2c,
rx => rx,
tx => tx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
f3eccef6a5ecfc41405eb0e703d59cf4
| 0.629356 | 3.854817 | false | true | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/RS232_RX.vhd
| 1 | 5,897 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:22:41 10/20/2016
-- Design Name:
-- Module Name: RS232_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RS232_RX is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
LineRD_in : in STD_LOGIC;
Valid_out : out STD_LOGIC;
Code_out : out STD_LOGIC;
Store_out : out STD_LOGIC);
end RS232_RX;
architecture Behavioral of RS232_RX is
-------------- Componentes ------------------
component Pulse_Width
generic (PulseEndOfCount : NATURAL);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
send : out std_logic);
end component;
component Data_Count
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out STD_LOGIC_VECTOR (3 downto 0));
end component;
---------------- Estados de la Maquina ------------
type State is (Idle,
StartBit,
RcvData,
StopBit);
------------------ Señales -------------------------
signal PresentState, NextState : State;
signal bit_out : std_logic;
signal half_bit_out : std_logic;
signal count : std_logic_vector(3 downto 0);
signal reset_data : std_logic;
signal reset_control : std_logic;
--signal reset_half : std_logic;
signal enable_half : std_logic;
signal enable_bitcounter : std_logic;
begin
reset_control <= reset_data and Reset;
--reset_half <= Reset and (not bit_out);
------------------- PORT MAP ----------------------
BitCounter: Pulse_Width
generic map (PulseEndOfCount => 174)
port map (
clk => Clk,
reset => Reset,
enable => enable_bitcounter,
send => bit_out);
HalfBitCounter: Pulse_Width
generic map (PulseEndOfCount => 87)
port map (
clk => Clk,
reset => Reset,
enable => enable_half,
send => half_bit_out);
Data_Control: Data_Count
port map (
clk => Clk,
reset => reset_control,
enable => bit_out,
count => count);
enable_half_counter: process(clk, Reset, bit_out, half_bit_out, enable_half)
begin
if Reset = '0' then
enable_half <= '0';
elsif clk'event and clk = '1' then
if half_bit_out = '1' or bit_out = '1' then
enable_half <= not enable_half;
end if;
end if;
end process;
--------------------- MAQUINA DE ESTADOS ----------------
FFs : process(Clk, Reset)
begin
if Reset ='0' then
PresentState <= Idle;
elsif Clk'event and Clk = '1' then
PresentState <= NextState;
end if;
end process;
Siguiente : process(PresentState, LineRD_in, bit_out, count)
begin
case PresentState is
when Idle =>
if LineRD_in = '0' then
NextState <= StartBit;
else
NextState <= Idle;
end if;
when StartBit =>
if bit_out ='1' then
NextState <= RcvData;
else
NextState <= StartBit;
end if;
when RcvData =>
if count = "1000" then
NextState <= StopBit;
else
NextState <= RcvData;
end if;
when StopBit =>
if bit_out ='1' then
NextState <= Idle;
else
NextState <= StopBit;
end if;
when others =>
NextState <= Idle;
end case;
end process;
Salidas : process(PresentState, half_bit_out, count, LineRD_in)
begin
case PresentState is
when Idle =>
Valid_out <= '0';
Code_out <= '0';
Store_out <= '0';
reset_data <= '0';
enable_bitcounter <= '0';
when StartBit =>
Valid_out <= '0';
Code_out <= '0';
Store_out <= '0';
reset_data <= '0';
enable_bitcounter <= '1';
when RcvData =>
Store_out <= '0';
reset_data <= '1';
Code_out <= '0';
Valid_out <= '0';
enable_bitcounter <= '1';
if half_bit_out = '1' then
case count is
when "0000" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0001" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0010" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0011" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0100" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0101" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0110" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when "0111" =>
Code_out <= LineRD_in;
Valid_out <= '1';
when others =>
Code_out <= '0';
Valid_out <= '0';
end case;
end if;
when StopBit =>
enable_bitcounter <= '1';
if half_bit_out = '1' and LineRD_in = '1' then
Valid_out <= '0';
Code_out <= '0';
Store_out <= '1';
reset_data <= '0';
else
Valid_out <= '0';
Code_out <= '0';
Store_out <= '0';
reset_data <= '0';
end if;
when others =>
Valid_out <= '0';
Code_out <= '0';
Store_out <= '0';
reset_data <= '0';
enable_bitcounter <= '0';
end case;
end process;
end Behavioral;
|
mit
|
b447317397a8a3bd6ebc0804df89349a
| 0.50619 | 3.466784 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/ALU.vhd
| 1 | 6,007 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:35:20 11/27/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.PIC_pkg.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
port ( Reset : in std_logic; -- asynnchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
u_instruction : in alu_op; -- u-instructions from CPU
FlagZ : out std_logic; -- Zero flag
-- FlagC : out std_logic; -- Carry flag
-- FlagN : out std_logic; -- Nibble carry bit
-- FlagE : out std_logic; -- Error flag
Index_Reg : out std_logic_vector(7 downto 0); -- Index register
Databus : inout std_logic_vector(7 downto 0)); -- System Data bus
end ALU;
architecture Behavioral of ALU is
signal operandoA : std_logic_vector(7 downto 0);
signal operandoB : std_logic_vector(7 downto 0);
signal acumulador : std_logic_vector(7 downto 0);
signal index : std_logic_vector(7 downto 0);
signal Flag_Z: std_logic;
begin
process(Clk, Databus, Reset)
begin
if Reset = '0' then
operandoA <= (others => '0');
operandoB <= (others => '0');
acumulador <= (others => '0');
index <= (others => '0');
Flag_Z <= '0';
Databus <= (others => 'Z');
elsif Clk'event and Clk = '1' then
Flag_Z <= '0';
case u_instruction is
when nop =>
Databus <= (others => 'Z');
when op_lda =>
operandoA <= Databus;
when op_ldb =>
operandoB <= Databus;
when op_ldacc =>
acumulador <= Databus;
when op_ldid =>
index <= Databus;
when op_mvacc2id =>
index <= acumulador;
Databus <= (others => 'Z');
when op_mvacc2a =>
operandoA <= acumulador;
Databus <= (others => 'Z');
when op_mvacc2b =>
operandoB <= acumulador;
Databus <= (others => 'Z');
when op_add =>
acumulador <= operandoA + operandoB;
if (operandoA + operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_sub =>
acumulador <= operandoA - operandoB;
if (operandoA - operandoB) = X"00" then
Flag_Z <= '0';
end if;
Databus <= (others => 'Z');
when op_shiftl =>
acumulador <= acumulador(7 downto 1) & '0';
Databus <= (others => 'Z');
when op_shiftr =>
acumulador <= '0' & acumulador(6 downto 0);
Databus <= (others => 'Z');
when op_and =>
acumulador <= operandoA and operandoB;
if (operandoA and operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_or =>
acumulador <= operandoA or operandoB;
if (operandoA or operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_xor =>
acumulador <= operandoA xor operandoB;
if (operandoA xor operandoB) = X"00" then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_cmpe =>
if (operandoA = OperandoB) then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_cmpl =>
if (operandoA < OperandoB) then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_cmpg =>
if (operandoA > OperandoB) then
Flag_Z <= '1';
end if;
Databus <= (others => 'Z');
when op_ascii2bin =>
Databus <= (others => 'Z');
if operandoA = X"30" then
acumulador <= X"00";
elsif operandoA = X"31" then
acumulador <= X"01";
elsif operandoA = X"32" then
acumulador <= X"02";
elsif operandoA = X"33" then
acumulador <= X"03";
elsif operandoA = X"34" then
acumulador <= X"04";
elsif operandoA = X"35" then
acumulador <= X"05";
elsif operandoA = X"36" then
acumulador <= X"06";
elsif operandoA = X"37" then
acumulador <= X"07";
elsif operandoA = X"38" then
acumulador <= X"08";
elsif operandoA = X"39" then
acumulador <= X"09";
else
acumulador <= X"FF";
end if;
when op_bin2ascii =>
Databus <= (others => 'Z');
if operandoA = 0 then
acumulador <= X"30";
elsif operandoA = 1 then
acumulador <= X"31";
elsif operandoA = 2 then
acumulador <= X"32";
elsif operandoA = 3 then
acumulador <= X"33";
elsif operandoA = 4 then
acumulador <= X"34";
elsif operandoA = 5 then
acumulador <= X"35";
elsif operandoA = 6 then
acumulador <= X"36";
elsif operandoA = 7 then
acumulador <= X"37";
elsif operandoA = 8 then
acumulador <= X"38";
elsif operandoA = 9 then
acumulador <= X"39";
elsif operandoA = 10 then
acumulador <= X"41"; -- A
elsif operandoA = 11 then
acumulador <= X"42"; -- B
elsif operandoA = 12 then
acumulador <= X"43"; -- C
elsif operandoA = 13 then
acumulador <= X"44"; -- D
elsif operandoA = 14 then
acumulador <= X"45"; -- E
elsif operandoA = 15 then
acumulador <= X"46"; -- F
else
acumulador <= X"FF";
end if;
when op_oeacc =>
Databus <= acumulador;
when others =>
Databus <= (others => 'Z');
end case;
FlagZ <= Flag_Z;
Index_Reg <= index;
end if;
end process;
end Behavioral;
|
mit
|
11b31688eb19c24d7f7e1272196c263a
| 0.549193 | 3.416951 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/PICtop.vhd
| 1 | 7,939 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity PICtop is
port (
Reset : in std_logic; -- Asynchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
RS232_RX : in std_logic; -- RS232 RX line
RS232_TX : out std_logic; -- RS232 TX line
Switches : out std_logic_vector(7 downto 0); -- Switch status bargraph
Temp_L : out std_logic_vector(6 downto 0); -- Less significant figure of T_STAT
Temp_H : out std_logic_vector(6 downto 0)); -- Most significant figure of T_STAT
end PICtop;
architecture behavior of PICtop is
-----------------------------------------------------------------------------------
-- Módulos de comunicación
-----------------------------------------------------------------------------------
component RS232top
port (
Reset : in std_logic;
Clk : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Valid_D : in std_logic;
Ack_in : out std_logic;
TX_RDY : out std_logic;
TD : out std_logic;
RD : in std_logic;
Data_out : out std_logic_vector(7 downto 0);
Data_read : in std_logic;
Full : out std_logic;
Empty : out std_logic;
FF_Count : out std_logic_vector(5 downto 0));
end component;
component DMA
Port (
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
RCVD_Data : in STD_LOGIC_VECTOR (7 downto 0);
RX_Full : in STD_LOGIC;
RX_Empty : in STD_LOGIC;
Data_Read : out STD_LOGIC;
ACK_out : in STD_LOGIC;
TX_RDY : in STD_LOGIC;
Valid_D : out STD_LOGIC;
TX_Data : out STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Write_en : out STD_LOGIC;
OE : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
Send_comm : in STD_LOGIC;
READY : out STD_LOGIC;
FF_Count : in std_logic_vector(5 downto 0));
end component;
-------------------------------------------------------------------------------
-- Memoria RAM
-------------------------------------------------------------------------------
component ram
PORT (
Clk : in std_logic;
Reset : in std_logic;
write_en : in std_logic;
oe : in std_logic;
address : in std_logic_vector(7 downto 0);
databus : inout std_logic_vector(7 downto 0);
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
END component;
------------------------------------------------------------------------------
-- ALU
------------------------------------------------------------------------------
component ALU
PORT (
Reset : in std_logic; -- asynnchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
u_instruction : in alu_op; -- u-instructions from CPU
FlagZ : out std_logic; -- Zero flag
-- FlagC : out std_logic; -- Carry flag
-- FlagN : out std_logic; -- Nibble carry bit
-- FlagE : out std_logic; -- Error flag
Index_Reg : out std_logic_vector(7 downto 0); -- Index register
Databus : inout std_logic_vector(7 downto 0)); -- System Data bus
END component;
------------------------------------------------------------------------------
-- CPU
------------------------------------------------------------------------------
component CPU
PORT (
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
ROM_Data : in STD_LOGIC_VECTOR (11 downto 0);
ROM_Addr : out STD_LOGIC_VECTOR (11 downto 0);
RAM_Addr : out STD_LOGIC_VECTOR (7 downto 0);
RAM_Write : out STD_LOGIC;
RAM_OE : out STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
DMA_RQ : in STD_LOGIC;
DMA_ACK : out STD_LOGIC;
SEND_comm : out STD_LOGIC;
DMA_READY : in STD_LOGIC;
Alu_op : out alu_op;
Index_Reg : in STD_LOGIC_VECTOR (7 downto 0);
FlagZ : in STD_LOGIC);
--FlagC : in STD_LOGIC;
--FlagN : in STD_LOGIC;
--FlagE : in STD_LOGIC
END component;
----------------------------------------------------------------------------
-- ROM
----------------------------------------------------------------------------
component ROM
PORT (
Instruction : out STD_LOGIC_VECTOR(11 downto 0); -- Instruction bus
Program_counter : in STD_LOGIC_VECTOR(11 downto 0));
END component;
-----------------------------------------------------------------------------
-- Señales internas
-----------------------------------------------------------------------------
signal Valid_D : STD_LOGIC;
signal Ack_out : STD_LOGIC;
signal TX_RDY : STD_LOGIC;
signal Data_Read : STD_LOGIC;
signal RX_Full : STD_LOGIC;
signal RX_Empty : STD_LOGIC;
signal Write_en : STD_LOGIC;
signal OE : STD_LOGIC;
signal DMA_ACK : STD_LOGIC;
signal DMA_RQ : STD_LOGIC;
signal Send_comm : STD_LOGIC;
signal READY : STD_LOGIC;
signal TX_Data : STD_LOGIC_VECTOR (7 downto 0);
signal Address : STD_LOGIC_VECTOR (7 downto 0);
signal Databus : STD_LOGIC_VECTOR (7 downto 0);
signal RCVD_Data : STD_LOGIC_VECTOR (7 downto 0);
signal fifo_count : STD_LOGIC_VECTOR (5 downto 0);
signal Index_Reg : STD_LOGIC_VECTOR (7 downto 0);
signal FlagZ : STD_LOGIC;
signal Alu_op : alu_op;
signal ROM_Data : STD_LOGIC_VECTOR (11 downto 0);
signal ROM_Addr : STD_LOGIC_VECTOR (11 downto 0);
begin -- behavior
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
RS232_PHY: RS232top
port map (
Reset => Reset,
Clk => Clk,
Data_in => TX_Data,
Valid_D => Valid_D,
Ack_in => Ack_out,
TX_RDY => TX_RDY,
TD => RS232_TX,
RD => RS232_RX,
Data_out => RCVD_Data,
Data_read => Data_Read,
Full => RX_Full,
Empty => RX_Empty,
FF_Count => fifo_count);
DMA_Unit: DMA
port map (
Reset => Reset,
Clk => Clk,
RCVD_Data => RCVD_Data,
RX_Full => RX_Full,
RX_Empty => RX_Empty,
Data_Read => Data_Read,
ACK_out => ACK_out,
TX_RDY => TX_RDY,
Valid_D => Valid_D,
TX_Data => TX_Data,
Address => Address,
Databus => Databus,
Write_en => Write_en,
OE => OE,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
Send_comm => Send_comm,
READY => READY,
FF_Count => fifo_count);
RAM_Unit: RAM
port map (
Clk => Clk,
Reset => Reset,
write_en => Write_en,
oe => OE,
address => Address,
databus => Databus,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H);
ALU_Unit: ALU
port map (
Reset => Reset,
Clk => Clk,
u_instruction => Alu_op,
FlagZ => FlagZ,
-- FlagC =>
-- FlagN =>
-- FlagE =>
Index_Reg => Index_Reg,
Databus => Databus);
CPU_Unit: CPU
port map (
Reset => Reset,
Clk => Clk,
ROM_Data => ROM_Data,
ROM_Addr => ROM_Addr,
RAM_Addr => Address,
RAM_Write => Write_en,
RAM_OE => OE,
Databus => Databus,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
SEND_comm => Send_comm,
DMA_READY => READY,
Alu_op => Alu_op,
Index_Reg => Index_Reg,
FlagZ => FlagZ);
--FlagC =>
--FlagN =>
--FlagE =>
ROM_Unit: ROM
port map (
Instruction => ROM_Data,
Program_counter => ROM_Addr);
end behavior;
|
mit
|
384b2826b8839ee2bd6e7d3a8a348433
| 0.478524 | 3.136705 | false | false | false | false |
ziyan/altera-de2-ann
|
src/lib/float/fp.vhd
| 1 | 5,763 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package float_types is
subtype float is std_logic_vector(31 downto 0);
type float_vector is array( NATURAL range <> ) of float;
type float_alu_mode is ( idle, add, sub, mul, div, exp);
end package float_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
package float_constants is
-- whole number constants
CONSTANT float_zero : float := "00000000000000000000000000000000";
CONSTANT float_one : float := "00111111100000000000000000000000";
-- other constants
CONSTANT float_half : float := "00111111000000000000000000000000";
CONSTANT float_1_10 : float := "00111101110011001100110011001100";
CONSTANT float_1_20 : float := "00111101010011001100110011001101";
CONSTANT float_1_100 : float := "00111100001000111101011100001010";
CONSTANT float_add_wait : INTEGER := 7;
CONSTANT float_sub_wait : INTEGER := 7;
CONSTANT float_div_wait : INTEGER := 6;
CONSTANT float_mul_wait : INTEGER := 11;
CONSTANT float_exp_wait : INTEGER := 17;
CONSTANT float_cmp_wait : INTEGER := 1;
end package float_constants;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
package float_components is
component fp_add
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component fp_cmp
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
agb : OUT STD_LOGIC
);
end component;
component fp_div
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component fp_exp
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component fp_mul
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component fp_sub
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component float_alu IS
PORT (
reset, clock : IN STD_LOGIC;
a, b : IN float;
c : OUT float;
mode : IN float_alu_mode;
ready : OUT STD_LOGIC
);
end component float_alu;
end package float_components;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE work.float_types.all;
USE work.float_components.all;
USE work.float_constants.all;
ENTITY float_alu IS
PORT (
reset, clock : IN STD_LOGIC;
a, b : IN float;
c : OUT float;
mode : IN float_alu_mode;
ready : OUT STD_LOGIC
);
END ENTITY float_alu;
ARCHITECTURE float_alu OF float_alu IS
-- wait counter
SIGNAL wait_counter : INTEGER := 0;
-- alu signals
SIGNAL add_enable, sub_enable, mul_enable, div_enable, exp_enable : STD_LOGIC := '0';
SIGNAL alu_a, alu_b, alu_c, add_c, sub_c, mul_c, div_c, exp_c : float := float_zero;
TYPE states IS (idle, add, sub, mul, div, exp);
SIGNAL state : states := idle;
BEGIN
c <= alu_c;
-- alu stuff
fp_add0 : fp_add port map (reset, add_enable, clock, alu_a, alu_b, add_c);
fp_sub0 : fp_sub port map (reset, sub_enable, clock, alu_a, alu_b, sub_c);
fp_mul0 : fp_mul port map (reset, mul_enable, clock, alu_a, alu_b, mul_c);
fp_div0 : fp_div port map (reset, div_enable, clock, alu_a, alu_b, div_c);
fp_exp0 : fp_exp port map (reset, exp_enable, clock, alu_a, exp_c);
fsm: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
wait_counter <= 0;
state <= idle;
ready <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wait_counter > 0) THEN
wait_counter <= wait_counter - 1;
ELSE
CASE state IS
WHEN idle =>
CASE mode IS
WHEN idle =>
ready <= '1';
state <= idle;
WHEN add =>
ready <= '0';
add_enable <= '1';
alu_a <= a;
alu_b <= b;
wait_counter <= float_add_wait;
state <= add;
WHEN sub =>
ready <= '0';
sub_enable <= '1';
alu_a <= a;
alu_b <= b;
wait_counter <= float_sub_wait;
state <= sub;
WHEN mul =>
ready <= '0';
mul_enable <= '1';
alu_a <= a;
alu_b <= b;
wait_counter <= float_mul_wait;
state <= mul;
WHEN div =>
ready <= '0';
div_enable <= '1';
alu_a <= a;
alu_b <= b;
wait_counter <= float_div_wait;
state <= div;
WHEN exp =>
ready <= '0';
exp_enable <= '1';
alu_a <= a;
wait_counter <= float_exp_wait;
state <= exp;
WHEN others =>
state <= idle;
END CASE;
WHEN add =>
alu_c <= add_c;
add_enable <= '0';
state <= idle;
ready <= '1';
WHEN sub =>
alu_c <= sub_c;
sub_enable <= '0';
state <= idle;
ready <= '1';
WHEN mul =>
alu_c <= mul_c;
mul_enable <= '0';
state <= idle;
ready <= '1';
WHEN div =>
alu_c <= div_c;
div_enable <= '0';
state <= idle;
ready <= '1';
WHEN exp =>
alu_c <= exp_c;
exp_enable <= '0';
state <= idle;
ready <= '1';
WHEN others =>
state <= idle;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE float_alu;
|
mit
|
a16ae6edb01afe75c9dd5377cf6705c1
| 0.613916 | 2.758736 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_header.vhd
| 1 | 8,292 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_header
---- Version: 1.0.0
---- Description:
---- TBD
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/28: initial release
---- 2016/10/21: rework
---- 2016/11/03: add idle data flag
-------------------------------
--TODO: static fixed virtual channel now - implement virtual channel service
--TODO: secondary header
--TODO: security header
--TRANSFER FRAME PRIMARY HEADER => 6 octets
-- \ MASTER CHANNEL ID => 12 bits
-- \ TRANSFER FRAME VERSION NUMBER => 2 bits
-- \ SPACECRAFT ID => 10 bits
-- \ VIRTUAL CHANNEL ID => 3 bits
-- \ OCF FLAG => 1 bit
-- \ MASTER CHANNEL FRAME COUNT => 1 octet
-- \ VIRTUAL CHANNEL FRAME COUNT => 1 octet
-- \ TRANSFER FRAME DATA FIELD STATUS => 2 octets
-- \ TRANSFER FRAME SECONDARY HEADER FLAG => 1 bit
-- \ SYNC FLAG => 1 bit
-- \ PACKET ORDER FLAG => 1 bit
-- \ SEGMENT LENGTH ID => 2 bits
-- \ FIRST HEADER POINTER => 11 bits
--[OPT] TRANSFER FRAME SECONDARY HEADER => up to 64 octets
-- \ TRANSFER FRAME SECONDARY HEADER ID => 1 octet
-- \ TRANSFER FRAME SECONDARY HEADER VERSION NUMBER => 2 bits
-- \ TRANSFER FRAME SECONDARY HEADER LENGTH => 6 bits
-- \ TRANSFER FRAME SECONDARY HEADER DATA FIELD => up to 63 octets
--[OPT] SECURITY HEADER
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx header inputs and outputs
--=============================================================================
entity ccsds_tx_header is
generic(
CCSDS_TX_HEADER_LENGTH: integer; -- in Bytes
CCSDS_TX_HEADER_MCI_TFVN: std_logic_vector(2-1 downto 0) := "00"; -- Transfer Frame Version Number value
CCSDS_TX_HEADER_MCI_SID: std_logic_vector(10-1 downto 0) := "1100110011"; -- Spacecraft ID value
CCSDS_TX_HEADER_MCFC_LENGTH: integer := 8; -- Master Channel Frame Count length - in bits
CCSDS_TX_HEADER_OCFF: std_logic := '0'; -- Operationnal Control Field Flag
CCSDS_TX_HEADER_VCI: std_logic_vector(3-1 downto 0) := "000"; -- Virtual Channel Identifier value
CCSDS_TX_HEADER_VCFC_LENGTH: integer := 8; -- Virtual Channel Frame Count length - in bits
CCSDS_TX_HEADER_TFDFS_LENGTH: integer := 16; -- Transfer Frame Data Field Status length - in bits
CCSDS_TX_HEADER_TFDFS_POF: std_logic := '0'; -- Packet Order Flag
CCSDS_TX_HEADER_TFDFS_SF: std_logic := '0'; -- Synchronization Flag
CCSDS_TX_HEADER_TFDFS_SLI: std_logic_vector(1 downto 0) := "11"; -- Segment Length Identifier
CCSDS_TX_HEADER_TFDFS_TFSHF: std_logic := '0' -- Transfer Frame Secondary Header Flag
);
port(
-- inputs
clk_i: in std_logic;
idl_i: in std_logic;
nxt_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_HEADER_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_header;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_header is
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKHEADERP0 : if CCSDS_TX_HEADER_LENGTH*8 /= (CCSDS_TX_HEADER_MCI_TFVN'length + CCSDS_TX_HEADER_MCI_SID'length + CCSDS_TX_HEADER_VCI'length + CCSDS_TX_HEADER_MCFC_LENGTH + CCSDS_TX_HEADER_VCFC_LENGTH + CCSDS_TX_HEADER_TFDFS_LENGTH + 1) generate
process
begin
report "ERROR: HEADER LENGTH IS DIFFERENT OF TOTAL SUBELEMENTS LENGTH" severity failure;
wait;
end process;
end generate CHKHEADERP0;
-- internal processing
--=============================================================================
-- Begin of headerp
-- Generate valid headers
--=============================================================================
-- read: rst_i, nxt_i
-- write: dat_val_o, dat_o
-- r/w:
HEADERP : process (clk_i)
variable header_mci_tfvn: std_logic_vector(CCSDS_TX_HEADER_MCI_TFVN'length-1 downto 0) := CCSDS_TX_HEADER_MCI_TFVN; -- Transfer Frame Version Number
variable header_mci_sid: std_logic_vector(CCSDS_TX_HEADER_MCI_SID'length-1 downto 0) := CCSDS_TX_HEADER_MCI_SID; -- Spacecraft ID
variable header_vci: std_logic_vector(CCSDS_TX_HEADER_VCI'length-1 downto 0) := CCSDS_TX_HEADER_VCI; -- Virtual Channel Identifier
variable header_ocff: std_logic := CCSDS_TX_HEADER_OCFF; -- Operationnal Control Field Flag
variable header_mcfc: integer range 0 to (2**CCSDS_TX_HEADER_MCFC_LENGTH)-1 := 0; -- Master Channel Frame Count
variable header_vcfc: integer range 0 to (2**CCSDS_TX_HEADER_VCFC_LENGTH)-1 := 0; -- Virtual Channel Frame Count
variable header_tfdfs_fhp: std_logic_vector(CCSDS_TX_HEADER_TFDFS_LENGTH-6 downto 0) := "00000000000"; -- First Header Pointer / 11111111110 when idle data inside only
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
dat_val_o <= '0';
header_mci_tfvn := CCSDS_TX_HEADER_MCI_TFVN;
header_mci_sid := CCSDS_TX_HEADER_MCI_SID;
header_vci := CCSDS_TX_HEADER_VCI;
header_ocff := '1';
header_mcfc := 0;
header_vcfc := 0;
header_tfdfs_fhp := "00000000000";
else
if (nxt_i = '1') then
if(idl_i = '1') then
header_tfdfs_fhp := "11111111110";
else
header_tfdfs_fhp := "00000000000";
end if;
dat_val_o <= '1';
dat_o(CCSDS_TX_HEADER_LENGTH*8-1 downto CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length) <= header_mci_tfvn;
dat_o(CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-1 downto CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length) <= header_mci_sid;
dat_o(CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-1 downto CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-CCSDS_TX_HEADER_VCI'length) <= header_vci;
dat_o(CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-CCSDS_TX_HEADER_VCI'length-1) <= header_ocff;
dat_o(CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-CCSDS_TX_HEADER_VCI'length-1-1 downto CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-CCSDS_TX_HEADER_VCI'length-1-CCSDS_TX_HEADER_MCFC_LENGTH) <= std_logic_vector(to_unsigned(header_mcfc,CCSDS_TX_HEADER_MCFC_LENGTH));
dat_o(CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-CCSDS_TX_HEADER_VCI'length-1-CCSDS_TX_HEADER_MCFC_LENGTH-1 downto CCSDS_TX_HEADER_LENGTH*8-CCSDS_TX_HEADER_MCI_TFVN'length-CCSDS_TX_HEADER_MCI_SID'length-CCSDS_TX_HEADER_VCI'length-1-CCSDS_TX_HEADER_MCFC_LENGTH-CCSDS_TX_HEADER_VCFC_LENGTH) <= std_logic_vector(to_unsigned(header_vcfc,CCSDS_TX_HEADER_VCFC_LENGTH));
dat_o(CCSDS_TX_HEADER_TFDFS_LENGTH-1 downto CCSDS_TX_HEADER_TFDFS_LENGTH-5) <= CCSDS_TX_HEADER_TFDFS_TFSHF & CCSDS_TX_HEADER_TFDFS_SF & CCSDS_TX_HEADER_TFDFS_POF & CCSDS_TX_HEADER_TFDFS_SLI;
dat_o(CCSDS_TX_HEADER_TFDFS_LENGTH-6 downto 0) <= header_tfdfs_fhp;
if (header_mcfc = (2**CCSDS_TX_HEADER_MCFC_LENGTH)-1) then
header_mcfc := 0;
else
header_mcfc := header_mcfc + 1;
end if;
if (header_vcfc = (2**CCSDS_TX_HEADER_VCFC_LENGTH)-1) then
header_vcfc := 0;
else
header_vcfc := header_vcfc + 1;
end if;
else
dat_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
mit
|
3f5161b0e7513bfc421285f1bb0efca4
| 0.605765 | 3.608355 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_bench.vhd
| 1 | 144,265 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_bench
---- Version: 1.0.0
---- Description:
---- Unit level + sub-components testing vhdl ressource
---- 1: generate clock signals
---- 2: generate resets signals
---- 3: generate wb read/write cycles signals
---- 4: generate rx/tx external data and samples signals
---- 5: generate test sequences for sub-components
---- 6: store signals results as ASCII files
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/18: initial release
---- 2015/12/28: adding random stimuli generation
---- 2016/10/19: adding sub-components (CRC + buffer) test ressources
---- 2016/10/25: adding framer sub-component test ressources + CRC checks
---- 2016/10/27: adding serdes sub-component test ressources
---- 2016/10/30: framer tests improvements
---- 2016/11/04: adding lfsr sub-component test ressources
---- 2016/11/05: adding mapper sub-component test ressources
---- 2016/11/08: adding srrc + filter sub-components test ressources
---- 2016/11/18: adding differential coder + symbols to samples mapper sub-components test ressources
---- 2016/11/20: adding files output for samples to allow external software analysis
---- 2017/15/01: adding convolutional coder
-------------------------------
--TODO: functions for sub-components interactions and checks (wb_read, wb_write, buffer_read, ...)
-- To convert hexa ASCII encoded output files (hex) to binary files (raw wav) : xxd -r -p samples.hex > samples.wav
-- To change endianness: xxd -r -p samples.hex | dd conv=swab of=samples.wav
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
use work.ccsds_rxtx_functions.all;
use work.ccsds_rxtx_parameters.all;
use work.ccsds_rxtx_types.all;
--=============================================================================
-- Entity declaration for ccsds_rxtx_bench - rx/tx unit test tool
--=============================================================================
entity ccsds_rxtx_bench is
generic (
-- system parameters
CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH: integer := RX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH: integer := TX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_BENCH_RXTX0_WB_ADDR_BUS_SIZE: integer := RXTX_SYSTEM_WB_ADDR_BUS_SIZE;
CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE: integer := RXTX_SYSTEM_WB_DATA_BUS_SIZE;
CCSDS_RXTX_BENCH_RXTX0_WB_WRITE_CYCLES_MAX: integer := 8;
-- sub-systems parameters
-- BUFFER
CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE : integer := 32;
CCSDS_RXTX_BENCH_BUFFER0_SIZE : integer := 16;
-- CODER DIFFERENTIAL
CCSDS_RXTX_BENCH_CODER_DIFF0_BITS_PER_CODEWORD: integer := 4;
CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE: integer := 32;
-- CODER CONVOLUTIONAL
--TODO: 2 TESTS / ONE STATIC WITH PREDIFINED INPUT/ OUTPUT + ONE DYNAMIC WITH RANDOM DATA
CCSDS_RXTX_BENCH_CODER_CONV0_CONNEXION_VECTORS: std_logic_vector_array := ("1111001", "1011011");
CCSDS_RXTX_BENCH_CODER_CONV0_CONSTRAINT_SIZE: integer := 7;
CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE: integer := 8; --255
CCSDS_RXTX_BENCH_CODER_CONV0_OPERATING_MODE: integer := 1;
CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT_INVERSION: boolean_array := (false, true);
CCSDS_RXTX_BENCH_CODER_CONV0_RATE_OUTPUT: integer := 2;
CCSDS_RXTX_BENCH_CODER_CONV0_SEED: std_logic_vector := "000000";
CCSDS_RXTX_BENCH_CODER_CONV0_INPUT: std_logic_vector := "10000000";
CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT: std_logic_vector := "1011101001001001";
-- CRC
CCSDS_RXTX_BENCH_CRC0_DATA: std_logic_vector := x"313233343536373839";
CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_LENGTH: integer := 2;
CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL: std_logic_vector := x"1021";
CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_RESULT: std_logic_vector := x"e5cc";
CCSDS_RXTX_BENCH_CRC0_SEED: std_logic_vector := x"ffff";
CCSDS_RXTX_BENCH_CRC0_XOR: std_logic_vector := x"0000";
-- FILTER
CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE: integer := 32;
CCSDS_RXTX_BENCH_FILTER0_OFFSET_IQ: boolean := true;
CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO: integer := 4;
CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF: real := 0.5;
CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH: integer := 8;
CCSDS_RXTX_BENCH_FILTER0_TARGET_SNR: real := 40.0;
CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL: integer := 1;
CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE: integer := 1;
-- FRAMER
CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE: integer := 32;
CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH: integer := 24;
CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH: integer := 2;
CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH: integer := 6;
CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO: integer := 8;
-- LFSR
CCSDS_RXTX_BENCH_LFSR0_RESULT: std_logic_vector := "1111111101001000000011101100000010011010";
CCSDS_RXTX_BENCH_LFSR0_MEMORY_SIZE: integer := 8;
CCSDS_RXTX_BENCH_LFSR0_MODE: std_logic := '0';
CCSDS_RXTX_BENCH_LFSR0_POLYNOMIAL: std_logic_vector := x"A9";
CCSDS_RXTX_BENCH_LFSR0_SEED: std_logic_vector := x"FF";
-- MAPPER BITS SYMBOLS
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL: integer := 2;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE: integer := 32;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_MODULATION_TYPE: integer := 1;
-- MAPPER SYMBOLS SAMPLES
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL: integer := 3;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_QUANTIZATION_DEPTH: integer := 8;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_TARGET_SNR: real := 40.0;
-- SERDES
CCSDS_RXTX_BENCH_SERDES0_DEPTH: integer := 32;
-- SRRC
CCSDS_RXTX_BENCH_SRRC0_APODIZATION_WINDOW_TYPE: integer := 1;
CCSDS_RXTX_BENCH_SRRC0_OVERSAMPLING_RATIO: integer := 8;
CCSDS_RXTX_BENCH_SRRC0_ROLL_OFF: real := 0.5;
CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH: integer := 16;
-- simulation/test parameters
CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CODER_CONV0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CODER_DIFF0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE: integer:= 8;
CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER: integer:= 25;
CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_FILTER0_SYMBOL_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER: integer := 25;
CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD: time := 20 ns;
CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER: integer := 5000;
CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW: boolean := true;
CCSDS_RXTX_BENCH_SEED: integer := 123456789;
CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER: integer := 25;
CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_START_BUFFER_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_CODER_CONV_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_CODER_DIFF_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_CRC_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_FILTER_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_LFSR_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_MAPPER_BITS_SYMBOLS_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_MAPPER_SYMBOLS_SAMPLES_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION: time := 400 ns;
CCSDS_RXTX_BENCH_START_SERDES_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_SRRC_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_WB_WAIT_DURATION: time := 1600 ns;
CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE: boolean := true;
CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME: string := "samples"
);
end ccsds_rxtx_bench;
--=============================================================================
-- architecture declaration / internal processing
--=============================================================================
architecture behaviour of ccsds_rxtx_bench is
component ccsds_rxtx_top is
port(
wb_ack_o: out std_logic;
wb_adr_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_ADDR_BUS_SIZE-1 downto 0);
wb_clk_i: in std_logic;
wb_cyc_i: in std_logic;
wb_dat_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
wb_dat_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
wb_err_o: out std_logic;
wb_rst_i: in std_logic;
wb_rty_o: out std_logic;
wb_stb_i: in std_logic;
wb_we_i: in std_logic;
rx_clk_i: in std_logic;
rx_sam_i_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
rx_sam_q_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
rx_ena_o: out std_logic;
rx_irq_o: out std_logic;
tx_clk_i: in std_logic;
tx_dat_ser_i: in std_logic;
tx_buf_ful_o: out std_logic;
tx_idl_o: out std_logic;
tx_sam_i_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
tx_sam_q_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
tx_clk_o: out std_logic;
tx_ena_o: out std_logic
);
end component;
component ccsds_rxtx_buffer is
generic(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer;
CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_nxt_i: in std_logic;
rst_i: in std_logic;
buf_emp_o: out std_logic;
buf_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_coder_convolutional is
generic(
CCSDS_TX_CODER_CONV_CONNEXION_VECTORS: std_logic_vector_array;
CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE: integer;
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE: integer;
CCSDS_TX_CODER_CONV_OPERATING_MODE: integer;
CCSDS_TX_CODER_CONV_OUTPUT_INVERSION: boolean_array;
CCSDS_TX_CODER_CONV_RATE_OUTPUT: integer;
CCSDS_TX_CODER_CONV_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE*CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_coder_differential is
generic(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_rxtx_crc is
generic(
CCSDS_RXTX_CRC_DATA_LENGTH: integer;
CCSDS_RXTX_CRC_FINAL_XOR: std_logic_vector;
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED: boolean;
CCSDS_RXTX_CRC_INPUT_REFLECTED: boolean;
CCSDS_RXTX_CRC_LENGTH: integer;
CCSDS_RXTX_CRC_OUTPUT_REFLECTED: boolean;
CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector;
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED: boolean;
CCSDS_RXTX_CRC_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
nxt_i: in std_logic;
pad_dat_i: in std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
pad_dat_val_i: in std_logic;
rst_i: in std_logic;
crc_o: out std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
bus_o: out std_logic;
dat_val_o: out std_logic
);
end component;
component ccsds_tx_filter is
generic(
CCSDS_TX_FILTER_OFFSET_IQ: boolean;
CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
CCSDS_TX_FILTER_MODULATION_TYPE: integer;
CCSDS_TX_FILTER_TARGET_SNR: real;
CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sym_i_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_q_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
component ccsds_tx_framer is
generic (
CCSDS_TX_FRAMER_HEADER_LENGTH: integer;
CCSDS_TX_FRAMER_FOOTER_LENGTH: integer;
CCSDS_TX_FRAMER_DATA_LENGTH: integer;
CCSDS_TX_FRAMER_DATA_BUS_SIZE: integer;
CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic;
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_rxtx_lfsr is
generic(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer;
CCSDS_RXTX_LFSR_MEMORY_SIZE: integer;
CCSDS_RXTX_LFSR_MODE: std_logic;
CCSDS_RXTX_LFSR_POLYNOMIAL: std_logic_vector;
CCSDS_RXTX_LFSR_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_mapper_bits_symbols is
generic(
CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer;
CCSDS_TX_MAPPER_MODULATION_TYPE: integer;
CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_MAPPER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
sym_i_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_q_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_o: out std_logic
);
end component;
component ccsds_tx_mapper_symbols_samples is
generic(
CCSDS_TX_MAPPER_TARGET_SNR: real;
CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer;
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
sam_val_o: out std_logic;
sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
);
end component;
component ccsds_rxtx_serdes is
generic (
CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
clk_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_i: in std_logic;
dat_ser_i: in std_logic;
dat_ser_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_o: out std_logic;
dat_ser_o: out std_logic;
dat_ser_val_o: out std_logic
);
end component;
component ccsds_rxtx_srrc is
generic(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE: integer;
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_SRRC_ROLL_OFF: real;
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
sam_o: out std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
-- internal constants
constant CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD: time := CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD*CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO;
constant CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD: time := CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD * CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE * CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE / (CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL * 2);
constant CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD: time := CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD * CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE * CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_MODULATION_TYPE / (CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL * 2);
constant CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD: time := CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD/8;
constant CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD: time := CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD;
-- internal variables
signal bench_ena_buffer0_random_data: std_logic := '0';
signal bench_ena_coder_conv0_random_data: std_logic := '0';
signal bench_ena_coder_diff0_random_data: std_logic := '0';
signal bench_ena_crc0_random_data: std_logic := '0';
signal bench_ena_filter0_random_data: std_logic := '0';
signal bench_ena_framer0_random_data: std_logic := '0';
signal bench_ena_mapper_bits_symbols0_random_data: std_logic := '0';
signal bench_ena_mapper_symbols_samples0_random_data: std_logic := '0';
signal bench_ena_rxtx0_random_data: std_logic := '0';
signal bench_ena_serdes0_random_data: std_logic := '0';
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_iq.csv";
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_IQ_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_iq.hex";
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_I_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_i.hex";
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_Q_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_q.hex";
file CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_srrc0.hex";
-- synthetic generated stimuli
--NB: un-initialized on purposes - to allow observation of components default behaviour
-- wishbone bus
signal bench_sti_rxtx0_wb_clk: std_logic;
signal bench_sti_rxtx0_wb_rst: std_logic;
signal bench_sti_rxtx0_wb_adr: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_ADDR_BUS_SIZE-1 downto 0);
signal bench_sti_rxtx0_wb_cyc: std_logic;
signal bench_sti_rxtx0_wb_dat: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_rxtx0_wb_random_dat: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_rxtx0_wb_stb: std_logic;
signal bench_sti_rxtx0_wb_we: std_logic;
-- rx
signal bench_sti_rxtx0_rx_clk: std_logic;
signal bench_sti_rxtx0_rx_data_next: std_logic;
signal bench_sti_rxtx0_rx_samples_i: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
signal bench_sti_rxtx0_rx_samples_q: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
-- tx
signal bench_sti_rxtx0_tx_clk: std_logic;
signal bench_sti_rxtx0_tx_data_ser: std_logic;
-- buffer
signal bench_sti_buffer0_clk: std_logic;
signal bench_sti_buffer0_rst: std_logic;
signal bench_sti_buffer0_next_data: std_logic;
signal bench_sti_buffer0_data: std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_buffer0_data_valid: std_logic;
-- coder convolutional
signal bench_sti_coder_conv0_clk: std_logic;
signal bench_sti_coder_conv0_rst: std_logic;
signal bench_sti_coder_conv0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_coder_conv0_dat_val: std_logic;
-- coder differential
signal bench_sti_coder_diff0_clk: std_logic;
signal bench_sti_coder_diff0_rst: std_logic;
signal bench_sti_coder_diff0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_coder_diff0_dat_val: std_logic;
-- crc
signal bench_sti_crc0_clk: std_logic;
signal bench_sti_crc0_rst: std_logic;
signal bench_sti_crc0_nxt: std_logic;
signal bench_sti_crc0_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_DATA'length-1 downto 0);
signal bench_sti_crc0_padding_data_valid: std_logic;
signal bench_sti_crc0_check_nxt: std_logic;
signal bench_sti_crc0_check_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_sti_crc0_check_padding_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_sti_crc0_check_padding_data_valid: std_logic;
signal bench_sti_crc0_random_nxt: std_logic;
signal bench_sti_crc0_random_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_sti_crc0_random_padding_data_valid: std_logic;
-- filter
signal bench_sti_filter0_clk: std_logic;
signal bench_sti_filter0_rst: std_logic;
signal bench_sti_filter0_sym_i: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL-1 downto 0);
signal bench_sti_filter0_sym_q: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL-1 downto 0);
signal bench_sti_filter0_sym_val: std_logic;
signal bench_sti_filter0_mapper_data: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_filter0_mapper_clk: std_logic;
signal bench_sti_filter0_mapper_dat_val: std_logic;
-- framer
signal bench_sti_framer0_clk: std_logic;
signal bench_sti_framer0_rst: std_logic;
signal bench_sti_framer0_data_valid: std_logic;
signal bench_sti_framer0_data: std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
-- lfsr
signal bench_sti_lfsr0_clk: std_logic;
signal bench_sti_lfsr0_rst: std_logic;
-- mapper bits symbols
signal bench_sti_mapper_bits_symbols0_clk: std_logic;
signal bench_sti_mapper_bits_symbols0_rst: std_logic;
signal bench_sti_mapper_bits_symbols0_data: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_mapper_bits_symbols0_dat_val: std_logic;
-- mapper symbols samples
signal bench_sti_mapper_symbols_samples0_clk: std_logic;
signal bench_sti_mapper_symbols_samples0_rst: std_logic;
signal bench_sti_mapper_symbols_samples0_sym: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL-1 downto 0);
signal bench_sti_mapper_symbols_samples0_sym_val: std_logic;
-- serdes
signal bench_sti_serdes0_clk: std_logic;
signal bench_sti_serdes0_rst: std_logic;
signal bench_sti_serdes0_data_par_valid: std_logic;
signal bench_sti_serdes0_data_par: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
signal bench_sti_serdes0_data_ser_valid: std_logic;
signal bench_sti_serdes0_data_ser: std_logic;
-- srrc
signal bench_sti_srrc0_clk: std_logic;
signal bench_sti_srrc0_rst: std_logic;
signal bench_sti_srrc0_sam: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_sti_srrc0_sam_val: std_logic;
-- core generated response
-- wishbone bus
signal bench_res_rxtx0_wb_ack: std_logic;
signal bench_res_rxtx0_wb_dat: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
signal bench_res_rxtx0_wb_err: std_logic;
signal bench_res_rxtx0_wb_rty: std_logic;
-- rx
signal bench_res_rxtx0_rx_ena: std_logic;
signal bench_res_rxtx0_rx_irq: std_logic;
-- tx
signal bench_res_rxtx0_tx_clk: std_logic;
signal bench_res_rxtx0_tx_buf_ful: std_logic;
signal bench_res_rxtx0_tx_idl: std_logic;
signal bench_res_rxtx0_tx_samples_i: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_rxtx0_tx_samples_q: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_rxtx0_tx_ena: std_logic;
-- buffer
signal bench_res_buffer0_buffer_empty: std_logic;
signal bench_res_buffer0_buffer_full: std_logic;
signal bench_res_buffer0_data: std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
signal bench_res_buffer0_data_valid: std_logic;
-- coder convolutional
signal bench_res_coder_conv0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE*CCSDS_RXTX_BENCH_CODER_CONV0_RATE_OUTPUT-1 downto 0);
signal bench_res_coder_conv0_dat_val: std_logic;
signal bench_res_coder_conv0_bus: std_logic;
-- coder differential
signal bench_res_coder_diff0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
signal bench_res_coder_diff0_dat_val: std_logic;
-- crc
signal bench_res_crc0_busy: std_logic;
signal bench_res_crc0_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_res_crc0_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_DATA'length-1 downto 0);
signal bench_res_crc0_data_valid: std_logic;
signal bench_res_crc0_check_busy: std_logic;
signal bench_res_crc0_check_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_res_crc0_check_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_res_crc0_check_data_valid: std_logic;
signal bench_res_crc0_random_busy: std_logic;
signal bench_res_crc0_random_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_res_crc0_random_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_res_crc0_random_data_valid: std_logic;
-- filter
signal bench_res_filter0_sam_i: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_sam_q: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_sam_val: std_logic;
signal bench_res_filter0_srrc_sam_i: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_srrc_sam_q: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_srrc_sam_i_val: std_logic;
signal bench_res_filter0_srrc_sam_q_val: std_logic;
-- framer
signal bench_res_framer0_data_valid: std_logic;
signal bench_res_framer0_dat_nxt: std_logic;
signal bench_res_framer0_idl: std_logic;
signal bench_res_framer0_data: std_logic_vector((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH)*8-1 downto 0);
-- lfsr
signal bench_res_lfsr0_data_valid: std_logic;
signal bench_res_lfsr0_data: std_logic_vector(CCSDS_RXTX_BENCH_LFSR0_RESULT'length-1 downto 0);
-- mapper bits symbols
signal bench_res_mapper_bits_symbols0_sym_i: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL-1 downto 0);
signal bench_res_mapper_bits_symbols0_sym_q: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL-1 downto 0);
signal bench_res_mapper_bits_symbols0_sym_val: std_logic;
-- mapper symbols samples
signal bench_res_mapper_symbols_samples0_sam: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_QUANTIZATION_DEPTH-1 downto 0);
signal bench_res_mapper_symbols_samples0_sam_val: std_logic;
-- serdes
signal bench_res_serdes0_busy: std_logic;
signal bench_res_serdes0_data_par: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
signal bench_res_serdes0_data_par_valid: std_logic;
signal bench_res_serdes0_data_ser: std_logic;
signal bench_res_serdes0_data_ser_valid: std_logic;
-- srrc
signal bench_res_srrc0_sam: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_srrc0_sam_val: std_logic;
signal bench_res_srrc1_sam: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_srrc1_sam_val: std_logic;
--=============================================================================
-- architecture begin
--=============================================================================
begin
-- Instance(s) of unit under test
rxtx_000: ccsds_rxtx_top
port map(
wb_ack_o => bench_res_rxtx0_wb_ack,
wb_adr_i => bench_sti_rxtx0_wb_adr,
wb_clk_i => bench_sti_rxtx0_wb_clk,
wb_cyc_i => bench_sti_rxtx0_wb_cyc,
wb_dat_i => bench_sti_rxtx0_wb_dat,
wb_dat_o => bench_res_rxtx0_wb_dat,
wb_err_o => bench_res_rxtx0_wb_err,
wb_rst_i => bench_sti_rxtx0_wb_rst,
wb_rty_o => bench_res_rxtx0_wb_rty,
wb_stb_i => bench_sti_rxtx0_wb_stb,
wb_we_i => bench_sti_rxtx0_wb_we,
rx_clk_i => bench_sti_rxtx0_rx_clk,
rx_sam_i_i => bench_sti_rxtx0_rx_samples_i,
rx_sam_q_i => bench_sti_rxtx0_rx_samples_q,
rx_irq_o => bench_res_rxtx0_rx_irq,
rx_ena_o => bench_res_rxtx0_rx_ena,
tx_clk_i => bench_sti_rxtx0_tx_clk,
tx_dat_ser_i => bench_sti_rxtx0_tx_data_ser,
tx_sam_i_o => bench_res_rxtx0_tx_samples_i,
tx_sam_q_o => bench_res_rxtx0_tx_samples_q,
tx_clk_o => bench_res_rxtx0_tx_clk,
tx_buf_ful_o => bench_res_rxtx0_tx_buf_ful,
tx_idl_o => bench_res_rxtx0_tx_idl,
tx_ena_o => bench_res_rxtx0_tx_ena
);
-- Instance(s) of sub-components under test
buffer_000: ccsds_rxtx_buffer
generic map(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE,
CCSDS_RXTX_BUFFER_SIZE => CCSDS_RXTX_BENCH_BUFFER0_SIZE
)
port map(
clk_i => bench_sti_buffer0_clk,
rst_i => bench_sti_buffer0_rst,
dat_val_i => bench_sti_buffer0_data_valid,
dat_i => bench_sti_buffer0_data,
dat_val_o => bench_res_buffer0_data_valid,
buf_emp_o => bench_res_buffer0_buffer_empty,
buf_ful_o => bench_res_buffer0_buffer_full,
dat_nxt_i => bench_sti_buffer0_next_data,
dat_o => bench_res_buffer0_data
);
coder_convolutionial_000: ccsds_tx_coder_convolutional
generic map(
CCSDS_TX_CODER_CONV_CONNEXION_VECTORS => CCSDS_RXTX_BENCH_CODER_CONV0_CONNEXION_VECTORS,
CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE => CCSDS_RXTX_BENCH_CODER_CONV0_CONSTRAINT_SIZE,
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE,
CCSDS_TX_CODER_CONV_OPERATING_MODE => CCSDS_RXTX_BENCH_CODER_CONV0_OPERATING_MODE,
CCSDS_TX_CODER_CONV_OUTPUT_INVERSION => CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT_INVERSION,
CCSDS_TX_CODER_CONV_RATE_OUTPUT => CCSDS_RXTX_BENCH_CODER_CONV0_RATE_OUTPUT,
CCSDS_TX_CODER_CONV_SEED => CCSDS_RXTX_BENCH_CODER_CONV0_SEED
)
port map(
clk_i => bench_sti_coder_conv0_clk,
rst_i => bench_sti_coder_conv0_rst,
dat_val_i => bench_sti_coder_conv0_dat_val,
dat_i => bench_sti_coder_conv0_dat,
bus_o => bench_res_coder_conv0_bus,
dat_val_o => bench_res_coder_conv0_dat_val,
dat_o => bench_res_coder_conv0_dat
);
coder_differential_000: ccsds_tx_coder_differential
generic map(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_RXTX_BENCH_CODER_DIFF0_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE
)
port map(
clk_i => bench_sti_coder_diff0_clk,
rst_i => bench_sti_coder_diff0_rst,
dat_val_i => bench_sti_coder_diff0_dat_val,
dat_i => bench_sti_coder_diff0_dat,
dat_val_o => bench_res_coder_diff0_dat_val,
dat_o => bench_res_coder_diff0_dat
);
crc_000: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_DATA'length/8,
CCSDS_RXTX_CRC_LENGTH => CCSDS_RXTX_BENCH_CRC0_LENGTH,
CCSDS_RXTX_CRC_POLYNOMIAL => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL,
CCSDS_RXTX_CRC_SEED => CCSDS_RXTX_BENCH_CRC0_SEED,
CCSDS_RXTX_CRC_INPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED,
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED,
CCSDS_RXTX_CRC_OUTPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED,
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED,
CCSDS_RXTX_CRC_FINAL_XOR => CCSDS_RXTX_BENCH_CRC0_XOR
)
port map(
clk_i => bench_sti_crc0_clk,
rst_i => bench_sti_crc0_rst,
nxt_i => bench_sti_crc0_nxt,
bus_o => bench_res_crc0_busy,
dat_i => bench_sti_crc0_data,
pad_dat_i => (others => '0'),
pad_dat_val_i => bench_sti_crc0_padding_data_valid,
crc_o => bench_res_crc0_crc,
dat_o => bench_res_crc0_data,
dat_val_o => bench_res_crc0_data_valid
);
crc_001: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE,
CCSDS_RXTX_CRC_LENGTH => CCSDS_RXTX_BENCH_CRC0_LENGTH,
CCSDS_RXTX_CRC_POLYNOMIAL => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL,
CCSDS_RXTX_CRC_SEED => CCSDS_RXTX_BENCH_CRC0_SEED,
CCSDS_RXTX_CRC_INPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED,
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED,
CCSDS_RXTX_CRC_OUTPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED,
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED,
CCSDS_RXTX_CRC_FINAL_XOR => CCSDS_RXTX_BENCH_CRC0_XOR
)
port map(
clk_i => bench_sti_crc0_clk,
rst_i => bench_sti_crc0_rst,
nxt_i => bench_sti_crc0_random_nxt,
bus_o => bench_res_crc0_random_busy,
dat_i => bench_sti_crc0_random_data,
pad_dat_i => (others => '0'),
pad_dat_val_i => bench_sti_crc0_random_padding_data_valid,
crc_o => bench_res_crc0_random_crc,
dat_o => bench_res_crc0_random_data,
dat_val_o => bench_res_crc0_random_data_valid
);
crc_002: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE,
CCSDS_RXTX_CRC_LENGTH => CCSDS_RXTX_BENCH_CRC0_LENGTH,
CCSDS_RXTX_CRC_POLYNOMIAL => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL,
CCSDS_RXTX_CRC_SEED => CCSDS_RXTX_BENCH_CRC0_SEED,
CCSDS_RXTX_CRC_INPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED,
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED,
CCSDS_RXTX_CRC_OUTPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED,
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED,
CCSDS_RXTX_CRC_FINAL_XOR => CCSDS_RXTX_BENCH_CRC0_XOR
)
port map(
clk_i => bench_sti_crc0_clk,
rst_i => bench_sti_crc0_rst,
nxt_i => bench_sti_crc0_check_nxt,
bus_o => bench_res_crc0_check_busy,
dat_i => bench_sti_crc0_check_data,
pad_dat_val_i => bench_sti_crc0_check_padding_data_valid,
pad_dat_i => bench_sti_crc0_check_padding_data,
crc_o => bench_res_crc0_check_crc,
dat_o => bench_res_crc0_check_data,
dat_val_o => bench_res_crc0_check_data_valid
);
filter000: ccsds_tx_filter
generic map(
CCSDS_TX_FILTER_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
CCSDS_TX_FILTER_OFFSET_IQ => CCSDS_RXTX_BENCH_FILTER0_OFFSET_IQ,
CCSDS_TX_FILTER_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH,
CCSDS_TX_FILTER_MODULATION_TYPE => CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE,
CCSDS_TX_FILTER_TARGET_SNR => CCSDS_RXTX_BENCH_FILTER0_TARGET_SNR,
CCSDS_TX_FILTER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_filter0_clk,
sym_i_i => bench_sti_filter0_sym_i,
sym_q_i => bench_sti_filter0_sym_q,
sym_val_i => bench_sti_filter0_sym_val,
rst_i => bench_sti_filter0_rst,
sam_val_o => bench_res_filter0_sam_val,
sam_i_o => bench_res_filter0_sam_i,
sam_q_o => bench_res_filter0_sam_q
);
framer_000: ccsds_tx_framer
generic map (
CCSDS_TX_FRAMER_HEADER_LENGTH => CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH,
CCSDS_TX_FRAMER_FOOTER_LENGTH => CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH,
CCSDS_TX_FRAMER_DATA_LENGTH => CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH,
CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE,
CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO => CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO
)
port map(
clk_i => bench_sti_framer0_clk,
rst_i => bench_sti_framer0_rst,
dat_val_i => bench_sti_framer0_data_valid,
dat_i => bench_sti_framer0_data,
dat_val_o => bench_res_framer0_data_valid,
dat_o => bench_res_framer0_data,
dat_nxt_o => bench_res_framer0_dat_nxt,
idl_o => bench_res_framer0_idl
);
lfsr_000: ccsds_rxtx_lfsr
generic map(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_LFSR0_RESULT'length,
CCSDS_RXTX_LFSR_MEMORY_SIZE => CCSDS_RXTX_BENCH_LFSR0_MEMORY_SIZE,
CCSDS_RXTX_LFSR_MODE => CCSDS_RXTX_BENCH_LFSR0_MODE,
CCSDS_RXTX_LFSR_POLYNOMIAL => CCSDS_RXTX_BENCH_LFSR0_POLYNOMIAL,
CCSDS_RXTX_LFSR_SEED => CCSDS_RXTX_BENCH_LFSR0_SEED
)
port map(
clk_i => bench_sti_lfsr0_clk,
rst_i => bench_sti_lfsr0_rst,
dat_val_o => bench_res_lfsr0_data_valid,
dat_o => bench_res_lfsr0_data
);
mapper_bits_symbols_000: ccsds_tx_mapper_bits_symbols
generic map(
CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE,
CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_MODULATION_TYPE,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_mapper_bits_symbols0_clk,
dat_i => bench_sti_mapper_bits_symbols0_data,
dat_val_i => bench_sti_mapper_bits_symbols0_dat_val,
rst_i => bench_sti_mapper_bits_symbols0_rst,
sym_i_o => bench_res_mapper_bits_symbols0_sym_i,
sym_q_o => bench_res_mapper_bits_symbols0_sym_q,
sym_val_o => bench_res_mapper_bits_symbols0_sym_val
);
mapper_bits_symbols_001: ccsds_tx_mapper_bits_symbols
generic map(
CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE,
CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_filter0_mapper_clk,
dat_i => bench_sti_filter0_mapper_data,
dat_val_i => bench_sti_filter0_mapper_dat_val,
rst_i => bench_sti_filter0_rst,
sym_i_o => bench_sti_filter0_sym_i,
sym_q_o => bench_sti_filter0_sym_q,
sym_val_o => bench_sti_filter0_sym_val
);
mapper_symbols_samples_000: ccsds_tx_mapper_symbols_samples
generic map(
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_QUANTIZATION_DEPTH,
CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_TARGET_SNR,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_mapper_symbols_samples0_clk,
sym_i => bench_sti_mapper_symbols_samples0_sym,
sym_val_i => bench_sti_mapper_symbols_samples0_sym_val,
rst_i => bench_sti_mapper_symbols_samples0_rst,
sam_o => bench_res_mapper_symbols_samples0_sam,
sam_val_o => bench_res_mapper_symbols_samples0_sam_val
);
serdes_000: ccsds_rxtx_serdes
generic map(
CCSDS_RXTX_SERDES_DEPTH => CCSDS_RXTX_BENCH_SERDES0_DEPTH
)
port map(
clk_i => bench_sti_serdes0_clk,
dat_par_i => bench_sti_serdes0_data_par,
dat_par_val_i => bench_sti_serdes0_data_par_valid,
dat_ser_i => bench_sti_serdes0_data_ser,
dat_ser_val_i => bench_sti_serdes0_data_ser_valid,
rst_i => bench_sti_serdes0_rst,
bus_o => bench_res_serdes0_busy,
dat_par_o => bench_res_serdes0_data_par,
dat_par_val_o => bench_res_serdes0_data_par_valid,
dat_ser_o => bench_res_serdes0_data_ser,
dat_ser_val_o => bench_res_serdes0_data_ser_valid
);
srrc_000: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => CCSDS_RXTX_BENCH_SRRC0_APODIZATION_WINDOW_TYPE,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_SRRC0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_SRRC0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_srrc0_clk,
sam_i => bench_sti_srrc0_sam,
sam_val_i => bench_sti_srrc0_sam_val,
rst_i => bench_sti_srrc0_rst,
sam_o => bench_res_srrc0_sam,
sam_val_o => bench_res_srrc0_sam_val
);
srrc_001: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => CCSDS_RXTX_BENCH_SRRC0_APODIZATION_WINDOW_TYPE,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_SRRC0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_SRRC0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_srrc0_clk,
sam_i => bench_res_srrc0_sam,
sam_val_i => bench_res_srrc0_sam_val,
rst_i => bench_sti_srrc0_rst,
sam_o => bench_res_srrc1_sam,
sam_val_o => bench_res_srrc1_sam_val
);
srrc_002: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => 1,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_filter0_clk,
sam_i => bench_res_filter0_sam_i,
sam_val_i => bench_res_filter0_sam_val,
rst_i => bench_sti_filter0_rst,
sam_o => bench_res_filter0_srrc_sam_i,
sam_val_o => bench_res_filter0_srrc_sam_i_val
);
srrc_003: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => 1,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_filter0_clk,
sam_i => bench_res_filter0_sam_q,
sam_val_i => bench_res_filter0_sam_val,
rst_i => bench_sti_filter0_rst,
sam_o => bench_res_filter0_srrc_sam_q,
sam_val_o => bench_res_filter0_srrc_sam_q_val
);
--=============================================================================
-- Begin of bench_sti_rxtx0_wb_clkp
-- bench_sti_rxtx0_wb_clk generation
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_wb_clk
-- r/w:
BENCH_STI_RXTX0_WB_CLKP : process
begin
bench_sti_rxtx0_wb_clk <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD/2;
bench_sti_rxtx0_wb_clk <= '0';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_rx_clkp
-- bench_sti_rxtx0_rx_clk generation
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_rx_clk
-- r/w:
BENCH_STI_RXTX0_RX_CLKP : process
begin
bench_sti_rxtx0_rx_clk <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD/2;
bench_sti_rxtx0_rx_clk <= '0';
wait for CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_tx_clkp
-- bench_sti_rxtx0_tx_clk generation
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_tx_clk
-- r/w:
BENCH_STI_RXTX0_TX_CLKP : process
begin
bench_sti_rxtx0_tx_clk <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD/2;
bench_sti_rxtx0_tx_clk <= '0';
wait for CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_buffer0_clkp
-- bench_sti_buffer0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_buffer0_clk
-- r/w:
BENCH_STI_BUFFER0_CLKP : process
begin
bench_sti_buffer0_clk <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
bench_sti_buffer0_clk <= '0';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_coder_conv0_clk
-- bench_sti_coder_conv0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_coder_conv0_clk
-- r/w:
BENCH_STI_CODER_CONV0_CLKP : process
begin
bench_sti_coder_conv0_clk <= '1';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD/2;
bench_sti_coder_conv0_clk <= '0';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_coder_diff0_clk
-- bench_sti_coder_diff0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_coder_diff0_clk
-- r/w:
BENCH_STI_CODER_DIFF0_CLKP : process
begin
bench_sti_coder_diff0_clk <= '1';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD/2;
bench_sti_coder_diff0_clk <= '0';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_crc0_clkp
-- bench_sti_crc0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_crc0_clk
-- r/w:
BENCH_STI_CRC0_CLKP : process
begin
bench_sti_crc0_clk <= '1';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
bench_sti_crc0_clk <= '0';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_filter0_clkp
-- bench_sti_filter0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_filter0_clk
-- r/w:
BENCH_STI_FILTER0_CLKP : process
begin
bench_sti_filter0_clk <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD/2;
bench_sti_filter0_clk <= '0';
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_filter0_mapper_clkp
-- bench_sti_filter0_mapper_clk generation
--=============================================================================
-- read:
-- write: bench_sti_filter0_mapper_clk
-- r/w:
BENCH_STI_FILTER0_MAPPER_CLKP : process
begin
bench_sti_filter0_mapper_clk <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD/2;
bench_sti_filter0_mapper_clk <= '0';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_framer0_clkp
-- bench_sti_framer0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_framer0_clk
-- r/w:
BENCH_STI_FRAMER0_CLKP : process
begin
bench_sti_framer0_clk <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
bench_sti_framer0_clk <= '0';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_lfsr0_clkp
-- bench_sti_lfsr0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_lfsr0_clk
-- r/w:
BENCH_STI_LFSR0_CLKP : process
begin
bench_sti_lfsr0_clk <= '1';
wait for CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD/2;
bench_sti_lfsr0_clk <= '0';
wait for CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_bits_symbols0_clkp
-- bench_sti_mapper_bits_symbols0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_mapper_bits_symbols0_clk
-- r/w:
BENCH_STI_MAPPER_BITS_SYMBOLS0_CLKP : process
begin
bench_sti_mapper_bits_symbols0_clk <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD/2;
bench_sti_mapper_bits_symbols0_clk <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_symbols_samples0_clkp
-- bench_sti_mapper_symbols_samples0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_mapper_symbols_samples0_clk
-- r/w:
BENCH_STI_MAPPER_SYMBOLS_SAMPLES0_CLKP : process
begin
bench_sti_mapper_symbols_samples0_clk <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD/2;
bench_sti_mapper_symbols_samples0_clk <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_serdes0_clkp
-- bench_sti_serdes0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_serdes0_clk
-- r/w:
BENCH_STI_SERDES0_CLKP : process
begin
bench_sti_serdes0_clk <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
bench_sti_serdes0_clk <= '0';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_srrc0_clkp
-- bench_sti_srrc0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_srrc0_clk
-- r/w:
BENCH_STI_SRRC0_CLKP : process
begin
bench_sti_srrc0_clk <= '1';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD/2;
bench_sti_srrc0_clk <= '0';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_tx_datap
-- bench_sti_rxtx0_tx_data generation / dephased from 1/2 clk with bench_sti_rxtx0_tx_clk
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_tx_data_ser0
-- r/w:
BENCH_STI_RXTX0_TX_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(1 downto 0);
begin
if (bench_ena_rxtx0_random_data = '1') then
sim_generate_random_std_logic_vector(2,seed1,seed2,random);
bench_sti_rxtx0_tx_data_ser <= random(0);
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_buffer0_datap
-- bench_sti_buffer0_data generation
--=============================================================================
-- read: bench_ena_buffer0_random_data
-- write: bench_sti_buffer0_data
-- r/w:
BENCH_STI_BUFFER0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_buffer0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_buffer0_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_coder_conv0_datap
-- bench_sti_coder_conv0_random_data generation
--=============================================================================
-- read: bench_ena_coder_conv0_random_data
-- write: bench_sti_coder_conv0_dat
-- r/w:
BENCH_STI_CODER_CONV0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE-1 downto 0);
begin
-- if (bench_ena_coder_conv0_random_data = '1') then
-- sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE,seed1,seed2,random);
-- bench_sti_coder_conv0_dat <= random;
-- end if;
-- wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
bench_sti_coder_conv0_dat <= CCSDS_RXTX_BENCH_CODER_CONV0_INPUT;
wait;
end process;
--=============================================================================
-- Begin of bench_sti_coder_diff0_datap
-- bench_sti_coder_diff0_random_data generation
--=============================================================================
-- read: bench_ena_coder_diff0_random_data
-- write: bench_sti_coder_diff0_dat
-- r/w:
BENCH_STI_CODER_DIFF0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_coder_diff0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_coder_diff0_dat <= random;
end if;
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_crc0_datap
-- bench_sti_crc0_random_data generation
--=============================================================================
-- read: bench_ena_crc0_random_data
-- write: bench_sti_crc0_random_data
-- r/w:
BENCH_STI_CRC0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
begin
if (bench_ena_crc0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8,seed1,seed2,random);
bench_sti_crc0_random_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_filter0_datap
-- bench_sti_filter0_mapper_data generation
--=============================================================================
-- read: bench_ena_filter0_random_data
-- write: bench_sti_filter0_mapper_data
-- r/w:
BENCH_STI_FILTER0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_filter0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_filter0_mapper_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_framer0_datap
-- bench_sti_framer0_data generation
--=============================================================================
-- read: bench_ena_framer0_random_data
-- write: bench_sti_framer0_data
-- r/w:
BENCH_STI_FRAMER0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_framer0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_framer0_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_bits_symbols0_datap
-- bench_sti_mapper_bits_symbols0_data generation
--=============================================================================
-- read: bench_ena_mapper_bits_symbols0_random_data
-- write: bench_sti_mapper_bits_symbols0_data
-- r/w:
BENCH_STI_MAPPER_BITS_SYMBOLS0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_mapper_bits_symbols0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_mapper_bits_symbols0_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_symbols_samples0_datap
-- bench_sti_mapper_symbols_samples0_data generation
--=============================================================================
-- read: bench_ena_mapper_symbols_samples0_random_data
-- write: bench_sti_mapper_symbols_samples0_data
-- r/w:
BENCH_STI_MAPPER_SYMBOLS_SAMPLES0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL-1 downto 0);
begin
if (bench_ena_mapper_symbols_samples0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL,seed1,seed2,random);
bench_sti_mapper_symbols_samples0_sym <= random;
end if;
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_serdes0_datap
-- bench_sti_serdes0_data generation
--=============================================================================
-- read: bench_ena_serdes0_random_data
-- write: bench_sti_serdes0_data_par, bench_sti_serdes0_data_ser
-- r/w:
BENCH_STI_SERDES0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
begin
if (bench_ena_serdes0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH,seed1,seed2,random);
bench_sti_serdes0_data_par <= random;
bench_sti_serdes0_data_ser <= random(0);
end if;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_rx_samplesp
-- bench_sti_rxtx0_rx_samples generation
--=============================================================================
-- read: bench_ena_rxtx0_random_data
-- write: bench_sti_rxtx0_rx_samples_i, bench_sti_rxtx0_rx_samples_q
-- r/w:
BENCH_STI_RXTX0_RX_SAMPLESP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random1 : std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
variable random2 : std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
begin
if (bench_ena_rxtx0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH,seed1,seed2,random1);
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH,seed2,seed1,random2);
bench_sti_rxtx0_rx_samples_i <= random1;
bench_sti_rxtx0_rx_samples_q <= random2;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_wb_datap
-- bench_sti_rxtx0_wb_random_dat generation
--=============================================================================
-- read: bench_ena_rxtx0_random_data
-- write: bench_sti_rxtx0_wb_random_dat0
-- r/w:
BENCH_STI_RXTX0_WB_DATP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random1 : std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_rxtx0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE,seed1,seed2,random1);
bench_sti_rxtx0_wb_random_dat <= random1;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bufferrwp
-- generation of buffer subsystem read-write unit-tests
--=============================================================================
-- read: bench_res_buffer0_buffer_empty, bench_res_buffer0_buffer_full, bench_res_buffer0_data, bench_res_buffer0_data_valid
-- write: bench_sti_buffer0_data_valid, bench_sti_buffer0_next_data, bench_ena_buffer0_random_data
-- r/w:
BUFFERRWP : process
type buffer_array is array (CCSDS_RXTX_BENCH_BUFFER0_SIZE downto 0) of std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
variable buffer_expected_stored_data: buffer_array := (others => (others => '0'));
variable buffer_content_ok: std_logic := '1';
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- check buffer is empty
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Default state - Buffer is empty" severity note;
else
report "BUFFERRWP: KO - Default state - Buffer is not empty" severity warning;
end if;
-- check buffer is not full
if (bench_res_buffer0_buffer_full = '0')then
report "BUFFERRWP: OK - Default state - Buffer is not full" severity note;
else
report "BUFFERRWP: KO - Default state - Buffer is full" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_BUFFER_WAIT_DURATION);
-- initial state tests:
-- check buffer is empty
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Initial state - Buffer is empty" severity note;
else
report "BUFFERRWP: KO - Initial state - Buffer is not empty" severity warning;
end if;
-- check buffer is not full
if (bench_res_buffer0_buffer_full = '0')then
report "BUFFERRWP: OK - Initial state - Buffer is not full" severity note;
else
report "BUFFERRWP: KO - Initial state - Buffer is full" severity warning;
end if;
-- behaviour tests:
report "BUFFERRWP: START BUFFER READ-WRITE TESTS" severity note;
-- ask for data
bench_sti_buffer0_next_data <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (bench_res_buffer0_data_valid = '0') then
report "BUFFERRWP: OK - No data came out with an empty buffer" severity note;
else
report "BUFFERRWP: KO - Data came out - buffer is empty / incoherent" severity warning;
end if;
bench_sti_buffer0_next_data <= '0';
bench_ena_buffer0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
-- store data
bench_sti_buffer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
buffer_expected_stored_data(0) := bench_sti_buffer0_data;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
bench_sti_buffer0_data_valid <= '0';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (bench_res_buffer0_buffer_empty = '0') then
report "BUFFERRWP: OK - Buffer is not empty" severity note;
else
report "BUFFERRWP: KO - Buffer should not be empty" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
-- get data
bench_sti_buffer0_next_data <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
bench_sti_buffer0_next_data <= '0';
if (bench_res_buffer0_data_valid = '1') then
report "BUFFERRWP: OK - Data valid signal received" severity note;
else
report "BUFFERRWP: KO - Data valid signal not received" severity warning;
end if;
if (bench_res_buffer0_data = buffer_expected_stored_data(0)) then
report "BUFFERRWP: OK - Received value is equal to previously stored value" severity note;
else
report "BUFFERRWP: KO - Received value is different from previously stored value" severity warning;
report "Received value:" severity note;
for i in 0 to bench_res_buffer0_data'length-1 loop
report std_logic'image(bench_res_buffer0_data(i));
end loop;
report "Expected value:" severity note;
for i in 0 to buffer_expected_stored_data(0)'length-1 loop
report std_logic'image(buffer_expected_stored_data(0)(i));
end loop;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Buffer is empty after reading value" severity note;
else
report "BUFFERRWP: KO - Buffer is not empty" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
-- store lot of data / make the buffer full
bench_sti_buffer0_data_valid <= '1';
for i in 0 to CCSDS_RXTX_BENCH_BUFFER0_SIZE loop
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
buffer_expected_stored_data(i) := bench_sti_buffer0_data;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
if (bench_res_buffer0_buffer_full = '1') then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Buffer is full too early - loop: " & integer'image(i) & " value of the buffer array" severity warning;
else
report "BUFFERRWP: OK - Buffer is full after all write operations" severity note;
end if;
else
if (i = CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Buffer is not full after all write operations" severity note;
end if;
end if;
end loop;
bench_sti_buffer0_data_valid <= '0';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
bench_ena_buffer0_random_data <= '0';
-- read all data / make the buffer empty
bench_sti_buffer0_next_data <= '1';
for i in 0 to CCSDS_RXTX_BENCH_BUFFER0_SIZE loop
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (buffer_expected_stored_data(i) /= bench_res_buffer0_data) then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Received value is different from previously stored value - loop: " & integer'image(i) severity warning;
buffer_content_ok := '0';
end if;
end if;
if (i = CCSDS_RXTX_BENCH_BUFFER0_SIZE) and (buffer_content_ok = '1') then
report "BUFFERRWP: OK - Received values are all equal to previously stored values" severity note;
end if;
if (bench_res_buffer0_data_valid = '0') then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Data valid signal not received - loop: " & integer'image(i) severity warning;
end if;
end if;
if (bench_res_buffer0_buffer_empty = '1') then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Data empty signal received too early - loop: " & integer'image(i) severity warning;
else
report "BUFFERRWP: OK - Buffer is empty after all read operations" severity note;
end if;
else
if (i = CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Buffer is not empty after all read operations" severity warning;
end if;
end if;
end loop;
bench_sti_buffer0_next_data <= '0';
-- final state tests:
-- check buffer is empty
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Final state - Buffer is empty" severity note;
else
report "BUFFERRWP: KO - Final state - Buffer is not empty" severity warning;
end if;
-- check buffer is not full
if (bench_res_buffer0_buffer_full = '0')then
report "BUFFERRWP: OK - Final state - Buffer is not full" severity note;
else
report "BUFFERRWP: KO - Final state - Buffer is full" severity warning;
end if;
report "BUFFERRWP: END BUFFER READ-WRITE TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of coderconvp
-- generation of coder convolutional subsystem unit-tests
--=============================================================================
-- read: bench_res_coder_conv0_dat, bench_res_coder_conv0_dat_val, bench_res_coder_conv0_bus
-- write: bench_ena_coder_conv0_random_data, bench_sti_coder_conv0_dat_val
-- r/w:
CODERCONVP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_coder_conv0_dat_val = '1') then
report "CODERCONVP: KO - Default state - Convolutional coder output data is valid" severity warning;
else
report "CODERCONVP: OK - Default state - Convolutional coder output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CODER_CONV_WAIT_DURATION);
-- initial state tests:
if (bench_res_coder_conv0_dat_val = '1') then
report "CODERCONVP: KO - Initial state - Convolutional coder output data is valid" severity warning;
else
report "CODERCONVP: OK - Initial state - Convolutional coder output data is not valid" severity note;
end if;
-- behaviour tests:
report "CODERCONVP: START CONVOLUTIONAL CODER TESTS" severity note;
bench_ena_coder_conv0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
for coder_current_check in 0 to CCSDS_RXTX_BENCH_CODER_CONV0_WORDS_NUMBER-1 loop
for coder_current_bit in 0 to CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE loop
if (coder_current_bit = 0) then
bench_sti_coder_conv0_dat_val <= '1';
else
bench_sti_coder_conv0_dat_val <= '0';
end if;
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
end loop;
if (bench_res_coder_conv0_dat_val = '0') then
report "CODERCONVP: KO - Convolutional coder output data is not valid" severity warning;
else
if (bench_res_coder_conv0_dat = CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT) then
report "CODERCONVP: OK - Convolutional coder output data match" severity note;
else
report "CODERCONVP: KO - Convolutional coder output data doesn't match" severity warning;
end if;
end if;
end loop;
bench_ena_coder_conv0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
-- final state tests:
if (bench_res_coder_conv0_dat_val = '1') then
report "CODERCONVP: KO - Final state - Convolutional coder output data is valid" severity warning;
else
report "CODERCONVP: OK - Final state - Convolutional coder output data is not valid" severity note;
end if;
report "CODERCONVP: END CONVOLUTIONAL CODER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of coderdiffp
-- generation of coder differential subsystem unit-tests
--=============================================================================
-- read: bench_res_coder_diff0_dat, bench_res_coder_diff0_dat_val
-- write: bench_ena_coder_diff0_random_data, bench_sti_coder_diff0_dat_val
-- r/w:
CODERDIFFP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_coder_diff0_dat_val = '1') then
report "CODERDIFFP: KO - Default state - Differential coder output data is valid" severity warning;
else
report "CODERDIFFP: OK - Default state - Differential coder output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CODER_DIFF_WAIT_DURATION);
-- initial state tests:
if (bench_res_coder_diff0_dat_val = '1') then
report "CODERDIFFP: KO - Initial state - Differential coder output data is valid" severity warning;
else
report "CODERDIFFP: OK - Initial state - Differential coder output data is not valid" severity note;
end if;
-- behaviour tests:
report "CODERDIFFP: START DIFFERENTIAL CODER TESTS" severity note;
bench_ena_coder_diff0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
bench_sti_coder_diff0_dat_val <= '1';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD*CCSDS_RXTX_BENCH_CODER_DIFF0_WORDS_NUMBER;
bench_sti_coder_diff0_dat_val <= '0';
bench_ena_coder_diff0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
-- final state tests:
if (bench_res_coder_diff0_dat_val = '1') then
report "CODERDIFFP: KO - Final state - Differential coder output data is valid" severity warning;
else
report "CODERDIFFP: OK - Final state - Differential coder output data is not valid" severity note;
end if;
report "CODERDIFFP: END DIFFERENTIAL CODER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of crcp
-- generation of crc subsystem unit-tests
--=============================================================================
-- read: bench_res_crc0_data, bench_res_crc0_data_valid
-- write: bench_sti_crc0_nxt, bench_sti_crc0_data, bench_ena_crc0_random_data
-- r/w:
CRCP : process
variable crc_random_data_sent: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0) := (others => '0');
variable crc_random_data_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0) := (others => '1');
variable crc_random_data_crc_check: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0) := (others => '0');
variable crc_check_ok: std_logic := '1';
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_crc0_data_valid = '1') then
report "CRCP: KO - Default state - CRC output data is valid" severity warning;
else
report "CRCP: OK - Default state - CRC output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CRC_WAIT_DURATION);
-- initial state tests:
if (bench_res_crc0_data_valid = '1') then
report "CRCP: KO - Initial state - CRC output data is valid" severity warning;
else
report "CRCP: OK - Initial state - CRC output data is not valid" severity note;
end if;
-- behaviour tests:
report "CRCP: START CRC COMPUTATION TESTS" severity note;
-- present crc test data
bench_sti_crc0_data <= CCSDS_RXTX_BENCH_CRC0_DATA;
-- no specific padding done
bench_sti_crc0_padding_data_valid <= '0';
-- send next crc signal
bench_sti_crc0_nxt <= '1';
-- wait for one clk
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
-- stop next signal
bench_sti_crc0_nxt <= '0';
-- remove crc test data
bench_sti_crc0_data <= (others => '0');
if (bench_res_crc0_busy = '0') then
report "CRCP: KO - CRC is not busy" severity warning;
end if;
-- wait for result
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD*(CCSDS_RXTX_BENCH_CRC0_DATA'length+CCSDS_RXTX_BENCH_CRC0_LENGTH*8+1);
if (bench_res_crc0_crc = CCSDS_RXTX_BENCH_CRC0_RESULT) and (bench_res_crc0_data_valid = '1') and (bench_res_crc0_data = CCSDS_RXTX_BENCH_CRC0_DATA) then
report "CRCP: OK - Output CRC is conform to expectations" severity note;
else
report "CRCP: KO - Output CRC is different from expectations" severity warning;
report "Received value:" severity note;
for i in 0 to bench_res_crc0_data'length-1 loop
report std_logic'image(bench_res_crc0_data(i));
end loop;
report "Expected value:" severity note;
for i in 0 to CCSDS_RXTX_BENCH_CRC0_RESULT'length-1 loop
report std_logic'image(CCSDS_RXTX_BENCH_CRC0_RESULT(i));
end loop;
end if;
bench_ena_crc0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
for crc_current_check in 0 to CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER-1 loop
-- present crc random data + store associated crc
-- send next crc signal
bench_sti_crc0_random_nxt <= '1';
-- no specific padding done
bench_sti_crc0_random_padding_data_valid <= '0';
-- wait for one clk and store random data sent
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
crc_random_data_sent := bench_sti_crc0_random_data;
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
-- stop next signal
bench_ena_crc0_random_data <= '0';
bench_sti_crc0_random_nxt <= '0';
if (bench_res_crc0_random_busy = '0') then
report "CRCP: KO - random data CRC is not busy" severity warning;
end if;
-- wait for result
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD*(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8+CCSDS_RXTX_BENCH_CRC0_LENGTH*8+1);
if (bench_res_crc0_random_data_valid = '1') then
-- store crc
crc_random_data_crc := bench_res_crc0_random_crc;
else
report "CRCP: KO - random data output CRC is not valid" severity warning;
end if;
-- present crc random data
bench_sti_crc0_check_data <= crc_random_data_sent;
-- present crc as padding value
bench_sti_crc0_check_padding_data <= crc_random_data_crc;
bench_sti_crc0_check_padding_data_valid <= '1';
-- send next crc signal
bench_sti_crc0_check_nxt <= '1';
-- wait for one clk
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
-- stop next signal
bench_sti_crc0_check_nxt <= '0';
-- stop padding signal
bench_sti_crc0_check_padding_data_valid <= '0';
if (bench_res_crc0_check_busy = '0') then
report "CRCP: KO - Random data checker CRC is not busy" severity warning;
end if;
-- wait for result
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD*(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8+CCSDS_RXTX_BENCH_CRC0_LENGTH*8+1);
if (bench_res_crc0_check_data_valid = '1') then
-- check output crc resulting is null
if (bench_res_crc0_check_crc = crc_random_data_crc_check) and (bench_res_crc0_check_data = crc_random_data_sent) then
if (crc_current_check = CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER-1) and (crc_check_ok = '1') then
report "CRCP: OK - Random data checker output CRCs are all null" severity note;
end if;
else
crc_check_ok := '0';
report "CRCP: KO - Random data checker output CRC is not null - loop " & integer'image(crc_current_check) severity warning;
report "Received value:" severity warning;
for i in 0 to bench_res_crc0_check_data'length-1 loop
report std_logic'image(bench_res_crc0_check_data(i)) severity warning;
end loop;
end if;
else
report "CRCP: KO - Output CRC checker is not valid" severity warning;
end if;
bench_ena_crc0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
end loop;
bench_ena_crc0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
-- final state tests:
if (bench_res_crc0_data_valid = '1') then
report "CRCP: KO - Final state - CRC output data is valid" severity warning;
else
report "CRCP: OK - Final state - CRC output data is not valid" severity note;
end if;
report "CRCP: END CRC COMPUTATION TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of filterp
-- generation of filter subsystem unit-tests
--=============================================================================
-- read:
-- write:
-- r/w:
FILTERP : process
variable samples_csv_output: line;
variable samples_hex_output: line;
variable samples_hex_i_output: line;
variable samples_hex_q_output: line;
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_filter0_sam_val = '0') then
report "FILTERP: OK - Default state - Output samples are not valid" severity note;
else
report "FILTERP: KO - Default state - Output samples are valid" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_FILTER_WAIT_DURATION);
-- initial state tests:
-- default state tests:
if (bench_res_filter0_sam_val = '0') then
report "FILTERP: OK - Initial state - Output samples are not valid" severity note;
else
report "FILTERP: KO - Initial state - Output samples are valid" severity warning;
end if;
-- behaviour tests:
report "FILTERP: START FILTER TESTS" severity note;
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
write(samples_csv_output, string'("I samples;Q samples - quantized on " & integer'image(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH) & " bits / Big-Endian (MSB first) ASCII hexa coded"));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE, samples_csv_output);
end if;
bench_ena_filter0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD;
bench_sti_filter0_mapper_dat_val <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL*CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD*CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL/CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE;
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 200 loop
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD;
if (bench_res_filter0_sam_val = '1') then
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i) & ";");
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE, samples_csv_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_IQ_FILE, samples_hex_output);
write(samples_hex_i_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_q_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_I_FILE, samples_hex_i_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_Q_FILE, samples_hex_q_output);
else
report "FILTERP: KO - Output samples are not valid" severity warning;
end if;
end loop;
else
wait for 200*CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD;
end if;
if (bench_res_filter0_sam_val = '1') then
report "FILTERP: OK - Output samples are valid" severity note;
else
report "FILTERP: KO - Output samples are not valid" severity warning;
end if;
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to CCSDS_RXTX_BENCH_FILTER0_SYMBOL_WORDS_NUMBER-1 loop
for j in 0 to CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD/CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD-1 loop
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD;
if (bench_res_filter0_sam_val = '1') then
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i) & ";");
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE, samples_csv_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_IQ_FILE, samples_hex_output);
write(samples_hex_i_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_q_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_I_FILE, samples_hex_i_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_Q_FILE, samples_hex_q_output);
else
report "FILTERP: KO - Output samples are not valid" severity warning;
end if;
end loop;
end loop;
else
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD*CCSDS_RXTX_BENCH_FILTER0_SYMBOL_WORDS_NUMBER;
end if;
bench_sti_filter0_mapper_dat_val <= '0';
bench_ena_filter0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD*12;
-- final state tests:
if (bench_res_filter0_sam_val = '0') then
report "FILTERP: OK - Final state - Output samples are not valid" severity note;
else
report "FILTERP: KO - Final state - Output samples are valid" severity warning;
end if;
report "FILTERP: END FILTER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of framerp
-- generation of framer subsystem unit-tests
--=============================================================================
-- read: bench_res_framer0_data0, bench_res_framer0_data_valid0
-- write: bench_ena_framer0_random_data
-- r/w:
FRAMERP : process
type data_array is array (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0) of std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
type frame_array is array (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1 downto 0) of data_array;
variable framer_expected_data: frame_array := (others => (others => (others => '0')));
variable frame_content_ok: std_logic := '1';
variable nb_data: integer;
variable FRAME_OUTPUT_CYCLES_REQUIRED: integer;
variable FRAME_PROCESSING_CYCLES_REQUIRED: integer := (CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+1;
constant FRAME_ACQUISITION_CYCLES: integer := (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE + 1;
constant FRAME_REPETITION_CYCLES: integer := CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE;
constant FRAME_ACQUISITION_CYCLES_IDLE: integer := FRAME_REPETITION_CYCLES - FRAME_ACQUISITION_CYCLES;
begin
if (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8 = CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE) and (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO = 1) then
FRAME_OUTPUT_CYCLES_REQUIRED := (CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+6;
else
FRAME_OUTPUT_CYCLES_REQUIRED := (CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+5;
end if;
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION);
report "FRAMERP: START FRAMER TESTS" severity note;
-- initial state tests:
bench_ena_framer0_random_data <= '1';
-- check output data is valid and idle only data found
if ((CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION/CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD) < FRAME_OUTPUT_CYCLES_REQUIRED) then
wait for (FRAME_OUTPUT_CYCLES_REQUIRED+1 - ((CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION/CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD) mod FRAME_OUTPUT_CYCLES_REQUIRED))*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
else
wait for (FRAME_REPETITION_CYCLES+1 - (((CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION/CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD) - FRAME_OUTPUT_CYCLES_REQUIRED) mod (FRAME_REPETITION_CYCLES)))*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
if bench_res_framer0_data_valid = '1' then
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+10 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) = "11111111110") then
report "FRAMERP: OK - Initial state - Output frame is valid and Only Idle Data flag found" severity note;
else
report "FRAMERP: KO - Initial state - Output frame is valid without sent data - Only Idle Flag not found" severity warning;
end if;
else
report "FRAMERP: KO - Initial state - Output frame is not valid without sent data" severity warning;
end if;
if (bench_res_framer0_dat_nxt = '0') then
report "FRAMERP: KO - Initial state - Next data not requested" severity warning;
else
report "FRAMERP: OK - Initial state - Next data requested" severity note;
end if;
-- behaviour tests:
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE);
-- send data for 1 frame
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
framer_expected_data(0)(i) := bench_sti_framer0_data;
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
if (i /= (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1) then
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end if;
end loop;
bench_sti_framer0_data_valid <= '0';
bench_ena_framer0_random_data <= '0';
-- wait for footer to be processed
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_PROCESSING_CYCLES_REQUIRED+4);
if bench_res_framer0_data_valid = '0' then
report "FRAMERP: KO - Output frame is not ready in time" severity warning;
else
report "FRAMERP: OK - Output frame is ready in time" severity note;
-- check frame content is coherent with sent data
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*i-1 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*(i+1)) /= framer_expected_data(0)(i)) then
report "FRAMERP: KO - Output frame content is not equal to sent data - loop: " & integer'image(i) severity warning;
frame_content_ok := '0';
else
if (i = (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1) and (frame_content_ok = '1') then
report "FRAMERP: OK - Output frame is equal to sent data" severity note;
end if;
end if;
end loop;
end if;
-- send data every CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO clk during CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER*frame_processing time, store sent data for first frame and check output frame content
bench_ena_framer0_random_data <= '1';
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE);
frame_content_ok := '1';
for f in 0 to (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1) loop
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
framer_expected_data(f)(i) := bench_sti_framer0_data;
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end loop;
-- waiting for footer to be processed
for data_packet in 0 to ((FRAME_PROCESSING_CYCLES_REQUIRED-1)/CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO)-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if (data_packet /= ((FRAME_PROCESSING_CYCLES_REQUIRED-1)/CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)) then
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end if;
end loop;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
end if;
wait for 5*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if bench_res_framer0_data_valid = '0' then
report "FRAMERP: KO - Output frame is not ready in time - frame loop: " & integer'image(f) severity warning;
else
-- check frame content is coherent with sent data
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*i-1 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*(i+1)) /= framer_expected_data(f)(i)) then
report "FRAMERP: KO - Output frame content is not equal to sent data - frame loop: " & integer'image(f) & " - data loop: " & integer'image(i) severity warning;
frame_content_ok := '0';
else
if (i = (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1) and (f = (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1)) and (frame_content_ok = '1') then
report "FRAMERP: OK - Received output frames are all equal to sent data" severity note;
end if;
end if;
end loop;
end if;
if (f /= (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1)) then
-- fill current frame to start with new one
if ((((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) mod FRAME_REPETITION_CYCLES) /= 0) then
nb_data := (FRAME_REPETITION_CYCLES - (((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) mod FRAME_REPETITION_CYCLES))/CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO;
for i in 0 to nb_data-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end loop;
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(2*FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE - nb_data*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO);
else
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE);
end if;
end if;
end loop;
bench_sti_framer0_data_valid <= '0';
-- wait for last frame to be processed and presented
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES*(((FRAME_PROCESSING_CYCLES_REQUIRED+1)/FRAME_REPETITION_CYCLES)+4));
-- send data continuously to test full-speed / overflow behaviour
bench_sti_framer0_data_valid <= '1';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO*CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
if (bench_res_framer0_dat_nxt = '0') then
report "FRAMERP: OK - Overflow stop next data request" severity note;
else
report "FRAMERP: KO - Overflow doesn't stop next data request" severity warning;
end if;
else
if (bench_res_framer0_dat_nxt = '1') then
report "FRAMERP: OK - Full speed doesn't stop next data request" severity note;
else
report "FRAMERP: KO - Full speed stop next data request" severity warning;
end if;
end if;
bench_sti_framer0_data_valid <= '0';
bench_ena_framer0_random_data <= '0';
-- final state tests:
if bench_res_framer0_data_valid = '1' then
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+10 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) = "11111111110") then
report "FRAMERP: OK - Final state - Output frame is valid and Only Idle Data flag found" severity note;
else
report "FRAMERP: KO - Final state - Output frame is valid without sent data - Only Idle Flag not found" severity warning;
end if;
else
report "FRAMERP: KO - Final state - Output frame is not valid without sent data" severity warning;
end if;
if (bench_res_framer0_dat_nxt = '0') then
report "FRAMERP: KO - Final state - Next data not requested" severity warning;
else
report "FRAMERP: OK - Final state - Next data requested" severity note;
end if;
report "FRAMERP: END FRAMER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of lfsrp
-- generation of lfsr subsystem unit-tests
--=============================================================================
-- read: bench_res_lfsr0_data, bench_res_lfsr0_data_valid
-- write:
-- r/w:
LFSRP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_LFSR_WAIT_DURATION);
-- initial state tests:
-- behaviour tests:
report "LFSRP: START LFSR TESTS" severity note;
wait for (CCSDS_RXTX_BENCH_LFSR0_RESULT'length)*CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD;
if (bench_res_lfsr0_data_valid = '1') then
report "LFSRP: OK - LFSR output is valid" severity note;
if (bench_res_lfsr0_data = CCSDS_RXTX_BENCH_LFSR0_RESULT) then
report "LFSRP: OK - LFSR output is equal to expected output" severity note;
else
report "LFSRP: KO - LFSR output is different from expected output" severity warning;
end if;
else
report "LFSRP: KO - LFSR output is not valid" severity warning;
end if;
-- final state tests:
report "LFSRP: END LFSR TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of mapperbitssymbolsp
-- generation of mapper subsystem unit-tests
--=============================================================================
-- read:
-- write: bench_sti_mapper_bits_symbols0_dat_val, bench_sti_mapper_bits_symbols0_dat_val
-- r/w:
MAPPERBITSSYMBOLSP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_mapper_bits_symbols0_sym_val = '1') then
report "MAPPERBITSSYMBOLSP: KO - Default state - Mapper output data is valid" severity warning;
else
report "MAPPERBITSSYMBOLSP: OK - Default state - Mapper output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_MAPPER_BITS_SYMBOLS_WAIT_DURATION);
-- initial state tests:
if (bench_res_mapper_bits_symbols0_sym_val = '1') then
report "MAPPERBITSSYMBOLSP: KO - Initial state - Mapper output data is valid" severity warning;
else
report "MAPPERBITSSYMBOLSP: OK - Initial state - Mapper output data is not valid" severity note;
end if;
-- behaviour tests:
report "MAPPERBITSSYMBOLSP: START BITS TO SYMBOLS MAPPER TESTS" severity note;
bench_ena_mapper_bits_symbols0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD;
bench_sti_mapper_bits_symbols0_dat_val <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD*CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE/CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL*CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_WORDS_NUMBER;
bench_sti_mapper_bits_symbols0_dat_val <= '0';
bench_ena_mapper_bits_symbols0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD;
-- final state tests:
if (bench_res_mapper_bits_symbols0_sym_val = '1') then
report "MAPPERBITSSYMBOLSP: KO - Final state - Mapper output data is valid" severity warning;
else
report "MAPPERBITSSYMBOLSP: OK - Final state - Mapper output data is not valid" severity note;
end if;
report "MAPPERBITSSYMBOLSP: END BITS TO SYMBOLS MAPPER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of mappersymbolssamplesp
-- generation of mapper subsystem unit-tests
--=============================================================================
-- read:
-- write: bench_sti_mapper_bits_symbols0_dat_val, bench_sti_mapper_bits_symbols0_dat_val
-- r/w:
MAPPERSYMBOLSSAMPLESP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_mapper_symbols_samples0_sam_val = '1') then
report "MAPPERSYMBOLSSAMPLESP: KO - Default state - Mapper output data is valid" severity warning;
else
report "MAPPERSYMBOLSSAMPLESP: OK - Default state - Mapper output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_MAPPER_SYMBOLS_SAMPLES_WAIT_DURATION);
-- initial state tests:
if (bench_res_mapper_symbols_samples0_sam_val = '1') then
report "MAPPERSYMBOLSSAMPLESP: KO - Initial state - Mapper output data is valid" severity warning;
else
report "MAPPERSYMBOLSSAMPLESP: OK - Initial state - Mapper output data is not valid" severity note;
end if;
-- behaviour tests:
report "MAPPERSYMBOLSSAMPLESP: START SYMBOLS TO SAMPLES MAPPER TESTS" severity note;
bench_ena_mapper_symbols_samples0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD;
bench_sti_mapper_symbols_samples0_sym_val <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD*CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_WORDS_NUMBER;
bench_sti_mapper_symbols_samples0_sym_val <= '0';
bench_ena_mapper_symbols_samples0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD;
-- final state tests:
if (bench_res_mapper_symbols_samples0_sam_val = '1') then
report "MAPPERSYMBOLSSAMPLESP: KO - Final state - Mapper output data is valid" severity warning;
else
report "MAPPERSYMBOLSSAMPLESP: OK - Final state - Mapper output data is not valid" severity note;
end if;
report "MAPPERSYMBOLSSAMPLESP: END SYMBOLS TO SAMPLES MAPPER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of serdesp
-- generation of serdes subsystem unit-tests
--=============================================================================
-- read: bench_res_serdes0_data_par_valid, bench_res_serdes0_data_par, bench_res_serdes0_data_ser, bench_res_serdes0_data_ser_valid, bench_res_serdes0_busy
-- write: bench_sti_serdes0_data_par_valid, bench_sti_serdes0_data_ser_valid, bench_ena_serdes0_random_data
-- r/w:
SERDESP : process
variable serdes_expected_output: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0) := (others => '0');
variable serdes_ok: std_logic := '1';
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- check serdes is not valid
if (bench_res_serdes0_data_par_valid = '0') then
report "SERDESP: OK - Default state - Serdes parallel output is not valid" severity note;
else
report "SERDESP: KO - Default state - Serdes parallel output is valid" severity warning;
end if;
if (bench_res_serdes0_data_ser_valid = '0') then
report "SERDESP: OK - Default state - Serdes serial output is not valid" severity note;
else
report "SERDESP: KO - Default state - Serdes serial output is valid" severity warning;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: OK - Default state - Serdes is not busy" severity note;
else
report "SERDESP: KO - Default state - Serdes is busy" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_SERDES_WAIT_DURATION);
-- initial state tests:
-- check serdes is not valid
if (bench_res_serdes0_data_par_valid = '0') then
report "SERDESP: OK - Initial state - Serdes parallel output is not valid" severity note;
else
report "SERDESP: KO - Initial state - Serdes parallel output is valid" severity warning;
end if;
if (bench_res_serdes0_data_ser_valid = '0') then
report "SERDESP: OK - Initial state - Serdes serial output is not valid" severity note;
else
report "SERDESP: KO - Initial state - Serdes serial output is valid" severity warning;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: OK - Initial state - Serdes is not busy" severity note;
else
report "SERDESP: KO - Initial state - Serdes is busy" severity warning;
end if;
-- behaviour tests:
report "SERDESP: START SERDES TESTS" severity note;
bench_ena_serdes0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
-- test par2ser
-- signal valid parallel data input
bench_sti_serdes0_data_par_valid <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output := bench_sti_serdes0_data_par;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
bench_sti_serdes0_data_par_valid <= '0';
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
if (bench_res_serdes0_busy = '0') then
report "SERDESP: KO - Serdes is not busy" severity warning;
else
if (bench_res_serdes0_data_ser_valid = '1') then
if (bench_res_serdes0_data_ser /= serdes_expected_output(bit_pointer)) then
serdes_ok := '0';
report "SERDESP: KO - Serdes serialized output data doesn't match expected output - cycle " & integer'image(bit_pointer) severity warning;
report "Expected value: " & std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
report "Received value: " & std_logic'image(bench_res_serdes0_data_ser) severity warning;
else
if (serdes_ok = '1') and (bit_pointer = 0) then
report "SERDESP: OK - Serdes serialized output data match expected output" severity note;
end if;
end if;
else
report "SERDESP: KO - Serdes serialized output data is not valid" severity warning;
end if;
end if;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
end loop;
-- test ser2par
-- signal valid serial data input
serdes_expected_output := (others => '0');
bench_sti_serdes0_data_ser_valid <= '1';
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output(bit_pointer) := bench_sti_serdes0_data_ser;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
end loop;
bench_sti_serdes0_data_ser_valid <= '0';
bench_ena_serdes0_random_data <= '0';
if (bench_res_serdes0_data_par_valid = '1') then
report "SERDESP: OK - Serdes parallelized output data is valid" severity note;
if (bench_res_serdes0_data_par = serdes_expected_output) then
report "SERDESP: OK - Serdes parallelized output data match expected output" severity note;
else
report "SERDESP: KO - Serdes parallelized output data doesn't match expected output" severity warning;
report "Expected value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
end loop;
report "Received value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(bench_res_serdes0_data_par(bit_pointer)) severity warning;
end loop;
end if;
else
report "SERDESP: KO - Serdes parallelized output data is not valid" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
--TODO: TEST SER2PAR + PAR2SER SIMULTANEOUSLY
-- many par2ser cycles
bench_ena_serdes0_random_data <= '1';
serdes_expected_output := (others => '0');
serdes_ok := '1';
for cycle_number in 0 to CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1 loop
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
if (bit_pointer = (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1)) then
-- signal valid parallel data input
bench_sti_serdes0_data_par_valid <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output := bench_sti_serdes0_data_par;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
bench_sti_serdes0_data_par_valid <= '0';
else
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: KO - Serdes is not busy" severity warning;
else
if (bench_res_serdes0_data_ser_valid = '1') then
if (bench_res_serdes0_data_ser /= serdes_expected_output(bit_pointer)) then
serdes_ok := '0';
report "SERDESP: KO - Serdes serialized output data doesn't match expected output - cycle " & integer'image(bit_pointer) severity warning;
report "Expected value: " & std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
report "Received value: " & std_logic'image(bench_res_serdes0_data_ser) severity warning;
else
if (serdes_ok = '1') and (bit_pointer = 0) and (cycle_number = (CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1)) then
report "SERDESP: OK - All serdes serialized output data match expected outputs" severity note;
end if;
end if;
else
report "SERDESP: KO - Serdes serialized output data is not valid" severity warning;
end if;
end if;
end loop;
end loop;
-- many par2ser cycles
serdes_expected_output := (others => '0');
serdes_ok := '1';
for cycle_number in 0 to CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1 loop
-- signal valid serial data input
bench_sti_serdes0_data_ser_valid <= '1';
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output(bit_pointer) := bench_sti_serdes0_data_ser;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
end loop;
if (bench_res_serdes0_data_par_valid = '1') then
if (bench_res_serdes0_data_par = serdes_expected_output) then
if (cycle_number = (CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1)) and (serdes_ok = '1') then
report "SERDESP: OK - All serdes parallelized output data match expected outputs" severity note;
end if;
else
serdes_ok := '0';
report "SERDESP: KO - Serdes parallelized output data doesn't match expected output" severity warning;
report "Expected value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
end loop;
report "Received value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(bench_res_serdes0_data_par(bit_pointer)) severity warning;
end loop;
end if;
else
report "SERDESP: KO - Serdes parallelized output data is not valid" severity warning;
end if;
end loop;
bench_sti_serdes0_data_ser_valid <= '0';
bench_ena_serdes0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
-- final state tests:
-- check serdes is not valid
if (bench_res_serdes0_data_par_valid = '0') then
report "SERDESP: OK - Final state - Serdes parallel output is not valid" severity note;
else
report "SERDESP: KO - Final state - Serdes parallel output is valid" severity warning;
end if;
if (bench_res_serdes0_data_ser_valid = '0') then
report "SERDESP: OK - Final state - Serdes serial output is not valid" severity note;
else
report "SERDESP: KO - Final state - Serdes serial output is valid" severity warning;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: OK - Final state - Serdes is not busy" severity note;
else
report "SERDESP: KO - Final state - Serdes is busy" severity warning;
end if;
report "SERDESP: END SERDES TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of srrcp
-- generation of SRRC subsystem unit-tests
--=============================================================================
-- read:
-- write:
-- r/w:
SRRCP : process
constant srrc_zero: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0) := (others => '0');
variable samples_hex_output: line;
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_srrc0_sam_val = '0') then
report "SRRCP: OK - Default state - SRRC samples are not valid" severity note;
else
report "SRRCP: KO - Default state - SRRC samples are valid" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_SRRC_WAIT_DURATION);
-- initial state tests:
if (bench_res_srrc0_sam_val = '0') then
report "SRRCP: OK - Initial state - SRRC samples are not valid" severity note;
else
report "SRRCP: KO - Initial state - SRRC samples are valid" severity warning;
end if;
if (bench_res_srrc0_sam = srrc_zero) then
report "SRRCP: OK - Initial state - SRRC samples are null" severity note;
else
report "SRRCP: KO - Initial state - SRRC samples are not null" severity warning;
end if;
-- behaviour tests:
report "SRRCP: START SRRC TESTS" severity note;
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1) <= '0';
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-2 downto 0) <= (others => '1');
bench_sti_srrc0_sam_val <= '1';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
bench_sti_srrc0_sam <= (others => '0');
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 400 loop
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
if (bench_res_srrc0_sam_val = '1') then
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_srrc0_sam));
writeline(CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE, samples_hex_output);
else
report "SRRCP: KO - SRRC samples are not valid" severity warning;
end if;
end loop;
else
wait for 400*CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
end if;
bench_sti_srrc0_sam(0) <= '1';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
bench_sti_srrc0_sam <= (others => '0');
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 400 loop
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
if (bench_res_srrc0_sam_val = '1') then
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_srrc0_sam));
writeline(CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE, samples_hex_output);
else
report "SRRCP: KO - SRRC samples are not valid" severity warning;
end if;
end loop;
else
wait for 400*CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
end if;
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1) <= '1';
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-2 downto 0) <= (others => '0');
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
bench_sti_srrc0_sam <= (others => '0');
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 400 loop
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
if (bench_res_srrc0_sam_val = '1') then
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_srrc0_sam));
writeline(CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE, samples_hex_output);
else
report "SRRCP: KO - SRRC samples are not valid" severity warning;
end if;
end loop;
else
wait for 400*CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
end if;
bench_sti_srrc0_sam_val <= '0';
-- final state tests:
if (bench_res_srrc0_sam_val = '0') then
report "SRRCP: OK - Final state - SRRC samples are not valid" severity note;
else
report "SRRCP: KO - Final state - SRRC samples are valid" severity warning;
end if;
if (bench_res_srrc0_sam = srrc_zero) then
report "SRRCP: OK - Final state - SRRC samples are null" severity note;
else
report "SRRCP: KO - Final state - SRRC samples are not null" severity warning;
end if;
report "SRRCP: END SRRC TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of resetp
-- generation of reset pulses
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_wb_rst, bench_sti_crc0_rst, bench_sti_buffer0_rst, bench_sti_framer0_rst
-- r/w:
RESETP : process
begin
-- let the system free run
wait for CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION;
report "RESETP: START RESET SIGNAL TEST" severity note;
-- send reset signals
bench_sti_rxtx0_wb_rst <= '1';
bench_sti_coder_conv0_rst <= '1';
bench_sti_coder_diff0_rst <= '1';
bench_sti_crc0_rst <= '1';
bench_sti_buffer0_rst <= '1';
bench_sti_filter0_rst <= '1';
bench_sti_framer0_rst <= '1';
bench_sti_lfsr0_rst <= '1';
bench_sti_mapper_bits_symbols0_rst <= '1';
bench_sti_srrc0_rst <= '1';
-- wait for some time
wait for CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION;
report "RESETP: END RESET SIGNAL TEST" severity note;
-- stop reset signals
bench_sti_rxtx0_wb_rst <= '0';
bench_sti_coder_conv0_rst <= '0';
bench_sti_coder_diff0_rst <= '0';
bench_sti_crc0_rst <= '0';
bench_sti_buffer0_rst <= '0';
bench_sti_filter0_rst <= '0';
bench_sti_framer0_rst <= '0';
bench_sti_lfsr0_rst <= '0';
bench_sti_mapper_bits_symbols0_rst <= '0';
bench_sti_srrc0_rst <= '0';
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of wbrwp
-- generation of master wb read / write cycles / aligned with clk0
--=============================================================================
-- read: bench_res_rxtx0_wb_ack0, bench_res_rxtx0_wb_err0, bench_res_rxtx0_wb_rty0, bench_sti_rxtx0_wb_random_dat0
-- write: bench_sti_rxtx0_wb_adr0, bench_sti_rxtx0_wb_cyc0, bench_sti_rxtx0_wb_stb0, bench_sti_rxtx0_wb_we0, bench_sti_rxtx0_wb_dat0, bench_ena_rxtx0_random_data
-- r/w:
WBRWP : process
variable output_done: boolean := false;
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_rxtx0_wb_ack = '0') then
report "WBRWP: OK - Default state - ACK not enabled" severity note;
else
report "WBRWP: OK - Default state - ACK enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_err = '0') then
report "WBRWP: OK - Default state - ERR not enabled" severity note;
else
report "WBRWP: OK - Default state - ERR enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Default state - RTY not enabled" severity note;
else
report "WBRWP: OK - Default state - RTY enabled" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_WB_WAIT_DURATION);
-- initial state tests:
if (bench_res_rxtx0_wb_ack = '0') then
report "WBRWP: OK - Initial state - ACK not enabled" severity note;
else
report "WBRWP: OK - Initial state - ACK enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_err = '0') then
report "WBRWP: OK - Initial state - ERR not enabled" severity note;
else
report "WBRWP: OK - Initial state - ERR enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Initial state - RTY not enabled" severity note;
else
report "WBRWP: OK - Initial state - RTY enabled" severity warning;
end if;
-- behaviour tests:
report "WBRWP: START WISHBONE BUS READ-WRITE TESTS" severity note;
bench_ena_rxtx0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
-- start a basic rx read cycle
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RX read cycle success" severity note;
else
report "WBRWP: KO - RX read cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start an error read cycle
bench_sti_rxtx0_wb_adr <= "0001";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '0') and (bench_res_rxtx0_wb_err = '1') and (bench_res_rxtx0_wb_rty = '1') then
report "WBRWP: OK - Error read cycle success" severity note;
else
report "WBRWP: KO - Error read cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> disable rx
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0001";
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RXTX configuration write cycle success (RX disabled)" severity note;
else
report "WBRWP: KO - RXTX configuration write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> disable tx
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0010";
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RXTX configuration write cycle success (TX disabled)" severity note;
else
report "WBRWP: KO - RXTX configuration write cycle fail" severity warning;
end if;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> enable tx + enable internal wb data use for tx
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0010";
bench_sti_rxtx0_wb_dat <= "00000000000000000000000000000001";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RXTX configuration write cycle success (TX enabled + internal WB data use)" severity note;
else
report "WBRWP: KO - RXTX configuration write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic tx write cycle
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_dat <= bench_sti_rxtx0_wb_random_dat;
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - TX write cycle success" severity note;
else
report "WBRWP: KO - TX write cycle fail" severity warning;
end if;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start an error basic tx write cycle (unknown address)
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0011";
bench_sti_rxtx0_wb_dat <= bench_sti_rxtx0_wb_random_dat;
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '0') and (bench_res_rxtx0_wb_err = '1') and (bench_res_rxtx0_wb_rty = '1') then
report "WBRWP: OK - Error write cycle success" severity note;
else
report "WBRWP: KO - Error write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start many tx write cycle
for i in 0 to CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER-1 loop
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_dat <= bench_sti_rxtx0_wb_random_dat;
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
if (bench_res_rxtx0_wb_ack = '0') or (bench_res_rxtx0_wb_err = '1') or (bench_res_rxtx0_wb_rty = '1') then
if (CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW = true) then
if (output_done = false) then
output_done := true;
report "WBRWP: OK - Many TX write cycles overflow appears after " & integer'image(i) & " WB write cycles (" & integer'image(i*CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE) & " bits max burst)" severity note;
end if;
else
report "WBRWP: KO - TX write cycle fail: ACK=" & std_logic'image(bench_res_rxtx0_wb_ack) & " ERR=" & std_logic'image(bench_res_rxtx0_wb_err) & " RTY=" & std_logic'image(bench_res_rxtx0_wb_rty) severity warning;
end if;
else
if (i = CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER-1) then
report "WBRWP: OK - Many TX write cycles terminated with success" severity note;
end if;
end if;
if (CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW = true) then
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
else
wait for (CCSDS_RXTX_BENCH_RXTX0_WB_WRITE_CYCLES_MAX-1)*CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*2 + CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
end if;
end loop;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> enable tx + external serial data activation
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0010";
bench_sti_rxtx0_wb_dat <= "00000000000000000000000000000011";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Basic configuration write cycle success (TX enabled + external serial data input activated)" severity note;
else
report "WBRWP: KO - Basic configuration write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
-- final state tests:
if (bench_res_rxtx0_wb_ack = '0') then
report "WBRWP: OK - Final state - ACK not enabled" severity note;
else
report "WBRWP: OK - Final state - ACK enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_err = '0') then
report "WBRWP: OK - Final state - ERR not enabled" severity note;
else
report "WBRWP: OK - Final state - ERR enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Final state - RTY not enabled" severity note;
else
report "WBRWP: OK - Final state - RTY enabled" severity warning;
end if;
report "WBRWP: END WISHBONE BUS READ-WRITE TESTS" severity note;
-- bench_ena_rxtx0_random_data <= '0';
wait;
end process;
end behaviour;
--=============================================================================
-- architecture end
--=============================================================================
|
mit
|
7435ec9ddd50540f4ed2d153327f82ad
| 0.608838 | 3.528124 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rx_physical_layer.vhd
| 1 | 2,450 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rx_physical_layer
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_rx_physical_layer / unitary rx physical layer
--=============================================================================
entity ccsds_rx_physical_layer is
generic (
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE: integer := 32;
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH : integer := 16
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sam_i_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
sam_q_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
-- outputs
clk_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto 0)
);
end ccsds_rx_physical_layer;
--=============================================================================
-- architecture declaration / internal processing
--=============================================================================
architecture rtl of ccsds_rx_physical_layer is
--=============================================================================
-- architecture begin
--=============================================================================
begin
dat_o(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH) <= sam_q_i;
dat_o(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0) <= sam_i_i;
clk_o <= clk_i;
--=============================================================================
-- Begin of physicalp
-- TEST PURPOSES / DUMMY PHYSICAL LAYER PROCESS
--=============================================================================
-- read: clk_i
-- write:
-- r/w:
PHYSICALP : process (clk_i)
begin
end process;
end rtl;
--=============================================================================
-- architecture end
--=============================================================================
|
mit
|
9c8090ba4faa32313d72bb8a43d734cb
| 0.402857 | 5.020492 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
pc_controller.vhd
| 1 | 2,228 |
-- program counter decoder circuit
-- takes a 3-bit pc opcode and produces the necessary signals for the required function
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
-- opcode 000 is increment pc by 4
-- opcode 001 is set pc
-- opcode 010 is offset pc
-- opcode 100 is push to stack and set pc
-- opcode 101 is push to stack and offset pc
-- opcode 110 is pop from stack
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity pc_controller is
port (
-- opcode input
opcode : in std_logic_vector(2 downto 0);
-- stack push/pop signal
stack_push : out std_logic;
-- pc update value select
pc_value_select : out std_logic_vector(1 downto 0);
-- increment select
inc_select : out std_logic;
-- stack clock enable
stack_clk_enable : out std_logic
);
end entity pc_controller;
architecture pc_controller_arch of pc_controller is
-- this circuit requires no internal signals
begin
pc_control : process(opcode)
begin
-- opcode 000 is increment pc by 4
if opcode = "000" then
stack_push <= '0';
pc_value_select <= "00";
inc_select <= '0';
stack_clk_enable <= '0';
-- opcode 001 is set pc to value
elsif opcode = "001" then
stack_push <= '0';
pc_value_select <= "01";
inc_select <= '0';
stack_clk_enable <= '0';
-- opcode 010 is increment pc by value
elsif opcode = "010" then
stack_push <= '0';
pc_value_select <= "00";
inc_select <= '1';
stack_clk_enable <= '0';
-- opcode 100 is push to stack and set pc
elsif opcode = "100" then
stack_push <= '1';
pc_value_select <= "01";
inc_select <= '0';
stack_clk_enable <= '1';
-- opcode 101 is push to stack and increment pc by value
elsif opcode = "101" then
stack_push <= '1';
pc_value_select <= "00";
inc_select <= '1';
stack_clk_enable <= '1';
-- opcode 110 is pop from stack
elsif opcode = "110" then
stack_push <= '0';
pc_value_select <= "10";
inc_select <= '0';
stack_clk_enable <= '1';
-- otherwise invalid opcode, all outputs 0
else
stack_push <= '0';
pc_value_select <= "00";
inc_select <= '0';
stack_clk_enable <= '0';
end if;
end process pc_control;
end architecture pc_controller_arch;
|
mit
|
5357134cf3668d8080bef028e6a1b880
| 0.639587 | 3.073103 | false | false | false | false |
daveshah1/openMixR
|
fpga/vivado/openmixr_base/openmixr_base.srcs/sources_1/ip/init_config_rom/synth/init_config_rom.vhd
| 1 | 14,187 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_4;
USE blk_mem_gen_v8_3_4.blk_mem_gen_v8_3_4;
ENTITY init_config_rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END init_config_rom;
ARCHITECTURE init_config_rom_arch OF init_config_rom IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF init_config_rom_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_4 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF init_config_rom_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_4,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF init_config_rom_arch : ARCHITECTURE IS "init_config_rom,blk_mem_gen_v8_3_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF init_config_rom_arch: ARCHITECTURE IS "init_config_rom,blk_mem_gen_v8_3_4,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe" &
"_file_loaded,C_INIT_FILE=init_config_rom.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_" &
"B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_" &
"CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.622 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_4
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "init_config_rom.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.622 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END init_config_rom_arch;
|
mit
|
0fa0b44a23b8038be2b6eb7c29e08548
| 0.624727 | 3.008908 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_tx_coder.vhd
| 1 | 5,720 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_coder
---- Version: 1.0.0
---- Description:
---- Implementation of standard CCSDS 131.0-B-2
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx coder inputs and outputs
--=============================================================================
entity ccsds_tx_coder is
generic(
constant CCSDS_TX_CODER_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword (should be equal to bits per symbol of lower link)
constant CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean -- Enable differential coder
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_coder;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_coder is
component ccsds_tx_coder_differential is
generic(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_randomizer is
generic(
CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_synchronizer is
generic(
CCSDS_TX_ASM_LENGTH: integer;
CCSDS_TX_ASM_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal wire_coder_diff_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
signal wire_coder_diff_dat_val_o: std_logic;
signal wire_randomizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
signal wire_randomizer_dat_val_o: std_logic;
signal wire_synchronizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
signal wire_synchronizer_dat_val_o: std_logic;
-- components instanciation and mapping
begin
tx_coder_randomizer_0: ccsds_tx_randomizer
generic map(
CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => dat_val_i,
dat_i => dat_i,
dat_val_o => wire_randomizer_dat_val_o,
dat_o => wire_randomizer_dat_o
);
NODIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = false) generate
tx_coder_synchronizer_0: ccsds_tx_synchronizer
generic map(
CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
);
end generate NODIFFCODERGENP;
DIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = true) generate
tx_coder_synchronizer_0: ccsds_tx_synchronizer
generic map(
CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => wire_synchronizer_dat_val_o,
dat_o => wire_synchronizer_dat_o
);
tx_coder_differential_0: ccsds_tx_coder_differential
generic map(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_synchronizer_dat_val_o,
dat_i => wire_synchronizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
);
end generate DIFFCODERGENP;
-- presynthesis checks
-- internal processing
end structure;
|
mit
|
cd4b7281f39f489b2d40368ef451eea3
| 0.595979 | 3.421053 | false | false | false | false |
jpendlum/crash
|
fpga/src/toplevel/zc706.vhd
| 2 | 63,331 |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: zc706.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Toplevel file for ZC706.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity zc706 is
port (
-- ARM Connections
MIO : inout std_logic_vector(53 downto 0);
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB_pin : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRP : inout std_logic;
DDR_VRN : inout std_logic;
-- USRP DDR Interface
RX_DATA_CLK_N : in std_logic;
RX_DATA_CLK_P : in std_logic;
RX_DATA_N : in std_logic_vector(4 downto 0);
RX_DATA_P : in std_logic_vector(4 downto 0);
RX_DATA_STB_N : in std_logic;
RX_DATA_STB_P : in std_logic;
TX_DATA_N : out std_logic_vector(5 downto 0);
TX_DATA_P : out std_logic_vector(5 downto 0);
TX_DATA_STB_N : out std_logic;
TX_DATA_STB_P : out std_logic;
SPARE : out std_logic_vector(4 downto 0);
UART_TX : out std_logic);
end entity;
architecture RTL of zc706 is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component zc706_ps is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0);
axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic;
processing_system7_0_IRQ_F2P_pin : in std_logic_vector(15 downto 0);
processing_system7_0_FCLK_CLK0_pin : out std_logic;
processing_system7_0_FCLK_RESET0_N_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_AWADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_AWLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_AWSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_AWCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_AWPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_WDATA_pin : in std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_WSTRB_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_WLAST_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_BVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_ARLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_ARSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_ARCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_ARPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RDATA_pin : out std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_RRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_RLAST_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWUSER_pin : in std_logic_vector(4 downto 0);
axi_ext_master_conn_0_S_AXI_ARUSER_pin : in std_logic_vector(4 downto 0));
end component;
component ps_pl_interface is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
-- AXIS Stream Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- AXI-Lite Slave bus for access to control & status registers
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI ACP Bus to interface with processor system
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Interrupt on successfully completed AXI ACP writes
irq : out std_logic;
-- Global reset for all accelerators
rst_glb_n : out std_logic;
-- Accelerator interfaces
-- Note: Master & Slave 0 are not listed as the Datamover componeent
-- uses both.
-- Accelerator 1
-- Accelerator 1
axis_master_1_tvalid : in std_logic;
axis_master_1_tready : out std_logic;
axis_master_1_tdata : in std_logic_vector(63 downto 0);
axis_master_1_tdest : in std_logic_vector(2 downto 0);
axis_master_1_tlast : in std_logic;
axis_master_1_irq : in std_logic;
axis_slave_1_tvalid : out std_logic;
axis_slave_1_tready : in std_logic;
axis_slave_1_tdata : out std_logic_vector(63 downto 0);
axis_slave_1_tid : out std_logic_vector(2 downto 0);
axis_slave_1_tlast : out std_logic;
axis_slave_1_irq : in std_logic;
status_1_addr : out std_logic_vector(7 downto 0);
status_1_data : in std_logic_vector(31 downto 0);
status_1_stb : out std_logic;
ctrl_1_addr : out std_logic_vector(7 downto 0);
ctrl_1_data : out std_logic_vector(31 downto 0);
ctrl_1_stb : out std_logic;
-- Accelerator 2
axis_master_2_tvalid : in std_logic;
axis_master_2_tready : out std_logic;
axis_master_2_tdata : in std_logic_vector(63 downto 0);
axis_master_2_tdest : in std_logic_vector(2 downto 0);
axis_master_2_tlast : in std_logic;
axis_master_2_irq : in std_logic;
axis_slave_2_tvalid : out std_logic;
axis_slave_2_tready : in std_logic;
axis_slave_2_tdata : out std_logic_vector(63 downto 0);
axis_slave_2_tid : out std_logic_vector(2 downto 0);
axis_slave_2_tlast : out std_logic;
axis_slave_2_irq : in std_logic;
status_2_addr : out std_logic_vector(7 downto 0);
status_2_data : in std_logic_vector(31 downto 0);
status_2_stb : out std_logic;
ctrl_2_addr : out std_logic_vector(7 downto 0);
ctrl_2_data : out std_logic_vector(31 downto 0);
ctrl_2_stb : out std_logic;
-- Accelerator 3
axis_master_3_tvalid : in std_logic;
axis_master_3_tready : out std_logic;
axis_master_3_tdata : in std_logic_vector(63 downto 0);
axis_master_3_tdest : in std_logic_vector(2 downto 0);
axis_master_3_tlast : in std_logic;
axis_master_3_irq : in std_logic;
axis_slave_3_tvalid : out std_logic;
axis_slave_3_tready : in std_logic;
axis_slave_3_tdata : out std_logic_vector(63 downto 0);
axis_slave_3_tid : out std_logic_vector(2 downto 0);
axis_slave_3_tlast : out std_logic;
axis_slave_3_irq : in std_logic;
status_3_addr : out std_logic_vector(7 downto 0);
status_3_data : in std_logic_vector(31 downto 0);
status_3_stb : out std_logic;
ctrl_3_addr : out std_logic_vector(7 downto 0);
ctrl_3_data : out std_logic_vector(31 downto 0);
ctrl_3_stb : out std_logic;
-- Accelerator 4
axis_master_4_tvalid : in std_logic;
axis_master_4_tready : out std_logic;
axis_master_4_tdata : in std_logic_vector(63 downto 0);
axis_master_4_tdest : in std_logic_vector(2 downto 0);
axis_master_4_tlast : in std_logic;
axis_master_4_irq : in std_logic;
axis_slave_4_tvalid : out std_logic;
axis_slave_4_tready : in std_logic;
axis_slave_4_tdata : out std_logic_vector(63 downto 0);
axis_slave_4_tid : out std_logic_vector(2 downto 0);
axis_slave_4_tlast : out std_logic;
axis_slave_4_irq : in std_logic;
status_4_addr : out std_logic_vector(7 downto 0);
status_4_data : in std_logic_vector(31 downto 0);
status_4_stb : out std_logic;
ctrl_4_addr : out std_logic_vector(7 downto 0);
ctrl_4_data : out std_logic_vector(31 downto 0);
ctrl_4_stb : out std_logic;
-- Accelerator 5
axis_master_5_tvalid : in std_logic;
axis_master_5_tready : out std_logic;
axis_master_5_tdata : in std_logic_vector(63 downto 0);
axis_master_5_tdest : in std_logic_vector(2 downto 0);
axis_master_5_tlast : in std_logic;
axis_master_5_irq : in std_logic;
axis_slave_5_tvalid : out std_logic;
axis_slave_5_tready : in std_logic;
axis_slave_5_tdata : out std_logic_vector(63 downto 0);
axis_slave_5_tid : out std_logic_vector(2 downto 0);
axis_slave_5_tlast : out std_logic;
axis_slave_5_irq : in std_logic;
status_5_addr : out std_logic_vector(7 downto 0);
status_5_data : in std_logic_vector(31 downto 0);
status_5_stb : out std_logic;
ctrl_5_addr : out std_logic_vector(7 downto 0);
ctrl_5_data : out std_logic_vector(31 downto 0);
ctrl_5_stb : out std_logic;
-- Accelerator 6
axis_master_6_tvalid : in std_logic;
axis_master_6_tready : out std_logic;
axis_master_6_tdata : in std_logic_vector(63 downto 0);
axis_master_6_tdest : in std_logic_vector(2 downto 0);
axis_master_6_tlast : in std_logic;
axis_master_6_irq : in std_logic;
axis_slave_6_tvalid : out std_logic;
axis_slave_6_tready : in std_logic;
axis_slave_6_tdata : out std_logic_vector(63 downto 0);
axis_slave_6_tid : out std_logic_vector(2 downto 0);
axis_slave_6_tlast : out std_logic;
axis_slave_6_irq : in std_logic;
status_6_addr : out std_logic_vector(7 downto 0);
status_6_data : in std_logic_vector(31 downto 0);
status_6_stb : out std_logic;
ctrl_6_addr : out std_logic_vector(7 downto 0);
ctrl_6_data : out std_logic_vector(31 downto 0);
ctrl_6_stb : out std_logic;
-- Accelerator 7
axis_master_7_tvalid : in std_logic;
axis_master_7_tready : out std_logic;
axis_master_7_tdata : in std_logic_vector(63 downto 0);
axis_master_7_tdest : in std_logic_vector(2 downto 0);
axis_master_7_tlast : in std_logic;
axis_master_7_irq : in std_logic;
axis_slave_7_tvalid : out std_logic;
axis_slave_7_tready : in std_logic;
axis_slave_7_tdata : out std_logic_vector(63 downto 0);
axis_slave_7_tid : out std_logic_vector(2 downto 0);
axis_slave_7_tlast : out std_logic;
axis_slave_7_irq : in std_logic;
status_7_addr : out std_logic_vector(7 downto 0);
status_7_data : in std_logic_vector(31 downto 0);
status_7_stb : out std_logic;
ctrl_7_addr : out std_logic_vector(7 downto 0);
ctrl_7_data : out std_logic_vector(31 downto 0);
ctrl_7_stb : out std_logic);
end component;
component usrp_ddr_intf_axis is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 115200); -- UART baud rate
port (
-- USRP Interface
UART_TX : out std_logic; -- UART
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(4 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(4 downto 0); -- Receive data (P)
RX_DATA_STB_N : in std_logic; -- Receive data strobe (N)
RX_DATA_STB_P : in std_logic; -- Receive data strobe (P)
TX_DATA_N : out std_logic_vector(5 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(5 downto 0); -- Transmit data (P)
TX_DATA_STB_N : out std_logic; -- Transmit data strobe (N)
TX_DATA_STB_P : out std_logic; -- Transmit data strobe (P)
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (DAC / TX Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (ADC / RX Data)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
rx_enable_aux : in std_logic;
tx_enable_aux : in std_logic);
end component;
component spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end component;
component bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal clk : std_logic;
signal rst_n : std_logic;
signal S_AXI_AWADDR : std_logic_vector(31 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(31 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
signal M_AXI_AWADDR : std_logic_vector(31 downto 0);
signal M_AXI_AWPROT : std_logic_vector(2 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_AWREADY : std_logic;
signal M_AXI_WDATA : std_logic_vector(63 downto 0);
signal M_AXI_WSTRB : std_logic_vector(7 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_WREADY : std_logic;
signal M_AXI_BRESP : std_logic_vector(1 downto 0);
signal M_AXI_BVALID : std_logic;
signal M_AXI_BREADY : std_logic;
signal M_AXI_AWLEN : std_logic_vector(7 downto 0);
signal M_AXI_AWSIZE : std_logic_vector(2 downto 0);
signal M_AXI_AWBURST : std_logic_vector(1 downto 0);
signal M_AXI_AWCACHE : std_logic_vector(3 downto 0);
signal M_AXI_AWUSER : std_logic_vector(4 downto 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_ARADDR : std_logic_vector(31 downto 0);
signal M_AXI_ARPROT : std_logic_vector(2 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_ARREADY : std_logic;
signal M_AXI_RDATA : std_logic_vector(63 downto 0);
signal M_AXI_RRESP : std_logic_vector(1 downto 0);
signal M_AXI_RVALID : std_logic;
signal M_AXI_RREADY : std_logic;
signal M_AXI_RLAST : std_logic;
signal M_AXI_ARCACHE : std_logic_vector(3 downto 0);
signal M_AXI_ARUSER : std_logic_vector(4 downto 0);
signal M_AXI_ARLEN : std_logic_vector(7 downto 0);
signal M_AXI_ARBURST : std_logic_vector(1 downto 0);
signal M_AXI_ARSIZE : std_logic_vector(2 downto 0);
signal processing_system7_0_IRQ_F2P_pin : std_logic_vector(15 downto 0);
signal irq : std_logic;
signal rst_glb_n : std_logic;
signal axis_master_1_tvalid : std_logic;
signal axis_master_1_tready : std_logic;
signal axis_master_1_tdata : std_logic_vector(63 downto 0);
signal axis_master_1_tdest : std_logic_vector(2 downto 0);
signal axis_master_1_tlast : std_logic;
signal axis_master_1_irq : std_logic;
signal axis_slave_1_tvalid : std_logic;
signal axis_slave_1_tready : std_logic;
signal axis_slave_1_tdata : std_logic_vector(63 downto 0);
signal axis_slave_1_tid : std_logic_vector(2 downto 0);
signal axis_slave_1_tlast : std_logic;
signal axis_slave_1_irq : std_logic;
signal status_1_addr : std_logic_vector(7 downto 0);
signal status_1_data : std_logic_vector(31 downto 0);
signal status_1_stb : std_logic;
signal ctrl_1_addr : std_logic_vector(7 downto 0);
signal ctrl_1_data : std_logic_vector(31 downto 0);
signal ctrl_1_stb : std_logic;
signal axis_master_2_tvalid : std_logic;
signal axis_master_2_tready : std_logic;
signal axis_master_2_tdata : std_logic_vector(63 downto 0);
signal axis_master_2_tdest : std_logic_vector(2 downto 0);
signal axis_master_2_tlast : std_logic;
signal axis_master_2_irq : std_logic;
signal axis_slave_2_tvalid : std_logic;
signal axis_slave_2_tready : std_logic;
signal axis_slave_2_tdata : std_logic_vector(63 downto 0);
signal axis_slave_2_tid : std_logic_vector(2 downto 0);
signal axis_slave_2_tlast : std_logic;
signal axis_slave_2_irq : std_logic;
signal status_2_addr : std_logic_vector(7 downto 0);
signal status_2_data : std_logic_vector(31 downto 0);
signal status_2_stb : std_logic;
signal ctrl_2_addr : std_logic_vector(7 downto 0);
signal ctrl_2_data : std_logic_vector(31 downto 0);
signal ctrl_2_stb : std_logic;
signal axis_master_3_tvalid : std_logic;
signal axis_master_3_tready : std_logic;
signal axis_master_3_tdata : std_logic_vector(63 downto 0);
signal axis_master_3_tdest : std_logic_vector(2 downto 0);
signal axis_master_3_tlast : std_logic;
signal axis_master_3_irq : std_logic;
signal axis_slave_3_tvalid : std_logic;
signal axis_slave_3_tready : std_logic;
signal axis_slave_3_tdata : std_logic_vector(63 downto 0);
signal axis_slave_3_tid : std_logic_vector(2 downto 0);
signal axis_slave_3_tlast : std_logic;
signal axis_slave_3_irq : std_logic;
signal status_3_addr : std_logic_vector(7 downto 0);
signal status_3_data : std_logic_vector(31 downto 0);
signal status_3_stb : std_logic;
signal ctrl_3_addr : std_logic_vector(7 downto 0);
signal ctrl_3_data : std_logic_vector(31 downto 0);
signal ctrl_3_stb : std_logic;
signal axis_master_4_tvalid : std_logic;
signal axis_master_4_tready : std_logic;
signal axis_master_4_tdata : std_logic_vector(63 downto 0);
signal axis_master_4_tdest : std_logic_vector(2 downto 0);
signal axis_master_4_tlast : std_logic;
signal axis_master_4_irq : std_logic;
signal axis_slave_4_tvalid : std_logic;
signal axis_slave_4_tready : std_logic;
signal axis_slave_4_tdata : std_logic_vector(63 downto 0);
signal axis_slave_4_tid : std_logic_vector(2 downto 0);
signal axis_slave_4_tlast : std_logic;
signal axis_slave_4_irq : std_logic;
signal status_4_addr : std_logic_vector(7 downto 0);
signal status_4_data : std_logic_vector(31 downto 0);
signal status_4_stb : std_logic;
signal ctrl_4_addr : std_logic_vector(7 downto 0);
signal ctrl_4_data : std_logic_vector(31 downto 0);
signal ctrl_4_stb : std_logic;
signal axis_master_5_tvalid : std_logic;
signal axis_master_5_tready : std_logic;
signal axis_master_5_tdata : std_logic_vector(63 downto 0);
signal axis_master_5_tdest : std_logic_vector(2 downto 0);
signal axis_master_5_tlast : std_logic;
signal axis_master_5_irq : std_logic;
signal axis_slave_5_tvalid : std_logic;
signal axis_slave_5_tready : std_logic;
signal axis_slave_5_tdata : std_logic_vector(63 downto 0);
signal axis_slave_5_tid : std_logic_vector(2 downto 0);
signal axis_slave_5_tlast : std_logic;
signal axis_slave_5_irq : std_logic;
signal status_5_addr : std_logic_vector(7 downto 0);
signal status_5_data : std_logic_vector(31 downto 0);
signal status_5_stb : std_logic;
signal ctrl_5_addr : std_logic_vector(7 downto 0);
signal ctrl_5_data : std_logic_vector(31 downto 0);
signal ctrl_5_stb : std_logic;
signal axis_master_6_tvalid : std_logic;
signal axis_master_6_tready : std_logic;
signal axis_master_6_tdata : std_logic_vector(63 downto 0);
signal axis_master_6_tdest : std_logic_vector(2 downto 0);
signal axis_master_6_tlast : std_logic;
signal axis_master_6_irq : std_logic;
signal axis_slave_6_tvalid : std_logic;
signal axis_slave_6_tready : std_logic;
signal axis_slave_6_tdata : std_logic_vector(63 downto 0);
signal axis_slave_6_tid : std_logic_vector(2 downto 0);
signal axis_slave_6_tlast : std_logic;
signal axis_slave_6_irq : std_logic;
signal status_6_addr : std_logic_vector(7 downto 0);
signal status_6_data : std_logic_vector(31 downto 0);
signal status_6_stb : std_logic;
signal ctrl_6_addr : std_logic_vector(7 downto 0);
signal ctrl_6_data : std_logic_vector(31 downto 0);
signal ctrl_6_stb : std_logic;
signal axis_master_7_tvalid : std_logic;
signal axis_master_7_tready : std_logic;
signal axis_master_7_tdata : std_logic_vector(63 downto 0);
signal axis_master_7_tdest : std_logic_vector(2 downto 0);
signal axis_master_7_tlast : std_logic;
signal axis_master_7_irq : std_logic;
signal axis_slave_7_tvalid : std_logic;
signal axis_slave_7_tready : std_logic;
signal axis_slave_7_tdata : std_logic_vector(63 downto 0);
signal axis_slave_7_tid : std_logic_vector(2 downto 0);
signal axis_slave_7_tlast : std_logic;
signal axis_slave_7_irq : std_logic;
signal status_7_addr : std_logic_vector(7 downto 0);
signal status_7_data : std_logic_vector(31 downto 0);
signal status_7_stb : std_logic;
signal ctrl_7_addr : std_logic_vector(7 downto 0);
signal ctrl_7_data : std_logic_vector(31 downto 0);
signal ctrl_7_stb : std_logic;
signal rx_enable_aux : std_logic;
signal tx_enable_aux : std_logic;
signal threshold_not_exceeded : std_logic;
signal threshold_not_exceeded_stb : std_logic;
signal threshold_exceeded : std_logic;
signal threshold_exceeded_stb : std_logic;
signal trigger_stb : std_logic;
begin
inst_zc706_ps : zc706_ps
port map (
processing_system7_0_MIO => MIO,
processing_system7_0_PS_SRSTB_pin => PS_SRSTB,
processing_system7_0_PS_CLK_pin => PS_CLK,
processing_system7_0_PS_PORB_pin => PS_PORB,
processing_system7_0_DDR_Clk => DDR_Clk,
processing_system7_0_DDR_Clk_n => DDR_Clk_n,
processing_system7_0_DDR_CKE => DDR_CKE,
processing_system7_0_DDR_CS_n => DDR_CS_n,
processing_system7_0_DDR_RAS_n => DDR_RAS_n,
processing_system7_0_DDR_CAS_n => DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => DDR_BankAddr,
processing_system7_0_DDR_Addr => DDR_Addr,
processing_system7_0_DDR_ODT => DDR_ODT,
processing_system7_0_DDR_DRSTB => DDR_DRSTB,
processing_system7_0_DDR_DQ => DDR_DQ,
processing_system7_0_DDR_DM => DDR_DM,
processing_system7_0_DDR_DQS => DDR_DQS,
processing_system7_0_DDR_DQS_n => DDR_DQS_n,
processing_system7_0_DDR_VRN => DDR_VRN,
processing_system7_0_DDR_VRP => DDR_VRP,
axi_ext_slave_conn_0_M_AXI_AWADDR_pin => S_AXI_AWADDR,
axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID,
axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY,
axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA,
axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB,
axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID,
axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY,
axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP,
axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID,
axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY,
axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR,
axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID,
axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY,
axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA,
axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP,
axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID,
axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY,
processing_system7_0_IRQ_F2P_pin => processing_system7_0_IRQ_F2P_pin,
processing_system7_0_FCLK_CLK0_pin => clk,
processing_system7_0_FCLK_RESET0_N_pin => rst_n,
axi_ext_master_conn_0_S_AXI_AWADDR_pin => M_AXI_AWADDR,
axi_ext_master_conn_0_S_AXI_AWLEN_pin => M_AXI_AWLEN,
axi_ext_master_conn_0_S_AXI_AWSIZE_pin => M_AXI_AWSIZE,
axi_ext_master_conn_0_S_AXI_AWBURST_pin => M_AXI_AWBURST,
axi_ext_master_conn_0_S_AXI_AWCACHE_pin => M_AXI_AWCACHE,
axi_ext_master_conn_0_S_AXI_AWPROT_pin => M_AXI_AWPROT,
axi_ext_master_conn_0_S_AXI_AWVALID_pin => M_AXI_AWVALID,
axi_ext_master_conn_0_S_AXI_AWREADY_pin => M_AXI_AWREADY,
axi_ext_master_conn_0_S_AXI_WDATA_pin => M_AXI_WDATA,
axi_ext_master_conn_0_S_AXI_WSTRB_pin => M_AXI_WSTRB,
axi_ext_master_conn_0_S_AXI_WLAST_pin => M_AXI_WLAST,
axi_ext_master_conn_0_S_AXI_WVALID_pin => M_AXI_WVALID,
axi_ext_master_conn_0_S_AXI_WREADY_pin => M_AXI_WREADY,
axi_ext_master_conn_0_S_AXI_BRESP_pin => M_AXI_BRESP,
axi_ext_master_conn_0_S_AXI_BVALID_pin => M_AXI_BVALID,
axi_ext_master_conn_0_S_AXI_BREADY_pin => M_AXI_BREADY,
axi_ext_master_conn_0_S_AXI_ARADDR_pin => M_AXI_ARADDR,
axi_ext_master_conn_0_S_AXI_ARLEN_pin => M_AXI_ARLEN,
axi_ext_master_conn_0_S_AXI_ARSIZE_pin => M_AXI_ARSIZE,
axi_ext_master_conn_0_S_AXI_ARBURST_pin => M_AXI_ARBURST,
axi_ext_master_conn_0_S_AXI_ARCACHE_pin => M_AXI_ARCACHE,
axi_ext_master_conn_0_S_AXI_ARPROT_pin => M_AXI_ARPROT,
axi_ext_master_conn_0_S_AXI_ARVALID_pin => M_AXI_ARVALID,
axi_ext_master_conn_0_S_AXI_ARREADY_pin => M_AXI_ARREADY,
axi_ext_master_conn_0_S_AXI_RDATA_pin => M_AXI_RDATA,
axi_ext_master_conn_0_S_AXI_RRESP_pin => M_AXI_RRESP,
axi_ext_master_conn_0_S_AXI_RLAST_pin => M_AXI_RLAST,
axi_ext_master_conn_0_S_AXI_RVALID_pin => M_AXI_RVALID,
axi_ext_master_conn_0_S_AXI_RREADY_pin => M_AXI_RREADY,
axi_ext_master_conn_0_S_AXI_AWUSER_pin => M_AXI_AWUSER,
axi_ext_master_conn_0_S_AXI_ARUSER_pin => M_AXI_ARUSER);
processing_system7_0_IRQ_F2P_pin(15) <= irq;
inst_ps_pl_interface : ps_pl_interface
generic map (
C_BASEADDR => x"40000000",
C_HIGHADDR => x"4001ffff")
port map (
clk => clk,
rst_n => rst_n,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARSIZE => M_AXI_ARSIZE,
irq => irq,
rst_glb_n => rst_glb_n,
-- Note: Master 0 & Slave 0 interfaces are occupied by the
-- datamover component internally.
axis_master_1_tvalid => axis_master_1_tvalid,
axis_master_1_tready => axis_master_1_tready,
axis_master_1_tdata => axis_master_1_tdata,
axis_master_1_tdest => axis_master_1_tdest,
axis_master_1_tlast => axis_master_1_tlast,
axis_master_1_irq => axis_master_1_irq,
axis_slave_1_tvalid => axis_slave_1_tvalid,
axis_slave_1_tready => axis_slave_1_tready,
axis_slave_1_tdata => axis_slave_1_tdata,
axis_slave_1_tid => axis_slave_1_tid,
axis_slave_1_tlast => axis_slave_1_tlast,
axis_slave_1_irq => axis_slave_1_irq,
status_1_addr => status_1_addr,
status_1_data => status_1_data,
status_1_stb => status_1_stb,
ctrl_1_addr => ctrl_1_addr,
ctrl_1_data => ctrl_1_data,
ctrl_1_stb => ctrl_1_stb,
axis_master_2_tvalid => axis_master_2_tvalid,
axis_master_2_tready => axis_master_2_tready,
axis_master_2_tdata => axis_master_2_tdata,
axis_master_2_tdest => axis_master_2_tdest,
axis_master_2_tlast => axis_master_2_tlast,
axis_master_2_irq => axis_master_2_irq,
axis_slave_2_tvalid => axis_slave_2_tvalid,
axis_slave_2_tready => axis_slave_2_tready,
axis_slave_2_tdata => axis_slave_2_tdata,
axis_slave_2_tid => axis_slave_2_tid,
axis_slave_2_tlast => axis_slave_2_tlast,
axis_slave_2_irq => axis_slave_2_irq,
status_2_addr => status_2_addr,
status_2_data => status_2_data,
status_2_stb => status_2_stb,
ctrl_2_addr => ctrl_2_addr,
ctrl_2_data => ctrl_2_data,
ctrl_2_stb => ctrl_2_stb,
axis_master_3_tvalid => axis_master_3_tvalid,
axis_master_3_tready => axis_master_3_tready,
axis_master_3_tdata => axis_master_3_tdata,
axis_master_3_tdest => axis_master_3_tdest,
axis_master_3_tlast => axis_master_3_tlast,
axis_master_3_irq => axis_master_3_irq,
axis_slave_3_tvalid => axis_slave_3_tvalid,
axis_slave_3_tready => axis_slave_3_tready,
axis_slave_3_tdata => axis_slave_3_tdata,
axis_slave_3_tid => axis_slave_3_tid,
axis_slave_3_tlast => axis_slave_3_tlast,
axis_slave_3_irq => axis_slave_3_irq,
status_3_addr => status_3_addr,
status_3_data => status_3_data,
status_3_stb => status_3_stb,
ctrl_3_addr => ctrl_3_addr,
ctrl_3_data => ctrl_3_data,
ctrl_3_stb => ctrl_3_stb,
axis_master_4_tvalid => axis_master_4_tvalid,
axis_master_4_tready => axis_master_4_tready,
axis_master_4_tdata => axis_master_4_tdata,
axis_master_4_tdest => axis_master_4_tdest,
axis_master_4_tlast => axis_master_4_tlast,
axis_master_4_irq => axis_master_4_irq,
axis_slave_4_tvalid => axis_slave_4_tvalid,
axis_slave_4_tready => axis_slave_4_tready,
axis_slave_4_tdata => axis_slave_4_tdata,
axis_slave_4_tid => axis_slave_4_tid,
axis_slave_4_tlast => axis_slave_4_tlast,
axis_slave_4_irq => axis_slave_4_irq,
status_4_addr => status_4_addr,
status_4_data => status_4_data,
status_4_stb => status_4_stb,
ctrl_4_addr => ctrl_4_addr,
ctrl_4_data => ctrl_4_data,
ctrl_4_stb => ctrl_4_stb,
axis_master_5_tvalid => axis_master_5_tvalid,
axis_master_5_tready => axis_master_5_tready,
axis_master_5_tdata => axis_master_5_tdata,
axis_master_5_tdest => axis_master_5_tdest,
axis_master_5_tlast => axis_master_5_tlast,
axis_master_5_irq => axis_master_5_irq,
axis_slave_5_tvalid => axis_slave_5_tvalid,
axis_slave_5_tready => axis_slave_5_tready,
axis_slave_5_tdata => axis_slave_5_tdata,
axis_slave_5_tid => axis_slave_5_tid,
axis_slave_5_tlast => axis_slave_5_tlast,
axis_slave_5_irq => axis_slave_5_irq,
status_5_addr => status_5_addr,
status_5_data => status_5_data,
status_5_stb => status_5_stb,
ctrl_5_addr => ctrl_5_addr,
ctrl_5_data => ctrl_5_data,
ctrl_5_stb => ctrl_5_stb,
axis_master_6_tvalid => axis_master_6_tvalid,
axis_master_6_tready => axis_master_6_tready,
axis_master_6_tdata => axis_master_6_tdata,
axis_master_6_tdest => axis_master_6_tdest,
axis_master_6_tlast => axis_master_6_tlast,
axis_master_6_irq => axis_master_6_irq,
axis_slave_6_tvalid => axis_slave_6_tvalid,
axis_slave_6_tready => axis_slave_6_tready,
axis_slave_6_tdata => axis_slave_6_tdata,
axis_slave_6_tid => axis_slave_6_tid,
axis_slave_6_tlast => axis_slave_6_tlast,
axis_slave_6_irq => axis_slave_6_irq,
status_6_addr => status_6_addr,
status_6_data => status_6_data,
status_6_stb => status_6_stb,
ctrl_6_addr => ctrl_6_addr,
ctrl_6_data => ctrl_6_data,
ctrl_6_stb => ctrl_6_stb,
axis_master_7_tvalid => axis_master_7_tvalid,
axis_master_7_tready => axis_master_7_tready,
axis_master_7_tdata => axis_master_7_tdata,
axis_master_7_tdest => axis_master_7_tdest,
axis_master_7_tlast => axis_master_7_tlast,
axis_master_7_irq => axis_master_7_irq,
axis_slave_7_tvalid => axis_slave_7_tvalid,
axis_slave_7_tready => axis_slave_7_tready,
axis_slave_7_tdata => axis_slave_7_tdata,
axis_slave_7_tid => axis_slave_7_tid,
axis_slave_7_tlast => axis_slave_7_tlast,
axis_slave_7_irq => axis_slave_7_irq,
status_7_addr => status_7_addr,
status_7_data => status_7_data,
status_7_stb => status_7_stb,
ctrl_7_addr => ctrl_7_addr,
ctrl_7_data => ctrl_7_data,
ctrl_7_stb => ctrl_7_stb);
-- Accelerator 1
inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis
generic map (
DDR_CLOCK_FREQ => 100e6,
BAUD => 1e6)
port map (
UART_TX => UART_TX,
RX_DATA_CLK_N => RX_DATA_CLK_N,
RX_DATA_CLK_P => RX_DATA_CLK_P,
RX_DATA_N => RX_DATA_N,
RX_DATA_P => RX_DATA_P,
RX_DATA_STB_N => RX_DATA_STB_N,
RX_DATA_STB_P => RX_DATA_STB_P,
TX_DATA_N => TX_DATA_N,
TX_DATA_P => TX_DATA_P,
TX_DATA_STB_N => TX_DATA_STB_N,
TX_DATA_STB_P => TX_DATA_STB_P,
clk => clk,
rst_n => rst_glb_n,
status_addr => status_1_addr,
status_data => status_1_data,
status_stb => status_1_stb,
ctrl_addr => ctrl_1_addr,
ctrl_data => ctrl_1_data,
ctrl_stb => ctrl_1_stb,
axis_slave_tvalid => axis_slave_1_tvalid,
axis_slave_tready => axis_slave_1_tready,
axis_slave_tdata => axis_slave_1_tdata,
axis_slave_tid => axis_slave_1_tid,
axis_slave_tlast => axis_slave_1_tlast,
axis_slave_irq => axis_slave_1_irq,
axis_master_tvalid => axis_master_1_tvalid,
axis_master_tready => axis_master_1_tready,
axis_master_tdata => axis_master_1_tdata,
axis_master_tdest => axis_master_1_tdest,
axis_master_tlast => axis_master_1_tlast,
axis_master_irq => axis_master_1_irq,
rx_enable_aux => rx_enable_aux,
tx_enable_aux => tx_enable_aux);
rx_enable_aux <= '0';
tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded;
-- Accelerator 2
inst_spectrum_sense : spectrum_sense
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_2_addr,
status_data => status_2_data,
status_stb => status_2_stb,
ctrl_addr => ctrl_2_addr,
ctrl_data => ctrl_2_data,
ctrl_stb => ctrl_2_stb,
axis_slave_tvalid => axis_slave_2_tvalid,
axis_slave_tready => axis_slave_2_tready,
axis_slave_tdata => axis_slave_2_tdata,
axis_slave_tid => axis_slave_2_tid,
axis_slave_tlast => axis_slave_2_tlast,
axis_slave_irq => axis_slave_2_irq,
axis_master_tvalid => axis_master_2_tvalid,
axis_master_tready => axis_master_2_tready,
axis_master_tdata => axis_master_2_tdata,
axis_master_tdest => axis_master_2_tdest,
axis_master_tlast => axis_master_2_tlast,
axis_master_irq => axis_master_2_irq,
threshold_not_exceeded => threshold_not_exceeded,
threshold_not_exceeded_stb => threshold_not_exceeded_stb,
threshold_exceeded => threshold_exceeded,
threshold_exceeded_stb => threshold_exceeded_stb);
-- Unused Accelerators
axis_slave_3_tready <= '0';
axis_slave_3_irq <= '0';
axis_master_3_tvalid <= '0';
axis_master_3_tdata <= x"0000000000000000";
axis_master_3_tdest <= "000";
axis_master_3_tlast <= '0';
axis_master_3_irq <= '0';
status_3_data <= x"00000000";
axis_slave_4_tready <= '0';
axis_slave_4_irq <= '0';
axis_master_4_tvalid <= '0';
axis_master_4_tdata <= x"0000000000000000";
axis_master_4_tdest <= "000";
axis_master_4_tlast <= '0';
axis_master_4_irq <= '0';
status_4_data <= x"00000000";
axis_slave_5_tready <= '0';
axis_slave_5_irq <= '0';
axis_master_5_tvalid <= '0';
axis_master_5_tdata <= x"0000000000000000";
axis_master_5_tdest <= "000";
axis_master_5_tlast <= '0';
axis_master_5_irq <= '0';
status_5_data <= x"00000000";
axis_slave_6_tready <= '0';
axis_slave_6_irq <= '0';
axis_master_6_tvalid <= '0';
axis_master_6_tdata <= x"0000000000000000";
axis_master_6_tdest <= "000";
axis_master_6_tlast <= '0';
axis_master_6_irq <= '0';
status_6_data <= x"00000000";
axis_slave_7_tready <= '0';
axis_slave_7_irq <= '0';
axis_master_7_tvalid <= '0';
axis_master_7_tdata <= x"0000000000000000";
axis_master_7_tdest <= "000";
axis_master_7_tlast <= '0';
axis_master_7_irq <= '0';
status_7_data <= x"00000000";
SPARE <= (others=>'Z');
end architecture;
|
gpl-3.0
|
df0d60fadaeef931aea7e00a7c1bb1c2
| 0.464749 | 3.787966 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/outputEncoder.vhd
| 1 | 10,160 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/30 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Encodes the length/distance pair or the literal to the output data stream
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity outputEncoder is
generic (
frameSize : integer := 8; -- number of data items per frame
minMatchLen : integer := 3; -- minimal match length that will be encoded as length/offset pair
maxMatchLen : integer := 16); -- max allowed value for length (must not be bigger than 16)
port (
ClkxCI : in std_logic;
RstxRI : in std_logic; -- Active high sync reset
OffsetxDI : in std_logic_vector(11 downto 0); -- stream history offset for matches
MatchLengthxDI : in integer range 0 to maxMatchLen; -- stream match length in bytes
EnxSI : in std_logic; -- Process input data if high
EndOfDataxSI : in std_logic; -- flushes internal buffers and creates an end-of-data symbol
LiteralxDI : in std_logic_vector(7 downto 0); -- literal byte from the data stream to be encoded (needed if there was no match)
BodyStrobexSO : out std_logic; -- strobe signal: is assert when a new item is available
BodyOutxDO : out std_logic_vector(7 downto 0); -- encoded data output
HeaderStrobexSO : out std_logic;
HeaderOutxDO : out std_logic_vector(frameSize-1 downto 0);
DonexSO : out std_logic); -- indicates that the end of data symbol has been created
end outputEncoder;
architecture Behavorial of outputEncoder is
signal suppressCntxDN, suppressCntxDP : integer range 0 to maxMatchLen := 0; -- data output supression for bytes that have already been encoded
signal FlagBytexDN, FlagBytexDP : std_logic_vector(frameSize-1 downto 0); -- stores the literal / pair flags for 8 output bytes
signal FlagCntxDN, FlagCntxDP : integer range 0 to frameSize := 0; -- number of bytes in the output buffer
signal HeaderStrobexSN, HeaderStrobexSP : std_logic := '0';
signal DonexSN, DonexSP : std_logic := '0';
signal suppressBytexS : std_logic := '0';
signal EncodeAsPairxS : std_logic := '0'; -- signals that this match will be encoded as offset/length pair
signal PairxD : std_logic_vector(15 downto 0); -- offset/length pair represented in two bytes
-- type outputBufferType is array (frameSize downto 0) of std_logic_vector(7 downto 0); -- one more byte to store the overflow byte if we have a pair
-- signal OutBufxDN, OutBufxDP : outputBufferType := (others => (others => '0')); -- buffer to assemble compressed data blocks
signal OutBufInxD : std_logic_vector(7 downto 0); -- input byte for output buffer
signal ShiftOutBufxS : std_logic;
signal OverflowBufxDN, OverflowBufxDP : std_logic_vector(7 downto 0);
signal OvfValidxSN, OvfValidxSP : std_logic;
--signal FlushxSN, FlushxSP : std_logic; -- indicates that buffers should be flushed (end of data processing)
signal EndOfDataxSN, EndOfDataxSP : std_logic := '0'; -- set when an end of data condition is detected
begin -- Behavorial
-- every match that is long enough will be encoded as offset/length pair
EncodeAsPairxS <= '1' when MatchLengthxDI >= minMatchLen or EndOfDataxSI = '1' else '0';
process (EndOfDataxSI, MatchLengthxDI, OffsetxDI)
begin -- process
PairxD <= std_logic_vector(to_unsigned(MatchLengthxDI-1, 4)) & OffsetxDI;
end process;
-- purpose: implements an output data suppress counter for bytes which have already been encoded in a previous match
suppressCntPrcs : process (EncodeAsPairxS, EnxSI, MatchLengthxDI,
suppressCntxDP)
begin -- process suppressCntPrcs
suppressCntxDN <= suppressCntxDP; -- default: do nothing
suppressBytexS <= '0';
if EnxSI = '1' then
if suppressCntxDP > 0 then
-- this byte has already been encoded -> suppress it
suppressBytexS <= '1';
suppressCntxDN <= suppressCntxDP - 1;
else
-- check if have to reload the counter
if EncodeAsPairxS = '1' then
suppressCntxDN <= MatchLengthxDI - 1; -- -1 because this one byte is processed now, we suppress (discard) the next length-1 bytes
end if;
end if;
end if;
end process suppressCntPrcs;
bufCntPrcs : process (DonexSP, EncodeAsPairxS, EndOfDataxSI, EndOfDataxSP,
EnxSI, FlagBytexDP, FlagCntxDP, LiteralxDI,
OverflowBufxDP, OvfValidxSP, PairxD, suppressBytexS)
begin -- process bufCntPrcs
OutBufInxD <= (others => '-'); -- use - to improve optimization
OverflowBufxDN <= OverflowBufxDP;
FlagBytexDN <= FlagBytexDP;
OvfValidxSN <= '0';
ShiftOutBufxS <= '0';
FlagCntxDN <= FlagCntxDP;
HeaderStrobexSN <= '0';
DonexSN <= DonexSP;
EndOfDataxSN <= EndOfDataxSP or EndOfDataxSI; -- remember an end-of-data condition
if EnxSI = '1' and suppressBytexS = '0' and EndOfDataxSP = '0' then
ShiftOutBufxS <= '1';
if EncodeAsPairxS = '1' then
-- we encode data as a pair, this means we have two bytes
OverflowBufxDN <= PairxD(7 downto 0); -- save second byte in overflow buffer
OutBufInxD <= PairxD(15 downto 8); -- big endian encoding
FlagBytexDN(FlagCntxDP) <= '1'; -- mark bytes as offset/length pair
OvfValidxSN <= '1'; -- mark that we have a byte in the overflow buffer
-- note: we don't check for end of frame here as the frame isn't over
-- now (there is a second byte in the overflow buffer)
else
-- encode data as literal
OutBufInxD <= LiteralxDI;
FlagBytexDN(FlagCntxDP) <= '0';
-- check for end of frame
if FlagCntxDP = frameSize-1 then
FlagCntxDN <= 0;
HeaderStrobexSN <= '1';
else
FlagCntxDN <= FlagCntxDP + 1;
end if;
end if;
end if;
if OvfValidxSP = '1' then -- this is ok, as we can not have two pairs on consecutive clock cycles (one pair encodes >= 3 bytes)
-- copy byte from overflow buffer into output shift register
OutBufInxD <= OverflowBufxDP;
ShiftOutBufxS <= '1';
-- check for the end of a frame
if FlagCntxDP = frameSize-1 then
FlagCntxDN <= 0;
HeaderStrobexSN <= '1';
else
FlagCntxDN <= FlagCntxDP + 1;
end if;
if EndOfDataxSP = '1' then
-- this is the very last byte in the stream
HeaderStrobexSN <= '1'; -- send the last header byte(s)
EndOfDataxSN <= '0'; -- transmission of end of data flag is done
DonexSN <= '1';
end if;
end if;
if EndOfDataxSP = '1' and OvfValidxSP = '0' and EnxSI = '0' then
-- an end of data was requested, insert the eof symbol (length/offset pair with a length of zero)
OverflowBufxDN <= x"00";
OvfValidxSN <= '1';
FlagBytexDN(FlagCntxDP) <= '1';
OutBufInxD <= x"00";
ShiftOutBufxS <= '1';
end if;
end process bufCntPrcs;
BodyOutxDO <= OutBufInxD;
BodyStrobexSO <= ShiftOutBufxS;
HeaderOutxDO <= FlagBytexDP;
HeaderStrobexSO <= HeaderStrobexSP;
DonexSO <= DonexSP;
-- purpose: implements the flip flops
-- type : sequential
regs : process (ClkxCI)
begin -- process regs
if ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if RstxRI = '1' then
suppressCntxDP <= 0;
FlagCntxDP <= 0;
OvfValidxSP <= '0';
OverflowBufxDP <= (others => '0');
EndOfDataxSP <= '0';
FlagBytexDP <= (others => '0');
HeaderStrobexSP <= '0';
DonexSP <= '0';
else
suppressCntxDP <= suppressCntxDN;
FlagCntxDP <= FlagCntxDN;
OvfValidxSP <= OvfValidxSN;
OverflowBufxDP <= OverflowBufxDN;
EndOfDataxSP <= EndOfDataxSN;
FlagBytexDP <= FlagBytexDN;
HeaderStrobexSP <= HeaderStrobexSN;
DonexSP <= DonexSN;
end if;
end if;
end process regs;
end Behavorial;
|
gpl-2.0
|
c47310dc4e3da815087f8b15e1791b4c
| 0.589764 | 4.467898 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_lfsr.vhd
| 1 | 5,951 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_lfsr
---- Version: 1.0.0
---- Description:
---- Linear Feedback Shift Register
---- Input: none
---- Timing requirements: CCSDS_RXTX_LFSR_DATA_BUS_SIZE+1 clock cycles for valid output data
---- Output: dat_val_o <= "1" / dat_o <= "LFSRSEQUENCE"
---- Ressources requirements: TODO
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- Test ressources:
-- GNURADIO GLFSR block
-- CCSDS parameters
-- Width = 8
-- Mode = Fibonacci ('0')
-- Polynomial = x"A9"
-- Seed = x"FF"
-- Result = "1111111101001000000011101100000010011010"
-- Width = 8
-- Mode = Galois ('1')
-- Polynomial = x"A9"
-- Seed = x"FF"
-- Result = "101001011011000001011000110110"
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx randomizer inputs and outputs
--=============================================================================
entity ccsds_rxtx_lfsr is
generic(
constant CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_RXTX_LFSR_MEMORY_SIZE: integer range 2 to 256 := 8; -- in bits
constant CCSDS_RXTX_LFSR_MODE: std_logic := '0'; -- 0: Fibonacci / 1: Galois
constant CCSDS_RXTX_LFSR_POLYNOMIAL: std_logic_vector := x"A9"; -- Polynomial / MSB <=> lower polynome (needs to be '1')
constant CCSDS_RXTX_LFSR_SEED: std_logic_vector := x"FF" -- Initial Value
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_rxtx_lfsr;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_rxtx_lfsr is
-- internal constants
-- internal variable signals
signal lfsr_memory: std_logic_vector(CCSDS_RXTX_LFSR_MEMORY_SIZE-1 downto 0) := CCSDS_RXTX_LFSR_SEED;
-- components instanciation and mapping
begin
-- presynthesis checks
CHKLFSRP0 : if CCSDS_RXTX_LFSR_POLYNOMIAL'length /= CCSDS_RXTX_LFSR_MEMORY_SIZE generate
process
begin
report "ERROR: LFSR_POLYNOMIAL LENGTH MUST BE EQUAL TO MEMORY SIZE (SHORTENED VERSION / DON'T PUT MANDATORY HIGHER POLYNOME '1')" severity failure;
wait;
end process;
end generate CHKLFSRP0;
CHKLFSRP1 : if CCSDS_RXTX_LFSR_MEMORY_SIZE <= 1 generate
process
begin
report "ERROR: LFSR_MEMORY_SIZE MUST BE BIGGER THAN 1" severity failure;
wait;
end process;
end generate CHKLFSRP1;
CHKLFSRP2 : if CCSDS_RXTX_LFSR_SEED'length /= CCSDS_RXTX_LFSR_MEMORY_SIZE generate
process
begin
report "ERROR: LFSR_SEED LENGTH MUST BE EQUAL TO LFSR_MEMORY_SIZE" severity failure;
wait;
end process;
end generate CHKLFSRP2;
CHKLFSRP3 : if CCSDS_RXTX_LFSR_POLYNOMIAL(CCSDS_RXTX_LFSR_MEMORY_SIZE-1) = '0' generate
process
begin
report "ERROR: LFSR POLYNOMIAL MSB MUST BE EQUAL TO 1" severity failure;
wait;
end process;
end generate CHKLFSRP3;
-- internal processing
--=============================================================================
-- Begin of crcp
-- Compute CRC based on input data
--=============================================================================
-- read: rst_i
-- write: dat_o, dat_val_o
-- r/w: lfsr_memory
LFSRP: process (clk_i)
variable output_pointer: integer range -1 to (CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1) := CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1;
variable feedback_register: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
lfsr_memory <= CCSDS_RXTX_LFSR_SEED;
dat_o <= (others => '0');
dat_val_o <= '0';
output_pointer := CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1;
feedback_register := '0';
else
-- generation is finished
if (output_pointer = -1) then
dat_val_o <= '1';
-- generating sequence
else
dat_val_o <= '0';
-- Fibonacci
if (CCSDS_RXTX_LFSR_MODE = '0') then
dat_o(output_pointer) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
output_pointer := output_pointer - 1;
feedback_register := lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
for i in 0 to CCSDS_RXTX_LFSR_MEMORY_SIZE-2 loop
if (CCSDS_RXTX_LFSR_POLYNOMIAL(i) = '1') then
feedback_register := feedback_register xor lfsr_memory(i);
end if;
end loop;
lfsr_memory <= std_logic_vector(resize(unsigned(lfsr_memory),CCSDS_RXTX_LFSR_MEMORY_SIZE-1)) & feedback_register;
-- Galois
else
dat_o(output_pointer) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
output_pointer := output_pointer - 1;
lfsr_memory(0) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
for i in 1 to CCSDS_RXTX_LFSR_MEMORY_SIZE-1 loop
if (CCSDS_RXTX_LFSR_POLYNOMIAL(i) = '1') then
lfsr_memory(i) <= lfsr_memory(i-1) xor lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
else
lfsr_memory(i) <= lfsr_memory(i-1);
end if;
end loop;
end if;
end if;
end if;
end if;
end process;
end structure;
|
mit
|
4efaf3c854f4ad415347211cdb871b9f
| 0.554529 | 3.99396 | false | false | false | false |
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_oversampler.vhd
| 1 | 4,071 |
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_oversampler
---- Version: 1.0.0
---- Description:
---- Insert OSR-1 '0' between symbols
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary rxtx oversampler inputs and outputs
--=============================================================================
entity ccsds_rxtx_oversampler is
generic(
constant CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer := 4;
constant CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: boolean := false;
constant CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
-- outputs
sam_o: out std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end ccsds_rxtx_oversampler;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_rxtx_oversampler is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKOVERSAMPLERP0 : if (CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO mod 2 /= 0) generate
process
begin
report "ERROR: OVERSAMPLING RATIO HAS TO BE A MULTIPLE OF 2" severity failure;
wait;
end process;
end generate CHKOVERSAMPLERP0;
CHKOVERSAMPLERP1 : if (CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO = 0) generate
process
begin
report "ERROR: OVERSAMPLING RATIO CANNOT BE 0" severity failure;
wait;
end process;
end generate CHKOVERSAMPLERP1;
-- internal processing
--=============================================================================
-- Begin of osrp
-- Insert all 0 samples
--=============================================================================
-- read: rst_i, sam_i
-- write: sam_o
-- r/w:
OSRP: process (clk_i)
variable samples_counter: integer range 0 to CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1 := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sam_o <= (others => '0');
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
else
if (sam_val_i = '1') then
sam_val_o <= '1';
if (CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING = true) then
if (samples_counter <= 0) then
sam_o <= (others => '0');
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
else
if (samples_counter = CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO/2) then
sam_o <= sam_i;
else
sam_o <= (others => '0');
end if;
samples_counter := samples_counter - 1;
end if;
else
if (samples_counter <= 0) then
sam_o <= sam_i;
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
else
sam_o <= (others => '0');
samples_counter := samples_counter - 1;
end if;
end if;
else
sam_val_o <= '0';
end if;
end if;
end if;
end process;
end structure;
|
mit
|
18998e034fae7c1b043acf2726fc9cfe
| 0.507738 | 4.673938 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/outputEncoderTb.vhd
| 1 | 8,484 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/7/8 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* This is the test bench for outputEncoder.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity outputEncoder_tb is
end outputEncoder_tb;
-------------------------------------------------------------------------------
architecture Tb of outputEncoder_tb is
component outputEncoder
generic (
frameSize : integer;
minMatchLen : integer;
maxMatchLen : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
OffsetxDI : in std_logic_vector(11 downto 0);
MatchLengthxDI : in integer range 0 to maxMatchLen;
EnxSI : in std_logic;
EndOfDataxSI : in std_logic;
LiteralxDI : in std_logic_vector(7 downto 0);
BodyStrobexSO : out std_logic; -- strobe signal: is assert when a new item is available
BodyOutxDO : out std_logic_vector(7 downto 0); -- encoded data output
HeaderStrobexSO : out std_logic;
HeaderOutxDO : out std_logic_vector(frameSize-1 downto 0);
DonexSO : out std_logic);
end component;
-- component generics
constant frameSize : integer := 8;
constant minMatchLen : integer := 3;
constant maxMatchLen : integer := 16;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal OffsetxDI : std_logic_vector(11 downto 0) := (others => '0');
signal MatchLengthxDI : integer range 0 to maxMatchLen := 0;
signal EnxSI : std_logic := '0';
signal EndOfDataxSI : std_logic := '0';
signal LiteralxDI : std_logic_vector(7 downto 0) := x"00";
-- signal EncHeaderOutxDO : std_logic_vector(frameSize-1 downto 0);
-- signal EncBodyOutputxDO : std_logic_vector(frameSize*8-1 downto 0);
-- signal EncOutputValidxSO : std_logic;
signal BodyStrobexSO : std_logic; -- strobe signal: is assert when a new item is available
signal BodyOutxDO : std_logic_vector(7 downto 0); -- encoded data output
signal HeaderStrobexSO : std_logic;
signal HeaderOutxDO : std_logic_vector(frameSize-1 downto 0);
signal DonexSO : std_logic;
-- clock
signal Clk : std_logic := '1';
begin -- Tb
-- component instantiation
DUT : outputEncoder
generic map (
frameSize => frameSize,
minMatchLen => minMatchLen,
maxMatchLen => maxMatchLen)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
OffsetxDI => OffsetxDI,
MatchLengthxDI => MatchLengthxDI,
EnxSI => EnxSI,
EndOfDataxSI => EndOfDataxSI,
LiteralxDI => LiteralxDI,
BodyStrobexSO => BodyStrobexSO,
BodyOutxDO => BodyOutxDO,
HeaderStrobexSO => HeaderStrobexSO,
HeaderOutxDO => HeaderOutxDO,
DonexSO => DonexSO);
-- clock generation
Clk <= not Clk after 10 ns;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
begin
wait until Clk'event and Clk = '1';
wait until Clk'event and Clk = '1';
RstxRI <= '0';
MatchLengthxDI <= 3;
OffsetxDI <= x"00a";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
LiteralxDI <= x"11";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
OffsetxDI <= x"222";
LiteralxDI <= x"22";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 2;
LiteralxDI <= x"11";
OffsetxDI <= x"fff";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 4;
OffsetxDI <= x"010";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
LiteralxDI <= x"11";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
OffsetxDI <= x"222";
LiteralxDI <= x"22";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 5; -- will be suppressed
LiteralxDI <= x"33";
wait until Clk'event and Clk = '1';
EnxSI <= '0';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0;
LiteralxDI <= x"ab";
OffsetxDI <= x"000";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
EnxSI <= '0';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 1;
LiteralxDI <= x"cd";
OffsetxDI <= x"00a";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
EnxSI <= '0';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 4;
OffsetxDI <= x"123";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
LiteralxDI <= x"11";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
OffsetxDI <= x"222";
LiteralxDI <= x"22";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 5; -- will be suppressed
LiteralxDI <= x"33";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 3;
OffsetxDI <= x"aaa";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
LiteralxDI <= x"11";
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 0; -- will be suppressed
OffsetxDI <= x"222";
LiteralxDI <= x"22";
wait until Clk'event and Clk = '1';
EnxSI <= '0';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 1;
LiteralxDI <= x"ef";
OffsetxDI <= x"00a";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
EnxSI <= '0';
wait until Clk'event and Clk = '1';
MatchLengthxDI <= 1;
LiteralxDI <= x"00";
OffsetxDI <= x"00a";
EnxSI <= '1';
wait until Clk'event and Clk = '1';
EnxSI <= '0';
EndOfDataxSI <= '1';
wait until Clk'event and Clk = '1';
EndOfDataxSI <= '0';
EnxSI <= '0';
wait;
end process WaveGen_Proc;
end Tb;
-------------------------------------------------------------------------------
configuration outputEncoder_tb_Tb_cfg of outputEncoder_tb is
for Tb
end for;
end outputEncoder_tb_Tb_cfg;
-------------------------------------------------------------------------------
|
gpl-2.0
|
51745b616e2505dd529b37bc44a4119a
| 0.506129 | 4.43956 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/xst_14_2/history.vhd
| 1 | 15,621 |
--/**************************************************************************************************************
--*
--* B i t H o u n d - A n F P G A B a s e d L o g i c A n a l y z e r
--*
--* FPGA Design
--*
--* Copyright 2012 Mario Mauerer (MM), Lukas Schrittwieser (LS), ETH Zurich
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 3 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program. If not, see <http://www.gnu.org/licenses/>.
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/21 - LS
--* started file
--*
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--*
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity historyBuffer is
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
WriteInxDI : in std_logic_vector(7 downto 0);
WExSI : in std_logic;
NextWrAdrxDO : out std_logic_vector(11 downto 0); -- memory address at which the next byte will be written
RExSI : in std_logic; -- initiate a memory read back
ReadBackAdrxDI : in std_logic_vector(11 downto 2); -- for speed up read back is only word adressable
ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
ReadBackDonexSO : out std_logic); -- indicates that requested read back data is available
end historyBuffer;
architecture Behavioral of historyBuffer is
signal WrPtrxDN, WrPtrxDP : std_logic_vector(11 downto 0) := (others => '0');
signal RamWrAdrxD : std_logic_vector(13 downto 0); -- address for all memroy banks
signal Ram0RdAdrAxD, Ram0RdAdrBxD : std_logic_vector(13 downto 0);
signal Ram1RdAdrAxD, Ram1RdAdrBxD : std_logic_vector(13 downto 0);
signal Ram0AdrAxD, Ram1AdrAxD : std_logic_vector(13 downto 0);
signal RamWrDataxD : std_logic_vector(31 downto 0);
signal Ram0OutAxD, Ram0OutBxD : std_logic_vector(32 downto 0);
signal Ram1OutAxD, Ram1OutBxD : std_logic_vector(31 downto 0);
signal Ram0WExS, Ram1WExS : std_logic;
signal RdAdrIntxD : integer; -- to split up long expressions (type casts)
signal Ram0RdAdrBasexD, Ram1RdAdrBasexD : integer;
signal LastReadBackAdrxDN, LastReadBackAdrxDP : std_logic_vector(11 downto 2);
begin
RamWrAdrxD <= "000000" & WrPtrxDP(11 downto 3);
-- Note: If the requested address is not a multiple of 8 (ie bit 2 is 1) the
-- first word (4 bytes) we read is in ram 1. Therefore the adress for ram 0 has
-- to be incremented by 1.
RdAdrIntxD <= to_integer(unsigned(ReadBackAdrxDI(11 downto 3)));
Ram0RdAdrBasexD <= RdAdrIntxD when ReadBackAdrxDI(2) = '0' else RdAdrIntxD+1;
Ram1RdAdrBasexD <= RdAdrIntxD;
Ram0RdAdrAxD <= "000000" & std_logic_vector(unsigned(Ram0RdAdrBasexD, 9));
Ram0RdAdrBxD <= "000000" & std_logic_vector(unsigned(Ram0RdAdrBasexD+1, 9));
Ram1RdAdrAxD <= "000000" & std_logic_vector(unsigned(Ram1RdAdrBasexD, 9));
Ram1RdAdrBxD <= "000000" & std_logic_vector(unsigned(Ram1RdAdrBasexD+1, 9));
-- select port A address based on read/write mode
Ram0AdrAxD <= Ram0RdAdrAxD when WExSI = '0' else ("000000", WrPtrxDP(11 downto 3));
Ram1AdrAxD <= Ram1RdAdrBxD when WExSI = '0' else ("000000", WrPtrxDP(11 downto 3));
RamWrDataxD <= WriteInxDI & WriteInxDI & WriteInxDI & WriteInxDI;
-- The memory behaves like a register -> save requested adress for output decoder
LastReadBackAdrxDN <= ReadBackAdrxDI;
-- the read back value is reordered depending on wether the requested address
-- is a multiple of 8 or not. See comment above.
ReadBackxDO <= (Ram0OutAxD, Ram1OutAxD, Ram0OutBxD, Ram1OutBxD) when LastReadBackAdrxDP(2) = '0' \
else (Ram1OutAxD, Ram0OutAxD, Ram1OutBxD, Ram0OutBxD);
-- implement a write address counter
wrCntPrcs : process (WExSI, WrPtrxDP)
begin
WrPtrxDN <= WrPtrxDP;
Ram0WExS <= "0000";
Ram1WExS <= "0000";
if WExSI = '1' then
WrPtrxDN <= std_logic_vector(unsigned(to_integer(unsigned(WrPtrxDP))+1, 12));
-- decode lower 3 bits to the 8 write enable lines
if WrPtrxDP(2) = '0' then
-- write to ram 0
Ram0WExS(to_integer(unsigned(WrPtrxDP(1 downto 0)))) <= '1';
else
Ram1WExS(to_integer(unsigned(WrPtrxDP(1 downto 0)))) <= '1';
end if;
end if;
end process wrCntPrcs;
NextWrAdrxDO <= WrPtrxDP;
process (ClkxCI, RstxRI)
begin -- process
if RstxRI = '1' then
LastReadBackAdrxDP <= (others => '0');
WrPtrxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
LastReadBackAdrxDP <= LastReadBackAdrxDN;
WrPtrxDP <= WrPtrxDN;
end if;
end process;
-- port A is used to write and read (lower bytes) data, port B is for read only
HistMem0Inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36,
DATA_WIDTH_B => 36,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => Ram0OutAxD, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => Ram0OutBxD,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => Ram0AdrAxD, -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => '1', -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => Ram0WExS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => RamWrDataxD, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => Ram0RdAdrBxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
-- RAM 1
-- port A is used to write and read (lower bytes) data, port B is for read only
HistMem1Inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36,
DATA_WIDTH_B => 36,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => Ram1OutAxD, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => Ram1OutBxD,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => Ram1AdrAxD, -- port A is used to write and read (lower bytes) data, port B is for read only
HistMem0Inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36,
DATA_WIDTH_B => 36,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => true,
EN_RSTRAM_B => true,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) Port A data
DOA => Ram0OutAxD, -- 32-bit A port data output
DOPA => open, -- 4-bit A port parity output
-- Port B Data: 32-bit (each) Port B data
DOB => Ram0OutBxD,
DOPB => open,
-- Port A Address/Control Signals: 14-bit (each) Port A address and control signals
ADDRA => Ram0AdrAxD, -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => , -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => "1111", -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => RamWrDataxD, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => Ram0RdAdrBxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
); -- 14-bit A port address input
CLKA => ClkxCI, -- 1-bit A port clock input
ENA => '1', -- 1-bit A port enable input
REGCEA => '1', -- 1-bit A port register clock enable input
RSTA => RstxRI, -- 1-bit A port register set/reset input
WEA => Ram1WExS, -- 4-bit Port A byte-wide write enable input
-- Port A Data: 32-bit (each) Port A data
DIA => RamWrDataxD, -- 32-bit A port data input
DIPA => "0000", -- 4-bit A port parity input
-- Port B Address/Control Signals: 14-bit (each) Port B address and control signals
ADDRB => Ram1RdAdrBxD, -- 14-bit B port address input
CLKB => ClkxCI, -- 1-bit B port clock input
ENB => '0', -- 1-bit B port enable input
REGCEB => '0', -- 1-bit B port register clock enable input
RSTB => RstxRI, -- 1-bit B port register set/reset input
WEB => x"0", -- 4-bit Port B byte-wide write enable input
-- Port B Data: 32-bit (each) Port B data
DIB => x"00000000", -- 32-bit B port data input
DIPB => x"0" -- 4-bit B port parity input
);
end Behavioral;
|
gpl-2.0
|
3dc500c2b72ca2be7133228fa6060f00
| 0.541771 | 3.908181 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/testbench/historyTb.vhd
| 1 | 6,050 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/10/16 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Simple testbench for manual signal inspection for histroy buffer.
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity historyBuffer_tb is
end historyBuffer_tb;
-------------------------------------------------------------------------------
architecture tb of historyBuffer_tb is
component historyBuffer
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
WriteInxDI : in std_logic_vector(7 downto 0);
WExSI : in std_logic;
NextWrAdrxDO : out std_logic_vector(11 downto 0);
RExSI : in std_logic;
ReadBackAdrxDI : in std_logic_vector(11 downto 2);
ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
ReadBackDonexSO : out std_logic);
end component;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal WriteInxDI : std_logic_vector(7 downto 0) := (others => '0');
signal WExSI : std_logic := '0';
signal NextWrAdrxDO : std_logic_vector(11 downto 0);
signal RExSI : std_logic := '0';
signal ReadBackAdrxDI : std_logic_vector(11 downto 2) := (others => '0');
signal ReadBackxDO : std_logic_vector(16*8-1 downto 0);
signal ReadBackDonexSO : std_logic;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT: historyBuffer
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
WriteInxDI => WriteInxDI,
WExSI => WExSI,
NextWrAdrxDO => NextWrAdrxDO,
RExSI => RExSI,
ReadBackAdrxDI => ReadBackAdrxDI,
ReadBackxDO => ReadBackxDO,
ReadBackDonexSO => ReadBackDonexSO);
-- clock generation
Clk <= not Clk after 10 ns;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc: process
begin
wait for 10 ns;
wait until Clk = '1';
RstxRI <= '0';
-- first: write some data to buffer
wait until Clk'event and Clk='1';
WriteInxDI <= x"00";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"01";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"02";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"03";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"04";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"05";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"06";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"07";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"08";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"09";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0a";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0b";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0c";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0d";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0e";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"0f";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"10";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"11";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"12";
WExSI <= '1';
wait until Clk'event and Clk='1';
WriteInxDI <= x"13";
WExSI <= '1';
wait until Clk'event and Clk='1';
WExSI <= '0';
-- now read back
ReadBackAdrxDI <= "0000000000";
wait until Clk'event and Clk='1';
ReadBackAdrxDI <= "0000000001";
wait until Clk'event and Clk='1';
ReadBackAdrxDI <= "0000000010";
wait until Clk'event and Clk='1';
wait;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration historyBuffer_tb_tb_cfg of historyBuffer_tb is
for tb
end for;
end historyBuffer_tb_tb_cfg;
-------------------------------------------------------------------------------
|
gpl-2.0
|
178399fa3892e805174c8501edda4af5
| 0.510579 | 4.257565 | false | false | false | false |
dgfiloso/VHDL_DSED_P3
|
PIC/tb_ram.vhd
| 1 | 3,684 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:25:41 11/22/2016
-- Design Name:
-- Module Name: C:/Users/dsed12/Desktop/DSED/Practica 3/PIC/tb_ram.vhd
-- Project Name: PIC
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ram
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_ram IS
END tb_ram;
ARCHITECTURE behavior OF tb_ram IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ram
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
write_en : IN std_logic;
oe : IN std_logic;
address : IN std_logic_vector(7 downto 0);
databus : INOUT std_logic_vector(7 downto 0);
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_H : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal write_en : std_logic := '0';
signal oe : std_logic := '0';
signal address : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal databus : std_logic_vector(7 downto 0);
--Outputs
signal Switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ram PORT MAP (
Clk => Clk,
Reset => Reset,
write_en => write_en,
oe => oe,
address => address,
databus => databus,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Reset <= '0', '1' after 125 ns;
-- Permitimos escribir en RAM
write_en <= 'Z', '1' after 75 ns, 'Z' after 300 ns;
-- Permitimos lectura de la RAM
oe <= 'Z', '0' after 325 ns, 'Z' after 600 ns;
-- Variaciones de los datos y las direcciones
databus <= (others => 'Z'), "00000001" after 85 ns, "01010101" after 135 ns, "00010001" after 185 ns, (others => 'Z') after 240 ns;
address <= (others => 'Z'), DMA_RX_BUFFER_MSB after 85 ns, DMA_RX_BUFFER_MID after 135 ns, DMA_RX_BUFFER_LSB after 185 ns,
-- DMA_TX_BUFFER_MSB after 330 ns, DMA_TX_BUFFER_LSB after 380 ns, T_STAT after 430 ns, (others => 'Z') after 500 ns;
T_STAT after 300 ns, (others => 'Z') after 500 ns;
wait;
end process;
END;
|
mit
|
f9c1f64824f82c903263d6a6119860ef
| 0.573018 | 3.618861 | false | false | false | false |
jayvalentine/vhdl-risc-processor
|
memory_interface.vhd
| 1 | 4,814 |
-- memory interface circuit
-- handles memory read/write and memory mapping to internal and external memory/io
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
-- opcodes
-- 000 is no operation
-- 001 is read byte
-- 010 is read half-word
-- 011 is read word
-- 100 is write byte
-- 101 is write half-word
-- 110 is write word
-- 111 is set block address
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity memory_interface is
port (
-- address
addr : in std_logic_vector(31 downto 0);
-- data in/out
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0) := (others => '0');
-- memory opcode
opcode : in std_logic_vector(2 downto 0);
-- rst, clk and bsy signal
rst : in std_logic;
clk : in std_logic;
bsy : out std_logic := '0';
-- address output, data inout, clk
ext_addr : out std_logic_vector(31 downto 0);
ext_data : inout std_logic_vector(7 downto 0);
ext_clk : out std_logic;
-- data access clock
data_clk : in std_logic
);
end entity memory_interface;
architecture memory_interface_arch of memory_interface is
-- block address
signal block_addr : integer := 0;
-- memory address
signal mem_addr : integer;
-- internal r/w
signal wr : std_logic;
-- bytes, counter
signal bytes : integer;
signal count : integer := 0;
-- external memory access active
signal ext_active : std_logic;
-- internal data buffer
signal data_buf : std_logic_vector(31 downto 0);
begin
-- design implementation
interface : process(clk)
begin
-- on reset high, reset internal counter, block address and signal bits
if rst = '1' then
block_addr <= 0;
bytes <= 0;
mem_addr <= 0;
wr <= '0';
ext_active <= '0';
bsy <= '0';
data_out <= (others => '0');
ext_addr <= (others => '0');
else
-- on rising clock edge, read/write
if rising_edge(clk) then
-- signal memory busy
bsy <= '1';
-- calculate address
mem_addr <= block_addr + to_integer(unsigned(addr));
-- opcode 001 is read byte
if opcode = "001" then
wr <= '0';
bytes <= 2;
ext_active <= '1';
-- opcode 010 is read half-word
elsif opcode = "010" then
wr <= '0';
bytes <= 2;
ext_active <= '1';
-- opcode 011 is read word
elsif opcode = "011" then
wr <= '0';
bytes <= 4;
ext_active <= '1';
-- opcode 100 is write byte
elsif opcode = "100" then
wr <= '1';
bytes <= 1;
ext_active <= '1';
-- opcode 101 is write half-word
elsif opcode = "101" then
wr <= '1';
bytes <= 2;
ext_active <= '1';
-- opcode 110 is write word
elsif opcode = "110" then
wr <= '1';
bytes <= 4;
ext_active <= '1';
-- opcode 111 is set block addr
elsif opcode = "111" then
wr <= '0';
bytes <= 0;
ext_active <= '0';
block_addr <= to_integer(unsigned(addr));
end if;
-- read/write if external memory access flag set
if ext_active = '1' then
while count < bytes loop
-- set external address
ext_addr <= std_logic_vector(to_unsigned(mem_addr, 32));
if wr = '1' then
-- first byte
if count = 0 then
ext_data <= data_in(7 downto 0);
-- second byte
elsif count = 1 then
ext_data <= data_in(15 downto 8);
-- third byte
elsif count = 2 then
ext_data <= data_in(23 downto 16);
-- fourth byte
elsif count = 3 then
ext_data <= data_in(31 downto 24);
end if;
else
-- first byte
if count = 0 then
data_buf(7 downto 0) <= ext_data;
-- second byte
elsif count = 1 then
data_buf(15 downto 8) <= ext_data;
-- third byte
elsif count = 2 then
data_buf(23 downto 16) <= ext_data;
-- fourth byte
elsif count = 3 then
data_buf(31 downto 24) <= ext_data;
end if;
end if;
-- on rising data clk edge set external clock high if writing
if rising_edge(data_clk) then
if wr = '1' then
ext_clk <= '1';
end if;
end if;
-- on falling edge set external clock low if writing and increment count and addr
if falling_edge(data_clk) then
if wr = '1' then
ext_clk <= '0';
end if;
count <= count + 1;
mem_addr <= mem_addr + 1;
end if;
end loop;
-- update data_out line with internal buffer contents
if wr = '0' then
data_out <= data_buf;
end if;
end if;
-- signal memory no longer busy
bsy <= '0';
end if;
end if;
end process interface;
end architecture memory_interface_arch;
|
mit
|
2dbad7aa591803b52da756c94276288a
| 0.566265 | 3.152587 | false | false | false | false |
GorosVi/AlDe
|
VGAOut.vhd
| 2 | 4,022 |
library IEEE;
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VOut is
port (
CLK : in STD_LOGIC;
TM : in STD_LOGIC := '1'; -- Negative
HS : out STD_LOGIC; -- Negative
VS : out STD_LOGIC; -- Negative
RCH : out STD_LOGIC_VECTOR(3 downto 0);
GCH : out STD_LOGIC_VECTOR(3 downto 0);
BCH : out STD_LOGIC_VECTOR(3 downto 0)
);
end entity;
architecture Behavioral of VOut is
-- 1024x768 @ 60Hz, 65mHz pixel clock - params from tinyvga.com/vga-timing
constant HorVisArea : INTEGER := 1024;
constant HorFrPArea : INTEGER := 24;
constant HorSyPArea : INTEGER := 136;
constant HorBkPArea : INTEGER := 160;
constant HorTotArea : INTEGER := HorVisArea + HorFrPArea + HorSyPArea + HorBkPArea;
constant VerVisArea : INTEGER := 768;
constant VerFrPArea : INTEGER := 3;
constant VerSyPArea : INTEGER := 6;
constant VerBkPArea : INTEGER := 29;
constant VerTotArea : INTEGER := VerVisArea + VerFrPArea + VerSyPArea + VerBkPArea;
signal color : STD_LOGIC;
signal VTest : STD_LOGIC;
signal mpos : INTEGER range 0 to 8979;
signal CCNT : INTEGER range 0 to HorTotArea;
signal RCNT : INTEGER range 0 to VerTotArea;
signal cctmp : INTEGER range 0 to VerVisArea;
signal picv : STD_LOGIC_VECTOR (7 downto 0);
component thpic is
port (
CLK : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (13 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
begin
TPic: thpic port map (
adr => conv_std_logic_vector(mpos,14),
clk => CLK,
q => picv
);
process(CLK)
begin
if rising_edge(CLK) then
-- Video test mode control
VTest <= not TM;
-- Video output
if CCNT < HorVisArea and RCNT < VerVisArea
then
if VTest = '0' then
-- Visible area control
if color = '1'
then RCH <= x"F"; GCH <= x"F"; BCH <= x"F";
else RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
-- Grid for display test
elsif conv_std_logic_vector(CCNT,1) = b"0" and conv_std_logic_vector(RCNT,1) = b"0" and
CCNT /= 2 and RCNT /= 2 and CCNT /= HorVisArea - 4 and RCNT /= VerVisArea - 4
then RCH <= x"F"; GCH <= x"F"; BCH <= x"F";
else RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
else
RCH <= x"0"; GCH <= x"0"; BCH <= x"0";
end if;
-- Overflow control
if (CCNT = HorTotArea - 1) then
CCNT <= 0;
if RCNT = VerTotArea - 1 then
RCNT <= 0;
else
RCNT <= RCNT + 1;
end if;
else
CCNT <= CCNT + 1;
end if;
-- Sync pulse generation - negative polarity
if (CCNT >= HorVisArea + HorFrPArea) and (CCNT < HorTotArea - HorBkPArea) then
HS <= '0';
else
HS <= '1';
end if;
if (RCNT >= VerVisArea + VerFrPArea) and (RCNT < VerTotArea - VerBkPArea) then
VS <= '0';
else
VS <= '1';
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
-- Fetch new pixel value
if (cctmp < HorVisArea) and (CCNT = cctmp) then
cctmp <= cctmp + conv_integer(picv(6 downto 0));
color <= picv(7);
mpos <= mpos + 1;
end if;
-- Fetch the new row
if CCNT = HorTotArea - 1 then
cctmp <= 0;
end if;
-- Clear memory position each new frame
if (CCNT = HorTotArea - 2) and (RCNT = VerTotArea - 1) then
mpos <= 1;
end if;
end if;
end process;
end Behavioral;
library IEEE, ALTERA;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ALTERA.ALTERA_SYN_ATTRIBUTES.ALL;
entity thpic is
port (
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (13 downto 0);
q : out STD_LOGIC_VECTOR (7 downto 0)
);
end thpic;
architecture rtl of thpic is
type mem_t is array (8979 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal rom: mem_t;
attribute ram_init_file: string;
attribute ram_init_file of rom: signal is "TPic.mif";
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= rom(conv_integer(adr));
end if;
end process;
end rtl;
|
mit
|
ef9b6d64c39a63f73aff5957602b7170
| 0.62357 | 2.810622 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/CompressorTop.vhd
| 1 | 22,852 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/10/16 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* released
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Top level file for data compressor. Implements the wishbone interfaces, a
--* simple DMA controller and some glue logic.
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity CompressorTop is
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
-- wishbone config and data input interface (32 bit access only!!)
SlCycxSI : in std_logic;
SlStbxSI : in std_logic;
SlWexSI : in std_logic;
SlSelxDI : in std_logic_vector(3 downto 0);
SlAdrxDI : in std_logic_vector(4 downto 2);
SlDatxDI : in std_logic_vector(31 downto 0);
SlDatxDO : out std_logic_vector(31 downto 0);
SlAckxSO : out std_logic;
SlErrxSO : out std_logic;
IntxSO : out std_logic;
-- wishbone dma master interface
MaCycxSO : out std_logic;
MaStbxSO : out std_logic;
MaWexSO : out std_logic;
MaSelxDO : out std_logic_vector(3 downto 0);
MaAdrxDO : out std_logic_vector(31 downto 0);
MaDatxDO : out std_logic_vector(31 downto 0);
MaDatxDI : in std_logic_vector(31 downto 0);
MaAckxSI : in std_logic;
MaErrxSI : in std_logic
);
end CompressorTop;
architecture Behavioral of CompressorTop is
component InputFIFO
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DInxDI : in std_logic_vector(31 downto 0);
WExSI : in std_logic;
StopOutputxSI : in std_logic;
BusyxSO : out std_logic;
DOutxDO : out std_logic_vector(7 downto 0);
OutStrobexSO : out std_logic;
LengthxDO : out integer range 0 to 2048);
end component;
component LZRWcompressor
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DataInxDI : in std_logic_vector(7 downto 0);
StrobexSI : in std_logic;
FlushBufxSI : in std_logic;
BusyxSO : out std_logic;
DonexSO : out std_logic;
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024);
end component;
constant INPUT_FIFO_SIZE : integer := 1024; -- length of input fifo in bytes
constant DMA_LEN_SIZE : integer := 16; -- size of dma len counter in bits
--constant MAX_DMA_LEN_VALUE : integer := 2**16-1; -- maximum value of the dma length counter
signal RstCorexSN, RstCorexSP : std_logic := '1';
signal WeInFIFOxS : std_logic;
signal InFIFOLenxD : integer range 0 to INPUT_FIFO_SIZE;
signal CoreBusyxS : std_logic;
signal CoreDonexS : std_logic;
signal CoreDatInxD : std_logic_vector(7 downto 0);
signal CoreStbxS : std_logic;
signal FIFOBusyxS : std_logic;
signal FlushxSN, FlushxSP : std_logic := '0';
signal FlushCorexSN, FlushCorexSP : std_logic := '0';
signal CoreRdStbxS : std_logic;
signal OutFIFOLenxD : integer range 0 to 1024;
signal CoreDatOutxD : std_logic_vector(7 downto 0);
signal CoreOutValidxS : std_logic;
signal ClearIntFlagsxSN, ClearIntFlagsxSP : std_logic := '0';
signal ClearInFIFOFlagsxS, ClearOutFIFOFlagsxS : std_logic;
signal InFIFOEmptyFlgxSN, InFIFOEmptyFlgxSP : std_logic := '0';
signal InFIFOFullFlgxSN, InFIFOFullFlgxSP : std_logic := '0';
signal OutFIFOEmptyFlgxSN, OutFIFOEmptyFlgxSP : std_logic := '0';
signal OutFIFOFullFlgxSN, OutFIFOFullFlgxSP : std_logic := '0';
signal IEInFIFOEmptyxSN, IEInFIFOEmptyxSP : std_logic := '0';
signal IEInFIFOFullxSN, IEInFIFOFullxSP : std_logic := '0';
signal IEOutFIFOEmptyxSN, IEOutFIFOEmptyxSP : std_logic := '0';
signal IEOutFIFOFullxSN, IEOutFIFOFullxSP : std_logic := '0';
signal IEDmaErrxSN, IEDmaErrxSP : std_logic := '0';
signal IECoreDonexSN, IECoreDonexSP : std_logic := '0';
signal IRQxSN, IRQxSP : std_logic := '0';
signal InFIFOEmptyThrxDN, InFIFOEmptyThrxDP : std_logic_vector(15 downto 0) := (others => '0');
signal InFIFOFullThrxDN, InFIFOFullThrxDP : std_logic_vector(15 downto 0) := (others => '1');
signal OutFIFOEmptyThrxDN, OutFIFOEmptyThrxDP : std_logic_vector(15 downto 0) := (others => '0');
signal OutFIFOFullThrxDN, OutFIFOFullThrxDP : std_logic_vector(15 downto 0) := (others => '1');
signal IncDestAdrFlgxSN, IncDestAdrFlgxSP : std_logic := '0';
signal DmaErrFlgxSN, DmaErrFlgxSP : std_logic := '0';
signal WrDmaDestAdrxS : std_logic;
signal WrDmaLenxS : std_logic;
signal DmaBusyxSN, DmaBusyxSP : std_logic := '0';
signal DmaDestAdrxDN, DmaDestAdrxDP : std_logic_vector(31 downto 0) := (others => '0');
signal XferByteCntxDN, XferByteCntxDP : integer range 0 to 4 := 0;
signal DmaLenxDN, DmaLenxDP : integer range 0 to 2**DMA_LEN_SIZE-1 := 0;
signal DmaDataOutxDN, DmaDataOutxDP : std_logic_vector(31 downto 0) := (others => '0');
signal DmaSelxSN, DmaSelxSP : std_logic_vector(3 downto 0) := (others => '0');
signal MaCycxSN, MaCycxSP : std_logic := '0';
signal MaStbxSN, MaStbxSP : std_logic := '0';
begin -- Behavioral
WbSlInPrcs : process (DmaBusyxSP, FlushCorexSP, FlushxSP, IECoreDonexSP,
IEDmaErrxSP, IEInFIFOEmptyxSP, IEInFIFOFullxSP,
IEOutFIFOEmptyxSP, IEOutFIFOFullxSP, InFIFOEmptyThrxDP,
InFIFOFullThrxDP, IncDestAdrFlgxSP, OutFIFOEmptyThrxDP,
OutFIFOFullThrxDP, SlAdrxDI, SlCycxSI, SlDatxDI,
SlStbxSI, SlWexSI)
begin
WeInFIFOxS <= '0';
RstCorexSN <= '0';
FlushxSN <= FlushxSP and not FlushCorexSP; -- clear flush flag when core is flushed
ClearInFIFOFlagsxS <= '0';
ClearOutFIFOFlagsxS <= '0';
ClearIntFlagsxSN <= '0';
IEInFIFOEmptyxSN <= IEInFIFOEmptyxSP;
IEInFIFOFullxSN <= IEInFIFOFullxSP;
IEOutFIFOEmptyxSN <= IEOutFIFOEmptyxSP;
IEOutFIFOFullxSN <= IEOutFIFOFullxSP;
IEDmaErrxSN <= IEDmaErrxSP;
IECoreDonexSN <= IECoreDonexSP;
IncDestAdrFlgxSN <= IncDestAdrFlgxSP;
InFIFOEmptyThrxDN <= InFIFOEmptyThrxDP;
InFIFOFullThrxDN <= InFIFOFullThrxDP;
OutFIFOFullThrxDN <= OutFIFOFullThrxDP;
OutFIFOEmptyThrxDN <= OutFIFOEmptyThrxDP;
WrDmaDestAdrxS <= '0';
WrDmaLenxS <= '0';
-- decode write commands
if SlCycxSI = '1' and SlStbxSI = '1' and SlWexSI = '1' then
case SlAdrxDI is
when "000" => -- data input register
if FlushxSP = '0' then -- ignore all data after flush command was sent
WeInFIFOxS <= '1';
end if;
when "001" => -- config flags
if DmaBusyxSP = '0' then
IncDestAdrFlgxSN <= SlDatxDI(8);
end if;
IEInFIFOEmptyxSN <= SlDatxDI(16);
IEInFIFOFullxSN <= SlDatxDI(17);
IEOutFIFOEmptyxSN <= SlDatxDI(18);
IEOutFIFOFullxSN <= SlDatxDI(19);
IEDmaErrxSN <= SlDatxDI(20);
IECoreDonexSN <= SlDatxDI(21);
ClearIntFlagsxSN <= '1';
when "010" =>
InFIFOFullThrxDN <= SlDatxDI(31 downto 16);
InFIFOEmptyThrxDN <= SlDatxDI(15 downto 0);
ClearInFIFOFlagsxS <= '1';
when "011" =>
OutFIFOFullThrxDN <= SlDatxDI(31 downto 16);
OutFIFOEmptyThrxDN <= SlDatxDI(15 downto 0);
ClearOutFIFOFlagsxS <= '1';
when "100" =>
-- may only be written if dma unit is not busy
if DmaBusyxSP = '0' then
WrDmaDestAdrxS <= '1';
end if;
when "101" =>
if DmaBusyxSP = '0' then
WrDmaLenxS <= '1';
end if;
when "111" => -- command register
if SlDatxDI(0) = '1' then
-- reset command
RstCorexSN <= SlDatxDI(0);
ClearInFIFOFlagsxS <= '1';
ClearOutFIFOFlagsxS <= '1';
end if;
FlushxSN <= SlDatxDI(1) or FlushxSP;
when others => null;
end case;
end if;
end process WbSlInPrcs;
-- we flush the core if a flush was requested and the intput fifo is empty
FlushCorexSN <= '1' when FlushxSP = '1' and InFIFOLenxD = 0 else '0';
process (CoreDonexS, DmaBusyxSP, DmaDestAdrxDP, DmaErrFlgxSP, DmaLenxDP,
IECoreDonexSP, IEDmaErrxSP, IEInFIFOEmptyxSP, IEInFIFOFullxSP,
IEOutFIFOEmptyxSP, IEOutFIFOFullxSP, InFIFOEmptyFlgxSP,
InFIFOEmptyThrxDP, InFIFOFullFlgxSP, InFIFOFullThrxDP, InFIFOLenxD,
IncDestAdrFlgxSP, OutFIFOEmptyFlgxSP, OutFIFOEmptyThrxDP,
OutFIFOFullFlgxSP, OutFIFOFullThrxDN, OutFIFOLenxD, SlAdrxDI,
SlCycxSI, SlStbxSI, SlWexSI, XferByteCntxDP)
begin --
SlDatxDO <= x"00000000";
-- decode read commands
if SlCycxSI = '1' and SlStbxSI = '1' and SlWexSI = '0' then
case SlAdrxDI is
when "000" => null; -- data input, no read access
when "001" => -- config and status reg
SlDatxDO(3) <= DmaBusyxSP;
SlDatxDO(8) <= IncDestAdrFlgxSP; -- config flags
SlDatxDO(16) <= IEInFIFOEmptyxSP; -- interrupt enables
SlDatxDO(17) <= IEInFIFOFullxSP;
SlDatxDO(18) <= IEOutFIFOEmptyxSP;
SlDatxDO(19) <= IEOutFIFOFullxSP;
SlDatxDO(20) <= IEDmaErrxSP;
SlDatxDO(21) <= IECoreDonexSP;
SlDatxDO(24) <= InFIFOEmptyFlgxSP; -- interrupt flags
SlDatxDO(25) <= InFIFOFullFlgxSP;
SlDatxDO(26) <= OutFIFOEmptyFlgxSP;
SlDatxDO(27) <= OutFIFOFullFlgxSP;
SlDatxDO(28) <= DmaErrFlgxSP;
SlDatxDO(29) <= CoreDonexS;
--ClearIntFlagsxSN <= '1';
when "010" => SlDatxDO <= InFIFOFullThrxDP & InFIFOEmptyThrxDP;
when "011" => SlDatxDO <= OutFIFOFullThrxDN & OutFIFOEmptyThrxDP;
when "100" => SlDatxDO <= DmaDestAdrxDP(31 downto 2) & std_logic_vector(to_unsigned(XferByteCntxDP, 2));
when "101" => SlDatxDO <= x"0000" & std_logic_vector(to_unsigned(DmaLenxDP, DMA_LEN_SIZE));
when "110" => SlDatxDO <= std_logic_vector(to_unsigned(OutFIFOLenxD, 16)) & std_logic_vector(to_unsigned(InFIFOLenxD, 16));
when others => null;
end case;
end if;
end process;
-- create an ACK on slave bus for all 32bits accesses. Other types of
-- accesses are not possible -> terminate with error signal
SlAckxSO <= SlCycxSI and SlStbxSI when SlSelxDI = "1111" else '0';
SlErrxSO <= SlCycxSI and SlStbxSI when SlSelxDI /= "1111" else '0';
InterruptsPrcs : process (ClearInFIFOFlagsxS, ClearIntFlagsxSP,
ClearOutFIFOFlagsxS, CoreDonexS, DmaErrFlgxSP,
IECoreDonexSP, IEDmaErrxSP, IEInFIFOEmptyxSP,
IEInFIFOFullxSP, IEOutFIFOEmptyxSP,
IEOutFIFOFullxSP, InFIFOEmptyFlgxSP,
InFIFOEmptyThrxDP, InFIFOFullFlgxSP,
InFIFOFullThrxDP, InFIFOLenxD, OutFIFOEmptyFlgxSP,
OutFIFOEmptyThrxDP, OutFIFOFullFlgxSP,
OutFIFOFullThrxDP, OutFIFOLenxD)
begin
InFIFOEmptyFlgxSN <= InFIFOEmptyFlgxSP;
InFIFOFullFlgxSN <= InFIFOFullFlgxSP;
OutFIFOEmptyFlgxSN <= OutFIFOEmptyFlgxSP;
OutFIFOFullFlgxSN <= OutFIFOFullFlgxSP;
if ClearInFIFOFlagsxS = '0' then
if InFIFOLenxD < to_integer(unsigned(InFIFOEmptyThrxDP)) then
InFIFOEmptyFlgxSN <= '1';
end if;
if InFIFOLenxD >= to_integer(unsigned(InFIFOFullThrxDP)) then
InFIFOFullFlgxSN <= '1';
end if;
else
InFIFOEmptyFlgxSN <= '0';
InFIFOFullFlgxSN <= '0';
end if;
if ClearOutFIFOFlagsxS = '0' then
if OutFIFOLenxD < to_integer(unsigned(OutFIFOEmptyThrxDP)) then
OutFIFOEmptyFlgxSN <= '1';
end if;
if OutFIFOLenxD >= to_integer(unsigned(OutFIFOFullThrxDP)) then
OutFIFOFullFlgxSN <= '1';
end if;
else
OutFIFOEmptyFlgxSN <= '0';
OutFIFOFullFlgxSN <= '0';
end if;
if ClearIntFlagsxSP = '1' then
InFIFOEmptyFlgxSN <= '0';
InFIFOFullFlgxSN <= '0';
OutFIFOEmptyFlgxSN <= '0';
OutFIFOFullFlgxSN <= '0';
end if;
IRQxSN <= (InFIFOEmptyFlgxSP and IEInFIFOEmptyxSP) or
(InFIFOFullFlgxSP and IEInFIFOFullxSP) or
(OutFIFOEmptyFlgxSP and IEOutFIFOEmptyxSP) or
(OutFIFOFullFlgxSP and IEOutFIFOFullxSP) or
(DmaErrFlgxSP and IEDmaErrxSP) or
(CoreDonexS and IECoreDonexSP);
end process InterruptsPrcs;
IntxSO <= IRQxSP;
DmaPrcs : process (ClearIntFlagsxSP, CoreDatOutxD, CoreOutValidxS,
DmaDataOutxDP, DmaDestAdrxDP, DmaErrFlgxSP, DmaLenxDP,
DmaSelxSP, IncDestAdrFlgxSP, MaAckxSI, MaCycxSP, MaErrxSI,
MaStbxSP, OutFIFOLenxD, RstCorexSP, SlDatxDI,
WrDmaDestAdrxS, WrDmaLenxS, XferByteCntxDP)
begin
DmaLenxDN <= DmaLenxDP;
DmaDestAdrxDN <= DmaDestAdrxDP;
XferByteCntxDN <= XferByteCntxDP;
DmaDataOutxDN <= DmaDataOutxDP;
DmaSelxSN <= DmaSelxSP;
CoreRdStbxS <= '0';
MaCycxSN <= MaCycxSP;
MaStbxSN <= MaStbxSP;
DmaErrFlgxSN <= DmaErrFlgxSP;
-- if len is not zero dma unit is busy with a transfer
if DmaLenxDP = 0 then
DmaBusyxSN <= '0';
if WrDmaDestAdrxS = '1' then
-- the last two bits specify at which byte within the 4 byte wide bus
-- we start -> load them into the transfer byte counter
DmaDestAdrxDN <= SlDatxDI(31 downto 2) & "00";
XferByteCntxDN <= to_integer(unsigned(SlDatxDI(1 downto 0)));
DmaSelxSN <= (others => '0');
end if;
if WrDmaLenxS = '1' then
DmaLenxDN <= to_integer(unsigned(SlDatxDI(DMA_LEN_SIZE-1 downto 0)));
end if;
else
if RstCorexSP = '1' then
-- abort the dma operation
DmaLenxDN <= 0;
MaCycxSN <= '0';
MaStbxSN <= '0';
DmaBusyxSN <= '0';
else
DmaBusyxSN <= '1';
-- wait until the last wishbone transfer is done
if MaCycxSP = '0' then
-- read data from output fifo when it becomes available
if OutFIFOLenxD > 0 then
-- output a read strobe if there is room for more than one byte
-- (check dma length counter and transfer byte counter). This condition is
-- loosened if there is no byte comming in this cycle
if (XferByteCntxDP < 3 and DmaLenxDP > 1) or CoreOutValidxS = '0' then
-- send read request to core
CoreRdStbxS <= '1';
end if;
end if;
if CoreOutValidxS = '1' then
-- copy byte from core into output buffer
DmaLenxDN <= DmaLenxDP - 1;
if IncDestAdrFlgxSP = '1' and XferByteCntxDP < 4 then
XferByteCntxDN <= XferByteCntxDP + 1;
end if;
DmaDataOutxDN((XferByteCntxDP+1)*8-1 downto XferByteCntxDP*8) <= CoreDatOutxD;
DmaSelxSN(XferByteCntxDP) <= '1';
-- if we write the last byte (end of buffer or end of fifo or end of dma len) address or we have a don't inc
-- transfer we create a whishbone cycle
if XferByteCntxDP = 3 or IncDestAdrFlgxSP = '0' or DmaLenxDP = 1 or OutFIFOLenxD = 0 then
MaCycxSN <= '1';
MaStbxSN <= '1';
end if;
end if;
end if;
end if;
end if;
-- wait for an ack or err from the slave
if MaAckxSI = '1' then
-- transfer is done, deassert signals
MaCycxSN <= '0';
MaStbxSN <= '0';
DmaSelxSN <= (others => '0'); -- reset sel signals for next transfer
if XferByteCntxDP = 4 then
XferByteCntxDN <= 0;
-- inc destination address to the next word
if IncDestAdrFlgxSP = '1' then
DmaDestAdrxDN <= std_logic_vector(to_unsigned(to_integer(unsigned(DmaDestAdrxDP))+4, 32));
end if;
end if;
end if;
if MaErrxSI = '1' then
-- transfer is done, deassert signals
MaCycxSN <= '0';
MaStbxSN <= '0';
-- an whishbone error occured, abort dma transfer
DmaLenxDN <= 0;
DmaErrFlgxSN <= '1';
end if;
if ClearIntFlagsxSP = '1' then
DmaErrFlgxSN <= '0';
end if;
end process DmaPrcs;
MaCycxSO <= MaCycxSP;
MaStbxSO <= MaStbxSP;
MaSelxDO <= DmaSelxSP;
MaDatxDO <= DmaDataOutxDP;
MaAdrxDO <= DmaDestAdrxDP;
MaWexSO <= '1'; -- we don't do any reads on the dma interface
-- registers
process (ClkxCI)
begin
if ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if RstxRI = '1' then
RstCorexSP <= '1';
FlushxSP <= '0';
FlushCorexSP <= '0';
ClearIntFlagsxSP <= '0';
InFIFOEmptyFlgxSP <= '0';
InFIFOFullFlgxSP <= '0';
OutFIFOEmptyFlgxSP <= '0';
OutFIFOFullFlgxSP <= '0';
IEInFIFOEmptyxSP <= '0';
IEInFIFOFullxSP <= '0';
IEOutFIFOEmptyxSP <= '0';
IEOutFIFOFullxSP <= '0';
IEDmaErrxSP <= '0';
IECoreDonexSP <= '0';
IRQxSP <= '0';
InFIFOEmptyThrxDP <= (others => '0');
InFIFOFullThrxDP <= (others => '1');
OutFIFOEmptyThrxDP <= (others => '0');
OutFIFOFullThrxDP <= (others => '1');
IncDestAdrFlgxSP <= '0';
DmaErrFlgxSP <= '0';
DmaBusyxSP <= '0';
DmaDestAdrxDP <= (others => '0');
XferByteCntxDP <= 0;
DmaLenxDP <= 0;
DmaDataOutxDP <= (others => '0');
DmaSelxSP <= (others => '0');
MaCycxSP <= '0';
MaStbxSP <= '0';
else
RstCorexSP <= RstCorexSN;
FlushxSP <= FlushxSN;
FlushCorexSP <= FlushCorexSN;
ClearIntFlagsxSP <= ClearIntFlagsxSN;
InFIFOEmptyFlgxSP <= InFIFOEmptyFlgxSN;
InFIFOFullFlgxSP <= InFIFOFullFlgxSN;
OutFIFOEmptyFlgxSP <= OutFIFOEmptyFlgxSN;
OutFIFOFullFlgxSP <= OutFIFOFullFlgxSN;
IEInFIFOEmptyxSP <= IEInFIFOEmptyxSN;
IEInFIFOFullxSP <= IEInFIFOFullxSN;
IEOutFIFOEmptyxSP <= IEOutFIFOEmptyxSN;
IEOutFIFOFullxSP <= IEOutFIFOFullxSN;
IEDmaErrxSP <= IEDmaErrxSN;
IECoreDonexSP <= IECoreDonexSN;
IRQxSP <= IRQxSN;
InFIFOEmptyThrxDP <= InFIFOEmptyThrxDN;
InFIFOFullThrxDP <= InFIFOFullThrxDN;
OutFIFOEmptyThrxDP <= OutFIFOEmptyThrxDN;
OutFIFOFullThrxDP <= OutFIFOFullThrxDN;
IncDestAdrFlgxSP <= IncDestAdrFlgxSN;
DmaErrFlgxSP <= DmaErrFlgxSN;
DmaBusyxSP <= DmaBusyxSP;
DmaDestAdrxDP <= DmaDestAdrxDN;
XferByteCntxDP <= XferByteCntxDN;
DmaLenxDP <= DmaLenxDN;
DmaDataOutxDP <= DmaDataOutxDN;
DmaSelxSP <= DmaSelxSN;
MaCycxSP <= MaCycxSN;
MaStbxSP <= MaStbxSN;
end if;
end if;
end process;
-- input data FIFO buffer
InputFIFOInst : InputFIFO
port map (
ClkxCI => ClkxCI,
RstxRI => RstCorexSP,
DInxDI => SlDatxDI,
WExSI => WeInFIFOxS,
StopOutputxSI => CoreBusyxS,
BusyxSO => FIFOBusyxS,
DOutxDO => CoreDatInxD,
OutStrobexSO => CoreStbxS,
LengthxDO => InFIFOLenxD);
LZRWcompressorInst : LZRWcompressor
port map (
ClkxCI => ClkxCI,
RstxRI => RstCorexSP,
DataInxDI => CoreDatInxD,
StrobexSI => CoreStbxS,
FlushBufxSI => FlushCorexSP,
BusyxSO => CoreBusyxS,
DonexSO => CoreDonexS,
BufOutxDO => CoreDatOutxD,
OutputValidxSO => CoreOutValidxS,
RdStrobexSI => CoreRdStbxS,
LengthxDO => OutFIFOLenxD);
end Behavioral;
|
gpl-2.0
|
401952e14679f01cc8d73f7bf01af3cc
| 0.561001 | 4.666531 | false | false | false | false |
freecores/lzrw1-compressor-core
|
hw/HDL/LZRWcompressor.vhd
| 1 | 26,041 |
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/6/17 - LS
--* started file
--*
--* Version 1.0 - 2013/04/05 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* This is the main file of the compression core. It connects several
--* sub-cores in a pipeline. Data IO is bytewise.
--*
--***************************************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity LZRWcompressor is
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
DataInxDI : in std_logic_vector(7 downto 0); -- uncompressed data input
StrobexSI : in std_logic; -- strobe for input data
FlushBufxSI : in std_logic;
BusyxSO : out std_logic; -- data can only be strobed in if this is low
DonexSO : out std_logic; -- flush is done, all data has been processed
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024
);
end LZRWcompressor;
architecture Behavioral of LZRWcompressor is
component HashTable
generic (
entryBitWidth : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
NewEntryxDI : in std_logic_vector(entryBitWidth-1 downto 0);
EnWrxSI : in std_logic;
Key0xDI : in std_logic_vector(7 downto 0);
Key1xDI : in std_logic_vector(7 downto 0);
Key2xDI : in std_logic_vector(7 downto 0);
OldEntryxDO : out std_logic_vector(entryBitWidth-1 downto 0));
end component;
component historyBuffer
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
WriteInxDI : in std_logic_vector(7 downto 0);
WExSI : in std_logic;
NextWrAdrxDO : out std_logic_vector(11 downto 0);
RExSI : in std_logic;
ReadBackAdrxDI : in std_logic_vector(11 downto 2);
ReadBackxDO : out std_logic_vector(16*8-1 downto 0);
ReadBackDonexSO : out std_logic);
end component;
component comparator
port (
LookAheadxDI : in std_logic_vector(16*8-1 downto 0);
LookAheadLenxDI : in integer range 0 to 16;
CandidatexDI : in std_logic_vector(16*8-1 downto 0);
CandidateLenxDI : in integer range 0 to 16;
MatchLenxDO : out integer range 0 to 16);
end component;
component outputEncoder
generic (
frameSize : integer;
minMatchLen : integer;
maxMatchLen : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
OffsetxDI : in std_logic_vector(11 downto 0);
MatchLengthxDI : in integer range 0 to maxMatchLen;
EnxSI : in std_logic;
EndOfDataxSI : in std_logic;
LiteralxDI : in std_logic_vector(7 downto 0);
BodyStrobexSO : out std_logic;
BodyOutxDO : out std_logic_vector(7 downto 0);
HeaderStrobexSO : out std_logic;
HeaderOutxDO : out std_logic_vector(frameSize-1 downto 0);
DonexSO : out std_logic);
end component;
component outputFIFO
generic (
frameSize : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
BodyDataxDI : in std_logic_vector(7 downto 0);
BodyStrobexSI : in std_logic;
HeaderDataxDI : in std_logic_vector(frameSize-1 downto 0);
HeaderStrobexSI : in std_logic;
BuffersEmptyxSO : out std_logic;
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024);
end component;
constant HIST_BUF_LEN : integer := 4096; -- length of the history buffer in bytes (DO NOT CHANGE!!)
constant LOOK_AHEAD_LEN : integer := 16; -- length of the look ahead buffer in bytes (DO NOT CHANGE!!)
constant OUT_FIFO_THR : integer := 1000; -- output length at which we set busy high. Should be at least one max frame size below 1024
type lookAheadBufType is array (LOOK_AHEAD_LEN-1 downto 0) of std_logic_vector(7 downto 0);
type ctrlFSMType is (ST_FILL_LOOK_AHEAD, ST_RUN, ST_DRAIN_LOOK_AHEAD, ST_DONE);
signal LookAheadBufxDN, LookAheadBufxDP : lookAheadBufType := (others => (others => '0'));
signal LookAheadLenxDN, LookAheadLenxDP : integer range 0 to LOOK_AHEAD_LEN := 0;
signal ShiftLookAheadxSN, ShiftLookAheadxSP : std_logic := '0';
signal Strobe0xSN, Strobe0xSP : std_logic := '0';
signal HistBufLen0xDN, HistBufLen0xDP : integer range 0 to HIST_BUF_LEN := 0; -- count history buffer length at startup
signal HistBufOutxD : std_logic_vector(LOOK_AHEAD_LEN*8-1 downto 0);
signal EndOfData0xSN, EndOfData0xSP : std_logic := '0';
signal DataIn0xDN, DataIn0xDP : std_logic_vector(7 downto 0) := x"00";
signal WrHistBufxS : std_logic;
signal LookAheadPtr0xD : std_logic_vector(11 downto 0);
signal NextWrAdrxD : std_logic_vector(11 downto 0);
signal BusyxSN, BusyxSP : std_logic := '0';
signal StatexSN, StatexSP : ctrlFSMType := ST_FILL_LOOK_AHEAD;
signal HashTableEntryxD : std_logic_vector(11 downto 0); -- entry found by the hash table
signal LookAheadLen1xDN, LookAheadLen1xDP : integer range 0 to LOOK_AHEAD_LEN := 0;
signal Strobe1xSN, Strobe1xSP : std_logic := '0';
signal HistBufLen1xDN, HistBufLen1xDP : integer range 0 to HIST_BUF_LEN := 0;
signal EndOfData1xSN, EndOfData1xSP : std_logic := '0';
signal LookAheadBuf1xDN, LookAheadBuf1xDP : lookAheadBufType := (others => (others => '0'));
signal WrAdr1xDN, WrAdr1xDP : std_logic_vector(11 downto 0) := (others => '0');
signal LookAheadPtr1xDN, LookAheadPtr1xDP : std_logic_vector(11 downto 0) := (others => '0');
signal CandAddr1xDN, CandAddr1xDP : std_logic_vector(11 downto 0) := (others => '0');
signal LookAheadLen2xDN, LookAheadLen2xDP : integer range 0 to LOOK_AHEAD_LEN := 0;
signal LookAheadBuf2xDN, LookAheadBuf2xDP : lookAheadBufType := (others => (others => '0'));
signal Strobe2xSN, Strobe2xSP : std_logic := '0';
signal HistBufLen2xDN, HistBufLen2xDP : integer range 0 to HIST_BUF_LEN := 0;
signal Candidate2xDN, Candidate2xDP : std_logic_vector(LOOK_AHEAD_LEN*8-1 downto 0) := (others => '0');
signal NextWrAdr2xDN, NextWrAdr2xDP : integer range 0 to LOOK_AHEAD_LEN := 0;
signal CandAddr2xDN, CandAddr2xDP : std_logic_vector(11 downto 0) := (others => '0');
signal CandLen2xDN, CandLen2xDP : integer range 0 to LOOK_AHEAD_LEN;
signal EndOfData2xSN, EndOfData2xSP : std_logic := '0';
signal OffsetIntxD : integer range -HIST_BUF_LEN to HIST_BUF_LEN;
signal OffsetxD : std_logic_vector(11 downto 0);
signal HashTableEntry2xDN, HashTableEntry2xDP : std_logic_vector(11 downto 0) := (others => '0');
signal MaxCandLenxD : integer range 0 to LOOK_AHEAD_LEN;
signal MatchLenxD, MatchLenLimitedxD : integer range 0 to LOOK_AHEAD_LEN := 0;
signal LookAheadPtr2xDN, LookAheadPtr2xDP : std_logic_vector(11 downto 0) := (others => '0');
signal CompLAIn3xD : std_logic_vector(LOOK_AHEAD_LEN*8-1 downto 0);
signal HeaderStrobexS : std_logic;
signal HeaderDataxD : std_logic_vector(7 downto 0);
signal BodyStrobexS : std_logic;
signal BodyDataxD : std_logic_vector(7 downto 0);
signal FifoBuffersEmptyxS : std_logic;
signal OutFIFOLengthxD : integer range 0 to 1024;
signal EncDonexS : std_logic;
signal Done3xSN, Done3xSP : std_logic := '0';
begin
-----------------------------------------------------------------------------
-- Pipeline stage 0
-----------------------------------------------------------------------------
-- control FSM for look ahead buffer
process (DataIn0xDP, DataInxDI, FlushBufxSI, LookAheadLenxDP,
OutFIFOLengthxD, StatexSP, Strobe0xSP, StrobexSI)
begin
StatexSN <= StatexSP;
ShiftLookAheadxSN <= '0';
WrHistBufxS <= '0';
Strobe0xSN <= '0';
EndOfData0xSN <= '0';
DataIn0xDN <= DataIn0xDP;
BusyxSN <= '0';
case StatexSP is
when ST_FILL_LOOK_AHEAD =>
-- don't shift here, we are still loading data
--ShiftLookAheadxSN <= StrobexSI; -- the shift is delayed by one cycle because we have to process the byte first
WrHistBufxS <= StrobexSI;
DataIn0xDN <= DataInxDI;
if FlushBufxSI = '1' then
StatexSN <= ST_DRAIN_LOOK_AHEAD;
elsif LookAheadLenxDP = LOOK_AHEAD_LEN-1 then
-- this byte is number look_ahead_len-1, so it is the last one before the buffer is full
-- the buffer will be full with the next incoming byte, so the next
-- one can be processed regularely
StatexSN <= ST_RUN;
end if;
when ST_RUN =>
ShiftLookAheadxSN <= StrobexSI;
Strobe0xSN <= StrobexSI; -- pass on strobe to pipeline
WrHistBufxS <= StrobexSI;
DataIn0xDN <= DataInxDI;
if FlushBufxSI = '1' then
StatexSN <= ST_DRAIN_LOOK_AHEAD;
end if;
when ST_DRAIN_LOOK_AHEAD =>
-- create a strobe every second cycle
if LookAheadLenxDP > 0 and Strobe0xSP = '0' then
ShiftLookAheadxSN <= '1';
Strobe0xSN <= '1';
end if;
if LookAheadLenxDP = 0 then
EndOfData0xSN <= '1';
StatexSN <= ST_DONE;
end if;
when ST_DONE => null;
when others => StatexSN <= ST_DONE; -- fail save, just block
end case;
if OutFIFOLengthxD > OUT_FIFO_THR then
BusyxSN <= '1'; -- request stop of data input if output FIFO is full
end if;
end process;
-- we can accept data only every second clock cycle -> feed strobe back as
-- busy signal
BusyxSO <= BusyxSP or StrobexSI;
-- implement a shift register for the look ahead buffer
lookAheadProc : process (DataInxDI, ShiftLookAheadxSP, StatexSP, StrobexSI,
lookAheadBufxDP, lookAheadLenxDP)
begin -- process lookAheadProc
lookAheadLenxDN <= lookAheadLenxDP;
if StrobexSI = '1' then
-- load new data into MSB
--lookAheadBufxDN(LOOK_AHEAD_LEN-1) <= DataInxDI;
-- increase length counter if it is below the top
if lookAheadLenxDP < LOOK_AHEAD_LEN then
lookAheadLenxDN <= lookAheadLenxDP + 1;
end if;
end if;
if ShiftLookAheadxSP = '1' then
-- decrease buffer length counter if there is no valid input data
if lookAheadLenxDP > 0 and StrobexSI = '0' and StatexSP /= ST_FILL_LOOK_AHEAD then
lookAheadLenxDN <= lookAheadLenxDP - 1;
end if;
end if;
end process lookAheadProc;
-- implement actual shift register
lookAheadShiftReg : for i in 0 to LOOK_AHEAD_LEN-2 generate
process (DataInxDI, LookAheadLenxDP, ShiftLookAheadxSP, StrobexSI,
lookAheadBufxDP)
begin -- process
lookAheadBufxDN(i) <= lookAheadBufxDP(i); -- default: do nothing
if ShiftLookAheadxSP = '1' then
lookAheadBufxDN(i) <= lookAheadBufxDP(i+1); -- shift done one entry
elsif LookAheadLenxDP = i and StrobexSI = '1' then
lookAheadBufxDN(i) <= DataInxDI; -- load new byte into shift register
end if;
end process;
end generate lookAheadShiftReg;
-- implement the top most byte of the shift register
lookAheadBufxDN(LOOK_AHEAD_LEN-1) <= DataInxDI when lookAheadLenxDP >= LOOK_AHEAD_LEN-1 and StrobexSI = '1' else lookAheadBufxDP(LOOK_AHEAD_LEN-1);
HashTableInst : HashTable
generic map (
entryBitWidth => 12)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
NewEntryxDI => LookAheadPtr0xD,
EnWrxSI => Strobe0xSP, -- delay write by one cycle because we have to read first
Key0xDI => lookAheadBufxDP(0),
Key1xDI => lookAheadBufxDP(1),
Key2xDI => lookAheadBufxDP(2),
OldEntryxDO => HashTableEntryxD);
historyBufferInst : historyBuffer
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
WriteInxDI => DataInxDI,
WExSI => WrHistBufxS,
NextWrAdrxDO => NextWrAdrxD,
RExSI => Strobe0xSP, -- delay read by one cycle (we write first)
ReadBackAdrxDI => HashTableEntryxD(11 downto 2),
ReadBackxDO => HistBufOutxD,
ReadBackDonexSO => open);
-- calculate a pointer to the beginning of the look ahead section in the
-- history buffer
process (LookAheadLenxDP, NextWrAdrxD)
begin -- process
if LookAheadLenxDP <= to_integer(unsigned(NextWrAdrxD)) then
-- this is the regular case, write index is bigger than look ahead len ->
-- no wrap around in buffer
LookAheadPtr0xD <= std_logic_vector(to_unsigned(to_integer(unsigned(NextWrAdrxD))-LookAheadLenxDP, 12));
else
-- wrap around -> add history buffer length to get a pos value
LookAheadPtr0xD <= std_logic_vector(to_unsigned(HIST_BUF_LEN + to_integer(unsigned(NextWrAdrxD)) - LookAheadLenxDP, 12));
end if;
end process;
-- count the number of bytes in the history buffer. Note that we only count
-- the _history_ so only bytes which have already been processed.
process (HistBufLen0xDP, Strobe0xSP)
begin
HistBufLen0xDN <= HistBufLen0xDP;
-- count the number of processed bytes
if Strobe0xSP = '1' then
if HistBufLen0xDP < HIST_BUF_LEN - LOOK_AHEAD_LEN then
HistBufLen0xDN <= HistBufLen0xDP + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- pipeline stage 1
--
-- wait for data from histroy buffer
-----------------------------------------------------------------------------
process (CandAddr1xDP, HashTableEntryxD, HistBufLen0xDP, HistBufLen1xDP,
LookAheadBuf1xDP, LookAheadLen1xDP, LookAheadPtr0xD,
LookAheadPtr1xDP, Strobe0xSP, lookAheadBufxDP, lookAheadLenxDP)
begin
LookAheadLen1xDN <= LookAheadLen1xDP;
LookAheadBuf1xDN <= LookAheadBuf1xDP;
LookAheadPtr1xDN <= LookAheadPtr1xDP;
HistBufLen1xDN <= HistBufLen1xDP;
CandAddr1xDN <= CandAddr1xDP;
if Strobe0xSP = '1' then
LookAheadLen1xDN <= lookAheadLenxDP;
LookAheadBuf1xDN <= lookAheadBufxDP;
CandAddr1xDN <= HashTableEntryxD;
LookAheadPtr1xDN <= LookAheadPtr0xD;
HistBufLen1xDN <= HistBufLen0xDP;
end if;
end process;
-- signals to be passed on
Strobe1xSN <= Strobe0xSP;
EndOfData1xSN <= EndOfData0xSP;
-----------------------------------------------------------------------------
-- pipeline stage 2
--
-- shift history buffer output
-----------------------------------------------------------------------------
-- limit the max candidate length
MaxCandLenxD <= LOOK_AHEAD_LEN;
-- use a shifter to implement the last two bytes of the address
process (CandAddr1xDP, CandAddr2xDP, CandLen2xDP, Candidate2xDP,
HistBufLen1xDP, HistBufLen2xDP, HistBufOutxD, LookAheadBuf1xDP,
LookAheadBuf2xDP, LookAheadLen1xDP, LookAheadLen2xDP,
LookAheadPtr1xDP, LookAheadPtr2xDP, MaxCandLenxD, Strobe1xSP)
begin
Candidate2xDN <= Candidate2xDP;
LookAheadBuf2xDN <= LookAheadBuf2xDP;
LookAheadLen2xDN <= LookAheadLen2xDP;
CandAddr2xDN <= CandAddr2xDP;
LookAheadPtr2xDN <= LookAheadPtr2xDP;
HistBufLen2xDN <= HistBufLen2xDP;
CandLen2xDN <= CandLen2xDP;
-- send data through pipeline when strobe is high
if Strobe1xSP = '1' then
-- note: the history buffer can't load data only from addresses where the
-- last two bits are zero. If this was not the case we shift the candidate
-- (which makes it shorter) to correct that
case CandAddr1xDP(1 downto 0) is
when "00" => Candidate2xDN <= HistBufOutxD; -- no shifting
CandLen2xDN <= MaxCandLenxD;
when "01" => Candidate2xDN <= x"00" & HistBufOutxD(LOOK_AHEAD_LEN*8-1 downto 8); -- shift one byte
CandLen2xDN <= MaxCandLenxD-1; -- we shifted one byte out -> candidate is one byte shorter
when "10" => Candidate2xDN <= x"0000" & HistBufOutxD(LOOK_AHEAD_LEN*8-1 downto 16); -- shift 2 bytes
CandLen2xDN <= MaxCandLenxD-2;
when "11" => Candidate2xDN <= x"000000" & HistBufOutxD(LOOK_AHEAD_LEN*8-1 downto 24); -- shift 3 bytes
CandLen2xDN <= MaxCandLenxD-3;
when others => null;
end case;
LookAheadBuf2xDN <= LookAheadBuf1xDP;
LookAheadLen2xDN <= LookAheadLen1xDP;
CandAddr2xDN <= CandAddr1xDP;
-- NextWrAdr2xDN <= NextWrAdr1xDP;
LookAheadPtr2xDN <= LookAheadPtr1xDP;
HistBufLen2xDN <= HistBufLen1xDP;
end if;
end process;
-- signals to be passed on to next stage
HashTableEntry2xDN <= HashTableEntryxD;
Strobe2xSN <= Strobe1xSP;
EndOfData2xSN <= EndOfData1xSP;
-------------------------------------------------------------------------------
-- Pipeline Stage 3
--
-- Comparator, Offset Calculation and Data Output
-------------------------------------------------------------------------------
-- reformat two dimensional look ahead buffer into one dimensional array
-- not nice, I know. We should have a package defining proper types and use
-- them consistently...
arrayReformatter : for i in 0 to LOOK_AHEAD_LEN-1 generate
CompLAIn3xD((i+1)*8-1 downto i*8) <= LookAheadBuf2xDP(i);
end generate arrayReformatter;
comparatorInst : comparator
port map (
LookAheadxDI => CompLAIn3xD,
LookAheadLenxDI => LookAheadLen2xDP,
CandidatexDI => Candidate2xDP,
CandidateLenxDI => CandLen2xDP,
MatchLenxDO => MatchLenxD);
-- calculate the offset
process (CandAddr2xDP, LookAheadPtr2xDP, OffsetIntxD)
begin
OffsetIntxD <= -1; -- default: illegal offset
if to_integer(unsigned(LookAheadPtr2xDP)) > to_integer(unsigned(CandAddr2xDP)) then
-- this is the regular case, the candidate address is smaller (ie in the
-- past) than the byte to be encoded (which is at index given by lookAheadPtr)
OffsetIntxD <= to_integer(unsigned(LookAheadPtr2xDP)) - to_integer(unsigned(CandAddr2xDP)) - 1;
elsif to_integer(unsigned(LookAheadPtr2xDP)) < to_integer(unsigned(CandAddr2xDP)) then
-- there is a buffer wrap around between the two pointers, the offset
-- would be negative -> add buffer length
OffsetIntxD <= HIST_BUF_LEN + to_integer(unsigned(LookAheadPtr2xDP)) - to_integer(unsigned(CandAddr2xDP)) - 1;
else
-- this means that the candidate and the history buffer (byte to be
-- encoded) are on the same location. This is invalid as the candidate can't be
-- in the future -> create an illeagal negative offset to invalidate this match
OffsetIntxD <= -1;
end if;
OffsetxD <= std_logic_vector(to_unsigned(OffsetIntxD, 12));
end process;
Done3xSN <= EncDonexS and FifoBuffersEmptyxS;
-- note: the offset can't be longer than the history buffer length
-- if the offset is too long we disable the match by setting the length to 0
-- we also check for illegal negative offsets
MatchLenLimitedxD <= MatchLenxD when OffsetIntxD < (HistBufLen2xDP) and OffsetIntxD >= 0 else 0;
outputEncoderInst : outputEncoder
generic map (
frameSize => 8,
minMatchLen => 3,
maxMatchLen => LOOK_AHEAD_LEN)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
OffsetxDI => OffsetxD,
MatchLengthxDI => MatchLenLimitedxD,
EnxSI => Strobe2xSP,
EndOfDataxSI => EndOfData2xSP,
LiteralxDI => LookAheadBuf2xDP(0),
BodyStrobexSO => BodyStrobexS,
BodyOutxDO => BodyDataxD,
HeaderStrobexSO => HeaderStrobexS,
HeaderOutxDO => HeaderDataxD,
DonexSO => EncDonexS);
outputFIFOInst : outputFIFO
generic map (
frameSize => 8) -- number of elements (pairs or literals) per frame
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
BodyDataxDI => BodyDataxD,
BodyStrobexSI => BodyStrobexS,
HeaderDataxDI => HeaderDataxD,
HeaderStrobexSI => HeaderStrobexS,
BuffersEmptyxSO => FifoBuffersEmptyxS,
BufOutxDO => BufOutxDO,
OutputValidxSO => OutputValidxSO,
RdStrobexSI => RdStrobexSI,
LengthxDO => OutFIFOLengthxD);
LengthxDO <= OutFIFOLengthxD;
DonexSO <= Done3xSP;
-----------------------------------------------------------------------------
-- GENERAL STUFF
-----------------------------------------------------------------------------
registers : process (ClkxCI)
begin -- process registers
if ClkxCI'event and ClkxCI = '1' then
if RstxRI = '1' then
StatexSP <= ST_FILL_LOOK_AHEAD;
BusyxSP <= '0';
ShiftLookAheadxSP <= '0';
lookAheadLenxDP <= 0;
Strobe0xSP <= '0';
LookAheadLen1xDP <= 0;
Strobe1xSP <= '0';
WrAdr1xDP <= (others => '0');
LookAheadLen2xDP <= 0;
Strobe2xSP <= '0';
HistBufLen0xDP <= 0;
EndOfData0xSP <= '0';
EndOfData1xSP <= '0';
EndOfData2xSP <= '0';
Done3xSP <= '0';
else
StatexSP <= StatexSN;
BusyxSP <= BusyxSN;
ShiftLookAheadxSP <= ShiftLookAheadxSN;
lookAheadLenxDP <= lookAheadLenxDN;
lookAheadBufxDP <= lookAheadBufxDN;
Strobe0xSP <= Strobe0xSN;
HistBufLen0xDP <= HistBufLen0xDN;
DataIn0xDP <= DataIn0xDN;
lookAheadLen1xDP <= lookAheadLen1xDN;
Strobe1xSP <= Strobe1xSN;
HistBufLen1xDP <= HistBufLen1xDN;
WrAdr1xDP <= WrAdr1xDN;
LookAheadPtr1xDP <= LookAheadPtr1xDN;
LookAheadBuf1xDP <= LookAheadBuf1xDN;
LookAheadLen2xDP <= LookAheadLen2xDN;
LookAheadBuf2xDP <= LookAheadBuf2xDN;
CandAddr1xDP <= CandAddr1xDN;
Strobe2xSP <= Strobe2xSN;
HistBufLen2xDP <= HistBufLen2xDN;
NextWrAdr2xDP <= NextWrAdr2xDN;
LookAheadPtr2xDP <= LookAheadPtr2xDN;
CandAddr2xDP <= CandAddr2xDN;
Candidate2xDP <= Candidate2xDN;
CandLen2xDP <= CandLen2xDN;
HashTableEntry2xDP <= HashTableEntry2xDN;
EndOfData0xSP <= EndOfData0xSN;
EndOfData1xSP <= EndOfData1xSN;
EndOfData2xSP <= EndOfData2xSN;
Done3xSP <= Done3xSN;
end if;
end if;
end process registers;
end Behavioral;
|
gpl-2.0
|
e04042d69c5814c2a481abca87b9b7e6
| 0.571099 | 4.474399 | false | false | false | false |
Dasio/FIT-Projects
|
INC/fsm.vhd
| 1 | 10,689 |
-- fsm.vhd: Finite State Machine
-- Author(s): David Mikus([email protected])
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity fsm is
port(
CLK : in std_logic;
RESET : in std_logic;
-- Input signals
KEY : in std_logic_vector(15 downto 0);
CNT_OF : in std_logic;
-- Output signals
FSM_CNT_CE : out std_logic;
FSM_MX_MEM : out std_logic;
FSM_MX_LCD : out std_logic;
FSM_LCD_WR : out std_logic;
FSM_LCD_CLR : out std_logic
);
end entity fsm;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of fsm is
type t_state is (TEST,TEST1_1,TEST1_2,TEST1_3,TEST1_4,TEST1_5,TEST1_6,TEST1_7,TEST1_8,TEST1_9,
TEST2_1,TEST2_2,TEST2_3,TEST2_4,TEST2_5,TEST2_6,TEST2_7,TEST2_8,TEST2_9,TEST2_10,PRINT_MESSAGE_OK,PRINT_MESSAGE_FAIL, FINISH_OK,FINISH_FAIL,FINISH);
signal present_state, next_state : t_state;
begin
-- -------------------------------------------------------
sync_logic : process(RESET, CLK)
begin
if (RESET = '1') then
present_state <= TEST;
elsif (CLK'event AND CLK = '1') then
present_state <= next_state;
end if;
end process sync_logic;
-- -------------------------------------------------------
next_state_logic : process(present_state, KEY, CNT_OF)
begin
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST =>
next_state <= TEST;
if (KEY(8) = '1') then
next_state <= TEST1_1;
elsif (KEY(1) = '1') then
next_state <= TEST2_1;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_1 =>
next_state <= TEST1_1;
if (KEY(4) = '1') then
next_state <= TEST1_2;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_2 =>
next_state <= TEST1_2;
if (KEY(3) = '1') then
next_state <= TEST1_3;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_3 =>
next_state <= TEST1_3;
if (KEY(2) = '1') then
next_state <= TEST1_4;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_4 =>
next_state <= TEST1_4;
if (KEY(1) = '1') then
next_state <= TEST1_5;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_5 =>
next_state <= TEST1_5;
if (KEY(5) = '1') then
next_state <= TEST1_6;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_6 =>
next_state <= TEST1_6;
if (KEY(7) = '1') then
next_state <= TEST1_7;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_7 =>
next_state <= TEST1_7;
if (KEY(5) = '1') then
next_state <= TEST1_8;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST1_8 =>
next_state <= TEST1_8;
if (KEY(5) = '1') then
next_state <= FINISH_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_1 =>
next_state <= TEST2_1;
if (KEY(5) = '1') then
next_state <= TEST2_2;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_2 =>
next_state <= TEST2_2;
if (KEY(1) = '1') then
next_state <= TEST2_3;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_3 =>
next_state <= TEST2_3;
if (KEY(7) = '1') then
next_state <= TEST2_4;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_4 =>
next_state <= TEST2_4;
if (KEY(7) = '1') then
next_state <= TEST2_5;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_5 =>
next_state <= TEST2_5;
if (KEY(8) = '1') then
next_state <= TEST2_6;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_6 =>
next_state <= TEST2_6;
if (KEY(8) = '1') then
next_state <= TEST2_7;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_7 =>
next_state <= TEST2_7;
if (KEY(3) = '1') then
next_state <= TEST2_8;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_8 =>
next_state <= TEST2_8;
if (KEY(6) = '1') then
next_state <= TEST2_9;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_9 =>
next_state <= TEST2_9;
if (KEY(0) = '1') then
next_state <= TEST2_10;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST2_10 =>
next_state <= TEST2_10;
if (KEY(0) = '1') then
next_state <= FINISH_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
elsif (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_MESSAGE_OK =>
next_state <= PRINT_MESSAGE_OK;
if (CNT_OF = '1') then
next_state <= FINISH;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_MESSAGE_FAIL =>
next_state <= PRINT_MESSAGE_FAIL;
if (CNT_OF = '1') then
next_state <= FINISH;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH_OK =>
next_state <= FINISH_OK;
if (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= FINISH_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH_FAIL =>
next_state <= FINISH_FAIL;
if (KEY(15) = '1') then
next_state <= PRINT_MESSAGE_FAIL;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH =>
next_state <= FINISH;
if (KEY(15) = '1') then
next_state <= TEST;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
next_state <= TEST;
end case;
end process next_state_logic;
-- -------------------------------------------------------
output_logic : process(present_state, KEY)
begin
FSM_CNT_CE <= '0';
FSM_MX_MEM <= '0';
FSM_MX_LCD <= '0';
FSM_LCD_WR <= '0';
FSM_LCD_CLR <= '0';
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when TEST | TEST1_1 | TEST1_2 | TEST1_3 | TEST1_4 | TEST1_5 | TEST1_6 | TEST1_7 | TEST1_8 | TEST1_9 | TEST2_1 | TEST2_2 | TEST2_3 | TEST2_4 | TEST2_5 | TEST2_6 | TEST2_7| TEST2_8 | TEST2_9 | TEST2_10 | FINISH_OK | FINISH_FAIL =>
if (KEY(14 downto 0) /= "000000000000000") then
FSM_LCD_WR <= '1';
end if;
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
when PRINT_MESSAGE_OK =>
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
FSM_MX_MEM <= '1';
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_MESSAGE_FAIL =>
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
FSM_MX_MEM <= '0';
-- - - - - - - - - - - - - - - - - - - - - - -
when FINISH =>
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
end case;
end process output_logic;
end architecture behavioral;
|
mit
|
c6428dd95bbc9d387b9c41901f8a19a4
| 0.432968 | 3.071552 | false | true | false | false |
rmilfont/Phoenix
|
inputModule.vhd
| 1 | 6,768 |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
use work.PhoenixPackage.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
entity inputModule is
generic(
address: regflit
);
port(
done: out std_logic;
data: out regflit;
enable: in std_logic;
currentTime: in std_logic_vector(4*TAM_FLIT-1 downto 0)
);
end;
architecture inputModule of inputModule is
function string_to_int(x_str : string; radix : positive range 2 to 36 := 10) return integer is
constant STR_LEN : integer := x_str'length;
variable chr_val : integer;
variable ret_int : integer := 0;
variable do_mult : boolean := true;
variable power : integer := 0;
begin
for i in STR_LEN downto 1 loop
case x_str(i) is
when '0' => chr_val := 0;
when '1' => chr_val := 1;
when '2' => chr_val := 2;
when '3' => chr_val := 3;
when '4' => chr_val := 4;
when '5' => chr_val := 5;
when '6' => chr_val := 6;
when '7' => chr_val := 7;
when '8' => chr_val := 8;
when '9' => chr_val := 9;
when 'A' | 'a' => chr_val := 10;
when 'B' | 'b' => chr_val := 11;
when 'C' | 'c' => chr_val := 12;
when 'D' | 'd' => chr_val := 13;
when 'E' | 'e' => chr_val := 14;
when 'F' | 'f' => chr_val := 15;
when others => report "Illegal character for conversion for string to integer" severity failure;
end case;
if chr_val >= radix then report "Illagel character at this radix" severity failure; end if;
if do_mult then
ret_int := ret_int + (chr_val * (radix**power));
end if;
power := power + 1;
end loop;
return ret_int;
end function;
begin
process
file file_pointer: text;
variable line_num : line;
variable tmp_word: string (1 to 500);
variable tmp_line: line;
variable line_counter: integer := 0;
variable char_pointer: integer;
variable char_pointer_tmp: integer;
variable pkt_time: integer := 0;
variable str_size: integer;
variable flit_counter: integer;
variable timestampNet: std_logic_vector(4*TAM_FLIT-1 downto 0) := (others=>'0');
variable pkt_size: regflit;
variable control_pkt: std_logic;
--variable fault_bits: regphit;
begin
file_open(file_pointer,"In/in"&to_hstring(address)&".txt",READ_MODE);
while not endfile(file_pointer) loop
-- limpa a string tmp_word
for j in 1 to tmp_word'length loop
tmp_word(j) := NUL;
end loop;
readline(file_pointer,line_num);
line_counter := line_counter + 1;
char_pointer := line_num'low;
str_size := 0;
-- copia a string da linha lida ate encontrar espaco (ira copiar o tempo do inicio do pacote)
while (line_num(char_pointer) /= ' ' and char_pointer <= line_num'high) loop
tmp_word(char_pointer) := line_num(char_pointer);
char_pointer := char_pointer + 1;
str_size := str_size + 1;
end loop;
-- converte string lida (tempo do inicio do pacote) para integer
pkt_time := string_to_int(tmp_word(1 to str_size),16);
done <= '0';
data <= (others=>'0');
-- loop esperando ate' tempo para injetar o pacote
while not (currentTime >= pkt_time) loop
wait for 1 ns;
end loop;
-- limpa a string tmp_word
for j in 1 to tmp_word'length loop
tmp_word(j) := NUL;
end loop;
char_pointer := char_pointer + 1;
char_pointer_tmp := 1;
-- copia a string da linha lida
while (char_pointer_tmp <= line_num'high) loop
tmp_word(char_pointer_tmp) := line_num(char_pointer_tmp);
char_pointer_tmp := char_pointer_tmp + 1;
end loop;
flit_counter := 0;
control_pkt := '0';
-- leitura da linha e injetado os flits lidos
while (char_pointer < line_num'high) loop
if (enable='1' and tmp_word(char_pointer) /= NUL) then
done <= '1';
if (flit_counter = 0) then -- captura o timestamp de entrada na rede
timestampNet := currentTime;
end if;
if (flit_counter = 1 and control_pkt='0') then
pkt_size := CONV_VECTOR(tmp_word, char_pointer) &
CONV_VECTOR(tmp_word, char_pointer + 1) &
CONV_VECTOR(tmp_word, char_pointer + 2) &
CONV_VECTOR(tmp_word, char_pointer + 3);
pkt_size := pkt_size + 4; -- reservar +4 espacos para o timestamp de entrada na rede
data <= pkt_size;
char_pointer := char_pointer + 5;
elsif (flit_counter>=9 and flit_counter<=12 and control_pkt='0') then
data <= timestampNet(((13-flit_counter)*TAM_FLIT-1) downto ((12-flit_counter)*TAM_FLIT));
else
data <= CONV_VECTOR(tmp_word, char_pointer) &
CONV_VECTOR(tmp_word, char_pointer + 1) &
CONV_VECTOR(tmp_word, char_pointer + 2) &
CONV_VECTOR(tmp_word, char_pointer + 3);
if (flit_counter = 0) then
control_pkt := CONV_VECTOR(tmp_word, char_pointer)(TAM_FLIT/4-1);
end if;
char_pointer := char_pointer + 5;
end if;
flit_counter := flit_counter + 1;
else
done <= '0';
data <= (others=>'0');
if (tmp_word(char_pointer) = NUL) then
exit;
end if;
end if;
wait for 20 ns; -- clock period
end loop;
-- fim da linha lida do arquivo e fim da injecao do pacote
done <= '0';
data <= (others=>'0');
end loop;
wait;
end process;
end inputModule;
|
lgpl-3.0
|
adbe5eb0fa9aa1cc4da641f6554370c8
| 0.478723 | 4.040597 | false | false | false | false |
ktemkin/ruby-adept
|
firmware/epp_stream/tests/fifo_testbench.vhdl
| 1 | 5,346 |
----------------------------------------------------------------------------------
-- Simple Synchronous FIFO
--
-- Author: Kyle J. Temkin, <[email protected]>
-- Copyright (c) Kyle J. Temkin, 2013 Binghamton University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.-
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_testbench is
end fifo_testbench;
architecture behavior of fifo_testbench is
-- component declaration for the unit under test (uut)
component fifo
generic(
count_bits : integer;
element_width : integer
);
port(
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
count : out std_logic_vector(4 downto 0);
enqueue : in std_logic;
dequeue : in std_logic;
empty : out std_logic;
full : out std_logic
);
end component;
--
-- Convenience function which waits until juster the rising edge.
--
procedure wait_until_after_rising_edge(signal clk : in std_logic) is
begin
wait until rising_edge(clk);
wait for 1 ps;
end procedure wait_until_after_rising_edge;
--inputs
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal enqueue : std_logic := '0';
signal dequeue : std_logic := '0';
--outputs
signal data_out : std_logic_vector(7 downto 0);
signal count : std_logic_vector(4 downto 0);
signal empty : std_logic;
signal full : std_logic;
-- clock period definitions
constant clk_period : time := 10 ns;
constant delta_delay : time := 1 ps;
begin
-- instantiate the unit under test (uut)
uut: fifo
generic map(
count_bits => 5,
element_width => 8
)
port map (
clk => clk,
reset => reset,
data_in => data_in,
data_out => data_out,
count => count,
enqueue => enqueue,
dequeue => dequeue,
empty => empty,
full => full
);
--Generate the system clock.
clk <= not clk after clk_period / 2;
-- stimulus process
stim_proc: process
begin
-- assert reset for 100ns;
wait for 100 ns;
reset <= '0';
--Assert conditions after reset.
assert data_out = x"00" report "Data_out should be zero after clear.";
assert count = "00000" report "Count should be zero after clear.";
assert empty = '1' report "Empty should be one after clear.";
--Add 31 elements to the FIFO.
enqueue <= '1';
dequeue <= '0';
for i in 1 to 31 loop
--Ensure that we're counting the values properly.
assert count = std_logic_vector(to_unsigned(i - 1, 5)) report "Count should be equal to the amount of elements enqueued.";
--Set up the FIFO to add a new, numbered element.
data_in <= std_logic_vector(to_unsigned(i, 8));
--Wait until just after the next rising-edge of the clock.
wait_until_after_rising_edge(clk);
--Check to see that our enqueue is behaving properly.
assert empty = '0' report "Empty should not be one while there are elements in the FIFO.";
assert data_out = x"01" report "Data out should show the first element enqueued until a dequeue is performed.";
end loop;
--Check to see that the FIFO is full.
assert full = '1' report "After adding 31 elements to the FIFO, it should be full.";
--Verify that we can perform simultaneous read/writes, even when the FIFO is full.
enqueue <= '1';
dequeue <= '1';
data_in <= x"20";
wait_until_after_rising_edge(clk);
--Check to ensure that the simultaneous enqueue/dequeue does not affect the count.
assert data_out = x"02" report "After a dequeue, the next value in the FIFO should be exposed.";
assert count = "11111" report "A simultaneous enqueue/dequeue should not affect the count.";
--Remove each of the elements from the FIFO.
enqueue <= '0';
dequeue <= '1';
for i in 2 to 32 loop
assert data_out = std_logic_vector(to_unsigned(i, 8)) report "Elements should be dequeued in the same ordered they were entered.";
assert count = std_logic_vector(to_unsigned(33 - i, 5)) report "Count should decrease as elements are dequeued.";
wait_until_after_rising_edge(clk);
end loop;
--Check to ensure that the FIFO is empty after all elements have been dequeued.
assert count = "00000" report "After all elements are dequeued, the count should be zero.";
assert empty = '1' report "After all elements are dequeued, the queue should be empty.";
report "Test complete.";
wait;
end process;
end;
|
mit
|
798f145ebdd5237ce2cb8f6bf3d128ec
| 0.641975 | 3.916484 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_1_0/sim/DemoInterconnect_internoc_ni_axi_master_1_0.vhd
| 2 | 10,681 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_internoc_ni_axi_master_1_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_1_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_1_0_arch OF DemoInterconnect_internoc_ni_axi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_1_0_arch;
|
mit
|
e65bc0e55025673aa861684e07086340
| 0.705458 | 3.188358 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/PIPO_TB.vhd
| 1 | 1,115 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PIPO_TB IS
END PIPO_TB;
ARCHITECTURE behavior OF PIPO_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PIPO
PORT(
D : IN std_logic_vector(3 downto 0);
Q : OUT std_logic_vector(3 downto 0);
CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(3 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal Q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PIPO PORT MAP (
D => D,
Q => Q,
CLK => CLK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
D <= "1011";
wait for 20 ns;
D <= "0000";
wait;
end process;
END;
|
gpl-3.0
|
6b5c631b5a97a00335040fadf17b033a
| 0.561435 | 3.484375 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_jtag_axi_0_0/synth/DemoInterconnect_jtag_axi_0_0.vhd
| 1 | 14,174 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:jtag_axi:1.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY jtag_axi;
USE jtag_axi.jtag_axi_v1_2_4_jtag_axi;
ENTITY DemoInterconnect_jtag_axi_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC;
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC;
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC
);
END DemoInterconnect_jtag_axi_0_0;
ARCHITECTURE DemoInterconnect_jtag_axi_0_0_arch OF DemoInterconnect_jtag_axi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_jtag_axi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT jtag_axi_v1_2_4_jtag_axi IS
GENERIC (
RD_TXN_QUEUE_LENGTH : INTEGER;
WR_TXN_QUEUE_LENGTH : INTEGER;
M_AXI_ID_WIDTH : INTEGER;
M_AXI_ADDR_WIDTH : INTEGER;
FAMILY : STRING;
M_AXI_DATA_WIDTH : INTEGER;
M_HAS_BURST : INTEGER;
PROTOCOL : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC;
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC;
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC
);
END COMPONENT jtag_axi_v1_2_4_jtag_axi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_jtag_axi_0_0_arch: ARCHITECTURE IS "jtag_axi_v1_2_4_jtag_axi,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_jtag_axi_0_0_arch : ARCHITECTURE IS "DemoInterconnect_jtag_axi_0_0,jtag_axi_v1_2_4_jtag_axi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_jtag_axi_0_0_arch: ARCHITECTURE IS "DemoInterconnect_jtag_axi_0_0,jtag_axi_v1_2_4_jtag_axi,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=jtag_axi,x_ipVersion=1.2,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RD_TXN_QUEUE_LENGTH=1,WR_TXN_QUEUE_LENGTH=1,M_AXI_ID_WIDTH=1,M_AXI_ADDR_WIDTH=32,FAMILY=artix7,M_AXI_DATA_WIDTH=32,M_HAS_BURST=1,PROTOCOL=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awqos: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_awid: SIGNAL IS "XIL_INTERFACENAME M_AXI, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, BUSER_WIDTH 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 72000000, ID_WIDTH 1, ADDR_WIDTH 32, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
BEGIN
U0 : jtag_axi_v1_2_4_jtag_axi
GENERIC MAP (
RD_TXN_QUEUE_LENGTH => 1,
WR_TXN_QUEUE_LENGTH => 1,
M_AXI_ID_WIDTH => 1,
M_AXI_ADDR_WIDTH => 32,
FAMILY => "artix7",
M_AXI_DATA_WIDTH => 32,
M_HAS_BURST => 1,
PROTOCOL => 0
)
PORT MAP (
aclk => aclk,
aresetn => aresetn,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
END DemoInterconnect_jtag_axi_0_0_arch;
|
mit
|
c5234be5d179ae9f0a191af7551ea6fe
| 0.696275 | 3.179453 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/hdl/axi_spi_master_v1_0.vhd
| 3 | 4,388 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0 is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
m_spi_mosi : out std_logic;
m_spi_miso : in std_logic;
m_spi_ss : out std_logic;
m_spi_sclk : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_spi_master_v1_0;
architecture arch_imp of axi_spi_master_v1_0 is
-- component declaration
component axi_spi_master_v1_0_S00_AXI is
generic (
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
spi_mosi : out std_logic;
spi_miso : in std_logic;
spi_ss : out std_logic;
spi_sclk : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_spi_master_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_spi_master_v1_0_S00_AXI_inst : axi_spi_master_v1_0_S00_AXI
generic map (
SPI_DATA_WIDTH => SPI_DATA_WIDTH,
SPI_CLK_DIV => SPI_CLK_DIV,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
spi_mosi => m_spi_mosi,
spi_miso => m_spi_miso,
spi_ss => m_spi_ss,
spi_sclk => m_spi_sclk,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
f3fdfccdf1f73f26fca22fc0488228de
| 0.644029 | 2.437778 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica6/testControl.vhd
| 1 | 3,672 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:35:23 10/23/2011
-- Design Name:
-- Module Name: C:/Users/cvargasc/Desktop/practica6new/practica6new/testControl.vhd
-- Project Name: practica6new
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testControl IS
END testControl;
ARCHITECTURE behavior OF testControl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control
PORT(
reset : in std_logic;
clock : in std_logic;
est0 : in STD_LOGIC;
est1 : in STD_LOGIC;
est2 : in STD_LOGIC;
est3 : in STD_LOGIC;
est4 : in STD_LOGIC;
est5 : in STD_LOGIC;
est6 : in STD_LOGIC;
est7 : in STD_LOGIC;
motor0 : out STD_LOGIC;
motor1 : out STD_LOGIC;
motor2 : out STD_LOGIC;
motor3 : out STD_LOGIC;
parlante : out std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '1';
signal clock : std_logic := '1';
signal est0 : std_logic := '1';
signal est1 : std_logic := '1';
signal est2 : std_logic := '1';
signal est3 : std_logic := '1';
signal est4 : std_logic := '1';
signal est5 : std_logic := '1';
signal est6 : std_logic := '1';
signal est7 : std_logic := '1';
--Outputs
signal motor0 : std_logic;
signal motor1 : std_logic;
signal motor2 : std_logic;
signal motor3 : std_logic;
signal parlante : std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control PORT MAP (
reset => reset,
clock => clock,
est0 => est0,
est1 => est1,
est2 => est2,
est3 => est3,
est4 => est4,
est5 => est5,
est6 => est6,
est7 => est7,
motor0 => motor0,
motor1 => motor1,
motor2 => motor2,
motor3 => motor3,
parlante => parlante
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clock_period*10;
reset <= '1';
est3 <= '0';
wait for clock_period*5;
est3 <= '1';
wait for clock_period*10;
est2 <= '0';
wait for clock_period*5;
est2 <= '1';
wait for clock_period*20;
est2 <= '0';
wait for clock_period*5;
est2 <= '1';
-- est3 <= '1';
-- wait for clock_period*5;
-- est3 <= '0';
-- wait for clock_period*5;
-- est7 <= '1';
-- wait for clock_period*5;
-- est7 <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
8b3a3a225e2ac06a260159b98ffc79df
| 0.555556 | 3.114504 | false | true | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica6/control.vhd
| 1 | 6,027 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:32:36 10/23/2011
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
est0 : in STD_LOGIC;
est1 : in STD_LOGIC;
est2 : in STD_LOGIC;
est3 : in STD_LOGIC;
est4 : in STD_LOGIC;
est5 : in STD_LOGIC;
est6 : in STD_LOGIC;
est7 : in STD_LOGIC;
motor0 : out STD_LOGIC;
motor1 : out STD_LOGIC;
motor2 : out STD_LOGIC;
motor3 : out STD_LOGIC;
parlante : out STD_LOGIC
);
end control;
architecture Behavioral of control is
type estadosMotor is (p0,p1,p2,p3,p4,p5,p6,p7);
signal estadoMotor : estadosMotor;
signal contadorMotor : std_logic_vector(4 downto 0);
signal avance : std_logic;
signal cuantasEstaciones: std_logic_vector(2 downto 0);
signal derecha : std_logic;
signal estacionSensor : std_logic_vector(2 downto 0);
signal estacionActual : std_logic_vector(2 downto 0);
begin
-- Calculadora de estaciones
process(clock,reset,estacionActual,estacionSensor,derecha,cuantasEstaciones,contadorMotor)
begin
if (reset = '0') then
avance <= '0';
estacionActual <=(others=>'0');
cuantasEstaciones <=(others=>'0');
derecha <= '0';
elsif (clock'event and clock = '1') then
if (estacionActual = estacionSensor) then
--cuantasEstaciones <=(others=>'0');
avance <= '0';
else
if (cuantasEstaciones = 0) then
cuantasEstaciones <= estacionSensor - estacionActual;
if (estacionSensor - estacionActual > 4) then
derecha <= '0';
else
derecha <= '1';
end if;
avance <= '1';
elsif (contadorMotor = "0110") then --*** NUM PASOS ENTRE ESTACIONES 1 DE 2
if (derecha = '1') then
cuantasEstaciones <= cuantasEstaciones - 1;
estacionActual <= estacionActual + 1;
else
cuantasEstaciones <= cuantasEstaciones + 1;
estacionActual <= estacionActual - 1;
end if;
end if;
end if;
end if;
end process;
-- Sensor
process(clock,reset,estacionActual,estacionSensor,est0,est1,est2,est3,est4,est5,est6,est7)
begin
if (reset = '0') then
estacionSensor <= "000";
elsif (clock'event and clock = '1') then
if (estacionActual = estacionSensor) then
if (est0 = '0') then estacionSensor <= "000";
elsif (est1 = '0') then estacionSensor <= "001";
elsif (est2 = '0') then estacionSensor <= "010";
elsif (est3 = '0') then estacionSensor <= "011";
elsif (est4 = '0') then estacionSensor <= "100";
elsif (est5 = '0') then estacionSensor <= "101";
elsif (est6 = '0') then estacionSensor <= "110";
elsif (est7 = '0') then estacionSensor <= "111";
end if;
end if;
end if;
end process;
-- Maquina de estados
process(clock,reset,estadoMotor,contadorMotor,derecha,avance)
begin
if (reset = '0') then
estadoMotor <= p0;
contadorMotor <=(others=>'0');
parlante <= '0';
elsif (clock'event and clock = '1') then
if (avance = '0' or contadorMotor = "0110") then --*** NUM PASOS ENTRE ESTACIONES 2 DE 2
contadorMotor <=(others=>'0');
parlante <= '0';
else
parlante <= '1';
contadorMotor <= contadorMotor + 1;
if (derecha = '1') then
case estadoMotor is
when p0 =>
estadoMotor <= p1;
when p1 =>
estadoMotor <= p2;
when p2 =>
estadoMotor <= p3;
when p3 =>
estadoMotor <= p4;
when p4 =>
estadoMotor <= p5;
when p5 =>
estadoMotor <= p6;
when p6 =>
estadoMotor <= p7;
when p7 =>
estadoMotor <= p0;
end case;
else
case estadoMotor is
when p0 =>
estadoMotor <= p7;
when p1 =>
estadoMotor <= p0;
when p2 =>
estadoMotor <= p1;
when p3 =>
estadoMotor <= p2;
when p4 =>
estadoMotor <= p3;
when p5 =>
estadoMotor <= p4;
when p6 =>
estadoMotor <= p5;
when p7 =>
estadoMotor <= p6;
end case;
end if;
end if;
end if;
end process;
-- Secuencia motor
process(reset,estadoMotor)
begin
if (reset = '0') then
motor0 <= '0';
motor1 <= '0';
motor2 <= '0';
motor3 <= '0';
else
case estadoMotor is
when p0 =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '0';
motor3 <= '1';
when p1 =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '1';
motor3 <= '1';
when p2 =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '1';
motor3 <= '0';
when p3 =>
motor0 <= '0';
motor1 <= '1';
motor2 <= '1';
motor3 <= '0';
when p4 =>
motor0 <= '0';
motor1 <= '1';
motor2 <= '0';
motor3 <= '0';
when p5 =>
motor0 <= '1';
motor1 <= '1';
motor2 <= '0';
motor3 <= '0';
when p6 =>
motor0 <= '1';
motor1 <= '0';
motor2 <= '0';
motor3 <= '0';
when p7 =>
motor0 <= '1';
motor1 <= '0';
motor2 <= '0';
motor3 <= '1';
when others =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '0';
motor3 <= '0';
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
defcad35ef698f461cad6a6c482b56a6
| 0.541397 | 3.119565 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_mutex_0_0/sim/DemoInterconnect_mutex_0_0.vhd
| 2 | 28,100 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mutex:2.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mutex_v2_1_8;
USE mutex_v2_1_8.mutex;
ENTITY DemoInterconnect_mutex_0_0 IS
PORT (
S0_AXI_ACLK : IN STD_LOGIC;
S0_AXI_ARESETN : IN STD_LOGIC;
S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_AWVALID : IN STD_LOGIC;
S0_AXI_AWREADY : OUT STD_LOGIC;
S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S0_AXI_WVALID : IN STD_LOGIC;
S0_AXI_WREADY : OUT STD_LOGIC;
S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_BVALID : OUT STD_LOGIC;
S0_AXI_BREADY : IN STD_LOGIC;
S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_ARVALID : IN STD_LOGIC;
S0_AXI_ARREADY : OUT STD_LOGIC;
S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_RVALID : OUT STD_LOGIC;
S0_AXI_RREADY : IN STD_LOGIC;
S1_AXI_ACLK : IN STD_LOGIC;
S1_AXI_ARESETN : IN STD_LOGIC;
S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_AWVALID : IN STD_LOGIC;
S1_AXI_AWREADY : OUT STD_LOGIC;
S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S1_AXI_WVALID : IN STD_LOGIC;
S1_AXI_WREADY : OUT STD_LOGIC;
S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_BVALID : OUT STD_LOGIC;
S1_AXI_BREADY : IN STD_LOGIC;
S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_ARVALID : IN STD_LOGIC;
S1_AXI_ARREADY : OUT STD_LOGIC;
S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_RVALID : OUT STD_LOGIC;
S1_AXI_RREADY : IN STD_LOGIC;
S2_AXI_ACLK : IN STD_LOGIC;
S2_AXI_ARESETN : IN STD_LOGIC;
S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_AWVALID : IN STD_LOGIC;
S2_AXI_AWREADY : OUT STD_LOGIC;
S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S2_AXI_WVALID : IN STD_LOGIC;
S2_AXI_WREADY : OUT STD_LOGIC;
S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_BVALID : OUT STD_LOGIC;
S2_AXI_BREADY : IN STD_LOGIC;
S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_ARVALID : IN STD_LOGIC;
S2_AXI_ARREADY : OUT STD_LOGIC;
S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_RVALID : OUT STD_LOGIC;
S2_AXI_RREADY : IN STD_LOGIC
);
END DemoInterconnect_mutex_0_0;
ARCHITECTURE DemoInterconnect_mutex_0_0_arch OF DemoInterconnect_mutex_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT mutex IS
GENERIC (
C_FAMILY : STRING;
C_NUM_AXI : INTEGER;
C_S0_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S0_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S0_AXI_ADDR_WIDTH : INTEGER;
C_S0_AXI_DATA_WIDTH : INTEGER;
C_S1_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S1_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S1_AXI_ADDR_WIDTH : INTEGER;
C_S1_AXI_DATA_WIDTH : INTEGER;
C_S2_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S2_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S2_AXI_ADDR_WIDTH : INTEGER;
C_S2_AXI_DATA_WIDTH : INTEGER;
C_S3_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S3_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S3_AXI_ADDR_WIDTH : INTEGER;
C_S3_AXI_DATA_WIDTH : INTEGER;
C_S4_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S4_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S4_AXI_ADDR_WIDTH : INTEGER;
C_S4_AXI_DATA_WIDTH : INTEGER;
C_S5_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S5_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S5_AXI_ADDR_WIDTH : INTEGER;
C_S5_AXI_DATA_WIDTH : INTEGER;
C_S6_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S6_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S6_AXI_ADDR_WIDTH : INTEGER;
C_S6_AXI_DATA_WIDTH : INTEGER;
C_S7_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S7_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S7_AXI_ADDR_WIDTH : INTEGER;
C_S7_AXI_DATA_WIDTH : INTEGER;
C_ASYNC_CLKS : INTEGER;
C_NUM_SYNC_FF : INTEGER;
C_ENABLE_USER : INTEGER;
C_OWNER_ID_WIDTH : INTEGER;
C_ENABLE_HW_PROT : INTEGER;
C_NUM_MUTEX : INTEGER
);
PORT (
S0_AXI_ACLK : IN STD_LOGIC;
S0_AXI_ARESETN : IN STD_LOGIC;
S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_AWVALID : IN STD_LOGIC;
S0_AXI_AWREADY : OUT STD_LOGIC;
S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S0_AXI_WVALID : IN STD_LOGIC;
S0_AXI_WREADY : OUT STD_LOGIC;
S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_BVALID : OUT STD_LOGIC;
S0_AXI_BREADY : IN STD_LOGIC;
S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_ARVALID : IN STD_LOGIC;
S0_AXI_ARREADY : OUT STD_LOGIC;
S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_RVALID : OUT STD_LOGIC;
S0_AXI_RREADY : IN STD_LOGIC;
S1_AXI_ACLK : IN STD_LOGIC;
S1_AXI_ARESETN : IN STD_LOGIC;
S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_AWVALID : IN STD_LOGIC;
S1_AXI_AWREADY : OUT STD_LOGIC;
S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S1_AXI_WVALID : IN STD_LOGIC;
S1_AXI_WREADY : OUT STD_LOGIC;
S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_BVALID : OUT STD_LOGIC;
S1_AXI_BREADY : IN STD_LOGIC;
S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_ARVALID : IN STD_LOGIC;
S1_AXI_ARREADY : OUT STD_LOGIC;
S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_RVALID : OUT STD_LOGIC;
S1_AXI_RREADY : IN STD_LOGIC;
S2_AXI_ACLK : IN STD_LOGIC;
S2_AXI_ARESETN : IN STD_LOGIC;
S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_AWVALID : IN STD_LOGIC;
S2_AXI_AWREADY : OUT STD_LOGIC;
S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S2_AXI_WVALID : IN STD_LOGIC;
S2_AXI_WREADY : OUT STD_LOGIC;
S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_BVALID : OUT STD_LOGIC;
S2_AXI_BREADY : IN STD_LOGIC;
S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_ARVALID : IN STD_LOGIC;
S2_AXI_ARREADY : OUT STD_LOGIC;
S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_RVALID : OUT STD_LOGIC;
S2_AXI_RREADY : IN STD_LOGIC;
S3_AXI_ACLK : IN STD_LOGIC;
S3_AXI_ARESETN : IN STD_LOGIC;
S3_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_AWVALID : IN STD_LOGIC;
S3_AXI_AWREADY : OUT STD_LOGIC;
S3_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S3_AXI_WVALID : IN STD_LOGIC;
S3_AXI_WREADY : OUT STD_LOGIC;
S3_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S3_AXI_BVALID : OUT STD_LOGIC;
S3_AXI_BREADY : IN STD_LOGIC;
S3_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_ARVALID : IN STD_LOGIC;
S3_AXI_ARREADY : OUT STD_LOGIC;
S3_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S3_AXI_RVALID : OUT STD_LOGIC;
S3_AXI_RREADY : IN STD_LOGIC;
S4_AXI_ACLK : IN STD_LOGIC;
S4_AXI_ARESETN : IN STD_LOGIC;
S4_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_AWVALID : IN STD_LOGIC;
S4_AXI_AWREADY : OUT STD_LOGIC;
S4_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4_AXI_WVALID : IN STD_LOGIC;
S4_AXI_WREADY : OUT STD_LOGIC;
S4_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S4_AXI_BVALID : OUT STD_LOGIC;
S4_AXI_BREADY : IN STD_LOGIC;
S4_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_ARVALID : IN STD_LOGIC;
S4_AXI_ARREADY : OUT STD_LOGIC;
S4_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S4_AXI_RVALID : OUT STD_LOGIC;
S4_AXI_RREADY : IN STD_LOGIC;
S5_AXI_ACLK : IN STD_LOGIC;
S5_AXI_ARESETN : IN STD_LOGIC;
S5_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_AWVALID : IN STD_LOGIC;
S5_AXI_AWREADY : OUT STD_LOGIC;
S5_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S5_AXI_WVALID : IN STD_LOGIC;
S5_AXI_WREADY : OUT STD_LOGIC;
S5_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S5_AXI_BVALID : OUT STD_LOGIC;
S5_AXI_BREADY : IN STD_LOGIC;
S5_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_ARVALID : IN STD_LOGIC;
S5_AXI_ARREADY : OUT STD_LOGIC;
S5_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S5_AXI_RVALID : OUT STD_LOGIC;
S5_AXI_RREADY : IN STD_LOGIC;
S6_AXI_ACLK : IN STD_LOGIC;
S6_AXI_ARESETN : IN STD_LOGIC;
S6_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_AWVALID : IN STD_LOGIC;
S6_AXI_AWREADY : OUT STD_LOGIC;
S6_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S6_AXI_WVALID : IN STD_LOGIC;
S6_AXI_WREADY : OUT STD_LOGIC;
S6_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S6_AXI_BVALID : OUT STD_LOGIC;
S6_AXI_BREADY : IN STD_LOGIC;
S6_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_ARVALID : IN STD_LOGIC;
S6_AXI_ARREADY : OUT STD_LOGIC;
S6_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S6_AXI_RVALID : OUT STD_LOGIC;
S6_AXI_RREADY : IN STD_LOGIC;
S7_AXI_ACLK : IN STD_LOGIC;
S7_AXI_ARESETN : IN STD_LOGIC;
S7_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_AWVALID : IN STD_LOGIC;
S7_AXI_AWREADY : OUT STD_LOGIC;
S7_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S7_AXI_WVALID : IN STD_LOGIC;
S7_AXI_WREADY : OUT STD_LOGIC;
S7_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S7_AXI_BVALID : OUT STD_LOGIC;
S7_AXI_BREADY : IN STD_LOGIC;
S7_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_ARVALID : IN STD_LOGIC;
S7_AXI_ARREADY : OUT STD_LOGIC;
S7_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S7_AXI_RVALID : OUT STD_LOGIC;
S7_AXI_RREADY : IN STD_LOGIC
);
END COMPONENT mutex;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S2_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S2_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S2_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S2_AXI_ACLK, ASSOCIATED_BUSIF S2_AXI, ASSOCIATED_RESET S2_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S2_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S1_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S1_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S1_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S1_AXI_ACLK, ASSOCIATED_BUSIF S1_AXI, ASSOCIATED_RESET S1_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S1_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S0_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S0_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S0_AXI_ACLK, ASSOCIATED_BUSIF S0_AXI, ASSOCIATED_RESET S0_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S0_AXI_ACLK CLK";
BEGIN
U0 : mutex
GENERIC MAP (
C_FAMILY => "artix7",
C_NUM_AXI => 3,
C_S0_AXI_BASEADDR => X"00100000",
C_S0_AXI_HIGHADDR => X"0010FFFF",
C_S0_AXI_ADDR_WIDTH => 32,
C_S0_AXI_DATA_WIDTH => 32,
C_S1_AXI_BASEADDR => X"00200000",
C_S1_AXI_HIGHADDR => X"0020FFFF",
C_S1_AXI_ADDR_WIDTH => 32,
C_S1_AXI_DATA_WIDTH => 32,
C_S2_AXI_BASEADDR => X"00300000",
C_S2_AXI_HIGHADDR => X"0030FFFF",
C_S2_AXI_ADDR_WIDTH => 32,
C_S2_AXI_DATA_WIDTH => 32,
C_S3_AXI_BASEADDR => X"FFFFFFFF",
C_S3_AXI_HIGHADDR => X"00000000",
C_S3_AXI_ADDR_WIDTH => 32,
C_S3_AXI_DATA_WIDTH => 32,
C_S4_AXI_BASEADDR => X"FFFFFFFF",
C_S4_AXI_HIGHADDR => X"00000000",
C_S4_AXI_ADDR_WIDTH => 32,
C_S4_AXI_DATA_WIDTH => 32,
C_S5_AXI_BASEADDR => X"FFFFFFFF",
C_S5_AXI_HIGHADDR => X"00000000",
C_S5_AXI_ADDR_WIDTH => 32,
C_S5_AXI_DATA_WIDTH => 32,
C_S6_AXI_BASEADDR => X"FFFFFFFF",
C_S6_AXI_HIGHADDR => X"00000000",
C_S6_AXI_ADDR_WIDTH => 32,
C_S6_AXI_DATA_WIDTH => 32,
C_S7_AXI_BASEADDR => X"FFFFFFFF",
C_S7_AXI_HIGHADDR => X"00000000",
C_S7_AXI_ADDR_WIDTH => 32,
C_S7_AXI_DATA_WIDTH => 32,
C_ASYNC_CLKS => 0,
C_NUM_SYNC_FF => 2,
C_ENABLE_USER => 1,
C_OWNER_ID_WIDTH => 8,
C_ENABLE_HW_PROT => 1,
C_NUM_MUTEX => 16
)
PORT MAP (
S0_AXI_ACLK => S0_AXI_ACLK,
S0_AXI_ARESETN => S0_AXI_ARESETN,
S0_AXI_AWADDR => S0_AXI_AWADDR,
S0_AXI_AWVALID => S0_AXI_AWVALID,
S0_AXI_AWREADY => S0_AXI_AWREADY,
S0_AXI_WDATA => S0_AXI_WDATA,
S0_AXI_WSTRB => S0_AXI_WSTRB,
S0_AXI_WVALID => S0_AXI_WVALID,
S0_AXI_WREADY => S0_AXI_WREADY,
S0_AXI_BRESP => S0_AXI_BRESP,
S0_AXI_BVALID => S0_AXI_BVALID,
S0_AXI_BREADY => S0_AXI_BREADY,
S0_AXI_ARADDR => S0_AXI_ARADDR,
S0_AXI_ARVALID => S0_AXI_ARVALID,
S0_AXI_ARREADY => S0_AXI_ARREADY,
S0_AXI_RDATA => S0_AXI_RDATA,
S0_AXI_RRESP => S0_AXI_RRESP,
S0_AXI_RVALID => S0_AXI_RVALID,
S0_AXI_RREADY => S0_AXI_RREADY,
S1_AXI_ACLK => S1_AXI_ACLK,
S1_AXI_ARESETN => S1_AXI_ARESETN,
S1_AXI_AWADDR => S1_AXI_AWADDR,
S1_AXI_AWVALID => S1_AXI_AWVALID,
S1_AXI_AWREADY => S1_AXI_AWREADY,
S1_AXI_WDATA => S1_AXI_WDATA,
S1_AXI_WSTRB => S1_AXI_WSTRB,
S1_AXI_WVALID => S1_AXI_WVALID,
S1_AXI_WREADY => S1_AXI_WREADY,
S1_AXI_BRESP => S1_AXI_BRESP,
S1_AXI_BVALID => S1_AXI_BVALID,
S1_AXI_BREADY => S1_AXI_BREADY,
S1_AXI_ARADDR => S1_AXI_ARADDR,
S1_AXI_ARVALID => S1_AXI_ARVALID,
S1_AXI_ARREADY => S1_AXI_ARREADY,
S1_AXI_RDATA => S1_AXI_RDATA,
S1_AXI_RRESP => S1_AXI_RRESP,
S1_AXI_RVALID => S1_AXI_RVALID,
S1_AXI_RREADY => S1_AXI_RREADY,
S2_AXI_ACLK => S2_AXI_ACLK,
S2_AXI_ARESETN => S2_AXI_ARESETN,
S2_AXI_AWADDR => S2_AXI_AWADDR,
S2_AXI_AWVALID => S2_AXI_AWVALID,
S2_AXI_AWREADY => S2_AXI_AWREADY,
S2_AXI_WDATA => S2_AXI_WDATA,
S2_AXI_WSTRB => S2_AXI_WSTRB,
S2_AXI_WVALID => S2_AXI_WVALID,
S2_AXI_WREADY => S2_AXI_WREADY,
S2_AXI_BRESP => S2_AXI_BRESP,
S2_AXI_BVALID => S2_AXI_BVALID,
S2_AXI_BREADY => S2_AXI_BREADY,
S2_AXI_ARADDR => S2_AXI_ARADDR,
S2_AXI_ARVALID => S2_AXI_ARVALID,
S2_AXI_ARREADY => S2_AXI_ARREADY,
S2_AXI_RDATA => S2_AXI_RDATA,
S2_AXI_RRESP => S2_AXI_RRESP,
S2_AXI_RVALID => S2_AXI_RVALID,
S2_AXI_RREADY => S2_AXI_RREADY,
S3_AXI_ACLK => '0',
S3_AXI_ARESETN => '0',
S3_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_AWVALID => '0',
S3_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S3_AXI_WVALID => '0',
S3_AXI_BREADY => '0',
S3_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_ARVALID => '0',
S3_AXI_RREADY => '0',
S4_AXI_ACLK => '0',
S4_AXI_ARESETN => '0',
S4_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_AWVALID => '0',
S4_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S4_AXI_WVALID => '0',
S4_AXI_BREADY => '0',
S4_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_ARVALID => '0',
S4_AXI_RREADY => '0',
S5_AXI_ACLK => '0',
S5_AXI_ARESETN => '0',
S5_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_AWVALID => '0',
S5_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S5_AXI_WVALID => '0',
S5_AXI_BREADY => '0',
S5_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_ARVALID => '0',
S5_AXI_RREADY => '0',
S6_AXI_ACLK => '0',
S6_AXI_ARESETN => '0',
S6_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_AWVALID => '0',
S6_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S6_AXI_WVALID => '0',
S6_AXI_BREADY => '0',
S6_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_ARVALID => '0',
S6_AXI_RREADY => '0',
S7_AXI_ACLK => '0',
S7_AXI_ARESETN => '0',
S7_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_AWVALID => '0',
S7_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S7_AXI_WVALID => '0',
S7_AXI_BREADY => '0',
S7_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_ARVALID => '0',
S7_AXI_RREADY => '0'
);
END DemoInterconnect_mutex_0_0_arch;
|
mit
|
6e0c9f45d5b02e7b5f2d0b3fe90478d5
| 0.663238 | 2.920087 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/Thor_crossbar.vhd
| 1 | 931 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.NoCPackage.all;
entity Thor_crossbar is
port(
data_av: in regNport;
data_in: in arrayNport_regflit;
data_ack: out regNport;
sender: in regNport;
free: in regNport;
tab_in: in arrayNport_reg3;
tab_out: in arrayNport_reg3;
tx: out regNport;
data_out: out arrayNport_regflit;
credit_i: in regNport);
end Thor_crossbar;
architecture Thor_crossbar of Thor_crossbar is
begin
MUXS : for i in EAST to LOCAL generate
tx(i) <= data_av( TO_INTEGER( unsigned(tab_out(i)) ) ) when free(i) = '0' else '0';
data_out(i) <= data_in( TO_INTEGER( unsigned(tab_out(i)) ) ) when free(i) = '0' else (others=>'0');
data_ack(i) <= credit_i( TO_INTEGER( unsigned(tab_in(i)) ) ) when data_av(i) = '1' else '0';
end generate MUXS;
end Thor_crossbar;
|
lgpl-3.0
|
c3604cfdaa801659bcc79cd95c2637cf
| 0.609023 | 3.032573 | false | false | false | false |
inforichland/freezing-spice
|
src/std_logic_textio.vhd
| 1 | 18,575 |
-- std_logic_textio.vhdl
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
bsd-3-clause
|
97d6f21d4f8fcb4a56ba574fcab1d823
| 0.590417 | 2.934439 | false | false | false | false |
dl3yc/sdr-fm
|
dev/div/div.vhd
| 1 | 1,866 |
-- DIV module for Betty SDR
-- implements an iterative restoring divider
-- heavily based on 8-bit Restoring Divider(p.94 U. Meyer-Baese "DSP with FPGA")
-- file: div.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - tested with use cases
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div is
generic (
WN : natural;
WD : natural
);
port (
clk : in std_logic;
stb : in std_logic;
num : in signed(WN-1 downto 0);
denom : in signed(WD-1 downto 0);
quot : out signed(WN-1 downto 0);
remaind : out signed(WD-1 downto 0);
rdy : out std_logic
);
end entity div;
architecture rtl of div is
type state_t is (init, processing, restoring, establish);
signal state : state_t;
signal r, d : signed(WN+WD-1 downto 0) := (others => '0');
signal q : signed(WN-1 downto 0);
signal count : integer range 0 to WN;
begin
process
begin
wait until rising_edge(clk);
case state is
when init =>
rdy <= '0';
if stb = '1' then
state <= processing;
count <= 0;
q <= (others => '0');
if denom = 0 then
state <= establish;
d <= to_signed(1,d'length);
r <= (others => '0');
else
d <= shift_left(resize(denom,d'length),WN-1);
r <= resize(num,r'length);
end if;
end if;
when processing =>
r <= r - d;
state <= restoring;
when restoring =>
if r < 0 then
r <= r + d;
q <= shift_left(q,1);
else
q <= shift_left(q,1) + 1;
end if;
count <= count + 1;
d <= d / 2;
if count = WN-1 then
state <= establish;
else
state <= processing;
end if;
when establish =>
quot <= q;
remaind <= resize(r,remaind'length);
rdy <= '1';
state <= init;
end case;
end process;
end architecture rtl;
|
gpl-2.0
|
8a289153094bf1791cc5434b51f11a0f
| 0.583065 | 2.866359 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_uart_transceiver_0_0/sim/DemoInterconnect_uart_transceiver_0_0.vhd
| 2 | 4,296 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_0 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_0;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_0_arch OF DemoInterconnect_uart_transceiver_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_0_arch;
|
mit
|
549baebf63453997e02ec1215389cf02
| 0.706006 | 3.729167 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/src/parallel2serial.vhd
| 3 | 2,927 |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: P2S Serializer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity word2byte is
generic (
DATA_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
rstn_i : in std_logic;
en_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(7 downto 0);
ss_o : out std_logic
) ;
end word2byte;
architecture behave of word2byte is
----------------------------------
signal shift_count : integer range 0 to 7 := 0;
signal send_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal sending : std_logic := '0';
signal tx_done : std_logic := '0';
----------------------------------
begin
send_ctrl: process(clk_i, en_i, data_i, sending, tx_done)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
sending <= '0';
send_data <= (others=>'0');
else
if (en_i = '1' and sending='0') then
send_data(DATA_WIDTH-1 downto 0) <= data_i; --register new data to send when not sending
sending <= '1';
elsif sending='1' and tx_done='1' then
sending <= '0';
end if;
end if;
end if;
end process;
shift_out: process(clk_i, shift_count, send_data, sending, tx_done)
begin
if rising_edge(clk_i) then
shift_o <= send_data((shift_count)*(8)+(8)-1 downto (shift_count)*(8)); --MSB first
end if;
end process;
strobe_out: process(clk_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
ss_o <= '1';
else
if (sending = '1' and tx_done='0' and send_i='1') then
ss_o <= '0';
else
ss_o <= '1';
end if;
end if;
end if;
end process;
count_shift: process(clk_i, shift_count, send_data, sending, tx_done)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_count <= 0;
tx_done <= '0';
else
if (sending = '1' and tx_done='0' and send_i='1') then
if shift_count = 0 then
tx_done <= '1';
else
shift_count <= shift_count - 1;
end if;
else
if (en_i = '1' and sending='0') then
shift_count <= to_integer(unsigned(shift_cnt_i))-1;
end if;
tx_done <= '0';
end if;
end if;
end if;
end process;
busy_o <= sending;
done_o <= tx_done;
end behave;
|
mit
|
c8045cba242be015ddc7c861d2871987
| 0.510079 | 3.360505 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/testPreEscalador.vhd
| 1 | 2,342 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:17 10/31/2011
-- Design Name:
-- Module Name: /home/cvargasc/Documentos/Uniandes/201120/Fundamentos de Sistemas Digitales/Laboratorios/practica7/practica7/testPreEscalador.vhd
-- Project Name: practica7
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: preEscalador
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testPreEscalador IS
END testPreEscalador;
ARCHITECTURE behavior OF testPreEscalador IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT preEscalador
PORT(
clk : IN std_logic;
reset : IN std_logic;
caidaBolitaOut : OUT std_logic;
multiplexorOut : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal caidaBolitaOut : std_logic;
signal multiplexorOut : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: preEscalador PORT MAP (
clk => clk,
reset => reset,
caidaBolitaOut => caidaBolitaOut,
multiplexorOut => multiplexorOut
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait;
end process;
END;
|
gpl-2.0
|
7ecd652b8aa9f6e1461486e3021c84b4
| 0.618275 | 4.094406 | false | true | false | false |
andbet050197/IS773UTP
|
sumadorcompleto/sumador_competo_tb.vhd
| 1 | 2,324 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:29:11 02/19/2017
-- Design Name:
-- Module Name: C:/ANDRES(temp)/Lab. Electronica Digital/sumedio/sumador_competo_tb.vhd
-- Project Name: sumedio
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sumpleto
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sumador_competo_tb IS
END sumador_competo_tb;
ARCHITECTURE behavior OF sumador_competo_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sumpleto
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
cout : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal cin : std_logic := '0';
--Outputs
signal cout : std_logic;
signal s : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sumpleto PORT MAP (
a => a,
b => b,
cin => cin,
cout => cout,
s => s
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--000
wait for 100 ns;
--001
b <= '1';
wait for 100 ns;
--010
b <= '0';
a <= '1';
wait for 100 ns;
--011
b <= '1';
wait for 100 ns;
--100
b <= '0';
a <= '0';
cin <= '1';
wait for 100 ns;
--101
b <= '1';
wait for 100 ns;
--110
b <= '0';
a <= '1';
wait for 100 ns;
--111
b <= '1';
wait;
end process;
END;
|
gpl-3.0
|
d823ebc77ea0a65594433d6bf61193dc
| 0.549914 | 3.521212 | false | true | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_uart_transceiver_0_1/sim/DemoInterconnect_uart_transceiver_0_1.vhd
| 2 | 4,296 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_1 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_1;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_1_arch OF DemoInterconnect_uart_transceiver_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_1_arch;
|
mit
|
8feac9defc55268d4476829f19315ef3
| 0.706006 | 3.729167 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sim_1/new/DemoInterconnect_TestBench.vhd
| 1 | 8,932 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/24/2017 06:40:21 PM
-- Design Name:
-- Module Name: DemoInterconnect_TestBench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DemoInterconnect_TestBench is
Generic(
CLKFREQ : integer := 72000000;
UARTFREQ : integer := 12000000;
SYSCLK_PERIOD : time := 83.333 ns; -- 12MHZ
BAUD_RATE : integer := 115200;
TRACE_DLY : time := 3 ns
);
Port (
UART_TX_0_wire : out STD_LOGIC;
UART_TX_1_wire : out STD_LOGIC;
spi_0_mosi_wire : out STD_LOGIC;
spi_0_sck_wire : out STD_LOGIC;
spi_0_ss_wire : out STD_LOGIC;
spi_1_mosi_wire : out STD_LOGIC;
spi_1_sck_wire : out STD_LOGIC;
spi_1_ss_wire : out STD_LOGIC;
spi_2_mosi_wire : out STD_LOGIC;
spi_2_sck_wire : out STD_LOGIC;
spi_2_ss_wire : out STD_LOGIC;
spi_3_mosi_wire : out STD_LOGIC;
spi_3_sck_wire : out STD_LOGIC;
spi_3_ss_wire : out STD_LOGIC
);
end DemoInterconnect_TestBench;
architecture Behavioral of DemoInterconnect_TestBench is
--comopennt declaration
component DemoInterconnect_wrapper is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
end component;
component parallel2serial is
generic (
DATA_WIDTH : integer := 8;
TX_WIDTH : integer := 1
);
port (
clk_i : in std_logic;
en_i : in std_logic;
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(TX_WIDTH-1 downto 0);
ss_o : out std_logic
) ;
end component;
component UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end component;
--constant declaration
constant c_CLKS_PER_BIT : integer := CLKFREQ/BAUD_RATE; -- Needs to be set correctly
--signal declaration
signal SYSCLK : std_logic := '0';
signal AXICLK : std_logic := '0';
signal UARTCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
signal UART_RX_0_wire, UART_RX_1_wire : std_logic := 'Z';
signal spi_0_miso_wire, spi_1_miso_wire, spi_2_miso_wire, spi_3_miso_wire : STD_LOGIC := 'Z';
signal dest_address : unsigned(4 downto 0) := (others=>'0'); --5bits
signal dest_data : unsigned(31 downto 0) := (others=>'0'); --32bits
signal dest_ctrl : std_logic_vector(2 downto 0) := "011"; --3bits
signal master_packet : std_logic_vector(39 downto 0) := (others=>'0'); --40bits
signal master_packet_send_en : std_logic := '0';
signal p2s_en, p2s_send, p2s_busy, p2s_done, p2s_ss : std_logic := '0';
signal uart_tx_en, uart_tx_done, uart_tx_active : std_logic := '0';
signal uart_tx_byte : std_logic_vector(7 downto 0) := (others=>'0');
signal resetn_ext_logic : std_logic := '1';
constant slave_0_addr : unsigned(4 downto 0) := "00000";
constant slave_1_addr : unsigned(4 downto 0) := "00001";
constant slave_2_addr : unsigned(4 downto 0) := "00010";
constant slave_3_addr : unsigned(4 downto 0) := "00011";
begin
drive_miso: process(dest_address)
begin
spi_0_miso_wire <= SYSCLK;
spi_1_miso_wire <= SYSCLK;
spi_2_miso_wire <= SYSCLK;
spi_3_miso_wire <= SYSCLK;
end process;
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
--Address Generator
addr_gen: process(AXICLK)
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
dest_address <= (others=>'0');
elsif (p2s_done = '1') then
if (dest_address = slave_0_addr) then
dest_address <= slave_1_addr;
elsif (dest_address = slave_1_addr) then
dest_address <= slave_2_addr;
elsif (dest_address = slave_2_addr) then
dest_address <= slave_3_addr;
else
dest_ctrl(2) <= not(dest_ctrl(2));
dest_address <= slave_0_addr;
end if;
end if;
end if;
end process;
--Data Generator
data_gen: process(AXICLK)
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
dest_data <= X"4433_2211";
else
dest_data <= X"4433_2211";
end if;
end if;
end process;
--Packet generate
packet_gen: process(AXICLK)
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
master_packet <= (others=>'0');
else
master_packet <= dest_ctrl & std_logic_vector(dest_address) & std_logic_vector(dest_data);
end if;
end if;
end process;
--Send packet
send_packet: process(AXICLK)
variable send_delay_countdown : integer := 32;
begin
if rising_edge(AXICLK) then
if (resetn_ext_logic = '0') then
master_packet_send_en <= '0';
p2s_en <= '0';
else
if (master_packet_send_en='0' and p2s_en='0' and p2s_busy='0' and uart_tx_active='0' and uart_tx_en='0') then
if (send_delay_countdown = 0) then
master_packet_send_en <= '1';
send_delay_countdown := 32;
else
send_delay_countdown := send_delay_countdown - 1;
end if;
else
master_packet_send_en <= '0';
end if;
if (master_packet_send_en = '1' and p2s_en='0' and p2s_busy='0' and uart_tx_en='0') then
p2s_en <= '1';
else
p2s_en <= '0';
end if;
end if;
end if;
end process;
--signal connection
p2s_send <= not(uart_tx_active) and not(uart_tx_en);
uart_tx_en <= not(p2s_ss);
UART_RX_1_wire <= 'Z';
--component instances
p2s_inst: parallel2serial
generic map(
DATA_WIDTH => 40,
TX_WIDTH => 8
)
port map(
clk_i => AXICLK,
en_i => p2s_en,
send_i => p2s_send,
data_i => master_packet,
busy_o => p2s_busy,
done_o => p2s_done,
shift_o => uart_tx_byte,
ss_o => p2s_ss
);
uart_tx_inst: uart_tx
generic map(
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
port map(
i_Clk => AXICLK,
i_TX_DV => uart_tx_en,
i_TX_Byte => uart_tx_byte,
o_TX_Active => uart_tx_active,
o_TX_Serial => UART_RX_0_wire,
o_TX_Done => uart_tx_done
);
DemoInterconnect_Inst: DemoInterconnect_wrapper
port map(
UART_RX_0 => UART_RX_0_wire,
UART_RX_1 => UART_RX_1_wire,
UART_TX_0 => UART_TX_0_wire,
UART_TX_1 => UART_TX_1_wire,
LED0_pll_aclk => AXICLK,
LED2_pll_lock => resetn_ext_logic,
LED1_pll_uart => UARTCLK,
m_spi_mosi => spi_0_mosi_wire,
m_spi_miso => spi_0_miso_wire,
m_spi_sclk => spi_0_sck_wire,
m_spi_ss => spi_0_ss_wire,
m_spi_mosi_1 => spi_1_mosi_wire,
m_spi_miso_1 => spi_1_miso_wire,
m_spi_sclk_1 => spi_1_sck_wire,
m_spi_ss_1 => spi_1_ss_wire,
m_spi_mosi_2 => spi_2_mosi_wire,
m_spi_miso_2 => spi_2_miso_wire,
m_spi_sclk_2 => spi_2_sck_wire,
m_spi_ss_2 => spi_2_ss_wire,
m_spi_mosi_3 => spi_3_mosi_wire,
m_spi_miso_3 => spi_3_miso_wire,
m_spi_sclk_3 => spi_3_sck_wire,
m_spi_ss_3 => spi_3_ss_wire,
sys_clk => SYSCLK,
sys_reset => not(NSYSRESET)
);
end Behavioral;
|
mit
|
3a50f330a3bd293de91f14aae15e00e6
| 0.570309 | 3.006395 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_1_0/synth/DemoInterconnect_internoc_ni_axi_master_1_0.vhd
| 1 | 11,146 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY xil_defaultlib;
USE xil_defaultlib.internoc_ni_axi_master_v1_0;
ENTITY DemoInterconnect_internoc_ni_axi_master_1_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_1_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_1_0_arch OF DemoInterconnect_internoc_ni_axi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_internoc_ni_axi_master_1_0_arch: ARCHITECTURE IS "internoc_ni_axi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_internoc_ni_axi_master_1_0_arch : ARCHITECTURE IS "DemoInterconnect_internoc_ni_axi_master_1_0,internoc_ni_axi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_1_0_arch;
|
mit
|
ed319939495e1d279c481a2647fad0d3
| 0.708505 | 3.189127 | false | false | false | false |
inforichland/freezing-spice
|
src/csr_pkg.vhd
| 1 | 2,331 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package csr_pkg is
subtype csr_addr_t is std_logic_vector(11 downto 0);
-- input record
type csr_in_t is record
csr_addr : csr_addr_t;
rs1 : word;
imm : word;
system_type : system_type_t;
valid : std_logic; -- '1' if this was a valid cycle that the core was executing
instret : std_logic; -- '1' for instruction retired this cycle
end record csr_in_t;
----------------------------------------------
-- User-mode (U) CSRs
----------------------------------------------
constant CSR_CYCLE : csr_addr_t := X"C00";
constant CSR_TIME : csr_addr_t := X"C01";
constant CSR_INSTRET : csr_addr_t := X"C02";
constant CSR_CYCLEH : csr_addr_t := X"C80";
constant CSR_TIMEH : csr_addr_t := X"C81";
constant CSR_INSTRETH : csr_addr_t := X"C82";
----------------------------------------------
-- Machine-mode (M) CSRs
----------------------------------------------
-- Machine Information Registers
constant CSR_MCPUID : csr_addr_t := X"F00";
constant CSR_MIMPID : csr_addr_t := X"F01";
constant CSR_MHARTID : csr_addr_t := X"F10";
-- Machine Trap Setup
constant CSR_MSTATUS : csr_addr_t := X"300";
constant CSR_MTVEC : csr_addr_t := X"301";
constant CSR_MTDELEG : csr_addr_t := X"302";
constant CSR_MIE : csr_addr_t := X"304";
constant CSR_MTIMECMP : csr_addr_t := X"321";
-- Machine Timers and Counters
constant CSR_MTIME : csr_addr_t := X"701";
constant CSR_MTIMEH : csr_addr_t := X"741";
-- Machine Trap Handling
constant CSR_MSCRATCH : csr_addr_t := X"340";
constant CSR_MEPC : csr_addr_t := X"341";
constant CSR_MCAUSE : csr_addr_t := X"342";
constant CSR_MBADADDR : csr_addr_t := X"343";
constant CSR_MIP : csr_addr_t := X"344";
-- Machine Protection and Translation
constant CSR_MBASE : csr_addr_t := X"380";
constant CSR_MBOUND : csr_addr_t := X"381";
constant CSR_MIBASE : csr_addr_t := X"382";
constant CSR_MIBOUND : csr_addr_t := X"383";
constant CSR_MDBASE : csr_addr_t := X"384";
constant CSR_MDBOUND : csr_addr_t := X"385";
end package csr_pkg;
|
bsd-3-clause
|
fa2119d26bccb4e5eec4441c5833ff16
| 0.542686 | 3.32525 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/generadorAleatorio.vhd
| 1 | 1,694 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:54 10/31/2011
-- Design Name:
-- Module Name: generadorAleatorio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity generadorAleatorio is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
derecha : in STD_LOGIC;
izquierda: in STD_LOGIC;
inicioOut: out STD_LOGIC_VECTOR (7 downto 0)
);
end generadorAleatorio;
architecture Behavioral of generadorAleatorio is
signal inicio : STD_LOGIC_VECTOR (7 downto 0);
begin
process(clk,reset,derecha,izquierda)
begin
if reset = '1' then
inicio <= "00000001";
elsif clk'event and clk = '1' then
if derecha = '1' or izquierda = '1' then
inicio(7) <= inicio(0);
inicio(6 downto 0) <= inicio(7 downto 1);
else
inicio(7 downto 1) <= inicio(6 downto 0);
inicio(0) <= inicio(7);
end if;
end if;
end process;
process(clk,reset,inicio)
begin
if reset = '1' then
inicioOut <= "00000001";
elsif clk'event and clk = '1' then
inicioOut <= inicio;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
fc88ca2e8035998208ea05679a9104f1
| 0.608619 | 3.543933 | false | false | false | false |
dl3yc/sdr-fm
|
testing/fir-1.0/test/fir_matlab.vhd
| 2 | 1,150 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
use work.fir_coeff_lib.all;
use std.textio.all;
entity fir_matlab is
end entity fir_matlab;
architecture sim of fir_matlab is
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal d : signed(26 downto 0);
signal q : signed(26 downto 0);
signal rdy : std_logic;
begin
dut : entity work.fir
generic map(
fir_order => fir_order,
fir_coeff => to_fir_coeff_t(fir_coeff_content)
)
port map(
clk => clk,
stb => stb,
d => d,
q => q,
rdy => rdy
);
clk <= not clk after 20345 ps;
process
variable cnt : unsigned(8 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if cnt = 511 then
stb <= '1';
else
stb <= '0';
end if;
cnt := cnt + 1;
end process;
process
variable l : line;
variable ll : integer;
begin
wait until rising_edge(clk);
if stb = '1' then
readline(input, l);
read(l, ll);
d <= to_signed(ll, 27);
end if;
if rdy = '1' then
ll := to_integer(q);
write(l, ll);
writeline(output, l);
end if;
end process;
end architecture sim;
|
gpl-2.0
|
b2585b743ce546369d89b20afc0f4dd7
| 0.612174 | 2.674419 | false | false | false | false |
LaNoC-UFC/NoCThor
|
tests/fifo_buffer_test.vhd
| 1 | 2,753 |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_buffer_test is
end;
architecture fifo_buffer_test of fifo_buffer_test is
constant CLOCK_PERIOD : time := 20 ns;
constant BUFFER_DEPTH : positive := 10;
constant BUFFER_WIDTH : positive := 13;
signal clock: std_logic := '0';
signal reset: std_logic;
signal head, tail : std_logic_vector(BUFFER_WIDTH-1 downto 0);
signal push, pull : std_logic;
signal counter : natural;
procedure wait_clock_tick is
begin
wait until rising_edge(clock);
wait until counter'stable;
wait until head'stable;
end wait_clock_tick;
begin
reset <= '1', '0' after CLOCK_PERIOD/4;
clock <= not clock after CLOCK_PERIOD/2;
UUT : entity work.fifo_buffer
generic map(
BUFFER_DEPTH => BUFFER_DEPTH,
BUFFER_WIDTH => BUFFER_WIDTH)
port map(
reset => reset,
clock => clock,
head => head,
tail => tail,
push => push,
pull => pull,
counter => counter
);
process
begin
push <= '0';
pull <= '0';
tail <= (others=>'0');
wait until reset = '0';
assert counter = 0 report "Buffer should be empty after reset" severity failure;
wait_clock_tick;
-- fill it completely
push <= '1';
for i in 1 to BUFFER_DEPTH loop
tail <= std_logic_vector(to_unsigned(i, tail'length));
wait_clock_tick;
assert counter = i report "Buffer should have " & integer'image(i) & " element(s)" severity failure;
end loop;
-- try to force one more
wait_clock_tick;
assert counter = BUFFER_DEPTH report "Buffer shouldnt pass its size" severity failure;
-- push and pull at the same time
pull <= '1';
for i in 1 to BUFFER_DEPTH loop
assert head = std_logic_vector(to_unsigned(i, head'length)) report "Values not equal when pushing/pulling" severity failure;
tail <= std_logic_vector(to_unsigned(i, tail'length));
wait_clock_tick;
assert counter = BUFFER_DEPTH report "Buffer counter should remain constant when pushing/pulling" severity failure;
end loop;
-- empty it completely
push <= '0';
for i in 1 to BUFFER_DEPTH loop
assert head = std_logic_vector(to_unsigned(i, head'length)) report "Values not equal when emptying" severity failure;
wait_clock_tick;
assert counter = (BUFFER_DEPTH - i) report "Buffer should have " & integer'image(BUFFER_DEPTH - i) & " element(s)" severity failure;
end loop;
wait;
end process;
end fifo_buffer_test;
|
lgpl-3.0
|
9010bdfbc32b05f2589a0f51cad682ed
| 0.597167 | 4.048529 | false | false | false | false |
andbet050197/IS773UTP
|
modulo3/ECO.vhd
| 1 | 811 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ECO is
Port ( Rx : in STD_LOGIC;
Tx : out STD_LOGIC;
CLK : in STD_LOGIC);
end ECO;
architecture Behavioral of ECO is
COMPONENT ProtocoloRS232_v2
PORT(
Rx_entrada : IN std_logic;
CLK : IN std_logic;
CampanaTx : IN std_logic;
Dato_Tx : IN std_logic_vector(7 downto 0);
Tx_salida : OUT std_logic;
CampanaRx : OUT std_logic;
Dato_Rx : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal campana : std_logic := '0';
signal Dato : std_logic_vector(7 downto 0) := "00000000";
begin
Inst_ProtocoloRS232_v2: ProtocoloRS232_v2 PORT MAP(
Tx_salida => Tx,
Rx_entrada => Rx,
CLK => CLK,
CampanaTx => campana,
CampanaRx => campana,
Dato_Tx => Dato,
Dato_Rx => Dato
);
end Behavioral;
|
gpl-3.0
|
c3fe8afbe40ef1566b4b98f8a616ccca
| 0.635018 | 2.796552 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_0_0/sim/DemoInterconnect_axi_spi_master_0_0.vhd
| 2 | 10,931 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_0_arch OF DemoInterconnect_axi_spi_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_0_arch;
|
mit
|
0b39aeb1943be0f7062ef1fa8fbdd24c
| 0.712744 | 3.190601 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AB.vhd
| 1 | 420 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LatchSR_AB is
Port ( Sn : in STD_LOGIC;
Rn : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AB;
architecture Behavioral of LatchSR_AB is
signal Q_aux : std_logic := '0';
signal Qn_aux : std_logic := '0';
begin
Q <= Q_aux;
Qn <= Qn_aux;
Q_aux <= Sn nand Qn_aux;
Qn_aux <= Rn nand Q_aux;
end Behavioral;
|
gpl-3.0
|
5d4ab968df32c0bdb190ab6bc4e43e1c
| 0.592857 | 2.818792 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/proyecto/testRoadWarrior.vhd
| 1 | 2,678 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:32:48 11/24/2011
-- Design Name:
-- Module Name: C:/Users/Digitales/Desktop/roadWarriorV2/roadWarrior/testRoadWarrior.vhd
-- Project Name: roadWarrior
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: roadWarrior
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testRoadWarrior IS
END testRoadWarrior;
ARCHITECTURE behavior OF testRoadWarrior IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT roadWarrior
PORT(
clk : IN std_logic;
avance : IN std_logic;
reset : IN std_logic;
memoria : OUT std_logic_vector(6 downto 0);
registro : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal avance : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal memoria : std_logic_vector(6 downto 0);
signal registro : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant avance_period : time := 200 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: roadWarrior PORT MAP (
clk => clk,
avance => avance,
reset => reset,
memoria => memoria,
registro => registro
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
avance_process :process
begin
avance <= '0';
wait for avance_period;
avance <= '1';
wait for clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
reset <= '1';
wait for clk_period*3;
reset <= '0';
wait for clk_period*3;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
38025c1fe3905435e99bd18c5403dd85
| 0.588499 | 3.932452 | false | true | false | false |
andbet050197/IS773UTP
|
modulo3/Tx_TB.vhd
| 1 | 1,302 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tx_TB IS
END Tx_TB;
ARCHITECTURE behavior OF Tx_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Tx
PORT(
Campana : IN std_logic;
CLK : IN std_logic;
Dato_entrada : IN std_logic_vector(7 downto 0);
Dato_salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal Campana : std_logic := '0';
signal CLK : std_logic := '0';
signal Dato_entrada : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Dato_salida : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Tx PORT MAP (
Campana => Campana,
CLK => CLK,
Dato_entrada => Dato_entrada,
Dato_salida => Dato_salida
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
wait for 156240 ns;
Campana <= '1';
Dato_entrada <= "10101100";
wait for 104160 ns;
Campana <= '0';
Dato_entrada <= "00000000";
wait;
end process;
END;
|
gpl-3.0
|
570e2ac9bf6608839a0765ae14fb88e8
| 0.582181 | 3.596685 | false | false | false | false |
LaNoC-UFC/NoCThor
|
topNoC.vhd
| 1 | 1,719 |
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
entity topNoC is
end;
architecture topNoC of topNoC is
component inputmodule
port
(
clock : in std_logic;
reset : in std_logic;
incredit : in regNrot;
outtx : out regNrot;
outdata : out arrayNrot_regflit
);
end component;
component outputmodule
port
(
clock : in std_logic;
reset : in std_logic;
intx : in regNrot;
indata : in arrayNrot_regflit
);
end component;
signal clock : regNrot:=(others=>'0');
signal reset : std_logic;
signal clock_rx: regNrot:=(others=>'0');
signal rx, credit_o: regNrot;
signal clock_tx, tx, credit_i: regNrot;
signal data_in, data_out : arrayNrot_regflit;
begin
reset <= '1', '0' after 10 ns;
clock <= not clock after 10 ns;
clock_rx <= not clock_rx after 10 ns;
credit_i <= tx;
NOC: Entity work.NOC
port map(
clock => clock,
reset => reset,
clock_rxLocal => clock_rx,
rxLocal => rx,
data_inLocal => data_in,
credit_oLocal => credit_o,
clock_txLocal => clock_tx,
txLocal => tx,
data_outLocal => data_out,
credit_iLocal => credit_i
);
cim00: inputmodule
port map
(
clock => clock(0),
reset => reset,
incredit => credit_o,
outtx => rx,
outdata => data_in
);
cim01: outputmodule
port map
(
clock => clock(0),
reset => reset,
intx => tx,
indata => data_out
);
end topNoC;
|
lgpl-3.0
|
fdd4c7dddfeabcd2fc9a01456fb378fa
| 0.515416 | 3.969977 | false | false | false | false |
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