repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
vargax/ejemplos
|
vhd/fundSistDigitales/practica4/deconcat5b.vhd
| 1 | 1,248 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:12:52 09/11/2011
-- Design Name:
-- Module Name: deconcat5b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity deconcat5b is
Port ( sig : in STD_LOGIC_VECTOR (4 downto 0);
A2 : out STD_LOGIC;
A1 : out STD_LOGIC;
A0 : out STD_LOGIC;
RBI : out STD_LOGIC;
RBO : out STD_LOGIC);
end deconcat5b;
architecture Behavioral of deconcat5b is
begin
A2 <= sig(4);
A1 <= sig(3);
A0 <= sig(2);
RBI <= sig(1);
RBO <= sig(0);
end Behavioral;
|
gpl-2.0
|
75aa75c266c6d038718812ceef3a834c
| 0.532051 | 3.714286 | false | false | false | false |
andbet050197/IS773UTP
|
modulo3/Rx_TB.vhd
| 1 | 1,705 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Rx_TB IS
END Rx_TB;
ARCHITECTURE behavior OF Rx_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Rx
PORT(
Dato_entrada : IN std_logic;
CLK : IN std_logic;
Dato_salida : OUT std_logic_vector(7 downto 0);
Campana : OUT std_logic
);
END COMPONENT;
--Inputs
signal Dato_entrada : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal Dato_salida : std_logic_vector(7 downto 0);
signal Campana : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Rx PORT MAP (
Dato_entrada => Dato_entrada,
CLK => CLK,
Dato_salida => Dato_salida,
Campana => Campana
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Dato_entrada <= '1';
wait for 10 ns;
wait for 156240 ns;
Dato_entrada <= '0';
wait for 104160 ns;
Dato_entrada <= '1';
wait for 104160 ns;
Dato_entrada <= '0';
wait for 104160 ns;
Dato_entrada <= '1';
wait for 104160 ns;
Dato_entrada <= '0';
wait for 104160 ns;
Dato_entrada <= '1';
wait for 104160 ns;
Dato_entrada <= '1';
wait for 104160 ns;
Dato_entrada <= '0';
wait for 104160 ns;
Dato_entrada <= '0';
wait for 104160 ns;
Dato_entrada <= '0';
wait for 104160 ns;
Dato_entrada <= '1';
wait for 104160 ns;
Dato_entrada <= '1';
wait;
end process;
END;
|
gpl-3.0
|
5791161fbeef068b455b9d9505e9c805
| 0.588856 | 3.343137 | false | false | false | false |
dl3yc/sdr-fm
|
testing/dfir-1.0/test/dfir_matlab.vhd
| 2 | 1,161 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
use work.dfir_coeff_lib.all;
use std.textio.all;
entity dfir_matlab is
end entity dfir_matlab;
architecture sim of dfir_matlab is
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal d : signed(26 downto 0);
signal q : signed(26 downto 0);
signal rdy : std_logic;
begin
dut : entity work.dfir
generic map(
dfir_order => dfir_order,
dfir_coeff => to_dfir_coeff_t(dfir_coeff_content)
)
port map(
clk => clk,
stb => stb,
d => d,
q => q,
rdy => rdy
);
clk <= not clk after 20345 ps;
process
variable cnt : unsigned(8 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if cnt = 511 then
stb <= '1';
else
stb <= '0';
end if;
cnt := cnt + 1;
end process;
process
variable l : line;
variable ll : integer;
begin
wait until rising_edge(clk);
if stb = '1' then
readline(input, l);
read(l, ll);
d <= to_signed(ll, 27);
end if;
if rdy = '1' then
ll := to_integer(q);
write(l, ll);
writeline(output, l);
end if;
end process;
end architecture sim;
|
gpl-2.0
|
6793bacab1b9424a7b3c03f7d124f8bd
| 0.615848 | 2.7 | false | false | false | false |
mosass/HexapodRobot
|
VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd
| 1 | 9,781 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_1_axi_gpio_0_0;
ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_gpio_0_0_arch : ARCHITECTURE IS "design_1_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "design_1_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=4,C_ALL_INPUTS=1,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 4,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END design_1_axi_gpio_0_0_arch;
|
mit
|
8dff73b54465e7f5e1312d4670b6cf3b
| 0.687558 | 3.160258 | false | false | false | false |
inforichland/freezing-spice
|
src/pipeline.vhd
| 1 | 29,954 |
-------------------------------------------------------------------------------
-- Title : 5-stage RISCV integer pipeline
-- Project : Freezing Spice
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : Tim Wawrzynczak
-- Created : 2015-07-07
-- Last update: 2017-01-15
-- Platform : FPGA
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: RV32I 5-stage ("classic MIPS") pipeline:
-- Instruction Fetch
-- Instruction Decode
-- Instruction Execute
-- Memory Access
-- Register File Writeback
-------------------------------------------------------------------------------
-- Interrupts: 32-bit wide IRQ number
-- Currently when an instruction signals that an interrupt
-- needs to be taken, a "trap instruction" is immediately inserted into
-- the pipeline. Once the trap instruction reaches the writeback stage,
-- all instructions in the pipeline are flushed, and the IF stage steers
-- the pipeline to the IRQ_VECTOR_ADDRESS. The pipeline will have inserted
-- the IRQ number into the "MCAUSE" CSR. The ISR can read that register
-- to determine the cause of the interrupt and can decide what to do with
-- that information.
--
-- Only one interrupt can be serviced at a time, due to this architectural
-- choice; the 'irq' and 'irq_ack' I/O ports are used to handshake with
-- an external interrupt controller.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Tim Wawrzynczak
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.if_pkg.all;
use work.id_pkg.all;
use work.ex_pkg.all;
use work.csr_pkg.all;
entity pipeline is
generic (g_initial_pc : unsigned(31 downto 0) := (others => '0');
g_for_sim : boolean := false;
g_regout_filename : string := "sim/regout.vec");
port (clk : in std_logic;
rst_n : in std_logic;
-- interrupt interface
irq_num : in word;
irq : in std_logic;
irq_ack : out std_logic;
-- Instruction interface
insn_in : in word;
insn_valid : in std_logic;
insn_addr : out word;
-- Data interface
data_in : in word;
data_out : out word;
data_addr : out word;
data_write_en : out std_logic;
data_read_en : out std_logic;
data_in_valid : in std_logic);
end entity pipeline;
architecture Behavioral of pipeline is
-------------------------------------------------
-- IF signals
-------------------------------------------------
signal if_d : if_in;
signal if_q : if_out;
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
signal if_id_ir : word := (others => '0');
signal if_id_pc : word := (others => '0');
-------------------------------------------------
-- ID signals
-------------------------------------------------
signal id_d : word;
signal id_q : decoded_t;
signal rs1_data : word;
signal rs2_data : word;
signal id_op1 : word;
signal id_op2 : word;
signal id_predict_taken : std_logic;
signal id_branch_pc : word;
-------------------------------------------------
-- ID/EX pipeline registers
-------------------------------------------------
signal id_ex_pc : word := (others => '0');
signal id_ex_rs1_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_rs2_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_op1 : word := (others => '0');
signal id_ex_op2 : word := (others => '0');
signal id_ex_ir : word := NOP;
signal id_ex_imm : word := (others => '0');
signal id_ex_insn_type : insn_type_t := OP_STALL;
signal id_ex_use_imm : std_logic := '0';
signal id_ex_alu_func : alu_func_t := ALU_NONE;
signal id_ex_branch_type : branch_type_t := BRANCH_NONE;
signal id_ex_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_load_type : load_type_t := LOAD_NONE;
signal id_ex_store_type : store_type_t := STORE_NONE;
signal id_ex_rf_we : std_logic := '0';
signal id_ex_taken : std_logic := '0';
signal id_ex_is_csr : std_logic := '0';
signal id_ex_csr_addr : csr_addr_t := (others => '0');
-------------------------------------------------
-- EX signals
-------------------------------------------------
signal ex_d : ex_in;
signal ex_q : ex_out;
signal ex_rf_data : word;
signal ex_load_pc : std_logic;
signal ex_data_addr : word;
signal ex_branch_mispredict : std_logic;
signal ex_csr_cycle_valid : std_logic;
signal ex_csr_timer_tick : std_logic;
signal ex_csr_instret : std_logic;
-------------------------------------------------
-- EX/MEM pipeline registers
-------------------------------------------------
signal ex_mem_load_pc : std_logic := '0';
signal ex_mem_next_pc : word := (others => '0');
signal ex_mem_rf_data : word := (others => '0');
signal ex_mem_return_addr : word := (others => '0');
signal ex_mem_load_type : load_type_t := LOAD_NONE;
signal ex_mem_store_type : store_type_t := STORE_NONE;
signal ex_mem_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal ex_mem_insn_type : insn_type_t := OP_STALL;
signal ex_mem_rf_we : std_logic := '0';
signal ex_mem_data_addr : word := (others => '0');
signal ex_mem_data_out : word := (others => '0');
signal ex_mem_rs1_addr : std_logic_vector(4 downto 0) := (others => '0');
signal ex_mem_rs2_addr : std_logic_vector(4 downto 0) := (others => '0');
signal ex_mem_csr_value : word := (others => '0');
signal ex_mem_is_csr : std_logic := '0';
-------------------------------------------------
-- MEM signals
-------------------------------------------------
signal mem_we : std_logic;
signal mem_re : std_logic;
signal mem_data_addr : word;
signal mem_data_out : word;
signal mem_lmd_lh : word;
signal mem_lmd_lb : word;
signal mem_lmd_lhu : word;
signal mem_lmd_lbu : word;
signal mem_lmd : word;
signal mem_rf_data_mux : word;
signal mem_data_out_mux : word;
-------------------------------------------------
-- MEM/WB pipeline registers
-------------------------------------------------
signal mem_wb_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal mem_wb_rf_we : std_logic := '0';
signal mem_wb_rf_data : word := (others => '0');
signal mem_wb_insn_type : insn_type_t := OP_STALL;
signal mem_wb_lmd : word := (others => '0');
signal mem_wb_is_csr : std_logic := '0';
-------------------------------------------------
-- WB signals
-------------------------------------------------
signal wb_rf_wr_addr : std_logic_vector(4 downto 0);
signal wb_rf_wr_en : std_logic;
signal wb_rf_wr_data : word;
-------------------------------------------------
-- Stalling / killing
-------------------------------------------------
signal branch_stall : std_logic;
signal if_kill : std_logic;
signal if_stall : std_logic;
signal id_kill : std_logic;
signal id_stall : std_logic;
signal full_stall : std_logic;
signal hazard_stall : std_logic;
-------------------------------------------------
-- Interrupt signals
-------------------------------------------------
signal in_irq : std_logic := '0';
signal trap_in_pipeline : std_logic := '0';
signal if_take_irq : std_logic := '0';
-------------------------------------------------
-- Simulation-specific signals
-------------------------------------------------
file regout_file : text open write_mode is g_regout_filename;
-- debug signals because VCD files can't contain information from VHDL records
signal debug_rs1 : std_logic_vector(4 downto 0);
signal debug_rs2 : std_logic_vector(4 downto 0);
signal debug_alu_result : word;
begin -- architecture Behavioral
-------------------------------------------------
-- Drive module outputs
-------------------------------------------------
-- instruction interface
insn_addr <= if_q.fetch_addr;
-- memory interface
data_read_en <= mem_re;
data_write_en <= mem_we;
data_addr <= mem_data_addr;
data_out <= mem_data_out;
-------------------------------------------------
-- Detect when stalling / killing is necessary
-------------------------------------------------
if_kill <= ex_mem_load_pc or (not insn_valid) or id_predict_taken or ex_branch_mispredict;
if_stall <= ex_mem_load_pc or branch_stall or full_stall or hazard_stall;
id_kill <= (ex_mem_load_pc or ex_branch_mispredict) and not id_predict_taken;
id_stall <= branch_stall or full_stall or hazard_stall;
-- being lazy and stalling on reads of CSR writes
hazard_stall <= '1' when ((id_ex_is_csr = '1' and id_ex_rd_addr = id_q.rs1 and id_q.rs1 /= "00000" and id_ex_rf_we = '1')
or (ex_mem_is_csr = '1' and ex_mem_rd_addr = id_q.rs1 and id_q.rs1 /= "00000" and ex_mem_rf_we = '1')
or (mem_wb_is_csr = '1' and mem_wb_rd_addr = id_q.rs1 and id_q.rs1 /= "00000" and mem_wb_rf_we = '1')
or (id_ex_is_csr = '1' and id_ex_rd_addr = id_q.rs2 and id_q.rs2 /= "00000" and id_ex_rf_we = '1')
or (ex_mem_is_csr = '1' and ex_mem_rd_addr = id_q.rs2 and id_q.rs2 /= "00000" and ex_mem_rf_we = '1')
or (mem_wb_is_csr = '1' and mem_wb_rd_addr = id_q.rs2 and id_q.rs2 /= "00000" and mem_wb_rf_we = '1'))
else '0';
-- stall when a PC redirection is imminent
branch_stall <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1'))
else '0';
-- stall on data not being available (data cache misses in the future)
full_stall <= '1' when (ex_mem_insn_type = OP_LOAD and data_in_valid = '0')
else '0';
---------------------------------------------------
-- Instruction fetch
---------------------------------------------------
-- inputs
if_d.stall <= if_stall;
if_d.load_pc <= ex_mem_load_pc or id_predict_taken or ex_branch_mispredict;
if_d.next_pc <= ex_mem_next_pc when (ex_mem_load_pc = '1') else id_branch_pc;
if_d.irq <= if_take_irq;
-- instantiation
if_stage : entity work.instruction_fetch(Behavioral)
port map (clk, rst_n, if_d, if_q);
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
if_id_reg_proc : process (clk, rst_n) is
begin -- process if_id_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
if_id_ir <= NOP;
if_id_pc <= (others => '0');
elsif (rising_edge(clk)) then
if (id_stall = '0') then
if (if_kill = '1') then
if_id_ir <= NOP;
else
if_id_ir <= insn_in;
end if;
if_id_pc <= if_q.pc;
end if;
end if;
end process if_id_reg_proc;
---------------------------------------------------
-- Instruction decode
---------------------------------------------------
-- register file
register_file : entity work.regfile(rtl)
port map (clk => clk,
addra => id_q.rs1,
addrb => id_q.rs2,
rega => rs1_data,
regb => rs2_data,
addrw => wb_rf_wr_addr,
dataw => wb_rf_wr_data,
we => wb_rf_wr_en);
-- instantiation of decoder
id_stage : entity work.instruction_decoder(Behavioral)
port map (if_id_ir, id_q);
-- debug b/c VCD files can't contain signals from VHDL records
gen_debug1 : if g_for_sim = true generate
debug_rs1 <= id_q.rs1;
debug_rs2 <= id_q.rs2;
end generate gen_debug1;
-- forwarding to ALU input multiplexer
id_op1 <= ex_q.alu_result when (id_q.rs1 = id_ex_rd_addr and id_q.rs1 /= "00000" and id_kill = '0') else
ex_mem_rf_data when (id_q.rs1 = ex_mem_rd_addr and id_q.rs1 /= "00000" and id_kill = '0') else
mem_wb_rf_data when (id_q.rs1 = mem_wb_rd_addr and id_q.rs1 /= "00000" and id_kill = '0') else
rs1_data;
-- forwarding to ALU input multiplexer
id_op2 <= ex_q.alu_result when (id_q.rs2 = id_ex_rd_addr and id_q.rs2 /= "00000" and id_kill = '0') else
ex_mem_rf_data when (id_q.rs2 = ex_mem_rd_addr and id_q.rs2 /= "00000" and id_kill = '0') else
mem_wb_rf_data when (id_q.rs2 = mem_wb_rd_addr and id_q.rs2 /= "00000" and id_kill = '0') else
rs2_data;
-- branch prediction: for now, predict backward branches as TAKEN
-- and forward as NOT TAKEN (optimized for loops)
id_predict_taken <= '1' when (id_q.imm(31) = '1' and (id_q.insn_type = OP_BRANCH or id_q.insn_type = OP_JAL or id_q.insn_type = OP_JALR))
else '0';
-- adder for branch prediction
id_branch_pc <= word(unsigned(if_id_pc) + unsigned(id_q.imm));
---------------------------------------------------
-- ID/EX pipeline registers
---------------------------------------------------
-- this is where instructions get issued,
-- controlled by id_stall, full_stall, and id_kill
id_ex_reg_proc : process (clk, rst_n) is
begin -- process id_ex_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
id_ex_pc <= (others => '0');
id_ex_rs1_addr <= (others => '0');
id_ex_rs2_addr <= (others => '0');
id_ex_op1 <= (others => '0');
id_ex_op2 <= (others => '0');
id_ex_ir <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_is_csr <= '0';
id_ex_csr_addr <= (others => '0');
elsif (rising_edge(clk)) then
id_ex_taken <= id_predict_taken;
if (id_stall = '0' and full_stall = '0') then
id_ex_rs1_addr <= id_q.rs1;
id_ex_rs2_addr <= id_q.rs2;
id_ex_op1 <= id_op1;
id_ex_op2 <= id_op2;
id_ex_use_imm <= id_q.use_imm;
-- to kill an instruction
if (id_kill = '1') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_STALL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
id_ex_is_csr <= '0';
id_ex_csr_addr <= (others => '0');
else
id_ex_pc <= if_id_pc;
id_ex_ir <= if_id_ir;
id_ex_rd_addr <= id_q.rd;
id_ex_insn_type <= id_q.insn_type;
id_ex_rf_we <= id_q.rf_we;
id_ex_use_imm <= id_q.use_imm;
id_ex_imm <= id_q.imm;
id_ex_alu_func <= id_q.alu_func;
id_ex_branch_type <= id_q.branch_type;
id_ex_load_type <= id_q.load_type;
id_ex_store_type <= id_q.store_type;
id_ex_is_csr <= id_q.is_csr;
id_ex_csr_addr <= id_q.csr_addr;
end if;
elsif (id_stall = '1' and full_stall = '0') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_STALL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
id_ex_is_csr <= '0';
id_ex_csr_addr <= (others => '0');
end if;
end if;
end process id_ex_reg_proc;
---------------------------------------------------
-- print instructions as they are issued
---------------------------------------------------
print_decode : if (g_for_sim = true) generate
print_decode_proc : process (id_ex_ir, id_ex_pc, id_ex_insn_type, id_ex_taken) is
variable l : line;
variable op1, op2 : word;
begin -- process print_decode_proc
write(l, to_integer(unsigned(id_ex_pc)));
write(l, string'(" : 0x"));
write(l, hstr(id_ex_ir));
writeline(output, l);
-- differentiate NOPs in the simulation output
if (id_ex_ir = NOP) then
write(l, string'("Instruction type: NOP"));
writeline(output, l);
else
print_insn(id_ex_insn_type);
end if;
print(id_ex_insn_type);
if id_ex_insn_type = OP_ALU then
if (id_ex_rs1_addr = ex_mem_rd_addr and ex_mem_insn_type = OP_LOAD) then
write(l, string'("op1 := mem_lmd"));
op1 := mem_lmd;
elsif (id_ex_rs1_addr = mem_wb_rd_addr and mem_wb_insn_type = OP_LOAD) then
write(l, string'("op1 := wb_rf_wr_data"));
op1 := wb_rf_wr_data;
elsif (ex_d.insn_type = OP_BRANCH or
ex_d.insn_type = OP_JAL or
ex_d.insn_type = OP_JALR or
ex_d.insn_type = OP_AUIPC) then
write(l, string'("op1 := id_ex_pc"));
op1 := id_ex_pc;
else
write(l, string'("op1 := id_ex_op1"));
op1 := id_ex_op1;
end if;
writeline(output, l);
if (id_ex_rs2_addr = ex_mem_rd_addr and ex_mem_insn_type = OP_LOAD) then
write(l, string'("op2 := mem_lmd"));
op2 := mem_lmd;
elsif (id_ex_rs2_addr = mem_wb_rd_addr and mem_wb_insn_type = OP_LOAD) then
write(l, string'("op2 := wb_rf_wr_data"));
op2 := wb_rf_wr_data;
elsif ((id_ex_insn_type = OP_ALU and id_ex_use_imm = '1') or
id_ex_insn_type = OP_BRANCH or
id_ex_insn_type = OP_JAL or
id_ex_insn_type = OP_JALR or
id_ex_insn_type = OP_LOAD or
id_ex_insn_type = OP_STORE or
id_ex_insn_type = OP_AUIPC) then
write(l, string'("op2 := id_ex_imm"));
op1 := id_ex_imm;
else
write(l, string'("op2 := id_ex_op2"));
op2 := id_ex_op2;
end if;
writeline(output, l);
write(l, string'(" Op1: "));
write(l, hstr(op1));
write(l, string'(", Op2: "));
write(l, hstr(op2));
writeline(output, l);
end if;
if id_ex_taken = '1' then
write(l, string'("Predicting branch as taken, redirecting PC to "));
writeline(output, l);
print(id_branch_pc);
end if;
if (ex_branch_mispredict = '1') then
write(l, string'("Branch incorrectly predicted, continuing . . ."));
writeline(output, l);
print(id_branch_pc);
end if;
writeline(output, l);
end process print_decode_proc;
end generate print_decode;
---------------------------------------------------
-- Instruction execution stage
---------------------------------------------------
-- inputs (includes multiplexers for ALU operands from the LMD "Load Memory
-- Data" datapath)
ex_d.insn_type <= id_ex_insn_type;
ex_d.npc <= id_ex_pc;
ex_d.op1 <= mem_lmd when (id_ex_rs1_addr = ex_mem_rd_addr and ex_mem_insn_type = OP_LOAD)
else wb_rf_wr_data when (id_ex_rs1_addr = mem_wb_rd_addr and mem_wb_insn_type = OP_LOAD)
else id_ex_op1;
ex_d.op2 <= mem_lmd when (id_ex_rs2_addr = ex_mem_rd_addr and ex_mem_insn_type = OP_LOAD)
else wb_rf_wr_data when (id_ex_rs2_addr = mem_wb_rd_addr and mem_wb_insn_type = OP_LOAD)
else id_ex_op2;
ex_d.use_imm <= id_ex_use_imm;
ex_d.alu_func <= id_ex_alu_func;
ex_d.branch_type <= id_ex_branch_type;
ex_d.imm <= id_ex_imm;
-- instantiation of execution stage
ex_stage : entity work.instruction_executor(Behavioral)
port map (ex_d, ex_q);
-- inputs to CSRs
ex_csr_cycle_valid <= '1' when rst_n = '1' else '0';
ex_csr_timer_tick <= '0'; -- TODO: implement
ex_csr_instret <= mem_we or wb_rf_wr_en;
-- instantiation of CSRs (core specific registers)
inst_csrs : entity work.csr(behavioral)
port map (clk => clk,
en => id_ex_is_csr,
addr => id_ex_csr_addr,
valid => ex_csr_cycle_valid,
tick => ex_csr_timer_tick,
instret => ex_csr_instret,
value => ex_mem_csr_value);
-- simulation-specific signal
gen_debug2 : if g_for_sim = true generate
debug_alu_result <= ex_q.alu_result;
end generate gen_debug2;
-- multiplexer for Register File write data
ex_rf_data <= ex_q.return_addr when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR) else
id_ex_imm when (id_ex_insn_type = OP_LUI) else
ex_q.alu_result;
-- selecter for loading the PC with a new value
ex_load_pc <= '1' when (id_ex_taken = '0' and (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1'))) else '0';
-- check for misprediction
ex_branch_mispredict <= '1' when (id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '0' and id_ex_taken = '1') else '0';
-- multiplexer for data memory address
ex_data_addr <= ex_q.alu_result when (id_ex_insn_type = OP_LOAD or id_ex_insn_type = OP_STORE) else ex_mem_data_addr;
---------------------------------------------------
-- EX/MEM pipeline registers
---------------------------------------------------
-- purpose: Pipeline data between EX and MEM stages
ex_mem_regs_proc : process (clk, rst_n) is
begin -- process ex_mem_regs_proc
if (rst_n = '0') then -- asynchronous reset (active low)
ex_mem_load_pc <= '0';
ex_mem_next_pc <= (others => '0');
ex_mem_rf_data <= (others => '0');
ex_mem_return_addr <= (others => '0');
ex_mem_load_type <= LOAD_NONE;
ex_mem_store_type <= STORE_NONE;
ex_mem_rd_addr <= (others => '0');
ex_mem_insn_type <= OP_STALL;
ex_mem_rf_we <= '0';
ex_mem_is_csr <= '0';
elsif (rising_edge(clk)) then
if (full_stall = '0') then
ex_mem_next_pc <= ex_q.alu_result;
ex_mem_load_pc <= ex_load_pc;
ex_mem_rf_data <= ex_rf_data;
ex_mem_data_addr <= ex_data_addr;
ex_mem_data_out <= id_ex_op2;
ex_mem_load_type <= id_ex_load_type;
ex_mem_store_type <= id_ex_store_type;
ex_mem_rd_addr <= id_ex_rd_addr;
ex_mem_insn_type <= id_ex_insn_type;
ex_mem_rf_we <= id_ex_rf_we;
ex_mem_rs1_addr <= id_ex_rs1_addr; -- only needed for forwarding
ex_mem_rs2_addr <= id_ex_rs2_addr; -- only needed for forwarding
ex_mem_is_csr <= id_ex_is_csr;
end if;
end if;
end process ex_mem_regs_proc;
---------------------------------------------------
-- Memory stage
---------------------------------------------------
-- memory access logic
mem_we <= '1' when ex_mem_insn_type = OP_STORE else '0';
mem_re <= '1' when ex_mem_insn_type = OP_LOAD else '0';
-- first level of data memory output muxing
mem_data_out_mux <= mem_wb_lmd when (mem_wb_insn_type = OP_LOAD) else ex_mem_data_out;
-- data memory interface multiplexers
mem_data_addr <= ex_mem_data_addr;
mem_data_out <= X"0000" & mem_data_out_mux(15 downto 0) when ex_mem_store_type = SH else
X"000000" & mem_data_out_mux(7 downto 0) when ex_mem_store_type = SB else
mem_data_out_mux;
-- load halfword (signed)
mem_lmd_lh <= word(resize(signed(data_in(15 downto 0)), word'length));
-- load byte (signed)
mem_lmd_lb <= word(resize(signed(data_in(7 downto 0)), word'length));
-- load halfword unsigned
mem_lmd_lhu <= word(resize(unsigned(data_in(15 downto 0)), word'length));
-- load byte unsigned
mem_lmd_lbu <= word(resize(unsigned(data_in(7 downto 0)), word'length));
-- Load Memory Data register input
with ex_mem_load_type select
mem_lmd <=
mem_lmd_lhu when LHU,
mem_lmd_lbu when LBU,
mem_lmd_lh when LH,
mem_lmd_lb when LB,
data_in when others;
-- mux for register-file writeback data
mem_rf_data_mux <= ex_mem_csr_value when ex_mem_is_csr = '1'
else mem_lmd when ex_mem_insn_type = OP_LOAD
else ex_mem_rf_data;
---------------------------------------------------
-- MEM/WB pipeline registers
---------------------------------------------------
-- purpose: Create the MEM/WB pipeline registers
mem_wb_regs : process (clk, rst_n) is
begin -- process mem_wb_regs
if (rst_n = '0') then -- asynchronous reset (active low)
mem_wb_rd_addr <= (others => '0');
mem_wb_rf_we <= '0';
mem_wb_rf_data <= (others => '0');
mem_wb_insn_type <= OP_STALL;
elsif (rising_edge(clk)) then
if (full_stall = '0') then
mem_wb_rd_addr <= ex_mem_rd_addr;
mem_wb_rf_we <= ex_mem_rf_we;
mem_wb_insn_type <= ex_mem_insn_type;
mem_wb_rf_data <= mem_rf_data_mux;
mem_wb_is_csr <= ex_mem_is_csr;
if (data_in_valid = '1') then
mem_wb_lmd <= mem_lmd;
end if;
else
mem_wb_rf_we <= '0';
mem_wb_is_csr <= '0';
end if;
end if;
end process mem_wb_regs;
---------------------------------------------------
-- Writeback stage
---------------------------------------------------
wb_rf_wr_addr <= mem_wb_rd_addr;
wb_rf_wr_en <= mem_wb_rf_we;
wb_rf_wr_data <= mem_wb_rf_data;
---------------------------------------------------
-- print register file writebacks
---------------------------------------------------
log_regs : if (g_for_sim = true) generate
log_regs_proc : process (wb_rf_wr_addr, wb_rf_wr_en, wb_rf_wr_data) is
variable l : line;
begin -- process print_decode_proc
if wb_rf_wr_en = '1' then
write(l, hstr(wb_rf_wr_addr));
write(l, string'(", "));
write(l, hstr(wb_rf_wr_data));
writeline(regout_file, l);
end if;
end process log_regs_proc;
end generate log_regs;
end architecture Behavioral;
|
bsd-3-clause
|
a810525341a5e1eb9572769326def48c
| 0.442912 | 3.738642 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/Thor_buffer.vhd
| 1 | 3,389 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.NoCPackage.all;
entity Thor_buffer is
port(
clock: in std_logic;
reset: in std_logic;
clock_rx: in std_logic;
rx: in std_logic;
data_in: in regflit;
credit_o: out std_logic;
h: out std_logic;
ack_h: in std_logic;
data_av: out std_logic;
data: out regflit;
data_ack: in std_logic;
sender: out std_logic);
end Thor_buffer;
architecture Thor_buffer of Thor_buffer is
type fila_out is (REQ_ROUTING, SEND_DATA);
signal next_state, current_state : fila_out;
signal pull: std_logic;
signal bufferHead : regflit;
signal has_data: std_logic;
signal has_data_and_sending : std_logic;
signal counter : integer;
signal sending : std_logic;
signal sent : std_logic;
begin
circularFifoBuffer : entity work.fifo_buffer
generic map(BUFFER_DEPTH => TAM_BUFFER ,
BUFFER_WIDTH => regflit'length)
port map(
reset => reset,
clock => clock_rx,
tail => data_in,
push => rx,
pull => pull,
counter => counter,
head => bufferHead
);
data <= bufferHead;
data_av <= has_data_and_sending;
credit_o <= '1' when (counter /= TAM_BUFFER or pull = '1') else '0';
sender <= sending;
h <= has_data and not sending;
pull <= data_ack and has_data_and_sending;
has_data <= '1' when (counter /= 0) else '0';
has_data_and_sending <= has_data and sending;
process(current_state, ack_h, sent)
begin
next_state <= current_state;
case current_state is
when REQ_ROUTING =>
if ack_h = '1' then
next_state <= SEND_DATA;
end if;
when SEND_DATA =>
if sent = '1' then
next_state <= REQ_ROUTING;
end if;
end case;
end process;
process(reset, clock)
begin
if reset = '1' then
current_state <= REQ_ROUTING;
elsif rising_edge(clock) then
current_state <= next_state;
end if;
end process;
process(current_state, sent)
begin
case current_state is
when SEND_DATA =>
sending <= not sent;
when others =>
sending <= '0';
end case;
end process;
process(reset, clock)
variable flit_index : integer;
variable counter_flit : integer;
begin
if reset = '1' then
sent <= '0';
elsif rising_edge(clock) then
if sending = '1' then
if data_ack = '1' and has_data = '1' then
sent <= '0';
if flit_index = 1 then
counter_flit := to_integer(unsigned(bufferHead));
elsif counter_flit /= 1 then
counter_flit := counter_flit - 1;
else -- counter_flit = 1
sent <= '1';
end if;
flit_index := flit_index + 1;
else
end if;
else
flit_index := 0;
counter_flit := 0;
sent <= '0';
end if;
end if;
end process;
end Thor_buffer;
|
lgpl-3.0
|
96ca3c4e40ef58f1c2906be86d76a54d
| 0.501918 | 3.913395 | false | false | false | false |
Dasio/FIT-Projects
|
INP/proj2/cpu.vhd
| 1 | 8,338 |
-- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter)
-- Copyright (C) 2014 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Dávid Mikuš (xmikus15)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity cpu is
port (
CLK : in std_logic; -- hodinovy signal
RESET : in std_logic; -- asynchronni reset procesoru
EN : in std_logic; -- povoleni cinnosti procesoru
-- synchronni pamet RAM
DATA_ADDR : out std_logic_vector(12 downto 0); -- adresa do pameti
DATA_WDATA : out std_logic_vector(7 downto 0); -- mem[DATA_ADDR] <- DATA_WDATA pokud DATA_EN='1'
DATA_RDATA : in std_logic_vector(7 downto 0); -- DATA_RDATA <- ram[DATA_ADDR] pokud DATA_EN='1'
DATA_RDWR : out std_logic; -- cteni (0) / zapis (1)
DATA_EN : out std_logic; -- povoleni cinnosti
-- vstupni port
IN_DATA : in std_logic_vector(7 downto 0); -- IN_DATA <- stav klavesnice pokud IN_VLD='1' a IN_REQ='1'
IN_VLD : in std_logic; -- data platna
IN_REQ : out std_logic; -- pozadavek na vstup data
-- vystupni port
OUT_DATA : out std_logic_vector(7 downto 0); -- zapisovana data
OUT_BUSY : in std_logic; -- LCD je zaneprazdnen (1), nelze zapisovat
OUT_WE : out std_logic -- LCD <- OUT_DATA pokud OUT_WE='1' a OUT_BUSY='0'
);
end cpu;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of cpu is
-- zde dopiste potrebne deklarace signalu
signal pc_reg : std_logic_vector(12 downto 0);
signal pc_inc : std_logic;
signal pc_dec : std_logic;
signal ptr_reg : std_logic_vector(12 downto 0);
signal ptr_inc : std_logic;
signal ptr_dec : std_logic;
signal cnt_reg : std_logic_vector(12 downto 0);
signal cnt_inc : std_logic;
signal cnt_dec : std_logic;
-- Instrukcie
type instructions is (incPtr, decPtr, incValue, decValue, whileB, whileE, putchar, getchar, nop, halt);
signal ireg_dec : instructions;
-- Automat
type fsm_state is (sidle, sfetch, sdecode, sIncPtr, sDecPtr, sIncValue1, sDecValue1,
sDecValue2,sIncValue2, sPutChar1,sPutChar2,sGetChar1,sGetChar2,
sWhileB1,sWhileB2,sWhileB3, sWhileB4, sWhileE1, sWhileE2,sWhileE3,sWhileE4,
sNop, shalt);
signal presentState : fsm_state;
signal nextState : fsm_state;
-- Multiplexori
signal mx1 : std_logic;
signal mx2 : std_logic_vector (1 downto 0);
begin
-- zde dopiste vlastni VHDL kod
-- Programovy citac
pc_cntr: process (RESET, CLK)
begin
if (RESET='1') then
pc_reg <= (others=>'0');
-- nabezna hrana
elsif (CLK'event) and (CLK='1') then
-- incrementuje programovy citac
if (pc_inc = '1') then
pc_reg <= pc_reg + 1;
end if;
-- deceremntuje programovy citac
if(pc_dec = '1') then
pc_reg <= pc_reg - 1;
end if;
end if;
end process;
-- Citac PTR
ptr: process(RESET,CLK)
begin
if (RESET = '1') then
ptr_reg <= "1000000000000"; -- 0x1000
elsif (CLK'event) and (CLK='1') then
if(ptr_inc = '1') then
ptr_reg <= ptr_reg + 1;
end if;
if(ptr_dec = '1') then
ptr_reg <= ptr_reg - 1;
end if;
end if;
end process;
-- Citac CNT
-- nepouzite
cnt:process(RESET,CLK)
begin
if (RESET = '1') then
cnt_reg <= (others => '0');
elsif (CLK'event) and (CLK='1') then
if(cnt_inc = '1') then
cnt_reg <= cnt_reg + 1;
end if;
if(cnt_dec = '1') then
cnt_reg <= cnt_reg - 1;
end if;
end if;
end process;
-- Multiplexori
with mx1 select
DATA_ADDR <= pc_reg when '0',
ptr_reg when '1',
(others => 'Z') when others;
with mx2 select
DATA_WDATA <= IN_DATA when "00",
DATA_RDATA + 1 when "01",
DATA_RDATA - 1 when "10",
(others => 'Z') when others;
-- Dekodovanie instrukcii
process (DATA_RDATA)
begin
case (DATA_RDATA) is
when X"3E" => ireg_dec <= incPtr;
when X"3C" => ireg_dec <= decPtr;
when X"2B" => ireg_dec <= incValue;
when X"2D" => ireg_dec <= decValue;
when X"5B" => ireg_dec <= whileB;
when X"5D" => ireg_dec <= whileE;
when X"2E" => ireg_dec <= putchar;
when X"2C" => ireg_dec <= getchar;
when X"00" => ireg_dec <= halt;
when others => ireg_dec <= nop;
end case;
end process;
fsm_pstate: process(CLK,RESET)
begin
if (RESET = '1') then
presentState <= sidle;
elsif (CLK'event) and (CLK='1') then
if(EN ='1') then
presentState <= nextState;
end if;
end if;
end process;
fsm_nextstate: process(presentState, ireg_dec, OUT_BUSY, DATA_RDATA, IN_VLD, EN, IN_DATA, cnt_reg)
begin
-- INIT
mx1 <= '0';
mx2 <= "00";
DATA_EN <= '0';
pc_inc <= '0';
pc_dec <= '0';
ptr_inc <= '0';
ptr_dec <= '0';
cnt_inc <= '0';
cnt_dec <= '0';
OUT_WE <= '0';
IN_REQ <= '0';
nextState <= sfetch;
case presentState is
when sidle =>
nextState <= sfetch;
when sfetch =>
mx1 <= '0'; -- nacitanie pc_reg do DATA_ADDR
DATA_EN <= '1';
DATA_RDWR <= '0';
nextState <= sdecode;
when sdecode =>
case ireg_dec is
when incPtr =>
nextState <= sIncPtr;
when decPtr =>
nextState <= sDecPtr;
when incValue =>
nextState <= sIncValue1;
when decValue =>
nextState <= sDecValue1;
when getchar =>
nextState <= sGetChar1;
when putchar =>
nextState <= sPutChar1;
when whileB =>
nextState <= sWhileB1;
when whileE =>
nextState <= sWhileE1;
when nop =>
nextState <= sNop;
when halt =>
nextState <= shalt;
when others =>
nextState <= sfetch;
end case;
when sIncPtr =>
pc_inc <= '1';
pc_dec <= '0';
ptr_inc <= '1';
ptr_dec <= '0';
nextState <= sfetch;
when sDecPtr =>
pc_inc <= '1';
pc_dec <= '0';
ptr_inc <= '0';
ptr_dec <= '1';
nextState <= sfetch;
when sIncValue1 =>
DATA_EN <= '1';
mx1 <= '1';
DATA_RDWR <= '0';
nextState <= sIncValue2;
when sIncValue2 =>
mx1 <= '1';
mx2 <= "01";
DATA_RDWR <= '1';
DATA_EN <= '1';
pc_inc <= '1';
nextState <= sfetch;
when sDecValue1 =>
DATA_EN <= '1';
mx1 <= '1';
DATA_RDWR <= '0';
nextState <= sDecValue2;
when sDecValue2 =>
mx1 <= '1';
mx2 <= "10";
DATA_RDWR <= '1';
DATA_EN <= '1';
pc_inc <= '1';
nextState <= sfetch;
when sGetChar1 =>
IN_REQ <= '1';
nextState <= sGetChar2;
when sGetChar2 =>
if (IN_VLD = '0') then
nextState <= sGetChar2;
else
mx1 <= '1';
mx2 <= "00"; -- citanie zo vstupu
DATA_RDWR <= '1';
DATA_EN <= '1';
pc_inc <= '1';
nextState <= sfetch;
end if;
when sPutChar1 =>
DATA_EN <= '1';
mx1 <= '1';
DATA_RDWR <= '0';
nextState <= sPutChar2;
when sPutChar2 =>
if (OUT_BUSY = '0') then
OUT_DATA <= DATA_RDATA;
OUT_WE <= '1';
pc_inc <= '1';
nextState <= sfetch;
else
nextState <= sPutChar2;
end if;
--Cykly
when sWhileB1 =>
mx1 <= '1';
DATA_RDWR <= '0';
DATA_EN <= '1';
pc_inc <= '1';
if (DATA_RDATA = 0) then
nextState <= sWhileB2;
else
nextState <= sfetch;
end if;
when sWhileB2 =>
mx1 <= '0';
DATA_EN <= '1';
nextState <= sWhileB3;
when sWhileB3 =>
pc_inc <= '1';
if (ireg_dec = whileE) then
nextState <= sfetch;
else
nextState <= sWhileB2;
end if;
when sWhileE1 =>
mx1 <= '1';
DATA_RDWR <= '0';
DATA_EN <= '1';
nextState <= sWhileE2;
when sWhileE2 =>
if (DATA_RDATA = 0) then
pc_inc <= '1';
nextState <= sfetch;
else
pc_dec <= '1';
nextState <= sWhileE3;
end if;
when sWhileE3 =>
mx1<= '0';
DATA_EN <= '1';
nextState <= sWhileE4;
when sWhileE4 =>
if (ireg_dec = whileB) then
nextState <= sfetch;
else
pc_dec <= '1';
nextState <= sWhileE3;
end if;
when sNop =>
pc_inc <= '1';
nextState <= sidle;
when shalt =>
nextState <= shalt;
when others =>
nextState <= sNop;
end case;
end process;
end behavioral;
|
mit
|
82d4c9753c2429461915b26f6e78561c
| 0.551583 | 2.889428 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_0_0/synth/DemoInterconnect_axi_spi_master_0_0.vhd
| 1 | 11,283 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_0_arch OF DemoInterconnect_axi_spi_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_axi_spi_master_0_0_arch: ARCHITECTURE IS "axi_spi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_axi_spi_master_0_0_arch : ARCHITECTURE IS "DemoInterconnect_axi_spi_master_0_0,axi_spi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_0_arch;
|
mit
|
5842a52bad72193e1bc386fa0123e939
| 0.714349 | 3.191796 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/control_unit.vhd
| 1 | 6,903 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_unit is
Port (
-- inputs
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
enable_neander : in STD_LOGIC;
N : in STD_LOGIC;
Z : in STD_LOGIC;
s_exec_nop, s_exec_sta, s_exec_lda, s_exec_add, s_exec_or, s_exec_shr, s_exec_shl, s_exec_mul,
s_exec_and, s_exec_not, s_exec_jmp, s_exec_jn, s_exec_jz, s_exec_hlt : in STD_LOGIC;
-- outputs--
-- operation selector
sel_ula : out STD_LOGIC_VECTOR(2 downto 0);
-- registers loads
loadAC : out STD_LOGIC;
loadPC : out STD_LOGIC;
loadREM : out STD_LOGIC;
loadRDM : out STD_LOGIC;
loadRI : out STD_LOGIC;
loadN : out STD_LOGIC;
loadZ : out STD_LOGIC;
-- write in memory
wr_enable_mem : out STD_LOGIC_VECTOR (0 downto 0);
-- selector for mux_rem: 0 for PC, 1 for RDM
sel : out STD_LOGIC;
-- Program Counter increment
PC_inc : out STD_LOGIC;
-- selector for mux_rdm: 0 for mem(read), 1 for AC
sel_mux_RDM : out STD_LOGIC;
-- stop signal
stop : out STD_LOGIC
);
end control_unit;
architecture Behavioral of control_unit is
type state_machine is (IDLE, BUSCA_INSTRUCAO, LER_INSTRUCAO, CARREGA_RI,
EXEC_STA2, BUSCA_DADOS, BUSCA_ENDERECO, TRATA_JUMP, TRATA_JUMP_FAIL,
READ_MEMORY, EXEC_STA, TRATA_HLT, EXEC_ULA, EXEC_ULA2);
signal current_state : state_machine;
signal next_state : state_machine;
signal stop_s : STD_LOGIC;
begin
process (clk_in, rst_in)
variable state_timer: integer; -- states for two cicles
begin
if (rst_in = '1') then
stop_s <= '0';
loadAC <= '0';
loadPC <= '0';
PC_inc <= '0';
loadREM <= '0';
loadRDM <= '0';
loadRI <= '0';
loadN <= '0';
loadZ <= '0';
wr_enable_mem <= "0";
state_timer := 1;
next_state <= IDLE;
elsif (clk_in = '1' and clk_in'EVENT) then
case current_state is
when IDLE =>
if (enable_neander = '1' and stop_s = '0') then -- start signal
next_state <= BUSCA_INSTRUCAO;
else
next_state <= IDLE;
end if;
-- E0: REM <- PC
when BUSCA_INSTRUCAO =>
sel_mux_RDM <= '0';
loadAC <= '0';
loadPC <= '0';
PC_inc <= '0';
loadRDM <= '0';
loadRI <= '0';
wr_enable_mem <= "0";
loadN <= '0';
loadZ <= '0';
-- select 0 for PC->REM
sel <= '0';
-- load REM
loadREM <= '1';
next_state <= LER_INSTRUCAO;
-- E1: RDM <- MEM(read), PC+
when LER_INSTRUCAO =>
loadREM <= '0';
loadRDM <= '1';
PC_inc <= '1';
next_state <= CARREGA_RI;
-- E2: RI <- RDM
when CARREGA_RI =>
loadRDM <= '0';
PC_inc <= '0';
loadRI <= '1';
if (s_exec_hlt = '1') then -- HLT
next_state <= TRATA_HLT;
elsif (s_exec_nop = '1') then -- NOP
next_state <= BUSCA_INSTRUCAO;
elsif (s_exec_not = '1') then -- NOT
next_state <= EXEC_ULA2;
elsif ((s_exec_jn = '1') and (N = '0')) or ((s_exec_jz = '1') and (z = '0')) then -- jump fail
next_state <= TRATA_JUMP_FAIL;
else
next_state <= BUSCA_DADOS;
end if;
-- E3: REM <- PC
when BUSCA_DADOS =>
loadRI <= '0';
sel <= '0';
loadREM <= '1';
next_state <= READ_MEMORY;
-- E4: RDM <- MEM(read), PC+
WHEN READ_MEMORY =>
loadREM <= '0';
loadRDM <= '1';
PC_inc <= '1';
if (s_exec_add = '1') then -- ADD
next_state <= BUSCA_ENDERECO;
elsif (s_exec_or = '1') then -- OR
next_state <= BUSCA_ENDERECO;
elsif (s_exec_and = '1') then -- AND
next_state <= BUSCA_ENDERECO;
elsif (s_exec_lda = '1') then -- LDA
next_state <= BUSCA_ENDERECO;
elsif (s_exec_shr = '1') then -- SHR
next_state <= BUSCA_ENDERECO;
elsif (s_exec_shl = '1') then -- SHL
next_state <= BUSCA_ENDERECO;
elsif (s_exec_mul = '1') then -- MUL
next_state <= BUSCA_ENDERECO;
elsif (s_exec_sta = '1') then -- STA
next_state <= BUSCA_ENDERECO;
elsif ((s_exec_jmp = '1') or ((s_exec_jn = '1') and (N = '1')) or ((s_exec_jz = '1') and (z = '1'))) then -- real jump
next_state <= TRATA_JUMP;
else
next_state <= IDLE;
end if;
-- E5: REM <- RDM
when BUSCA_ENDERECO =>
loadRDM <= '0';
PC_inc <= '0';
sel <= '1'; -- select 1 for RDM->REM
loadREM <= '1';
if (s_exec_add = '1') then -- ADD
next_state <= EXEC_ULA;
elsif (s_exec_or = '1') then -- OR
next_state <= EXEC_ULA;
elsif (s_exec_and = '1') then -- AND
next_state <= EXEC_ULA;
elsif (s_exec_lda = '1') then -- LDA
next_state <= EXEC_ULA;
elsif (s_exec_shr = '1') then -- SHR
next_state <= EXEC_ULA;
elsif (s_exec_shl = '1') then -- SHL
next_state <= EXEC_ULA;
elsif (s_exec_mul = '1') then -- MUL
next_state <= EXEC_ULA;
elsif (s_exec_sta = '1') then -- STA
next_state <= EXEC_STA;
end if;
-- E6: RDM <- MEM(read)
when EXEC_ULA =>
loadREM <= '0';
loadRDM <= '1';
if (s_exec_add = '1') then -- ADD
sel_ula <= "000";
elsif (s_exec_or = '1') then -- OR
sel_ula <= "010";
elsif (s_exec_and = '1') then -- AND
sel_ula <= "001";
elsif (s_exec_not = '1') then -- NOT
sel_ula <= "011";
elsif (s_exec_lda = '1') then -- LDA
sel_ula <= "100";
elsif (s_exec_shr = '1') then -- SHR
sel_ula <= "101";
elsif (s_exec_shl = '1') then -- SHL
sel_ula <= "110";
elsif (s_exec_mul = '1') then -- MUL
sel_ula <= "111";
end if;
next_state <= EXEC_ULA2;
-- E7: AC <- ULA
when EXEC_ULA2 =>
loadRDM <= '0';
loadRI <= '0';
loadAC <= '1';
loadN <= '1';
loadZ <= '1';
next_state <= BUSCA_INSTRUCAO;
-- E8: RDM <- AC
when EXEC_STA =>
loadREM <= '0';
sel_mux_RDM <= '1'; -- select 1 for AC->RDM
loadRDM <= '1';
next_state <= EXEC_STA2;
-- E9: MEM <- RDM(write)
when EXEC_STA2 =>
sel_mux_RDM <= '0';
loadRDM <= '0';
wr_enable_mem <= "1";
next_state <= BUSCA_INSTRUCAO;
-- E10: PC <- RDM
when TRATA_JUMP =>
loadRDM <= '0';
PC_inc <= '0';
loadPC <= '1';
next_state <= BUSCA_INSTRUCAO;
-- E11: PC+
when TRATA_JUMP_FAIL =>
loadRI <= '0';
PC_inc <= '1';
next_state <= BUSCA_INSTRUCAO;
-- E12: STOP
when TRATA_HLT =>
loadRI <= '0';
stop_s <= '1';
next_state <= IDLE;
-- others
when others =>
next_state <= IDLE;
end case;
if state_timer = 0 then -- states for two cicles
current_state <= next_state;
state_timer := 1;
else
current_state <= current_state;
state_timer := state_timer -1;
end if;
end if;
stop <= stop_s;
end process;
end;
|
mit
|
55c09635f75e55a322194fd7e9697b17
| 0.532387 | 2.728747 | false | false | false | false |
rmilfont/Phoenix
|
outputModule.vhd
| 1 | 4,124 |
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
entity outputModule is
generic(
address: regflit
);
port(
clock: in std_logic;
tx: in std_logic;
data: in regflit;
currentTime: std_logic_vector(4*TAM_FLIT-1 downto 0)
);
end;
architecture outputModule of outputModule is
begin
process(clock, tx, data, currentTime)
variable cont : integer := 0;
variable remaining_flits : std_logic_vector(TAM_FLIT-1 downto 0) := (others=>'0');
file my_output : TEXT open WRITE_MODE is "Out/out"&to_hstring(address)&".txt";
variable my_output_line : LINE;
variable timeSourceCore: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable timeSourceNet: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable timeTarget: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable aux_latency: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0'); --latência desde o tempo de criação do pacote (em decimal)
variable control_pkt: std_logic;
begin
if(clock'event and clock='0' and tx='1')then
-- DADOS DE CONTROLE:
if (cont = 0) then -- destino
write(my_output_line, string'(to_hstring(data)));
write(my_output_line, string'(" "));
cont := 1;
control_pkt := data((TAM_FLIT-1));
elsif (cont = 1) then -- tamanho
write(my_output_line, string'(to_hstring(data)));
write(my_output_line, string'(" "));
remaining_flits := data;
cont := 2;
-- DADOS DO PAYLOAD:
elsif (remaining_flits > 1) then
remaining_flits := remaining_flits - 1; -- vai sair quando remaining_flits for 0
if (cont >= 3 and cont <= 6 and control_pkt='0') then -- captura timestamp
timeSourceCore((TAM_FLIT*(7-cont)-1) downto (TAM_FLIT*(6-cont))) := data;
end if;
if (cont >= 9 and cont <= 12 and control_pkt='0') then -- captura timestamp
timeSourceNet((TAM_FLIT*(13-cont)-1) downto (TAM_FLIT*(12-cont))) := data;
end if;
write(my_output_line, string'(to_hstring(data)));
write(my_output_line, string'(" "));
cont := cont + 1;
-- ultimo flit do pacote
else
write(my_output_line, string'(to_hstring(data)));
--writeline(my_output, my_output_line);
cont := 0;
if (control_pkt='0') then
timeTarget := currentTime;
for j in (TAM_FLIT/4) downto 1 loop
write(my_output_line, string'(" "));
write(my_output_line, string'(to_hstring(timeTarget( TAM_FLIT*j-1 downto TAM_FLIT*(j-1) ))));
end loop;
write(my_output_line, string'(" "));
write(my_output_line, string'(integer'image(CONV_INTEGER(timeSourceCore((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
write(my_output_line, string'(integer'image(CONV_INTEGER(timeSourceNet((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
write(my_output_line, string'(integer'image(CONV_INTEGER(timeTarget((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
aux_latency := (timeTarget-timeSourceCore);
write(my_output_line, string'(integer'image(CONV_INTEGER(aux_latency((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
write(my_output_line, string'("0"));
writeline(my_output, my_output_line);
end if;
end if;
end if; --end if clock'event...
end process;
end outputModule;
|
lgpl-3.0
|
e529d0b4bd9b958d7197b4a1f00b9190
| 0.531523 | 3.950192 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AB_TB.vhd
| 1 | 1,010 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AB_TB IS
END LatchSR_AB_TB;
ARCHITECTURE behavior OF LatchSR_AB_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AB
PORT(
Sn : IN std_logic;
Rn : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
--Inputs
signal Sn : std_logic := '0';
signal Rn : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LatchSR_AB PORT MAP (
Sn => Sn,
Rn => Rn,
Q => Q,
Qn => Qn
);
-- Stimulus process
stim_proc: process
begin
-- S = '0' y R = '0'
wait for 100 ns;
-- S = '0' y R = '1'
Rn <= '1';
wait for 100 ns;
-- S = '1' y R = '0'
Rn <= '0';
Sn <= '1';
wait for 100 ns;
-- S = '1' y R = '1'
Rn <= '1';
wait;
end process;
END;
|
gpl-3.0
|
5b776aabbe8500f5a051a6843644f040
| 0.487129 | 3.176101 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_1_1/synth/DemoInterconnect_axi_spi_master_1_1.vhd
| 1 | 11,283 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_1 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_1;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_1_arch OF DemoInterconnect_axi_spi_master_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_axi_spi_master_1_1_arch: ARCHITECTURE IS "axi_spi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_axi_spi_master_1_1_arch : ARCHITECTURE IS "DemoInterconnect_axi_spi_master_1_1,axi_spi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_1_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_1_arch;
|
mit
|
e65d78d8083400550e4ab17f68ce6b13
| 0.714349 | 3.191796 | false | false | false | false |
inforichland/freezing-spice
|
src/encode_pkg.vhd
| 1 | 11,162 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.id_pkg.all;
use work.csr_pkg.all;
package encode_pkg is
subtype register_t is integer range 0 to 31;
-- functions to encode the different types of instructions, organized by format
function encode_r_type (insn_type : r_insn_t;
rs1, rs2, rd : register_t)
return word;
function encode_i_type (insn_type : i_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rd : register_t)
return word;
function encode_s_type (insn_type : s_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rs2 : register_t)
return word;
function encode_sb_type (insn_type : sb_insn_t;
imm : std_logic_vector(12 downto 1);
rs1, rs2 : register_t)
return word;
function encode_u_type (insn_type : u_insn_t;
imm_31_12 : std_logic_vector(31 downto 12);
rd : register_t)
return word;
function encode_uj_type (insn_type : uj_insn_t;
imm : std_logic_vector(20 downto 1);
rd : register_t)
return word;
function encode_i_shift (i_insn : i_insn_t;
shamt : std_logic_vector(4 downto 0);
rs1, rd : register_t)
return word;
function encode_i_csr (csr_addr : csr_addr_t;
rd : register_t)
return word;
end package encode_pkg;
package body encode_pkg is
-- purpose: encode a U-type instruction
function encode_u_type (insn_type : u_insn_t;
imm_31_12 : std_logic_vector(31 downto 12);
rd : register_t) return word is
variable result : word;
begin -- function encode_lui
result(31 downto 12) := imm_31_12;
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
case insn_type is
when U_LUI => result(6 downto 0) := c_op_lui;
when U_AUIPC => result(6 downto 0) := c_op_auipc;
end case;
return result;
end function encode_u_type;
-- purpose: encode an R-type instruction
function encode_r_type (insn_type : r_insn_t;
rs1, rs2, rd : register_t)
return word is
variable result : word;
begin -- function encode_r_type
result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5));
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
result(6 downto 0) := c_op_reg;
case insn_type is
when R_ADD =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "000";
when R_SUB =>
result(31 downto 25) := "0100000";
result(14 downto 12) := "000";
when R_SLL =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "001";
when R_SLT =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "010";
when R_SLTU =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "011";
when R_XOR =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "100";
when R_SRL =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "101";
when R_SRA =>
result(31 downto 25) := "0100000";
result(14 downto 12) := "101";
when R_OR =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "110";
when R_AND =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "111";
end case;
return result;
end function encode_r_type;
-- purpose: encode a UJ-type instruction
function encode_uj_type (
insn_type : uj_insn_t;
imm : std_logic_vector(20 downto 1);
rd : register_t)
return word is
variable result : word;
begin -- function encode_uj_type
result(31) := imm(20);
result(30 downto 21) := imm(10 downto 1);
result(20) := imm(11);
result(19 downto 12) := imm(19 downto 12);
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
case insn_type is
when UJ_JAL => result(6 downto 0) := c_op_jal;
end case;
return result;
end function encode_uj_type;
-- purpose: encode an I-type instruction (for shifts only)
function encode_i_shift (
i_insn : i_insn_t;
shamt : std_logic_vector(4 downto 0);
rs1, rd : register_t)
return word is
variable result : word;
begin -- function encode_i_shift
result(24 downto 20) := shamt;
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
result(6 downto 0) := c_op_imm;
case (i_insn) is
when I_SLLI =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "001";
when I_SRLI =>
result(31 downto 25) := "0000000";
result(14 downto 12) := "101";
when I_SRAI =>
result(31 downto 25) := "0100000";
result(14 downto 12) := "101";
when others =>
assert false report "Not an immediate shift instruction" severity error;
end case;
return result;
end function encode_i_shift;
-- encode a CSR access instruction
function encode_i_csr (
csr_addr : csr_addr_t;
rd : register_t)
return word is
variable result : word;
begin
case csr_addr is
when CSR_CYCLE => result(31 downto 20) := "110000000000";
when CSR_CYCLEH => result(31 downto 20) := "110010000000";
when CSR_TIME => result(31 downto 20) := "110000000001";
when CSR_TIMEH => result(31 downto 20) := "110010000001";
when CSR_INSTRET => result(31 downto 20) := "110000000010";
when CSR_INSTRETH => result(31 downto 20) := "110010000010";
when others => null;
end case;
result(19 downto 15) := "00000";
result(14 downto 12) := "010";
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
result(6 downto 0) := c_op_system;
return result;
end function encode_i_csr;
-- purpose: encode an I-type instruction
function encode_i_type (insn_type : i_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rd : register_t)
return word is
variable result : word;
begin
result(31 downto 20) := imm;
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5));
case insn_type is
when I_JALR =>
result(14 downto 12) := "000";
result(6 downto 0) := c_op_jalr;
when I_LB =>
result(14 downto 12) := "000";
result(6 downto 0) := c_op_load;
when I_LH =>
result(14 downto 12) := "001";
result(6 downto 0) := c_op_load;
when I_LW =>
result(14 downto 12) := "010";
result(6 downto 0) := c_op_load;
when I_LBU =>
result(14 downto 12) := "100";
result(6 downto 0) := c_op_load;
when I_LHU =>
result(14 downto 12) := "101";
result(6 downto 0) := c_op_load;
when I_ADDI =>
result(14 downto 12) := "000";
result(6 downto 0) := c_op_imm;
when I_SLTI =>
result(14 downto 12) := "010";
result(6 downto 0) := c_op_imm;
when I_SLTIU =>
result(14 downto 12) := "011";
result(6 downto 0) := c_op_imm;
when I_XORI =>
result(14 downto 12) := "100";
result(6 downto 0) := c_op_imm;
when I_ORI =>
result(14 downto 12) := "110";
result(6 downto 0) := c_op_imm;
when I_ANDI =>
result(14 downto 12) := "111";
result(6 downto 0) := c_op_imm;
when others =>
assert false report "Use encode_i_shift" severity error;
end case;
return result;
end function encode_i_type;
-- purpose: encode an S-type instruction
function encode_s_type (insn_type : s_insn_t;
imm : std_logic_vector(11 downto 0);
rs1, rs2 : register_t)
return word is
variable result : word;
begin -- function encode_s_type
result(31 downto 25) := imm(11 downto 5);
result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5));
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 7) := imm(4 downto 0);
result(6 downto 0) := c_op_store;
case insn_type is
when S_SB => result(14 downto 12) := "000";
when S_SH => result(14 downto 12) := "001";
when S_SW => result(14 downto 12) := "010";
end case;
return result;
end function encode_s_type;
-- encode an SB-type instruction
function encode_sb_type (insn_type : sb_insn_t;
imm : std_logic_vector(12 downto 1);
rs1, rs2 : register_t)
return word is
variable result : word;
begin
result(31) := imm(12);
result(30 downto 25) := imm(10 downto 5);
result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5));
result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5));
result(11 downto 8) := imm(4 downto 1);
result(7) := imm(11);
result(6 downto 0) := c_op_branch;
case insn_type is
when SB_BEQ => result(14 downto 12) := "000";
when SB_BNE => result(14 downto 12) := "001";
when SB_BLT => result(14 downto 12) := "100";
when SB_BGE => result(14 downto 12) := "101";
when SB_BLTU => result(14 downto 12) := "110";
when SB_BGEU => result(14 downto 12) := "111";
end case;
return result;
end function encode_sb_type;
end package body encode_pkg;
|
bsd-3-clause
|
c8dbb9b0eb05388236dd90fc00f216d3
| 0.490593 | 3.890554 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_i2c_master_1.0/hdl/axi_i2c_master_v1_0.vhd
| 1 | 3,723 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_i2c_master_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_i2c_master_v1_0;
architecture arch_imp of axi_i2c_master_v1_0 is
-- component declaration
component axi_i2c_master_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_i2c_master_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_i2c_master_v1_0_S00_AXI_inst : axi_i2c_master_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
140f003f7331e116c4ddfb30ea2b0a6a
| 0.67365 | 2.332707 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/SIPO.vhd
| 1 | 527 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIPO is
Port ( I : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (3 downto 0));
end SIPO;
architecture Behavioral of SIPO is
signal aux : std_logic_vector(3 downto 0) := "0000";
begin
O <= aux;
process (clk, CLR)
begin
if CLR = '1' then
aux <= "0000";
elsif (CLK'event and CLK='1') then
aux(3 downto 1) <= aux(2 downto 0);
aux(0) <= I;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
3197ff9d9373c337f476191b9ae4e1ab
| 0.582543 | 2.879781 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/reg8bits.vhd
| 1 | 830 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg8bits is
Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0);
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end reg8bits;
architecture Behavioral of reg8bits is
--signal reg : std_logic_vector (7 downto 0);
begin
process (clk_in, rst_in)
begin
if (rst_in = '1') then
data_out <= "00000000";
elsif (clk_in = '1' and clk_in'EVENT) then
if (load = '1') then
data_out <= data_in;
end if;
end if;
end process;
end Behavioral;
|
mit
|
6b59f94986f30bbc81f5ba6de4aa67d4
| 0.653382 | 2.835616 | false | false | false | false |
inforichland/freezing-spice
|
src/id_pkg.vhd
| 1 | 4,339 |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
use work.csr_pkg.all;
package id_pkg is
-- decoder input
type id_in is record
instruction : word;
end record id_in;
-- opcode type
subtype opcode_t is std_logic_vector(6 downto 0);
-- structure for decoded instruction
type decoded_t is record
alu_func : alu_func_t;
op2_src : std_logic;
insn_type : insn_type_t;
branch_type : branch_type_t;
load_type : load_type_t;
store_type : store_type_t;
rs1 : reg_addr_t;
rs2 : reg_addr_t;
rd : reg_addr_t;
imm : word;
opcode : opcode_t;
rs1_rd : std_logic;
rs2_rd : std_logic;
use_imm : std_logic;
rf_we : std_logic;
csr_addr : csr_addr_t;
system_type : system_type_t;
end record decoded_t;
-- value of decoding after reset
constant c_decoded_reset : decoded_t := (alu_func => ALU_NONE,
op2_src => '0',
insn_type => OP_ILLEGAL,
branch_type => BRANCH_NONE,
load_type => LOAD_NONE,
store_type => STORE_NONE,
rs1 => "00000",
rs2 => "00000",
rd => "00000",
imm => (others => '0'),
opcode => (others => '0'),
rs1_rd => '0',
rs2_rd => '0',
use_imm => '0',
rf_we => '0',
csr_addr => (others => '0'),
system_type => SYSTEM_ECALL);
-- Constants
constant c_op_load : opcode_t := "0000011";
constant c_op_misc_mem : opcode_t := "0001111";
constant c_op_imm : opcode_t := "0010011";
constant c_op_auipc : opcode_t := "0010111";
constant c_op_store : opcode_t := "0100011";
constant c_op_reg : opcode_t := "0110011";
constant c_op_lui : opcode_t := "0110111";
constant c_op_branch : opcode_t := "1100011";
constant c_op_jalr : opcode_t := "1100111";
constant c_op_jal : opcode_t := "1101111";
constant c_op_system : opcode_t := "1110011";
procedure print_insn (insn_type : in insn_type_t);
end package id_pkg;
package body id_pkg is
procedure print_insn (insn_type : in insn_type_t) is
variable l : line;
begin
write(l, string'("Instruction type: "));
if insn_type = OP_LUI then
write(l, string'("LUI"));
writeline(output, l);
elsif insn_type = OP_AUIPC then
write(l, string'("AUIPC"));
writeline(output, l);
elsif insn_type = OP_JAL then
write(l, string'("JAL"));
writeline(output, l);
elsif insn_type = OP_JALR then
write(l, string'("JALR"));
writeline(output, l);
elsif insn_type = OP_BRANCH then
write(l, string'("BRANCH"));
writeline(output, l);
elsif insn_type = OP_LOAD then
write(l, string'("LOAD"));
writeline(output, l);
elsif insn_type = OP_STORE then
write(l, string'("STORE"));
writeline(output, l);
elsif insn_type = OP_ALU then
write(l, string'("ALU"));
writeline(output, l);
elsif insn_type = OP_STALL then
write(l, string'("STALL"));
writeline(output, l);
elsif insn_type = OP_SYSTEM then
write(l, string'("SYSTEM"));
writeline(output, l);
else
write(l, string'("ILLEGAL"));
writeline(output, l);
end if;
end procedure print_insn;
end package body id_pkg;
|
bsd-3-clause
|
9ed0b28ca65e6419e6c587c7ea03b605
| 0.434432 | 4.245597 | false | false | false | false |
andbet050197/IS773UTP
|
sumadormedio/sumador_medio_tb.vhd
| 1 | 2,130 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:58:18 02/19/2017
-- Design Name:
-- Module Name: C:/ANDRES(temp)/Lab. Electronica Digital/sumedio/sumador_medio_tb.vhd
-- Project Name: sumedio
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sumador_medio
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sumador_medio_tb IS
END sumador_medio_tb;
ARCHITECTURE behavior OF sumador_medio_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sumador_medio
PORT(
a : IN std_logic;
b : IN std_logic;
cout : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal cout : std_logic;
signal s : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sumador_medio PORT MAP (
a => a,
b => b,
cout => cout,
s => s
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--00
wait for 100 ns;
--01
b <= '1';
wait for 100 ns;
--11
a <= '1';
wait for 100 ns;
--10
b <= '0';
wait;
end process;
END;
|
gpl-3.0
|
915684c82257b321ba652add2e197007
| 0.576995 | 3.844765 | false | true | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica4/comp_mux_sum.vhd
| 1 | 1,987 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:20:25 09/10/2011
-- Design Name:
-- Module Name: comp_mux_sum - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comp_mux_sum is
Port ( nx1 : in STD_LOGIC_VECTOR (2 downto 0);
nx2 : in STD_LOGIC_VECTOR (2 downto 0);
nux1 : out STD_LOGIC_VECTOR (2 downto 0);
nux2 : out STD_LOGIC_VECTOR (2 downto 0));
end comp_mux_sum;
architecture Behavioral of comp_mux_sum is
component sumador
Port ( num : in STD_LOGIC_VECTOR (2 downto 0);
suma : out STD_LOGIC_VECTOR (2 downto 0));
end component;
component comparador
Port ( num1 : in STD_LOGIC_VECTOR (2 downto 0);
num2 : in STD_LOGIC_VECTOR (2 downto 0);
answer : out STD_LOGIC);
end component;
component mux
Port ( sel : in STD_LOGIC;
n : in STD_LOGIC_VECTOR (2 downto 0);
nsum : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (2 downto 0));
end component;
signal s1,s2,s3,s4 : std_logic_vector(2 downto 0);
signal r: bit;
begin
u1: component comparador port map(num1 <= nx1, num2 <= nx2, answer <= r);
u2: sumador port map(num <= nx2, suma <= s1);
u3: mux port map (sel <= r, n <= nx2, nsum <= s1, salida <= s2)
nux1 <= nx1;
end Behavioral;
|
gpl-2.0
|
07629e9c6dfc5f3f298977e121d8141f
| 0.571213 | 3.437716 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/src/SPI_Master_v2.vhd
| 1 | 5,114 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spi_master is
generic(
DATA_WIDTH : integer := 8;
CLK_DIV : integer := 100 -- input clock divider to generate output serial clock; o_sclk frequency = i_clk/(2*CLK_DIV)
);
port(
--Out port
o_sclk : out std_logic := '1';
o_mosi : out std_logic := '1';
o_ss : out std_logic := '1';
o_tx_rx_busy : out std_logic := '0';
o_tx_rx_end : out std_logic := '0';
o_data_rx : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
--In port
i_miso : in std_logic := '0';
i_data_tx : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); -- data to send
--Control
i_clk : in std_logic := '0';
i_reset : in std_logic := '0';
i_tx_rx_start : in std_logic := '0' -- Start TX
);
end spi_master;
architecture behave_v2 of spi_master is
--control
signal spi_en : std_logic := '0';
signal spi_busy : std_logic := '0';
signal spi_done : std_logic := '0';
signal load_buffer : std_logic := '0';
signal buffer_ready : std_logic := '0';
--single buffer SPI
signal tx_rx_buffer : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'1');
signal load_buffer_val : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'1');
--counters
signal spi_bit_counter : integer range 0 to DATA_WIDTH := 0;
signal spi_clock_counter : integer range 0 to CLK_DIV := 0;
--I/O reg
signal mosi_reg : std_logic := '1';
signal ss_reg : std_logic := '1';
signal sclk_reg : std_logic := '1';
begin
-- I/O Connections assignments
o_sclk <= sclk_reg when spi_en='1' else '1';
o_mosi <= mosi_reg when spi_en='1' else '1';
o_ss <= ss_reg;
o_tx_rx_busy <= spi_busy;
o_tx_rx_end <= spi_done;
o_data_rx <= tx_rx_buffer;
p_gen_sclk: process(i_clk)
begin
if rising_edge(i_clk) then
if spi_clock_counter=CLK_DIV then
spi_clock_counter <= 0;
sclk_reg <= not(sclk_reg);
else
spi_clock_counter <= spi_clock_counter + 1;
end if;
end if;
end process;
p_spi: process(i_clk)
begin
if rising_edge(i_clk) then
if (i_tx_rx_start='1') then
spi_busy <= '1'; --busy starts before 'spi_en' to signal the user request
load_buffer <= '1';
load_buffer_val <= i_data_tx;
else
if (buffer_ready = '1') then --after buffer is initialized
load_buffer <= '0'; --de-assert load buffer
spi_en <= '1'; --enable spi Tx-Rx
end if;
if (spi_done='1') then
spi_en <= '0';
end if;
if (load_buffer='0' and spi_done='0' and spi_en='0') then
spi_busy <= '0';
end if;
end if;
end if;
end process;
p_count: process(sclk_reg)
begin
if rising_edge(sclk_reg) then
if (spi_en='1') then
if (spi_bit_counter=DATA_WIDTH-1) then
spi_bit_counter <= 0;
spi_done <= '1';
else
spi_bit_counter <= spi_bit_counter + 1;
end if;
end if;
if (spi_done = '1') then
spi_done <= '0';
end if;
end if;
end process;
p_ss: process(sclk_reg)
begin
if rising_edge(sclk_reg) then
if (spi_en='1') then
ss_reg <= '0'; --active LOW 'ss' is asserted on rising edge before data
else
ss_reg <= '1';
end if;
end if;
end process;
p_tx_rx: process(sclk_reg)
begin
if falling_edge(sclk_reg) then
if (load_buffer='1') then
tx_rx_buffer <= load_buffer_val; --load buffer in parallel with user data
buffer_ready <= '1';
elsif (spi_en='1') then
mosi_reg <= tx_rx_buffer(DATA_WIDTH-1); --shift out TX MSB
tx_rx_buffer <= tx_rx_buffer(DATA_WIDTH-2 downto 0) & i_miso; --shift in RX MSB
end if;
if (buffer_ready = '1') then
buffer_ready <= '0'; --pulse buffer ready
end if;
end if;
end process;
end behave_v2;
|
mit
|
0b1fadea4f65a96a0e60cf322b266665
| 0.443684 | 3.903817 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/preEscalador.vhd
| 1 | 2,240 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:49 10/31/2011
-- Design Name:
-- Module Name: preEscalador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity preEscalador is
Port (clk : in STD_LOGIC;
reset : in STD_LOGIC;
caidaBolitaOut : out STD_LOGIC;
multiplexorOut : out STD_LOGIC
);
end preEscalador;
architecture Behavioral of preEscalador is
signal contCaidaBolita : integer range 0 to 1100000;--***
signal contMultiplexor : integer range 0 to 33000;--***
signal caidaBolita : STD_LOGIC;
signal multiplexor : STD_LOGIC;
begin
process(reset,clk,contCaidaBolita,contMultiplexor,caidaBolita,multiplexor)
begin
if reset = '1' then
caidaBolita <= '0';
multiplexor <= '0';
contCaidaBolita <= 1100000;--***
contMultiplexor <= 33000;--***
elsif clk'event and clk = '1' then
if contCaidaBolita = 0 then
contCaidaBolita <= 1100000;--***
if caidaBolita = '1' then
caidaBolita <= '0';
else
caidaBolita <= '1';
end if;
else
contCaidaBolita <= contCaidaBolita - 1;
end if;
if contMultiplexor = 0 then
contMultiplexor <= 33000; --***
if multiplexor = '1' then
multiplexor <= '0';
else
multiplexor <= '1';
end if;
else
contMultiplexor <= contMultiplexor - 1;
end if;
end if;
end process;
process(clk,reset,multiplexor,caidaBolita)
begin
if reset = '1' then
caidaBolitaOut <= '0';
multiplexorOut <= '0';
elsif clk'event and clk = '1' then
multiplexorOut <= multiplexor;
caidaBolitaOut <= caidaBolita;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
496fa1d949e871fdae76d828f0ff9ac8
| 0.619643 | 3.601286 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/reg1bit.vhd
| 1 | 789 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg1bit is
Port ( data_in : in STD_LOGIC;
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC
);
end reg1bit;
architecture Behavioral of reg1bit is
signal reg : std_logic;
begin
process (clk_in, rst_in)
begin
if (rst_in = '1') then
reg <= '0';
elsif (clk_in = '1' and clk_in'EVENT) then
if (load = '1') then
reg <= data_in;
else
reg <= reg;
end if;
end if;
end process;
data_out <= reg;
end Behavioral;
|
mit
|
1a1ba541e371c5bd417d273d2e06ac88
| 0.636595 | 2.761404 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/PISO8bits.vhd
| 1 | 714 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PISO8bits is
Port ( Reset : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
SL : in STD_LOGIC;
O : out STD_LOGIC);
end PISO8bits;
architecture Behavioral of PISO8bits is
signal aux : std_logic := '0';
begin
O <= aux;
process (clk , SL, D, Reset) is
variable temp : std_logic_vector (7 downto 0);
begin
if (Reset = '1') then
temp := "00000000";
aux <= '0';
elsif (SL='1') then
temp := D;
elsif (rising_edge (clk)) then
aux <= temp(0);
temp := '0' & temp(7 downto 1);
end if;
end process;
end Behavioral;
|
gpl-3.0
|
7abbcbb073be6fa8cea370e1b40fdedc
| 0.537815 | 3.230769 | false | false | false | false |
andbet050197/IS773UTP
|
modulo4/memoria_tb.vhd
| 1 | 2,008 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY memoria_tb IS
END memoria_tb;
ARCHITECTURE behavior OF memoria_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Memoria
PORT(
clk : IN std_logic;
lectura_escritura : IN std_logic;
habilitador : IN std_logic;
direccion : IN std_logic_vector(3 downto 0);
dato_entrada : IN std_logic_vector(2 downto 0);
dato_salida : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal lectura_escritura : std_logic := '0';
signal habilitador : std_logic := '0';
signal direccion : std_logic_vector(3 downto 0) := (others => '0');
signal dato_entrada : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal dato_salida : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Memoria PORT MAP (
clk => clk,
lectura_escritura => lectura_escritura,
habilitador => habilitador,
direccion => direccion,
dato_entrada => dato_entrada,
dato_salida => dato_salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
habilitador <= '1';
lectura_escritura <= '1'; -- Escritura
wait for 10 ns;
direccion <= "0000"; -- Guardando dato
dato_entrada <= "101";
wait for 30 ns;
direccion <= "0100"; -- Guardando dato
dato_entrada <= "001";
wait for 30 ns;
lectura_escritura <= '0'; -- Lectura
direccion <= "0000"; -- Leyendo dato
wait for 30 ns;
direccion <= "0100"; -- Leyendo dato
wait for 30 ns;
direccion <= "1111"; -- Leyendo de una posicion no asignada
wait;
end process;
END;
|
gpl-3.0
|
441793c82886988edfdaf7711f7141e7
| 0.599602 | 3.618018 | false | false | false | false |
dl3yc/sdr-fm
|
dev/euler/euler.vhd
| 1 | 2,129 |
-- EULER module for Betty SDR
-- implements a rectangle to polar conversion
-- file: euler.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
-- depends on: vcordic.vhd
--
-- change log:
-- - release implementation 1.0
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity euler is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of euler is
signal cordic_i : signed(A-1 downto 0);
signal cordic_q : signed(A-1 downto 0);
signal cordic_phi : signed(P-1 downto 0);
alias i_sign : std_logic is i(i'high);
alias q_sign : std_logic is q(q'high);
type quadrant_t is array(N+1 downto 0) of bit_vector(1 downto 0);
signal quadrant : quadrant_t;
alias actual_quadrant : bit_vector(1 downto 0) is quadrant(0);
alias last_quadrant : bit_vector(1 downto 0) is quadrant(N+1);
begin
cordic : entity work.vcordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => cordic_i,
q => cordic_q,
amp => amp,
phi => cordic_phi
);
process
begin
wait until rising_edge(clk);
quadrant(N+1 downto 1) <= quadrant(N downto 0);
end process;
quadrant(0) <= to_bit(i_sign) & to_bit(q_sign);
process
begin
wait until rising_edge(clk);
case actual_quadrant is
when "11" => -- 1st quadrant
cordic_i <= i;
cordic_q <= q;
when "10" => -- 2nd quadrant
cordic_i <= i;
cordic_q <= -q;
when "00" => -- 3rd quadrant
cordic_i <= -i;
cordic_q <= -q;
when "01" => -- 4th quadrant
cordic_i <= -i;
cordic_q <= q;
end case;
end process;
process
begin
wait until rising_edge(clk);
case last_quadrant is
when "11" => phi <= cordic_phi; -- 1st quadrant
when "10" => phi <= 2**(P-1) - cordic_phi; -- 2nd quadrant
when "00" => phi <= 2**(P-1) + cordic_phi; -- 3rd quadrant
when "01" => phi <= -cordic_phi; -- 4th quadrant
end case;
end process;
end behavioral;
|
gpl-2.0
|
7d34bf4c812cdcbc9f7d894e7a6dda8d
| 0.613903 | 2.66125 | false | false | false | false |
nkkav/ledramp-s3esk
|
ledramp_tb.vhd
| 1 | 1,433 |
library IEEE, STD;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_1164.all;
entity ledramp_tb is
end ledramp_tb;
architecture tb_arch of ledramp_tb is
-- UUT component
component ledramp
generic (
PWM_RANGE_MAX : integer := 5000000
);
port (
clk : in std_logic;
ramp : out std_logic_vector(7 downto 0)
);
end component;
-- I/O signals
signal clk : std_logic := '0';
signal ramp : std_logic_vector(7 downto 0);
-- Constant declarations
constant CLK_PERIOD : time := 20 ns;
-- Declare results file
file ResultsFile: text open write_mode is "ledramp_results.txt";
begin
uut : ledramp
generic map (
PWM_RANGE_MAX => 1000
)
port map (
clk => clk,
ramp => ramp
);
CLK_GEN_PROC: process(clk)
begin
if (clk = '0') then
clk <= '1';
else
clk <= not clk after CLK_PERIOD/2;
end if;
end process CLK_GEN_PROC;
process (clk)
variable line_el: line;
variable ramp_ext : std_logic_vector(7 downto 0);
begin
if rising_edge(clk) then
-- Write the time
write(line_el, now); -- write the line
write(line_el, ':'); -- write the line
-- Write the ramp signal
write(line_el, ' ');
write(line_el, ramp); -- write the line
writeline(ResultsFile, line_el); -- write the contents into the file
end if;
end process;
end tb_arch;
|
bsd-3-clause
|
8cfd318f5e89af0fb4eda03b277d41d0
| 0.601535 | 3.4038 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica3/practica3.vhd
| 1 | 1,832 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:29 09/02/2011
-- Design Name:
-- Module Name: practica3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practica3 is
Port ( LED1 : in STD_LOGIC;
LED2 : in STD_LOGIC;
LED3 : in STD_LOGIC;
LED4 : in STD_LOGIC;
LED5 : in STD_LOGIC;
LED6 : in STD_LOGIC;
LED7 : in STD_LOGIC;
SEGA : out STD_LOGIC;
SEGB : out STD_LOGIC;
SEGC : out STD_LOGIC;
SEGD : out STD_LOGIC;
SEGE : out STD_LOGIC;
SEGF : out STD_LOGIC;
SEGG : out STD_LOGIC);
end practica3;
architecture Behavioral of practica3 is
begin
SEGA <= (LED1 AND LED2 AND LED3 AND NOT LED4) OR (NOT LED1 AND NOT LED3 AND LED4);
SEGB <= (LED2 AND NOT LED3 AND NOT LED4) OR (NOT LED1 AND NOT LED2 AND NOT LED3 AND LED4);
SEGC <= LED1 AND LED2 AND NOT LED3 AND LED4;
SEGD <= (LED1 AND LED2 AND LED3 AND NOT LED4) OR (NOT LED1 AND LED2 AND NOT LED3 AND LED4);
SEGE <= (LED1 AND LED2 AND LED3 AND NOT LED4) OR (NOT LED1 AND LED2 AND NOT LED3);
SEGF <= LED1;
SEGG <= LED3;
end Behavioral;
|
gpl-2.0
|
9d7b0a1ea592896c1385ebe1739e7523
| 0.562227 | 3.671343 | false | false | false | false |
andbet050197/IS773UTP
|
sumador4bits/Sumador4bits.vhd
| 1 | 1,112 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Sumador4bits is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Sumador4bits;
architecture Behavioral of Sumador4bits is
COMPONENT SumadorCompleto
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
cout : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
signal co1: std_logic := '0';
signal co2: std_logic := '0';
signal co3: std_logic := '0';
begin
Inst_SumadorCompleto0: SumadorCompleto PORT MAP(
a => A(0),
b => B(0),
cin => Cin,
cout => co1,
s => cout
);
Inst_SumadorCompleto1: SumadorCompleto PORT MAP(
a => A(1),
b => B(1),
cin => co1,
cout => co2,
s => S(0)
);
Inst_SumadorCompleto2: SumadorCompleto PORT MAP(
a => A(2),
b => B(2),
cin => co2,
cout => co3,
s => S(1)
);
Inst_SumadorCompleto3: SumadorCompleto PORT MAP(
a => A(3),
b => B(3),
cin => co3,
cout => S(3),
s => S(2)
);
end Behavioral;
|
gpl-3.0
|
cf2ff2b83d67c1ceb5aab08b741657e1
| 0.580036 | 2.628842 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/fifo_buffer.vhd
| 1 | 2,261 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fifo_buffer is
generic(
BUFFER_DEPTH : positive;
BUFFER_WIDTH : positive
);
port(
reset : in std_logic;
clock : in std_logic;
head: out std_logic_vector(BUFFER_WIDTH-1 downto 0);
tail : in std_logic_vector(BUFFER_WIDTH-1 downto 0);
push : in std_logic;
pull : in std_logic;
counter : out natural
);
end;
architecture circular_fifo_buffer of fifo_buffer is
type buff is array(0 to BUFFER_DEPTH - 1) of std_logic_vector(BUFFER_WIDTH-1 downto 0);
subtype pointer is natural range 0 to BUFFER_DEPTH - 1;
procedure increment_pointer(p: inout pointer) is
begin
if p = BUFFER_DEPTH - 1 then
p := 0;
else
p := p + 1;
end if;
end increment_pointer;
signal buf: buff := (others=>(others=>'0'));
signal is_full : boolean;
signal first: pointer;
signal last: pointer;
begin
head <= buf(first);
counter <= BUFFER_DEPTH when is_full else
last - first when (last >= first) else
BUFFER_DEPTH - (first - last);
process(reset, clock)
variable aux_first, aux_last: pointer;
variable aux_is_full, is_empty : boolean;
begin
if reset = '1' then
last <= 0;
first <= 0;
is_full <= false;
is_empty := true;
elsif rising_edge(clock) then
aux_is_full := is_full;
aux_last := last;
aux_first := first;
-- remove data
if not is_empty and pull = '1' then
increment_pointer(aux_first);
aux_is_full := false;
is_empty := (aux_first = aux_last);
end if;
-- append data
if not aux_is_full and push = '1' then
buf(aux_last) <= tail;
increment_pointer(aux_last);
is_empty := false;
aux_is_full := (aux_last = aux_first);
end if;
is_full <= aux_is_full;
last <= aux_last;
first <= aux_first;
end if;
end process;
end circular_fifo_buffer;
|
lgpl-3.0
|
2da39480c49175ef1bc5caba04644cbc
| 0.513047 | 3.966667 | false | false | false | false |
dl3yc/sdr-fm
|
testing/vcordic-1.0/sim/vcordic_tb.vhd
| 1 | 3,591 |
-- title: Testbench for VCORDIC
-- author: Sebastian Weiss
-- last change: 03.12.14
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic_tb is
end entity;
architecture behavioral of vcordic_tb is
constant A : natural := 16;
constant P : natural := 24;
constant N : natural := 15;
signal clk : std_logic := '0';
signal i : signed(A-1 downto 0) := (others => '0');
signal q : signed(A-1 downto 0) := (others => '0');
signal amp : unsigned(A-1 downto 0);
signal phi : signed(P-1 downto 0) := (others => '0');
begin
dut : entity work.vcordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => i,
q => q,
amp => amp,
phi => phi
);
process
begin
wait until rising_edge(clk);
i <= to_signed(integer(1.0 * 2.0**(A-1)-1.0),A);
q <= to_signed(integer(1.0 * 2.0**(A-1)-1.0),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
q <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.5 * 2.0**(A-1)),A);
q <= to_signed(integer(0.2 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(-0.1 * 2.0**(A-1)),A);
q <= to_signed(integer(0.9 * 2.0**(A-1)),A);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
i <= to_signed(integer(0.0 * (2.0**(A-1)-1.0)),A);
q <= to_signed(integer(0.0 * (2.0**(A-1)-1.0)),A);
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.4142 * 2.0**(A-1)),A)) and (amp >= to_unsigned(integer(0.99 * 1.4142 * 2.0**(A-1)),A))
report "case 1 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P))
report "case 2 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.0 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 1.0 * 2.0**(A-1)),A))
report "case 3 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P))
report "case 4 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.5385 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.5385 * 2.0**(A-1)),A))
report "case 5 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P))
report "case 6 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.9055 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.9055 * 2.0**(A-1)),A))
report "case 7 failed!" severity error;
assert (phi < to_signed(integer(1.01 * 1.6815/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * 1.6815/(MATH_PI) * 2.0**(P-1)),P))
report "case 8 failed!" severity error;
report "all tests finished!";
wait;
end process;
clk <= not clk after 11363 ps;
end behavioral;
|
gpl-2.0
|
02838a44cf39a0d9d7ffebdd16dad9e5
| 0.600111 | 2.52 | false | false | false | false |
rmilfont/Phoenix
|
NoC/FPPM_AA00.vhd
| 1 | 2,876 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.PhoenixPackage.regNport;
use work.HammingPack16.all;
entity FPPM is
port
(
clock : in std_logic;
reset_in : in std_logic; -- reset geral da NoC
rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao)
statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH)
write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas
row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas
);
end FPPM;
architecture FPPM of FPPM is
-- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits!
constant N: integer range 1 to 31 := 8;
constant M: integer range 1 to 31 := 4;
constant P: integer range 1 to 31 := 30;
constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela
begin
FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate
begin
process(clock, reset_in)
variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE;
variable reset: std_logic := '0';
variable counter_N, counter_M, counter_P: std_logic_vector((COUNTERS_SIZE-1) downto 0);
variable link_status: std_logic_vector(1 downto 0) := "00";
begin
if (reset_in='1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
if (clock'event and clock='1' and rx(i)='1') then
--counter_write := counter_write + 1;
case statusHamming(i) is
when NE =>
counter_N := counter_N + 1;
if (counter_N = N) then
link_status := "00";
reset := '1';
end if;
when EC =>
counter_M := counter_M + 1;
if (counter_M = M) then
link_status := "01";
reset := '1';
end if;
when ED =>
counter_P := counter_P + 1;
if (counter_P = P) then
link_status := "10";
reset := '1';
end if;
when others => null;
end case;
if (reset = '1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
end if;
if (counter_write = COUNTER_UPDATE_TABLE) then
--if (false) then
write_FaultTable(i) <= '1';
row_FaultTablePorts_out(i) <= link_status & counter_N & counter_M & counter_P;
counter_write := 0;
else
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
elsif (rx(i)='0') then
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
end process;
end generate;
end FPPM;
|
lgpl-3.0
|
e01aaedaeadba6d82f1e287c42c355d5
| 0.598748 | 3.146608 | false | false | false | false |
dl3yc/sdr-fm
|
testing/fir-1.0/src/fir.vhd
| 2 | 3,922 |
-- FIR module for Betty SDR
-- implements a FIR filter for universal filter order without symmetry presumption
-- file: fir.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with dirac impulse
-- - test for linear phase with complex carrier
--
-- needs generics with definition of fir_order and fir_coeff
-- with fir_order+1 elements in Q0.26 signed fixed point format
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package fir_types is
type fir_coeff_t is array(natural range <>) of signed(26 downto 0);
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
entity fir is
generic (
fir_order : natural;
fir_coeff : fir_coeff_t
);
port (
clk : in std_logic;
stb : in std_logic;
d : in signed(26 downto 0);
q : out signed(26 downto 0);
rdy : out std_logic
);
end entity fir;
architecture rtl of fir is
-- shift register
type shift_t is array(fir_order downto 0) of signed(26 downto 0);
type sr_t is record
input : signed(26 downto 0);
shift : shift_t;
sel : std_logic;
en : std_logic;
end record;
constant sr_default : sr_t := (
input => (others => '0'),
shift => (others => (others => '0')),
sel => '0',
en => '0'
);
signal sr : sr_t := sr_default;
-- coeff ROM
signal rom : fir_coeff_t(fir_order downto 0) := fir_coeff;
signal coeff : signed(26 downto 0);
signal coeff_index : natural range 0 to fir_order;
-- MAC unit
type mac_t is record
in_a : signed(26 downto 0);
in_b : signed(26 downto 0);
mult_out : signed(53 downto 0);
acc_out : signed(53 downto 0);
mac_out : signed(26 downto 0);
clr : std_logic;
stb : std_logic;
end record;
signal mac : mac_t;
-- finite state machine
type state_t is (reset, prolog, multiply_and_add, epilog);
signal state : state_t;
signal fsm_index : natural range 0 to fir_order;
begin
rom_register : process
begin
wait until rising_edge(clk);
coeff <= rom(coeff_index);
end process rom_register;
shift_register : process
begin
wait until rising_edge(clk);
if sr.en = '1' then
sr.shift(sr.shift'high downto sr.shift'low+1) <= sr.shift(sr.shift'high-1 downto sr.shift'low);
if sr.sel = '1' then
sr.shift(sr.shift'low) <= sr.input;
else
sr.shift(sr.shift'low) <= sr.shift(sr.shift'high);
end if;
end if;
end process shift_register;
sr.input <= d;
mac_unit : process
begin
wait until rising_edge(clk);
mac.in_a <= coeff;
mac.in_b <= sr.shift(sr.shift'high);
mac.mult_out <= mac.in_a * mac.in_b;
if mac.clr = '1' then
mac.acc_out <= (others => '0');
else
mac.acc_out <= mac.acc_out + mac.mult_out;
end if;
if mac.stb = '1' then
mac.mac_out <= mac.acc_out(52 downto 26);
end if;
end process mac_unit;
fsm : process
begin
wait until rising_edge(clk);
case state is
when reset =>
rdy <= '0';
mac.stb <= '0';
sr.en <= '0';
fsm_index <= 0;
if stb = '1' then
sr.en <= '1';
sr.sel <= '1';
state <= prolog;
end if;
when prolog =>
sr.sel <= '0';
fsm_index <= fsm_index + 1;
coeff_index <= fsm_index;
if fsm_index = 0 then
sr.en <= '0';
else
sr.en <= '1';
end if;
if fsm_index = 2 then
mac.clr <= '1';
end if;
if fsm_index = 3 then
mac.clr <= '0';
state <= multiply_and_add;
end if;
when multiply_and_add =>
coeff_index <= fsm_index;
if fsm_index = fir_order then
state <= epilog;
fsm_index <= 0;
else
fsm_index <= fsm_index + 1;
end if;
when epilog =>
fsm_index <= fsm_index + 1;
if fsm_index = 1 then
sr.en <= '0';
end if;
if fsm_index = 3 then
mac.stb <= '1';
state <= reset;
rdy <= '1';
end if;
end case;
end process fsm;
q <= mac.mac_out;
end architecture rtl;
|
gpl-2.0
|
5e88e4e1b1b594c4585bc0f6d83ae0ec
| 0.611933 | 2.779589 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Phoenix_crossbar.vhd
| 1 | 8,882 |
----------------------------------------------------------------
-- CROSSBAR
-- --------------
-- DATA_AV ->| |
-- DATA_IN ->| |
-- DATA_ACK <-| |-> TX
-- SENDER ->| |-> DATA_OUT
-- FREE ->| |<- CREDIT_I
-- TAB_IN ->| |
-- TAB_OUT ->| |
-- --------------
----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
entity Phoenix_crossbar is
port(
data_av: in regNport;
data_in: in arrayNport_regflit;
data_ack: out regNport;
sender: in regNport;
free: in regNport;
tab_in: in arrayNport_reg3;
tab_out: in arrayNport_reg3;
tx: out regNport;
data_out: out arrayNport_regflit;
credit_i: in regNport;
retransmission_i: in regNport;
retransmission_in_buf: out regNport);
end Phoenix_crossbar;
architecture Phoenix_crossbar of Phoenix_crossbar is
begin
----------------------------------------------------------------------------------
-- PORTA LOCAL
----------------------------------------------------------------------------------
tx(LOCAL) <= data_av(EAST) when tab_out(LOCAL)="000" and free(LOCAL)='0' else
data_av(WEST) when tab_out(LOCAL)="001" and free(LOCAL)='0' else
data_av(NORTH) when tab_out(LOCAL)="010" and free(LOCAL)='0' else
data_av(SOUTH) when tab_out(LOCAL)="011" and free(LOCAL)='0' else
data_av(LOCAL) when tab_out(LOCAL)="100" and free(LOCAL)='0' else
'0';
data_out(LOCAL) <= data_in(EAST) when tab_out(LOCAL)="000" and free(LOCAL)='0' else
data_in(WEST) when tab_out(LOCAL)="001" and free(LOCAL)='0' else
data_in(NORTH) when tab_out(LOCAL)="010" and free(LOCAL)='0' else
data_in(SOUTH) when tab_out(LOCAL)="011" and free(LOCAL)='0' else
data_in(LOCAL) when tab_out(LOCAL)="100" and free(LOCAL)='0' else
(others=>'0');
data_ack(LOCAL) <= credit_i(EAST) when tab_in(LOCAL)="000" and data_av(LOCAL)='1' else
credit_i(WEST) when tab_in(LOCAL)="001" and data_av(LOCAL)='1' else
credit_i(NORTH) when tab_in(LOCAL)="010" and data_av(LOCAL)='1' else
credit_i(SOUTH) when tab_in(LOCAL)="011" and data_av(LOCAL)='1' else
credit_i(LOCAL) when tab_in(LOCAL)="100" and data_av(LOCAL)='1' else
'0';
retransmission_in_buf(LOCAL) <= retransmission_i(EAST) when tab_in(LOCAL)="000" and data_av(LOCAL)='1' else
retransmission_i(WEST) when tab_in(LOCAL)="001" and data_av(LOCAL)='1' else
retransmission_i(NORTH) when tab_in(LOCAL)="010" and data_av(LOCAL)='1' else
retransmission_i(SOUTH) when tab_in(LOCAL)="011" and data_av(LOCAL)='1' else
retransmission_i(LOCAL) when tab_in(LOCAL)="100" and data_av(LOCAL)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA EAST
----------------------------------------------------------------------------------
tx(EAST) <= data_av(WEST) when tab_out(EAST)="001" and free(EAST)='0' else
data_av(NORTH) when tab_out(EAST)="010" and free(EAST)='0' else
data_av(SOUTH) when tab_out(EAST)="011" and free(EAST)='0' else
data_av(LOCAL) when tab_out(EAST)="100" and free(EAST)='0' else
'0';
data_out(EAST) <= data_in(WEST) when tab_out(EAST)="001" and free(EAST)='0' else
data_in(NORTH) when tab_out(EAST)="010" and free(EAST)='0' else
data_in(SOUTH) when tab_out(EAST)="011" and free(EAST)='0' else
data_in(LOCAL) when tab_out(EAST)="100" and free(EAST)='0' else
(others=>'0');
data_ack(EAST) <= credit_i(WEST) when tab_in(EAST)="001" and data_av(EAST)='1' else
credit_i(NORTH) when tab_in(EAST)="010" and data_av(EAST)='1' else
credit_i(SOUTH) when tab_in(EAST)="011" and data_av(EAST)='1' else
credit_i(LOCAL) when tab_in(EAST)="100" and data_av(EAST)='1' else
'0';
retransmission_in_buf(EAST) <= retransmission_i(WEST) when tab_in(EAST)="001" and data_av(EAST)='1' else
retransmission_i(NORTH) when tab_in(EAST)="010" and data_av(EAST)='1' else
retransmission_i(SOUTH) when tab_in(EAST)="011" and data_av(EAST)='1' else
retransmission_i(LOCAL) when tab_in(EAST)="100" and data_av(EAST)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA WEST
----------------------------------------------------------------------------------
tx(WEST) <= data_av(EAST) when tab_out(WEST)="000" and free(WEST)='0' else
data_av(NORTH) when tab_out(WEST)="010" and free(WEST)='0' else
data_av(SOUTH) when tab_out(WEST)="011" and free(WEST)='0' else
data_av(LOCAL) when tab_out(WEST)="100" and free(WEST)='0' else
'0';
data_out(WEST) <= data_in(EAST) when tab_out(WEST)="000" and free(WEST)='0' else
data_in(NORTH) when tab_out(WEST)="010" and free(WEST)='0' else
data_in(SOUTH) when tab_out(WEST)="011" and free(WEST)='0' else
data_in(LOCAL) when tab_out(WEST)="100" and free(WEST)='0' else
(others=>'0');
data_ack(WEST) <= credit_i(EAST) when tab_in(WEST)="000" and data_av(WEST)='1' else
credit_i(NORTH) when tab_in(WEST)="010" and data_av(WEST)='1' else
credit_i(SOUTH) when tab_in(WEST)="011" and data_av(WEST)='1' else
credit_i(LOCAL) when tab_in(WEST)="100" and data_av(WEST)='1' else
'0';
retransmission_in_buf(WEST) <= retransmission_i(EAST) when tab_in(WEST)="000" and data_av(WEST)='1' else
retransmission_i(NORTH) when tab_in(WEST)="010" and data_av(WEST)='1' else
retransmission_i(SOUTH) when tab_in(WEST)="011" and data_av(WEST)='1' else
retransmission_i(LOCAL) when tab_in(WEST)="100" and data_av(WEST)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA NORTH
----------------------------------------------------------------------------------
tx(NORTH) <= data_av(EAST) when tab_out(NORTH)="000" and free(NORTH)='0' else
data_av(WEST) when tab_out(NORTH)="001" and free(NORTH)='0' else
data_av(SOUTH) when tab_out(NORTH)="011" and free(NORTH)='0' else
data_av(LOCAL) when tab_out(NORTH)="100" and free(NORTH)='0' else
'0';
data_out(NORTH) <= data_in(EAST) when tab_out(NORTH)="000" and free(NORTH)='0' else
data_in(WEST) when tab_out(NORTH)="001" and free(NORTH)='0' else
data_in(SOUTH) when tab_out(NORTH)="011" and free(NORTH)='0' else
data_in(LOCAL) when tab_out(NORTH)="100" and free(NORTH)='0' else
(others=>'0');
data_ack(NORTH) <= credit_i(EAST) when tab_in(NORTH)="000" and data_av(NORTH)='1' else
credit_i(WEST) when tab_in(NORTH)="001" and data_av(NORTH)='1' else
credit_i(SOUTH) when tab_in(NORTH)="011" and data_av(NORTH)='1' else
credit_i(LOCAL) when tab_in(NORTH)="100" and data_av(NORTH)='1' else
'0';
retransmission_in_buf(NORTH) <= retransmission_i(EAST) when tab_in(NORTH)="000" and data_av(NORTH)='1' else
retransmission_i(WEST) when tab_in(NORTH)="001" and data_av(NORTH)='1' else
retransmission_i(SOUTH) when tab_in(NORTH)="011" and data_av(NORTH)='1' else
retransmission_i(LOCAL) when tab_in(NORTH)="100" and data_av(NORTH)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA SOUTH
----------------------------------------------------------------------------------
tx(SOUTH) <= data_av(EAST) when tab_out(SOUTH)="000" and free(SOUTH)='0' else
data_av(WEST) when tab_out(SOUTH)="001" and free(SOUTH)='0' else
data_av(NORTH) when tab_out(SOUTH)="010" and free(SOUTH)='0' else
data_av(LOCAL) when tab_out(SOUTH)="100" and free(SOUTH)='0' else
'0';
data_out(SOUTH) <= data_in(EAST) when tab_out(SOUTH)="000" and free(SOUTH)='0' else
data_in(WEST) when tab_out(SOUTH)="001" and free(SOUTH)='0' else
data_in(NORTH) when tab_out(SOUTH)="010" and free(SOUTH)='0' else
data_in(LOCAL) when tab_out(SOUTH)="100" and free(SOUTH)='0' else
(others=>'0');
data_ack(SOUTH) <= credit_i(EAST) when tab_in(SOUTH)="000" and data_av(SOUTH)='1' else
credit_i(WEST) when tab_in(SOUTH)="001" and data_av(SOUTH)='1' else
credit_i(NORTH) when tab_in(SOUTH)="010" and data_av(SOUTH)='1' else
credit_i(LOCAL) when tab_in(SOUTH)="100" and data_av(SOUTH)='1' else
'0';
retransmission_in_buf(SOUTH) <= retransmission_i(EAST) when tab_in(SOUTH)="000" and data_av(SOUTH)='1' else
retransmission_i(WEST) when tab_in(SOUTH)="001" and data_av(SOUTH)='1' else
retransmission_i(NORTH) when tab_in(SOUTH)="010" and data_av(SOUTH)='1' else
retransmission_i(LOCAL) when tab_in(SOUTH)="100" and data_av(SOUTH)='1' else
'0';
end Phoenix_crossbar;
|
lgpl-3.0
|
b669f5d1781129dc793fc06e5cbf17fa
| 0.550552 | 3.182372 | false | false | false | false |
mosass/HexapodRobot
|
VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/synth/design_1_axi_gpio_1_0.vhd
| 1 | 10,017 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY design_1_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_1_axi_gpio_1_0;
ARCHITECTURE design_1_axi_gpio_1_0_arch OF design_1_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_gpio_1_0_arch : ARCHITECTURE IS "design_1_axi_gpio_1_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "design_1_axi_gpio_1_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_1_0_arch;
|
mit
|
f502350c85b58c77d7919ea50a4b0f9c
| 0.686733 | 3.152975 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/hdl/axi_spi_master_v1_0_S00_AXI.vhd
| 3 | 15,332 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_spi_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
SPI_DATA_WIDTH : integer := 8;
SPI_CLK_DIV : integer := 100;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 1
);
port (
-- Users to add ports here
spi_mosi : out std_logic;
spi_miso : in std_logic;
spi_ss : out std_logic;
spi_sclk : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_spi_master_v1_0_S00_AXI;
architecture arch_imp of axi_spi_master_v1_0_S00_AXI is
-- Components
component word2byte is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(7 downto 0);
ss_o : out std_logic
) ;
end component;
component byte2word is
generic (
DATA_WIDTH : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end component;
component spi_master is
generic(
DATA_WIDTH : integer;
CLK_DIV : integer -- input clock divider to generate output serial clock; o_sclk frequency = i_clk/(2*CLK_DIV)
);
port(
--Out port
o_sclk : out std_logic := '1';
o_mosi : out std_logic := '1';
o_ss : out std_logic := '1';
o_tx_rx_busy : out std_logic := '0';
o_tx_rx_end : out std_logic := '0';
o_data_rx : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
--In port
i_miso : in std_logic := '0';
i_data_tx : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); -- data to send
--Control
i_clk : in std_logic := '0';
i_reset : in std_logic := '0';
i_tx_rx_start : in std_logic := '0' -- Start TX
);
end component;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Packet logic
signal packet_byte_cnt : std_logic_vector(2 downto 0) := "100";
-- SPI interface signals
signal spi_tx_rx_start : std_logic := '0';
signal spi_tx_rx_busy : std_logic := '0';
signal spi_tx_rx_done : std_logic := '0';
signal spi_tx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
signal spi_rx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
-- PISO SIPO converters interface signals
signal p2s_load : std_logic := '0';
signal p2s_send : std_logic := '0';
signal p2s_busy : std_logic := '0';
signal p2s_ss : std_logic := '0';
signal p2s_done : std_logic := '0';
signal s2p_en : std_logic := '0';
signal s2p_done : std_logic := '0';
-- Registers
signal slv_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_wdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
wr_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
wr_addr_latch: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
wr_data_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and p2s_busy='0' and spi_tx_rx_busy='0') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
slv_wdata <= S_AXI_WDATA;
case S_AXI_WSTRB is
when "0001"=>
packet_byte_cnt <= "001";
when "0011"=>
packet_byte_cnt <= "010";
when "0111"=>
packet_byte_cnt <= "011";
when "1111"=>
packet_byte_cnt <= "100";
when others=>
packet_byte_cnt <= "100";
end case;
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
wr_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
rd_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and s2p_done='1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
rd_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
axi_rdata <= slv_rdata;
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Add user logic here
start_interface: process(S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
p2s_load <= '0';
else
if (p2s_load='0' and p2s_busy='0') and ((axi_bvalid='1') or (S_AXI_ARVALID='1')) then
p2s_load <= '1';
else
p2s_load <= '0';
end if;
end if;
end if;
end process;
p2s_send <= not(spi_tx_rx_busy) and not(spi_tx_rx_start);
s2p_en <= spi_tx_rx_done;
spi_tx_rx_start <= not(p2s_ss);
word2byte_inst: word2byte
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => p2s_load,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
send_i => p2s_send,
busy_o => p2s_busy,
data_i => slv_wdata,
shift_o => spi_tx_byte,
ss_o => p2s_ss
);
byte2word_inst: byte2word
generic map(
DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
clk_i => S_AXI_ACLK,
en_i => s2p_en,
rstn_i => S_AXI_ARESETN,
shift_cnt_i => packet_byte_cnt,
shift_i => spi_rx_byte,
done_o => s2p_done,
data_o => slv_rdata
);
spi_master_inst: spi_master
generic map(
DATA_WIDTH => SPI_DATA_WIDTH,
CLK_DIV => SPI_CLK_DIV
)
port map(
--Out port
o_sclk => spi_sclk,
o_mosi => spi_mosi,
o_ss => spi_ss,
o_tx_rx_busy => spi_tx_rx_busy,
o_tx_rx_end => spi_tx_rx_done,
o_data_rx => spi_rx_byte,
--In port
i_miso => spi_miso,
i_data_tx => spi_tx_byte,
--Control
i_clk => S_AXI_ACLK,
i_reset => S_AXI_ARESETN,
i_tx_rx_start => spi_tx_rx_start
);
-- User logic ends
end arch_imp;
|
mit
|
68b24771277e93bc49ff1958b3dae1a3
| 0.601487 | 3.28449 | false | false | false | false |
dl3yc/sdr-fm
|
dev/pfd/pfd_matlab.vhd
| 1 | 1,267 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity pfd_matlab is
end entity pfd_matlab;
architecture sim of pfd_matlab is
signal clk : std_logic := '0';
signal stb : std_logic;
signal rdy : std_logic;
signal i_in : signed(26 downto 0);
signal q_in : signed(26 downto 0);
signal i_out : signed(26 downto 0);
signal q_out : signed(26 downto 0);
begin
dut : entity work.pfd
port map(
clk => clk,
stb => stb,
i_in => i_in,
q_in => q_in,
i_out => i_out,
q_out => q_out,
rdy => rdy
);
clk <= not clk after 20345 ps;
process
variable cnt : unsigned(8 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if cnt = 511 then
stb <= '1';
else
stb <= '0';
end if;
cnt := cnt + 1;
end process;
process
variable l : line;
variable ll : integer;
begin
wait until rising_edge(clk);
if stb = '1' then
readline(input, l);
read(l, ll);
i_in <= to_signed(ll, 27);
readline(input, l);
read(l, ll);
q_in <= to_signed(ll, 27);
end if;
if rdy = '1' then
ll := to_integer(i_out);
write(l, ll);
writeline(output, l);
ll := to_integer(q_out);
write(l, ll);
writeline(output, l);
end if;
end process;
end architecture sim;
|
gpl-2.0
|
c5933080bf3b17f1b42695b0927942de
| 0.601421 | 2.575203 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/control.vhd
| 1 | 2,855 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:16:12 11/02/2011
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
inicioIn : in STD_LOGIC;
filasBolita : in STD_LOGIC_VECTOR (7 downto 0);
columnasJugador: in STD_LOGIC_VECTOR (7 downto 0);
columnasBolita : in STD_LOGIC_VECTOR (7 downto 0);
visible : out STD_LOGIC;
inicioOut : out STD_LOGIC;
puntajeOut : out STD_LOGIC_VECTOR (3 downto 0);
filas : out STD_LOGIC_VECTOR (7 downto 0);
columnas : out STD_LOGIC_VECTOR (7 downto 0)
);
end control;
architecture Behavioral of control is
type estados is (inicio, jugando, victoria, derrota);
signal estado : estados;
signal puntaje : STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk, reset, inicioIn, filasBolita, columnasJugador, columnasBolita, estado, puntaje)
begin
if reset = '1' then
estado <= inicio;
puntaje <= "0000";
visible <= '0';
inicioOut <= '1';
puntajeOut <= "0000";
filas <= "00000000";
columnas <= "00000000";
elsif clk'event and clk = '1' then
case estado is
when inicio =>
inicioOut<= '1';
visible <= '0';
puntaje <= "0000";
if (inicioIn = '1') then
estado <= jugando;
end if;
when jugando =>
inicioOut<= '0';
visible <= '0';
if filasBolita = "10000000" then
if columnasJugador = columnasBolita then
if (puntaje = 9) then
estado <= victoria;
else
puntaje <= puntaje + 1;
puntajeOut <= puntaje + 1;
end if;
else
estado <= derrota;
end if;
end if;
when victoria =>
inicioOut <= '1';
visible <= '1';
filas <= "10000001";
columnas <= "11111111";
if inicioIn = '1' then
estado <= inicio;
end if;
when derrota =>
inicioOut <= '1';
visible <= '1';
filas <= "11111111";
columnas <= "11111111";
if inicioIn = '1' then
estado <= inicio;
end if;
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
5f06ddeb3a9ee5bfa499c59ea04f68e9
| 0.57373 | 3.382701 | false | false | false | false |
dl3yc/sdr-fm
|
testing/euler-1.0/inc/vcordic.vhd
| 1 | 2,326 |
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with some test cases
-- - known bug: don't use the phase!
--
-- !!! because of the arctan table used in the CORDIC algorithm
-- !!! it only converges in the range of -99.7° to 99.7°
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of vcordic is
type alpha_t is array(0 to N-1) of signed(P-1 downto 0); -- -180°..180°
type xy_vector is array(natural range <>) of signed(A+2 downto 0); -- -3.999..+3.999
type z_vector is array(natural range <>) of signed(P-1 downto 0); -- -180°..180°
constant K : signed(A-1 downto 0) := to_signed(integer(0.6073*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) * (real(2**(P-1))-1.0) / math_pi ),P);
end generate;
process begin
wait until rising_edge(clk);
if i >= 0 then
x(0) <= resize(i,A+3);
y(0) <= resize(q,A+3);
z(0) <= (others => '0');
elsif q >= 0 then
x(0) <= resize(q,A+3);
y(0) <= resize(-i,A+3);
z(0) <= to_signed(2**(P-2),P);-- 90°
report "buggy phase!" severity warning;
else
x(0) <= resize(-q,A+3);
y(0) <= resize(i,A+3);
z(0) <= to_signed(-2**(P-2),P);-- -90°
report "buggy phase!" severity warning;
end if;
for i in 1 to N loop
if x(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
end if;
end loop;
amp <= resize(unsigned(shift_right((y(N) * K), (A-1))),A);
phi <= z(N);
end process;
end behavioral;
|
gpl-2.0
|
3d002ff08a7763ec7f9d1c8f77c6345e
| 0.568594 | 2.422153 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_1_0/sim/DemoInterconnect_axi_spi_master_1_0.vhd
| 2 | 10,931 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_0_arch OF DemoInterconnect_axi_spi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_0_arch;
|
mit
|
83ddadc68ca158eac414cdf2e1011dd6
| 0.712744 | 3.190601 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AB_HAA_TB.vhd
| 1 | 1,235 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AB_HAA_TB IS
END LatchSR_AB_HAA_TB;
ARCHITECTURE behavior OF LatchSR_AB_HAA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AB_HAA
PORT(
Sn : IN std_logic;
Rn : IN std_logic;
EN : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
--Inputs
signal Sn : std_logic := '0';
signal Rn : std_logic := '0';
signal EN : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LatchSR_AB_HAA PORT MAP (
Sn => Sn,
Rn => Rn,
EN => EN,
Q => Q,
Qn => Qn
);
-- Stimulus process
stim_proc: process
begin
-- EN = '1', S = '0' y R = '0';
EN <= '1';
wait for 100 ns;
-- EN = '1', S = '0' y R = '1';
Rn <= '1';
wait for 100 ns;
-- EN = '1', S = '1' y R = '0';
Sn <= '1';
Rn <= '0';
wait for 100 ns;
-- EN = '1', S = '1' y R = '1';
Rn <= '1';
wait for 100 ns;
-- EN = '0', S = 'x' y R = 'x';
EN <= '0';
wait;
end process;
END;
|
gpl-3.0
|
d4bcc99cea1d60c7f9f06584dff83aaf
| 0.468016 | 2.997573 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/PISO_TB.vhd
| 1 | 1,180 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PISO_TB IS
END PISO_TB;
ARCHITECTURE behavior OF PISO_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PISO
PORT(
SL : IN std_logic;
clk : IN std_logic;
A : IN std_logic_vector(3 downto 0);
S : OUT std_logic
);
END COMPONENT;
--Inputs
signal SL : std_logic := '0';
signal clk : std_logic := '0';
signal A : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal S : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PISO PORT MAP (
SL => SL,
clk => clk,
A => A,
S => S
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
SL <= '1';
A <= "1011";
wait for 10 ns;
SL <= '0';
A <= "0000";
wait;
end process;
END;
|
gpl-3.0
|
d7c6888573da3b52ccd8ab40d31e567e
| 0.539831 | 3.440233 | false | false | false | false |
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/hdl/internoc_ni_axi_master_v1_0_M00_AXI.vhd
| 2 | 27,495 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.internoc_pack.all;
entity internoc_ni_axi_master_v1_0_M00_AXI is
generic (
-- Users to add parameters here
C_IF00_DATA_WIDTH : integer := 8;
C_PACKET_WIDTH : integer := 40;
C_PACKET_ADDR_WIDTH : integer := 5;
C_PACKET_DATA_WIDTH : integer := 16;
C_PACKET_CTRL_WIDTH : integer := 3;
C_AXI_PACKET_ADDR_OFFSET : integer := 16;
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 5;
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
PACKET_TX : in std_logic_vector(C_PACKET_WIDTH-1 downto 0);
SLV_TYPE : in std_logic_vector(2 downto 0);
-- Initiate AXI transactions
INIT_AXI_TXN : in std_logic;
INIT_AXI_RXN : in std_logic;
-- Asserts when ERROR is detected
ERROR : out std_logic;
-- Asserts when AXI transactions is complete
TXN_DONE : out std_logic;
RXN_DONE : out std_logic;
RXN_DATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- AXI clock signal
M_AXI_ACLK : in std_logic;
-- AXI active low reset signal
M_AXI_ARESETN : in std_logic;
-- Master Interface Write Address Channel ports. Write address (issued by master)
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
-- Write address valid.
-- This signal indicates that the master signaling valid write address and control information.
M_AXI_AWVALID : out std_logic;
-- Write address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
M_AXI_AWREADY : in std_logic;
-- Master Interface Write Data Channel ports. Write data (issued by master)
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes.
-- This signal indicates which byte lanes hold valid data.
-- There is one write strobe bit for each eight bits of the write data bus.
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
-- Write valid. This signal indicates that valid write data and strobes are available.
M_AXI_WVALID : out std_logic;
-- Write ready. This signal indicates that the slave can accept the write data.
M_AXI_WREADY : in std_logic;
-- Master Interface Write Response Channel ports.
-- This signal indicates the status of the write transaction.
M_AXI_BRESP : in std_logic_vector(1 downto 0);
-- Write response valid.
-- This signal indicates that the channel is signaling a valid write response
M_AXI_BVALID : in std_logic;
-- Response ready. This signal indicates that the master can accept a write response.
M_AXI_BREADY : out std_logic;
-- Master Interface Read Address Channel ports. Read address (issued by master)
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
-- Read address valid.
-- This signal indicates that the channel is signaling valid read address and control information.
M_AXI_ARVALID : out std_logic;
-- Read address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
M_AXI_ARREADY : in std_logic;
-- Master Interface Read Data Channel ports. Read data (issued by slave)
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer.
M_AXI_RRESP : in std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is signaling the required read data.
M_AXI_RVALID : in std_logic;
-- Read ready. This signal indicates that the master can accept the read data and response information.
M_AXI_RREADY : out std_logic
);
end internoc_ni_axi_master_v1_0_M00_AXI;
architecture implementation of internoc_ni_axi_master_v1_0_M00_AXI is
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
-- Example State machine to initialize counter, initialize write transactions,
-- initialize read transactions and comparison of read data with the
-- written data words.
type state is ( IDLE, -- This state initiates AXI4Lite transaction
-- after the state machine changes state to INIT_WRITE
-- when there is 0 to 1 transition on INIT_AXI_TXN
INIT_WRITE, -- This state initializes write transaction,
-- once writes are done, the state machine
-- changes state to OP_WRITE
OP_WRITE,
INIT_READ, -- This state initializes read transaction
-- once reads are done, the state machine
-- changes state to INIT_COMPARE
OP_READ);
signal mst_exec_state : state;
-- AXI4LITE signals
--write address valid
signal axi_awvalid : std_logic;
--write data valid
signal axi_wvalid : std_logic;
--read address valid
signal axi_arvalid : std_logic;
--read data acceptance
signal axi_rready : std_logic;
--write response acceptance
signal axi_bready : std_logic;
--write address
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--write data
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--read addresss
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
--Asserts when there is a write response error
signal write_resp_error : std_logic;
--Asserts when there is a read response error
signal read_resp_error : std_logic;
--A pulse to initiate a write transaction
signal start_single_write : std_logic;
--A pulse to initiate a read transaction
signal start_single_read : std_logic;
--register that marks the completion of a write trasactions. The number of write transaction is user selected by the parameter C_M_TRANSACTIONS_NUM.
signal writes_done : std_logic;
--register that marks the completion of a read trasactions. The number of read transaction is user selected by the parameter C_M_TRANSACTIONS_NUM
signal reads_done : std_logic;
--register data from AXI transaction
signal reads_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
--The error register is asserted when any of the write response error, read response error or the data mismatch flags are asserted.
signal error_reg : std_logic;
signal init_txn_ff : std_logic;
signal init_txn_ff2 : std_logic;
signal init_txn_pulse : std_logic;
signal init_rxn_ff : std_logic;
signal init_rxn_ff2 : std_logic;
signal init_rxn_pulse : std_logic;
alias packet_dest_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) is PACKET_TX(C_PACKET_DATA_WIDTH-1 downto 0);
alias packet_dest_address : std_logic_vector(C_PACKET_ADDR_WIDTH-1 downto 0) is PACKET_TX(C_PACKET_DATA_WIDTH+C_PACKET_ADDR_WIDTH-1 downto C_PACKET_DATA_WIDTH);
alias packet_byte_cnt : std_logic_vector(C_PACKET_CTRL_WIDTH-2 downto 0) is PACKET_TX(C_PACKET_WIDTH-2 downto C_PACKET_WIDTH-C_PACKET_CTRL_WIDTH);
begin
-- I/O Connections assignments
--Adding the offset address to the base addr of the slave
M_AXI_AWADDR <= axi_awaddr;
--AXI 4 write data
M_AXI_WDATA <= axi_wdata;
M_AXI_AWPROT <= "000";
M_AXI_AWVALID <= axi_awvalid;
--Write Data(W)
M_AXI_WVALID <= axi_wvalid;
--Set all byte strobes in this example
-- M_AXI_WSTRB <= (others=>'1');
--Write Response (B)
M_AXI_BREADY <= axi_bready;
--Read Address (AR)
M_AXI_ARADDR <= axi_araddr;
M_AXI_ARVALID <= axi_arvalid;
M_AXI_ARPROT <= "001";
--Read and Read Response (R)
M_AXI_RREADY <= axi_rready;
--AXI Master Write Slave Complete
TXN_DONE <= writes_done;
--AXI Master Read Slave Complete
RXN_DONE <= reads_done;
--Data Read from AXI Slave
RXN_DATA <= reads_data;
--Indicate an AXI transaction error
ERROR <= error_reg;
--Check for init transaction pulses
init_txn_pulse <= ( not init_txn_ff2) and init_txn_ff;
init_rxn_pulse <= ( not init_rxn_ff2) and init_rxn_ff;
--Packet de-interleaving
packet_deinterleave: process(PACKET_TX)
begin
axi_awaddr <= (others=>'0');
axi_araddr <= (others=>'0');
if SLV_TYPE=SPI_INTERFACE then
--write address packet assign
axi_awaddr(C_AXI_PACKET_ADDR_OFFSET+C_PACKET_ADDR_WIDTH-1 downto C_AXI_PACKET_ADDR_OFFSET) <= packet_dest_address;
--write data packet assign
axi_wdata <= packet_dest_data;
--read address packet assign
axi_araddr(C_AXI_PACKET_ADDR_OFFSET+C_PACKET_ADDR_WIDTH-1 downto C_AXI_PACKET_ADDR_OFFSET) <= packet_dest_address;
--read data packet assign
--not used
case packet_byte_cnt is
when "00"=>
M_AXI_WSTRB <= "0001";
when "01"=>
M_AXI_WSTRB <= "0011";
when "10"=>
M_AXI_WSTRB <= "0111";
when "11"=>
M_AXI_WSTRB <= "1111";
when others=>
M_AXI_WSTRB <= "1111";
end case;
else
--write address packet assign
axi_awaddr(C_AXI_PACKET_ADDR_OFFSET-1 downto 0) <= packet_dest_data(C_PACKET_DATA_WIDTH-1 downto 16);
axi_awaddr(C_AXI_PACKET_ADDR_OFFSET+C_PACKET_ADDR_WIDTH-1 downto C_AXI_PACKET_ADDR_OFFSET) <= packet_dest_address;
--write data packet assign
axi_wdata <= packet_dest_data;
--read address packet assign
axi_araddr(C_AXI_PACKET_ADDR_OFFSET-1 downto 0) <= packet_dest_data(C_PACKET_DATA_WIDTH-1 downto 16);
axi_araddr(C_AXI_PACKET_ADDR_OFFSET+C_PACKET_ADDR_WIDTH-1 downto C_AXI_PACKET_ADDR_OFFSET) <= packet_dest_address;
--read data packet assign
--not used
M_AXI_WSTRB <= "0001";
end if;
end process;
--Generate a pulse to initiate AXI transaction.
gen_txn_pulse: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
-- Initiates AXI transaction delay
if (M_AXI_ARESETN = '0' ) then
init_txn_ff <= '0';
init_txn_ff2 <= '0';
else
init_txn_ff <= INIT_AXI_TXN;
init_txn_ff2 <= init_rxn_ff;
end if;
end if;
end process;
gen_rxn_pulse: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
-- Initiates AXI transaction delay
if (M_AXI_ARESETN = '0' ) then
init_rxn_ff <= '0';
init_rxn_ff2 <= '0';
else
init_rxn_ff <= INIT_AXI_RXN;
init_rxn_ff2 <= init_rxn_ff;
end if;
end if;
end process;
----------------------
--Write Address Channel
----------------------
-- The purpose of the write address channel is to request the address and
-- command information for the entire transaction. It is a single beat
-- of information.
-- Note for this example the axi_awvalid/axi_wvalid are asserted at the same
-- time, and then each is deasserted independent from each other.
-- This is a lower-performance, but simplier control scheme.
-- AXI VALID signals must be held active until accepted by the partner.
-- A data transfer is accepted by the slave when a master has
-- VALID data and the slave acknoledges it is also READY. While the master
-- is allowed to generated multiple, back-to-back requests by not
-- deasserting VALID, this design will add rest cycle for
-- simplicity.
-- Since only one outstanding transaction is issued by the user design,
-- there will not be a collision between a new request and an accepted
-- request on the same clock cycle.
wr_addr_channel: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
--Only VALID signals must be deasserted during reset per AXI spec
--Consider inverting then registering active-low reset for higher fmax
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_awvalid <= '0';
else
--Signal a new address/data command is available by user logic
if (start_single_write = '1') then
axi_awvalid <= '1';
elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
--Address accepted by interconnect/slave (issue of M_AXI_AWREADY by slave)
axi_awvalid <= '0';
end if;
end if;
end if;
end process;
----------------------
--Write Data Channel
----------------------
--The write data channel is for transfering the actual data.
--The data generation is speific to the example design, and
--so only the WVALID/WREADY handshake is shown here
wr_data_channel: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
axi_wvalid <= '0';
else
if (start_single_write = '1') then
--Signal a new address/data command is available by user logic
axi_wvalid <= '1';
elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
--Data accepted by interconnect/slave (issue of M_AXI_WREADY by slave)
axi_wvalid <= '0';
end if;
end if;
end if;
end process;
------------------------------
--Write Response (B) Channel
------------------------------
--The write response channel provides feedback that the write has committed
--to memory. BREADY will occur after both the data and the write address
--has arrived and been accepted by the slave, and can guarantee that no
--other accesses launched afterwards will be able to be reordered before it.
--The BRESP bit [1] is used indicate any errors from the interconnect or
--slave for the entire write burst. This example will capture the error.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
wr_resp_channel: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_bready <= '0';
else
if (M_AXI_BVALID = '1' and axi_bready = '0') then
-- accept/acknowledge bresp with axi_bready by the master
-- when M_AXI_BVALID is asserted by slave
axi_bready <= '1';
elsif (axi_bready = '1') then
-- deassert after one clock cycle
axi_bready <= '0';
end if;
end if;
end if;
end process;
--Flag write errors
write_resp_error <= (axi_bready and M_AXI_BVALID and M_AXI_BRESP(1));
------------------------------
--Read Address Channel
------------------------------
-- A new axi_arvalid is asserted when there is a valid read address
-- available by the master. start_single_read triggers a new read
-- transaction
rd_addr_channel: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_arvalid <= '0';
else
if (start_single_read = '1') then
--Signal a new read address command is available by user logic
axi_arvalid <= '1';
elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
--RAddress accepted by interconnect/slave (issue of M_AXI_ARREADY by slave)
axi_arvalid <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--Read Data (and Response) Channel
----------------------------------
--The Read Data channel returns the results of the read request
--The master will accept the read data by asserting axi_rready
--when there is a valid read data available.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
rd_dataresp_channel: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
axi_rready <= '1';
else
if (M_AXI_RVALID = '1' and axi_rready = '0') then
-- accept/acknowledge rdata/rresp with axi_rready by the master
-- when M_AXI_RVALID is asserted by slave
axi_rready <= '1';
elsif (axi_rready = '1') then
-- deassert after one clock cycle
axi_rready <= '0';
end if;
end if;
end if;
end process;
--Flag write errors
read_resp_error <= (axi_rready and M_AXI_RVALID and M_AXI_RRESP(1));
----------------------------------
--User Logic
----------------------------------
--implement master command interface state machine
ctrl_master_fsm: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' ) then
-- reset condition
-- All the signals are ed default values under reset condition
mst_exec_state <= IDLE;
start_single_write <= '0';
start_single_read <= '0';
else
-- state transition
case (mst_exec_state) is
when IDLE =>
-- This state is responsible to initiate
-- AXI transaction when init_txn_pulse is asserted
reads_done <= '0';
writes_done <= '0';
if ( init_txn_pulse = '1') then
mst_exec_state <= INIT_WRITE;
elsif (init_rxn_pulse = '1') then
mst_exec_state <= INIT_READ;
else
mst_exec_state <= IDLE;
end if;
when INIT_WRITE =>
start_single_write <= '1';
mst_exec_state <= OP_WRITE;
when OP_WRITE=>
start_single_write <= '0';
error_reg <= write_resp_error or read_resp_error;
if (axi_bready = '1') then
writes_done <= '1';
mst_exec_state <= IDLE;
end if;
when INIT_READ =>
start_single_read <= '1';
mst_exec_state <= OP_READ;
when OP_READ=>
start_single_read <= '0';
error_reg <= write_resp_error or read_resp_error;
if (axi_rready = '1') then
reads_done <= '1';
reads_data <= M_AXI_RDATA;
mst_exec_state <= IDLE;
end if;
when others =>
mst_exec_state <= IDLE;
end case;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end implementation;
|
mit
|
e1ffabc7e8e64b32cb1f4edb69f61bc7
| 0.443462 | 4.952269 | false | false | false | false |
andbet050197/IS773UTP
|
modulo2/Motorapasos.vhd
| 1 | 2,365 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:00:13 03/01/2017
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Motor_a_pasos is
Port ( StepDrive : out std_logic_vector(3 downto 0);
Direction : in std_logic;
StepEnable : in std_logic;
CLK : in std_logic);
end Motor_a_pasos;
--Direction: indica la dirección a la que va a girar el motor
--StepEnable: switch que activa o no el movimiento del motor
--CLK: para llevar un conteo de pasos
--StepDrive: las salidas de los 4 pines.
architecture Behavioral of Motor_a_pasos is
--Variables temporales:
signal aux : std_logic_vector (3 downto 0) := "0000";
signal state : std_logic_vector(1 downto 0) := "00";
signal StepCounter : std_logic_vector(31 downto 0) := (others => '0');
constant StepLockOut : std_logic_vector(31 downto 0) := "00000000000001111010000100100000";
begin
--State: los posibles estados del motor.
--StepCounter: contador que aumenta cada vez que encuentra un flanco de subida en la señal de reloj.
--StepLockOut: indica la frecuencia a la cual el motor va a dar cada paso.
StepDrive <= aux;
process(CLK)
begin
if ((CLK'event) and (CLK='1')) then --Esto indica que cada vez que el reloj
StepCounter <= StepCounter + 1; -- este en frente de subida se le
--aumentará en 1 a StepCounter
if (StepCounter >= StepLockOut) then --Se resetea el contador
StepCounter <= (others => '0'); --si es mayor a la frecuencia
aux <= "1111";
if (StepEnable = '1') then --Habilitador activado
if (Direction = '1') then state <= state + "01"; end if;
if (Direction = '0') then state <= state - "01"; end if;
case state is --Determina hacia dónde va a girar
when "00" =>aux <= "1000";
when "01" =>aux <= "0100";
when "10" =>aux <= "0010";
when "11" =>aux <= "0001";
when others => end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
600f50a360cb57407f62956beee7e54f
| 0.603805 | 3.388252 | false | false | false | false |
ktemkin/ruby-adept
|
firmware/epp_stream/epp_controller.vhd
| 1 | 5,976 |
----------------------------------------------------------------------------------
-- EPP Controller
--
-- Original Author: Chris McClelland
-- Altered for use with EPP periperhals by Kyle Temkin
--
-- Portions copyright (c) 2013 Binghamton University
-- Copyright (c) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.-
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
iThisR3 when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
mit
|
fce13ee38c004397f6048a9c7b30fb9c
| 0.602744 | 3.641682 | false | false | false | false |
rmilfont/Phoenix
|
NoC/NOC.vhd
| 1 | 4,753 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
entity NOC is
port(
clock : in regNrot;
reset : in std_logic;
clock_rxLocal : in regNrot;
rxLocal : in regNrot;
data_inLocal_flit : in arrayNrot_regflit;
credit_oLocal : out regNrot;
clock_txLocal : out regNrot;
txLocal : out regNrot;
data_outLocal_flit : out arrayNrot_regflit;
credit_iLocal : in regNrot
);
end NOC;
architecture NOC of NOC is
signal data_inLocal, data_outLocal: arrayNrot_regphit;
signal retransmission_i, retransmission_o, rx, clock_rx, credit_i, tx, clock_tx, credit_o, testLink_i, testLink_o : arrayNrot_regNport;
signal data_in, data_out : matrixNrot_Nport_regphit;
begin
fillLocalFlits: for i in 0 to NROT-1 generate
begin
data_inLocal(i) <= data_inLocal_flit(i) & CONV_STD_LOGIC_VECTOR(0,TAM_HAMM);
data_outLocal_flit(i) <= data_outLocal(i)(TAM_PHIT-1 downto TAM_HAMM);
end generate;
Router: for i in 0 to (NROT-1) generate
n : Entity work.RouterCC
generic map( address => NUMBER_TO_ADDRESS(i)((METADEFLIT-1) downto 0))
port map(
clock => clock(i),
reset => reset,
clock_rx => clock_rx(i),
rx => rx(i),
data_in => data_in(i),
credit_o => credit_o(i),
clock_tx => clock_tx(i),
tx => tx(i),
data_out => data_out(i),
credit_i => credit_i(i),
testLink_i => testLink_i(i),
testLink_o => testLink_o(i),
retransmission_i => retransmission_i(i),
retransmission_o => retransmission_o(i)
);
end generate Router;
link1: for i in 0 to (NROT-1) generate
east: if i < NUM_Y*MAX_X generate
clock_rx(i)(0) <= clock_tx(i+NUM_Y)(1);
rx(i)(0) <= tx(i+NUM_Y)(1);
data_in(i)(0) <= data_out(i+NUM_Y)(1);
credit_i(i)(0) <= credit_o(i+NUM_Y)(1);
testLink_i(i)(0) <= testLink_o(i+NUM_Y)(1);
retransmission_i(i)(0) <= retransmission_o(i+NUM_Y)(1);
end generate east;
west: if i >= NUM_Y generate
clock_rx(i)(1) <= clock_tx(i-NUM_Y)(0);
rx(i)(1) <= tx(i-NUM_Y)(0);
data_in(i)(1) <= data_out(i-NUM_Y)(0);
credit_i(i)(1) <= credit_o(i-NUM_Y)(0);
testLink_i(i)(1) <= testLink_o(i-NUM_Y)(0);
retransmission_i(i)(1) <= retransmission_o(i-NUM_Y)(0);
end generate west;
north: if (i-(i/NUM_Y)*NUM_Y) < MAX_Y generate
clock_rx(i)(2) <= clock_tx(i+1)(3);
rx(i)(2) <= tx(i+1)(3);
data_in(i)(2) <= data_out(i+1)(3);
credit_i(i)(2) <= credit_o(i+1)(3);
testLink_i(i)(2) <= testLink_o(i+1)(3);
retransmission_i(i)(2) <= retransmission_o(i+1)(3);
end generate north;
south: if (i-(i/NUM_Y)*NUM_Y) > MIN_Y generate
clock_rx(i)(3) <= clock_tx(i-1)(2);
rx(i)(3) <= tx(i-1)(2);
data_in(i)(3) <= data_out(i-1)(2);
credit_i(i)(3) <= credit_o(i-1)(2);
testLink_i(i)(3) <= testLink_o(i-1)(2);
retransmission_i(i)(3) <= retransmission_o(i-1)(2);
end generate south;
end generate link1;
link2 : for i in 0 to (NROT-1) generate
-- LOCAL port
clock_rx(i)(LOCAL) <= clock_rxLocal(i);
data_in(i)(LOCAL) <= data_inLocal(i);
credit_i(i)(LOCAL) <= credit_iLocal(i);
rx(i)(LOCAL) <= rxLocal(i);
clock_txLocal(i) <= clock_tx(i)(LOCAL);
data_outLocal(i) <= data_out(i)(LOCAL);
credit_oLocal(i) <= credit_o(i)(LOCAL);
txLocal(i) <= tx(i)(LOCAL);
testLink_i(i)(LOCAL) <= '0';
retransmission_i(i)(LOCAL) <= '0';
end generate link2;
end NOC;
|
lgpl-3.0
|
f04b024afa63fa4693e6f1956c2dc690
| 0.44393 | 3.505162 | false | true | false | false |
egk696/InterNoC
|
ip_repo/axi_i2c_master_1.0/src/I2C_Master.vhd
| 1 | 8,265 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Eleftherios Kyriakakis
--
-- Create Date: 11/02/2017 04:43:17 PM
-- Design Name:
-- Module Name: I2C_Master - behave
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity I2C_Master is
Generic ( CLK_DIV : integer := 720);
Port ( io_sda : inout std_logic;
io_scl : inout std_logic;
i_clk : in std_logic;
i_tx_init : in std_logic;
i_rx_init : in std_logic;
i_tx_data : in std_logic_VECTOR (7 downto 0);
i_slv_addr : in std_logic_VECTOR (6 downto 0);
i_reg_addr : in std_logic_VECTOR (7 downto 0);
o_rx_data : out std_logic_VECTOR (7 downto 0);
o_i2c_busy : out std_logic;
o_i2c_done : out std_logic);
end I2C_Master;
architecture behave of I2C_Master is
--Constants
constant BIT_COUNT : integer := 7;
--Bus
signal sda_release : std_logic := '1';
signal sda_in : std_logic := '0';
signal scl_release : std_logic := '1';
signal scl_in : std_logic := '0';
--Buffers
signal slv_addr_rw : std_logic_VECTOR(7 downto 0);
signal reg_addr : std_logic_VECTOR(7 downto 0);
signal tx_data : std_logic_VECTOR(7 downto 0);
signal rx_data : std_logic_VECTOR(7 downto 0);
--Counters
signal scl_div_count : integer range 0 to CLK_DIV+1 := CLK_DIV;
signal scl_bit_count : integer range 0 to 7 := BIT_COUNT;
--FSM
type i2c_fsm_type is
(
ST_IDLE,
ST_START,
ST_TX_DEV_ADDR,
ST_RX_ACK_1,
ST_TX_REG_ADDR,
ST_RX_ACK_2,
ST_TX_DATA,
ST_RX_ACK_3,
ST_RX_DATA,
ST_TX_NACK,
ST_STOP
);
signal state : i2c_fsm_type := ST_IDLE;
--Control
signal i2c_tx_grnt : std_logic := '0';
signal i2c_rx_grnt : std_logic := '0';
signal i2c_rx_done : std_logic := '0';
begin
o_i2c_busy <= i2c_tx_grnt or i2c_rx_grnt;
o_i2c_done <= i2c_rx_done;
--single master support only...
sclbuf_inst: IOBUF
port map(
I=>'0',
O=>scl_in,
IO=>io_scl,
T=>scl_release
);
--single master support only...
sdabuf_inst: IOBUF
port map(
I=>'0',
O=>sda_in,
IO=>io_sda,
T=>sda_release
);
p_gen_scl: process(i_clk)
begin
if rising_edge(i_clk) then
if (i2c_tx_grnt or i2c_rx_grnt) then
if (scl_div_count=0) then
scl_div_count <= CLK_DIV;
scl_release <= not(scl_release);
else
scl_div_count <= scl_div_count - 1;
end if;
else
scl_release <= '1'; --if not i2c-ing release to float 'Z'
end if;
end if;
end process;
p_i2c_fsm: process(i_clk)
variable old_scl_release : std_logic := '1';
begin
if rising_edge(i_clk) then
case state is
when ST_IDLE=>
sda_release <= '1'; --if IDLE then release to float 'Z'
i2c_rx_grnt <= '0';
i2c_tx_grnt <= '0';
if (i_tx_init='1') then
slv_addr_rw <= i_slv_addr & '0'; --pack together with r/w for easier shift
reg_addr <= i_reg_addr;
tx_data <= i_tx_data;
i2c_tx_grnt <= '1'; --grant TX
state <= ST_START;
elsif (i_rx_init='1') then
slv_addr_rw <= i_slv_addr & '0'; --pack together with r/w for easier shift
reg_addr <= i_reg_addr;
i2c_rx_grnt <= '1'; --grant RX
state <= ST_START;
end if;
when ST_START=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
sda_release <= '0'; --transition from high-to-low while SCL high
state <= ST_TX_DEV_ADDR;
end if;
when ST_TX_DEV_ADDR=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
if (scl_bit_count=0) then
scl_bit_count <= BIT_COUNT;
state <= ST_RX_ACK_1;
sda_release <= '1';
else
scl_bit_count <= scl_bit_count - 1;
end if;
elsif (old_scl_release='1' and scl_release='0') then --falling edge SCL
sda_release <= slv_addr_rw(scl_bit_count); --shift out TX MSB
end if;
when ST_RX_ACK_1=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
if (sda_in='0') then
state <= ST_TX_REG_ADDR;
end if;
end if;
when ST_TX_REG_ADDR=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
if (scl_bit_count=0) then
scl_bit_count <= BIT_COUNT;
state <= ST_RX_ACK_2;
else
scl_bit_count <= scl_bit_count - 1;
end if;
elsif (old_scl_release='1' and scl_release='0') then --falling edge SCL
sda_release <= reg_addr(scl_bit_count); --shift out TX MSB
end if;
when ST_RX_ACK_2=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
if (sda_in='0') then
state <= ST_TX_DATA;
end if;
end if;
when ST_TX_DATA=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
if (scl_bit_count=0) then
scl_bit_count <= BIT_COUNT;
state <= ST_RX_ACK_2;
else
scl_bit_count <= scl_bit_count - 1;
end if;
elsif (old_scl_release='1' and scl_release='0') then --falling edge SCL
sda_release <= tx_data(scl_bit_count); --shift out TX MSB
end if;
when ST_RX_ACK_3=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
if (sda_in='0') then
state <= ST_STOP;
end if;
end if;
when ST_RX_DATA=>
state <= ST_IDLE;
when ST_TX_NACK=>
state <= ST_IDLE;
when ST_STOP=>
if (old_scl_release='0' and scl_release='1') then --rising edge SCL
sda_release <= '1';
state <= ST_IDLE;
slv_addr_rw <= (others=>'0'); --pack together with r/w for easier shift
reg_addr <= (others=>'0');
tx_data <= (others=>'0');
tx_done <= '1';
end if;
end case;
old_scl_release := scl_release; --register after the case because it is a variable
end if;
end process;
end behave;
|
mit
|
b90adda9954cb3896fdd3da805f0c928
| 0.438959 | 3.958333 | false | false | false | false |
andbet050197/IS773UTP
|
modulo3/Rx.vhd
| 1 | 2,074 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Rx is
Port ( Dato_entrada : in STD_LOGIC;
CLK : in STD_LOGIC;
Dato_salida : out STD_LOGIC_VECTOR (7 downto 0);
Campana : out STD_LOGIC);
end Rx;
architecture Behavioral of Rx is
COMPONENT Divisor
PORT(
clk : IN std_logic;
newC : OUT std_logic
);
END COMPONENT;
signal reloj_baudios : std_logic := '0';
signal estado : std_logic_vector(1 downto 0) := "00";
-- 00 -> Recepcion de Idle
-- 01 -> Recepcion de dato
-- 10 -> bit de paridad
-- 11 -> bits de parada
signal contador_de_bits : std_logic_vector(3 downto 0) := "0000";
signal Paridad : std_logic := '0';
signal aux : std_logic_vector(7 downto 0) := "00000000";
begin
Inst_Divisor: Divisor PORT MAP(
clk => CLK,
newC => reloj_baudios
);
Dato_salida <= aux;
process (CLK)
variable Dato_temporal : std_logic_vector(7 downto 0) := (others => '0');
begin
if (rising_edge(CLK) and reloj_baudios = '1') then
Campana <= '0';
if (estado = "00" and Dato_entrada = '0') then
estado <= "01";
elsif (estado = "01") then
if (Dato_entrada = '1') then
Paridad <= not Paridad;
end if;
Dato_temporal(6 downto 0) := Dato_temporal(7 downto 1);
Dato_temporal(7) := Dato_entrada;
contador_de_bits <= contador_de_bits + 1;
if (contador_de_bits >= "0111") then
contador_de_bits <= (others => '0');
estado <= "10";
end if;
elsif (estado = "10") then
if (Paridad = Dato_entrada) then
estado <= "11";
else
estado <= "00";
Paridad <= '0';
end if;
elsif (estado = "11") then
if (contador_de_bits = "0001") then
estado <= "00";
contador_de_bits <= (others => '0');
aux <= Dato_temporal;
Campana <= '1';
elsif (Dato_entrada = '1') then
contador_de_bits <= contador_de_bits + 1;
else
estado <= "00";
Paridad <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
374f14fa6e902758d8bd8cd6e45123d2
| 0.567502 | 3.023324 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/PISO.vhd
| 1 | 593 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PISO is
Port ( SL : in STD_LOGIC;
clk : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
S : out STD_LOGIC);
end PISO;
architecture Behavioral of PISO is
signal aux : std_logic := '0';
begin
S <= aux;
process (clk , SL, A) is
variable temp : std_logic_vector (3 downto 0);
begin
if (SL='1') then
temp := A ;
elsif (rising_edge (clk)) then
aux <= temp(0);
temp := '0' & temp(3 downto 1);
end if;
end process;
end Behavioral;
|
gpl-3.0
|
7f0a11311aa1558fc593116d7e61a38b
| 0.536256 | 3.294444 | false | false | false | false |
egk696/InterNoC
|
ip_repo/uart_transceiver_v1_0/uart_tx.vhd
| 3 | 3,921 |
----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Transmitter. This transmitter is able
-- to transmit 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When transmit is complete o_TX_Done will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end UART_TX;
architecture RTL of UART_TX is
type t_SM_Main is (s_Idle, s_TX_Start_Bit, s_TX_Data_Bits,
s_TX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_TX_Data : std_logic_vector(7 downto 0) := (others => '0');
signal r_TX_Done : std_logic := '0';
begin
p_UART_TX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
o_TX_Active <= '0';
o_TX_Serial <= '1'; -- Drive Line High for Idle
r_TX_Done <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if i_TX_DV = '1' then
r_TX_Data <= i_TX_Byte;
r_SM_Main <= s_TX_Start_Bit;
o_TX_Active <= '1';
else
r_SM_Main <= s_Idle;
end if;
-- Send out Start Bit. Start bit = 0
when s_TX_Start_Bit =>
o_TX_Serial <= '0';
-- Wait g_CLKS_PER_BIT-1 clock cycles for start bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Start_Bit;
else
r_Clk_Count <= 0;
r_SM_Main <= s_TX_Data_Bits;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles for data bits to finish
when s_TX_Data_Bits =>
o_TX_Serial <= r_TX_Data(r_Bit_Index);
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Clk_Count <= 0;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_TX_Stop_Bit;
end if;
end if;
-- Send out Stop bit. Stop bit = 1
when s_TX_Stop_Bit =>
o_TX_Serial <= '1';
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_TX_Stop_Bit;
else
r_TX_Done <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
o_TX_Active <= '0';
r_TX_Done <= '1';
r_SM_Main <= s_Idle;
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_TX;
o_TX_Done <= r_TX_Done;
end RTL;
|
mit
|
81ef9592bed1f4af2f290a6a70032b27
| 0.472584 | 3.351282 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/SIPO_TB.vhd
| 1 | 1,159 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SIPO_TB IS
END SIPO_TB;
ARCHITECTURE behavior OF SIPO_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SIPO
PORT(
I : IN std_logic;
CLR : IN std_logic;
CLK : IN std_logic;
O : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal I : std_logic := '0';
signal CLR : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal O : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SIPO PORT MAP (
I => I,
CLR => CLR,
CLK => CLK,
O => O
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
I <= '1';
wait for 10 ns;
I <= '0';
wait for 20 ns;
I <= '1';
wait for 40 ns;
I <= '0';
wait;
end process;
END;
|
gpl-3.0
|
ff348022320f917d35a0daeb7031af89
| 0.540984 | 3.349711 | false | false | false | false |
rmilfont/Phoenix
|
NoC/RouterCC.vhd
| 1 | 15,205 |
---------------------------------------------------------------------------------------
-- ROUTER
--
--
-- NORTH LOCAL
-- -----------------------------------
-- | ****** ****** |
-- | *FILA* *FILA* |
-- | ****** ****** |
-- | ************* |
-- | * ARBITRO * |
-- | ****** ************* ****** |
-- WEST | *FILA* ************* *FILA* | EAST
-- | ****** * CONTROLE * ****** |
-- | ************* |
-- | ****** |
-- | *FILA* |
-- | ****** |
-- -----------------------------------
-- SOUTH
--
-- As chaves realizam a transferência de mensagens entre ncleos.
-- A chave possui uma lógica de controle de chaveamento e 5 portas bidirecionais:
-- East, West, North, South e Local. Cada porta possui uma fila para o armazenamento
-- temporário de flits. A porta Local estabelece a comunicação entre a chave e seu
-- ncleo. As demais portas ligam a chave à chaves vizinhas.
-- Os endereços das chaves são compostos pelas coordenadas XY da rede de interconexão,
-- onde X sãa posição horizontal e Y a posição vertical. A atribuição de endereços é
-- chaves é necessária para a execução do algoritmo de chaveamento.
-- Os módulos principais que compõem a chave são: fila, árbitro e lógica de
-- chaveamento implementada pelo controle_mux. Cada uma das filas da chave (E, W, N,
-- S e L), ao receber um novo pacote requisita chaveamento ao árbitro. O árbitro
-- seleciona a requisição de maior prioridade, quando existem requisições simultâneas,
-- e encaminha o pedido de chaveamento é lógica de chaveamento. A lógica de
-- chaveamento verifica se é possível atender é solicitação. Sendo possível, a conexão
-- é estabelecida e o árbitro é informado. Por sua vez, o árbitro informa a fila que
-- começa a enviar os flits armazenados. Quando todos os flits do pacote foram
-- enviados, a conexão é concluída pela sinalização, por parte da fila, através do
-- sinal sender.
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
use STD.textio.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
USE ieee.math_real.ALL; -- for UNIFORM, TRUNC functions
entity RouterCC is
generic( address: regmetadeflit);
port(
clock: in std_logic;
reset: in std_logic;
testLink_i: in regNport;
credit_i: in regNport;
clock_rx: in regNport;
rx: in regNport;
data_in: in arrayNport_regphit;
retransmission_i: in regNPort;
testLink_o: out regNport;
credit_o: out regNport;
clock_tx: out regNport;
tx: out regNport;
data_out: out arrayNport_regphit;
retransmission_o: out regNPort);
end RouterCC;
architecture RouterCC of RouterCC is
signal h, ack_h, data_av, sender, data_ack: regNport := (others=>'0');
signal data: arrayNport_regflit := (others=>(others=>'0'));
signal mux_in, mux_out: arrayNport_reg3 := (others=>(others=>'0'));
signal free: regNport := (others=>'0');
signal retransmission_in_buf: regNport := (others=>'0');
signal retransmission_out: regNPort:= (others=>'0'); -- sinal que solicita retransmissao do flit, pois o Decoder nao conseguiu arrumar o erro
------------New Hardware------------
signal c_ctrl : std_logic;
signal c_CodControle : regflit;
signal c_BuffCtrl : buffControl;
signal c_ceTR : std_logic; --[c_ce][T]abela[R]oteamento
signal c_ceTF : regNport := (others=>'0'); --[c_ce][T]abela[F]alhas
signal c_BuffTabelaFalhas : row_FaultTable_Nport_Ports := (others=>(others=>(others=>'0')));
signal c_erro_ArrayFind : ArrayRouterControl;
signal c_erro_dir : regNport;
signal c_tabela_falhas: row_FaultTable_Ports;
signal c_test_link_out: regNport;
signal c_data_test: regFlit;
signal credit_i_A : regNport;
signal credit_o_A : regNport;
signal data_out_A : arrayNport_regflit;
signal c_stpLinkTst : regNport;
signal c_strLinkTst : regNport;
signal c_faultTableFDM : regNport;
signal c_strLinkTstOthers : regNport := (others=>'0');
signal c_strLinkTstAll: std_logic := '0';
-- sinais do FPPM
signal row_FaultTablePorts_out: row_FaultTable_Ports := (others=>(others=>'0')); -- linha a ser escrita na tabela de falhas
signal write_FaultTable: regHamm_Nport := (others=>'0'); -- sinal para indicar escrita na tabela de falhas
signal statusHamming: array_statusHamming; -- status da decodificacao (sem erro, erro corrigido, erro detectado)
-- sinais para o Hamming Code
-- saida (Encode)
signal dataOutHamming: arrayNport_regphit; -- dado de saida codificado (dado + paridade)
signal data_out_B: arrayNport_regflit; -- dado de saida
-- entrada (Decode)
signal parity_dataOutHamming: arrayNport_reghamm; -- paridade do dado de saida
signal dataInHamming: arrayNport_regflit; -- dado de entrada (sem paridade)
signal parity_dataInHamming: arrayNport_reghamm; -- paridade de entrada
signal dataDecoded: arrayNport_regflit; -- dado corrigido
signal parityDecoded: arrayNport_reghamm; -- paridade corrigida
signal statusDecoded: arrayNport_reg3; -- status da decodificacao (sem erro, erro corrigido, erro detectado)
signal aux_tx: regNport;
begin
tx <= aux_tx;
dataDecoded(LOCAL) <= data_in(LOCAL)(TAM_PHIT-1 downto TAM_HAMM); -- nao tem Hamming nos links locais
parityDecoded(LOCAL) <= (others=>'0'); -- nao tem Hamming nos links locais
statusDecoded(LOCAL) <= (others=>'0');
parity_dataOutHamming(LOCAL) <= (others=>'0');
FPPM_cast: for i in 0 to HAMM_NPORT-1 generate
begin
statusHamming(i) <= statusDecoded(i);
end generate;
retransmission_o <= retransmission_out;
retransmission_out(LOCAL) <= '0';
HammingData: for i in 0 to NPORT-1 generate
begin
dataOutHamming(i) <= data_out_B(i) & parity_dataOutHamming(i);
dataInHamming(i) <= data_in(i)(TAM_PHIT-1 downto TAM_HAMM);
parity_dataInHamming(i) <= data_in(i)(TAM_HAMM-1 downto 0);
end generate;
-- manda testLink_o = '1' para todas portas de saida QUANDO algum buffer detectar pacote de controle do tipo TEST_LINKS
testLink_o <= (others=>'1') when c_strLinkTst /= x"0"
else (others=>'0');
-- manda aos buffers c_strLinkTstOthers = '1' QUANDO receber de algum roteador vizinho pedir para testar o link
c_strLinkTstOthers <= (others=>'1') when testLink_i /= x"0"
else (others=>'0');
Faulter : Entity work.FaultInjector
generic map(address => address)
port map(
clock => clock,
reset => reset,
tx => aux_tx,
restransmit => retransmission_i,
data_in => dataOutHamming,
data_out => data_out,
credit => credit_i
);
InputBuffers : for i in EAST to (LOCAL-1) generate
IB : entity work.Phoenix_buffer
generic map(
address => address,
bufLocation => i
)
port map(
clock => clock,
reset => reset,
data_in => dataDecoded(i),
rx => rx(i),
h => h(i), -- requisicao de chaveamento
c_buffCtrlFalha => c_BuffTabelaFalhas(i), -- tabela de falhas lida do pacote de controle que solicitou escrever/atualizar a tabela
c_ceTF_out => c_ceTF(i), -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_Find => c_erro_ArrayFind(i), -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_error_dir => c_erro_dir, -- indica qual destino/porta de saida o pacote sera encaminhado
c_tabelaFalhas => c_tabela_falhas, -- tabela de falhas atualizada/final
c_strLinkTst => c_strLinkTst(i), -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links.q
c_stpLinkTst => c_stpLinkTst(i), -- (stop link test) indica o fim do teste do link
c_strLinkTstOthers => c_strLinkTstOthers(i), -- indica se algum vizinho pediu para testar o link
c_strLinkTstNeighbor => testLink_i(i), -- indica se o vizinho pediu para testar o link
c_strLinkTstAll => c_strLinkTstAll, -- se algum buffer fez o pedido de teste de link
ack_h => ack_h(i), -- resposta da requisicao de chaveamento
data_av => data_av(i),
data => data(i),
sender => sender(i),
clock_rx => clock_rx(i),
data_ack => data_ack(i),
credit_o => credit_o_A(i),
retransmission_in => retransmission_in_buf(i),
retransmission_out => retransmission_out(i),
statusHamming => statusHamming(i)
);
end generate InputBuffers;
LocalBuffer : Entity work.Phoenix_buffer
generic map(
address => address,
bufLocation => LOCAL
)
port map(
clock => clock,
reset => reset,
data_in => dataDecoded(LOCAL),
rx => rx(LOCAL),
h => h(LOCAL),
c_ctrl=> c_ctrl, -- (exclusivo do buffer local) indica se foi lido ou criado de um pacote de controle pelo buffer
c_buffCtrlOut=> c_BuffCtrl, -- (exclusivo do buffer local) linha da tabela de roteamento lida do pacote de controle que sera escrita na tabela de roteamento
c_codigoCtrl=> c_CodControle, -- (exclusivo do buffer local) codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_chipETable => c_ceTR, -- (exclusivo do buffer local) chip enable da tabela de roteamento
c_buffCtrlFalha => c_BuffTabelaFalhas(LOCAL),
c_ceTF_out => c_ceTF(LOCAL),
c_error_Find => c_erro_ArrayFind(LOCAL),
c_error_dir => c_erro_dir,
c_tabelaFalhas => c_tabela_falhas,
c_strLinkTst => c_strLinkTst(LOCAL),
c_stpLinkTst => c_stpLinkTst(LOCAL),
c_strLinkTstOthers => c_strLinkTstOthers(LOCAL),
c_strLinkTstNeighbor => testLink_i(LOCAL),
c_strLinkTstAll => c_strLinkTstAll,
ack_h => ack_h(LOCAL),
data_av => data_av(LOCAL),
data => data(LOCAL),
sender => sender(LOCAL),
clock_rx => clock_rx(LOCAL),
data_ack => data_ack(LOCAL),
credit_o => credit_o_A(LOCAL),
retransmission_in => retransmission_in_buf(LOCAL),
retransmission_out => retransmission_out(LOCAL),
statusHamming => (others=>'0')
);
FaultDetection: Entity work.FaultDetection
port map(
clock => clock,
reset => reset,
c_strLinkTst => c_strLinkTst, -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_strLinkTstAll => c_strLinkTstAll, -- se algum buffer fez o pedido de teste de links
c_stpLinkTst => c_stpLinkTst, -- (stop link test) indica o fim do teste dos links
test_link_inA => testLink_i, -- sinal testLink_i dos roteadores vizinhos que indica teste de link (desta maneira o roteador sabe que precisa revolver o dado recebido durante o teste do link)
data_outA => data_out_A, -- data_out normal. Dado que sera encaminhado para as portas de saida, caso nao esteja em teste
data_inA => dataDecoded, -- dado(flit) recebido nas portas de entrada dos buffers
credit_inA => credit_i,
credit_outA => credit_o_A,
data_outB => data_out_B, -- dado que sera encaminhado para as portas de saida (pode ser encaminhado data_out normal ou dados para teste de link)
credit_inB => credit_i_A,
c_faultTableFDM => c_faultTableFDM, -- tabela de falhas ('0' indica sem falha, '1' indica falha)
credit_outB =>credit_o);
SwitchControl : Entity work.SwitchControl
generic map(address => address)
port map(
clock => clock,
reset => reset,
h => h, -- solicitacoes de chaveamento
ack_h => ack_h, -- resposta para as solitacoes de chaveamento
data => data, -- dado do buffer (contem o endereco destino)
c_Ctrl => c_ctrl, -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_buffTabelaFalhas_in=> c_BuffTabelaFalhas, -- tabela de falhas recebida no roteador por um pacote de controle do tipo WR_FAULT_TABLE
c_CodControle => c_CodControle, -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_BuffCtrl => c_BuffCtrl, -- linha da tabela de roteamento lida do pacote de controle que sera escrita na tabela de roteamento
c_ce => c_ceTR, -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
c_ceTF_in => c_ceTF, -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_ArrayFind => c_erro_ArrayFind, -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_error_dir => c_erro_dir, -- indica qual porta de saida o pacote sera encaminhado
c_tabelaFalhas => c_tabela_falhas, -- tabela de falhas atualizada/final
c_strLinkTst => c_strLinkTst, -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_faultTableFDM => c_faultTableFDM, -- tabela de falhas gerado pelo teste de links
sender => sender,
free => free, -- portas de saida que estao livres
mux_in => mux_in,
mux_out => mux_out,
row_FaultTablePorts_in => row_FaultTablePorts_out, -- linhas a serem escritas na tabela (do FFPM)
write_FaultTable => write_FaultTable); -- sinal para indicar escrita na tabela (do FPPM)
CrossBar : Entity work.Phoenix_crossbar
port map(
data_av => data_av,
data_in => data,
data_ack => data_ack,
sender => sender,
free => free,
tab_in => mux_in,
tab_out => mux_out,
tx => aux_tx,
data_out => data_out_A,
credit_i => credit_i_A,
retransmission_i => retransmission_i,
retransmission_in_buf => retransmission_in_buf);
FPPM: Entity work.FPPM
port map(
clock => clock,
reset_in => reset,
rx => rx((HAMM_NPORT-1) downto 0),
statusHamming => statusHamming,
write_FaultTable => write_FaultTable,
row_FaultTablePorts_out => row_FaultTablePorts_out);
HammingEncode : for i in EAST to LOCAL-1 generate
HE: entity work.HAM_ENC
port map(
data_in => data_out_B(i),
data_out => parity_dataOutHamming(i)
);
end generate HammingEncode;
HammingDecode : for i in EAST to LOCAL-1 generate
HD : entity work.HAM_DEC
port map(
data_in => dataInHamming(i),
parity_in => parity_dataInHamming(i),
data_out => dataDecoded(i),
parity_out => parityDecoded(i),
credit_out => statusDecoded(i)
);
end generate HammingDecode;
CLK_TX : for i in 0 to(NPORT-1) generate
clock_tx(i) <= clock;
end generate CLK_TX;
end RouterCC;
|
lgpl-3.0
|
88bef92ad03cb3100080f511e19bb4b0
| 0.624422 | 3.77241 | false | true | false | false |
dl3yc/sdr-fm
|
testing/euler-1.0/src/euler.vhd
| 1 | 2,309 |
-- EULER module for Betty SDR
-- implements a rectangle to polar conversion
-- file: euler.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
-- depends on: vcordic.vhd
--
-- change log:
-- - release implementation 1.0
-- - buggy phase in vcordic
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity euler is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of euler is
signal cordic_i : signed(A-1 downto 0) := (others => '0');
signal cordic_q : signed(A-1 downto 0) := (others => '0');
signal cordic_phi : signed(P-1 downto 0) := (others => '0');
signal cordic_amp : unsigned(A-1 downto 0) := (others => '0');
alias i_sign : std_logic is i(i'high);
alias q_sign : std_logic is q(q'high);
type quadrant_t is array(N+3 downto 0) of bit_vector(1 downto 0);
signal quadrant : quadrant_t;
alias actual_quadrant : bit_vector(1 downto 0) is quadrant(0);
alias last_quadrant : bit_vector(1 downto 0) is quadrant(N+3);
begin
cordic : entity work.vcordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => cordic_i,
q => cordic_q,
amp => cordic_amp,
phi => cordic_phi
);
process
begin
wait until rising_edge(clk);
quadrant(N+3 downto 1) <= quadrant(N+2 downto 0);
end process;
quadrant(0) <= to_bit(i_sign) & to_bit(q_sign);
process
begin
wait until rising_edge(clk);
case actual_quadrant is
when "00" => -- 1st quadrant
cordic_i <= i;
cordic_q <= q;
when "01" => -- 2nd quadrant
cordic_i <= i;
cordic_q <= -q;
when "11" => -- 3rd quadrant
cordic_i <= -i;
cordic_q <= -q;
when "10" => -- 4th quadrant
cordic_i <= -i;
cordic_q <= q;
end case;
end process;
process
begin
wait until rising_edge(clk);
case last_quadrant is
when "00" => phi <= cordic_phi; -- 1st quadrant
when "01" => phi <= 2**(P-1) - cordic_phi; -- 2nd quadrant
when "11" => phi <= 2**(P-1) + cordic_phi; -- 3rd quadrant
when "10" => phi <= -cordic_phi; -- 4th quadrant
end case;
amp <= cordic_amp;
end process;
end behavioral;
|
gpl-2.0
|
4a1505e05fc927204d9385497d416dcc
| 0.608489 | 2.672454 | false | false | false | false |
inforichland/freezing-spice
|
tests/compare_tb.vhd
| 1 | 5,073 |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
use work.id_pkg.all;
entity compare_tb is
end entity compare_tb;
architecture test of compare_tb is
signal branch_type : branch_type_t;
signal op1 : word;
signal op2 : word;
signal compare_result : std_logic;
begin -- architecture test
uut : entity work.compare_unit(behavioral)
port map (
branch_type => branch_type,
op1 => op1,
op2 => op2,
compare_result => compare_result);
process
begin
----------------------------------------------------------------
-- BEQ
----------------------------------------------------------------
println("BEQ");
branch_type <= BEQ;
op1 <= "00010001000100010001000100010001";
op2 <= "00010001000100010001000100010001";
wait for 1 ns;
assert compare_result = '1' report "Invalid BEQ" severity error;
op2 <= "00010001000100010001000100010000";
wait for 1 ns;
assert compare_result = '0' report "Invalid BEQ" severity error;
----------------------------------------------------------------
-- BNE
----------------------------------------------------------------
println("BNE");
branch_type <= BNE;
wait for 1 ns;
assert compare_result = '1' report "Invalid BNE" severity error;
op2 <= "00010001000100010001000100010001";
wait for 1 ns;
assert compare_result = '0' report "Invalid BNE" severity error;
----------------------------------------------------------------
-- BLT
----------------------------------------------------------------
println("BLT");
branch_type <= BLT;
op1 <= "00000000000000000000000000000001";
op2 <= "00000000000000000000000000000000";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLT" severity error;
op1 <= "00000000000000000000000000000010";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLT" severity error;
op2 <= "01111111111111111111111111111111";
wait for 1 ns;
assert compare_result = '1' report "Invalid BLT" severity error;
----------------------------------------------------------------
-- BGE
----------------------------------------------------------------
println("BGE");
branch_type <= BGE;
wait for 1 ns;
assert compare_result = '0' report "Invalid BGE" severity error;
op1 <= "00000000000000000000000000000010";
op2 <= "00000000000000000000000000000010";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGE" severity error;
op1 <= "11111111111111111111111111111111";
wait for 1 ns;
assert compare_result = '0' report "Invalid BGE" severity error;
op2 <= "11111111111111111111111111111110";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGE" severity error;
----------------------------------------------------------------
-- BLTU
----------------------------------------------------------------
println("BLTU");
branch_type <= BLTU;
wait for 1 ns;
assert compare_result = '0' report "Invalid BLTU" severity error;
op1 <= "11111111111111111111111111111100";
wait for 1 ns;
assert compare_result = '1' report "Invalid BLTU" severity error;
op2 <= "11111111111111111111111111111100";
wait for 1 ns;
assert compare_result = '0' report "Invalid BLTU" severity error;
----------------------------------------------------------------
-- BGEU
----------------------------------------------------------------
println("BGEU");
branch_type <= BGEU;
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "00000000000000000000000000000000";
op2 <= "00000000000000000000000000000000";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "00000000000000000000000000000001";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
op1 <= "11111111111111111111111111111111";
op2 <= "11111111111111111111111111111110";
wait for 1 ns;
assert compare_result = '1' report "Invalid BGEU" severity error;
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
wait;
end process;
end architecture test;
|
bsd-3-clause
|
c8f7b712af4b14af74f8729f1ca6b843
| 0.455155 | 5.919487 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodJSTK_v1_0/src/PmodJSTK_axi_quad_spi_0_0/sim/PmodJSTK_axi_quad_spi_0_0.vhd
| 1 | 15,025 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_6;
USE axi_quad_spi_v3_2_6.axi_quad_spi;
ENTITY PmodJSTK_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END PmodJSTK_axi_quad_spi_0_0;
ARCHITECTURE PmodJSTK_axi_quad_spi_0_0_arch OF PmodJSTK_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodJSTK_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "artix7",
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 48,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '0',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END PmodJSTK_axi_quad_spi_0_0_arch;
|
bsd-3-clause
|
c6f267b732aa9ed90dc0af495a10717e
| 0.642729 | 3.042114 | false | false | false | false |
makestuff/dvr-connectors
|
fifo/vhdl/tb_unit/fifo_tb.vhdl
| 1 | 4,338 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity fifo_tb is
generic(
WIDTH : natural := 8; -- number of bits in each FIFO word
DEPTH : natural := 2 -- 2**DEPTH gives number of words in FIFO
);
end entity;
architecture behavioural of fifo_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- Depth
signal curDepth : std_logic_vector(DEPTH downto 0);
-- Input pipe
signal inputData : std_logic_vector(WIDTH-1 downto 0);
signal inputValid : std_logic;
signal inputReady : std_logic;
-- Output pipe
signal outputData : std_logic_vector(WIDTH-1 downto 0);
signal outputValid : std_logic;
signal outputReady : std_logic;
begin
-- Instantiate the FIFO for testing
uut: entity work.fifo
generic map(
WIDTH => WIDTH,
DEPTH => DEPTH
)
port map(
clk_in => sysClk,
reset_in => '0',
depth_out => curDepth,
-- Input pipe
inputData_in => inputData,
inputValid_in => inputValid,
inputReady_out => inputReady,
-- Output pipe
outputData_out => outputData,
outputValid_out => outputValid,
outputReady_in => outputReady
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
inputData <= (others => 'X');
inputValid <= '0';
outputReady <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
inputData <= to_4(inLine.all(1)) & to_4(inLine.all(2));
inputValid <= to_1(inLine.all(4));
outputReady <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(inputData(7 downto 4)) & from_4(inputData(3 downto 0)));
write(outLine, ' ');
write(outLine, inputValid);
write(outLine, ' ');
write(outLine, inputReady);
write(outLine, ' ');
if ( inputReady = '1' and inputValid = '1' ) then
write(outLine, '*');
else
write(outLine, ' ');
end if;
write(outLine, ' ');
write(outLine, '|');
write(outLine, ' ');
if ( DEPTH = 2 ) then
write(outLine, from_4('0' & curDepth));
elsif ( DEPTH = 3 ) then
write(outLine, from_4(curDepth));
end if;
write(outLine, ' ');
write(outLine, '|');
write(outLine, ' ');
write(outLine, from_4(outputData(7 downto 4)) & from_4(outputData(3 downto 0)));
write(outLine, ' ');
write(outLine, outputValid);
write(outLine, ' ');
write(outLine, outputReady);
if ( outputReady = '1' and outputValid = '1' ) then
write(outLine, ' ');
write(outLine, '*');
end if;
writeline(outFile, outLine);
wait for 10 ns;
end loop;
inputData <= (others => 'X');
inputValid <= '0';
outputReady <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
562d46332b4e4bbd3fce2caf76c7402c
| 0.651683 | 3.360186 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/main_pack.vhd
| 1 | 278,524 |
library ieee;
use ieee.std_logic_1164.all;
package main_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 7976;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body main_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C0101";
ram_buffer(1) := X"279CFC90";
ram_buffer(2) := X"3C050100";
ram_buffer(3) := X"24A57CA0";
ram_buffer(4) := X"3C040102";
ram_buffer(5) := X"24848144";
ram_buffer(6) := X"3C1D0101";
ram_buffer(7) := X"27BD7FD8";
ram_buffer(8) := X"ACA00000";
ram_buffer(9) := X"00A4182A";
ram_buffer(10) := X"1460FFFD";
ram_buffer(11) := X"24A50004";
ram_buffer(12) := X"0C40007C";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"0840000E";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C401CBD";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C050100";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A0100";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"AC900000";
ram_buffer(89) := X"AC910004";
ram_buffer(90) := X"AC920008";
ram_buffer(91) := X"AC93000C";
ram_buffer(92) := X"AC940010";
ram_buffer(93) := X"AC950014";
ram_buffer(94) := X"AC960018";
ram_buffer(95) := X"AC97001C";
ram_buffer(96) := X"AC9E0020";
ram_buffer(97) := X"AC9C0024";
ram_buffer(98) := X"AC9D0028";
ram_buffer(99) := X"AC9F002C";
ram_buffer(100) := X"03E00008";
ram_buffer(101) := X"34020000";
ram_buffer(102) := X"8C900000";
ram_buffer(103) := X"8C910004";
ram_buffer(104) := X"8C920008";
ram_buffer(105) := X"8C93000C";
ram_buffer(106) := X"8C940010";
ram_buffer(107) := X"8C950014";
ram_buffer(108) := X"8C960018";
ram_buffer(109) := X"8C97001C";
ram_buffer(110) := X"8C9E0020";
ram_buffer(111) := X"8C9C0024";
ram_buffer(112) := X"8C9D0028";
ram_buffer(113) := X"8C9F002C";
ram_buffer(114) := X"03E00008";
ram_buffer(115) := X"34A20000";
ram_buffer(116) := X"00850019";
ram_buffer(117) := X"00001012";
ram_buffer(118) := X"00002010";
ram_buffer(119) := X"03E00008";
ram_buffer(120) := X"ACC40000";
ram_buffer(121) := X"0000000C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"00000000";
ram_buffer(124) := X"27BDFFD0";
ram_buffer(125) := X"00002025";
ram_buffer(126) := X"AFBF002C";
ram_buffer(127) := X"AFB30028";
ram_buffer(128) := X"AFB20024";
ram_buffer(129) := X"AFB10020";
ram_buffer(130) := X"0C400046";
ram_buffer(131) := X"AFB0001C";
ram_buffer(132) := X"3C050102";
ram_buffer(133) := X"3C0644A0";
ram_buffer(134) := X"24A28030";
ram_buffer(135) := X"ACA68030";
ram_buffer(136) := X"3C0544A2";
ram_buffer(137) := X"AF858074";
ram_buffer(138) := X"3C0444A1";
ram_buffer(139) := X"3405C350";
ram_buffer(140) := X"AF84806C";
ram_buffer(141) := X"3C0344A3";
ram_buffer(142) := X"AC850004";
ram_buffer(143) := X"24040004";
ram_buffer(144) := X"AF838084";
ram_buffer(145) := X"AC640000";
ram_buffer(146) := X"3C030100";
ram_buffer(147) := X"24630724";
ram_buffer(148) := X"AC43000C";
ram_buffer(149) := X"3C030100";
ram_buffer(150) := X"246306F0";
ram_buffer(151) := X"AC430004";
ram_buffer(152) := X"3C030100";
ram_buffer(153) := X"2463076C";
ram_buffer(154) := X"3C040102";
ram_buffer(155) := X"24060040";
ram_buffer(156) := X"00002825";
ram_buffer(157) := X"24848074";
ram_buffer(158) := X"AC430014";
ram_buffer(159) := X"AC40001C";
ram_buffer(160) := X"AC400024";
ram_buffer(161) := X"AC40002C";
ram_buffer(162) := X"AC400034";
ram_buffer(163) := X"AC40003C";
ram_buffer(164) := X"AC400010";
ram_buffer(165) := X"AC400008";
ram_buffer(166) := X"AC400018";
ram_buffer(167) := X"0C401EB2";
ram_buffer(168) := X"AF808088";
ram_buffer(169) := X"00003025";
ram_buffer(170) := X"24050004";
ram_buffer(171) := X"0C4004C2";
ram_buffer(172) := X"24040008";
ram_buffer(173) := X"1040001E";
ram_buffer(174) := X"AF82807C";
ram_buffer(175) := X"00002825";
ram_buffer(176) := X"0C4004FA";
ram_buffer(177) := X"24040008";
ram_buffer(178) := X"10400014";
ram_buffer(179) := X"AF828078";
ram_buffer(180) := X"24100003";
ram_buffer(181) := X"3C050100";
ram_buffer(182) := X"3C040100";
ram_buffer(183) := X"AFA00014";
ram_buffer(184) := X"AFB00010";
ram_buffer(185) := X"00003825";
ram_buffer(186) := X"2406012C";
ram_buffer(187) := X"24A57C00";
ram_buffer(188) := X"0C400C2B";
ram_buffer(189) := X"24840920";
ram_buffer(190) := X"00409825";
ram_buffer(191) := X"24020001";
ram_buffer(192) := X"12620010";
ram_buffer(193) := X"240300ED";
ram_buffer(194) := X"8F828074";
ram_buffer(195) := X"00000000";
ram_buffer(196) := X"AC430008";
ram_buffer(197) := X"1000FFFF";
ram_buffer(198) := X"00000000";
ram_buffer(199) := X"8F828074";
ram_buffer(200) := X"240300EB";
ram_buffer(201) := X"AC430008";
ram_buffer(202) := X"1000FFFF";
ram_buffer(203) := X"00000000";
ram_buffer(204) := X"8F828074";
ram_buffer(205) := X"240300E9";
ram_buffer(206) := X"AC430008";
ram_buffer(207) := X"1000FFFF";
ram_buffer(208) := X"00000000";
ram_buffer(209) := X"27828080";
ram_buffer(210) := X"24110005";
ram_buffer(211) := X"3C050100";
ram_buffer(212) := X"3C040100";
ram_buffer(213) := X"AFA20014";
ram_buffer(214) := X"AFB10010";
ram_buffer(215) := X"00003825";
ram_buffer(216) := X"2406012C";
ram_buffer(217) := X"24A57C08";
ram_buffer(218) := X"0C400C2B";
ram_buffer(219) := X"248407C8";
ram_buffer(220) := X"10530006";
ram_buffer(221) := X"00409025";
ram_buffer(222) := X"8F828074";
ram_buffer(223) := X"240300EF";
ram_buffer(224) := X"AC430008";
ram_buffer(225) := X"1000FFFF";
ram_buffer(226) := X"00000000";
ram_buffer(227) := X"3C050100";
ram_buffer(228) := X"3C040100";
ram_buffer(229) := X"AFB10010";
ram_buffer(230) := X"AFA00014";
ram_buffer(231) := X"00003825";
ram_buffer(232) := X"2406012C";
ram_buffer(233) := X"24A57C10";
ram_buffer(234) := X"0C400C2B";
ram_buffer(235) := X"24840804";
ram_buffer(236) := X"10520006";
ram_buffer(237) := X"00408825";
ram_buffer(238) := X"8F828074";
ram_buffer(239) := X"240300F1";
ram_buffer(240) := X"AC430008";
ram_buffer(241) := X"1000FFFF";
ram_buffer(242) := X"00000000";
ram_buffer(243) := X"27828070";
ram_buffer(244) := X"3C050100";
ram_buffer(245) := X"3C040100";
ram_buffer(246) := X"AFA20014";
ram_buffer(247) := X"AFB00010";
ram_buffer(248) := X"00003825";
ram_buffer(249) := X"2406012C";
ram_buffer(250) := X"24A57C18";
ram_buffer(251) := X"0C400C2B";
ram_buffer(252) := X"24840840";
ram_buffer(253) := X"10510006";
ram_buffer(254) := X"240300F3";
ram_buffer(255) := X"8F828074";
ram_buffer(256) := X"00000000";
ram_buffer(257) := X"AC430008";
ram_buffer(258) := X"1000FFFF";
ram_buffer(259) := X"00000000";
ram_buffer(260) := X"8F83806C";
ram_buffer(261) := X"00000000";
ram_buffer(262) := X"AC700000";
ram_buffer(263) := X"8F838074";
ram_buffer(264) := X"24045000";
ram_buffer(265) := X"AC620000";
ram_buffer(266) := X"8F838084";
ram_buffer(267) := X"00000000";
ram_buffer(268) := X"AC640000";
ram_buffer(269) := X"8F838074";
ram_buffer(270) := X"00000000";
ram_buffer(271) := X"0C4010C1";
ram_buffer(272) := X"AC620008";
ram_buffer(273) := X"8F828074";
ram_buffer(274) := X"24030102";
ram_buffer(275) := X"AC430008";
ram_buffer(276) := X"1000FFFF";
ram_buffer(277) := X"00000000";
ram_buffer(278) := X"2082FF78";
ram_buffer(279) := X"AC450078";
ram_buffer(280) := X"03E00008";
ram_buffer(281) := X"AC46001C";
ram_buffer(282) := X"3C1A0100";
ram_buffer(283) := X"375A7CF8";
ram_buffer(284) := X"8F5B0000";
ram_buffer(285) := X"AF400000";
ram_buffer(286) := X"23BDFF78";
ram_buffer(287) := X"AFA10010";
ram_buffer(288) := X"AFA20014";
ram_buffer(289) := X"AFA30018";
ram_buffer(290) := X"AFA4001C";
ram_buffer(291) := X"AFA50020";
ram_buffer(292) := X"AFA60024";
ram_buffer(293) := X"AFA70028";
ram_buffer(294) := X"AFA8002C";
ram_buffer(295) := X"AFA90030";
ram_buffer(296) := X"AFAA0034";
ram_buffer(297) := X"AFAB0038";
ram_buffer(298) := X"AFAC003C";
ram_buffer(299) := X"AFAD0040";
ram_buffer(300) := X"AFAE0044";
ram_buffer(301) := X"AFAF0048";
ram_buffer(302) := X"AFB0004C";
ram_buffer(303) := X"AFB10050";
ram_buffer(304) := X"AFB20054";
ram_buffer(305) := X"AFB30058";
ram_buffer(306) := X"AFB4005C";
ram_buffer(307) := X"AFB50060";
ram_buffer(308) := X"AFB60064";
ram_buffer(309) := X"AFB70068";
ram_buffer(310) := X"AFB8006C";
ram_buffer(311) := X"AFB90070";
ram_buffer(312) := X"AFBF0074";
ram_buffer(313) := X"401A7000";
ram_buffer(314) := X"17600003";
ram_buffer(315) := X"235AFFFC";
ram_buffer(316) := X"0840013F";
ram_buffer(317) := X"00000000";
ram_buffer(318) := X"235A0004";
ram_buffer(319) := X"AFBA0078";
ram_buffer(320) := X"0000D810";
ram_buffer(321) := X"AFBB007C";
ram_buffer(322) := X"0000D812";
ram_buffer(323) := X"AFBB0080";
ram_buffer(324) := X"3C1A0100";
ram_buffer(325) := X"375A7CA0";
ram_buffer(326) := X"8F5A0000";
ram_buffer(327) := X"AF5D0000";
ram_buffer(328) := X"3C1A0101";
ram_buffer(329) := X"375A7DF0";
ram_buffer(330) := X"8F5D0000";
ram_buffer(331) := X"0C4003EC";
ram_buffer(332) := X"00000000";
ram_buffer(333) := X"3C1A0101";
ram_buffer(334) := X"375A7DF0";
ram_buffer(335) := X"AF5D0000";
ram_buffer(336) := X"3C1A0100";
ram_buffer(337) := X"375A7CA0";
ram_buffer(338) := X"8F5A0000";
ram_buffer(339) := X"8F5D0000";
ram_buffer(340) := X"8FA10010";
ram_buffer(341) := X"8FA20014";
ram_buffer(342) := X"8FA30018";
ram_buffer(343) := X"8FA4001C";
ram_buffer(344) := X"8FA50020";
ram_buffer(345) := X"8FA60024";
ram_buffer(346) := X"8FA70028";
ram_buffer(347) := X"8FA8002C";
ram_buffer(348) := X"8FA90030";
ram_buffer(349) := X"8FAA0034";
ram_buffer(350) := X"8FAB0038";
ram_buffer(351) := X"8FAC003C";
ram_buffer(352) := X"8FAD0040";
ram_buffer(353) := X"8FAE0044";
ram_buffer(354) := X"8FAF0048";
ram_buffer(355) := X"8FB0004C";
ram_buffer(356) := X"8FB10050";
ram_buffer(357) := X"8FB20054";
ram_buffer(358) := X"8FB30058";
ram_buffer(359) := X"8FB4005C";
ram_buffer(360) := X"8FB50060";
ram_buffer(361) := X"8FB60064";
ram_buffer(362) := X"8FB70068";
ram_buffer(363) := X"8FB8006C";
ram_buffer(364) := X"8FB90070";
ram_buffer(365) := X"8FBF0074";
ram_buffer(366) := X"8FBA0078";
ram_buffer(367) := X"8FBB007C";
ram_buffer(368) := X"03600011";
ram_buffer(369) := X"8FBB0080";
ram_buffer(370) := X"03600013";
ram_buffer(371) := X"23BD0088";
ram_buffer(372) := X"341B0001";
ram_buffer(373) := X"03400008";
ram_buffer(374) := X"409B6000";
ram_buffer(375) := X"00000000";
ram_buffer(376) := X"3C080100";
ram_buffer(377) := X"2508060C";
ram_buffer(378) := X"8D090000";
ram_buffer(379) := X"AC09003C";
ram_buffer(380) := X"8D090004";
ram_buffer(381) := X"AC090040";
ram_buffer(382) := X"8D090008";
ram_buffer(383) := X"AC090044";
ram_buffer(384) := X"8D09000C";
ram_buffer(385) := X"03E00008";
ram_buffer(386) := X"AC090048";
ram_buffer(387) := X"3C1A0100";
ram_buffer(388) := X"375A0468";
ram_buffer(389) := X"03400008";
ram_buffer(390) := X"00000000";
ram_buffer(391) := X"3C1A0101";
ram_buffer(392) := X"375A7DF0";
ram_buffer(393) := X"AF5D0000";
ram_buffer(394) := X"3C1A0100";
ram_buffer(395) := X"375A7CA0";
ram_buffer(396) := X"8F5A0000";
ram_buffer(397) := X"8F5D0000";
ram_buffer(398) := X"8FA10010";
ram_buffer(399) := X"8FA20014";
ram_buffer(400) := X"8FA30018";
ram_buffer(401) := X"8FA4001C";
ram_buffer(402) := X"8FA50020";
ram_buffer(403) := X"8FA60024";
ram_buffer(404) := X"8FA70028";
ram_buffer(405) := X"8FA8002C";
ram_buffer(406) := X"8FA90030";
ram_buffer(407) := X"8FAA0034";
ram_buffer(408) := X"8FAB0038";
ram_buffer(409) := X"8FAC003C";
ram_buffer(410) := X"8FAD0040";
ram_buffer(411) := X"8FAE0044";
ram_buffer(412) := X"8FAF0048";
ram_buffer(413) := X"8FB0004C";
ram_buffer(414) := X"8FB10050";
ram_buffer(415) := X"8FB20054";
ram_buffer(416) := X"8FB30058";
ram_buffer(417) := X"8FB4005C";
ram_buffer(418) := X"8FB50060";
ram_buffer(419) := X"8FB60064";
ram_buffer(420) := X"8FB70068";
ram_buffer(421) := X"8FB8006C";
ram_buffer(422) := X"8FB90070";
ram_buffer(423) := X"8FBF0074";
ram_buffer(424) := X"8FBA0078";
ram_buffer(425) := X"8FBB007C";
ram_buffer(426) := X"03600011";
ram_buffer(427) := X"8FBB0080";
ram_buffer(428) := X"03600013";
ram_buffer(429) := X"23BD0088";
ram_buffer(430) := X"341B0001";
ram_buffer(431) := X"03400008";
ram_buffer(432) := X"409B6000";
ram_buffer(433) := X"40806000";
ram_buffer(434) := X"20090001";
ram_buffer(435) := X"3C080100";
ram_buffer(436) := X"35087CF8";
ram_buffer(437) := X"AD090000";
ram_buffer(438) := X"3C080100";
ram_buffer(439) := X"35087CDC";
ram_buffer(440) := X"AD090000";
ram_buffer(441) := X"0000000C";
ram_buffer(442) := X"03E00008";
ram_buffer(443) := X"00000000";
ram_buffer(444) := X"27BDFFE8";
ram_buffer(445) := X"AFBF0014";
ram_buffer(446) := X"0C401124";
ram_buffer(447) := X"00000000";
ram_buffer(448) := X"10400002";
ram_buffer(449) := X"24020001";
ram_buffer(450) := X"AF82804C";
ram_buffer(451) := X"8FBF0014";
ram_buffer(452) := X"8F82806C";
ram_buffer(453) := X"24030007";
ram_buffer(454) := X"AC430000";
ram_buffer(455) := X"03E00008";
ram_buffer(456) := X"27BD0018";
ram_buffer(457) := X"27BDFFE0";
ram_buffer(458) := X"AFBF001C";
ram_buffer(459) := X"AFA00010";
ram_buffer(460) := X"8F828074";
ram_buffer(461) := X"8F848080";
ram_buffer(462) := X"24030003";
ram_buffer(463) := X"AC430000";
ram_buffer(464) := X"0C401C2B";
ram_buffer(465) := X"27A50010";
ram_buffer(466) := X"8FA20010";
ram_buffer(467) := X"00000000";
ram_buffer(468) := X"10400002";
ram_buffer(469) := X"24020001";
ram_buffer(470) := X"AF82804C";
ram_buffer(471) := X"8FBF001C";
ram_buffer(472) := X"00000000";
ram_buffer(473) := X"03E00008";
ram_buffer(474) := X"27BD0020";
ram_buffer(475) := X"27BDFFE0";
ram_buffer(476) := X"8F828084";
ram_buffer(477) := X"AFA00010";
ram_buffer(478) := X"8C430004";
ram_buffer(479) := X"AFBF001C";
ram_buffer(480) := X"AF838088";
ram_buffer(481) := X"24034000";
ram_buffer(482) := X"AC430004";
ram_buffer(483) := X"8F828084";
ram_buffer(484) := X"8F848070";
ram_buffer(485) := X"24031000";
ram_buffer(486) := X"AC430004";
ram_buffer(487) := X"0C401C2B";
ram_buffer(488) := X"27A50010";
ram_buffer(489) := X"8FA20010";
ram_buffer(490) := X"00000000";
ram_buffer(491) := X"10400002";
ram_buffer(492) := X"24020001";
ram_buffer(493) := X"AF82804C";
ram_buffer(494) := X"8FBF001C";
ram_buffer(495) := X"00000000";
ram_buffer(496) := X"03E00008";
ram_buffer(497) := X"27BD0020";
ram_buffer(498) := X"27BDFFE0";
ram_buffer(499) := X"AFBF001C";
ram_buffer(500) := X"8F828074";
ram_buffer(501) := X"8F84807C";
ram_buffer(502) := X"8C420004";
ram_buffer(503) := X"27A50010";
ram_buffer(504) := X"00003825";
ram_buffer(505) := X"2406FFFF";
ram_buffer(506) := X"0C40053C";
ram_buffer(507) := X"AFA20010";
ram_buffer(508) := X"2405FFFF";
ram_buffer(509) := X"0C4019D7";
ram_buffer(510) := X"24040001";
ram_buffer(511) := X"1000FFF4";
ram_buffer(512) := X"00000000";
ram_buffer(513) := X"27BDFFE0";
ram_buffer(514) := X"AFBF001C";
ram_buffer(515) := X"0C4010F5";
ram_buffer(516) := X"00000000";
ram_buffer(517) := X"AFA20010";
ram_buffer(518) := X"27A40010";
ram_buffer(519) := X"0C401264";
ram_buffer(520) := X"24050002";
ram_buffer(521) := X"8F848078";
ram_buffer(522) := X"00003825";
ram_buffer(523) := X"00003025";
ram_buffer(524) := X"0C40053C";
ram_buffer(525) := X"00002825";
ram_buffer(526) := X"1000FFF8";
ram_buffer(527) := X"27A40010";
ram_buffer(528) := X"27BDFFE0";
ram_buffer(529) := X"AFB00010";
ram_buffer(530) := X"3C100102";
ram_buffer(531) := X"AFBF001C";
ram_buffer(532) := X"AFB20018";
ram_buffer(533) := X"AFB10014";
ram_buffer(534) := X"00001025";
ram_buffer(535) := X"261080B4";
ram_buffer(536) := X"24050040";
ram_buffer(537) := X"304400FF";
ram_buffer(538) := X"02021821";
ram_buffer(539) := X"24420001";
ram_buffer(540) := X"A0640000";
ram_buffer(541) := X"1445FFFC";
ram_buffer(542) := X"304400FF";
ram_buffer(543) := X"24060040";
ram_buffer(544) := X"02002825";
ram_buffer(545) := X"24040004";
ram_buffer(546) := X"0C400424";
ram_buffer(547) := X"3C110101";
ram_buffer(548) := X"26317FF0";
ram_buffer(549) := X"10000005";
ram_buffer(550) := X"24120040";
ram_buffer(551) := X"1460001B";
ram_buffer(552) := X"24030092";
ram_buffer(553) := X"10400014";
ram_buffer(554) := X"24030093";
ram_buffer(555) := X"8F828084";
ram_buffer(556) := X"24040001";
ram_buffer(557) := X"AC500018";
ram_buffer(558) := X"2405FFFF";
ram_buffer(559) := X"AC510020";
ram_buffer(560) := X"AC520028";
ram_buffer(561) := X"0C4019D7";
ram_buffer(562) := X"00000000";
ram_buffer(563) := X"8F828088";
ram_buffer(564) := X"00000000";
ram_buffer(565) := X"30440040";
ram_buffer(566) := X"30430020";
ram_buffer(567) := X"1080FFEF";
ram_buffer(568) := X"30420002";
ram_buffer(569) := X"8F828074";
ram_buffer(570) := X"24030091";
ram_buffer(571) := X"AC430008";
ram_buffer(572) := X"1000FFFF";
ram_buffer(573) := X"00000000";
ram_buffer(574) := X"8F828074";
ram_buffer(575) := X"00000000";
ram_buffer(576) := X"AC430008";
ram_buffer(577) := X"1000FFFF";
ram_buffer(578) := X"00000000";
ram_buffer(579) := X"8F828074";
ram_buffer(580) := X"00000000";
ram_buffer(581) := X"AC430008";
ram_buffer(582) := X"1000FFFF";
ram_buffer(583) := X"00000000";
ram_buffer(584) := X"27BDFFC0";
ram_buffer(585) := X"AFB50030";
ram_buffer(586) := X"AFB4002C";
ram_buffer(587) := X"3C15FFFF";
ram_buffer(588) := X"3C140102";
ram_buffer(589) := X"AFB70038";
ram_buffer(590) := X"AFB60034";
ram_buffer(591) := X"AFB30028";
ram_buffer(592) := X"AFB20024";
ram_buffer(593) := X"AFB10020";
ram_buffer(594) := X"AFB0001C";
ram_buffer(595) := X"AFBF003C";
ram_buffer(596) := X"00008825";
ram_buffer(597) := X"0000B825";
ram_buffer(598) := X"26908074";
ram_buffer(599) := X"24130001";
ram_buffer(600) := X"241200F9";
ram_buffer(601) := X"26B57FFF";
ram_buffer(602) := X"2416BFFF";
ram_buffer(603) := X"8F84807C";
ram_buffer(604) := X"00003825";
ram_buffer(605) := X"00003025";
ram_buffer(606) := X"0C400846";
ram_buffer(607) := X"27A50010";
ram_buffer(608) := X"14530044";
ram_buffer(609) := X"00000000";
ram_buffer(610) := X"8FB70010";
ram_buffer(611) := X"00000000";
ram_buffer(612) := X"00171027";
ram_buffer(613) := X"30430001";
ram_buffer(614) := X"10600003";
ram_buffer(615) := X"30430002";
ram_buffer(616) := X"AE808074";
ram_buffer(617) := X"30430002";
ram_buffer(618) := X"10600003";
ram_buffer(619) := X"30430004";
ram_buffer(620) := X"AE000004";
ram_buffer(621) := X"30430004";
ram_buffer(622) := X"10600003";
ram_buffer(623) := X"30430008";
ram_buffer(624) := X"AE000008";
ram_buffer(625) := X"30430008";
ram_buffer(626) := X"10600003";
ram_buffer(627) := X"30430010";
ram_buffer(628) := X"AE00000C";
ram_buffer(629) := X"30430010";
ram_buffer(630) := X"10600003";
ram_buffer(631) := X"30430020";
ram_buffer(632) := X"AE000010";
ram_buffer(633) := X"30430020";
ram_buffer(634) := X"10600003";
ram_buffer(635) := X"30430040";
ram_buffer(636) := X"AE000014";
ram_buffer(637) := X"30430040";
ram_buffer(638) := X"10600003";
ram_buffer(639) := X"30430080";
ram_buffer(640) := X"AE000018";
ram_buffer(641) := X"30430080";
ram_buffer(642) := X"10600003";
ram_buffer(643) := X"30430100";
ram_buffer(644) := X"AE00001C";
ram_buffer(645) := X"30430100";
ram_buffer(646) := X"10600003";
ram_buffer(647) := X"30430200";
ram_buffer(648) := X"AE000020";
ram_buffer(649) := X"30430200";
ram_buffer(650) := X"10600003";
ram_buffer(651) := X"30430400";
ram_buffer(652) := X"AE000024";
ram_buffer(653) := X"30430400";
ram_buffer(654) := X"10600003";
ram_buffer(655) := X"30430800";
ram_buffer(656) := X"AE000028";
ram_buffer(657) := X"30430800";
ram_buffer(658) := X"10600003";
ram_buffer(659) := X"30431000";
ram_buffer(660) := X"AE00002C";
ram_buffer(661) := X"30431000";
ram_buffer(662) := X"10600003";
ram_buffer(663) := X"30432000";
ram_buffer(664) := X"AE000030";
ram_buffer(665) := X"30432000";
ram_buffer(666) := X"10600003";
ram_buffer(667) := X"30434000";
ram_buffer(668) := X"AE000034";
ram_buffer(669) := X"30434000";
ram_buffer(670) := X"10600002";
ram_buffer(671) := X"00000000";
ram_buffer(672) := X"AE000038";
ram_buffer(673) := X"30428000";
ram_buffer(674) := X"10400002";
ram_buffer(675) := X"00000000";
ram_buffer(676) := X"AE00003C";
ram_buffer(677) := X"8F848078";
ram_buffer(678) := X"00003825";
ram_buffer(679) := X"00003025";
ram_buffer(680) := X"0C400846";
ram_buffer(681) := X"00002825";
ram_buffer(682) := X"1453FFB0";
ram_buffer(683) := X"32E20001";
ram_buffer(684) := X"104000B3";
ram_buffer(685) := X"2402FFFE";
ram_buffer(686) := X"8E828074";
ram_buffer(687) := X"00000000";
ram_buffer(688) := X"105200F0";
ram_buffer(689) := X"32220001";
ram_buffer(690) := X"8E828074";
ram_buffer(691) := X"00000000";
ram_buffer(692) := X"24420001";
ram_buffer(693) := X"AE828074";
ram_buffer(694) := X"32E20002";
ram_buffer(695) := X"104000AC";
ram_buffer(696) := X"2402FFFD";
ram_buffer(697) := X"8E020004";
ram_buffer(698) := X"00000000";
ram_buffer(699) := X"105200E0";
ram_buffer(700) := X"32220002";
ram_buffer(701) := X"8E020004";
ram_buffer(702) := X"00000000";
ram_buffer(703) := X"24420001";
ram_buffer(704) := X"AE020004";
ram_buffer(705) := X"32E20004";
ram_buffer(706) := X"104000A5";
ram_buffer(707) := X"2402FFFB";
ram_buffer(708) := X"8E020008";
ram_buffer(709) := X"00000000";
ram_buffer(710) := X"105200E4";
ram_buffer(711) := X"32220004";
ram_buffer(712) := X"8E020008";
ram_buffer(713) := X"00000000";
ram_buffer(714) := X"24420001";
ram_buffer(715) := X"AE020008";
ram_buffer(716) := X"32E20008";
ram_buffer(717) := X"1040009E";
ram_buffer(718) := X"2402FFF7";
ram_buffer(719) := X"8E02000C";
ram_buffer(720) := X"00000000";
ram_buffer(721) := X"105200D4";
ram_buffer(722) := X"32220008";
ram_buffer(723) := X"8E02000C";
ram_buffer(724) := X"00000000";
ram_buffer(725) := X"24420001";
ram_buffer(726) := X"AE02000C";
ram_buffer(727) := X"32E20010";
ram_buffer(728) := X"10400097";
ram_buffer(729) := X"2402FFEF";
ram_buffer(730) := X"8E020010";
ram_buffer(731) := X"00000000";
ram_buffer(732) := X"105200D8";
ram_buffer(733) := X"32220010";
ram_buffer(734) := X"8E020010";
ram_buffer(735) := X"00000000";
ram_buffer(736) := X"24420001";
ram_buffer(737) := X"AE020010";
ram_buffer(738) := X"32E20020";
ram_buffer(739) := X"10400090";
ram_buffer(740) := X"2402FFDF";
ram_buffer(741) := X"8E020014";
ram_buffer(742) := X"00000000";
ram_buffer(743) := X"105200C8";
ram_buffer(744) := X"32220020";
ram_buffer(745) := X"8E020014";
ram_buffer(746) := X"00000000";
ram_buffer(747) := X"24420001";
ram_buffer(748) := X"AE020014";
ram_buffer(749) := X"32E20040";
ram_buffer(750) := X"10400089";
ram_buffer(751) := X"2402FFBF";
ram_buffer(752) := X"8E020018";
ram_buffer(753) := X"00000000";
ram_buffer(754) := X"105200CC";
ram_buffer(755) := X"32220040";
ram_buffer(756) := X"8E020018";
ram_buffer(757) := X"00000000";
ram_buffer(758) := X"24420001";
ram_buffer(759) := X"AE020018";
ram_buffer(760) := X"32E20080";
ram_buffer(761) := X"10400082";
ram_buffer(762) := X"2402FF7F";
ram_buffer(763) := X"8E02001C";
ram_buffer(764) := X"00000000";
ram_buffer(765) := X"105200BC";
ram_buffer(766) := X"32220080";
ram_buffer(767) := X"8E02001C";
ram_buffer(768) := X"00000000";
ram_buffer(769) := X"24420001";
ram_buffer(770) := X"AE02001C";
ram_buffer(771) := X"32E20100";
ram_buffer(772) := X"1040007B";
ram_buffer(773) := X"2402FEFF";
ram_buffer(774) := X"8E020020";
ram_buffer(775) := X"00000000";
ram_buffer(776) := X"105200C0";
ram_buffer(777) := X"32220100";
ram_buffer(778) := X"8E020020";
ram_buffer(779) := X"00000000";
ram_buffer(780) := X"24420001";
ram_buffer(781) := X"AE020020";
ram_buffer(782) := X"32E20200";
ram_buffer(783) := X"10400074";
ram_buffer(784) := X"2402FDFF";
ram_buffer(785) := X"8E020024";
ram_buffer(786) := X"00000000";
ram_buffer(787) := X"105200B0";
ram_buffer(788) := X"32220200";
ram_buffer(789) := X"8E020024";
ram_buffer(790) := X"00000000";
ram_buffer(791) := X"24420001";
ram_buffer(792) := X"AE020024";
ram_buffer(793) := X"32E20400";
ram_buffer(794) := X"1040006D";
ram_buffer(795) := X"2402FBFF";
ram_buffer(796) := X"8E020028";
ram_buffer(797) := X"00000000";
ram_buffer(798) := X"105200B4";
ram_buffer(799) := X"32220400";
ram_buffer(800) := X"8E020028";
ram_buffer(801) := X"00000000";
ram_buffer(802) := X"24420001";
ram_buffer(803) := X"AE020028";
ram_buffer(804) := X"32E20800";
ram_buffer(805) := X"10400066";
ram_buffer(806) := X"2402F7FF";
ram_buffer(807) := X"8E02002C";
ram_buffer(808) := X"00000000";
ram_buffer(809) := X"105200A4";
ram_buffer(810) := X"32220800";
ram_buffer(811) := X"8E02002C";
ram_buffer(812) := X"00000000";
ram_buffer(813) := X"24420001";
ram_buffer(814) := X"AE02002C";
ram_buffer(815) := X"32E21000";
ram_buffer(816) := X"1040005F";
ram_buffer(817) := X"2402EFFF";
ram_buffer(818) := X"8E020030";
ram_buffer(819) := X"00000000";
ram_buffer(820) := X"105200A8";
ram_buffer(821) := X"32221000";
ram_buffer(822) := X"8E020030";
ram_buffer(823) := X"00000000";
ram_buffer(824) := X"24420001";
ram_buffer(825) := X"AE020030";
ram_buffer(826) := X"32E22000";
ram_buffer(827) := X"10400058";
ram_buffer(828) := X"2402DFFF";
ram_buffer(829) := X"8E020034";
ram_buffer(830) := X"00000000";
ram_buffer(831) := X"10520098";
ram_buffer(832) := X"32222000";
ram_buffer(833) := X"8E020034";
ram_buffer(834) := X"00000000";
ram_buffer(835) := X"24420001";
ram_buffer(836) := X"AE020034";
ram_buffer(837) := X"32E24000";
ram_buffer(838) := X"10400051";
ram_buffer(839) := X"32E28000";
ram_buffer(840) := X"8E020038";
ram_buffer(841) := X"00000000";
ram_buffer(842) := X"1052009C";
ram_buffer(843) := X"32224000";
ram_buffer(844) := X"8E020038";
ram_buffer(845) := X"00000000";
ram_buffer(846) := X"24420001";
ram_buffer(847) := X"AE020038";
ram_buffer(848) := X"32E28000";
ram_buffer(849) := X"10400048";
ram_buffer(850) := X"00000000";
ram_buffer(851) := X"8E02003C";
ram_buffer(852) := X"00000000";
ram_buffer(853) := X"1052008C";
ram_buffer(854) := X"32228000";
ram_buffer(855) := X"8E02003C";
ram_buffer(856) := X"00000000";
ram_buffer(857) := X"24420001";
ram_buffer(858) := X"AE02003C";
ram_buffer(859) := X"8F828074";
ram_buffer(860) := X"00000000";
ram_buffer(861) := X"AC510008";
ram_buffer(862) := X"1000FEFC";
ram_buffer(863) := X"00000000";
ram_buffer(864) := X"02228824";
ram_buffer(865) := X"32E20002";
ram_buffer(866) := X"1440FF56";
ram_buffer(867) := X"2402FFFD";
ram_buffer(868) := X"02228824";
ram_buffer(869) := X"32E20004";
ram_buffer(870) := X"1440FF5D";
ram_buffer(871) := X"2402FFFB";
ram_buffer(872) := X"02228824";
ram_buffer(873) := X"32E20008";
ram_buffer(874) := X"1440FF64";
ram_buffer(875) := X"2402FFF7";
ram_buffer(876) := X"02228824";
ram_buffer(877) := X"32E20010";
ram_buffer(878) := X"1440FF6B";
ram_buffer(879) := X"2402FFEF";
ram_buffer(880) := X"02228824";
ram_buffer(881) := X"32E20020";
ram_buffer(882) := X"1440FF72";
ram_buffer(883) := X"2402FFDF";
ram_buffer(884) := X"02228824";
ram_buffer(885) := X"32E20040";
ram_buffer(886) := X"1440FF79";
ram_buffer(887) := X"2402FFBF";
ram_buffer(888) := X"02228824";
ram_buffer(889) := X"32E20080";
ram_buffer(890) := X"1440FF80";
ram_buffer(891) := X"2402FF7F";
ram_buffer(892) := X"02228824";
ram_buffer(893) := X"32E20100";
ram_buffer(894) := X"1440FF87";
ram_buffer(895) := X"2402FEFF";
ram_buffer(896) := X"02228824";
ram_buffer(897) := X"32E20200";
ram_buffer(898) := X"1440FF8E";
ram_buffer(899) := X"2402FDFF";
ram_buffer(900) := X"02228824";
ram_buffer(901) := X"32E20400";
ram_buffer(902) := X"1440FF95";
ram_buffer(903) := X"2402FBFF";
ram_buffer(904) := X"02228824";
ram_buffer(905) := X"32E20800";
ram_buffer(906) := X"1440FF9C";
ram_buffer(907) := X"2402F7FF";
ram_buffer(908) := X"02228824";
ram_buffer(909) := X"32E21000";
ram_buffer(910) := X"1440FFA3";
ram_buffer(911) := X"2402EFFF";
ram_buffer(912) := X"02228824";
ram_buffer(913) := X"32E22000";
ram_buffer(914) := X"1440FFAA";
ram_buffer(915) := X"2402DFFF";
ram_buffer(916) := X"02228824";
ram_buffer(917) := X"32E24000";
ram_buffer(918) := X"1440FFB1";
ram_buffer(919) := X"32E28000";
ram_buffer(920) := X"1440FFBA";
ram_buffer(921) := X"02368824";
ram_buffer(922) := X"1000FFC0";
ram_buffer(923) := X"02358824";
ram_buffer(924) := X"AE000004";
ram_buffer(925) := X"1440FFC6";
ram_buffer(926) := X"2402FFFD";
ram_buffer(927) := X"1000FF21";
ram_buffer(928) := X"36310002";
ram_buffer(929) := X"AE808074";
ram_buffer(930) := X"1440FFBD";
ram_buffer(931) := X"2402FFFE";
ram_buffer(932) := X"1000FF11";
ram_buffer(933) := X"36310001";
ram_buffer(934) := X"AE00000C";
ram_buffer(935) := X"1440FFC4";
ram_buffer(936) := X"2402FFF7";
ram_buffer(937) := X"1000FF2D";
ram_buffer(938) := X"36310008";
ram_buffer(939) := X"AE000008";
ram_buffer(940) := X"1440FFBB";
ram_buffer(941) := X"2402FFFB";
ram_buffer(942) := X"1000FF1D";
ram_buffer(943) := X"36310004";
ram_buffer(944) := X"AE000014";
ram_buffer(945) := X"1440FFC2";
ram_buffer(946) := X"2402FFDF";
ram_buffer(947) := X"1000FF39";
ram_buffer(948) := X"36310020";
ram_buffer(949) := X"AE000010";
ram_buffer(950) := X"1440FFB9";
ram_buffer(951) := X"2402FFEF";
ram_buffer(952) := X"1000FF29";
ram_buffer(953) := X"36310010";
ram_buffer(954) := X"AE00001C";
ram_buffer(955) := X"1440FFC0";
ram_buffer(956) := X"2402FF7F";
ram_buffer(957) := X"1000FF45";
ram_buffer(958) := X"36310080";
ram_buffer(959) := X"AE000018";
ram_buffer(960) := X"1440FFB7";
ram_buffer(961) := X"2402FFBF";
ram_buffer(962) := X"1000FF35";
ram_buffer(963) := X"36310040";
ram_buffer(964) := X"AE000024";
ram_buffer(965) := X"1440FFBE";
ram_buffer(966) := X"2402FDFF";
ram_buffer(967) := X"1000FF51";
ram_buffer(968) := X"36310200";
ram_buffer(969) := X"AE000020";
ram_buffer(970) := X"1440FFB5";
ram_buffer(971) := X"2402FEFF";
ram_buffer(972) := X"1000FF41";
ram_buffer(973) := X"36310100";
ram_buffer(974) := X"AE00002C";
ram_buffer(975) := X"1440FFBC";
ram_buffer(976) := X"2402F7FF";
ram_buffer(977) := X"1000FF5D";
ram_buffer(978) := X"36310800";
ram_buffer(979) := X"AE000028";
ram_buffer(980) := X"1440FFB3";
ram_buffer(981) := X"2402FBFF";
ram_buffer(982) := X"1000FF4D";
ram_buffer(983) := X"36310400";
ram_buffer(984) := X"AE000034";
ram_buffer(985) := X"1440FFBA";
ram_buffer(986) := X"2402DFFF";
ram_buffer(987) := X"1000FF69";
ram_buffer(988) := X"36312000";
ram_buffer(989) := X"AE000030";
ram_buffer(990) := X"1440FFB1";
ram_buffer(991) := X"2402EFFF";
ram_buffer(992) := X"1000FF59";
ram_buffer(993) := X"36311000";
ram_buffer(994) := X"AE00003C";
ram_buffer(995) := X"1440FFB6";
ram_buffer(996) := X"00000000";
ram_buffer(997) := X"1000FF75";
ram_buffer(998) := X"36318000";
ram_buffer(999) := X"AE000038";
ram_buffer(1000) := X"1440FFAF";
ram_buffer(1001) := X"32E28000";
ram_buffer(1002) := X"1000FF66";
ram_buffer(1003) := X"36314000";
ram_buffer(1004) := X"27BDFFE0";
ram_buffer(1005) := X"AFB10018";
ram_buffer(1006) := X"3C110102";
ram_buffer(1007) := X"8E228030";
ram_buffer(1008) := X"AFBF001C";
ram_buffer(1009) := X"8C420004";
ram_buffer(1010) := X"00000000";
ram_buffer(1011) := X"2C430008";
ram_buffer(1012) := X"10600010";
ram_buffer(1013) := X"AFB00014";
ram_buffer(1014) := X"3C100102";
ram_buffer(1015) := X"26108034";
ram_buffer(1016) := X"000210C0";
ram_buffer(1017) := X"02021021";
ram_buffer(1018) := X"8C430000";
ram_buffer(1019) := X"8C440004";
ram_buffer(1020) := X"0060F809";
ram_buffer(1021) := X"00000000";
ram_buffer(1022) := X"8E228030";
ram_buffer(1023) := X"00000000";
ram_buffer(1024) := X"8C420004";
ram_buffer(1025) := X"00000000";
ram_buffer(1026) := X"2C430008";
ram_buffer(1027) := X"1460FFF5";
ram_buffer(1028) := X"000210C0";
ram_buffer(1029) := X"8F82804C";
ram_buffer(1030) := X"00000000";
ram_buffer(1031) := X"14400006";
ram_buffer(1032) := X"00000000";
ram_buffer(1033) := X"8FBF001C";
ram_buffer(1034) := X"8FB10018";
ram_buffer(1035) := X"8FB00014";
ram_buffer(1036) := X"03E00008";
ram_buffer(1037) := X"27BD0020";
ram_buffer(1038) := X"8FBF001C";
ram_buffer(1039) := X"8FB10018";
ram_buffer(1040) := X"8FB00014";
ram_buffer(1041) := X"27BD0020";
ram_buffer(1042) := X"AF80804C";
ram_buffer(1043) := X"084016DA";
ram_buffer(1044) := X"00000000";
ram_buffer(1045) := X"3C020102";
ram_buffer(1046) := X"8C428030";
ram_buffer(1047) := X"240300FF";
ram_buffer(1048) := X"03E00008";
ram_buffer(1049) := X"AC430000";
ram_buffer(1050) := X"3C020102";
ram_buffer(1051) := X"8C428030";
ram_buffer(1052) := X"00000000";
ram_buffer(1053) := X"03E00008";
ram_buffer(1054) := X"AC400000";
ram_buffer(1055) := X"8F828074";
ram_buffer(1056) := X"00000000";
ram_buffer(1057) := X"AC450008";
ram_buffer(1058) := X"1000FFFF";
ram_buffer(1059) := X"00000000";
ram_buffer(1060) := X"10C00010";
ram_buffer(1061) := X"00C51821";
ram_buffer(1062) := X"2406FFF0";
ram_buffer(1063) := X"00661024";
ram_buffer(1064) := X"0043182B";
ram_buffer(1065) := X"00031900";
ram_buffer(1066) := X"24420010";
ram_buffer(1067) := X"00A62824";
ram_buffer(1068) := X"00431821";
ram_buffer(1069) := X"10A30007";
ram_buffer(1070) := X"2484FF00";
ram_buffer(1071) := X"00A61024";
ram_buffer(1072) := X"AC820000";
ram_buffer(1073) := X"AC400000";
ram_buffer(1074) := X"24A50010";
ram_buffer(1075) := X"14A3FFFC";
ram_buffer(1076) := X"00A61024";
ram_buffer(1077) := X"03E00008";
ram_buffer(1078) := X"00000000";
ram_buffer(1079) := X"24820008";
ram_buffer(1080) := X"2403FFFF";
ram_buffer(1081) := X"AC820004";
ram_buffer(1082) := X"AC830008";
ram_buffer(1083) := X"AC82000C";
ram_buffer(1084) := X"AC820010";
ram_buffer(1085) := X"03E00008";
ram_buffer(1086) := X"AC800000";
ram_buffer(1087) := X"03E00008";
ram_buffer(1088) := X"AC800010";
ram_buffer(1089) := X"8C820004";
ram_buffer(1090) := X"8C830000";
ram_buffer(1091) := X"8C460008";
ram_buffer(1092) := X"24630001";
ram_buffer(1093) := X"ACA60008";
ram_buffer(1094) := X"8C460008";
ram_buffer(1095) := X"ACA20004";
ram_buffer(1096) := X"ACC50004";
ram_buffer(1097) := X"AC450008";
ram_buffer(1098) := X"ACA40010";
ram_buffer(1099) := X"03E00008";
ram_buffer(1100) := X"AC830000";
ram_buffer(1101) := X"8CA70000";
ram_buffer(1102) := X"2402FFFF";
ram_buffer(1103) := X"10E20014";
ram_buffer(1104) := X"24860008";
ram_buffer(1105) := X"10000002";
ram_buffer(1106) := X"00000000";
ram_buffer(1107) := X"00603025";
ram_buffer(1108) := X"8CC30004";
ram_buffer(1109) := X"00000000";
ram_buffer(1110) := X"8C620000";
ram_buffer(1111) := X"00000000";
ram_buffer(1112) := X"00E2102B";
ram_buffer(1113) := X"1040FFF9";
ram_buffer(1114) := X"00000000";
ram_buffer(1115) := X"8C820000";
ram_buffer(1116) := X"ACA30004";
ram_buffer(1117) := X"24420001";
ram_buffer(1118) := X"AC650008";
ram_buffer(1119) := X"ACA60008";
ram_buffer(1120) := X"ACC50004";
ram_buffer(1121) := X"ACA40010";
ram_buffer(1122) := X"03E00008";
ram_buffer(1123) := X"AC820000";
ram_buffer(1124) := X"8C860010";
ram_buffer(1125) := X"8C820000";
ram_buffer(1126) := X"8CC30004";
ram_buffer(1127) := X"24420001";
ram_buffer(1128) := X"ACA30004";
ram_buffer(1129) := X"AC650008";
ram_buffer(1130) := X"ACA60008";
ram_buffer(1131) := X"ACC50004";
ram_buffer(1132) := X"ACA40010";
ram_buffer(1133) := X"03E00008";
ram_buffer(1134) := X"AC820000";
ram_buffer(1135) := X"8C850008";
ram_buffer(1136) := X"8C820004";
ram_buffer(1137) := X"8C830010";
ram_buffer(1138) := X"AC450008";
ram_buffer(1139) := X"8C850008";
ram_buffer(1140) := X"8C660004";
ram_buffer(1141) := X"00000000";
ram_buffer(1142) := X"10860006";
ram_buffer(1143) := X"ACA20004";
ram_buffer(1144) := X"8C620000";
ram_buffer(1145) := X"AC800010";
ram_buffer(1146) := X"2442FFFF";
ram_buffer(1147) := X"03E00008";
ram_buffer(1148) := X"AC620000";
ram_buffer(1149) := X"8C620000";
ram_buffer(1150) := X"AC650004";
ram_buffer(1151) := X"2442FFFF";
ram_buffer(1152) := X"AC800010";
ram_buffer(1153) := X"03E00008";
ram_buffer(1154) := X"AC620000";
ram_buffer(1155) := X"27BDFFE0";
ram_buffer(1156) := X"AFB10018";
ram_buffer(1157) := X"AFB00014";
ram_buffer(1158) := X"AFBF001C";
ram_buffer(1159) := X"00808025";
ram_buffer(1160) := X"10800033";
ram_buffer(1161) := X"00A08825";
ram_buffer(1162) := X"0C401997";
ram_buffer(1163) := X"00000000";
ram_buffer(1164) := X"8E040040";
ram_buffer(1165) := X"8E02003C";
ram_buffer(1166) := X"8E030000";
ram_buffer(1167) := X"00820018";
ram_buffer(1168) := X"2405FFFF";
ram_buffer(1169) := X"AE030008";
ram_buffer(1170) := X"AE000038";
ram_buffer(1171) := X"A2050044";
ram_buffer(1172) := X"A2050045";
ram_buffer(1173) := X"00001012";
ram_buffer(1174) := X"00442023";
ram_buffer(1175) := X"00621021";
ram_buffer(1176) := X"00641821";
ram_buffer(1177) := X"AE020004";
ram_buffer(1178) := X"16200015";
ram_buffer(1179) := X"AE03000C";
ram_buffer(1180) := X"8E020010";
ram_buffer(1181) := X"00000000";
ram_buffer(1182) := X"14400009";
ram_buffer(1183) := X"00000000";
ram_buffer(1184) := X"0C4019A9";
ram_buffer(1185) := X"00000000";
ram_buffer(1186) := X"8FBF001C";
ram_buffer(1187) := X"8FB10018";
ram_buffer(1188) := X"8FB00014";
ram_buffer(1189) := X"24020001";
ram_buffer(1190) := X"03E00008";
ram_buffer(1191) := X"27BD0020";
ram_buffer(1192) := X"0C4017E2";
ram_buffer(1193) := X"26040010";
ram_buffer(1194) := X"1040FFF5";
ram_buffer(1195) := X"00000000";
ram_buffer(1196) := X"0C4001B1";
ram_buffer(1197) := X"00000000";
ram_buffer(1198) := X"1000FFF1";
ram_buffer(1199) := X"00000000";
ram_buffer(1200) := X"0C400437";
ram_buffer(1201) := X"26040010";
ram_buffer(1202) := X"0C400437";
ram_buffer(1203) := X"26040024";
ram_buffer(1204) := X"0C4019A9";
ram_buffer(1205) := X"00000000";
ram_buffer(1206) := X"8FBF001C";
ram_buffer(1207) := X"8FB10018";
ram_buffer(1208) := X"8FB00014";
ram_buffer(1209) := X"24020001";
ram_buffer(1210) := X"03E00008";
ram_buffer(1211) := X"27BD0020";
ram_buffer(1212) := X"3C040100";
ram_buffer(1213) := X"2405011B";
ram_buffer(1214) := X"0C40041F";
ram_buffer(1215) := X"24847C20";
ram_buffer(1216) := X"1000FFC9";
ram_buffer(1217) := X"00000000";
ram_buffer(1218) := X"27BDFFE0";
ram_buffer(1219) := X"AFB20018";
ram_buffer(1220) := X"AFB10014";
ram_buffer(1221) := X"AFBF001C";
ram_buffer(1222) := X"AFB00010";
ram_buffer(1223) := X"00808825";
ram_buffer(1224) := X"1080002B";
ram_buffer(1225) := X"00A09025";
ram_buffer(1226) := X"02320018";
ram_buffer(1227) := X"00002012";
ram_buffer(1228) := X"0C401CCF";
ram_buffer(1229) := X"24840048";
ram_buffer(1230) := X"1040001C";
ram_buffer(1231) := X"00408025";
ram_buffer(1232) := X"16400021";
ram_buffer(1233) := X"00000000";
ram_buffer(1234) := X"AE020000";
ram_buffer(1235) := X"AE11003C";
ram_buffer(1236) := X"0C401997";
ram_buffer(1237) := X"AE120040";
ram_buffer(1238) := X"8E050040";
ram_buffer(1239) := X"8E02003C";
ram_buffer(1240) := X"8E030000";
ram_buffer(1241) := X"00A20018";
ram_buffer(1242) := X"2406FFFF";
ram_buffer(1243) := X"AE030008";
ram_buffer(1244) := X"AE000038";
ram_buffer(1245) := X"26040010";
ram_buffer(1246) := X"A2060044";
ram_buffer(1247) := X"A2060045";
ram_buffer(1248) := X"00001012";
ram_buffer(1249) := X"00452823";
ram_buffer(1250) := X"00621021";
ram_buffer(1251) := X"00651821";
ram_buffer(1252) := X"AE020004";
ram_buffer(1253) := X"0C400437";
ram_buffer(1254) := X"AE03000C";
ram_buffer(1255) := X"0C400437";
ram_buffer(1256) := X"26040024";
ram_buffer(1257) := X"0C4019A9";
ram_buffer(1258) := X"00000000";
ram_buffer(1259) := X"8FBF001C";
ram_buffer(1260) := X"02001025";
ram_buffer(1261) := X"8FB20018";
ram_buffer(1262) := X"8FB10014";
ram_buffer(1263) := X"8FB00010";
ram_buffer(1264) := X"03E00008";
ram_buffer(1265) := X"27BD0020";
ram_buffer(1266) := X"1000FFDF";
ram_buffer(1267) := X"24420048";
ram_buffer(1268) := X"3C040100";
ram_buffer(1269) := X"24050188";
ram_buffer(1270) := X"0C40041F";
ram_buffer(1271) := X"24847C20";
ram_buffer(1272) := X"1000FFD2";
ram_buffer(1273) := X"02320018";
ram_buffer(1274) := X"27BDFFE0";
ram_buffer(1275) := X"AFB20018";
ram_buffer(1276) := X"AFB10014";
ram_buffer(1277) := X"AFBF001C";
ram_buffer(1278) := X"AFB00010";
ram_buffer(1279) := X"00809025";
ram_buffer(1280) := X"10800029";
ram_buffer(1281) := X"00A08825";
ram_buffer(1282) := X"0085102B";
ram_buffer(1283) := X"14400033";
ram_buffer(1284) := X"3C040100";
ram_buffer(1285) := X"0C401CCF";
ram_buffer(1286) := X"24040048";
ram_buffer(1287) := X"1040001B";
ram_buffer(1288) := X"00408025";
ram_buffer(1289) := X"AE020000";
ram_buffer(1290) := X"AC52003C";
ram_buffer(1291) := X"0C401997";
ram_buffer(1292) := X"AC400040";
ram_buffer(1293) := X"8E050040";
ram_buffer(1294) := X"8E02003C";
ram_buffer(1295) := X"8E030000";
ram_buffer(1296) := X"00A20018";
ram_buffer(1297) := X"2406FFFF";
ram_buffer(1298) := X"AE030008";
ram_buffer(1299) := X"AE000038";
ram_buffer(1300) := X"26040010";
ram_buffer(1301) := X"A2060044";
ram_buffer(1302) := X"A2060045";
ram_buffer(1303) := X"00001012";
ram_buffer(1304) := X"00452823";
ram_buffer(1305) := X"00621021";
ram_buffer(1306) := X"00651821";
ram_buffer(1307) := X"AE020004";
ram_buffer(1308) := X"0C400437";
ram_buffer(1309) := X"AE03000C";
ram_buffer(1310) := X"0C400437";
ram_buffer(1311) := X"26040024";
ram_buffer(1312) := X"0C4019A9";
ram_buffer(1313) := X"00000000";
ram_buffer(1314) := X"AE110038";
ram_buffer(1315) := X"8FBF001C";
ram_buffer(1316) := X"02001025";
ram_buffer(1317) := X"8FB20018";
ram_buffer(1318) := X"8FB10014";
ram_buffer(1319) := X"8FB00010";
ram_buffer(1320) := X"03E00008";
ram_buffer(1321) := X"27BD0020";
ram_buffer(1322) := X"3C100100";
ram_buffer(1323) := X"240502BD";
ram_buffer(1324) := X"0C40041F";
ram_buffer(1325) := X"26047C20";
ram_buffer(1326) := X"12200003";
ram_buffer(1327) := X"240502BE";
ram_buffer(1328) := X"0C40041F";
ram_buffer(1329) := X"26047C20";
ram_buffer(1330) := X"24050188";
ram_buffer(1331) := X"0C40041F";
ram_buffer(1332) := X"26047C20";
ram_buffer(1333) := X"1000FFCF";
ram_buffer(1334) := X"00000000";
ram_buffer(1335) := X"240502BE";
ram_buffer(1336) := X"0C40041F";
ram_buffer(1337) := X"24847C20";
ram_buffer(1338) := X"1000FFCA";
ram_buffer(1339) := X"00000000";
ram_buffer(1340) := X"27BDFFC8";
ram_buffer(1341) := X"AFB5002C";
ram_buffer(1342) := X"AFB30024";
ram_buffer(1343) := X"AFB00018";
ram_buffer(1344) := X"AFBF0034";
ram_buffer(1345) := X"AFB60030";
ram_buffer(1346) := X"AFB40028";
ram_buffer(1347) := X"AFB20020";
ram_buffer(1348) := X"AFB1001C";
ram_buffer(1349) := X"00808025";
ram_buffer(1350) := X"00A0A825";
ram_buffer(1351) := X"AFA60040";
ram_buffer(1352) := X"108001BB";
ram_buffer(1353) := X"00E09825";
ram_buffer(1354) := X"12A001B0";
ram_buffer(1355) := X"00000000";
ram_buffer(1356) := X"24020002";
ram_buffer(1357) := X"1262015D";
ram_buffer(1358) := X"24020001";
ram_buffer(1359) := X"0C40190C";
ram_buffer(1360) := X"00000000";
ram_buffer(1361) := X"14400005";
ram_buffer(1362) := X"00000000";
ram_buffer(1363) := X"8FA20040";
ram_buffer(1364) := X"00000000";
ram_buffer(1365) := X"14400150";
ram_buffer(1366) := X"3C040100";
ram_buffer(1367) := X"0C401997";
ram_buffer(1368) := X"00000000";
ram_buffer(1369) := X"8E020038";
ram_buffer(1370) := X"8E03003C";
ram_buffer(1371) := X"0000B025";
ram_buffer(1372) := X"0043102B";
ram_buffer(1373) := X"24140002";
ram_buffer(1374) := X"26120024";
ram_buffer(1375) := X"14400078";
ram_buffer(1376) := X"26110010";
ram_buffer(1377) := X"12740152";
ram_buffer(1378) := X"00000000";
ram_buffer(1379) := X"8FA20040";
ram_buffer(1380) := X"00000000";
ram_buffer(1381) := X"1040017A";
ram_buffer(1382) := X"00000000";
ram_buffer(1383) := X"12C000D3";
ram_buffer(1384) := X"00000000";
ram_buffer(1385) := X"0C4019A9";
ram_buffer(1386) := X"00000000";
ram_buffer(1387) := X"0C4010EF";
ram_buffer(1388) := X"00000000";
ram_buffer(1389) := X"0C401997";
ram_buffer(1390) := X"00000000";
ram_buffer(1391) := X"92020044";
ram_buffer(1392) := X"2403FFFF";
ram_buffer(1393) := X"00021600";
ram_buffer(1394) := X"00021603";
ram_buffer(1395) := X"104300D5";
ram_buffer(1396) := X"00000000";
ram_buffer(1397) := X"92020045";
ram_buffer(1398) := X"2403FFFF";
ram_buffer(1399) := X"00021600";
ram_buffer(1400) := X"00021603";
ram_buffer(1401) := X"104300D6";
ram_buffer(1402) := X"00000000";
ram_buffer(1403) := X"0C4019A9";
ram_buffer(1404) := X"00000000";
ram_buffer(1405) := X"27A50040";
ram_buffer(1406) := X"0C401884";
ram_buffer(1407) := X"27A40010";
ram_buffer(1408) := X"144000D7";
ram_buffer(1409) := X"00000000";
ram_buffer(1410) := X"0C401997";
ram_buffer(1411) := X"00000000";
ram_buffer(1412) := X"8E030038";
ram_buffer(1413) := X"8E02003C";
ram_buffer(1414) := X"00000000";
ram_buffer(1415) := X"10620064";
ram_buffer(1416) := X"00000000";
ram_buffer(1417) := X"0C4019A9";
ram_buffer(1418) := X"00000000";
ram_buffer(1419) := X"0C401997";
ram_buffer(1420) := X"00000000";
ram_buffer(1421) := X"92020045";
ram_buffer(1422) := X"00000000";
ram_buffer(1423) := X"0002B600";
ram_buffer(1424) := X"0016B603";
ram_buffer(1425) := X"1EC00007";
ram_buffer(1426) := X"2402FFFF";
ram_buffer(1427) := X"10000015";
ram_buffer(1428) := X"00000000";
ram_buffer(1429) := X"304200FF";
ram_buffer(1430) := X"0002B600";
ram_buffer(1431) := X"10400010";
ram_buffer(1432) := X"0016B603";
ram_buffer(1433) := X"8E020024";
ram_buffer(1434) := X"00000000";
ram_buffer(1435) := X"1040000D";
ram_buffer(1436) := X"2402FFFF";
ram_buffer(1437) := X"0C4017E2";
ram_buffer(1438) := X"02402025";
ram_buffer(1439) := X"1040FFF5";
ram_buffer(1440) := X"26C2FFFF";
ram_buffer(1441) := X"0C4018EE";
ram_buffer(1442) := X"00000000";
ram_buffer(1443) := X"26C2FFFF";
ram_buffer(1444) := X"304200FF";
ram_buffer(1445) := X"0002B600";
ram_buffer(1446) := X"1440FFF2";
ram_buffer(1447) := X"0016B603";
ram_buffer(1448) := X"2402FFFF";
ram_buffer(1449) := X"A2020045";
ram_buffer(1450) := X"0C4019A9";
ram_buffer(1451) := X"00000000";
ram_buffer(1452) := X"0C401997";
ram_buffer(1453) := X"00000000";
ram_buffer(1454) := X"92020044";
ram_buffer(1455) := X"00000000";
ram_buffer(1456) := X"0002B600";
ram_buffer(1457) := X"0016B603";
ram_buffer(1458) := X"1EC00007";
ram_buffer(1459) := X"2402FFFF";
ram_buffer(1460) := X"10000015";
ram_buffer(1461) := X"00000000";
ram_buffer(1462) := X"304200FF";
ram_buffer(1463) := X"0002B600";
ram_buffer(1464) := X"10400010";
ram_buffer(1465) := X"0016B603";
ram_buffer(1466) := X"8E020010";
ram_buffer(1467) := X"00000000";
ram_buffer(1468) := X"1040000D";
ram_buffer(1469) := X"2402FFFF";
ram_buffer(1470) := X"0C4017E2";
ram_buffer(1471) := X"02202025";
ram_buffer(1472) := X"1040FFF5";
ram_buffer(1473) := X"26C2FFFF";
ram_buffer(1474) := X"0C4018EE";
ram_buffer(1475) := X"00000000";
ram_buffer(1476) := X"26C2FFFF";
ram_buffer(1477) := X"304200FF";
ram_buffer(1478) := X"0002B600";
ram_buffer(1479) := X"1440FFF2";
ram_buffer(1480) := X"0016B603";
ram_buffer(1481) := X"2402FFFF";
ram_buffer(1482) := X"A2020044";
ram_buffer(1483) := X"0C4019A9";
ram_buffer(1484) := X"00000000";
ram_buffer(1485) := X"0C4011C5";
ram_buffer(1486) := X"00000000";
ram_buffer(1487) := X"24160001";
ram_buffer(1488) := X"0C401997";
ram_buffer(1489) := X"00000000";
ram_buffer(1490) := X"8E020038";
ram_buffer(1491) := X"8E03003C";
ram_buffer(1492) := X"00000000";
ram_buffer(1493) := X"0043102B";
ram_buffer(1494) := X"1040FF8A";
ram_buffer(1495) := X"00000000";
ram_buffer(1496) := X"8E060040";
ram_buffer(1497) := X"8E110038";
ram_buffer(1498) := X"10C000DD";
ram_buffer(1499) := X"00000000";
ram_buffer(1500) := X"1660012D";
ram_buffer(1501) := X"00000000";
ram_buffer(1502) := X"8E040008";
ram_buffer(1503) := X"0C401DD6";
ram_buffer(1504) := X"02A02825";
ram_buffer(1505) := X"8E020008";
ram_buffer(1506) := X"8E040040";
ram_buffer(1507) := X"8E030004";
ram_buffer(1508) := X"00441021";
ram_buffer(1509) := X"0043182B";
ram_buffer(1510) := X"146000D5";
ram_buffer(1511) := X"AE020008";
ram_buffer(1512) := X"8E020000";
ram_buffer(1513) := X"26310001";
ram_buffer(1514) := X"100000D2";
ram_buffer(1515) := X"AE020008";
ram_buffer(1516) := X"0C4019A9";
ram_buffer(1517) := X"00000000";
ram_buffer(1518) := X"8FA50040";
ram_buffer(1519) := X"0C401753";
ram_buffer(1520) := X"02202025";
ram_buffer(1521) := X"0C401997";
ram_buffer(1522) := X"00000000";
ram_buffer(1523) := X"92020045";
ram_buffer(1524) := X"00000000";
ram_buffer(1525) := X"0002B600";
ram_buffer(1526) := X"0016B603";
ram_buffer(1527) := X"1EC00007";
ram_buffer(1528) := X"2402FFFF";
ram_buffer(1529) := X"10000015";
ram_buffer(1530) := X"00000000";
ram_buffer(1531) := X"304200FF";
ram_buffer(1532) := X"0002B600";
ram_buffer(1533) := X"10400010";
ram_buffer(1534) := X"0016B603";
ram_buffer(1535) := X"8E020024";
ram_buffer(1536) := X"00000000";
ram_buffer(1537) := X"1040000D";
ram_buffer(1538) := X"2402FFFF";
ram_buffer(1539) := X"0C4017E2";
ram_buffer(1540) := X"02402025";
ram_buffer(1541) := X"1040FFF5";
ram_buffer(1542) := X"26C2FFFF";
ram_buffer(1543) := X"0C4018EE";
ram_buffer(1544) := X"00000000";
ram_buffer(1545) := X"26C2FFFF";
ram_buffer(1546) := X"304200FF";
ram_buffer(1547) := X"0002B600";
ram_buffer(1548) := X"1440FFF2";
ram_buffer(1549) := X"0016B603";
ram_buffer(1550) := X"2402FFFF";
ram_buffer(1551) := X"A2020045";
ram_buffer(1552) := X"0C4019A9";
ram_buffer(1553) := X"00000000";
ram_buffer(1554) := X"0C401997";
ram_buffer(1555) := X"00000000";
ram_buffer(1556) := X"92020044";
ram_buffer(1557) := X"00000000";
ram_buffer(1558) := X"0002B600";
ram_buffer(1559) := X"0016B603";
ram_buffer(1560) := X"1EC00007";
ram_buffer(1561) := X"2402FFFF";
ram_buffer(1562) := X"10000015";
ram_buffer(1563) := X"00000000";
ram_buffer(1564) := X"304200FF";
ram_buffer(1565) := X"0002B600";
ram_buffer(1566) := X"10400010";
ram_buffer(1567) := X"0016B603";
ram_buffer(1568) := X"8E020010";
ram_buffer(1569) := X"00000000";
ram_buffer(1570) := X"1040000D";
ram_buffer(1571) := X"2402FFFF";
ram_buffer(1572) := X"0C4017E2";
ram_buffer(1573) := X"02202025";
ram_buffer(1574) := X"1040FFF5";
ram_buffer(1575) := X"26C2FFFF";
ram_buffer(1576) := X"0C4018EE";
ram_buffer(1577) := X"00000000";
ram_buffer(1578) := X"26C2FFFF";
ram_buffer(1579) := X"304200FF";
ram_buffer(1580) := X"0002B600";
ram_buffer(1581) := X"1440FFF2";
ram_buffer(1582) := X"0016B603";
ram_buffer(1583) := X"2402FFFF";
ram_buffer(1584) := X"A2020044";
ram_buffer(1585) := X"0C4019A9";
ram_buffer(1586) := X"00000000";
ram_buffer(1587) := X"0C4011C5";
ram_buffer(1588) := X"00000000";
ram_buffer(1589) := X"1440FF99";
ram_buffer(1590) := X"00000000";
ram_buffer(1591) := X"0C4001B1";
ram_buffer(1592) := X"24160001";
ram_buffer(1593) := X"1000FF96";
ram_buffer(1594) := X"00000000";
ram_buffer(1595) := X"0C40186B";
ram_buffer(1596) := X"27A40010";
ram_buffer(1597) := X"0C4019A9";
ram_buffer(1598) := X"00000000";
ram_buffer(1599) := X"0C4010EF";
ram_buffer(1600) := X"00000000";
ram_buffer(1601) := X"0C401997";
ram_buffer(1602) := X"00000000";
ram_buffer(1603) := X"92020044";
ram_buffer(1604) := X"2403FFFF";
ram_buffer(1605) := X"00021600";
ram_buffer(1606) := X"00021603";
ram_buffer(1607) := X"1443FF2D";
ram_buffer(1608) := X"00000000";
ram_buffer(1609) := X"A2000044";
ram_buffer(1610) := X"92020045";
ram_buffer(1611) := X"2403FFFF";
ram_buffer(1612) := X"00021600";
ram_buffer(1613) := X"00021603";
ram_buffer(1614) := X"1443FF2C";
ram_buffer(1615) := X"00000000";
ram_buffer(1616) := X"A2000045";
ram_buffer(1617) := X"0C4019A9";
ram_buffer(1618) := X"00000000";
ram_buffer(1619) := X"27A50040";
ram_buffer(1620) := X"0C401884";
ram_buffer(1621) := X"27A40010";
ram_buffer(1622) := X"1040FF2B";
ram_buffer(1623) := X"00000000";
ram_buffer(1624) := X"0C401997";
ram_buffer(1625) := X"00000000";
ram_buffer(1626) := X"92110045";
ram_buffer(1627) := X"00000000";
ram_buffer(1628) := X"00118E00";
ram_buffer(1629) := X"00118E03";
ram_buffer(1630) := X"1A20001B";
ram_buffer(1631) := X"2402FFFF";
ram_buffer(1632) := X"8E020024";
ram_buffer(1633) := X"00000000";
ram_buffer(1634) := X"10400017";
ram_buffer(1635) := X"2402FFFF";
ram_buffer(1636) := X"1000000A";
ram_buffer(1637) := X"26120024";
ram_buffer(1638) := X"2631FFFF";
ram_buffer(1639) := X"322200FF";
ram_buffer(1640) := X"00028E00";
ram_buffer(1641) := X"1040000F";
ram_buffer(1642) := X"00118E03";
ram_buffer(1643) := X"8E020024";
ram_buffer(1644) := X"00000000";
ram_buffer(1645) := X"1040000C";
ram_buffer(1646) := X"2402FFFF";
ram_buffer(1647) := X"0C4017E2";
ram_buffer(1648) := X"02402025";
ram_buffer(1649) := X"1040FFF4";
ram_buffer(1650) := X"00000000";
ram_buffer(1651) := X"0C4018EE";
ram_buffer(1652) := X"2631FFFF";
ram_buffer(1653) := X"322200FF";
ram_buffer(1654) := X"00028E00";
ram_buffer(1655) := X"1440FFF3";
ram_buffer(1656) := X"00118E03";
ram_buffer(1657) := X"2402FFFF";
ram_buffer(1658) := X"A2020045";
ram_buffer(1659) := X"0C4019A9";
ram_buffer(1660) := X"00000000";
ram_buffer(1661) := X"0C401997";
ram_buffer(1662) := X"00000000";
ram_buffer(1663) := X"92110044";
ram_buffer(1664) := X"00000000";
ram_buffer(1665) := X"00118E00";
ram_buffer(1666) := X"00118E03";
ram_buffer(1667) := X"1A20001B";
ram_buffer(1668) := X"2402FFFF";
ram_buffer(1669) := X"8E020010";
ram_buffer(1670) := X"00000000";
ram_buffer(1671) := X"10400016";
ram_buffer(1672) := X"26120010";
ram_buffer(1673) := X"1000000A";
ram_buffer(1674) := X"00000000";
ram_buffer(1675) := X"2631FFFF";
ram_buffer(1676) := X"322200FF";
ram_buffer(1677) := X"00028E00";
ram_buffer(1678) := X"1040000F";
ram_buffer(1679) := X"00118E03";
ram_buffer(1680) := X"8E020010";
ram_buffer(1681) := X"00000000";
ram_buffer(1682) := X"1040000C";
ram_buffer(1683) := X"2402FFFF";
ram_buffer(1684) := X"0C4017E2";
ram_buffer(1685) := X"02402025";
ram_buffer(1686) := X"1040FFF4";
ram_buffer(1687) := X"00000000";
ram_buffer(1688) := X"0C4018EE";
ram_buffer(1689) := X"2631FFFF";
ram_buffer(1690) := X"322200FF";
ram_buffer(1691) := X"00028E00";
ram_buffer(1692) := X"1440FFF3";
ram_buffer(1693) := X"00118E03";
ram_buffer(1694) := X"2402FFFF";
ram_buffer(1695) := X"A2020044";
ram_buffer(1696) := X"0C4019A9";
ram_buffer(1697) := X"00000000";
ram_buffer(1698) := X"0C4011C5";
ram_buffer(1699) := X"00000000";
ram_buffer(1700) := X"10000023";
ram_buffer(1701) := X"00001025";
ram_buffer(1702) := X"240502DE";
ram_buffer(1703) := X"0C40041F";
ram_buffer(1704) := X"24847C20";
ram_buffer(1705) := X"1000FEAD";
ram_buffer(1706) := X"00000000";
ram_buffer(1707) := X"8E03003C";
ram_buffer(1708) := X"00000000";
ram_buffer(1709) := X"1062FEA1";
ram_buffer(1710) := X"3C040100";
ram_buffer(1711) := X"240502DB";
ram_buffer(1712) := X"0C40041F";
ram_buffer(1713) := X"24847C20";
ram_buffer(1714) := X"1000FE9C";
ram_buffer(1715) := X"00000000";
ram_buffer(1716) := X"8E060040";
ram_buffer(1717) := X"8E110038";
ram_buffer(1718) := X"14C0002D";
ram_buffer(1719) := X"00000000";
ram_buffer(1720) := X"8E020000";
ram_buffer(1721) := X"00000000";
ram_buffer(1722) := X"10400017";
ram_buffer(1723) := X"00000000";
ram_buffer(1724) := X"26310001";
ram_buffer(1725) := X"8E020024";
ram_buffer(1726) := X"AE110038";
ram_buffer(1727) := X"10400005";
ram_buffer(1728) := X"00000000";
ram_buffer(1729) := X"0C4017E2";
ram_buffer(1730) := X"26040024";
ram_buffer(1731) := X"14400018";
ram_buffer(1732) := X"00000000";
ram_buffer(1733) := X"0C4019A9";
ram_buffer(1734) := X"00000000";
ram_buffer(1735) := X"24020001";
ram_buffer(1736) := X"8FBF0034";
ram_buffer(1737) := X"8FB60030";
ram_buffer(1738) := X"8FB5002C";
ram_buffer(1739) := X"8FB40028";
ram_buffer(1740) := X"8FB30024";
ram_buffer(1741) := X"8FB20020";
ram_buffer(1742) := X"8FB1001C";
ram_buffer(1743) := X"8FB00018";
ram_buffer(1744) := X"03E00008";
ram_buffer(1745) := X"27BD0038";
ram_buffer(1746) := X"8E040004";
ram_buffer(1747) := X"0C401958";
ram_buffer(1748) := X"26310001";
ram_buffer(1749) := X"8E030024";
ram_buffer(1750) := X"AE000004";
ram_buffer(1751) := X"AE110038";
ram_buffer(1752) := X"1460FFE8";
ram_buffer(1753) := X"00000000";
ram_buffer(1754) := X"1040FFEA";
ram_buffer(1755) := X"00000000";
ram_buffer(1756) := X"0C4001B1";
ram_buffer(1757) := X"00000000";
ram_buffer(1758) := X"1000FFE6";
ram_buffer(1759) := X"00000000";
ram_buffer(1760) := X"0C4019A9";
ram_buffer(1761) := X"00000000";
ram_buffer(1762) := X"1000FFE5";
ram_buffer(1763) := X"00001025";
ram_buffer(1764) := X"8E04000C";
ram_buffer(1765) := X"0C401DD6";
ram_buffer(1766) := X"02A02825";
ram_buffer(1767) := X"8E020040";
ram_buffer(1768) := X"8E03000C";
ram_buffer(1769) := X"00021023";
ram_buffer(1770) := X"8E040000";
ram_buffer(1771) := X"00621821";
ram_buffer(1772) := X"0064202B";
ram_buffer(1773) := X"10800009";
ram_buffer(1774) := X"AE03000C";
ram_buffer(1775) := X"8E030004";
ram_buffer(1776) := X"00000000";
ram_buffer(1777) := X"00621021";
ram_buffer(1778) := X"AE02000C";
ram_buffer(1779) := X"24020002";
ram_buffer(1780) := X"1662FFC8";
ram_buffer(1781) := X"26310001";
ram_buffer(1782) := X"2631FFFF";
ram_buffer(1783) := X"1620FFC5";
ram_buffer(1784) := X"00000000";
ram_buffer(1785) := X"1000FFC3";
ram_buffer(1786) := X"24110001";
ram_buffer(1787) := X"8E020040";
ram_buffer(1788) := X"00000000";
ram_buffer(1789) := X"1040FE4E";
ram_buffer(1790) := X"3C040100";
ram_buffer(1791) := X"240502DA";
ram_buffer(1792) := X"0C40041F";
ram_buffer(1793) := X"24847C20";
ram_buffer(1794) := X"1000FE4A";
ram_buffer(1795) := X"24020002";
ram_buffer(1796) := X"3C040100";
ram_buffer(1797) := X"240502D9";
ram_buffer(1798) := X"0C40041F";
ram_buffer(1799) := X"24847C20";
ram_buffer(1800) := X"1000FE41";
ram_buffer(1801) := X"00000000";
ram_buffer(1802) := X"8E04000C";
ram_buffer(1803) := X"0C401DD6";
ram_buffer(1804) := X"02A02825";
ram_buffer(1805) := X"8E020040";
ram_buffer(1806) := X"8E03000C";
ram_buffer(1807) := X"00021023";
ram_buffer(1808) := X"8E040000";
ram_buffer(1809) := X"00621821";
ram_buffer(1810) := X"0064202B";
ram_buffer(1811) := X"1080FFDF";
ram_buffer(1812) := X"AE03000C";
ram_buffer(1813) := X"1000FFD9";
ram_buffer(1814) := X"00000000";
ram_buffer(1815) := X"27BDFFE8";
ram_buffer(1816) := X"AFB00010";
ram_buffer(1817) := X"AFBF0014";
ram_buffer(1818) := X"0C401CCF";
ram_buffer(1819) := X"24040048";
ram_buffer(1820) := X"10400023";
ram_buffer(1821) := X"00408025";
ram_buffer(1822) := X"AE020000";
ram_buffer(1823) := X"24020001";
ram_buffer(1824) := X"AE02003C";
ram_buffer(1825) := X"0C401997";
ram_buffer(1826) := X"AE000040";
ram_buffer(1827) := X"8E050040";
ram_buffer(1828) := X"8E02003C";
ram_buffer(1829) := X"8E030000";
ram_buffer(1830) := X"00A20018";
ram_buffer(1831) := X"2406FFFF";
ram_buffer(1832) := X"AE030008";
ram_buffer(1833) := X"AE000038";
ram_buffer(1834) := X"26040010";
ram_buffer(1835) := X"A2060044";
ram_buffer(1836) := X"A2060045";
ram_buffer(1837) := X"00001012";
ram_buffer(1838) := X"00452823";
ram_buffer(1839) := X"00621021";
ram_buffer(1840) := X"00651821";
ram_buffer(1841) := X"AE020004";
ram_buffer(1842) := X"0C400437";
ram_buffer(1843) := X"AE03000C";
ram_buffer(1844) := X"0C400437";
ram_buffer(1845) := X"26040024";
ram_buffer(1846) := X"0C4019A9";
ram_buffer(1847) := X"00000000";
ram_buffer(1848) := X"AE000004";
ram_buffer(1849) := X"AE000000";
ram_buffer(1850) := X"AE00000C";
ram_buffer(1851) := X"00003825";
ram_buffer(1852) := X"00003025";
ram_buffer(1853) := X"00002825";
ram_buffer(1854) := X"0C40053C";
ram_buffer(1855) := X"02002025";
ram_buffer(1856) := X"8FBF0014";
ram_buffer(1857) := X"02001025";
ram_buffer(1858) := X"8FB00010";
ram_buffer(1859) := X"03E00008";
ram_buffer(1860) := X"27BD0018";
ram_buffer(1861) := X"27BDFFE0";
ram_buffer(1862) := X"AFB00014";
ram_buffer(1863) := X"AFBF001C";
ram_buffer(1864) := X"AFB10018";
ram_buffer(1865) := X"1080001D";
ram_buffer(1866) := X"00808025";
ram_buffer(1867) := X"8E110004";
ram_buffer(1868) := X"0C401909";
ram_buffer(1869) := X"00000000";
ram_buffer(1870) := X"12220006";
ram_buffer(1871) := X"00001025";
ram_buffer(1872) := X"8FBF001C";
ram_buffer(1873) := X"8FB10018";
ram_buffer(1874) := X"8FB00014";
ram_buffer(1875) := X"03E00008";
ram_buffer(1876) := X"27BD0020";
ram_buffer(1877) := X"8E02000C";
ram_buffer(1878) := X"00000000";
ram_buffer(1879) := X"2442FFFF";
ram_buffer(1880) := X"10400007";
ram_buffer(1881) := X"AE02000C";
ram_buffer(1882) := X"8FBF001C";
ram_buffer(1883) := X"8FB10018";
ram_buffer(1884) := X"8FB00014";
ram_buffer(1885) := X"24020001";
ram_buffer(1886) := X"03E00008";
ram_buffer(1887) := X"27BD0020";
ram_buffer(1888) := X"00003825";
ram_buffer(1889) := X"00003025";
ram_buffer(1890) := X"00002825";
ram_buffer(1891) := X"0C40053C";
ram_buffer(1892) := X"02002025";
ram_buffer(1893) := X"1000FFEA";
ram_buffer(1894) := X"24020001";
ram_buffer(1895) := X"3C040100";
ram_buffer(1896) := X"24050241";
ram_buffer(1897) := X"0C40041F";
ram_buffer(1898) := X"24847C20";
ram_buffer(1899) := X"1000FFDF";
ram_buffer(1900) := X"00000000";
ram_buffer(1901) := X"27BDFFD0";
ram_buffer(1902) := X"AFB40024";
ram_buffer(1903) := X"AFB30020";
ram_buffer(1904) := X"AFB2001C";
ram_buffer(1905) := X"AFB00014";
ram_buffer(1906) := X"AFBF002C";
ram_buffer(1907) := X"AFB50028";
ram_buffer(1908) := X"AFB10018";
ram_buffer(1909) := X"00808025";
ram_buffer(1910) := X"00A09025";
ram_buffer(1911) := X"00C0A025";
ram_buffer(1912) := X"10800075";
ram_buffer(1913) := X"00E09825";
ram_buffer(1914) := X"1240006A";
ram_buffer(1915) := X"00000000";
ram_buffer(1916) := X"24020002";
ram_buffer(1917) := X"12620027";
ram_buffer(1918) := X"24030001";
ram_buffer(1919) := X"8E030038";
ram_buffer(1920) := X"8E02003C";
ram_buffer(1921) := X"00000000";
ram_buffer(1922) := X"0062102B";
ram_buffer(1923) := X"1440000A";
ram_buffer(1924) := X"00000000";
ram_buffer(1925) := X"8FBF002C";
ram_buffer(1926) := X"8FB50028";
ram_buffer(1927) := X"8FB40024";
ram_buffer(1928) := X"8FB30020";
ram_buffer(1929) := X"8FB2001C";
ram_buffer(1930) := X"8FB10018";
ram_buffer(1931) := X"8FB00014";
ram_buffer(1932) := X"03E00008";
ram_buffer(1933) := X"27BD0030";
ram_buffer(1934) := X"92110045";
ram_buffer(1935) := X"8E060040";
ram_buffer(1936) := X"00118E00";
ram_buffer(1937) := X"00118E03";
ram_buffer(1938) := X"8E150038";
ram_buffer(1939) := X"10C00020";
ram_buffer(1940) := X"00000000";
ram_buffer(1941) := X"1660002C";
ram_buffer(1942) := X"00000000";
ram_buffer(1943) := X"8E040008";
ram_buffer(1944) := X"0C401DD6";
ram_buffer(1945) := X"02402825";
ram_buffer(1946) := X"8E020008";
ram_buffer(1947) := X"8E040040";
ram_buffer(1948) := X"8E030004";
ram_buffer(1949) := X"00441021";
ram_buffer(1950) := X"0043182B";
ram_buffer(1951) := X"14600018";
ram_buffer(1952) := X"AE020008";
ram_buffer(1953) := X"8E020000";
ram_buffer(1954) := X"26B50001";
ram_buffer(1955) := X"10000015";
ram_buffer(1956) := X"AE020008";
ram_buffer(1957) := X"8E02003C";
ram_buffer(1958) := X"00000000";
ram_buffer(1959) := X"10430004";
ram_buffer(1960) := X"240503A1";
ram_buffer(1961) := X"3C040100";
ram_buffer(1962) := X"0C40041F";
ram_buffer(1963) := X"24847C20";
ram_buffer(1964) := X"8E030038";
ram_buffer(1965) := X"92110045";
ram_buffer(1966) := X"8E060040";
ram_buffer(1967) := X"00118E00";
ram_buffer(1968) := X"00118E03";
ram_buffer(1969) := X"8E150038";
ram_buffer(1970) := X"14C0000F";
ram_buffer(1971) := X"00000000";
ram_buffer(1972) := X"8E020000";
ram_buffer(1973) := X"00000000";
ram_buffer(1974) := X"1040003D";
ram_buffer(1975) := X"00000000";
ram_buffer(1976) := X"26B50001";
ram_buffer(1977) := X"2402FFFF";
ram_buffer(1978) := X"AE150038";
ram_buffer(1979) := X"1222001C";
ram_buffer(1980) := X"26310001";
ram_buffer(1981) := X"00118E00";
ram_buffer(1982) := X"00118E03";
ram_buffer(1983) := X"A2110045";
ram_buffer(1984) := X"1000FFC4";
ram_buffer(1985) := X"24020001";
ram_buffer(1986) := X"8E04000C";
ram_buffer(1987) := X"0C401DD6";
ram_buffer(1988) := X"02402825";
ram_buffer(1989) := X"8E030040";
ram_buffer(1990) := X"8E02000C";
ram_buffer(1991) := X"00031823";
ram_buffer(1992) := X"8E040000";
ram_buffer(1993) := X"00431021";
ram_buffer(1994) := X"0044202B";
ram_buffer(1995) := X"10800005";
ram_buffer(1996) := X"AE02000C";
ram_buffer(1997) := X"8E020004";
ram_buffer(1998) := X"00000000";
ram_buffer(1999) := X"00431821";
ram_buffer(2000) := X"AE03000C";
ram_buffer(2001) := X"24020002";
ram_buffer(2002) := X"1662FFE5";
ram_buffer(2003) := X"00000000";
ram_buffer(2004) := X"16A0FFE5";
ram_buffer(2005) := X"2402FFFF";
ram_buffer(2006) := X"1000FFE3";
ram_buffer(2007) := X"24150001";
ram_buffer(2008) := X"8E020024";
ram_buffer(2009) := X"00000000";
ram_buffer(2010) := X"1040FFAA";
ram_buffer(2011) := X"24020001";
ram_buffer(2012) := X"0C4017E2";
ram_buffer(2013) := X"26040024";
ram_buffer(2014) := X"1040FFE1";
ram_buffer(2015) := X"00000000";
ram_buffer(2016) := X"1280FFDF";
ram_buffer(2017) := X"00000000";
ram_buffer(2018) := X"24020001";
ram_buffer(2019) := X"1000FFA1";
ram_buffer(2020) := X"AE820000";
ram_buffer(2021) := X"8E020040";
ram_buffer(2022) := X"00000000";
ram_buffer(2023) := X"1040FF94";
ram_buffer(2024) := X"3C040100";
ram_buffer(2025) := X"240503A0";
ram_buffer(2026) := X"0C40041F";
ram_buffer(2027) := X"24847C20";
ram_buffer(2028) := X"1000FF90";
ram_buffer(2029) := X"24020002";
ram_buffer(2030) := X"3C040100";
ram_buffer(2031) := X"2405039F";
ram_buffer(2032) := X"0C40041F";
ram_buffer(2033) := X"24847C20";
ram_buffer(2034) := X"1000FF87";
ram_buffer(2035) := X"00000000";
ram_buffer(2036) := X"8E040004";
ram_buffer(2037) := X"0C401958";
ram_buffer(2038) := X"26B50001";
ram_buffer(2039) := X"1000FFC1";
ram_buffer(2040) := X"AE000004";
ram_buffer(2041) := X"27BDFFE0";
ram_buffer(2042) := X"AFB10018";
ram_buffer(2043) := X"AFB00014";
ram_buffer(2044) := X"AFBF001C";
ram_buffer(2045) := X"00808025";
ram_buffer(2046) := X"10800041";
ram_buffer(2047) := X"00A08825";
ram_buffer(2048) := X"8E020040";
ram_buffer(2049) := X"00000000";
ram_buffer(2050) := X"14400021";
ram_buffer(2051) := X"3C040100";
ram_buffer(2052) := X"8E020000";
ram_buffer(2053) := X"00000000";
ram_buffer(2054) := X"10400024";
ram_buffer(2055) := X"00000000";
ram_buffer(2056) := X"8E030038";
ram_buffer(2057) := X"8E02003C";
ram_buffer(2058) := X"00000000";
ram_buffer(2059) := X"0062102B";
ram_buffer(2060) := X"10400012";
ram_buffer(2061) := X"00001025";
ram_buffer(2062) := X"92020045";
ram_buffer(2063) := X"24630001";
ram_buffer(2064) := X"00022E00";
ram_buffer(2065) := X"00052E03";
ram_buffer(2066) := X"2404FFFF";
ram_buffer(2067) := X"AE030038";
ram_buffer(2068) := X"10A4001F";
ram_buffer(2069) := X"24420001";
ram_buffer(2070) := X"00021600";
ram_buffer(2071) := X"00021603";
ram_buffer(2072) := X"A2020045";
ram_buffer(2073) := X"24020001";
ram_buffer(2074) := X"8FBF001C";
ram_buffer(2075) := X"8FB10018";
ram_buffer(2076) := X"8FB00014";
ram_buffer(2077) := X"03E00008";
ram_buffer(2078) := X"27BD0020";
ram_buffer(2079) := X"8FBF001C";
ram_buffer(2080) := X"8FB10018";
ram_buffer(2081) := X"8FB00014";
ram_buffer(2082) := X"03E00008";
ram_buffer(2083) := X"27BD0020";
ram_buffer(2084) := X"24050440";
ram_buffer(2085) := X"0C40041F";
ram_buffer(2086) := X"24847C20";
ram_buffer(2087) := X"8E020000";
ram_buffer(2088) := X"00000000";
ram_buffer(2089) := X"1440FFDE";
ram_buffer(2090) := X"00000000";
ram_buffer(2091) := X"8E020004";
ram_buffer(2092) := X"00000000";
ram_buffer(2093) := X"1040FFDA";
ram_buffer(2094) := X"3C040100";
ram_buffer(2095) := X"24050445";
ram_buffer(2096) := X"0C40041F";
ram_buffer(2097) := X"24847C20";
ram_buffer(2098) := X"1000FFD5";
ram_buffer(2099) := X"00000000";
ram_buffer(2100) := X"8E020024";
ram_buffer(2101) := X"00000000";
ram_buffer(2102) := X"1040FFE3";
ram_buffer(2103) := X"24020001";
ram_buffer(2104) := X"0C4017E2";
ram_buffer(2105) := X"26040024";
ram_buffer(2106) := X"1040FFDF";
ram_buffer(2107) := X"24020001";
ram_buffer(2108) := X"1220FFDD";
ram_buffer(2109) := X"00000000";
ram_buffer(2110) := X"1000FFDB";
ram_buffer(2111) := X"AE220000";
ram_buffer(2112) := X"3C040100";
ram_buffer(2113) := X"2405043C";
ram_buffer(2114) := X"0C40041F";
ram_buffer(2115) := X"24847C20";
ram_buffer(2116) := X"1000FFBB";
ram_buffer(2117) := X"00000000";
ram_buffer(2118) := X"27BDFFC0";
ram_buffer(2119) := X"AFB50030";
ram_buffer(2120) := X"AFB4002C";
ram_buffer(2121) := X"AFB0001C";
ram_buffer(2122) := X"AFBF003C";
ram_buffer(2123) := X"AFB70038";
ram_buffer(2124) := X"AFB60034";
ram_buffer(2125) := X"AFB30028";
ram_buffer(2126) := X"AFB20024";
ram_buffer(2127) := X"AFB10020";
ram_buffer(2128) := X"00808025";
ram_buffer(2129) := X"00A0A025";
ram_buffer(2130) := X"AFA60048";
ram_buffer(2131) := X"10800191";
ram_buffer(2132) := X"00E0A825";
ram_buffer(2133) := X"12800186";
ram_buffer(2134) := X"00000000";
ram_buffer(2135) := X"0C40190C";
ram_buffer(2136) := X"00000000";
ram_buffer(2137) := X"14400005";
ram_buffer(2138) := X"00000000";
ram_buffer(2139) := X"8FA20048";
ram_buffer(2140) := X"00000000";
ram_buffer(2141) := X"1440015B";
ram_buffer(2142) := X"3C040100";
ram_buffer(2143) := X"0C401997";
ram_buffer(2144) := X"00000000";
ram_buffer(2145) := X"8E160038";
ram_buffer(2146) := X"0000B825";
ram_buffer(2147) := X"2413FFFF";
ram_buffer(2148) := X"26110024";
ram_buffer(2149) := X"16C00073";
ram_buffer(2150) := X"26120010";
ram_buffer(2151) := X"8FA20048";
ram_buffer(2152) := X"00000000";
ram_buffer(2153) := X"10400141";
ram_buffer(2154) := X"00000000";
ram_buffer(2155) := X"12E00127";
ram_buffer(2156) := X"00000000";
ram_buffer(2157) := X"0C4019A9";
ram_buffer(2158) := X"00000000";
ram_buffer(2159) := X"0C4010EF";
ram_buffer(2160) := X"00000000";
ram_buffer(2161) := X"0C401997";
ram_buffer(2162) := X"00000000";
ram_buffer(2163) := X"92020044";
ram_buffer(2164) := X"00000000";
ram_buffer(2165) := X"00021600";
ram_buffer(2166) := X"00021603";
ram_buffer(2167) := X"10530129";
ram_buffer(2168) := X"00000000";
ram_buffer(2169) := X"92020045";
ram_buffer(2170) := X"00000000";
ram_buffer(2171) := X"00021600";
ram_buffer(2172) := X"00021603";
ram_buffer(2173) := X"1053012A";
ram_buffer(2174) := X"00000000";
ram_buffer(2175) := X"0C4019A9";
ram_buffer(2176) := X"00000000";
ram_buffer(2177) := X"27A50048";
ram_buffer(2178) := X"0C401884";
ram_buffer(2179) := X"27A40010";
ram_buffer(2180) := X"1440006D";
ram_buffer(2181) := X"00000000";
ram_buffer(2182) := X"0C401997";
ram_buffer(2183) := X"00000000";
ram_buffer(2184) := X"8E020038";
ram_buffer(2185) := X"00000000";
ram_buffer(2186) := X"104000B5";
ram_buffer(2187) := X"00000000";
ram_buffer(2188) := X"0C4019A9";
ram_buffer(2189) := X"00000000";
ram_buffer(2190) := X"0C401997";
ram_buffer(2191) := X"00000000";
ram_buffer(2192) := X"92020045";
ram_buffer(2193) := X"00000000";
ram_buffer(2194) := X"0002B600";
ram_buffer(2195) := X"0016B603";
ram_buffer(2196) := X"1EC00007";
ram_buffer(2197) := X"2402FFFF";
ram_buffer(2198) := X"10000015";
ram_buffer(2199) := X"00000000";
ram_buffer(2200) := X"304200FF";
ram_buffer(2201) := X"0002B600";
ram_buffer(2202) := X"10400010";
ram_buffer(2203) := X"0016B603";
ram_buffer(2204) := X"8E020024";
ram_buffer(2205) := X"00000000";
ram_buffer(2206) := X"1040000D";
ram_buffer(2207) := X"2402FFFF";
ram_buffer(2208) := X"0C4017E2";
ram_buffer(2209) := X"02202025";
ram_buffer(2210) := X"1040FFF5";
ram_buffer(2211) := X"26C2FFFF";
ram_buffer(2212) := X"0C4018EE";
ram_buffer(2213) := X"00000000";
ram_buffer(2214) := X"26C2FFFF";
ram_buffer(2215) := X"304200FF";
ram_buffer(2216) := X"0002B600";
ram_buffer(2217) := X"1440FFF2";
ram_buffer(2218) := X"0016B603";
ram_buffer(2219) := X"2402FFFF";
ram_buffer(2220) := X"A2020045";
ram_buffer(2221) := X"0C4019A9";
ram_buffer(2222) := X"00000000";
ram_buffer(2223) := X"0C401997";
ram_buffer(2224) := X"00000000";
ram_buffer(2225) := X"92020044";
ram_buffer(2226) := X"00000000";
ram_buffer(2227) := X"0002B600";
ram_buffer(2228) := X"0016B603";
ram_buffer(2229) := X"1EC00007";
ram_buffer(2230) := X"2402FFFF";
ram_buffer(2231) := X"10000015";
ram_buffer(2232) := X"00000000";
ram_buffer(2233) := X"304200FF";
ram_buffer(2234) := X"0002B600";
ram_buffer(2235) := X"10400010";
ram_buffer(2236) := X"0016B603";
ram_buffer(2237) := X"8E020010";
ram_buffer(2238) := X"00000000";
ram_buffer(2239) := X"1040000D";
ram_buffer(2240) := X"2402FFFF";
ram_buffer(2241) := X"0C4017E2";
ram_buffer(2242) := X"02402025";
ram_buffer(2243) := X"1040FFF5";
ram_buffer(2244) := X"26C2FFFF";
ram_buffer(2245) := X"0C4018EE";
ram_buffer(2246) := X"00000000";
ram_buffer(2247) := X"26C2FFFF";
ram_buffer(2248) := X"304200FF";
ram_buffer(2249) := X"0002B600";
ram_buffer(2250) := X"1440FFF2";
ram_buffer(2251) := X"0016B603";
ram_buffer(2252) := X"2402FFFF";
ram_buffer(2253) := X"A2020044";
ram_buffer(2254) := X"0C4019A9";
ram_buffer(2255) := X"00000000";
ram_buffer(2256) := X"0C4011C5";
ram_buffer(2257) := X"00000000";
ram_buffer(2258) := X"24170001";
ram_buffer(2259) := X"0C401997";
ram_buffer(2260) := X"00000000";
ram_buffer(2261) := X"8E160038";
ram_buffer(2262) := X"00000000";
ram_buffer(2263) := X"12C0FF8F";
ram_buffer(2264) := X"00000000";
ram_buffer(2265) := X"8E060040";
ram_buffer(2266) := X"8E11000C";
ram_buffer(2267) := X"10C00008";
ram_buffer(2268) := X"02262821";
ram_buffer(2269) := X"8E020004";
ram_buffer(2270) := X"00000000";
ram_buffer(2271) := X"00A2102B";
ram_buffer(2272) := X"104000F2";
ram_buffer(2273) := X"AE05000C";
ram_buffer(2274) := X"0C401DD6";
ram_buffer(2275) := X"02802025";
ram_buffer(2276) := X"16A000E2";
ram_buffer(2277) := X"26D6FFFF";
ram_buffer(2278) := X"8E020000";
ram_buffer(2279) := X"AE160038";
ram_buffer(2280) := X"10400102";
ram_buffer(2281) := X"00000000";
ram_buffer(2282) := X"8E020010";
ram_buffer(2283) := X"00000000";
ram_buffer(2284) := X"144000E9";
ram_buffer(2285) := X"00000000";
ram_buffer(2286) := X"0C4019A9";
ram_buffer(2287) := X"00000000";
ram_buffer(2288) := X"100000BD";
ram_buffer(2289) := X"24020001";
ram_buffer(2290) := X"0C401997";
ram_buffer(2291) := X"00000000";
ram_buffer(2292) := X"92020045";
ram_buffer(2293) := X"00000000";
ram_buffer(2294) := X"0002B600";
ram_buffer(2295) := X"0016B603";
ram_buffer(2296) := X"1EC00007";
ram_buffer(2297) := X"2402FFFF";
ram_buffer(2298) := X"10000015";
ram_buffer(2299) := X"00000000";
ram_buffer(2300) := X"304200FF";
ram_buffer(2301) := X"0002B600";
ram_buffer(2302) := X"10400010";
ram_buffer(2303) := X"0016B603";
ram_buffer(2304) := X"8E020024";
ram_buffer(2305) := X"00000000";
ram_buffer(2306) := X"1040000D";
ram_buffer(2307) := X"2402FFFF";
ram_buffer(2308) := X"0C4017E2";
ram_buffer(2309) := X"02202025";
ram_buffer(2310) := X"1040FFF5";
ram_buffer(2311) := X"26C2FFFF";
ram_buffer(2312) := X"0C4018EE";
ram_buffer(2313) := X"00000000";
ram_buffer(2314) := X"26C2FFFF";
ram_buffer(2315) := X"304200FF";
ram_buffer(2316) := X"0002B600";
ram_buffer(2317) := X"1440FFF2";
ram_buffer(2318) := X"0016B603";
ram_buffer(2319) := X"2402FFFF";
ram_buffer(2320) := X"A2020045";
ram_buffer(2321) := X"0C4019A9";
ram_buffer(2322) := X"00000000";
ram_buffer(2323) := X"0C401997";
ram_buffer(2324) := X"00000000";
ram_buffer(2325) := X"92020044";
ram_buffer(2326) := X"00000000";
ram_buffer(2327) := X"0002B600";
ram_buffer(2328) := X"0016B603";
ram_buffer(2329) := X"1EC00007";
ram_buffer(2330) := X"2402FFFF";
ram_buffer(2331) := X"10000015";
ram_buffer(2332) := X"00000000";
ram_buffer(2333) := X"304200FF";
ram_buffer(2334) := X"0002B600";
ram_buffer(2335) := X"10400010";
ram_buffer(2336) := X"0016B603";
ram_buffer(2337) := X"8E020010";
ram_buffer(2338) := X"00000000";
ram_buffer(2339) := X"1040000D";
ram_buffer(2340) := X"2402FFFF";
ram_buffer(2341) := X"0C4017E2";
ram_buffer(2342) := X"02402025";
ram_buffer(2343) := X"1040FFF5";
ram_buffer(2344) := X"26C2FFFF";
ram_buffer(2345) := X"0C4018EE";
ram_buffer(2346) := X"00000000";
ram_buffer(2347) := X"26C2FFFF";
ram_buffer(2348) := X"304200FF";
ram_buffer(2349) := X"0002B600";
ram_buffer(2350) := X"1440FFF2";
ram_buffer(2351) := X"0016B603";
ram_buffer(2352) := X"2402FFFF";
ram_buffer(2353) := X"A2020044";
ram_buffer(2354) := X"0C4019A9";
ram_buffer(2355) := X"00000000";
ram_buffer(2356) := X"0C4011C5";
ram_buffer(2357) := X"00000000";
ram_buffer(2358) := X"0C401997";
ram_buffer(2359) := X"00000000";
ram_buffer(2360) := X"8E020038";
ram_buffer(2361) := X"00000000";
ram_buffer(2362) := X"10400070";
ram_buffer(2363) := X"00000000";
ram_buffer(2364) := X"0C4019A9";
ram_buffer(2365) := X"24170001";
ram_buffer(2366) := X"1000FF94";
ram_buffer(2367) := X"00000000";
ram_buffer(2368) := X"0C4019A9";
ram_buffer(2369) := X"00000000";
ram_buffer(2370) := X"8E020000";
ram_buffer(2371) := X"00000000";
ram_buffer(2372) := X"10400079";
ram_buffer(2373) := X"00000000";
ram_buffer(2374) := X"8FA50048";
ram_buffer(2375) := X"0C401753";
ram_buffer(2376) := X"02202025";
ram_buffer(2377) := X"0C401997";
ram_buffer(2378) := X"00000000";
ram_buffer(2379) := X"92020045";
ram_buffer(2380) := X"00000000";
ram_buffer(2381) := X"0002B600";
ram_buffer(2382) := X"0016B603";
ram_buffer(2383) := X"1EC00007";
ram_buffer(2384) := X"2402FFFF";
ram_buffer(2385) := X"10000015";
ram_buffer(2386) := X"00000000";
ram_buffer(2387) := X"304200FF";
ram_buffer(2388) := X"0002B600";
ram_buffer(2389) := X"10400010";
ram_buffer(2390) := X"0016B603";
ram_buffer(2391) := X"8E020024";
ram_buffer(2392) := X"00000000";
ram_buffer(2393) := X"1040000D";
ram_buffer(2394) := X"2402FFFF";
ram_buffer(2395) := X"0C4017E2";
ram_buffer(2396) := X"02202025";
ram_buffer(2397) := X"1040FFF5";
ram_buffer(2398) := X"26C2FFFF";
ram_buffer(2399) := X"0C4018EE";
ram_buffer(2400) := X"00000000";
ram_buffer(2401) := X"26C2FFFF";
ram_buffer(2402) := X"304200FF";
ram_buffer(2403) := X"0002B600";
ram_buffer(2404) := X"1440FFF2";
ram_buffer(2405) := X"0016B603";
ram_buffer(2406) := X"2402FFFF";
ram_buffer(2407) := X"A2020045";
ram_buffer(2408) := X"0C4019A9";
ram_buffer(2409) := X"00000000";
ram_buffer(2410) := X"0C401997";
ram_buffer(2411) := X"00000000";
ram_buffer(2412) := X"92020044";
ram_buffer(2413) := X"00000000";
ram_buffer(2414) := X"0002B600";
ram_buffer(2415) := X"0016B603";
ram_buffer(2416) := X"1EC00007";
ram_buffer(2417) := X"2402FFFF";
ram_buffer(2418) := X"10000015";
ram_buffer(2419) := X"00000000";
ram_buffer(2420) := X"304200FF";
ram_buffer(2421) := X"0002B600";
ram_buffer(2422) := X"10400010";
ram_buffer(2423) := X"0016B603";
ram_buffer(2424) := X"8E020010";
ram_buffer(2425) := X"00000000";
ram_buffer(2426) := X"1040000D";
ram_buffer(2427) := X"2402FFFF";
ram_buffer(2428) := X"0C4017E2";
ram_buffer(2429) := X"02402025";
ram_buffer(2430) := X"1040FFF5";
ram_buffer(2431) := X"26C2FFFF";
ram_buffer(2432) := X"0C4018EE";
ram_buffer(2433) := X"00000000";
ram_buffer(2434) := X"26C2FFFF";
ram_buffer(2435) := X"304200FF";
ram_buffer(2436) := X"0002B600";
ram_buffer(2437) := X"1440FFF2";
ram_buffer(2438) := X"0016B603";
ram_buffer(2439) := X"2402FFFF";
ram_buffer(2440) := X"A2020044";
ram_buffer(2441) := X"0C4019A9";
ram_buffer(2442) := X"00000000";
ram_buffer(2443) := X"0C4011C5";
ram_buffer(2444) := X"00000000";
ram_buffer(2445) := X"1440FF44";
ram_buffer(2446) := X"00000000";
ram_buffer(2447) := X"0C4001B1";
ram_buffer(2448) := X"24170001";
ram_buffer(2449) := X"1000FF41";
ram_buffer(2450) := X"00000000";
ram_buffer(2451) := X"0C40186B";
ram_buffer(2452) := X"27A40010";
ram_buffer(2453) := X"0C4019A9";
ram_buffer(2454) := X"00000000";
ram_buffer(2455) := X"0C4010EF";
ram_buffer(2456) := X"00000000";
ram_buffer(2457) := X"0C401997";
ram_buffer(2458) := X"00000000";
ram_buffer(2459) := X"92020044";
ram_buffer(2460) := X"00000000";
ram_buffer(2461) := X"00021600";
ram_buffer(2462) := X"00021603";
ram_buffer(2463) := X"1453FED9";
ram_buffer(2464) := X"00000000";
ram_buffer(2465) := X"A2000044";
ram_buffer(2466) := X"92020045";
ram_buffer(2467) := X"00000000";
ram_buffer(2468) := X"00021600";
ram_buffer(2469) := X"00021603";
ram_buffer(2470) := X"1453FED8";
ram_buffer(2471) := X"00000000";
ram_buffer(2472) := X"A2000045";
ram_buffer(2473) := X"1000FED5";
ram_buffer(2474) := X"00000000";
ram_buffer(2475) := X"0C4019A9";
ram_buffer(2476) := X"00000000";
ram_buffer(2477) := X"00001025";
ram_buffer(2478) := X"8FBF003C";
ram_buffer(2479) := X"8FB70038";
ram_buffer(2480) := X"8FB60034";
ram_buffer(2481) := X"8FB50030";
ram_buffer(2482) := X"8FB4002C";
ram_buffer(2483) := X"8FB30028";
ram_buffer(2484) := X"8FB20024";
ram_buffer(2485) := X"8FB10020";
ram_buffer(2486) := X"8FB0001C";
ram_buffer(2487) := X"03E00008";
ram_buffer(2488) := X"27BD0040";
ram_buffer(2489) := X"240504E0";
ram_buffer(2490) := X"0C40041F";
ram_buffer(2491) := X"24847C20";
ram_buffer(2492) := X"1000FEA2";
ram_buffer(2493) := X"00000000";
ram_buffer(2494) := X"0C401997";
ram_buffer(2495) := X"00000000";
ram_buffer(2496) := X"8E040004";
ram_buffer(2497) := X"0C401917";
ram_buffer(2498) := X"00000000";
ram_buffer(2499) := X"0C4019A9";
ram_buffer(2500) := X"00000000";
ram_buffer(2501) := X"1000FF80";
ram_buffer(2502) := X"00000000";
ram_buffer(2503) := X"8E020024";
ram_buffer(2504) := X"00000000";
ram_buffer(2505) := X"1040FF24";
ram_buffer(2506) := X"AE11000C";
ram_buffer(2507) := X"0C4017E2";
ram_buffer(2508) := X"26040024";
ram_buffer(2509) := X"1040FF20";
ram_buffer(2510) := X"00000000";
ram_buffer(2511) := X"0C4001B1";
ram_buffer(2512) := X"00000000";
ram_buffer(2513) := X"1000FF1C";
ram_buffer(2514) := X"00000000";
ram_buffer(2515) := X"8E050000";
ram_buffer(2516) := X"1000FF0D";
ram_buffer(2517) := X"AE05000C";
ram_buffer(2518) := X"0C4017E2";
ram_buffer(2519) := X"26040010";
ram_buffer(2520) := X"1040FF15";
ram_buffer(2521) := X"00000000";
ram_buffer(2522) := X"1000FFF4";
ram_buffer(2523) := X"00000000";
ram_buffer(2524) := X"8E020040";
ram_buffer(2525) := X"00000000";
ram_buffer(2526) := X"1040FE78";
ram_buffer(2527) := X"3C040100";
ram_buffer(2528) := X"240504DD";
ram_buffer(2529) := X"0C40041F";
ram_buffer(2530) := X"24847C20";
ram_buffer(2531) := X"1000FE73";
ram_buffer(2532) := X"00000000";
ram_buffer(2533) := X"3C040100";
ram_buffer(2534) := X"240504DC";
ram_buffer(2535) := X"0C40041F";
ram_buffer(2536) := X"24847C20";
ram_buffer(2537) := X"1000FE6B";
ram_buffer(2538) := X"00000000";
ram_buffer(2539) := X"0C4019CA";
ram_buffer(2540) := X"00000000";
ram_buffer(2541) := X"1000FEFC";
ram_buffer(2542) := X"AE020004";
ram_buffer(2543) := X"27BDFFE0";
ram_buffer(2544) := X"AFB20018";
ram_buffer(2545) := X"AFB00010";
ram_buffer(2546) := X"AFBF001C";
ram_buffer(2547) := X"AFB10014";
ram_buffer(2548) := X"00808025";
ram_buffer(2549) := X"10800020";
ram_buffer(2550) := X"00A09025";
ram_buffer(2551) := X"8E110004";
ram_buffer(2552) := X"0C401909";
ram_buffer(2553) := X"00000000";
ram_buffer(2554) := X"12220011";
ram_buffer(2555) := X"00003825";
ram_buffer(2556) := X"02403025";
ram_buffer(2557) := X"00002825";
ram_buffer(2558) := X"0C400846";
ram_buffer(2559) := X"02002025";
ram_buffer(2560) := X"10400005";
ram_buffer(2561) := X"00000000";
ram_buffer(2562) := X"8E03000C";
ram_buffer(2563) := X"00000000";
ram_buffer(2564) := X"24630001";
ram_buffer(2565) := X"AE03000C";
ram_buffer(2566) := X"8FBF001C";
ram_buffer(2567) := X"8FB20018";
ram_buffer(2568) := X"8FB10014";
ram_buffer(2569) := X"8FB00010";
ram_buffer(2570) := X"03E00008";
ram_buffer(2571) := X"27BD0020";
ram_buffer(2572) := X"8E03000C";
ram_buffer(2573) := X"24020001";
ram_buffer(2574) := X"24630001";
ram_buffer(2575) := X"AE03000C";
ram_buffer(2576) := X"8FBF001C";
ram_buffer(2577) := X"8FB20018";
ram_buffer(2578) := X"8FB10014";
ram_buffer(2579) := X"8FB00010";
ram_buffer(2580) := X"03E00008";
ram_buffer(2581) := X"27BD0020";
ram_buffer(2582) := X"3C040100";
ram_buffer(2583) := X"24050278";
ram_buffer(2584) := X"0C40041F";
ram_buffer(2585) := X"24847C20";
ram_buffer(2586) := X"1000FFDC";
ram_buffer(2587) := X"00000000";
ram_buffer(2588) := X"27BDFFD8";
ram_buffer(2589) := X"AFB40020";
ram_buffer(2590) := X"AFB3001C";
ram_buffer(2591) := X"AFB00010";
ram_buffer(2592) := X"AFBF0024";
ram_buffer(2593) := X"AFB20018";
ram_buffer(2594) := X"AFB10014";
ram_buffer(2595) := X"00808025";
ram_buffer(2596) := X"00A09825";
ram_buffer(2597) := X"1080004E";
ram_buffer(2598) := X"00C0A025";
ram_buffer(2599) := X"1260002E";
ram_buffer(2600) := X"00000000";
ram_buffer(2601) := X"8E110038";
ram_buffer(2602) := X"00000000";
ram_buffer(2603) := X"16200009";
ram_buffer(2604) := X"00001025";
ram_buffer(2605) := X"8FBF0024";
ram_buffer(2606) := X"8FB40020";
ram_buffer(2607) := X"8FB3001C";
ram_buffer(2608) := X"8FB20018";
ram_buffer(2609) := X"8FB10014";
ram_buffer(2610) := X"8FB00010";
ram_buffer(2611) := X"03E00008";
ram_buffer(2612) := X"27BD0028";
ram_buffer(2613) := X"92120044";
ram_buffer(2614) := X"8E060040";
ram_buffer(2615) := X"00129600";
ram_buffer(2616) := X"10C00009";
ram_buffer(2617) := X"00129603";
ram_buffer(2618) := X"8E05000C";
ram_buffer(2619) := X"8E020004";
ram_buffer(2620) := X"00A62821";
ram_buffer(2621) := X"00A2102B";
ram_buffer(2622) := X"10400014";
ram_buffer(2623) := X"AE05000C";
ram_buffer(2624) := X"0C401DD6";
ram_buffer(2625) := X"02602025";
ram_buffer(2626) := X"2631FFFF";
ram_buffer(2627) := X"2402FFFF";
ram_buffer(2628) := X"AE110038";
ram_buffer(2629) := X"12420022";
ram_buffer(2630) := X"26520001";
ram_buffer(2631) := X"00129600";
ram_buffer(2632) := X"00129603";
ram_buffer(2633) := X"A2120044";
ram_buffer(2634) := X"8FBF0024";
ram_buffer(2635) := X"8FB40020";
ram_buffer(2636) := X"8FB3001C";
ram_buffer(2637) := X"8FB20018";
ram_buffer(2638) := X"8FB10014";
ram_buffer(2639) := X"8FB00010";
ram_buffer(2640) := X"24020001";
ram_buffer(2641) := X"03E00008";
ram_buffer(2642) := X"27BD0028";
ram_buffer(2643) := X"8E050000";
ram_buffer(2644) := X"1000FFEB";
ram_buffer(2645) := X"AE05000C";
ram_buffer(2646) := X"8E020040";
ram_buffer(2647) := X"00000000";
ram_buffer(2648) := X"1440000A";
ram_buffer(2649) := X"3C040100";
ram_buffer(2650) := X"8E110038";
ram_buffer(2651) := X"00000000";
ram_buffer(2652) := X"1220FFD0";
ram_buffer(2653) := X"00001025";
ram_buffer(2654) := X"92120044";
ram_buffer(2655) := X"00000000";
ram_buffer(2656) := X"00129600";
ram_buffer(2657) := X"1000FFE0";
ram_buffer(2658) := X"00129603";
ram_buffer(2659) := X"240505A1";
ram_buffer(2660) := X"0C40041F";
ram_buffer(2661) := X"24847C20";
ram_buffer(2662) := X"1000FFC2";
ram_buffer(2663) := X"00000000";
ram_buffer(2664) := X"8E020010";
ram_buffer(2665) := X"00000000";
ram_buffer(2666) := X"1040FFDF";
ram_buffer(2667) := X"00000000";
ram_buffer(2668) := X"0C4017E2";
ram_buffer(2669) := X"26040010";
ram_buffer(2670) := X"1040FFDB";
ram_buffer(2671) := X"00000000";
ram_buffer(2672) := X"1280FFD9";
ram_buffer(2673) := X"24020001";
ram_buffer(2674) := X"1000FFBA";
ram_buffer(2675) := X"AE820000";
ram_buffer(2676) := X"3C040100";
ram_buffer(2677) := X"240505A0";
ram_buffer(2678) := X"0C40041F";
ram_buffer(2679) := X"24847C20";
ram_buffer(2680) := X"1000FFAE";
ram_buffer(2681) := X"00000000";
ram_buffer(2682) := X"27BDFFE0";
ram_buffer(2683) := X"AFB10014";
ram_buffer(2684) := X"AFB00010";
ram_buffer(2685) := X"AFBF001C";
ram_buffer(2686) := X"AFB20018";
ram_buffer(2687) := X"00808025";
ram_buffer(2688) := X"1080003C";
ram_buffer(2689) := X"00A08825";
ram_buffer(2690) := X"12200031";
ram_buffer(2691) := X"00000000";
ram_buffer(2692) := X"8E060040";
ram_buffer(2693) := X"00000000";
ram_buffer(2694) := X"10C00020";
ram_buffer(2695) := X"3C040100";
ram_buffer(2696) := X"8E020038";
ram_buffer(2697) := X"00000000";
ram_buffer(2698) := X"14400008";
ram_buffer(2699) := X"00000000";
ram_buffer(2700) := X"8FBF001C";
ram_buffer(2701) := X"8FB20018";
ram_buffer(2702) := X"8FB10014";
ram_buffer(2703) := X"8FB00010";
ram_buffer(2704) := X"00001025";
ram_buffer(2705) := X"03E00008";
ram_buffer(2706) := X"27BD0020";
ram_buffer(2707) := X"8E12000C";
ram_buffer(2708) := X"8E020004";
ram_buffer(2709) := X"02462821";
ram_buffer(2710) := X"00A2102B";
ram_buffer(2711) := X"14400004";
ram_buffer(2712) := X"AE05000C";
ram_buffer(2713) := X"8E050000";
ram_buffer(2714) := X"00000000";
ram_buffer(2715) := X"AE05000C";
ram_buffer(2716) := X"0C401DD6";
ram_buffer(2717) := X"02202025";
ram_buffer(2718) := X"AE12000C";
ram_buffer(2719) := X"24020001";
ram_buffer(2720) := X"8FBF001C";
ram_buffer(2721) := X"8FB20018";
ram_buffer(2722) := X"8FB10014";
ram_buffer(2723) := X"8FB00010";
ram_buffer(2724) := X"03E00008";
ram_buffer(2725) := X"27BD0020";
ram_buffer(2726) := X"3C040100";
ram_buffer(2727) := X"240505FE";
ram_buffer(2728) := X"0C40041F";
ram_buffer(2729) := X"24847C20";
ram_buffer(2730) := X"8E020038";
ram_buffer(2731) := X"00000000";
ram_buffer(2732) := X"1040FFDF";
ram_buffer(2733) := X"00000000";
ram_buffer(2734) := X"8E060040";
ram_buffer(2735) := X"8E12000C";
ram_buffer(2736) := X"14C0FFE3";
ram_buffer(2737) := X"24020001";
ram_buffer(2738) := X"1000FFED";
ram_buffer(2739) := X"AE12000C";
ram_buffer(2740) := X"8E020040";
ram_buffer(2741) := X"00000000";
ram_buffer(2742) := X"1040FFEF";
ram_buffer(2743) := X"240505FD";
ram_buffer(2744) := X"3C040100";
ram_buffer(2745) := X"0C40041F";
ram_buffer(2746) := X"24847C20";
ram_buffer(2747) := X"1000FFC8";
ram_buffer(2748) := X"00000000";
ram_buffer(2749) := X"3C040100";
ram_buffer(2750) := X"240505FC";
ram_buffer(2751) := X"0C40041F";
ram_buffer(2752) := X"24847C20";
ram_buffer(2753) := X"1000FFC0";
ram_buffer(2754) := X"00000000";
ram_buffer(2755) := X"27BDFFE8";
ram_buffer(2756) := X"AFB00010";
ram_buffer(2757) := X"AFBF0014";
ram_buffer(2758) := X"1080000B";
ram_buffer(2759) := X"00808025";
ram_buffer(2760) := X"0C401997";
ram_buffer(2761) := X"00000000";
ram_buffer(2762) := X"8E100038";
ram_buffer(2763) := X"0C4019A9";
ram_buffer(2764) := X"00000000";
ram_buffer(2765) := X"8FBF0014";
ram_buffer(2766) := X"02001025";
ram_buffer(2767) := X"8FB00010";
ram_buffer(2768) := X"03E00008";
ram_buffer(2769) := X"27BD0018";
ram_buffer(2770) := X"3C040100";
ram_buffer(2771) := X"2405062F";
ram_buffer(2772) := X"0C40041F";
ram_buffer(2773) := X"24847C20";
ram_buffer(2774) := X"0C401997";
ram_buffer(2775) := X"00000000";
ram_buffer(2776) := X"8E100038";
ram_buffer(2777) := X"0C4019A9";
ram_buffer(2778) := X"00000000";
ram_buffer(2779) := X"8FBF0014";
ram_buffer(2780) := X"02001025";
ram_buffer(2781) := X"8FB00010";
ram_buffer(2782) := X"03E00008";
ram_buffer(2783) := X"27BD0018";
ram_buffer(2784) := X"27BDFFE0";
ram_buffer(2785) := X"AFB10018";
ram_buffer(2786) := X"AFBF001C";
ram_buffer(2787) := X"AFB00014";
ram_buffer(2788) := X"1080000D";
ram_buffer(2789) := X"00808825";
ram_buffer(2790) := X"0C401997";
ram_buffer(2791) := X"00000000";
ram_buffer(2792) := X"8E220038";
ram_buffer(2793) := X"8E30003C";
ram_buffer(2794) := X"0C4019A9";
ram_buffer(2795) := X"02028023";
ram_buffer(2796) := X"8FBF001C";
ram_buffer(2797) := X"02001025";
ram_buffer(2798) := X"8FB10018";
ram_buffer(2799) := X"8FB00014";
ram_buffer(2800) := X"03E00008";
ram_buffer(2801) := X"27BD0020";
ram_buffer(2802) := X"3C040100";
ram_buffer(2803) := X"24050641";
ram_buffer(2804) := X"0C40041F";
ram_buffer(2805) := X"24847C20";
ram_buffer(2806) := X"1000FFEF";
ram_buffer(2807) := X"00000000";
ram_buffer(2808) := X"27BDFFE8";
ram_buffer(2809) := X"AFB00010";
ram_buffer(2810) := X"AFBF0014";
ram_buffer(2811) := X"10800006";
ram_buffer(2812) := X"00808025";
ram_buffer(2813) := X"8FBF0014";
ram_buffer(2814) := X"8E020038";
ram_buffer(2815) := X"8FB00010";
ram_buffer(2816) := X"03E00008";
ram_buffer(2817) := X"27BD0018";
ram_buffer(2818) := X"3C040100";
ram_buffer(2819) := X"24050651";
ram_buffer(2820) := X"0C40041F";
ram_buffer(2821) := X"24847C20";
ram_buffer(2822) := X"8FBF0014";
ram_buffer(2823) := X"8E020038";
ram_buffer(2824) := X"8FB00010";
ram_buffer(2825) := X"03E00008";
ram_buffer(2826) := X"27BD0018";
ram_buffer(2827) := X"27BDFFE8";
ram_buffer(2828) := X"AFB00010";
ram_buffer(2829) := X"AFBF0014";
ram_buffer(2830) := X"1080002F";
ram_buffer(2831) := X"00808025";
ram_buffer(2832) := X"3C020102";
ram_buffer(2833) := X"244280F4";
ram_buffer(2834) := X"8C430004";
ram_buffer(2835) := X"00000000";
ram_buffer(2836) := X"1203002F";
ram_buffer(2837) := X"00001825";
ram_buffer(2838) := X"8C43000C";
ram_buffer(2839) := X"00000000";
ram_buffer(2840) := X"1203002B";
ram_buffer(2841) := X"24030001";
ram_buffer(2842) := X"8C430014";
ram_buffer(2843) := X"00000000";
ram_buffer(2844) := X"12030027";
ram_buffer(2845) := X"24030002";
ram_buffer(2846) := X"8C43001C";
ram_buffer(2847) := X"00000000";
ram_buffer(2848) := X"12030023";
ram_buffer(2849) := X"24030003";
ram_buffer(2850) := X"8C430024";
ram_buffer(2851) := X"00000000";
ram_buffer(2852) := X"1203001F";
ram_buffer(2853) := X"24030004";
ram_buffer(2854) := X"8C43002C";
ram_buffer(2855) := X"00000000";
ram_buffer(2856) := X"1203001B";
ram_buffer(2857) := X"24030005";
ram_buffer(2858) := X"8C430034";
ram_buffer(2859) := X"00000000";
ram_buffer(2860) := X"12030017";
ram_buffer(2861) := X"24030006";
ram_buffer(2862) := X"8C43003C";
ram_buffer(2863) := X"00000000";
ram_buffer(2864) := X"12030013";
ram_buffer(2865) := X"24030007";
ram_buffer(2866) := X"8C430044";
ram_buffer(2867) := X"00000000";
ram_buffer(2868) := X"1203000F";
ram_buffer(2869) := X"24030008";
ram_buffer(2870) := X"8C43004C";
ram_buffer(2871) := X"00000000";
ram_buffer(2872) := X"1203001C";
ram_buffer(2873) := X"02002025";
ram_buffer(2874) := X"8FBF0014";
ram_buffer(2875) := X"8FB00010";
ram_buffer(2876) := X"08401D6D";
ram_buffer(2877) := X"27BD0018";
ram_buffer(2878) := X"3C040100";
ram_buffer(2879) := X"2405065D";
ram_buffer(2880) := X"0C40041F";
ram_buffer(2881) := X"24847C20";
ram_buffer(2882) := X"1000FFCE";
ram_buffer(2883) := X"3C020102";
ram_buffer(2884) := X"000318C0";
ram_buffer(2885) := X"00431021";
ram_buffer(2886) := X"8FBF0014";
ram_buffer(2887) := X"02002025";
ram_buffer(2888) := X"8FB00010";
ram_buffer(2889) := X"AC400000";
ram_buffer(2890) := X"AC400004";
ram_buffer(2891) := X"08401D6D";
ram_buffer(2892) := X"27BD0018";
ram_buffer(2893) := X"1000FFF6";
ram_buffer(2894) := X"24030002";
ram_buffer(2895) := X"1000FFF4";
ram_buffer(2896) := X"24030004";
ram_buffer(2897) := X"1000FFF2";
ram_buffer(2898) := X"24030006";
ram_buffer(2899) := X"1000FFF0";
ram_buffer(2900) := X"24030008";
ram_buffer(2901) := X"1000FFEE";
ram_buffer(2902) := X"24030009";
ram_buffer(2903) := X"27BDFFE8";
ram_buffer(2904) := X"AFB00010";
ram_buffer(2905) := X"AFBF0014";
ram_buffer(2906) := X"10800007";
ram_buffer(2907) := X"00808025";
ram_buffer(2908) := X"8E020038";
ram_buffer(2909) := X"8FBF0014";
ram_buffer(2910) := X"8FB00010";
ram_buffer(2911) := X"2C420001";
ram_buffer(2912) := X"03E00008";
ram_buffer(2913) := X"27BD0018";
ram_buffer(2914) := X"3C040100";
ram_buffer(2915) := X"24050793";
ram_buffer(2916) := X"0C40041F";
ram_buffer(2917) := X"24847C20";
ram_buffer(2918) := X"1000FFF5";
ram_buffer(2919) := X"00000000";
ram_buffer(2920) := X"27BDFFE8";
ram_buffer(2921) := X"AFB00010";
ram_buffer(2922) := X"AFBF0014";
ram_buffer(2923) := X"10800009";
ram_buffer(2924) := X"00808025";
ram_buffer(2925) := X"8E030038";
ram_buffer(2926) := X"8E02003C";
ram_buffer(2927) := X"8FBF0014";
ram_buffer(2928) := X"00431026";
ram_buffer(2929) := X"8FB00010";
ram_buffer(2930) := X"2C420001";
ram_buffer(2931) := X"03E00008";
ram_buffer(2932) := X"27BD0018";
ram_buffer(2933) := X"3C040100";
ram_buffer(2934) := X"240507BA";
ram_buffer(2935) := X"0C40041F";
ram_buffer(2936) := X"24847C20";
ram_buffer(2937) := X"1000FFF3";
ram_buffer(2938) := X"00000000";
ram_buffer(2939) := X"3C020102";
ram_buffer(2940) := X"8C4380F4";
ram_buffer(2941) := X"00000000";
ram_buffer(2942) := X"1060002E";
ram_buffer(2943) := X"00001825";
ram_buffer(2944) := X"244280F4";
ram_buffer(2945) := X"8C430008";
ram_buffer(2946) := X"00000000";
ram_buffer(2947) := X"10600024";
ram_buffer(2948) := X"24030001";
ram_buffer(2949) := X"8C430010";
ram_buffer(2950) := X"00000000";
ram_buffer(2951) := X"10600020";
ram_buffer(2952) := X"24030002";
ram_buffer(2953) := X"8C430018";
ram_buffer(2954) := X"00000000";
ram_buffer(2955) := X"1060001C";
ram_buffer(2956) := X"24030003";
ram_buffer(2957) := X"8C430020";
ram_buffer(2958) := X"00000000";
ram_buffer(2959) := X"10600018";
ram_buffer(2960) := X"24030004";
ram_buffer(2961) := X"8C430028";
ram_buffer(2962) := X"00000000";
ram_buffer(2963) := X"10600014";
ram_buffer(2964) := X"24030005";
ram_buffer(2965) := X"8C430030";
ram_buffer(2966) := X"00000000";
ram_buffer(2967) := X"10600010";
ram_buffer(2968) := X"24030006";
ram_buffer(2969) := X"8C430038";
ram_buffer(2970) := X"00000000";
ram_buffer(2971) := X"1060000C";
ram_buffer(2972) := X"24030007";
ram_buffer(2973) := X"8C430040";
ram_buffer(2974) := X"00000000";
ram_buffer(2975) := X"10600008";
ram_buffer(2976) := X"24030008";
ram_buffer(2977) := X"8C430048";
ram_buffer(2978) := X"00000000";
ram_buffer(2979) := X"10600003";
ram_buffer(2980) := X"00000000";
ram_buffer(2981) := X"03E00008";
ram_buffer(2982) := X"00000000";
ram_buffer(2983) := X"24030009";
ram_buffer(2984) := X"000318C0";
ram_buffer(2985) := X"00431021";
ram_buffer(2986) := X"AC450000";
ram_buffer(2987) := X"03E00008";
ram_buffer(2988) := X"AC440004";
ram_buffer(2989) := X"1000FFFA";
ram_buffer(2990) := X"244280F4";
ram_buffer(2991) := X"1000FFF8";
ram_buffer(2992) := X"24030002";
ram_buffer(2993) := X"1000FFF6";
ram_buffer(2994) := X"24030004";
ram_buffer(2995) := X"1000FFF4";
ram_buffer(2996) := X"24030006";
ram_buffer(2997) := X"1000FFF2";
ram_buffer(2998) := X"24030008";
ram_buffer(2999) := X"3C030102";
ram_buffer(3000) := X"246380F4";
ram_buffer(3001) := X"8C620004";
ram_buffer(3002) := X"00000000";
ram_buffer(3003) := X"10820026";
ram_buffer(3004) := X"00001025";
ram_buffer(3005) := X"8C62000C";
ram_buffer(3006) := X"00000000";
ram_buffer(3007) := X"10820022";
ram_buffer(3008) := X"24020001";
ram_buffer(3009) := X"8C620014";
ram_buffer(3010) := X"00000000";
ram_buffer(3011) := X"1082001E";
ram_buffer(3012) := X"24020002";
ram_buffer(3013) := X"8C62001C";
ram_buffer(3014) := X"00000000";
ram_buffer(3015) := X"1082001A";
ram_buffer(3016) := X"24020003";
ram_buffer(3017) := X"8C620024";
ram_buffer(3018) := X"00000000";
ram_buffer(3019) := X"10820016";
ram_buffer(3020) := X"24020004";
ram_buffer(3021) := X"8C62002C";
ram_buffer(3022) := X"00000000";
ram_buffer(3023) := X"10820012";
ram_buffer(3024) := X"24020005";
ram_buffer(3025) := X"8C620034";
ram_buffer(3026) := X"00000000";
ram_buffer(3027) := X"1082000E";
ram_buffer(3028) := X"24020006";
ram_buffer(3029) := X"8C62003C";
ram_buffer(3030) := X"00000000";
ram_buffer(3031) := X"1082000A";
ram_buffer(3032) := X"24020007";
ram_buffer(3033) := X"8C620044";
ram_buffer(3034) := X"00000000";
ram_buffer(3035) := X"10820013";
ram_buffer(3036) := X"00000000";
ram_buffer(3037) := X"8C65004C";
ram_buffer(3038) := X"00000000";
ram_buffer(3039) := X"14A40005";
ram_buffer(3040) := X"00001025";
ram_buffer(3041) := X"24020009";
ram_buffer(3042) := X"000210C0";
ram_buffer(3043) := X"00621821";
ram_buffer(3044) := X"8C620000";
ram_buffer(3045) := X"03E00008";
ram_buffer(3046) := X"00000000";
ram_buffer(3047) := X"1000FFFA";
ram_buffer(3048) := X"24020001";
ram_buffer(3049) := X"1000FFF8";
ram_buffer(3050) := X"24020003";
ram_buffer(3051) := X"1000FFF6";
ram_buffer(3052) := X"24020005";
ram_buffer(3053) := X"1000FFF4";
ram_buffer(3054) := X"24020007";
ram_buffer(3055) := X"1000FFF2";
ram_buffer(3056) := X"24020008";
ram_buffer(3057) := X"3C020102";
ram_buffer(3058) := X"244280F4";
ram_buffer(3059) := X"8C430004";
ram_buffer(3060) := X"00000000";
ram_buffer(3061) := X"10830028";
ram_buffer(3062) := X"00001825";
ram_buffer(3063) := X"8C43000C";
ram_buffer(3064) := X"00000000";
ram_buffer(3065) := X"10830024";
ram_buffer(3066) := X"24030001";
ram_buffer(3067) := X"8C430014";
ram_buffer(3068) := X"00000000";
ram_buffer(3069) := X"10830020";
ram_buffer(3070) := X"24030002";
ram_buffer(3071) := X"8C43001C";
ram_buffer(3072) := X"00000000";
ram_buffer(3073) := X"1083001C";
ram_buffer(3074) := X"24030003";
ram_buffer(3075) := X"8C430024";
ram_buffer(3076) := X"00000000";
ram_buffer(3077) := X"10830018";
ram_buffer(3078) := X"24030004";
ram_buffer(3079) := X"8C43002C";
ram_buffer(3080) := X"00000000";
ram_buffer(3081) := X"10830014";
ram_buffer(3082) := X"24030005";
ram_buffer(3083) := X"8C430034";
ram_buffer(3084) := X"00000000";
ram_buffer(3085) := X"10830010";
ram_buffer(3086) := X"24030006";
ram_buffer(3087) := X"8C43003C";
ram_buffer(3088) := X"00000000";
ram_buffer(3089) := X"1083000C";
ram_buffer(3090) := X"24030007";
ram_buffer(3091) := X"8C430044";
ram_buffer(3092) := X"00000000";
ram_buffer(3093) := X"10830008";
ram_buffer(3094) := X"24030008";
ram_buffer(3095) := X"8C43004C";
ram_buffer(3096) := X"00000000";
ram_buffer(3097) := X"10640003";
ram_buffer(3098) := X"00000000";
ram_buffer(3099) := X"03E00008";
ram_buffer(3100) := X"00000000";
ram_buffer(3101) := X"24030009";
ram_buffer(3102) := X"000318C0";
ram_buffer(3103) := X"00431021";
ram_buffer(3104) := X"AC400000";
ram_buffer(3105) := X"03E00008";
ram_buffer(3106) := X"AC400004";
ram_buffer(3107) := X"1000FFFA";
ram_buffer(3108) := X"24030001";
ram_buffer(3109) := X"1000FFF8";
ram_buffer(3110) := X"24030003";
ram_buffer(3111) := X"1000FFF6";
ram_buffer(3112) := X"24030005";
ram_buffer(3113) := X"1000FFF4";
ram_buffer(3114) := X"24030007";
ram_buffer(3115) := X"27BDFFD0";
ram_buffer(3116) := X"AFB20018";
ram_buffer(3117) := X"00069080";
ram_buffer(3118) := X"AFB40020";
ram_buffer(3119) := X"0080A025";
ram_buffer(3120) := X"02402025";
ram_buffer(3121) := X"AFB50024";
ram_buffer(3122) := X"AFB3001C";
ram_buffer(3123) := X"AFB10014";
ram_buffer(3124) := X"AFBF002C";
ram_buffer(3125) := X"AFB60028";
ram_buffer(3126) := X"AFB00010";
ram_buffer(3127) := X"00A08825";
ram_buffer(3128) := X"8FB30044";
ram_buffer(3129) := X"0C401CCF";
ram_buffer(3130) := X"00E0A825";
ram_buffer(3131) := X"104000FB";
ram_buffer(3132) := X"24040058";
ram_buffer(3133) := X"0C401CCF";
ram_buffer(3134) := X"0040B025";
ram_buffer(3135) := X"10400124";
ram_buffer(3136) := X"00408025";
ram_buffer(3137) := X"02403025";
ram_buffer(3138) := X"AC560030";
ram_buffer(3139) := X"240500A5";
ram_buffer(3140) := X"0C401EB2";
ram_buffer(3141) := X"02C02025";
ram_buffer(3142) := X"82230000";
ram_buffer(3143) := X"8E020030";
ram_buffer(3144) := X"A2030034";
ram_buffer(3145) := X"2652FFFC";
ram_buffer(3146) := X"82230000";
ram_buffer(3147) := X"00529021";
ram_buffer(3148) := X"2402FFFC";
ram_buffer(3149) := X"1060005F";
ram_buffer(3150) := X"02429024";
ram_buffer(3151) := X"82220001";
ram_buffer(3152) := X"00000000";
ram_buffer(3153) := X"A2020035";
ram_buffer(3154) := X"82220001";
ram_buffer(3155) := X"00000000";
ram_buffer(3156) := X"10400058";
ram_buffer(3157) := X"00000000";
ram_buffer(3158) := X"82220002";
ram_buffer(3159) := X"00000000";
ram_buffer(3160) := X"A2020036";
ram_buffer(3161) := X"82220002";
ram_buffer(3162) := X"00000000";
ram_buffer(3163) := X"10400051";
ram_buffer(3164) := X"00000000";
ram_buffer(3165) := X"82220003";
ram_buffer(3166) := X"00000000";
ram_buffer(3167) := X"A2020037";
ram_buffer(3168) := X"82220003";
ram_buffer(3169) := X"00000000";
ram_buffer(3170) := X"1040004A";
ram_buffer(3171) := X"00000000";
ram_buffer(3172) := X"82220004";
ram_buffer(3173) := X"00000000";
ram_buffer(3174) := X"A2020038";
ram_buffer(3175) := X"82220004";
ram_buffer(3176) := X"00000000";
ram_buffer(3177) := X"10400043";
ram_buffer(3178) := X"00000000";
ram_buffer(3179) := X"82220005";
ram_buffer(3180) := X"00000000";
ram_buffer(3181) := X"A2020039";
ram_buffer(3182) := X"82220005";
ram_buffer(3183) := X"00000000";
ram_buffer(3184) := X"1040003C";
ram_buffer(3185) := X"00000000";
ram_buffer(3186) := X"82220006";
ram_buffer(3187) := X"00000000";
ram_buffer(3188) := X"A202003A";
ram_buffer(3189) := X"82220006";
ram_buffer(3190) := X"00000000";
ram_buffer(3191) := X"10400035";
ram_buffer(3192) := X"00000000";
ram_buffer(3193) := X"82220007";
ram_buffer(3194) := X"00000000";
ram_buffer(3195) := X"A202003B";
ram_buffer(3196) := X"82220007";
ram_buffer(3197) := X"00000000";
ram_buffer(3198) := X"1040002E";
ram_buffer(3199) := X"00000000";
ram_buffer(3200) := X"82220008";
ram_buffer(3201) := X"00000000";
ram_buffer(3202) := X"A202003C";
ram_buffer(3203) := X"82220008";
ram_buffer(3204) := X"00000000";
ram_buffer(3205) := X"10400027";
ram_buffer(3206) := X"00000000";
ram_buffer(3207) := X"82220009";
ram_buffer(3208) := X"00000000";
ram_buffer(3209) := X"A202003D";
ram_buffer(3210) := X"82220009";
ram_buffer(3211) := X"00000000";
ram_buffer(3212) := X"10400020";
ram_buffer(3213) := X"00000000";
ram_buffer(3214) := X"8222000A";
ram_buffer(3215) := X"00000000";
ram_buffer(3216) := X"A202003E";
ram_buffer(3217) := X"8222000A";
ram_buffer(3218) := X"00000000";
ram_buffer(3219) := X"10400019";
ram_buffer(3220) := X"00000000";
ram_buffer(3221) := X"8222000B";
ram_buffer(3222) := X"00000000";
ram_buffer(3223) := X"A202003F";
ram_buffer(3224) := X"8222000B";
ram_buffer(3225) := X"00000000";
ram_buffer(3226) := X"10400012";
ram_buffer(3227) := X"00000000";
ram_buffer(3228) := X"8222000C";
ram_buffer(3229) := X"00000000";
ram_buffer(3230) := X"A2020040";
ram_buffer(3231) := X"8222000C";
ram_buffer(3232) := X"00000000";
ram_buffer(3233) := X"1040000B";
ram_buffer(3234) := X"00000000";
ram_buffer(3235) := X"8222000D";
ram_buffer(3236) := X"00000000";
ram_buffer(3237) := X"A2020041";
ram_buffer(3238) := X"8222000D";
ram_buffer(3239) := X"00000000";
ram_buffer(3240) := X"10400004";
ram_buffer(3241) := X"00000000";
ram_buffer(3242) := X"8222000E";
ram_buffer(3243) := X"00000000";
ram_buffer(3244) := X"A2020042";
ram_buffer(3245) := X"8FB60040";
ram_buffer(3246) := X"00000000";
ram_buffer(3247) := X"2EC20005";
ram_buffer(3248) := X"10400080";
ram_buffer(3249) := X"A2000043";
ram_buffer(3250) := X"26110004";
ram_buffer(3251) := X"02202025";
ram_buffer(3252) := X"AE16002C";
ram_buffer(3253) := X"AE160048";
ram_buffer(3254) := X"0C40043F";
ram_buffer(3255) := X"AE00004C";
ram_buffer(3256) := X"0C40043F";
ram_buffer(3257) := X"26040018";
ram_buffer(3258) := X"24020005";
ram_buffer(3259) := X"0056B023";
ram_buffer(3260) := X"AE000050";
ram_buffer(3261) := X"AE100010";
ram_buffer(3262) := X"AE160018";
ram_buffer(3263) := X"AE100024";
ram_buffer(3264) := X"AE000044";
ram_buffer(3265) := X"A2000054";
ram_buffer(3266) := X"A2000055";
ram_buffer(3267) := X"02A03025";
ram_buffer(3268) := X"02802825";
ram_buffer(3269) := X"0C400116";
ram_buffer(3270) := X"02402025";
ram_buffer(3271) := X"12600002";
ram_buffer(3272) := X"AE020000";
ram_buffer(3273) := X"AE700000";
ram_buffer(3274) := X"0C40041A";
ram_buffer(3275) := X"00000000";
ram_buffer(3276) := X"8F828030";
ram_buffer(3277) := X"00000000";
ram_buffer(3278) := X"1440006A";
ram_buffer(3279) := X"00000000";
ram_buffer(3280) := X"8F82803C";
ram_buffer(3281) := X"00000000";
ram_buffer(3282) := X"24420001";
ram_buffer(3283) := X"AF82803C";
ram_buffer(3284) := X"8F828010";
ram_buffer(3285) := X"00000000";
ram_buffer(3286) := X"10400036";
ram_buffer(3287) := X"00000000";
ram_buffer(3288) := X"8F828030";
ram_buffer(3289) := X"00000000";
ram_buffer(3290) := X"14400037";
ram_buffer(3291) := X"00000000";
ram_buffer(3292) := X"8F828010";
ram_buffer(3293) := X"8E04002C";
ram_buffer(3294) := X"8C42002C";
ram_buffer(3295) := X"00000000";
ram_buffer(3296) := X"0082102B";
ram_buffer(3297) := X"14400002";
ram_buffer(3298) := X"00000000";
ram_buffer(3299) := X"AF908010";
ram_buffer(3300) := X"8F838020";
ram_buffer(3301) := X"8F828034";
ram_buffer(3302) := X"24630001";
ram_buffer(3303) := X"0044102B";
ram_buffer(3304) := X"3C120100";
ram_buffer(3305) := X"10400002";
ram_buffer(3306) := X"AF838020";
ram_buffer(3307) := X"AF848034";
ram_buffer(3308) := X"00041080";
ram_buffer(3309) := X"00441021";
ram_buffer(3310) := X"00021080";
ram_buffer(3311) := X"26447D84";
ram_buffer(3312) := X"00822021";
ram_buffer(3313) := X"0C400441";
ram_buffer(3314) := X"02202825";
ram_buffer(3315) := X"8F828030";
ram_buffer(3316) := X"00000000";
ram_buffer(3317) := X"14400027";
ram_buffer(3318) := X"00000000";
ram_buffer(3319) := X"8F828030";
ram_buffer(3320) := X"00000000";
ram_buffer(3321) := X"10400009";
ram_buffer(3322) := X"24020001";
ram_buffer(3323) := X"8F828010";
ram_buffer(3324) := X"8E03002C";
ram_buffer(3325) := X"8C42002C";
ram_buffer(3326) := X"00000000";
ram_buffer(3327) := X"0043102B";
ram_buffer(3328) := X"14400032";
ram_buffer(3329) := X"00000000";
ram_buffer(3330) := X"24020001";
ram_buffer(3331) := X"8FBF002C";
ram_buffer(3332) := X"8FB60028";
ram_buffer(3333) := X"8FB50024";
ram_buffer(3334) := X"8FB40020";
ram_buffer(3335) := X"8FB3001C";
ram_buffer(3336) := X"8FB20018";
ram_buffer(3337) := X"8FB10014";
ram_buffer(3338) := X"8FB00010";
ram_buffer(3339) := X"03E00008";
ram_buffer(3340) := X"27BD0030";
ram_buffer(3341) := X"AF908010";
ram_buffer(3342) := X"8F83803C";
ram_buffer(3343) := X"24020001";
ram_buffer(3344) := X"1062002F";
ram_buffer(3345) := X"3C120100";
ram_buffer(3346) := X"8E04002C";
ram_buffer(3347) := X"3C120100";
ram_buffer(3348) := X"8F838020";
ram_buffer(3349) := X"8F828034";
ram_buffer(3350) := X"24630001";
ram_buffer(3351) := X"0044102B";
ram_buffer(3352) := X"1040FFD3";
ram_buffer(3353) := X"AF838020";
ram_buffer(3354) := X"AF848034";
ram_buffer(3355) := X"1000FFD1";
ram_buffer(3356) := X"00041080";
ram_buffer(3357) := X"8F828010";
ram_buffer(3358) := X"00000000";
ram_buffer(3359) := X"8C420044";
ram_buffer(3360) := X"00000000";
ram_buffer(3361) := X"1040FFD5";
ram_buffer(3362) := X"00000000";
ram_buffer(3363) := X"8F838010";
ram_buffer(3364) := X"8F848010";
ram_buffer(3365) := X"8C620044";
ram_buffer(3366) := X"00000000";
ram_buffer(3367) := X"2442FFFF";
ram_buffer(3368) := X"AC620044";
ram_buffer(3369) := X"8C820044";
ram_buffer(3370) := X"00000000";
ram_buffer(3371) := X"1440FFCB";
ram_buffer(3372) := X"00000000";
ram_buffer(3373) := X"0C400415";
ram_buffer(3374) := X"00000000";
ram_buffer(3375) := X"1000FFC7";
ram_buffer(3376) := X"00000000";
ram_buffer(3377) := X"1000FF80";
ram_buffer(3378) := X"24160004";
ram_buffer(3379) := X"0C4001B1";
ram_buffer(3380) := X"00000000";
ram_buffer(3381) := X"1000FFCD";
ram_buffer(3382) := X"24020001";
ram_buffer(3383) := X"1000FFCB";
ram_buffer(3384) := X"2402FFFF";
ram_buffer(3385) := X"8F838010";
ram_buffer(3386) := X"8F828010";
ram_buffer(3387) := X"8C620044";
ram_buffer(3388) := X"00000000";
ram_buffer(3389) := X"24420001";
ram_buffer(3390) := X"1000FF91";
ram_buffer(3391) := X"AC620044";
ram_buffer(3392) := X"0C400437";
ram_buffer(3393) := X"26447D84";
ram_buffer(3394) := X"3C040100";
ram_buffer(3395) := X"0C400437";
ram_buffer(3396) := X"24847D98";
ram_buffer(3397) := X"3C040100";
ram_buffer(3398) := X"0C400437";
ram_buffer(3399) := X"24847DAC";
ram_buffer(3400) := X"3C040100";
ram_buffer(3401) := X"0C400437";
ram_buffer(3402) := X"24847DC0";
ram_buffer(3403) := X"3C040100";
ram_buffer(3404) := X"24847DD4";
ram_buffer(3405) := X"0C400437";
ram_buffer(3406) := X"3C140100";
ram_buffer(3407) := X"3C130100";
ram_buffer(3408) := X"0C400437";
ram_buffer(3409) := X"26847D70";
ram_buffer(3410) := X"0C400437";
ram_buffer(3411) := X"26647D5C";
ram_buffer(3412) := X"3C040100";
ram_buffer(3413) := X"0C400437";
ram_buffer(3414) := X"24847D48";
ram_buffer(3415) := X"3C040100";
ram_buffer(3416) := X"0C400437";
ram_buffer(3417) := X"24847D34";
ram_buffer(3418) := X"3C040100";
ram_buffer(3419) := X"24847D20";
ram_buffer(3420) := X"26947D70";
ram_buffer(3421) := X"0C400437";
ram_buffer(3422) := X"26737D5C";
ram_buffer(3423) := X"AF948048";
ram_buffer(3424) := X"8E04002C";
ram_buffer(3425) := X"AF938044";
ram_buffer(3426) := X"1000FFB1";
ram_buffer(3427) := X"00000000";
ram_buffer(3428) := X"0C401D6D";
ram_buffer(3429) := X"02C02025";
ram_buffer(3430) := X"1000FF9C";
ram_buffer(3431) := X"2402FFFF";
ram_buffer(3432) := X"27BDFFE0";
ram_buffer(3433) := X"AFB00014";
ram_buffer(3434) := X"AFBF001C";
ram_buffer(3435) := X"AFB10018";
ram_buffer(3436) := X"0C40041A";
ram_buffer(3437) := X"00808025";
ram_buffer(3438) := X"8F828030";
ram_buffer(3439) := X"00000000";
ram_buffer(3440) := X"14400037";
ram_buffer(3441) := X"00000000";
ram_buffer(3442) := X"1200003C";
ram_buffer(3443) := X"00000000";
ram_buffer(3444) := X"26110004";
ram_buffer(3445) := X"0C40046F";
ram_buffer(3446) := X"02202025";
ram_buffer(3447) := X"8E020028";
ram_buffer(3448) := X"00000000";
ram_buffer(3449) := X"10400003";
ram_buffer(3450) := X"00000000";
ram_buffer(3451) := X"0C40046F";
ram_buffer(3452) := X"26040018";
ram_buffer(3453) := X"8F828020";
ram_buffer(3454) := X"8F838010";
ram_buffer(3455) := X"24420001";
ram_buffer(3456) := X"12030053";
ram_buffer(3457) := X"AF828020";
ram_buffer(3458) := X"8F82803C";
ram_buffer(3459) := X"8E040030";
ram_buffer(3460) := X"2442FFFF";
ram_buffer(3461) := X"AF82803C";
ram_buffer(3462) := X"0C401D6D";
ram_buffer(3463) := X"00000000";
ram_buffer(3464) := X"0C401D6D";
ram_buffer(3465) := X"02002025";
ram_buffer(3466) := X"8F828048";
ram_buffer(3467) := X"00000000";
ram_buffer(3468) := X"8C420000";
ram_buffer(3469) := X"00000000";
ram_buffer(3470) := X"14400023";
ram_buffer(3471) := X"2402FFFF";
ram_buffer(3472) := X"AF82801C";
ram_buffer(3473) := X"8F828030";
ram_buffer(3474) := X"00000000";
ram_buffer(3475) := X"10400007";
ram_buffer(3476) := X"00000000";
ram_buffer(3477) := X"8F828010";
ram_buffer(3478) := X"00000000";
ram_buffer(3479) := X"8C420044";
ram_buffer(3480) := X"00000000";
ram_buffer(3481) := X"14400023";
ram_buffer(3482) := X"00000000";
ram_buffer(3483) := X"8F828030";
ram_buffer(3484) := X"00000000";
ram_buffer(3485) := X"10400005";
ram_buffer(3486) := X"00000000";
ram_buffer(3487) := X"8F828010";
ram_buffer(3488) := X"00000000";
ram_buffer(3489) := X"12020029";
ram_buffer(3490) := X"00000000";
ram_buffer(3491) := X"8FBF001C";
ram_buffer(3492) := X"8FB10018";
ram_buffer(3493) := X"8FB00014";
ram_buffer(3494) := X"03E00008";
ram_buffer(3495) := X"27BD0020";
ram_buffer(3496) := X"8F838010";
ram_buffer(3497) := X"8F828010";
ram_buffer(3498) := X"8C620044";
ram_buffer(3499) := X"00000000";
ram_buffer(3500) := X"24420001";
ram_buffer(3501) := X"1600FFC6";
ram_buffer(3502) := X"AC620044";
ram_buffer(3503) := X"8F908010";
ram_buffer(3504) := X"1000FFC4";
ram_buffer(3505) := X"26110004";
ram_buffer(3506) := X"8F828048";
ram_buffer(3507) := X"00000000";
ram_buffer(3508) := X"8C42000C";
ram_buffer(3509) := X"00000000";
ram_buffer(3510) := X"8C42000C";
ram_buffer(3511) := X"00000000";
ram_buffer(3512) := X"8C420004";
ram_buffer(3513) := X"00000000";
ram_buffer(3514) := X"AF82801C";
ram_buffer(3515) := X"1000FFD5";
ram_buffer(3516) := X"00000000";
ram_buffer(3517) := X"8F838010";
ram_buffer(3518) := X"8F848010";
ram_buffer(3519) := X"8C620044";
ram_buffer(3520) := X"00000000";
ram_buffer(3521) := X"2442FFFF";
ram_buffer(3522) := X"AC620044";
ram_buffer(3523) := X"8C820044";
ram_buffer(3524) := X"00000000";
ram_buffer(3525) := X"1440FFD5";
ram_buffer(3526) := X"00000000";
ram_buffer(3527) := X"0C400415";
ram_buffer(3528) := X"00000000";
ram_buffer(3529) := X"1000FFD1";
ram_buffer(3530) := X"00000000";
ram_buffer(3531) := X"8F828014";
ram_buffer(3532) := X"00000000";
ram_buffer(3533) := X"14400010";
ram_buffer(3534) := X"24050465";
ram_buffer(3535) := X"8FBF001C";
ram_buffer(3536) := X"8FB10018";
ram_buffer(3537) := X"8FB00014";
ram_buffer(3538) := X"084001B1";
ram_buffer(3539) := X"27BD0020";
ram_buffer(3540) := X"3C040100";
ram_buffer(3541) := X"02202825";
ram_buffer(3542) := X"0C400441";
ram_buffer(3543) := X"24847D34";
ram_buffer(3544) := X"8F828040";
ram_buffer(3545) := X"00000000";
ram_buffer(3546) := X"24420001";
ram_buffer(3547) := X"AF828040";
ram_buffer(3548) := X"1000FFB4";
ram_buffer(3549) := X"00000000";
ram_buffer(3550) := X"3C040100";
ram_buffer(3551) := X"0C40041F";
ram_buffer(3552) := X"24847C38";
ram_buffer(3553) := X"1000FFED";
ram_buffer(3554) := X"00000000";
ram_buffer(3555) := X"27BDFFE0";
ram_buffer(3556) := X"AFB00014";
ram_buffer(3557) := X"AFBF001C";
ram_buffer(3558) := X"AFB10018";
ram_buffer(3559) := X"10800051";
ram_buffer(3560) := X"00808025";
ram_buffer(3561) := X"8F828010";
ram_buffer(3562) := X"00000000";
ram_buffer(3563) := X"12020042";
ram_buffer(3564) := X"00001025";
ram_buffer(3565) := X"0C40041A";
ram_buffer(3566) := X"00000000";
ram_buffer(3567) := X"8F828030";
ram_buffer(3568) := X"00000000";
ram_buffer(3569) := X"14400035";
ram_buffer(3570) := X"00000000";
ram_buffer(3571) := X"8F828030";
ram_buffer(3572) := X"8E110014";
ram_buffer(3573) := X"14400017";
ram_buffer(3574) := X"00000000";
ram_buffer(3575) := X"8F828048";
ram_buffer(3576) := X"00000000";
ram_buffer(3577) := X"12220028";
ram_buffer(3578) := X"24020002";
ram_buffer(3579) := X"8F828044";
ram_buffer(3580) := X"00000000";
ram_buffer(3581) := X"12220023";
ram_buffer(3582) := X"3C020100";
ram_buffer(3583) := X"24427D20";
ram_buffer(3584) := X"1222003E";
ram_buffer(3585) := X"00000000";
ram_buffer(3586) := X"3C020100";
ram_buffer(3587) := X"24427D34";
ram_buffer(3588) := X"1222002E";
ram_buffer(3589) := X"00000000";
ram_buffer(3590) := X"1220002C";
ram_buffer(3591) := X"24020001";
ram_buffer(3592) := X"8FBF001C";
ram_buffer(3593) := X"8FB10018";
ram_buffer(3594) := X"8FB00014";
ram_buffer(3595) := X"03E00008";
ram_buffer(3596) := X"27BD0020";
ram_buffer(3597) := X"8F828010";
ram_buffer(3598) := X"00000000";
ram_buffer(3599) := X"8C420044";
ram_buffer(3600) := X"00000000";
ram_buffer(3601) := X"1040FFE5";
ram_buffer(3602) := X"00000000";
ram_buffer(3603) := X"8F838010";
ram_buffer(3604) := X"8F848010";
ram_buffer(3605) := X"8C620044";
ram_buffer(3606) := X"00000000";
ram_buffer(3607) := X"2442FFFF";
ram_buffer(3608) := X"AC620044";
ram_buffer(3609) := X"8C820044";
ram_buffer(3610) := X"00000000";
ram_buffer(3611) := X"1440FFDB";
ram_buffer(3612) := X"00000000";
ram_buffer(3613) := X"0C400415";
ram_buffer(3614) := X"00000000";
ram_buffer(3615) := X"1000FFD7";
ram_buffer(3616) := X"00000000";
ram_buffer(3617) := X"24020002";
ram_buffer(3618) := X"8FBF001C";
ram_buffer(3619) := X"8FB10018";
ram_buffer(3620) := X"8FB00014";
ram_buffer(3621) := X"03E00008";
ram_buffer(3622) := X"27BD0020";
ram_buffer(3623) := X"8F838010";
ram_buffer(3624) := X"8F828010";
ram_buffer(3625) := X"8C620044";
ram_buffer(3626) := X"00000000";
ram_buffer(3627) := X"24420001";
ram_buffer(3628) := X"1000FFC6";
ram_buffer(3629) := X"AC620044";
ram_buffer(3630) := X"8FBF001C";
ram_buffer(3631) := X"8FB10018";
ram_buffer(3632) := X"8FB00014";
ram_buffer(3633) := X"03E00008";
ram_buffer(3634) := X"27BD0020";
ram_buffer(3635) := X"8FBF001C";
ram_buffer(3636) := X"8FB10018";
ram_buffer(3637) := X"8FB00014";
ram_buffer(3638) := X"24020004";
ram_buffer(3639) := X"03E00008";
ram_buffer(3640) := X"27BD0020";
ram_buffer(3641) := X"3C040100";
ram_buffer(3642) := X"24050502";
ram_buffer(3643) := X"0C40041F";
ram_buffer(3644) := X"24847C38";
ram_buffer(3645) := X"1000FFAB";
ram_buffer(3646) := X"00000000";
ram_buffer(3647) := X"8E020028";
ram_buffer(3648) := X"00000000";
ram_buffer(3649) := X"2C420001";
ram_buffer(3650) := X"1000FFDF";
ram_buffer(3651) := X"24420002";
ram_buffer(3652) := X"27BDFFE0";
ram_buffer(3653) := X"AFB00018";
ram_buffer(3654) := X"AFBF001C";
ram_buffer(3655) := X"0C40041A";
ram_buffer(3656) := X"00808025";
ram_buffer(3657) := X"8F828030";
ram_buffer(3658) := X"00000000";
ram_buffer(3659) := X"14400020";
ram_buffer(3660) := X"00000000";
ram_buffer(3661) := X"12000025";
ram_buffer(3662) := X"00000000";
ram_buffer(3663) := X"8F838030";
ram_buffer(3664) := X"8E02002C";
ram_buffer(3665) := X"10600007";
ram_buffer(3666) := X"00000000";
ram_buffer(3667) := X"8F838010";
ram_buffer(3668) := X"00000000";
ram_buffer(3669) := X"8C630044";
ram_buffer(3670) := X"00000000";
ram_buffer(3671) := X"14600005";
ram_buffer(3672) := X"00000000";
ram_buffer(3673) := X"8FBF001C";
ram_buffer(3674) := X"8FB00018";
ram_buffer(3675) := X"03E00008";
ram_buffer(3676) := X"27BD0020";
ram_buffer(3677) := X"8F848010";
ram_buffer(3678) := X"8F858010";
ram_buffer(3679) := X"8C830044";
ram_buffer(3680) := X"00000000";
ram_buffer(3681) := X"2463FFFF";
ram_buffer(3682) := X"AC830044";
ram_buffer(3683) := X"8CA30044";
ram_buffer(3684) := X"00000000";
ram_buffer(3685) := X"1460FFF3";
ram_buffer(3686) := X"00000000";
ram_buffer(3687) := X"0C400415";
ram_buffer(3688) := X"AFA20010";
ram_buffer(3689) := X"8FA20010";
ram_buffer(3690) := X"1000FFEE";
ram_buffer(3691) := X"00000000";
ram_buffer(3692) := X"8F838010";
ram_buffer(3693) := X"8F828010";
ram_buffer(3694) := X"8C620044";
ram_buffer(3695) := X"00000000";
ram_buffer(3696) := X"24420001";
ram_buffer(3697) := X"1600FFDD";
ram_buffer(3698) := X"AC620044";
ram_buffer(3699) := X"8F908010";
ram_buffer(3700) := X"1000FFDA";
ram_buffer(3701) := X"00000000";
ram_buffer(3702) := X"10800004";
ram_buffer(3703) := X"00000000";
ram_buffer(3704) := X"8C82002C";
ram_buffer(3705) := X"03E00008";
ram_buffer(3706) := X"00000000";
ram_buffer(3707) := X"8F848010";
ram_buffer(3708) := X"00000000";
ram_buffer(3709) := X"8C82002C";
ram_buffer(3710) := X"03E00008";
ram_buffer(3711) := X"00000000";
ram_buffer(3712) := X"27BDFFD8";
ram_buffer(3713) := X"2CA20005";
ram_buffer(3714) := X"AFB00014";
ram_buffer(3715) := X"AFBF0024";
ram_buffer(3716) := X"AFB30020";
ram_buffer(3717) := X"AFB2001C";
ram_buffer(3718) := X"AFB10018";
ram_buffer(3719) := X"1040005A";
ram_buffer(3720) := X"00808025";
ram_buffer(3721) := X"0C40041A";
ram_buffer(3722) := X"00A08825";
ram_buffer(3723) := X"8F828030";
ram_buffer(3724) := X"00000000";
ram_buffer(3725) := X"1440005E";
ram_buffer(3726) := X"00000000";
ram_buffer(3727) := X"12000063";
ram_buffer(3728) := X"00000000";
ram_buffer(3729) := X"8E030048";
ram_buffer(3730) := X"00000000";
ram_buffer(3731) := X"1223001F";
ram_buffer(3732) := X"0071102B";
ram_buffer(3733) := X"1440002E";
ram_buffer(3734) := X"00000000";
ram_buffer(3735) := X"8F928010";
ram_buffer(3736) := X"00000000";
ram_buffer(3737) := X"02129026";
ram_buffer(3738) := X"2E520001";
ram_buffer(3739) := X"8E04002C";
ram_buffer(3740) := X"00000000";
ram_buffer(3741) := X"10640031";
ram_buffer(3742) := X"00000000";
ram_buffer(3743) := X"8E020018";
ram_buffer(3744) := X"00000000";
ram_buffer(3745) := X"04400004";
ram_buffer(3746) := X"AE110048";
ram_buffer(3747) := X"24050005";
ram_buffer(3748) := X"00B18823";
ram_buffer(3749) := X"AE110018";
ram_buffer(3750) := X"00041080";
ram_buffer(3751) := X"00441021";
ram_buffer(3752) := X"3C110100";
ram_buffer(3753) := X"00021080";
ram_buffer(3754) := X"26317D84";
ram_buffer(3755) := X"8E030014";
ram_buffer(3756) := X"02221021";
ram_buffer(3757) := X"1062004A";
ram_buffer(3758) := X"26130004";
ram_buffer(3759) := X"12400003";
ram_buffer(3760) := X"00000000";
ram_buffer(3761) := X"0C4001B1";
ram_buffer(3762) := X"00000000";
ram_buffer(3763) := X"8F828030";
ram_buffer(3764) := X"00000000";
ram_buffer(3765) := X"10400007";
ram_buffer(3766) := X"00000000";
ram_buffer(3767) := X"8F828010";
ram_buffer(3768) := X"00000000";
ram_buffer(3769) := X"8C420044";
ram_buffer(3770) := X"00000000";
ram_buffer(3771) := X"14400015";
ram_buffer(3772) := X"00000000";
ram_buffer(3773) := X"8FBF0024";
ram_buffer(3774) := X"8FB30020";
ram_buffer(3775) := X"8FB2001C";
ram_buffer(3776) := X"8FB10018";
ram_buffer(3777) := X"8FB00014";
ram_buffer(3778) := X"03E00008";
ram_buffer(3779) := X"27BD0028";
ram_buffer(3780) := X"8F828010";
ram_buffer(3781) := X"00000000";
ram_buffer(3782) := X"1202002F";
ram_buffer(3783) := X"00000000";
ram_buffer(3784) := X"8F828010";
ram_buffer(3785) := X"8E04002C";
ram_buffer(3786) := X"8C52002C";
ram_buffer(3787) := X"00000000";
ram_buffer(3788) := X"0232902B";
ram_buffer(3789) := X"1464FFD1";
ram_buffer(3790) := X"3A520001";
ram_buffer(3791) := X"1000FFCF";
ram_buffer(3792) := X"AE11002C";
ram_buffer(3793) := X"8F838010";
ram_buffer(3794) := X"8F848010";
ram_buffer(3795) := X"8C620044";
ram_buffer(3796) := X"00000000";
ram_buffer(3797) := X"2442FFFF";
ram_buffer(3798) := X"AC620044";
ram_buffer(3799) := X"8C820044";
ram_buffer(3800) := X"00000000";
ram_buffer(3801) := X"1440FFE3";
ram_buffer(3802) := X"00000000";
ram_buffer(3803) := X"8FBF0024";
ram_buffer(3804) := X"8FB30020";
ram_buffer(3805) := X"8FB2001C";
ram_buffer(3806) := X"8FB10018";
ram_buffer(3807) := X"8FB00014";
ram_buffer(3808) := X"08400415";
ram_buffer(3809) := X"27BD0028";
ram_buffer(3810) := X"3C040100";
ram_buffer(3811) := X"24050587";
ram_buffer(3812) := X"0C40041F";
ram_buffer(3813) := X"24847C38";
ram_buffer(3814) := X"0C40041A";
ram_buffer(3815) := X"00000000";
ram_buffer(3816) := X"8F828030";
ram_buffer(3817) := X"00000000";
ram_buffer(3818) := X"1040FFA4";
ram_buffer(3819) := X"24110004";
ram_buffer(3820) := X"8F838010";
ram_buffer(3821) := X"8F828010";
ram_buffer(3822) := X"8C620044";
ram_buffer(3823) := X"00000000";
ram_buffer(3824) := X"24420001";
ram_buffer(3825) := X"1600FF9F";
ram_buffer(3826) := X"AC620044";
ram_buffer(3827) := X"8F908010";
ram_buffer(3828) := X"1000FF9C";
ram_buffer(3829) := X"00000000";
ram_buffer(3830) := X"1000FFA4";
ram_buffer(3831) := X"00009025";
ram_buffer(3832) := X"0C40046F";
ram_buffer(3833) := X"02602025";
ram_buffer(3834) := X"8E02002C";
ram_buffer(3835) := X"8F838034";
ram_buffer(3836) := X"00000000";
ram_buffer(3837) := X"0062182B";
ram_buffer(3838) := X"10600002";
ram_buffer(3839) := X"00000000";
ram_buffer(3840) := X"AF828034";
ram_buffer(3841) := X"00022080";
ram_buffer(3842) := X"00822021";
ram_buffer(3843) := X"00042080";
ram_buffer(3844) := X"02602825";
ram_buffer(3845) := X"0C400441";
ram_buffer(3846) := X"02242021";
ram_buffer(3847) := X"1000FFA7";
ram_buffer(3848) := X"00000000";
ram_buffer(3849) := X"27BDFFE0";
ram_buffer(3850) := X"AFB00010";
ram_buffer(3851) := X"AFBF001C";
ram_buffer(3852) := X"AFB20018";
ram_buffer(3853) := X"AFB10014";
ram_buffer(3854) := X"0C40041A";
ram_buffer(3855) := X"00808025";
ram_buffer(3856) := X"8F828030";
ram_buffer(3857) := X"00000000";
ram_buffer(3858) := X"14400028";
ram_buffer(3859) := X"00000000";
ram_buffer(3860) := X"1200002D";
ram_buffer(3861) := X"00000000";
ram_buffer(3862) := X"26110004";
ram_buffer(3863) := X"0C40046F";
ram_buffer(3864) := X"02202025";
ram_buffer(3865) := X"8E020028";
ram_buffer(3866) := X"00000000";
ram_buffer(3867) := X"10400004";
ram_buffer(3868) := X"3C120100";
ram_buffer(3869) := X"0C40046F";
ram_buffer(3870) := X"26040018";
ram_buffer(3871) := X"3C120100";
ram_buffer(3872) := X"02202825";
ram_buffer(3873) := X"0C400441";
ram_buffer(3874) := X"26447D20";
ram_buffer(3875) := X"8F828030";
ram_buffer(3876) := X"00000000";
ram_buffer(3877) := X"10400007";
ram_buffer(3878) := X"00000000";
ram_buffer(3879) := X"8F828010";
ram_buffer(3880) := X"00000000";
ram_buffer(3881) := X"8C420044";
ram_buffer(3882) := X"00000000";
ram_buffer(3883) := X"1440004F";
ram_buffer(3884) := X"00000000";
ram_buffer(3885) := X"8F828030";
ram_buffer(3886) := X"00000000";
ram_buffer(3887) := X"14400015";
ram_buffer(3888) := X"00000000";
ram_buffer(3889) := X"8F828010";
ram_buffer(3890) := X"00000000";
ram_buffer(3891) := X"12020036";
ram_buffer(3892) := X"00000000";
ram_buffer(3893) := X"8FBF001C";
ram_buffer(3894) := X"8FB20018";
ram_buffer(3895) := X"8FB10014";
ram_buffer(3896) := X"8FB00010";
ram_buffer(3897) := X"03E00008";
ram_buffer(3898) := X"27BD0020";
ram_buffer(3899) := X"8F838010";
ram_buffer(3900) := X"8F828010";
ram_buffer(3901) := X"8C620044";
ram_buffer(3902) := X"00000000";
ram_buffer(3903) := X"24420001";
ram_buffer(3904) := X"1600FFD5";
ram_buffer(3905) := X"AC620044";
ram_buffer(3906) := X"8F908010";
ram_buffer(3907) := X"1000FFD3";
ram_buffer(3908) := X"26110004";
ram_buffer(3909) := X"0C40041A";
ram_buffer(3910) := X"00000000";
ram_buffer(3911) := X"8F828030";
ram_buffer(3912) := X"00000000";
ram_buffer(3913) := X"14400056";
ram_buffer(3914) := X"00000000";
ram_buffer(3915) := X"8F828048";
ram_buffer(3916) := X"00000000";
ram_buffer(3917) := X"8C420000";
ram_buffer(3918) := X"00000000";
ram_buffer(3919) := X"14400045";
ram_buffer(3920) := X"2402FFFF";
ram_buffer(3921) := X"AF82801C";
ram_buffer(3922) := X"8F828030";
ram_buffer(3923) := X"00000000";
ram_buffer(3924) := X"1040FFDC";
ram_buffer(3925) := X"00000000";
ram_buffer(3926) := X"8F828010";
ram_buffer(3927) := X"00000000";
ram_buffer(3928) := X"8C420044";
ram_buffer(3929) := X"00000000";
ram_buffer(3930) := X"1040FFD6";
ram_buffer(3931) := X"00000000";
ram_buffer(3932) := X"8F838010";
ram_buffer(3933) := X"8F848010";
ram_buffer(3934) := X"8C620044";
ram_buffer(3935) := X"00000000";
ram_buffer(3936) := X"2442FFFF";
ram_buffer(3937) := X"AC620044";
ram_buffer(3938) := X"8C820044";
ram_buffer(3939) := X"00000000";
ram_buffer(3940) := X"1440FFCC";
ram_buffer(3941) := X"00000000";
ram_buffer(3942) := X"0C400415";
ram_buffer(3943) := X"00000000";
ram_buffer(3944) := X"1000FFC8";
ram_buffer(3945) := X"00000000";
ram_buffer(3946) := X"8F828030";
ram_buffer(3947) := X"00000000";
ram_buffer(3948) := X"1040001C";
ram_buffer(3949) := X"00000000";
ram_buffer(3950) := X"8F828014";
ram_buffer(3951) := X"00000000";
ram_buffer(3952) := X"10400004";
ram_buffer(3953) := X"3C040100";
ram_buffer(3954) := X"2405065E";
ram_buffer(3955) := X"0C40041F";
ram_buffer(3956) := X"24847C38";
ram_buffer(3957) := X"8FBF001C";
ram_buffer(3958) := X"8FB20018";
ram_buffer(3959) := X"8FB10014";
ram_buffer(3960) := X"8FB00010";
ram_buffer(3961) := X"084001B1";
ram_buffer(3962) := X"27BD0020";
ram_buffer(3963) := X"8F838010";
ram_buffer(3964) := X"8F848010";
ram_buffer(3965) := X"8C620044";
ram_buffer(3966) := X"00000000";
ram_buffer(3967) := X"2442FFFF";
ram_buffer(3968) := X"AC620044";
ram_buffer(3969) := X"8C820044";
ram_buffer(3970) := X"00000000";
ram_buffer(3971) := X"1440FFA9";
ram_buffer(3972) := X"00000000";
ram_buffer(3973) := X"0C400415";
ram_buffer(3974) := X"00000000";
ram_buffer(3975) := X"1000FFA5";
ram_buffer(3976) := X"00000000";
ram_buffer(3977) := X"8F82803C";
ram_buffer(3978) := X"8E437D20";
ram_buffer(3979) := X"00000000";
ram_buffer(3980) := X"1062006C";
ram_buffer(3981) := X"00000000";
ram_buffer(3982) := X"8F828014";
ram_buffer(3983) := X"00000000";
ram_buffer(3984) := X"10400016";
ram_buffer(3985) := X"24020001";
ram_buffer(3986) := X"AF828028";
ram_buffer(3987) := X"1000FFA1";
ram_buffer(3988) := X"00000000";
ram_buffer(3989) := X"8F828048";
ram_buffer(3990) := X"00000000";
ram_buffer(3991) := X"8C42000C";
ram_buffer(3992) := X"00000000";
ram_buffer(3993) := X"8C42000C";
ram_buffer(3994) := X"00000000";
ram_buffer(3995) := X"8C420004";
ram_buffer(3996) := X"00000000";
ram_buffer(3997) := X"AF82801C";
ram_buffer(3998) := X"1000FFB3";
ram_buffer(3999) := X"00000000";
ram_buffer(4000) := X"8F838010";
ram_buffer(4001) := X"8F828010";
ram_buffer(4002) := X"8C620044";
ram_buffer(4003) := X"00000000";
ram_buffer(4004) := X"24420001";
ram_buffer(4005) := X"1000FFA5";
ram_buffer(4006) := X"AC620044";
ram_buffer(4007) := X"AF808028";
ram_buffer(4008) := X"8F908034";
ram_buffer(4009) := X"3C110100";
ram_buffer(4010) := X"00101080";
ram_buffer(4011) := X"00501821";
ram_buffer(4012) := X"00031880";
ram_buffer(4013) := X"26317D84";
ram_buffer(4014) := X"02231821";
ram_buffer(4015) := X"8C630000";
ram_buffer(4016) := X"00000000";
ram_buffer(4017) := X"14600032";
ram_buffer(4018) := X"00501021";
ram_buffer(4019) := X"12000048";
ram_buffer(4020) := X"3C040100";
ram_buffer(4021) := X"2604FFFF";
ram_buffer(4022) := X"00041080";
ram_buffer(4023) := X"00441821";
ram_buffer(4024) := X"00031880";
ram_buffer(4025) := X"02231821";
ram_buffer(4026) := X"8C630000";
ram_buffer(4027) := X"00000000";
ram_buffer(4028) := X"1460003A";
ram_buffer(4029) := X"00000000";
ram_buffer(4030) := X"10800047";
ram_buffer(4031) := X"3C040100";
ram_buffer(4032) := X"2604FFFE";
ram_buffer(4033) := X"00041080";
ram_buffer(4034) := X"00441821";
ram_buffer(4035) := X"00031880";
ram_buffer(4036) := X"02231821";
ram_buffer(4037) := X"8C630000";
ram_buffer(4038) := X"00000000";
ram_buffer(4039) := X"1460002F";
ram_buffer(4040) := X"00000000";
ram_buffer(4041) := X"10800037";
ram_buffer(4042) := X"3C040100";
ram_buffer(4043) := X"2604FFFD";
ram_buffer(4044) := X"00041080";
ram_buffer(4045) := X"00441821";
ram_buffer(4046) := X"00031880";
ram_buffer(4047) := X"02231821";
ram_buffer(4048) := X"8C630000";
ram_buffer(4049) := X"00000000";
ram_buffer(4050) := X"14600024";
ram_buffer(4051) := X"00000000";
ram_buffer(4052) := X"10800036";
ram_buffer(4053) := X"3C040100";
ram_buffer(4054) := X"2604FFFC";
ram_buffer(4055) := X"00041080";
ram_buffer(4056) := X"00441821";
ram_buffer(4057) := X"00031880";
ram_buffer(4058) := X"02231821";
ram_buffer(4059) := X"8C630000";
ram_buffer(4060) := X"00000000";
ram_buffer(4061) := X"14600019";
ram_buffer(4062) := X"00000000";
ram_buffer(4063) := X"10800012";
ram_buffer(4064) := X"3C040100";
ram_buffer(4065) := X"2610FFFB";
ram_buffer(4066) := X"00101080";
ram_buffer(4067) := X"00501021";
ram_buffer(4068) := X"00021080";
ram_buffer(4069) := X"02222021";
ram_buffer(4070) := X"8C830004";
ram_buffer(4071) := X"24420008";
ram_buffer(4072) := X"8C630004";
ram_buffer(4073) := X"02221021";
ram_buffer(4074) := X"10620025";
ram_buffer(4075) := X"AC830004";
ram_buffer(4076) := X"8C62000C";
ram_buffer(4077) := X"00000000";
ram_buffer(4078) := X"AF828010";
ram_buffer(4079) := X"AF908034";
ram_buffer(4080) := X"1000FF44";
ram_buffer(4081) := X"00000000";
ram_buffer(4082) := X"24050B05";
ram_buffer(4083) := X"0C40041F";
ram_buffer(4084) := X"24847C38";
ram_buffer(4085) := X"1000FFEC";
ram_buffer(4086) := X"2610FFFB";
ram_buffer(4087) := X"1000FFEB";
ram_buffer(4088) := X"00808025";
ram_buffer(4089) := X"AF808010";
ram_buffer(4090) := X"1000FF3A";
ram_buffer(4091) := X"00000000";
ram_buffer(4092) := X"24050B05";
ram_buffer(4093) := X"0C40041F";
ram_buffer(4094) := X"24847C38";
ram_buffer(4095) := X"1000FFB6";
ram_buffer(4096) := X"2604FFFF";
ram_buffer(4097) := X"24050B05";
ram_buffer(4098) := X"0C40041F";
ram_buffer(4099) := X"24847C38";
ram_buffer(4100) := X"1000FFC7";
ram_buffer(4101) := X"2604FFFD";
ram_buffer(4102) := X"24050B05";
ram_buffer(4103) := X"0C40041F";
ram_buffer(4104) := X"24847C38";
ram_buffer(4105) := X"1000FFB7";
ram_buffer(4106) := X"2604FFFE";
ram_buffer(4107) := X"24050B05";
ram_buffer(4108) := X"0C40041F";
ram_buffer(4109) := X"24847C38";
ram_buffer(4110) := X"1000FFC8";
ram_buffer(4111) := X"2604FFFC";
ram_buffer(4112) := X"8C630004";
ram_buffer(4113) := X"1000FFDA";
ram_buffer(4114) := X"AC830004";
ram_buffer(4115) := X"1080005C";
ram_buffer(4116) := X"240506B2";
ram_buffer(4117) := X"8F828010";
ram_buffer(4118) := X"27BDFFE0";
ram_buffer(4119) := X"AFBF001C";
ram_buffer(4120) := X"AFB10018";
ram_buffer(4121) := X"10820015";
ram_buffer(4122) := X"AFB00014";
ram_buffer(4123) := X"0C40041A";
ram_buffer(4124) := X"00808025";
ram_buffer(4125) := X"8F828030";
ram_buffer(4126) := X"00000000";
ram_buffer(4127) := X"14400014";
ram_buffer(4128) := X"3C020100";
ram_buffer(4129) := X"8E030014";
ram_buffer(4130) := X"24427D20";
ram_buffer(4131) := X"1062001B";
ram_buffer(4132) := X"3C020100";
ram_buffer(4133) := X"8F828030";
ram_buffer(4134) := X"00000000";
ram_buffer(4135) := X"10400007";
ram_buffer(4136) := X"00000000";
ram_buffer(4137) := X"8F828010";
ram_buffer(4138) := X"00000000";
ram_buffer(4139) := X"8C420044";
ram_buffer(4140) := X"00000000";
ram_buffer(4141) := X"14400033";
ram_buffer(4142) := X"00000000";
ram_buffer(4143) := X"8FBF001C";
ram_buffer(4144) := X"8FB10018";
ram_buffer(4145) := X"8FB00014";
ram_buffer(4146) := X"03E00008";
ram_buffer(4147) := X"27BD0020";
ram_buffer(4148) := X"8F838010";
ram_buffer(4149) := X"8F828010";
ram_buffer(4150) := X"8C620044";
ram_buffer(4151) := X"00000000";
ram_buffer(4152) := X"24420001";
ram_buffer(4153) := X"AC620044";
ram_buffer(4154) := X"3C020100";
ram_buffer(4155) := X"8E030014";
ram_buffer(4156) := X"24427D20";
ram_buffer(4157) := X"1462FFE7";
ram_buffer(4158) := X"3C020100";
ram_buffer(4159) := X"8E030028";
ram_buffer(4160) := X"24427D48";
ram_buffer(4161) := X"1062FFE3";
ram_buffer(4162) := X"00000000";
ram_buffer(4163) := X"1460FFE1";
ram_buffer(4164) := X"26110004";
ram_buffer(4165) := X"0C40046F";
ram_buffer(4166) := X"02202025";
ram_buffer(4167) := X"8E04002C";
ram_buffer(4168) := X"8F828034";
ram_buffer(4169) := X"00000000";
ram_buffer(4170) := X"0044102B";
ram_buffer(4171) := X"10400003";
ram_buffer(4172) := X"00041080";
ram_buffer(4173) := X"AF848034";
ram_buffer(4174) := X"00041080";
ram_buffer(4175) := X"00441021";
ram_buffer(4176) := X"3C040100";
ram_buffer(4177) := X"00021080";
ram_buffer(4178) := X"24847D84";
ram_buffer(4179) := X"00822021";
ram_buffer(4180) := X"0C400441";
ram_buffer(4181) := X"02202825";
ram_buffer(4182) := X"8F838010";
ram_buffer(4183) := X"8E02002C";
ram_buffer(4184) := X"8C63002C";
ram_buffer(4185) := X"00000000";
ram_buffer(4186) := X"0043102B";
ram_buffer(4187) := X"1440FFC9";
ram_buffer(4188) := X"00000000";
ram_buffer(4189) := X"0C4001B1";
ram_buffer(4190) := X"00000000";
ram_buffer(4191) := X"1000FFC5";
ram_buffer(4192) := X"00000000";
ram_buffer(4193) := X"8F838010";
ram_buffer(4194) := X"8F848010";
ram_buffer(4195) := X"8C620044";
ram_buffer(4196) := X"00000000";
ram_buffer(4197) := X"2442FFFF";
ram_buffer(4198) := X"AC620044";
ram_buffer(4199) := X"8C820044";
ram_buffer(4200) := X"00000000";
ram_buffer(4201) := X"1440FFC5";
ram_buffer(4202) := X"00000000";
ram_buffer(4203) := X"8FBF001C";
ram_buffer(4204) := X"8FB10018";
ram_buffer(4205) := X"8FB00014";
ram_buffer(4206) := X"08400415";
ram_buffer(4207) := X"27BD0020";
ram_buffer(4208) := X"3C040100";
ram_buffer(4209) := X"0840041F";
ram_buffer(4210) := X"24847C38";
ram_buffer(4211) := X"27BDFFE0";
ram_buffer(4212) := X"AFB00010";
ram_buffer(4213) := X"AFBF001C";
ram_buffer(4214) := X"AFB20018";
ram_buffer(4215) := X"AFB10014";
ram_buffer(4216) := X"1080003F";
ram_buffer(4217) := X"00808025";
ram_buffer(4218) := X"3C020100";
ram_buffer(4219) := X"8E030014";
ram_buffer(4220) := X"24427D20";
ram_buffer(4221) := X"10620009";
ram_buffer(4222) := X"3C040100";
ram_buffer(4223) := X"8FBF001C";
ram_buffer(4224) := X"00008825";
ram_buffer(4225) := X"02201025";
ram_buffer(4226) := X"8FB20018";
ram_buffer(4227) := X"8FB10014";
ram_buffer(4228) := X"8FB00010";
ram_buffer(4229) := X"03E00008";
ram_buffer(4230) := X"27BD0020";
ram_buffer(4231) := X"8E020028";
ram_buffer(4232) := X"24847D48";
ram_buffer(4233) := X"1044FFF5";
ram_buffer(4234) := X"00000000";
ram_buffer(4235) := X"1440FFF3";
ram_buffer(4236) := X"00000000";
ram_buffer(4237) := X"8F828014";
ram_buffer(4238) := X"00000000";
ram_buffer(4239) := X"1440001E";
ram_buffer(4240) := X"00000000";
ram_buffer(4241) := X"8F828010";
ram_buffer(4242) := X"8E11002C";
ram_buffer(4243) := X"8C42002C";
ram_buffer(4244) := X"26120004";
ram_buffer(4245) := X"02402025";
ram_buffer(4246) := X"0C40046F";
ram_buffer(4247) := X"0222882B";
ram_buffer(4248) := X"8E04002C";
ram_buffer(4249) := X"8F828034";
ram_buffer(4250) := X"00000000";
ram_buffer(4251) := X"0044102B";
ram_buffer(4252) := X"10400002";
ram_buffer(4253) := X"3A310001";
ram_buffer(4254) := X"AF848034";
ram_buffer(4255) := X"00041080";
ram_buffer(4256) := X"00441021";
ram_buffer(4257) := X"3C040100";
ram_buffer(4258) := X"00021080";
ram_buffer(4259) := X"24847D84";
ram_buffer(4260) := X"02402825";
ram_buffer(4261) := X"0C400441";
ram_buffer(4262) := X"00822021";
ram_buffer(4263) := X"8FBF001C";
ram_buffer(4264) := X"02201025";
ram_buffer(4265) := X"8FB20018";
ram_buffer(4266) := X"8FB10014";
ram_buffer(4267) := X"8FB00010";
ram_buffer(4268) := X"03E00008";
ram_buffer(4269) := X"27BD0020";
ram_buffer(4270) := X"0C400441";
ram_buffer(4271) := X"26050018";
ram_buffer(4272) := X"8FBF001C";
ram_buffer(4273) := X"00008825";
ram_buffer(4274) := X"02201025";
ram_buffer(4275) := X"8FB20018";
ram_buffer(4276) := X"8FB10014";
ram_buffer(4277) := X"8FB00010";
ram_buffer(4278) := X"03E00008";
ram_buffer(4279) := X"27BD0020";
ram_buffer(4280) := X"3C110100";
ram_buffer(4281) := X"26247C38";
ram_buffer(4282) := X"0C40041F";
ram_buffer(4283) := X"240506E9";
ram_buffer(4284) := X"24050688";
ram_buffer(4285) := X"0C40041F";
ram_buffer(4286) := X"26247C38";
ram_buffer(4287) := X"1000FFBB";
ram_buffer(4288) := X"3C020100";
ram_buffer(4289) := X"27BDFFD8";
ram_buffer(4290) := X"27828018";
ram_buffer(4291) := X"3C050100";
ram_buffer(4292) := X"3C040100";
ram_buffer(4293) := X"00003825";
ram_buffer(4294) := X"AFA20014";
ram_buffer(4295) := X"AFA00010";
ram_buffer(4296) := X"2406012C";
ram_buffer(4297) := X"24A57C50";
ram_buffer(4298) := X"AFBF0024";
ram_buffer(4299) := X"0C400C2B";
ram_buffer(4300) := X"24844C04";
ram_buffer(4301) := X"24030001";
ram_buffer(4302) := X"1043000C";
ram_buffer(4303) := X"2403FFFF";
ram_buffer(4304) := X"10430005";
ram_buffer(4305) := X"2405078B";
ram_buffer(4306) := X"8FBF0024";
ram_buffer(4307) := X"00000000";
ram_buffer(4308) := X"03E00008";
ram_buffer(4309) := X"27BD0028";
ram_buffer(4310) := X"8FBF0024";
ram_buffer(4311) := X"3C040100";
ram_buffer(4312) := X"24847C38";
ram_buffer(4313) := X"0840041F";
ram_buffer(4314) := X"27BD0028";
ram_buffer(4315) := X"0C40041A";
ram_buffer(4316) := X"AFA20018";
ram_buffer(4317) := X"8FA20018";
ram_buffer(4318) := X"8FBF0024";
ram_buffer(4319) := X"2403FFFF";
ram_buffer(4320) := X"27BD0028";
ram_buffer(4321) := X"AF83801C";
ram_buffer(4322) := X"AF828030";
ram_buffer(4323) := X"AF808038";
ram_buffer(4324) := X"08401CBF";
ram_buffer(4325) := X"00000000";
ram_buffer(4326) := X"27BDFFE8";
ram_buffer(4327) := X"AFBF0014";
ram_buffer(4328) := X"0C40041A";
ram_buffer(4329) := X"00000000";
ram_buffer(4330) := X"8FBF0014";
ram_buffer(4331) := X"27BD0018";
ram_buffer(4332) := X"AF808030";
ram_buffer(4333) := X"08401CCB";
ram_buffer(4334) := X"00000000";
ram_buffer(4335) := X"8F828014";
ram_buffer(4336) := X"00000000";
ram_buffer(4337) := X"24420001";
ram_buffer(4338) := X"AF828014";
ram_buffer(4339) := X"03E00008";
ram_buffer(4340) := X"00000000";
ram_buffer(4341) := X"8F828038";
ram_buffer(4342) := X"03E00008";
ram_buffer(4343) := X"00000000";
ram_buffer(4344) := X"8F828038";
ram_buffer(4345) := X"03E00008";
ram_buffer(4346) := X"00000000";
ram_buffer(4347) := X"8F82803C";
ram_buffer(4348) := X"03E00008";
ram_buffer(4349) := X"00000000";
ram_buffer(4350) := X"27BDFFE8";
ram_buffer(4351) := X"AFBF0014";
ram_buffer(4352) := X"10800007";
ram_buffer(4353) := X"AFB00010";
ram_buffer(4354) := X"00808025";
ram_buffer(4355) := X"8FBF0014";
ram_buffer(4356) := X"26020034";
ram_buffer(4357) := X"8FB00010";
ram_buffer(4358) := X"03E00008";
ram_buffer(4359) := X"27BD0018";
ram_buffer(4360) := X"8F908010";
ram_buffer(4361) := X"00000000";
ram_buffer(4362) := X"1600FFF8";
ram_buffer(4363) := X"3C040100";
ram_buffer(4364) := X"24050893";
ram_buffer(4365) := X"0C40041F";
ram_buffer(4366) := X"24847C38";
ram_buffer(4367) := X"8FBF0014";
ram_buffer(4368) := X"26020034";
ram_buffer(4369) := X"8FB00010";
ram_buffer(4370) := X"03E00008";
ram_buffer(4371) := X"27BD0018";
ram_buffer(4372) := X"8F828018";
ram_buffer(4373) := X"27BDFFE8";
ram_buffer(4374) := X"10400005";
ram_buffer(4375) := X"AFBF0014";
ram_buffer(4376) := X"8FBF0014";
ram_buffer(4377) := X"00000000";
ram_buffer(4378) := X"03E00008";
ram_buffer(4379) := X"27BD0018";
ram_buffer(4380) := X"3C040100";
ram_buffer(4381) := X"24050966";
ram_buffer(4382) := X"0C40041F";
ram_buffer(4383) := X"24847C38";
ram_buffer(4384) := X"8FBF0014";
ram_buffer(4385) := X"8F828018";
ram_buffer(4386) := X"03E00008";
ram_buffer(4387) := X"27BD0018";
ram_buffer(4388) := X"8F828014";
ram_buffer(4389) := X"27BDFFD8";
ram_buffer(4390) := X"AFBF0024";
ram_buffer(4391) := X"AFB40020";
ram_buffer(4392) := X"AFB3001C";
ram_buffer(4393) := X"AFB20018";
ram_buffer(4394) := X"AFB10014";
ram_buffer(4395) := X"14400073";
ram_buffer(4396) := X"AFB00010";
ram_buffer(4397) := X"8F918038";
ram_buffer(4398) := X"00000000";
ram_buffer(4399) := X"26310001";
ram_buffer(4400) := X"AF918038";
ram_buffer(4401) := X"16200017";
ram_buffer(4402) := X"00000000";
ram_buffer(4403) := X"8F828048";
ram_buffer(4404) := X"00000000";
ram_buffer(4405) := X"8C420000";
ram_buffer(4406) := X"00000000";
ram_buffer(4407) := X"1440006D";
ram_buffer(4408) := X"3C040100";
ram_buffer(4409) := X"8F828048";
ram_buffer(4410) := X"8F838044";
ram_buffer(4411) := X"00000000";
ram_buffer(4412) := X"AF838048";
ram_buffer(4413) := X"AF828044";
ram_buffer(4414) := X"8F828024";
ram_buffer(4415) := X"00000000";
ram_buffer(4416) := X"24420001";
ram_buffer(4417) := X"AF828024";
ram_buffer(4418) := X"8F828048";
ram_buffer(4419) := X"00000000";
ram_buffer(4420) := X"8C420000";
ram_buffer(4421) := X"00000000";
ram_buffer(4422) := X"14400063";
ram_buffer(4423) := X"2402FFFF";
ram_buffer(4424) := X"AF82801C";
ram_buffer(4425) := X"8F82801C";
ram_buffer(4426) := X"3C120100";
ram_buffer(4427) := X"0222102B";
ram_buffer(4428) := X"00009825";
ram_buffer(4429) := X"14400035";
ram_buffer(4430) := X"26527D84";
ram_buffer(4431) := X"8F828048";
ram_buffer(4432) := X"00000000";
ram_buffer(4433) := X"8C420000";
ram_buffer(4434) := X"00000000";
ram_buffer(4435) := X"1040002E";
ram_buffer(4436) := X"2402FFFF";
ram_buffer(4437) := X"8F828048";
ram_buffer(4438) := X"00000000";
ram_buffer(4439) := X"8C42000C";
ram_buffer(4440) := X"00000000";
ram_buffer(4441) := X"8C50000C";
ram_buffer(4442) := X"00000000";
ram_buffer(4443) := X"8E020004";
ram_buffer(4444) := X"26140004";
ram_buffer(4445) := X"0222182B";
ram_buffer(4446) := X"14600056";
ram_buffer(4447) := X"02802025";
ram_buffer(4448) := X"0C40046F";
ram_buffer(4449) := X"00000000";
ram_buffer(4450) := X"8E020028";
ram_buffer(4451) := X"00000000";
ram_buffer(4452) := X"10400003";
ram_buffer(4453) := X"26040018";
ram_buffer(4454) := X"0C40046F";
ram_buffer(4455) := X"00000000";
ram_buffer(4456) := X"8E02002C";
ram_buffer(4457) := X"8F838034";
ram_buffer(4458) := X"00022080";
ram_buffer(4459) := X"00822021";
ram_buffer(4460) := X"00042080";
ram_buffer(4461) := X"0062182B";
ram_buffer(4462) := X"02802825";
ram_buffer(4463) := X"10600002";
ram_buffer(4464) := X"02442021";
ram_buffer(4465) := X"AF828034";
ram_buffer(4466) := X"0C400441";
ram_buffer(4467) := X"00000000";
ram_buffer(4468) := X"8F838010";
ram_buffer(4469) := X"8E02002C";
ram_buffer(4470) := X"8C63002C";
ram_buffer(4471) := X"00000000";
ram_buffer(4472) := X"0043102B";
ram_buffer(4473) := X"1440FFD5";
ram_buffer(4474) := X"00000000";
ram_buffer(4475) := X"8F828048";
ram_buffer(4476) := X"00000000";
ram_buffer(4477) := X"8C420000";
ram_buffer(4478) := X"00000000";
ram_buffer(4479) := X"1440FFD5";
ram_buffer(4480) := X"24130001";
ram_buffer(4481) := X"2402FFFF";
ram_buffer(4482) := X"AF82801C";
ram_buffer(4483) := X"8F828010";
ram_buffer(4484) := X"00000000";
ram_buffer(4485) := X"8C43002C";
ram_buffer(4486) := X"00000000";
ram_buffer(4487) := X"00031080";
ram_buffer(4488) := X"00431021";
ram_buffer(4489) := X"00021080";
ram_buffer(4490) := X"02429021";
ram_buffer(4491) := X"8E420000";
ram_buffer(4492) := X"00000000";
ram_buffer(4493) := X"2C420002";
ram_buffer(4494) := X"14400002";
ram_buffer(4495) := X"00000000";
ram_buffer(4496) := X"24130001";
ram_buffer(4497) := X"8F828028";
ram_buffer(4498) := X"00000000";
ram_buffer(4499) := X"10400002";
ram_buffer(4500) := X"00000000";
ram_buffer(4501) := X"24130001";
ram_buffer(4502) := X"8FBF0024";
ram_buffer(4503) := X"02601025";
ram_buffer(4504) := X"8FB40020";
ram_buffer(4505) := X"8FB3001C";
ram_buffer(4506) := X"8FB20018";
ram_buffer(4507) := X"8FB10014";
ram_buffer(4508) := X"8FB00010";
ram_buffer(4509) := X"03E00008";
ram_buffer(4510) := X"27BD0028";
ram_buffer(4511) := X"8F82802C";
ram_buffer(4512) := X"00009825";
ram_buffer(4513) := X"24420001";
ram_buffer(4514) := X"AF82802C";
ram_buffer(4515) := X"1000FFED";
ram_buffer(4516) := X"00000000";
ram_buffer(4517) := X"240509E4";
ram_buffer(4518) := X"0C40041F";
ram_buffer(4519) := X"24847C38";
ram_buffer(4520) := X"1000FF90";
ram_buffer(4521) := X"00000000";
ram_buffer(4522) := X"8F828048";
ram_buffer(4523) := X"00000000";
ram_buffer(4524) := X"8C42000C";
ram_buffer(4525) := X"00000000";
ram_buffer(4526) := X"8C42000C";
ram_buffer(4527) := X"00000000";
ram_buffer(4528) := X"8C420004";
ram_buffer(4529) := X"00000000";
ram_buffer(4530) := X"AF82801C";
ram_buffer(4531) := X"1000FF95";
ram_buffer(4532) := X"00000000";
ram_buffer(4533) := X"AF82801C";
ram_buffer(4534) := X"8F828010";
ram_buffer(4535) := X"00000000";
ram_buffer(4536) := X"8C43002C";
ram_buffer(4537) := X"00000000";
ram_buffer(4538) := X"00031080";
ram_buffer(4539) := X"00431021";
ram_buffer(4540) := X"00021080";
ram_buffer(4541) := X"02429021";
ram_buffer(4542) := X"8E420000";
ram_buffer(4543) := X"00000000";
ram_buffer(4544) := X"2C420002";
ram_buffer(4545) := X"1040FFCE";
ram_buffer(4546) := X"00000000";
ram_buffer(4547) := X"1000FFCD";
ram_buffer(4548) := X"00000000";
ram_buffer(4549) := X"8F828014";
ram_buffer(4550) := X"27BDFFC8";
ram_buffer(4551) := X"AFBF0034";
ram_buffer(4552) := X"AFB50030";
ram_buffer(4553) := X"AFB4002C";
ram_buffer(4554) := X"AFB30028";
ram_buffer(4555) := X"AFB20024";
ram_buffer(4556) := X"AFB10020";
ram_buffer(4557) := X"10400081";
ram_buffer(4558) := X"AFB0001C";
ram_buffer(4559) := X"0C40041A";
ram_buffer(4560) := X"00000000";
ram_buffer(4561) := X"8F828030";
ram_buffer(4562) := X"00000000";
ram_buffer(4563) := X"14400074";
ram_buffer(4564) := X"00000000";
ram_buffer(4565) := X"8F828014";
ram_buffer(4566) := X"00000000";
ram_buffer(4567) := X"2442FFFF";
ram_buffer(4568) := X"AF828014";
ram_buffer(4569) := X"8F828014";
ram_buffer(4570) := X"00000000";
ram_buffer(4571) := X"1440004A";
ram_buffer(4572) := X"00001025";
ram_buffer(4573) := X"8F82803C";
ram_buffer(4574) := X"00000000";
ram_buffer(4575) := X"10400046";
ram_buffer(4576) := X"00001025";
ram_buffer(4577) := X"3C120100";
ram_buffer(4578) := X"3C110100";
ram_buffer(4579) := X"00008025";
ram_buffer(4580) := X"26537D48";
ram_buffer(4581) := X"26317D84";
ram_buffer(4582) := X"24140001";
ram_buffer(4583) := X"8E427D48";
ram_buffer(4584) := X"00000000";
ram_buffer(4585) := X"10400021";
ram_buffer(4586) := X"00000000";
ram_buffer(4587) := X"8E62000C";
ram_buffer(4588) := X"00000000";
ram_buffer(4589) := X"8C50000C";
ram_buffer(4590) := X"00000000";
ram_buffer(4591) := X"26040018";
ram_buffer(4592) := X"0C40046F";
ram_buffer(4593) := X"26150004";
ram_buffer(4594) := X"0C40046F";
ram_buffer(4595) := X"02A02025";
ram_buffer(4596) := X"8E02002C";
ram_buffer(4597) := X"8F838034";
ram_buffer(4598) := X"00022080";
ram_buffer(4599) := X"00822021";
ram_buffer(4600) := X"00042080";
ram_buffer(4601) := X"0062182B";
ram_buffer(4602) := X"02A02825";
ram_buffer(4603) := X"10600002";
ram_buffer(4604) := X"02242021";
ram_buffer(4605) := X"AF828034";
ram_buffer(4606) := X"0C400441";
ram_buffer(4607) := X"00000000";
ram_buffer(4608) := X"8F838010";
ram_buffer(4609) := X"8E02002C";
ram_buffer(4610) := X"8C63002C";
ram_buffer(4611) := X"00000000";
ram_buffer(4612) := X"0043102B";
ram_buffer(4613) := X"1440FFE1";
ram_buffer(4614) := X"00000000";
ram_buffer(4615) := X"8E427D48";
ram_buffer(4616) := X"AF948028";
ram_buffer(4617) := X"1440FFE1";
ram_buffer(4618) := X"00000000";
ram_buffer(4619) := X"12000008";
ram_buffer(4620) := X"00000000";
ram_buffer(4621) := X"8F828048";
ram_buffer(4622) := X"00000000";
ram_buffer(4623) := X"8C420000";
ram_buffer(4624) := X"00000000";
ram_buffer(4625) := X"14400047";
ram_buffer(4626) := X"2402FFFF";
ram_buffer(4627) := X"AF82801C";
ram_buffer(4628) := X"8F90802C";
ram_buffer(4629) := X"00000000";
ram_buffer(4630) := X"1200000A";
ram_buffer(4631) := X"00000000";
ram_buffer(4632) := X"24110001";
ram_buffer(4633) := X"0C401124";
ram_buffer(4634) := X"2610FFFF";
ram_buffer(4635) := X"10400002";
ram_buffer(4636) := X"00000000";
ram_buffer(4637) := X"AF918028";
ram_buffer(4638) := X"1600FFFA";
ram_buffer(4639) := X"00000000";
ram_buffer(4640) := X"AF80802C";
ram_buffer(4641) := X"8F828028";
ram_buffer(4642) := X"00000000";
ram_buffer(4643) := X"14400031";
ram_buffer(4644) := X"00000000";
ram_buffer(4645) := X"00001025";
ram_buffer(4646) := X"8F838030";
ram_buffer(4647) := X"00000000";
ram_buffer(4648) := X"10600007";
ram_buffer(4649) := X"00000000";
ram_buffer(4650) := X"8F838010";
ram_buffer(4651) := X"00000000";
ram_buffer(4652) := X"8C630044";
ram_buffer(4653) := X"00000000";
ram_buffer(4654) := X"1460000A";
ram_buffer(4655) := X"00000000";
ram_buffer(4656) := X"8FBF0034";
ram_buffer(4657) := X"8FB50030";
ram_buffer(4658) := X"8FB4002C";
ram_buffer(4659) := X"8FB30028";
ram_buffer(4660) := X"8FB20024";
ram_buffer(4661) := X"8FB10020";
ram_buffer(4662) := X"8FB0001C";
ram_buffer(4663) := X"03E00008";
ram_buffer(4664) := X"27BD0038";
ram_buffer(4665) := X"8F848010";
ram_buffer(4666) := X"8F858010";
ram_buffer(4667) := X"8C830044";
ram_buffer(4668) := X"00000000";
ram_buffer(4669) := X"2463FFFF";
ram_buffer(4670) := X"AC830044";
ram_buffer(4671) := X"8CA30044";
ram_buffer(4672) := X"00000000";
ram_buffer(4673) := X"1460FFEE";
ram_buffer(4674) := X"00000000";
ram_buffer(4675) := X"0C400415";
ram_buffer(4676) := X"AFA20010";
ram_buffer(4677) := X"8FA20010";
ram_buffer(4678) := X"1000FFE9";
ram_buffer(4679) := X"00000000";
ram_buffer(4680) := X"8F838010";
ram_buffer(4681) := X"8F828010";
ram_buffer(4682) := X"8C620044";
ram_buffer(4683) := X"00000000";
ram_buffer(4684) := X"24420001";
ram_buffer(4685) := X"1000FF87";
ram_buffer(4686) := X"AC620044";
ram_buffer(4687) := X"3C040100";
ram_buffer(4688) := X"240507EF";
ram_buffer(4689) := X"0C40041F";
ram_buffer(4690) := X"24847C38";
ram_buffer(4691) := X"1000FF7B";
ram_buffer(4692) := X"00000000";
ram_buffer(4693) := X"0C4001B1";
ram_buffer(4694) := X"00000000";
ram_buffer(4695) := X"1000FFCE";
ram_buffer(4696) := X"24020001";
ram_buffer(4697) := X"8F828048";
ram_buffer(4698) := X"00000000";
ram_buffer(4699) := X"8C42000C";
ram_buffer(4700) := X"00000000";
ram_buffer(4701) := X"8C42000C";
ram_buffer(4702) := X"00000000";
ram_buffer(4703) := X"8C420004";
ram_buffer(4704) := X"00000000";
ram_buffer(4705) := X"AF82801C";
ram_buffer(4706) := X"1000FFB1";
ram_buffer(4707) := X"00000000";
ram_buffer(4708) := X"27BDFFE0";
ram_buffer(4709) := X"AFB10014";
ram_buffer(4710) := X"AFB00010";
ram_buffer(4711) := X"AFBF001C";
ram_buffer(4712) := X"AFB20018";
ram_buffer(4713) := X"00808825";
ram_buffer(4714) := X"10800052";
ram_buffer(4715) := X"00A08025";
ram_buffer(4716) := X"12000045";
ram_buffer(4717) := X"3C040100";
ram_buffer(4718) := X"8F828014";
ram_buffer(4719) := X"00000000";
ram_buffer(4720) := X"1440003C";
ram_buffer(4721) := X"3C040100";
ram_buffer(4722) := X"8F838014";
ram_buffer(4723) := X"8E220000";
ram_buffer(4724) := X"24630001";
ram_buffer(4725) := X"AF838014";
ram_buffer(4726) := X"8F838038";
ram_buffer(4727) := X"02028021";
ram_buffer(4728) := X"0062202B";
ram_buffer(4729) := X"1080000E";
ram_buffer(4730) := X"0202102B";
ram_buffer(4731) := X"1440000E";
ram_buffer(4732) := X"0070102B";
ram_buffer(4733) := X"AE300000";
ram_buffer(4734) := X"0C4011C5";
ram_buffer(4735) := X"00000000";
ram_buffer(4736) := X"10400026";
ram_buffer(4737) := X"00000000";
ram_buffer(4738) := X"8FBF001C";
ram_buffer(4739) := X"8FB20018";
ram_buffer(4740) := X"8FB10014";
ram_buffer(4741) := X"8FB00010";
ram_buffer(4742) := X"03E00008";
ram_buffer(4743) := X"27BD0020";
ram_buffer(4744) := X"14400003";
ram_buffer(4745) := X"0070102B";
ram_buffer(4746) := X"1040FFF2";
ram_buffer(4747) := X"00000000";
ram_buffer(4748) := X"8F928038";
ram_buffer(4749) := X"8F828010";
ram_buffer(4750) := X"8F848010";
ram_buffer(4751) := X"AE300000";
ram_buffer(4752) := X"24840004";
ram_buffer(4753) := X"02438823";
ram_buffer(4754) := X"0C40046F";
ram_buffer(4755) := X"A0400055";
ram_buffer(4756) := X"02118021";
ram_buffer(4757) := X"8F828010";
ram_buffer(4758) := X"0212902B";
ram_buffer(4759) := X"1640001F";
ram_buffer(4760) := X"AC500004";
ram_buffer(4761) := X"8F848048";
ram_buffer(4762) := X"8F858010";
ram_buffer(4763) := X"0C40044D";
ram_buffer(4764) := X"24A50004";
ram_buffer(4765) := X"8F82801C";
ram_buffer(4766) := X"00000000";
ram_buffer(4767) := X"0202102B";
ram_buffer(4768) := X"1040FFDD";
ram_buffer(4769) := X"00000000";
ram_buffer(4770) := X"AF90801C";
ram_buffer(4771) := X"0C4011C5";
ram_buffer(4772) := X"00000000";
ram_buffer(4773) := X"1440FFDC";
ram_buffer(4774) := X"00000000";
ram_buffer(4775) := X"8FBF001C";
ram_buffer(4776) := X"8FB20018";
ram_buffer(4777) := X"8FB10014";
ram_buffer(4778) := X"8FB00010";
ram_buffer(4779) := X"084001B1";
ram_buffer(4780) := X"27BD0020";
ram_buffer(4781) := X"2405047B";
ram_buffer(4782) := X"0C40041F";
ram_buffer(4783) := X"24847C38";
ram_buffer(4784) := X"1000FFC1";
ram_buffer(4785) := X"00000000";
ram_buffer(4786) := X"2405047A";
ram_buffer(4787) := X"0C40041F";
ram_buffer(4788) := X"24847C38";
ram_buffer(4789) := X"1000FFB8";
ram_buffer(4790) := X"00000000";
ram_buffer(4791) := X"8F848044";
ram_buffer(4792) := X"8F858010";
ram_buffer(4793) := X"0C40044D";
ram_buffer(4794) := X"24A50004";
ram_buffer(4795) := X"1000FFC2";
ram_buffer(4796) := X"00000000";
ram_buffer(4797) := X"3C040100";
ram_buffer(4798) := X"24050479";
ram_buffer(4799) := X"0C40041F";
ram_buffer(4800) := X"24847C38";
ram_buffer(4801) := X"1000FFAA";
ram_buffer(4802) := X"00000000";
ram_buffer(4803) := X"14800003";
ram_buffer(4804) := X"00000000";
ram_buffer(4805) := X"084001B1";
ram_buffer(4806) := X"00000000";
ram_buffer(4807) := X"8F828014";
ram_buffer(4808) := X"27BDFFE0";
ram_buffer(4809) := X"AFB00014";
ram_buffer(4810) := X"AFBF001C";
ram_buffer(4811) := X"AFB10018";
ram_buffer(4812) := X"1440002E";
ram_buffer(4813) := X"00808025";
ram_buffer(4814) := X"8F828014";
ram_buffer(4815) := X"00000000";
ram_buffer(4816) := X"24420001";
ram_buffer(4817) := X"AF828014";
ram_buffer(4818) := X"8F918038";
ram_buffer(4819) := X"8F828010";
ram_buffer(4820) := X"8F848010";
ram_buffer(4821) := X"A0400055";
ram_buffer(4822) := X"0C40046F";
ram_buffer(4823) := X"24840004";
ram_buffer(4824) := X"02118021";
ram_buffer(4825) := X"8F828010";
ram_buffer(4826) := X"0211882B";
ram_buffer(4827) := X"16200019";
ram_buffer(4828) := X"AC500004";
ram_buffer(4829) := X"8F848048";
ram_buffer(4830) := X"8F858010";
ram_buffer(4831) := X"0C40044D";
ram_buffer(4832) := X"24A50004";
ram_buffer(4833) := X"8F82801C";
ram_buffer(4834) := X"00000000";
ram_buffer(4835) := X"0202102B";
ram_buffer(4836) := X"10400002";
ram_buffer(4837) := X"00000000";
ram_buffer(4838) := X"AF90801C";
ram_buffer(4839) := X"0C4011C5";
ram_buffer(4840) := X"00000000";
ram_buffer(4841) := X"10400006";
ram_buffer(4842) := X"00000000";
ram_buffer(4843) := X"8FBF001C";
ram_buffer(4844) := X"8FB10018";
ram_buffer(4845) := X"8FB00014";
ram_buffer(4846) := X"03E00008";
ram_buffer(4847) := X"27BD0020";
ram_buffer(4848) := X"8FBF001C";
ram_buffer(4849) := X"8FB10018";
ram_buffer(4850) := X"8FB00014";
ram_buffer(4851) := X"084001B1";
ram_buffer(4852) := X"27BD0020";
ram_buffer(4853) := X"8F848044";
ram_buffer(4854) := X"8F858010";
ram_buffer(4855) := X"0C40044D";
ram_buffer(4856) := X"24A50004";
ram_buffer(4857) := X"1000FFED";
ram_buffer(4858) := X"00000000";
ram_buffer(4859) := X"3C040100";
ram_buffer(4860) := X"240504D6";
ram_buffer(4861) := X"0C40041F";
ram_buffer(4862) := X"24847C38";
ram_buffer(4863) := X"1000FFCE";
ram_buffer(4864) := X"00000000";
ram_buffer(4865) := X"27BDFFD8";
ram_buffer(4866) := X"AFB10018";
ram_buffer(4867) := X"3C110100";
ram_buffer(4868) := X"AFB30020";
ram_buffer(4869) := X"AFB2001C";
ram_buffer(4870) := X"AFBF0024";
ram_buffer(4871) := X"AFB00014";
ram_buffer(4872) := X"26337D34";
ram_buffer(4873) := X"10000009";
ram_buffer(4874) := X"3C120100";
ram_buffer(4875) := X"8F828014";
ram_buffer(4876) := X"8E307D34";
ram_buffer(4877) := X"24420001";
ram_buffer(4878) := X"AF828014";
ram_buffer(4879) := X"0C4011C5";
ram_buffer(4880) := X"00000000";
ram_buffer(4881) := X"1600000E";
ram_buffer(4882) := X"00000000";
ram_buffer(4883) := X"8F828040";
ram_buffer(4884) := X"00000000";
ram_buffer(4885) := X"1440FFF5";
ram_buffer(4886) := X"00000000";
ram_buffer(4887) := X"8E427D84";
ram_buffer(4888) := X"00000000";
ram_buffer(4889) := X"2C420002";
ram_buffer(4890) := X"1440FFF8";
ram_buffer(4891) := X"00000000";
ram_buffer(4892) := X"0C4001B1";
ram_buffer(4893) := X"00000000";
ram_buffer(4894) := X"1000FFF4";
ram_buffer(4895) := X"00000000";
ram_buffer(4896) := X"0C40041A";
ram_buffer(4897) := X"00000000";
ram_buffer(4898) := X"8F828030";
ram_buffer(4899) := X"00000000";
ram_buffer(4900) := X"1440001F";
ram_buffer(4901) := X"00000000";
ram_buffer(4902) := X"8E62000C";
ram_buffer(4903) := X"00000000";
ram_buffer(4904) := X"8C50000C";
ram_buffer(4905) := X"0C40046F";
ram_buffer(4906) := X"26040004";
ram_buffer(4907) := X"8F82803C";
ram_buffer(4908) := X"00000000";
ram_buffer(4909) := X"2442FFFF";
ram_buffer(4910) := X"AF82803C";
ram_buffer(4911) := X"8F828040";
ram_buffer(4912) := X"00000000";
ram_buffer(4913) := X"2442FFFF";
ram_buffer(4914) := X"AF828040";
ram_buffer(4915) := X"8F828030";
ram_buffer(4916) := X"00000000";
ram_buffer(4917) := X"10400007";
ram_buffer(4918) := X"00000000";
ram_buffer(4919) := X"8F828010";
ram_buffer(4920) := X"00000000";
ram_buffer(4921) := X"8C420044";
ram_buffer(4922) := X"00000000";
ram_buffer(4923) := X"1440000F";
ram_buffer(4924) := X"00000000";
ram_buffer(4925) := X"8E040030";
ram_buffer(4926) := X"0C401D6D";
ram_buffer(4927) := X"00000000";
ram_buffer(4928) := X"0C401D6D";
ram_buffer(4929) := X"02002025";
ram_buffer(4930) := X"1000FFD0";
ram_buffer(4931) := X"00000000";
ram_buffer(4932) := X"8F838010";
ram_buffer(4933) := X"8F828010";
ram_buffer(4934) := X"8C620044";
ram_buffer(4935) := X"00000000";
ram_buffer(4936) := X"24420001";
ram_buffer(4937) := X"1000FFDC";
ram_buffer(4938) := X"AC620044";
ram_buffer(4939) := X"8F838010";
ram_buffer(4940) := X"8F848010";
ram_buffer(4941) := X"8C620044";
ram_buffer(4942) := X"00000000";
ram_buffer(4943) := X"2442FFFF";
ram_buffer(4944) := X"AC620044";
ram_buffer(4945) := X"8C820044";
ram_buffer(4946) := X"00000000";
ram_buffer(4947) := X"1440FFE9";
ram_buffer(4948) := X"00000000";
ram_buffer(4949) := X"0C400415";
ram_buffer(4950) := X"00000000";
ram_buffer(4951) := X"1000FFE5";
ram_buffer(4952) := X"00000000";
ram_buffer(4953) := X"27BDFFE0";
ram_buffer(4954) := X"AFB10018";
ram_buffer(4955) := X"AFBF001C";
ram_buffer(4956) := X"AFB00014";
ram_buffer(4957) := X"0C401EF9";
ram_buffer(4958) := X"00808825";
ram_buffer(4959) := X"2C420010";
ram_buffer(4960) := X"10400127";
ram_buffer(4961) := X"3C040100";
ram_buffer(4962) := X"8F828014";
ram_buffer(4963) := X"3C040100";
ram_buffer(4964) := X"24420001";
ram_buffer(4965) := X"3C070100";
ram_buffer(4966) := X"AF828014";
ram_buffer(4967) := X"24847DDC";
ram_buffer(4968) := X"24E77D78";
ram_buffer(4969) := X"8C82FFF8";
ram_buffer(4970) := X"00000000";
ram_buffer(4971) := X"10400087";
ram_buffer(4972) := X"00000000";
ram_buffer(4973) := X"8C82FFFC";
ram_buffer(4974) := X"00000000";
ram_buffer(4975) := X"8C420004";
ram_buffer(4976) := X"00000000";
ram_buffer(4977) := X"1044007E";
ram_buffer(4978) := X"AC82FFFC";
ram_buffer(4979) := X"8C46000C";
ram_buffer(4980) := X"10000074";
ram_buffer(4981) := X"00000000";
ram_buffer(4982) := X"8C50000C";
ram_buffer(4983) := X"82230000";
ram_buffer(4984) := X"82050034";
ram_buffer(4985) := X"00000000";
ram_buffer(4986) := X"1465006C";
ram_buffer(4987) := X"00000000";
ram_buffer(4988) := X"10600103";
ram_buffer(4989) := X"00000000";
ram_buffer(4990) := X"82050035";
ram_buffer(4991) := X"82230001";
ram_buffer(4992) := X"00000000";
ram_buffer(4993) := X"14650065";
ram_buffer(4994) := X"00000000";
ram_buffer(4995) := X"106000FC";
ram_buffer(4996) := X"00000000";
ram_buffer(4997) := X"82050036";
ram_buffer(4998) := X"82230002";
ram_buffer(4999) := X"00000000";
ram_buffer(5000) := X"1465005E";
ram_buffer(5001) := X"00000000";
ram_buffer(5002) := X"106000F5";
ram_buffer(5003) := X"00000000";
ram_buffer(5004) := X"82050037";
ram_buffer(5005) := X"82230003";
ram_buffer(5006) := X"00000000";
ram_buffer(5007) := X"14650057";
ram_buffer(5008) := X"00000000";
ram_buffer(5009) := X"106000EE";
ram_buffer(5010) := X"00000000";
ram_buffer(5011) := X"82050038";
ram_buffer(5012) := X"82230004";
ram_buffer(5013) := X"00000000";
ram_buffer(5014) := X"14650050";
ram_buffer(5015) := X"00000000";
ram_buffer(5016) := X"106000E7";
ram_buffer(5017) := X"00000000";
ram_buffer(5018) := X"82050039";
ram_buffer(5019) := X"82230005";
ram_buffer(5020) := X"00000000";
ram_buffer(5021) := X"14650049";
ram_buffer(5022) := X"00000000";
ram_buffer(5023) := X"106000E0";
ram_buffer(5024) := X"00000000";
ram_buffer(5025) := X"8205003A";
ram_buffer(5026) := X"82230006";
ram_buffer(5027) := X"00000000";
ram_buffer(5028) := X"14650042";
ram_buffer(5029) := X"00000000";
ram_buffer(5030) := X"106000D9";
ram_buffer(5031) := X"00000000";
ram_buffer(5032) := X"8205003B";
ram_buffer(5033) := X"82230007";
ram_buffer(5034) := X"00000000";
ram_buffer(5035) := X"1465003B";
ram_buffer(5036) := X"00000000";
ram_buffer(5037) := X"106000D2";
ram_buffer(5038) := X"00000000";
ram_buffer(5039) := X"8205003C";
ram_buffer(5040) := X"82230008";
ram_buffer(5041) := X"00000000";
ram_buffer(5042) := X"14650034";
ram_buffer(5043) := X"00000000";
ram_buffer(5044) := X"106000CB";
ram_buffer(5045) := X"00000000";
ram_buffer(5046) := X"8205003D";
ram_buffer(5047) := X"82230009";
ram_buffer(5048) := X"00000000";
ram_buffer(5049) := X"1465002D";
ram_buffer(5050) := X"00000000";
ram_buffer(5051) := X"106000C4";
ram_buffer(5052) := X"00000000";
ram_buffer(5053) := X"8205003E";
ram_buffer(5054) := X"8223000A";
ram_buffer(5055) := X"00000000";
ram_buffer(5056) := X"14650026";
ram_buffer(5057) := X"00000000";
ram_buffer(5058) := X"106000BD";
ram_buffer(5059) := X"00000000";
ram_buffer(5060) := X"8205003F";
ram_buffer(5061) := X"8223000B";
ram_buffer(5062) := X"00000000";
ram_buffer(5063) := X"1465001F";
ram_buffer(5064) := X"00000000";
ram_buffer(5065) := X"106000B6";
ram_buffer(5066) := X"00000000";
ram_buffer(5067) := X"82050040";
ram_buffer(5068) := X"8223000C";
ram_buffer(5069) := X"00000000";
ram_buffer(5070) := X"14650018";
ram_buffer(5071) := X"00000000";
ram_buffer(5072) := X"106000AF";
ram_buffer(5073) := X"00000000";
ram_buffer(5074) := X"82050041";
ram_buffer(5075) := X"8223000D";
ram_buffer(5076) := X"00000000";
ram_buffer(5077) := X"14650011";
ram_buffer(5078) := X"00000000";
ram_buffer(5079) := X"106000A8";
ram_buffer(5080) := X"00000000";
ram_buffer(5081) := X"82050042";
ram_buffer(5082) := X"8223000E";
ram_buffer(5083) := X"00000000";
ram_buffer(5084) := X"1465000A";
ram_buffer(5085) := X"00000000";
ram_buffer(5086) := X"106000A1";
ram_buffer(5087) := X"00000000";
ram_buffer(5088) := X"82050043";
ram_buffer(5089) := X"8223000F";
ram_buffer(5090) := X"00000000";
ram_buffer(5091) := X"14650003";
ram_buffer(5092) := X"00000000";
ram_buffer(5093) := X"1060009A";
ram_buffer(5094) := X"00000000";
ram_buffer(5095) := X"10D0000B";
ram_buffer(5096) := X"00000000";
ram_buffer(5097) := X"8C420004";
ram_buffer(5098) := X"00000000";
ram_buffer(5099) := X"1444FF8A";
ram_buffer(5100) := X"AC82FFFC";
ram_buffer(5101) := X"8C420004";
ram_buffer(5102) := X"1000FF87";
ram_buffer(5103) := X"AC82FFFC";
ram_buffer(5104) := X"8C820004";
ram_buffer(5105) := X"1000FF81";
ram_buffer(5106) := X"00000000";
ram_buffer(5107) := X"2484FFEC";
ram_buffer(5108) := X"1487FF74";
ram_buffer(5109) := X"00000000";
ram_buffer(5110) := X"8F838048";
ram_buffer(5111) := X"00000000";
ram_buffer(5112) := X"8C620000";
ram_buffer(5113) := X"00000000";
ram_buffer(5114) := X"10400092";
ram_buffer(5115) := X"24640008";
ram_buffer(5116) := X"8C620004";
ram_buffer(5117) := X"00000000";
ram_buffer(5118) := X"8C420004";
ram_buffer(5119) := X"00000000";
ram_buffer(5120) := X"1044022A";
ram_buffer(5121) := X"AC620004";
ram_buffer(5122) := X"8C46000C";
ram_buffer(5123) := X"10000074";
ram_buffer(5124) := X"00000000";
ram_buffer(5125) := X"8C50000C";
ram_buffer(5126) := X"82250000";
ram_buffer(5127) := X"82070034";
ram_buffer(5128) := X"00000000";
ram_buffer(5129) := X"14A7006C";
ram_buffer(5130) := X"00000000";
ram_buffer(5131) := X"10A00074";
ram_buffer(5132) := X"00000000";
ram_buffer(5133) := X"82070035";
ram_buffer(5134) := X"82250001";
ram_buffer(5135) := X"00000000";
ram_buffer(5136) := X"14A70065";
ram_buffer(5137) := X"00000000";
ram_buffer(5138) := X"10A0006D";
ram_buffer(5139) := X"00000000";
ram_buffer(5140) := X"82070036";
ram_buffer(5141) := X"82250002";
ram_buffer(5142) := X"00000000";
ram_buffer(5143) := X"14A7005E";
ram_buffer(5144) := X"00000000";
ram_buffer(5145) := X"10A00066";
ram_buffer(5146) := X"00000000";
ram_buffer(5147) := X"82070037";
ram_buffer(5148) := X"82250003";
ram_buffer(5149) := X"00000000";
ram_buffer(5150) := X"14A70057";
ram_buffer(5151) := X"00000000";
ram_buffer(5152) := X"10A0005F";
ram_buffer(5153) := X"00000000";
ram_buffer(5154) := X"82070038";
ram_buffer(5155) := X"82250004";
ram_buffer(5156) := X"00000000";
ram_buffer(5157) := X"14A70050";
ram_buffer(5158) := X"00000000";
ram_buffer(5159) := X"10A00058";
ram_buffer(5160) := X"00000000";
ram_buffer(5161) := X"82070039";
ram_buffer(5162) := X"82250005";
ram_buffer(5163) := X"00000000";
ram_buffer(5164) := X"14A70049";
ram_buffer(5165) := X"00000000";
ram_buffer(5166) := X"10A00051";
ram_buffer(5167) := X"00000000";
ram_buffer(5168) := X"8207003A";
ram_buffer(5169) := X"82250006";
ram_buffer(5170) := X"00000000";
ram_buffer(5171) := X"14A70042";
ram_buffer(5172) := X"00000000";
ram_buffer(5173) := X"10A0004A";
ram_buffer(5174) := X"00000000";
ram_buffer(5175) := X"8207003B";
ram_buffer(5176) := X"82250007";
ram_buffer(5177) := X"00000000";
ram_buffer(5178) := X"14A7003B";
ram_buffer(5179) := X"00000000";
ram_buffer(5180) := X"10A00043";
ram_buffer(5181) := X"00000000";
ram_buffer(5182) := X"8207003C";
ram_buffer(5183) := X"82250008";
ram_buffer(5184) := X"00000000";
ram_buffer(5185) := X"14A70034";
ram_buffer(5186) := X"00000000";
ram_buffer(5187) := X"10A0003C";
ram_buffer(5188) := X"00000000";
ram_buffer(5189) := X"8207003D";
ram_buffer(5190) := X"82250009";
ram_buffer(5191) := X"00000000";
ram_buffer(5192) := X"14A7002D";
ram_buffer(5193) := X"00000000";
ram_buffer(5194) := X"10A00035";
ram_buffer(5195) := X"00000000";
ram_buffer(5196) := X"8207003E";
ram_buffer(5197) := X"8225000A";
ram_buffer(5198) := X"00000000";
ram_buffer(5199) := X"14A70026";
ram_buffer(5200) := X"00000000";
ram_buffer(5201) := X"10A0002E";
ram_buffer(5202) := X"00000000";
ram_buffer(5203) := X"8207003F";
ram_buffer(5204) := X"8225000B";
ram_buffer(5205) := X"00000000";
ram_buffer(5206) := X"14A7001F";
ram_buffer(5207) := X"00000000";
ram_buffer(5208) := X"10A00027";
ram_buffer(5209) := X"00000000";
ram_buffer(5210) := X"82070040";
ram_buffer(5211) := X"8225000C";
ram_buffer(5212) := X"00000000";
ram_buffer(5213) := X"14A70018";
ram_buffer(5214) := X"00000000";
ram_buffer(5215) := X"10A00020";
ram_buffer(5216) := X"00000000";
ram_buffer(5217) := X"82070041";
ram_buffer(5218) := X"8225000D";
ram_buffer(5219) := X"00000000";
ram_buffer(5220) := X"14A70011";
ram_buffer(5221) := X"00000000";
ram_buffer(5222) := X"10A00019";
ram_buffer(5223) := X"00000000";
ram_buffer(5224) := X"82070042";
ram_buffer(5225) := X"8225000E";
ram_buffer(5226) := X"00000000";
ram_buffer(5227) := X"14A7000A";
ram_buffer(5228) := X"00000000";
ram_buffer(5229) := X"10A00012";
ram_buffer(5230) := X"00000000";
ram_buffer(5231) := X"82070043";
ram_buffer(5232) := X"8225000F";
ram_buffer(5233) := X"00000000";
ram_buffer(5234) := X"14A70003";
ram_buffer(5235) := X"00000000";
ram_buffer(5236) := X"10A0000B";
ram_buffer(5237) := X"00000000";
ram_buffer(5238) := X"10D00016";
ram_buffer(5239) := X"00000000";
ram_buffer(5240) := X"8C420004";
ram_buffer(5241) := X"00000000";
ram_buffer(5242) := X"1482FF8A";
ram_buffer(5243) := X"AC620004";
ram_buffer(5244) := X"8C62000C";
ram_buffer(5245) := X"1000FF87";
ram_buffer(5246) := X"AC620004";
ram_buffer(5247) := X"00008025";
ram_buffer(5248) := X"0C4011C5";
ram_buffer(5249) := X"00000000";
ram_buffer(5250) := X"8FBF001C";
ram_buffer(5251) := X"02001025";
ram_buffer(5252) := X"8FB10018";
ram_buffer(5253) := X"8FB00014";
ram_buffer(5254) := X"03E00008";
ram_buffer(5255) := X"27BD0020";
ram_buffer(5256) := X"240508DD";
ram_buffer(5257) := X"0C40041F";
ram_buffer(5258) := X"24847C38";
ram_buffer(5259) := X"1000FED6";
ram_buffer(5260) := X"00000000";
ram_buffer(5261) := X"8F838044";
ram_buffer(5262) := X"00000000";
ram_buffer(5263) := X"8C620000";
ram_buffer(5264) := X"00000000";
ram_buffer(5265) := X"10400084";
ram_buffer(5266) := X"24640008";
ram_buffer(5267) := X"8C620004";
ram_buffer(5268) := X"00000000";
ram_buffer(5269) := X"8C420004";
ram_buffer(5270) := X"00000000";
ram_buffer(5271) := X"10440190";
ram_buffer(5272) := X"AC620004";
ram_buffer(5273) := X"8C46000C";
ram_buffer(5274) := X"10000074";
ram_buffer(5275) := X"00000000";
ram_buffer(5276) := X"8C50000C";
ram_buffer(5277) := X"82250000";
ram_buffer(5278) := X"82070034";
ram_buffer(5279) := X"00000000";
ram_buffer(5280) := X"14A7006C";
ram_buffer(5281) := X"00000000";
ram_buffer(5282) := X"10A0FFDD";
ram_buffer(5283) := X"00000000";
ram_buffer(5284) := X"82070035";
ram_buffer(5285) := X"82250001";
ram_buffer(5286) := X"00000000";
ram_buffer(5287) := X"14A70065";
ram_buffer(5288) := X"00000000";
ram_buffer(5289) := X"10A0FFD6";
ram_buffer(5290) := X"00000000";
ram_buffer(5291) := X"82070036";
ram_buffer(5292) := X"82250002";
ram_buffer(5293) := X"00000000";
ram_buffer(5294) := X"14A7005E";
ram_buffer(5295) := X"00000000";
ram_buffer(5296) := X"10A0FFCF";
ram_buffer(5297) := X"00000000";
ram_buffer(5298) := X"82070037";
ram_buffer(5299) := X"82250003";
ram_buffer(5300) := X"00000000";
ram_buffer(5301) := X"14A70057";
ram_buffer(5302) := X"00000000";
ram_buffer(5303) := X"10A0FFC8";
ram_buffer(5304) := X"00000000";
ram_buffer(5305) := X"82070038";
ram_buffer(5306) := X"82250004";
ram_buffer(5307) := X"00000000";
ram_buffer(5308) := X"14A70050";
ram_buffer(5309) := X"00000000";
ram_buffer(5310) := X"10A0FFC1";
ram_buffer(5311) := X"00000000";
ram_buffer(5312) := X"82070039";
ram_buffer(5313) := X"82250005";
ram_buffer(5314) := X"00000000";
ram_buffer(5315) := X"14A70049";
ram_buffer(5316) := X"00000000";
ram_buffer(5317) := X"10A0FFBA";
ram_buffer(5318) := X"00000000";
ram_buffer(5319) := X"8207003A";
ram_buffer(5320) := X"82250006";
ram_buffer(5321) := X"00000000";
ram_buffer(5322) := X"14A70042";
ram_buffer(5323) := X"00000000";
ram_buffer(5324) := X"10A0FFB3";
ram_buffer(5325) := X"00000000";
ram_buffer(5326) := X"8207003B";
ram_buffer(5327) := X"82250007";
ram_buffer(5328) := X"00000000";
ram_buffer(5329) := X"14A7003B";
ram_buffer(5330) := X"00000000";
ram_buffer(5331) := X"10A0FFAC";
ram_buffer(5332) := X"00000000";
ram_buffer(5333) := X"8207003C";
ram_buffer(5334) := X"82250008";
ram_buffer(5335) := X"00000000";
ram_buffer(5336) := X"14A70034";
ram_buffer(5337) := X"00000000";
ram_buffer(5338) := X"10A0FFA5";
ram_buffer(5339) := X"00000000";
ram_buffer(5340) := X"8207003D";
ram_buffer(5341) := X"82250009";
ram_buffer(5342) := X"00000000";
ram_buffer(5343) := X"14A7002D";
ram_buffer(5344) := X"00000000";
ram_buffer(5345) := X"10A0FF9E";
ram_buffer(5346) := X"00000000";
ram_buffer(5347) := X"8207003E";
ram_buffer(5348) := X"8225000A";
ram_buffer(5349) := X"00000000";
ram_buffer(5350) := X"14A70026";
ram_buffer(5351) := X"00000000";
ram_buffer(5352) := X"10A0FF97";
ram_buffer(5353) := X"00000000";
ram_buffer(5354) := X"8207003F";
ram_buffer(5355) := X"8225000B";
ram_buffer(5356) := X"00000000";
ram_buffer(5357) := X"14A7001F";
ram_buffer(5358) := X"00000000";
ram_buffer(5359) := X"10A0FF90";
ram_buffer(5360) := X"00000000";
ram_buffer(5361) := X"82070040";
ram_buffer(5362) := X"8225000C";
ram_buffer(5363) := X"00000000";
ram_buffer(5364) := X"14A70018";
ram_buffer(5365) := X"00000000";
ram_buffer(5366) := X"10A0FF89";
ram_buffer(5367) := X"00000000";
ram_buffer(5368) := X"82070041";
ram_buffer(5369) := X"8225000D";
ram_buffer(5370) := X"00000000";
ram_buffer(5371) := X"14A70011";
ram_buffer(5372) := X"00000000";
ram_buffer(5373) := X"10A0FF82";
ram_buffer(5374) := X"00000000";
ram_buffer(5375) := X"82070042";
ram_buffer(5376) := X"8225000E";
ram_buffer(5377) := X"00000000";
ram_buffer(5378) := X"14A7000A";
ram_buffer(5379) := X"00000000";
ram_buffer(5380) := X"10A0FF7B";
ram_buffer(5381) := X"00000000";
ram_buffer(5382) := X"82070043";
ram_buffer(5383) := X"8225000F";
ram_buffer(5384) := X"00000000";
ram_buffer(5385) := X"14A70003";
ram_buffer(5386) := X"00000000";
ram_buffer(5387) := X"10A0FF74";
ram_buffer(5388) := X"00000000";
ram_buffer(5389) := X"10D00008";
ram_buffer(5390) := X"00000000";
ram_buffer(5391) := X"8C420004";
ram_buffer(5392) := X"00000000";
ram_buffer(5393) := X"1482FF8A";
ram_buffer(5394) := X"AC620004";
ram_buffer(5395) := X"8C62000C";
ram_buffer(5396) := X"1000FF87";
ram_buffer(5397) := X"AC620004";
ram_buffer(5398) := X"3C030100";
ram_buffer(5399) := X"8C627D20";
ram_buffer(5400) := X"00000000";
ram_buffer(5401) := X"10400085";
ram_buffer(5402) := X"24637D20";
ram_buffer(5403) := X"8C620004";
ram_buffer(5404) := X"3C040100";
ram_buffer(5405) := X"8C420004";
ram_buffer(5406) := X"24847D28";
ram_buffer(5407) := X"10440111";
ram_buffer(5408) := X"AC620004";
ram_buffer(5409) := X"8C47000C";
ram_buffer(5410) := X"8C65000C";
ram_buffer(5411) := X"10000074";
ram_buffer(5412) := X"00000000";
ram_buffer(5413) := X"8C50000C";
ram_buffer(5414) := X"82260000";
ram_buffer(5415) := X"82080034";
ram_buffer(5416) := X"00000000";
ram_buffer(5417) := X"14C8006C";
ram_buffer(5418) := X"00000000";
ram_buffer(5419) := X"10C0FF54";
ram_buffer(5420) := X"00000000";
ram_buffer(5421) := X"82080035";
ram_buffer(5422) := X"82260001";
ram_buffer(5423) := X"00000000";
ram_buffer(5424) := X"14C80065";
ram_buffer(5425) := X"00000000";
ram_buffer(5426) := X"10C0FF4D";
ram_buffer(5427) := X"00000000";
ram_buffer(5428) := X"82080036";
ram_buffer(5429) := X"82260002";
ram_buffer(5430) := X"00000000";
ram_buffer(5431) := X"14C8005E";
ram_buffer(5432) := X"00000000";
ram_buffer(5433) := X"10C0FF46";
ram_buffer(5434) := X"00000000";
ram_buffer(5435) := X"82080037";
ram_buffer(5436) := X"82260003";
ram_buffer(5437) := X"00000000";
ram_buffer(5438) := X"14C80057";
ram_buffer(5439) := X"00000000";
ram_buffer(5440) := X"10C0FF3F";
ram_buffer(5441) := X"00000000";
ram_buffer(5442) := X"82080038";
ram_buffer(5443) := X"82260004";
ram_buffer(5444) := X"00000000";
ram_buffer(5445) := X"14C80050";
ram_buffer(5446) := X"00000000";
ram_buffer(5447) := X"10C0FF38";
ram_buffer(5448) := X"00000000";
ram_buffer(5449) := X"82080039";
ram_buffer(5450) := X"82260005";
ram_buffer(5451) := X"00000000";
ram_buffer(5452) := X"14C80049";
ram_buffer(5453) := X"00000000";
ram_buffer(5454) := X"10C0FF31";
ram_buffer(5455) := X"00000000";
ram_buffer(5456) := X"8208003A";
ram_buffer(5457) := X"82260006";
ram_buffer(5458) := X"00000000";
ram_buffer(5459) := X"14C80042";
ram_buffer(5460) := X"00000000";
ram_buffer(5461) := X"10C0FF2A";
ram_buffer(5462) := X"00000000";
ram_buffer(5463) := X"8208003B";
ram_buffer(5464) := X"82260007";
ram_buffer(5465) := X"00000000";
ram_buffer(5466) := X"14C8003B";
ram_buffer(5467) := X"00000000";
ram_buffer(5468) := X"10C0FF23";
ram_buffer(5469) := X"00000000";
ram_buffer(5470) := X"8208003C";
ram_buffer(5471) := X"82260008";
ram_buffer(5472) := X"00000000";
ram_buffer(5473) := X"14C80034";
ram_buffer(5474) := X"00000000";
ram_buffer(5475) := X"10C0FF1C";
ram_buffer(5476) := X"00000000";
ram_buffer(5477) := X"8208003D";
ram_buffer(5478) := X"82260009";
ram_buffer(5479) := X"00000000";
ram_buffer(5480) := X"14C8002D";
ram_buffer(5481) := X"00000000";
ram_buffer(5482) := X"10C0FF15";
ram_buffer(5483) := X"00000000";
ram_buffer(5484) := X"8208003E";
ram_buffer(5485) := X"8226000A";
ram_buffer(5486) := X"00000000";
ram_buffer(5487) := X"14C80026";
ram_buffer(5488) := X"00000000";
ram_buffer(5489) := X"10C0FF0E";
ram_buffer(5490) := X"00000000";
ram_buffer(5491) := X"8208003F";
ram_buffer(5492) := X"8226000B";
ram_buffer(5493) := X"00000000";
ram_buffer(5494) := X"14C8001F";
ram_buffer(5495) := X"00000000";
ram_buffer(5496) := X"10C0FF07";
ram_buffer(5497) := X"00000000";
ram_buffer(5498) := X"82080040";
ram_buffer(5499) := X"8226000C";
ram_buffer(5500) := X"00000000";
ram_buffer(5501) := X"14C80018";
ram_buffer(5502) := X"00000000";
ram_buffer(5503) := X"10C0FF00";
ram_buffer(5504) := X"00000000";
ram_buffer(5505) := X"82080041";
ram_buffer(5506) := X"8226000D";
ram_buffer(5507) := X"00000000";
ram_buffer(5508) := X"14C80011";
ram_buffer(5509) := X"00000000";
ram_buffer(5510) := X"10C0FEF9";
ram_buffer(5511) := X"00000000";
ram_buffer(5512) := X"82080042";
ram_buffer(5513) := X"8226000E";
ram_buffer(5514) := X"00000000";
ram_buffer(5515) := X"14C8000A";
ram_buffer(5516) := X"00000000";
ram_buffer(5517) := X"10C0FEF2";
ram_buffer(5518) := X"00000000";
ram_buffer(5519) := X"82080043";
ram_buffer(5520) := X"8226000F";
ram_buffer(5521) := X"00000000";
ram_buffer(5522) := X"14C80003";
ram_buffer(5523) := X"00000000";
ram_buffer(5524) := X"10C0FEEB";
ram_buffer(5525) := X"00000000";
ram_buffer(5526) := X"10F00008";
ram_buffer(5527) := X"00000000";
ram_buffer(5528) := X"8C420004";
ram_buffer(5529) := X"00000000";
ram_buffer(5530) := X"1444FF8A";
ram_buffer(5531) := X"AC620004";
ram_buffer(5532) := X"AC650004";
ram_buffer(5533) := X"1000FF87";
ram_buffer(5534) := X"00A01025";
ram_buffer(5535) := X"3C030100";
ram_buffer(5536) := X"8C627D34";
ram_buffer(5537) := X"00000000";
ram_buffer(5538) := X"1040FEDC";
ram_buffer(5539) := X"24637D34";
ram_buffer(5540) := X"8C620004";
ram_buffer(5541) := X"3C040100";
ram_buffer(5542) := X"8C420004";
ram_buffer(5543) := X"24847D3C";
ram_buffer(5544) := X"10440085";
ram_buffer(5545) := X"AC620004";
ram_buffer(5546) := X"8C48000C";
ram_buffer(5547) := X"8C67000C";
ram_buffer(5548) := X"10000074";
ram_buffer(5549) := X"00000000";
ram_buffer(5550) := X"8C50000C";
ram_buffer(5551) := X"82250000";
ram_buffer(5552) := X"82060034";
ram_buffer(5553) := X"00000000";
ram_buffer(5554) := X"14A6006C";
ram_buffer(5555) := X"00000000";
ram_buffer(5556) := X"10A0FECB";
ram_buffer(5557) := X"00000000";
ram_buffer(5558) := X"82260001";
ram_buffer(5559) := X"82050035";
ram_buffer(5560) := X"00000000";
ram_buffer(5561) := X"14A60065";
ram_buffer(5562) := X"00000000";
ram_buffer(5563) := X"10A0FEC4";
ram_buffer(5564) := X"00000000";
ram_buffer(5565) := X"82260002";
ram_buffer(5566) := X"82050036";
ram_buffer(5567) := X"00000000";
ram_buffer(5568) := X"14A6005E";
ram_buffer(5569) := X"00000000";
ram_buffer(5570) := X"10A0FEBD";
ram_buffer(5571) := X"00000000";
ram_buffer(5572) := X"82060037";
ram_buffer(5573) := X"82250003";
ram_buffer(5574) := X"00000000";
ram_buffer(5575) := X"14A60057";
ram_buffer(5576) := X"00000000";
ram_buffer(5577) := X"10A0FEB6";
ram_buffer(5578) := X"00000000";
ram_buffer(5579) := X"82060038";
ram_buffer(5580) := X"82250004";
ram_buffer(5581) := X"00000000";
ram_buffer(5582) := X"14A60050";
ram_buffer(5583) := X"00000000";
ram_buffer(5584) := X"10A0FEAF";
ram_buffer(5585) := X"00000000";
ram_buffer(5586) := X"82060039";
ram_buffer(5587) := X"82250005";
ram_buffer(5588) := X"00000000";
ram_buffer(5589) := X"14A60049";
ram_buffer(5590) := X"00000000";
ram_buffer(5591) := X"10A0FEA8";
ram_buffer(5592) := X"00000000";
ram_buffer(5593) := X"8206003A";
ram_buffer(5594) := X"82250006";
ram_buffer(5595) := X"00000000";
ram_buffer(5596) := X"14A60042";
ram_buffer(5597) := X"00000000";
ram_buffer(5598) := X"10A0FEA1";
ram_buffer(5599) := X"00000000";
ram_buffer(5600) := X"8206003B";
ram_buffer(5601) := X"82250007";
ram_buffer(5602) := X"00000000";
ram_buffer(5603) := X"14A6003B";
ram_buffer(5604) := X"00000000";
ram_buffer(5605) := X"10A0FE9A";
ram_buffer(5606) := X"00000000";
ram_buffer(5607) := X"8206003C";
ram_buffer(5608) := X"82250008";
ram_buffer(5609) := X"00000000";
ram_buffer(5610) := X"14A60034";
ram_buffer(5611) := X"00000000";
ram_buffer(5612) := X"10A0FE93";
ram_buffer(5613) := X"00000000";
ram_buffer(5614) := X"8206003D";
ram_buffer(5615) := X"82250009";
ram_buffer(5616) := X"00000000";
ram_buffer(5617) := X"14A6002D";
ram_buffer(5618) := X"00000000";
ram_buffer(5619) := X"10A0FE8C";
ram_buffer(5620) := X"00000000";
ram_buffer(5621) := X"8206003E";
ram_buffer(5622) := X"8225000A";
ram_buffer(5623) := X"00000000";
ram_buffer(5624) := X"14A60026";
ram_buffer(5625) := X"00000000";
ram_buffer(5626) := X"10A0FE85";
ram_buffer(5627) := X"00000000";
ram_buffer(5628) := X"8206003F";
ram_buffer(5629) := X"8225000B";
ram_buffer(5630) := X"00000000";
ram_buffer(5631) := X"14A6001F";
ram_buffer(5632) := X"00000000";
ram_buffer(5633) := X"10A0FE7E";
ram_buffer(5634) := X"00000000";
ram_buffer(5635) := X"82060040";
ram_buffer(5636) := X"8225000C";
ram_buffer(5637) := X"00000000";
ram_buffer(5638) := X"14A60018";
ram_buffer(5639) := X"00000000";
ram_buffer(5640) := X"10A0FE77";
ram_buffer(5641) := X"00000000";
ram_buffer(5642) := X"82060041";
ram_buffer(5643) := X"8225000D";
ram_buffer(5644) := X"00000000";
ram_buffer(5645) := X"14A60011";
ram_buffer(5646) := X"00000000";
ram_buffer(5647) := X"10A0FE70";
ram_buffer(5648) := X"00000000";
ram_buffer(5649) := X"82060042";
ram_buffer(5650) := X"8225000E";
ram_buffer(5651) := X"00000000";
ram_buffer(5652) := X"14A6000A";
ram_buffer(5653) := X"00000000";
ram_buffer(5654) := X"10A0FE69";
ram_buffer(5655) := X"00000000";
ram_buffer(5656) := X"82060043";
ram_buffer(5657) := X"8225000F";
ram_buffer(5658) := X"00000000";
ram_buffer(5659) := X"14A60003";
ram_buffer(5660) := X"00000000";
ram_buffer(5661) := X"10A0FE62";
ram_buffer(5662) := X"00000000";
ram_buffer(5663) := X"1110FE60";
ram_buffer(5664) := X"00008025";
ram_buffer(5665) := X"8C420004";
ram_buffer(5666) := X"00000000";
ram_buffer(5667) := X"1444FF8A";
ram_buffer(5668) := X"AC620004";
ram_buffer(5669) := X"AC670004";
ram_buffer(5670) := X"1000FF87";
ram_buffer(5671) := X"00E01025";
ram_buffer(5672) := X"8C62000C";
ram_buffer(5673) := X"1000FE6F";
ram_buffer(5674) := X"00000000";
ram_buffer(5675) := X"8C62000C";
ram_buffer(5676) := X"1000FDD5";
ram_buffer(5677) := X"00000000";
ram_buffer(5678) := X"8C62000C";
ram_buffer(5679) := X"1000FF7A";
ram_buffer(5680) := X"00000000";
ram_buffer(5681) := X"8C62000C";
ram_buffer(5682) := X"1000FEEE";
ram_buffer(5683) := X"00000000";
ram_buffer(5684) := X"27BDFFE0";
ram_buffer(5685) := X"AFB00014";
ram_buffer(5686) := X"AFBF001C";
ram_buffer(5687) := X"AFB10018";
ram_buffer(5688) := X"1080007F";
ram_buffer(5689) := X"00808025";
ram_buffer(5690) := X"8F828014";
ram_buffer(5691) := X"00000000";
ram_buffer(5692) := X"24420001";
ram_buffer(5693) := X"AF828014";
ram_buffer(5694) := X"8F828010";
ram_buffer(5695) := X"00000000";
ram_buffer(5696) := X"12020016";
ram_buffer(5697) := X"00000000";
ram_buffer(5698) := X"0C40041A";
ram_buffer(5699) := X"00000000";
ram_buffer(5700) := X"8F828030";
ram_buffer(5701) := X"00000000";
ram_buffer(5702) := X"1440006A";
ram_buffer(5703) := X"00000000";
ram_buffer(5704) := X"8F828030";
ram_buffer(5705) := X"8E110014";
ram_buffer(5706) := X"14400014";
ram_buffer(5707) := X"00000000";
ram_buffer(5708) := X"8F828048";
ram_buffer(5709) := X"00000000";
ram_buffer(5710) := X"12220028";
ram_buffer(5711) := X"00000000";
ram_buffer(5712) := X"8F828044";
ram_buffer(5713) := X"00000000";
ram_buffer(5714) := X"12220024";
ram_buffer(5715) := X"3C020100";
ram_buffer(5716) := X"24427D20";
ram_buffer(5717) := X"1222001D";
ram_buffer(5718) := X"00000000";
ram_buffer(5719) := X"0C4011C5";
ram_buffer(5720) := X"00000000";
ram_buffer(5721) := X"8FBF001C";
ram_buffer(5722) := X"8FB10018";
ram_buffer(5723) := X"8FB00014";
ram_buffer(5724) := X"00001025";
ram_buffer(5725) := X"03E00008";
ram_buffer(5726) := X"27BD0020";
ram_buffer(5727) := X"8F828010";
ram_buffer(5728) := X"00000000";
ram_buffer(5729) := X"8C420044";
ram_buffer(5730) := X"00000000";
ram_buffer(5731) := X"1040FFE8";
ram_buffer(5732) := X"00000000";
ram_buffer(5733) := X"8F838010";
ram_buffer(5734) := X"8F848010";
ram_buffer(5735) := X"8C620044";
ram_buffer(5736) := X"00000000";
ram_buffer(5737) := X"2442FFFF";
ram_buffer(5738) := X"AC620044";
ram_buffer(5739) := X"8C820044";
ram_buffer(5740) := X"00000000";
ram_buffer(5741) := X"1440FFDE";
ram_buffer(5742) := X"00000000";
ram_buffer(5743) := X"0C400415";
ram_buffer(5744) := X"00000000";
ram_buffer(5745) := X"1000FFDA";
ram_buffer(5746) := X"00000000";
ram_buffer(5747) := X"8E020028";
ram_buffer(5748) := X"00000000";
ram_buffer(5749) := X"1040FFE1";
ram_buffer(5750) := X"00000000";
ram_buffer(5751) := X"26110004";
ram_buffer(5752) := X"0C40046F";
ram_buffer(5753) := X"02202025";
ram_buffer(5754) := X"0C40041A";
ram_buffer(5755) := X"00000000";
ram_buffer(5756) := X"8F828030";
ram_buffer(5757) := X"00000000";
ram_buffer(5758) := X"14400046";
ram_buffer(5759) := X"00000000";
ram_buffer(5760) := X"8E020028";
ram_buffer(5761) := X"00000000";
ram_buffer(5762) := X"10400005";
ram_buffer(5763) := X"00000000";
ram_buffer(5764) := X"0C40046F";
ram_buffer(5765) := X"26040018";
ram_buffer(5766) := X"24020001";
ram_buffer(5767) := X"A2020055";
ram_buffer(5768) := X"8F828030";
ram_buffer(5769) := X"00000000";
ram_buffer(5770) := X"10400007";
ram_buffer(5771) := X"00000000";
ram_buffer(5772) := X"8F828010";
ram_buffer(5773) := X"00000000";
ram_buffer(5774) := X"8C420044";
ram_buffer(5775) := X"00000000";
ram_buffer(5776) := X"1440003B";
ram_buffer(5777) := X"00000000";
ram_buffer(5778) := X"8E04002C";
ram_buffer(5779) := X"8F828034";
ram_buffer(5780) := X"00000000";
ram_buffer(5781) := X"0044102B";
ram_buffer(5782) := X"10400003";
ram_buffer(5783) := X"00041080";
ram_buffer(5784) := X"AF848034";
ram_buffer(5785) := X"00041080";
ram_buffer(5786) := X"00441021";
ram_buffer(5787) := X"3C040100";
ram_buffer(5788) := X"00021080";
ram_buffer(5789) := X"24847D84";
ram_buffer(5790) := X"00822021";
ram_buffer(5791) := X"0C400441";
ram_buffer(5792) := X"02202825";
ram_buffer(5793) := X"8F838010";
ram_buffer(5794) := X"8E02002C";
ram_buffer(5795) := X"8C63002C";
ram_buffer(5796) := X"00000000";
ram_buffer(5797) := X"0062102B";
ram_buffer(5798) := X"1040FFB0";
ram_buffer(5799) := X"24020001";
ram_buffer(5800) := X"AF828028";
ram_buffer(5801) := X"0C4011C5";
ram_buffer(5802) := X"00000000";
ram_buffer(5803) := X"8FBF001C";
ram_buffer(5804) := X"8FB10018";
ram_buffer(5805) := X"8FB00014";
ram_buffer(5806) := X"00001025";
ram_buffer(5807) := X"03E00008";
ram_buffer(5808) := X"27BD0020";
ram_buffer(5809) := X"8F838010";
ram_buffer(5810) := X"8F828010";
ram_buffer(5811) := X"8C620044";
ram_buffer(5812) := X"00000000";
ram_buffer(5813) := X"24420001";
ram_buffer(5814) := X"1000FF91";
ram_buffer(5815) := X"AC620044";
ram_buffer(5816) := X"3C110100";
ram_buffer(5817) := X"26247C38";
ram_buffer(5818) := X"0C40041F";
ram_buffer(5819) := X"24050987";
ram_buffer(5820) := X"8F828014";
ram_buffer(5821) := X"24050502";
ram_buffer(5822) := X"24420001";
ram_buffer(5823) := X"26247C38";
ram_buffer(5824) := X"AF828014";
ram_buffer(5825) := X"0C40041F";
ram_buffer(5826) := X"00000000";
ram_buffer(5827) := X"1000FF7A";
ram_buffer(5828) := X"00000000";
ram_buffer(5829) := X"8F838010";
ram_buffer(5830) := X"8F828010";
ram_buffer(5831) := X"8C620044";
ram_buffer(5832) := X"00000000";
ram_buffer(5833) := X"24420001";
ram_buffer(5834) := X"1000FFB5";
ram_buffer(5835) := X"AC620044";
ram_buffer(5836) := X"8F838010";
ram_buffer(5837) := X"8F848010";
ram_buffer(5838) := X"8C620044";
ram_buffer(5839) := X"00000000";
ram_buffer(5840) := X"2442FFFF";
ram_buffer(5841) := X"AC620044";
ram_buffer(5842) := X"8C820044";
ram_buffer(5843) := X"00000000";
ram_buffer(5844) := X"1440FFBD";
ram_buffer(5845) := X"00000000";
ram_buffer(5846) := X"0C400415";
ram_buffer(5847) := X"00000000";
ram_buffer(5848) := X"1000FFB9";
ram_buffer(5849) := X"00000000";
ram_buffer(5850) := X"8F828014";
ram_buffer(5851) := X"27BDFFE0";
ram_buffer(5852) := X"AFBF001C";
ram_buffer(5853) := X"AFB10018";
ram_buffer(5854) := X"14400050";
ram_buffer(5855) := X"AFB00014";
ram_buffer(5856) := X"AF808028";
ram_buffer(5857) := X"8F908034";
ram_buffer(5858) := X"3C110100";
ram_buffer(5859) := X"00101080";
ram_buffer(5860) := X"00501821";
ram_buffer(5861) := X"00031880";
ram_buffer(5862) := X"26317D84";
ram_buffer(5863) := X"02231821";
ram_buffer(5864) := X"8C630000";
ram_buffer(5865) := X"00000000";
ram_buffer(5866) := X"14600032";
ram_buffer(5867) := X"00501021";
ram_buffer(5868) := X"1200005E";
ram_buffer(5869) := X"3C040100";
ram_buffer(5870) := X"2604FFFF";
ram_buffer(5871) := X"00041080";
ram_buffer(5872) := X"00441821";
ram_buffer(5873) := X"00031880";
ram_buffer(5874) := X"02231821";
ram_buffer(5875) := X"8C630000";
ram_buffer(5876) := X"00000000";
ram_buffer(5877) := X"14600037";
ram_buffer(5878) := X"00000000";
ram_buffer(5879) := X"1080004E";
ram_buffer(5880) := X"3C040100";
ram_buffer(5881) := X"2604FFFE";
ram_buffer(5882) := X"00041080";
ram_buffer(5883) := X"00441821";
ram_buffer(5884) := X"00031880";
ram_buffer(5885) := X"02231821";
ram_buffer(5886) := X"8C630000";
ram_buffer(5887) := X"00000000";
ram_buffer(5888) := X"1460002C";
ram_buffer(5889) := X"00000000";
ram_buffer(5890) := X"1080003E";
ram_buffer(5891) := X"3C040100";
ram_buffer(5892) := X"2604FFFD";
ram_buffer(5893) := X"00041080";
ram_buffer(5894) := X"00441821";
ram_buffer(5895) := X"00031880";
ram_buffer(5896) := X"02231821";
ram_buffer(5897) := X"8C630000";
ram_buffer(5898) := X"00000000";
ram_buffer(5899) := X"14600021";
ram_buffer(5900) := X"00000000";
ram_buffer(5901) := X"1080002E";
ram_buffer(5902) := X"3C040100";
ram_buffer(5903) := X"2604FFFC";
ram_buffer(5904) := X"00041080";
ram_buffer(5905) := X"00441821";
ram_buffer(5906) := X"00031880";
ram_buffer(5907) := X"02231821";
ram_buffer(5908) := X"8C630000";
ram_buffer(5909) := X"00000000";
ram_buffer(5910) := X"14600016";
ram_buffer(5911) := X"00000000";
ram_buffer(5912) := X"1080001D";
ram_buffer(5913) := X"3C040100";
ram_buffer(5914) := X"2610FFFB";
ram_buffer(5915) := X"00101080";
ram_buffer(5916) := X"00501021";
ram_buffer(5917) := X"00021080";
ram_buffer(5918) := X"02222021";
ram_buffer(5919) := X"8C830004";
ram_buffer(5920) := X"24420008";
ram_buffer(5921) := X"8C630004";
ram_buffer(5922) := X"02221021";
ram_buffer(5923) := X"1062002C";
ram_buffer(5924) := X"AC830004";
ram_buffer(5925) := X"8C62000C";
ram_buffer(5926) := X"8FBF001C";
ram_buffer(5927) := X"8FB10018";
ram_buffer(5928) := X"AF828010";
ram_buffer(5929) := X"AF908034";
ram_buffer(5930) := X"8FB00014";
ram_buffer(5931) := X"03E00008";
ram_buffer(5932) := X"27BD0020";
ram_buffer(5933) := X"1000FFEE";
ram_buffer(5934) := X"00808025";
ram_buffer(5935) := X"8FBF001C";
ram_buffer(5936) := X"24020001";
ram_buffer(5937) := X"8FB10018";
ram_buffer(5938) := X"8FB00014";
ram_buffer(5939) := X"AF828028";
ram_buffer(5940) := X"03E00008";
ram_buffer(5941) := X"27BD0020";
ram_buffer(5942) := X"24050B05";
ram_buffer(5943) := X"24847C38";
ram_buffer(5944) := X"0C40041F";
ram_buffer(5945) := X"2610FFFB";
ram_buffer(5946) := X"1000FFE1";
ram_buffer(5947) := X"00101080";
ram_buffer(5948) := X"24050B05";
ram_buffer(5949) := X"0C40041F";
ram_buffer(5950) := X"24847C38";
ram_buffer(5951) := X"1000FFD0";
ram_buffer(5952) := X"2604FFFC";
ram_buffer(5953) := X"24050B05";
ram_buffer(5954) := X"0C40041F";
ram_buffer(5955) := X"24847C38";
ram_buffer(5956) := X"1000FFC0";
ram_buffer(5957) := X"2604FFFD";
ram_buffer(5958) := X"24050B05";
ram_buffer(5959) := X"0C40041F";
ram_buffer(5960) := X"24847C38";
ram_buffer(5961) := X"1000FFB0";
ram_buffer(5962) := X"2604FFFE";
ram_buffer(5963) := X"24050B05";
ram_buffer(5964) := X"0C40041F";
ram_buffer(5965) := X"24847C38";
ram_buffer(5966) := X"1000FFA0";
ram_buffer(5967) := X"2604FFFF";
ram_buffer(5968) := X"8C630004";
ram_buffer(5969) := X"1000FFD3";
ram_buffer(5970) := X"AC830004";
ram_buffer(5971) := X"27BDFFE0";
ram_buffer(5972) := X"AFB10018";
ram_buffer(5973) := X"AFB00014";
ram_buffer(5974) := X"AFBF001C";
ram_buffer(5975) := X"00808825";
ram_buffer(5976) := X"10800033";
ram_buffer(5977) := X"00A08025";
ram_buffer(5978) := X"8F858010";
ram_buffer(5979) := X"02202025";
ram_buffer(5980) := X"0C40044D";
ram_buffer(5981) := X"24A50018";
ram_buffer(5982) := X"8F918038";
ram_buffer(5983) := X"8F828010";
ram_buffer(5984) := X"8F848010";
ram_buffer(5985) := X"A0400055";
ram_buffer(5986) := X"0C40046F";
ram_buffer(5987) := X"24840004";
ram_buffer(5988) := X"2402FFFF";
ram_buffer(5989) := X"1202001D";
ram_buffer(5990) := X"00000000";
ram_buffer(5991) := X"02118021";
ram_buffer(5992) := X"8F828010";
ram_buffer(5993) := X"0211882B";
ram_buffer(5994) := X"16200010";
ram_buffer(5995) := X"AC500004";
ram_buffer(5996) := X"8F848048";
ram_buffer(5997) := X"8F858010";
ram_buffer(5998) := X"0C40044D";
ram_buffer(5999) := X"24A50004";
ram_buffer(6000) := X"8F82801C";
ram_buffer(6001) := X"00000000";
ram_buffer(6002) := X"0202102B";
ram_buffer(6003) := X"10400002";
ram_buffer(6004) := X"00000000";
ram_buffer(6005) := X"AF90801C";
ram_buffer(6006) := X"8FBF001C";
ram_buffer(6007) := X"8FB10018";
ram_buffer(6008) := X"8FB00014";
ram_buffer(6009) := X"03E00008";
ram_buffer(6010) := X"27BD0020";
ram_buffer(6011) := X"8F848044";
ram_buffer(6012) := X"8F858010";
ram_buffer(6013) := X"8FBF001C";
ram_buffer(6014) := X"8FB10018";
ram_buffer(6015) := X"8FB00014";
ram_buffer(6016) := X"24A50004";
ram_buffer(6017) := X"0840044D";
ram_buffer(6018) := X"27BD0020";
ram_buffer(6019) := X"8F858010";
ram_buffer(6020) := X"8FBF001C";
ram_buffer(6021) := X"8FB10018";
ram_buffer(6022) := X"8FB00014";
ram_buffer(6023) := X"3C040100";
ram_buffer(6024) := X"24A50004";
ram_buffer(6025) := X"24847D20";
ram_buffer(6026) := X"08400441";
ram_buffer(6027) := X"27BD0020";
ram_buffer(6028) := X"3C040100";
ram_buffer(6029) := X"24050B15";
ram_buffer(6030) := X"0C40041F";
ram_buffer(6031) := X"24847C38";
ram_buffer(6032) := X"1000FFC9";
ram_buffer(6033) := X"00000000";
ram_buffer(6034) := X"27BDFFE0";
ram_buffer(6035) := X"AFB20018";
ram_buffer(6036) := X"AFB10014";
ram_buffer(6037) := X"AFB00010";
ram_buffer(6038) := X"AFBF001C";
ram_buffer(6039) := X"00809025";
ram_buffer(6040) := X"00A08825";
ram_buffer(6041) := X"10800042";
ram_buffer(6042) := X"00C08025";
ram_buffer(6043) := X"8F828014";
ram_buffer(6044) := X"00000000";
ram_buffer(6045) := X"14400005";
ram_buffer(6046) := X"00000000";
ram_buffer(6047) := X"3C040100";
ram_buffer(6048) := X"24050B2A";
ram_buffer(6049) := X"0C40041F";
ram_buffer(6050) := X"24847C38";
ram_buffer(6051) := X"8F828010";
ram_buffer(6052) := X"3C038000";
ram_buffer(6053) := X"8F858010";
ram_buffer(6054) := X"02238825";
ram_buffer(6055) := X"AC510018";
ram_buffer(6056) := X"02402025";
ram_buffer(6057) := X"0C400441";
ram_buffer(6058) := X"24A50018";
ram_buffer(6059) := X"8F918038";
ram_buffer(6060) := X"8F828010";
ram_buffer(6061) := X"8F848010";
ram_buffer(6062) := X"A0400055";
ram_buffer(6063) := X"0C40046F";
ram_buffer(6064) := X"24840004";
ram_buffer(6065) := X"2402FFFF";
ram_buffer(6066) := X"1202001F";
ram_buffer(6067) := X"00000000";
ram_buffer(6068) := X"02118021";
ram_buffer(6069) := X"8F828010";
ram_buffer(6070) := X"0211882B";
ram_buffer(6071) := X"16200011";
ram_buffer(6072) := X"AC500004";
ram_buffer(6073) := X"8F848048";
ram_buffer(6074) := X"8F858010";
ram_buffer(6075) := X"0C40044D";
ram_buffer(6076) := X"24A50004";
ram_buffer(6077) := X"8F82801C";
ram_buffer(6078) := X"00000000";
ram_buffer(6079) := X"0202102B";
ram_buffer(6080) := X"10400002";
ram_buffer(6081) := X"00000000";
ram_buffer(6082) := X"AF90801C";
ram_buffer(6083) := X"8FBF001C";
ram_buffer(6084) := X"8FB20018";
ram_buffer(6085) := X"8FB10014";
ram_buffer(6086) := X"8FB00010";
ram_buffer(6087) := X"03E00008";
ram_buffer(6088) := X"27BD0020";
ram_buffer(6089) := X"8F848044";
ram_buffer(6090) := X"8F858010";
ram_buffer(6091) := X"8FBF001C";
ram_buffer(6092) := X"8FB20018";
ram_buffer(6093) := X"8FB10014";
ram_buffer(6094) := X"8FB00010";
ram_buffer(6095) := X"24A50004";
ram_buffer(6096) := X"0840044D";
ram_buffer(6097) := X"27BD0020";
ram_buffer(6098) := X"8F858010";
ram_buffer(6099) := X"8FBF001C";
ram_buffer(6100) := X"8FB20018";
ram_buffer(6101) := X"8FB10014";
ram_buffer(6102) := X"8FB00010";
ram_buffer(6103) := X"3C040100";
ram_buffer(6104) := X"24A50004";
ram_buffer(6105) := X"24847D20";
ram_buffer(6106) := X"08400441";
ram_buffer(6107) := X"27BD0020";
ram_buffer(6108) := X"3C040100";
ram_buffer(6109) := X"24050B26";
ram_buffer(6110) := X"0C40041F";
ram_buffer(6111) := X"24847C38";
ram_buffer(6112) := X"1000FFBA";
ram_buffer(6113) := X"00000000";
ram_buffer(6114) := X"8C82000C";
ram_buffer(6115) := X"27BDFFE0";
ram_buffer(6116) := X"AFB00014";
ram_buffer(6117) := X"8C50000C";
ram_buffer(6118) := X"AFBF001C";
ram_buffer(6119) := X"1200003A";
ram_buffer(6120) := X"AFB10018";
ram_buffer(6121) := X"26110018";
ram_buffer(6122) := X"0C40046F";
ram_buffer(6123) := X"02202025";
ram_buffer(6124) := X"8F828014";
ram_buffer(6125) := X"00000000";
ram_buffer(6126) := X"14400020";
ram_buffer(6127) := X"3C040100";
ram_buffer(6128) := X"26110004";
ram_buffer(6129) := X"0C40046F";
ram_buffer(6130) := X"02202025";
ram_buffer(6131) := X"8E04002C";
ram_buffer(6132) := X"8F828034";
ram_buffer(6133) := X"00000000";
ram_buffer(6134) := X"0044102B";
ram_buffer(6135) := X"14400027";
ram_buffer(6136) := X"00000000";
ram_buffer(6137) := X"00041080";
ram_buffer(6138) := X"00441021";
ram_buffer(6139) := X"3C040100";
ram_buffer(6140) := X"00021080";
ram_buffer(6141) := X"24847D84";
ram_buffer(6142) := X"00822021";
ram_buffer(6143) := X"0C400441";
ram_buffer(6144) := X"02202825";
ram_buffer(6145) := X"8F838010";
ram_buffer(6146) := X"8E02002C";
ram_buffer(6147) := X"8C63002C";
ram_buffer(6148) := X"00000000";
ram_buffer(6149) := X"0062102B";
ram_buffer(6150) := X"10400012";
ram_buffer(6151) := X"00000000";
ram_buffer(6152) := X"8FBF001C";
ram_buffer(6153) := X"24020001";
ram_buffer(6154) := X"8FB10018";
ram_buffer(6155) := X"8FB00014";
ram_buffer(6156) := X"AF828028";
ram_buffer(6157) := X"03E00008";
ram_buffer(6158) := X"27BD0020";
ram_buffer(6159) := X"02202825";
ram_buffer(6160) := X"0C400441";
ram_buffer(6161) := X"24847D48";
ram_buffer(6162) := X"8F838010";
ram_buffer(6163) := X"8E02002C";
ram_buffer(6164) := X"8C63002C";
ram_buffer(6165) := X"00000000";
ram_buffer(6166) := X"0062102B";
ram_buffer(6167) := X"1440FFF0";
ram_buffer(6168) := X"00000000";
ram_buffer(6169) := X"8FBF001C";
ram_buffer(6170) := X"8FB10018";
ram_buffer(6171) := X"8FB00014";
ram_buffer(6172) := X"00001025";
ram_buffer(6173) := X"03E00008";
ram_buffer(6174) := X"27BD0020";
ram_buffer(6175) := X"AF848034";
ram_buffer(6176) := X"1000FFD9";
ram_buffer(6177) := X"00041080";
ram_buffer(6178) := X"3C040100";
ram_buffer(6179) := X"24050B70";
ram_buffer(6180) := X"0C40041F";
ram_buffer(6181) := X"24847C38";
ram_buffer(6182) := X"1000FFC3";
ram_buffer(6183) := X"26110018";
ram_buffer(6184) := X"8F828014";
ram_buffer(6185) := X"27BDFFE0";
ram_buffer(6186) := X"AFB20018";
ram_buffer(6187) := X"AFB10014";
ram_buffer(6188) := X"AFBF001C";
ram_buffer(6189) := X"AFB00010";
ram_buffer(6190) := X"00808825";
ram_buffer(6191) := X"1040002F";
ram_buffer(6192) := X"00A09025";
ram_buffer(6193) := X"3C028000";
ram_buffer(6194) := X"8E30000C";
ram_buffer(6195) := X"02429025";
ram_buffer(6196) := X"12000030";
ram_buffer(6197) := X"AE320000";
ram_buffer(6198) := X"02202025";
ram_buffer(6199) := X"0C40046F";
ram_buffer(6200) := X"26110004";
ram_buffer(6201) := X"0C40046F";
ram_buffer(6202) := X"02202025";
ram_buffer(6203) := X"8E04002C";
ram_buffer(6204) := X"8F828034";
ram_buffer(6205) := X"00000000";
ram_buffer(6206) := X"0044102B";
ram_buffer(6207) := X"10400003";
ram_buffer(6208) := X"00041080";
ram_buffer(6209) := X"AF848034";
ram_buffer(6210) := X"00041080";
ram_buffer(6211) := X"00441021";
ram_buffer(6212) := X"3C040100";
ram_buffer(6213) := X"00021080";
ram_buffer(6214) := X"24847D84";
ram_buffer(6215) := X"00822021";
ram_buffer(6216) := X"0C400441";
ram_buffer(6217) := X"02202825";
ram_buffer(6218) := X"8F838010";
ram_buffer(6219) := X"8E02002C";
ram_buffer(6220) := X"8C63002C";
ram_buffer(6221) := X"00000000";
ram_buffer(6222) := X"0062102B";
ram_buffer(6223) := X"10400008";
ram_buffer(6224) := X"24020001";
ram_buffer(6225) := X"8FBF001C";
ram_buffer(6226) := X"8FB20018";
ram_buffer(6227) := X"8FB10014";
ram_buffer(6228) := X"8FB00010";
ram_buffer(6229) := X"AF828028";
ram_buffer(6230) := X"03E00008";
ram_buffer(6231) := X"27BD0020";
ram_buffer(6232) := X"8FBF001C";
ram_buffer(6233) := X"8FB20018";
ram_buffer(6234) := X"8FB10014";
ram_buffer(6235) := X"8FB00010";
ram_buffer(6236) := X"00001025";
ram_buffer(6237) := X"03E00008";
ram_buffer(6238) := X"27BD0020";
ram_buffer(6239) := X"3C040100";
ram_buffer(6240) := X"24050BA8";
ram_buffer(6241) := X"0C40041F";
ram_buffer(6242) := X"24847C38";
ram_buffer(6243) := X"1000FFCE";
ram_buffer(6244) := X"3C028000";
ram_buffer(6245) := X"3C040100";
ram_buffer(6246) := X"24050BB0";
ram_buffer(6247) := X"0C40041F";
ram_buffer(6248) := X"24847C38";
ram_buffer(6249) := X"1000FFCD";
ram_buffer(6250) := X"02202025";
ram_buffer(6251) := X"27BDFFE8";
ram_buffer(6252) := X"AFB00010";
ram_buffer(6253) := X"AFBF0014";
ram_buffer(6254) := X"10800009";
ram_buffer(6255) := X"00808025";
ram_buffer(6256) := X"8F838024";
ram_buffer(6257) := X"8FBF0014";
ram_buffer(6258) := X"8F828038";
ram_buffer(6259) := X"AE030000";
ram_buffer(6260) := X"AE020004";
ram_buffer(6261) := X"8FB00010";
ram_buffer(6262) := X"03E00008";
ram_buffer(6263) := X"27BD0018";
ram_buffer(6264) := X"3C040100";
ram_buffer(6265) := X"24050BD0";
ram_buffer(6266) := X"0C40041F";
ram_buffer(6267) := X"24847C38";
ram_buffer(6268) := X"8F838024";
ram_buffer(6269) := X"8FBF0014";
ram_buffer(6270) := X"8F828038";
ram_buffer(6271) := X"AE030000";
ram_buffer(6272) := X"AE020004";
ram_buffer(6273) := X"8FB00010";
ram_buffer(6274) := X"03E00008";
ram_buffer(6275) := X"27BD0018";
ram_buffer(6276) := X"27BDFFD8";
ram_buffer(6277) := X"AFB10020";
ram_buffer(6278) := X"AFB0001C";
ram_buffer(6279) := X"AFBF0024";
ram_buffer(6280) := X"00808025";
ram_buffer(6281) := X"1080005E";
ram_buffer(6282) := X"00A08825";
ram_buffer(6283) := X"12200057";
ram_buffer(6284) := X"3C040100";
ram_buffer(6285) := X"0C40041A";
ram_buffer(6286) := X"00000000";
ram_buffer(6287) := X"8F828030";
ram_buffer(6288) := X"00000000";
ram_buffer(6289) := X"14400048";
ram_buffer(6290) := X"00000000";
ram_buffer(6291) := X"8F838038";
ram_buffer(6292) := X"8F828010";
ram_buffer(6293) := X"00000000";
ram_buffer(6294) := X"90420055";
ram_buffer(6295) := X"00000000";
ram_buffer(6296) := X"10400013";
ram_buffer(6297) := X"2404FFFF";
ram_buffer(6298) := X"8F838010";
ram_buffer(6299) := X"24020001";
ram_buffer(6300) := X"A0600055";
ram_buffer(6301) := X"8F838030";
ram_buffer(6302) := X"00000000";
ram_buffer(6303) := X"10600007";
ram_buffer(6304) := X"00000000";
ram_buffer(6305) := X"8F838010";
ram_buffer(6306) := X"00000000";
ram_buffer(6307) := X"8C630044";
ram_buffer(6308) := X"00000000";
ram_buffer(6309) := X"14600016";
ram_buffer(6310) := X"00000000";
ram_buffer(6311) := X"8FBF0024";
ram_buffer(6312) := X"8FB10020";
ram_buffer(6313) := X"8FB0001C";
ram_buffer(6314) := X"03E00008";
ram_buffer(6315) := X"27BD0028";
ram_buffer(6316) := X"8E220000";
ram_buffer(6317) := X"00000000";
ram_buffer(6318) := X"10440032";
ram_buffer(6319) := X"00000000";
ram_buffer(6320) := X"8F848024";
ram_buffer(6321) := X"8E050000";
ram_buffer(6322) := X"00000000";
ram_buffer(6323) := X"10A40017";
ram_buffer(6324) := X"00000000";
ram_buffer(6325) := X"8E040004";
ram_buffer(6326) := X"00000000";
ram_buffer(6327) := X"0064282B";
ram_buffer(6328) := X"14A00015";
ram_buffer(6329) := X"00642823";
ram_buffer(6330) := X"1000FFE2";
ram_buffer(6331) := X"24020001";
ram_buffer(6332) := X"8F848010";
ram_buffer(6333) := X"8F858010";
ram_buffer(6334) := X"8C830044";
ram_buffer(6335) := X"00000000";
ram_buffer(6336) := X"2463FFFF";
ram_buffer(6337) := X"AC830044";
ram_buffer(6338) := X"8CA30044";
ram_buffer(6339) := X"00000000";
ram_buffer(6340) := X"1460FFE2";
ram_buffer(6341) := X"00000000";
ram_buffer(6342) := X"0C400415";
ram_buffer(6343) := X"AFA20010";
ram_buffer(6344) := X"8FA20010";
ram_buffer(6345) := X"1000FFDD";
ram_buffer(6346) := X"00000000";
ram_buffer(6347) := X"8E040004";
ram_buffer(6348) := X"00000000";
ram_buffer(6349) := X"00642823";
ram_buffer(6350) := X"00A2282B";
ram_buffer(6351) := X"10A0FFEA";
ram_buffer(6352) := X"00000000";
ram_buffer(6353) := X"8F858024";
ram_buffer(6354) := X"00431023";
ram_buffer(6355) := X"8F838038";
ram_buffer(6356) := X"00441021";
ram_buffer(6357) := X"AE220000";
ram_buffer(6358) := X"00001025";
ram_buffer(6359) := X"AE050000";
ram_buffer(6360) := X"1000FFC4";
ram_buffer(6361) := X"AE030004";
ram_buffer(6362) := X"8F838010";
ram_buffer(6363) := X"8F828010";
ram_buffer(6364) := X"8C620044";
ram_buffer(6365) := X"00000000";
ram_buffer(6366) := X"24420001";
ram_buffer(6367) := X"1000FFB3";
ram_buffer(6368) := X"AC620044";
ram_buffer(6369) := X"1000FFBB";
ram_buffer(6370) := X"00001025";
ram_buffer(6371) := X"24050BDB";
ram_buffer(6372) := X"0C40041F";
ram_buffer(6373) := X"24847C38";
ram_buffer(6374) := X"1000FFA6";
ram_buffer(6375) := X"00000000";
ram_buffer(6376) := X"3C040100";
ram_buffer(6377) := X"24050BDA";
ram_buffer(6378) := X"0C40041F";
ram_buffer(6379) := X"24847C38";
ram_buffer(6380) := X"1000FF9E";
ram_buffer(6381) := X"00000000";
ram_buffer(6382) := X"24020001";
ram_buffer(6383) := X"AF828028";
ram_buffer(6384) := X"03E00008";
ram_buffer(6385) := X"00000000";
ram_buffer(6386) := X"10800011";
ram_buffer(6387) := X"00000000";
ram_buffer(6388) := X"8C850030";
ram_buffer(6389) := X"240200A5";
ram_buffer(6390) := X"90A30000";
ram_buffer(6391) := X"00000000";
ram_buffer(6392) := X"1462000E";
ram_buffer(6393) := X"00000000";
ram_buffer(6394) := X"00A01025";
ram_buffer(6395) := X"240600A5";
ram_buffer(6396) := X"24420001";
ram_buffer(6397) := X"90430000";
ram_buffer(6398) := X"00000000";
ram_buffer(6399) := X"1066FFFC";
ram_buffer(6400) := X"00452023";
ram_buffer(6401) := X"00041082";
ram_buffer(6402) := X"03E00008";
ram_buffer(6403) := X"3042FFFF";
ram_buffer(6404) := X"8F848010";
ram_buffer(6405) := X"1000FFEE";
ram_buffer(6406) := X"00000000";
ram_buffer(6407) := X"03E00008";
ram_buffer(6408) := X"00001025";
ram_buffer(6409) := X"8F828010";
ram_buffer(6410) := X"03E00008";
ram_buffer(6411) := X"00000000";
ram_buffer(6412) := X"8F828030";
ram_buffer(6413) := X"00000000";
ram_buffer(6414) := X"10400006";
ram_buffer(6415) := X"00000000";
ram_buffer(6416) := X"8F828014";
ram_buffer(6417) := X"00000000";
ram_buffer(6418) := X"2C420001";
ram_buffer(6419) := X"03E00008";
ram_buffer(6420) := X"00021040";
ram_buffer(6421) := X"03E00008";
ram_buffer(6422) := X"24020001";
ram_buffer(6423) := X"10800028";
ram_buffer(6424) := X"00000000";
ram_buffer(6425) := X"8F828010";
ram_buffer(6426) := X"8C85002C";
ram_buffer(6427) := X"8C43002C";
ram_buffer(6428) := X"27BDFFE0";
ram_buffer(6429) := X"00A3182B";
ram_buffer(6430) := X"AFBF001C";
ram_buffer(6431) := X"AFB20018";
ram_buffer(6432) := X"AFB10014";
ram_buffer(6433) := X"10600019";
ram_buffer(6434) := X"AFB00010";
ram_buffer(6435) := X"8C820018";
ram_buffer(6436) := X"00000000";
ram_buffer(6437) := X"04400008";
ram_buffer(6438) := X"00051080";
ram_buffer(6439) := X"8F828010";
ram_buffer(6440) := X"00000000";
ram_buffer(6441) := X"8C43002C";
ram_buffer(6442) := X"24020005";
ram_buffer(6443) := X"00431023";
ram_buffer(6444) := X"AC820018";
ram_buffer(6445) := X"00051080";
ram_buffer(6446) := X"00451021";
ram_buffer(6447) := X"3C110100";
ram_buffer(6448) := X"00021080";
ram_buffer(6449) := X"26317D84";
ram_buffer(6450) := X"8C830014";
ram_buffer(6451) := X"02221021";
ram_buffer(6452) := X"1062000D";
ram_buffer(6453) := X"24920004";
ram_buffer(6454) := X"8F828010";
ram_buffer(6455) := X"00000000";
ram_buffer(6456) := X"8C42002C";
ram_buffer(6457) := X"00000000";
ram_buffer(6458) := X"AC82002C";
ram_buffer(6459) := X"8FBF001C";
ram_buffer(6460) := X"8FB20018";
ram_buffer(6461) := X"8FB10014";
ram_buffer(6462) := X"8FB00010";
ram_buffer(6463) := X"27BD0020";
ram_buffer(6464) := X"03E00008";
ram_buffer(6465) := X"00000000";
ram_buffer(6466) := X"00808025";
ram_buffer(6467) := X"0C40046F";
ram_buffer(6468) := X"02402025";
ram_buffer(6469) := X"8F828010";
ram_buffer(6470) := X"8F838034";
ram_buffer(6471) := X"8C42002C";
ram_buffer(6472) := X"00000000";
ram_buffer(6473) := X"0062182B";
ram_buffer(6474) := X"10600002";
ram_buffer(6475) := X"AE02002C";
ram_buffer(6476) := X"AF828034";
ram_buffer(6477) := X"00022080";
ram_buffer(6478) := X"00822021";
ram_buffer(6479) := X"00042080";
ram_buffer(6480) := X"8FBF001C";
ram_buffer(6481) := X"8FB00010";
ram_buffer(6482) := X"02402825";
ram_buffer(6483) := X"02242021";
ram_buffer(6484) := X"8FB20018";
ram_buffer(6485) := X"8FB10014";
ram_buffer(6486) := X"08400441";
ram_buffer(6487) := X"27BD0020";
ram_buffer(6488) := X"1080003C";
ram_buffer(6489) := X"00000000";
ram_buffer(6490) := X"8F828010";
ram_buffer(6491) := X"27BDFFE0";
ram_buffer(6492) := X"AFB00014";
ram_buffer(6493) := X"AFBF001C";
ram_buffer(6494) := X"AFB10018";
ram_buffer(6495) := X"10820005";
ram_buffer(6496) := X"00808025";
ram_buffer(6497) := X"3C040100";
ram_buffer(6498) := X"24050ED6";
ram_buffer(6499) := X"0C40041F";
ram_buffer(6500) := X"24847C38";
ram_buffer(6501) := X"8E02004C";
ram_buffer(6502) := X"00000000";
ram_buffer(6503) := X"10400027";
ram_buffer(6504) := X"3C040100";
ram_buffer(6505) := X"8E04002C";
ram_buffer(6506) := X"8E030048";
ram_buffer(6507) := X"2442FFFF";
ram_buffer(6508) := X"10830003";
ram_buffer(6509) := X"AE02004C";
ram_buffer(6510) := X"10400007";
ram_buffer(6511) := X"26110004";
ram_buffer(6512) := X"8FBF001C";
ram_buffer(6513) := X"8FB10018";
ram_buffer(6514) := X"8FB00014";
ram_buffer(6515) := X"00001025";
ram_buffer(6516) := X"03E00008";
ram_buffer(6517) := X"27BD0020";
ram_buffer(6518) := X"0C40046F";
ram_buffer(6519) := X"02202025";
ram_buffer(6520) := X"8E040048";
ram_buffer(6521) := X"8F828034";
ram_buffer(6522) := X"24030005";
ram_buffer(6523) := X"00641823";
ram_buffer(6524) := X"0044102B";
ram_buffer(6525) := X"AE04002C";
ram_buffer(6526) := X"10400002";
ram_buffer(6527) := X"AE030018";
ram_buffer(6528) := X"AF848034";
ram_buffer(6529) := X"00041080";
ram_buffer(6530) := X"00442021";
ram_buffer(6531) := X"3C020100";
ram_buffer(6532) := X"24427D84";
ram_buffer(6533) := X"00042080";
ram_buffer(6534) := X"02202825";
ram_buffer(6535) := X"0C400441";
ram_buffer(6536) := X"00442021";
ram_buffer(6537) := X"8FBF001C";
ram_buffer(6538) := X"8FB10018";
ram_buffer(6539) := X"8FB00014";
ram_buffer(6540) := X"24020001";
ram_buffer(6541) := X"03E00008";
ram_buffer(6542) := X"27BD0020";
ram_buffer(6543) := X"24050ED8";
ram_buffer(6544) := X"0C40041F";
ram_buffer(6545) := X"24847C38";
ram_buffer(6546) := X"8E02004C";
ram_buffer(6547) := X"1000FFD5";
ram_buffer(6548) := X"00000000";
ram_buffer(6549) := X"03E00008";
ram_buffer(6550) := X"00001025";
ram_buffer(6551) := X"27BDFFE8";
ram_buffer(6552) := X"AFBF0014";
ram_buffer(6553) := X"0C40041A";
ram_buffer(6554) := X"00000000";
ram_buffer(6555) := X"8F828030";
ram_buffer(6556) := X"00000000";
ram_buffer(6557) := X"10400007";
ram_buffer(6558) := X"00000000";
ram_buffer(6559) := X"8F838010";
ram_buffer(6560) := X"8F828010";
ram_buffer(6561) := X"8C620044";
ram_buffer(6562) := X"00000000";
ram_buffer(6563) := X"24420001";
ram_buffer(6564) := X"AC620044";
ram_buffer(6565) := X"8FBF0014";
ram_buffer(6566) := X"00000000";
ram_buffer(6567) := X"03E00008";
ram_buffer(6568) := X"27BD0018";
ram_buffer(6569) := X"8F828030";
ram_buffer(6570) := X"00000000";
ram_buffer(6571) := X"10400011";
ram_buffer(6572) := X"00000000";
ram_buffer(6573) := X"8F828010";
ram_buffer(6574) := X"00000000";
ram_buffer(6575) := X"8C420044";
ram_buffer(6576) := X"00000000";
ram_buffer(6577) := X"1040000B";
ram_buffer(6578) := X"00000000";
ram_buffer(6579) := X"8F838010";
ram_buffer(6580) := X"8F848010";
ram_buffer(6581) := X"8C620044";
ram_buffer(6582) := X"00000000";
ram_buffer(6583) := X"2442FFFF";
ram_buffer(6584) := X"AC620044";
ram_buffer(6585) := X"8C820044";
ram_buffer(6586) := X"00000000";
ram_buffer(6587) := X"10400003";
ram_buffer(6588) := X"00000000";
ram_buffer(6589) := X"03E00008";
ram_buffer(6590) := X"00000000";
ram_buffer(6591) := X"08400415";
ram_buffer(6592) := X"00000000";
ram_buffer(6593) := X"8F828010";
ram_buffer(6594) := X"8F848010";
ram_buffer(6595) := X"8F838010";
ram_buffer(6596) := X"8C420018";
ram_buffer(6597) := X"8C65002C";
ram_buffer(6598) := X"24030005";
ram_buffer(6599) := X"00651823";
ram_buffer(6600) := X"03E00008";
ram_buffer(6601) := X"AC830018";
ram_buffer(6602) := X"8F828010";
ram_buffer(6603) := X"00000000";
ram_buffer(6604) := X"10400007";
ram_buffer(6605) := X"00000000";
ram_buffer(6606) := X"8F838010";
ram_buffer(6607) := X"00000000";
ram_buffer(6608) := X"8C62004C";
ram_buffer(6609) := X"00000000";
ram_buffer(6610) := X"24420001";
ram_buffer(6611) := X"AC62004C";
ram_buffer(6612) := X"8F828010";
ram_buffer(6613) := X"03E00008";
ram_buffer(6614) := X"00000000";
ram_buffer(6615) := X"27BDFFD8";
ram_buffer(6616) := X"AFB1001C";
ram_buffer(6617) := X"AFB00018";
ram_buffer(6618) := X"AFBF0024";
ram_buffer(6619) := X"AFB20020";
ram_buffer(6620) := X"00808825";
ram_buffer(6621) := X"0C40041A";
ram_buffer(6622) := X"00A08025";
ram_buffer(6623) := X"8F828030";
ram_buffer(6624) := X"00000000";
ram_buffer(6625) := X"14400052";
ram_buffer(6626) := X"00000000";
ram_buffer(6627) := X"8F828010";
ram_buffer(6628) := X"00000000";
ram_buffer(6629) := X"8C420050";
ram_buffer(6630) := X"00000000";
ram_buffer(6631) := X"14400006";
ram_buffer(6632) := X"00000000";
ram_buffer(6633) := X"8F828010";
ram_buffer(6634) := X"24030001";
ram_buffer(6635) := X"A0430054";
ram_buffer(6636) := X"1600005C";
ram_buffer(6637) := X"00000000";
ram_buffer(6638) := X"8F828030";
ram_buffer(6639) := X"00000000";
ram_buffer(6640) := X"10400007";
ram_buffer(6641) := X"00000000";
ram_buffer(6642) := X"8F828010";
ram_buffer(6643) := X"00000000";
ram_buffer(6644) := X"8C420044";
ram_buffer(6645) := X"00000000";
ram_buffer(6646) := X"14400044";
ram_buffer(6647) := X"00000000";
ram_buffer(6648) := X"0C40041A";
ram_buffer(6649) := X"00000000";
ram_buffer(6650) := X"8F828030";
ram_buffer(6651) := X"00000000";
ram_buffer(6652) := X"14400030";
ram_buffer(6653) := X"00000000";
ram_buffer(6654) := X"8F828010";
ram_buffer(6655) := X"00000000";
ram_buffer(6656) := X"8C420050";
ram_buffer(6657) := X"00000000";
ram_buffer(6658) := X"10400005";
ram_buffer(6659) := X"00000000";
ram_buffer(6660) := X"8F838010";
ram_buffer(6661) := X"12200015";
ram_buffer(6662) := X"2444FFFF";
ram_buffer(6663) := X"AC600050";
ram_buffer(6664) := X"8F838010";
ram_buffer(6665) := X"00000000";
ram_buffer(6666) := X"A0600054";
ram_buffer(6667) := X"8F838030";
ram_buffer(6668) := X"00000000";
ram_buffer(6669) := X"10600007";
ram_buffer(6670) := X"00000000";
ram_buffer(6671) := X"8F838010";
ram_buffer(6672) := X"00000000";
ram_buffer(6673) := X"8C630044";
ram_buffer(6674) := X"00000000";
ram_buffer(6675) := X"1460000A";
ram_buffer(6676) := X"00000000";
ram_buffer(6677) := X"8FBF0024";
ram_buffer(6678) := X"8FB20020";
ram_buffer(6679) := X"8FB1001C";
ram_buffer(6680) := X"8FB00018";
ram_buffer(6681) := X"03E00008";
ram_buffer(6682) := X"27BD0028";
ram_buffer(6683) := X"AC640050";
ram_buffer(6684) := X"1000FFEB";
ram_buffer(6685) := X"00000000";
ram_buffer(6686) := X"8F848010";
ram_buffer(6687) := X"8F858010";
ram_buffer(6688) := X"8C830044";
ram_buffer(6689) := X"00000000";
ram_buffer(6690) := X"2463FFFF";
ram_buffer(6691) := X"AC830044";
ram_buffer(6692) := X"8CA30044";
ram_buffer(6693) := X"00000000";
ram_buffer(6694) := X"1460FFEE";
ram_buffer(6695) := X"00000000";
ram_buffer(6696) := X"0C400415";
ram_buffer(6697) := X"AFA20010";
ram_buffer(6698) := X"8FA20010";
ram_buffer(6699) := X"1000FFE9";
ram_buffer(6700) := X"00000000";
ram_buffer(6701) := X"8F838010";
ram_buffer(6702) := X"8F828010";
ram_buffer(6703) := X"8C620044";
ram_buffer(6704) := X"00000000";
ram_buffer(6705) := X"24420001";
ram_buffer(6706) := X"1000FFCB";
ram_buffer(6707) := X"AC620044";
ram_buffer(6708) := X"8F838010";
ram_buffer(6709) := X"8F828010";
ram_buffer(6710) := X"8C620044";
ram_buffer(6711) := X"00000000";
ram_buffer(6712) := X"24420001";
ram_buffer(6713) := X"1000FFA9";
ram_buffer(6714) := X"AC620044";
ram_buffer(6715) := X"8F838010";
ram_buffer(6716) := X"8F848010";
ram_buffer(6717) := X"8C620044";
ram_buffer(6718) := X"00000000";
ram_buffer(6719) := X"2442FFFF";
ram_buffer(6720) := X"AC620044";
ram_buffer(6721) := X"8C820044";
ram_buffer(6722) := X"00000000";
ram_buffer(6723) := X"1440FFB4";
ram_buffer(6724) := X"00000000";
ram_buffer(6725) := X"0C400415";
ram_buffer(6726) := X"00000000";
ram_buffer(6727) := X"1000FFB0";
ram_buffer(6728) := X"00000000";
ram_buffer(6729) := X"8F928038";
ram_buffer(6730) := X"8F828010";
ram_buffer(6731) := X"8F848010";
ram_buffer(6732) := X"A0400055";
ram_buffer(6733) := X"0C40046F";
ram_buffer(6734) := X"24840004";
ram_buffer(6735) := X"2402FFFF";
ram_buffer(6736) := X"1202001C";
ram_buffer(6737) := X"00000000";
ram_buffer(6738) := X"02128021";
ram_buffer(6739) := X"8F828010";
ram_buffer(6740) := X"0212902B";
ram_buffer(6741) := X"1640000F";
ram_buffer(6742) := X"AC500004";
ram_buffer(6743) := X"8F848048";
ram_buffer(6744) := X"8F858010";
ram_buffer(6745) := X"0C40044D";
ram_buffer(6746) := X"24A50004";
ram_buffer(6747) := X"8F82801C";
ram_buffer(6748) := X"00000000";
ram_buffer(6749) := X"0202102B";
ram_buffer(6750) := X"10400002";
ram_buffer(6751) := X"00000000";
ram_buffer(6752) := X"AF90801C";
ram_buffer(6753) := X"0C4001B1";
ram_buffer(6754) := X"00000000";
ram_buffer(6755) := X"1000FF8A";
ram_buffer(6756) := X"00000000";
ram_buffer(6757) := X"8F848044";
ram_buffer(6758) := X"8F858010";
ram_buffer(6759) := X"0C40044D";
ram_buffer(6760) := X"24A50004";
ram_buffer(6761) := X"0C4001B1";
ram_buffer(6762) := X"00000000";
ram_buffer(6763) := X"1000FF82";
ram_buffer(6764) := X"00000000";
ram_buffer(6765) := X"8F858010";
ram_buffer(6766) := X"3C040100";
ram_buffer(6767) := X"24A50004";
ram_buffer(6768) := X"0C400441";
ram_buffer(6769) := X"24847D20";
ram_buffer(6770) := X"0C4001B1";
ram_buffer(6771) := X"00000000";
ram_buffer(6772) := X"1000FF79";
ram_buffer(6773) := X"00000000";
ram_buffer(6774) := X"27BDFFD0";
ram_buffer(6775) := X"AFB30028";
ram_buffer(6776) := X"AFB20024";
ram_buffer(6777) := X"AFB10020";
ram_buffer(6778) := X"AFB0001C";
ram_buffer(6779) := X"AFBF002C";
ram_buffer(6780) := X"00808825";
ram_buffer(6781) := X"00A08025";
ram_buffer(6782) := X"00C09025";
ram_buffer(6783) := X"0C40041A";
ram_buffer(6784) := X"00E09825";
ram_buffer(6785) := X"8F828030";
ram_buffer(6786) := X"00000000";
ram_buffer(6787) := X"14400061";
ram_buffer(6788) := X"00000000";
ram_buffer(6789) := X"8F828010";
ram_buffer(6790) := X"24030002";
ram_buffer(6791) := X"90420054";
ram_buffer(6792) := X"00000000";
ram_buffer(6793) := X"304200FF";
ram_buffer(6794) := X"1043000C";
ram_buffer(6795) := X"00000000";
ram_buffer(6796) := X"8F828010";
ram_buffer(6797) := X"00118827";
ram_buffer(6798) := X"8C440050";
ram_buffer(6799) := X"24030001";
ram_buffer(6800) := X"02248824";
ram_buffer(6801) := X"AC510050";
ram_buffer(6802) := X"8F828010";
ram_buffer(6803) := X"00000000";
ram_buffer(6804) := X"A0430054";
ram_buffer(6805) := X"16600056";
ram_buffer(6806) := X"00000000";
ram_buffer(6807) := X"8F828030";
ram_buffer(6808) := X"00000000";
ram_buffer(6809) := X"10400007";
ram_buffer(6810) := X"00000000";
ram_buffer(6811) := X"8F828010";
ram_buffer(6812) := X"00000000";
ram_buffer(6813) := X"8C420044";
ram_buffer(6814) := X"00000000";
ram_buffer(6815) := X"14400068";
ram_buffer(6816) := X"00000000";
ram_buffer(6817) := X"0C40041A";
ram_buffer(6818) := X"00000000";
ram_buffer(6819) := X"8F828030";
ram_buffer(6820) := X"00000000";
ram_buffer(6821) := X"14400038";
ram_buffer(6822) := X"00000000";
ram_buffer(6823) := X"12400006";
ram_buffer(6824) := X"00000000";
ram_buffer(6825) := X"8F828010";
ram_buffer(6826) := X"00000000";
ram_buffer(6827) := X"8C420050";
ram_buffer(6828) := X"00000000";
ram_buffer(6829) := X"AE420000";
ram_buffer(6830) := X"8F828010";
ram_buffer(6831) := X"24030001";
ram_buffer(6832) := X"90420054";
ram_buffer(6833) := X"00000000";
ram_buffer(6834) := X"304200FF";
ram_buffer(6835) := X"10430007";
ram_buffer(6836) := X"00001025";
ram_buffer(6837) := X"8F838010";
ram_buffer(6838) := X"00108027";
ram_buffer(6839) := X"8C640050";
ram_buffer(6840) := X"24020001";
ram_buffer(6841) := X"02048024";
ram_buffer(6842) := X"AC700050";
ram_buffer(6843) := X"8F838010";
ram_buffer(6844) := X"00000000";
ram_buffer(6845) := X"A0600054";
ram_buffer(6846) := X"8F838030";
ram_buffer(6847) := X"00000000";
ram_buffer(6848) := X"10600007";
ram_buffer(6849) := X"00000000";
ram_buffer(6850) := X"8F838010";
ram_buffer(6851) := X"00000000";
ram_buffer(6852) := X"8C630044";
ram_buffer(6853) := X"00000000";
ram_buffer(6854) := X"14600008";
ram_buffer(6855) := X"00000000";
ram_buffer(6856) := X"8FBF002C";
ram_buffer(6857) := X"8FB30028";
ram_buffer(6858) := X"8FB20024";
ram_buffer(6859) := X"8FB10020";
ram_buffer(6860) := X"8FB0001C";
ram_buffer(6861) := X"03E00008";
ram_buffer(6862) := X"27BD0030";
ram_buffer(6863) := X"8F848010";
ram_buffer(6864) := X"8F858010";
ram_buffer(6865) := X"8C830044";
ram_buffer(6866) := X"00000000";
ram_buffer(6867) := X"2463FFFF";
ram_buffer(6868) := X"AC830044";
ram_buffer(6869) := X"8CA30044";
ram_buffer(6870) := X"00000000";
ram_buffer(6871) := X"1460FFF0";
ram_buffer(6872) := X"00000000";
ram_buffer(6873) := X"0C400415";
ram_buffer(6874) := X"AFA20010";
ram_buffer(6875) := X"8FA20010";
ram_buffer(6876) := X"1000FFEB";
ram_buffer(6877) := X"00000000";
ram_buffer(6878) := X"8F838010";
ram_buffer(6879) := X"8F828010";
ram_buffer(6880) := X"8C620044";
ram_buffer(6881) := X"00000000";
ram_buffer(6882) := X"24420001";
ram_buffer(6883) := X"1000FFC3";
ram_buffer(6884) := X"AC620044";
ram_buffer(6885) := X"8F838010";
ram_buffer(6886) := X"8F828010";
ram_buffer(6887) := X"8C620044";
ram_buffer(6888) := X"00000000";
ram_buffer(6889) := X"24420001";
ram_buffer(6890) := X"1000FF9A";
ram_buffer(6891) := X"AC620044";
ram_buffer(6892) := X"8F918038";
ram_buffer(6893) := X"8F828010";
ram_buffer(6894) := X"8F848010";
ram_buffer(6895) := X"A0400055";
ram_buffer(6896) := X"0C40046F";
ram_buffer(6897) := X"24840004";
ram_buffer(6898) := X"2402FFFF";
ram_buffer(6899) := X"12620022";
ram_buffer(6900) := X"00000000";
ram_buffer(6901) := X"02719821";
ram_buffer(6902) := X"8F828010";
ram_buffer(6903) := X"0271882B";
ram_buffer(6904) := X"16200026";
ram_buffer(6905) := X"AC530004";
ram_buffer(6906) := X"8F848048";
ram_buffer(6907) := X"8F858010";
ram_buffer(6908) := X"0C40044D";
ram_buffer(6909) := X"24A50004";
ram_buffer(6910) := X"8F82801C";
ram_buffer(6911) := X"00000000";
ram_buffer(6912) := X"0262102B";
ram_buffer(6913) := X"10400002";
ram_buffer(6914) := X"00000000";
ram_buffer(6915) := X"AF93801C";
ram_buffer(6916) := X"0C4001B1";
ram_buffer(6917) := X"00000000";
ram_buffer(6918) := X"1000FF90";
ram_buffer(6919) := X"00000000";
ram_buffer(6920) := X"8F838010";
ram_buffer(6921) := X"8F848010";
ram_buffer(6922) := X"8C620044";
ram_buffer(6923) := X"00000000";
ram_buffer(6924) := X"2442FFFF";
ram_buffer(6925) := X"AC620044";
ram_buffer(6926) := X"8C820044";
ram_buffer(6927) := X"00000000";
ram_buffer(6928) := X"1440FF90";
ram_buffer(6929) := X"00000000";
ram_buffer(6930) := X"0C400415";
ram_buffer(6931) := X"00000000";
ram_buffer(6932) := X"1000FF8C";
ram_buffer(6933) := X"00000000";
ram_buffer(6934) := X"8F858010";
ram_buffer(6935) := X"3C040100";
ram_buffer(6936) := X"24A50004";
ram_buffer(6937) := X"0C400441";
ram_buffer(6938) := X"24847D20";
ram_buffer(6939) := X"0C4001B1";
ram_buffer(6940) := X"00000000";
ram_buffer(6941) := X"1000FF79";
ram_buffer(6942) := X"00000000";
ram_buffer(6943) := X"8F848044";
ram_buffer(6944) := X"8F858010";
ram_buffer(6945) := X"0C40044D";
ram_buffer(6946) := X"24A50004";
ram_buffer(6947) := X"0C4001B1";
ram_buffer(6948) := X"00000000";
ram_buffer(6949) := X"1000FF71";
ram_buffer(6950) := X"00000000";
ram_buffer(6951) := X"27BDFFD0";
ram_buffer(6952) := X"AFB30028";
ram_buffer(6953) := X"AFB20024";
ram_buffer(6954) := X"AFB10020";
ram_buffer(6955) := X"AFB0001C";
ram_buffer(6956) := X"AFBF002C";
ram_buffer(6957) := X"00808025";
ram_buffer(6958) := X"00A09825";
ram_buffer(6959) := X"00C08825";
ram_buffer(6960) := X"1080007D";
ram_buffer(6961) := X"00E09025";
ram_buffer(6962) := X"0C40041A";
ram_buffer(6963) := X"00000000";
ram_buffer(6964) := X"8F828030";
ram_buffer(6965) := X"00000000";
ram_buffer(6966) := X"14400059";
ram_buffer(6967) := X"00000000";
ram_buffer(6968) := X"12400004";
ram_buffer(6969) := X"00000000";
ram_buffer(6970) := X"8E020050";
ram_buffer(6971) := X"00000000";
ram_buffer(6972) := X"AE420000";
ram_buffer(6973) := X"92020054";
ram_buffer(6974) := X"24040002";
ram_buffer(6975) := X"24030002";
ram_buffer(6976) := X"304200FF";
ram_buffer(6977) := X"A2040054";
ram_buffer(6978) := X"12230063";
ram_buffer(6979) := X"2E240003";
ram_buffer(6980) := X"1480001D";
ram_buffer(6981) := X"24040003";
ram_buffer(6982) := X"12240005";
ram_buffer(6983) := X"24040004";
ram_buffer(6984) := X"16240004";
ram_buffer(6985) := X"00000000";
ram_buffer(6986) := X"10430061";
ram_buffer(6987) := X"00000000";
ram_buffer(6988) := X"AE130050";
ram_buffer(6989) := X"24030001";
ram_buffer(6990) := X"1043001E";
ram_buffer(6991) := X"26110004";
ram_buffer(6992) := X"24020001";
ram_buffer(6993) := X"8F838030";
ram_buffer(6994) := X"00000000";
ram_buffer(6995) := X"10600007";
ram_buffer(6996) := X"00000000";
ram_buffer(6997) := X"8F838010";
ram_buffer(6998) := X"00000000";
ram_buffer(6999) := X"8C630044";
ram_buffer(7000) := X"00000000";
ram_buffer(7001) := X"1460003D";
ram_buffer(7002) := X"00000000";
ram_buffer(7003) := X"8FBF002C";
ram_buffer(7004) := X"8FB30028";
ram_buffer(7005) := X"8FB20024";
ram_buffer(7006) := X"8FB10020";
ram_buffer(7007) := X"8FB0001C";
ram_buffer(7008) := X"03E00008";
ram_buffer(7009) := X"27BD0030";
ram_buffer(7010) := X"24030001";
ram_buffer(7011) := X"1623FFEA";
ram_buffer(7012) := X"00000000";
ram_buffer(7013) := X"8E030050";
ram_buffer(7014) := X"00000000";
ram_buffer(7015) := X"00739825";
ram_buffer(7016) := X"24030001";
ram_buffer(7017) := X"AE130050";
ram_buffer(7018) := X"1443FFE6";
ram_buffer(7019) := X"24020001";
ram_buffer(7020) := X"26110004";
ram_buffer(7021) := X"0C40046F";
ram_buffer(7022) := X"02202025";
ram_buffer(7023) := X"8E04002C";
ram_buffer(7024) := X"8F828034";
ram_buffer(7025) := X"00000000";
ram_buffer(7026) := X"0044102B";
ram_buffer(7027) := X"10400003";
ram_buffer(7028) := X"00041080";
ram_buffer(7029) := X"AF848034";
ram_buffer(7030) := X"00041080";
ram_buffer(7031) := X"00441021";
ram_buffer(7032) := X"3C040100";
ram_buffer(7033) := X"00021080";
ram_buffer(7034) := X"24847D84";
ram_buffer(7035) := X"00822021";
ram_buffer(7036) := X"0C400441";
ram_buffer(7037) := X"02202825";
ram_buffer(7038) := X"8E020028";
ram_buffer(7039) := X"00000000";
ram_buffer(7040) := X"10400004";
ram_buffer(7041) := X"24051144";
ram_buffer(7042) := X"3C040100";
ram_buffer(7043) := X"0C40041F";
ram_buffer(7044) := X"24847C38";
ram_buffer(7045) := X"8F838010";
ram_buffer(7046) := X"8E02002C";
ram_buffer(7047) := X"8C63002C";
ram_buffer(7048) := X"00000000";
ram_buffer(7049) := X"0062102B";
ram_buffer(7050) := X"1040FFC5";
ram_buffer(7051) := X"00000000";
ram_buffer(7052) := X"0C4001B1";
ram_buffer(7053) := X"00000000";
ram_buffer(7054) := X"1000FFC2";
ram_buffer(7055) := X"24020001";
ram_buffer(7056) := X"8F838010";
ram_buffer(7057) := X"8F828010";
ram_buffer(7058) := X"8C620044";
ram_buffer(7059) := X"00000000";
ram_buffer(7060) := X"24420001";
ram_buffer(7061) := X"1000FFA2";
ram_buffer(7062) := X"AC620044";
ram_buffer(7063) := X"8F848010";
ram_buffer(7064) := X"8F858010";
ram_buffer(7065) := X"8C830044";
ram_buffer(7066) := X"00000000";
ram_buffer(7067) := X"2463FFFF";
ram_buffer(7068) := X"AC830044";
ram_buffer(7069) := X"8CA30044";
ram_buffer(7070) := X"00000000";
ram_buffer(7071) := X"1460FFBB";
ram_buffer(7072) := X"00000000";
ram_buffer(7073) := X"0C400415";
ram_buffer(7074) := X"AFA20010";
ram_buffer(7075) := X"8FA20010";
ram_buffer(7076) := X"1000FFB6";
ram_buffer(7077) := X"00000000";
ram_buffer(7078) := X"8E030050";
ram_buffer(7079) := X"00000000";
ram_buffer(7080) := X"24630001";
ram_buffer(7081) := X"AE030050";
ram_buffer(7082) := X"1000FFA3";
ram_buffer(7083) := X"24030001";
ram_buffer(7084) := X"1000FFA4";
ram_buffer(7085) := X"00001025";
ram_buffer(7086) := X"3C040100";
ram_buffer(7087) := X"2405110C";
ram_buffer(7088) := X"0C40041F";
ram_buffer(7089) := X"24847C38";
ram_buffer(7090) := X"1000FF7F";
ram_buffer(7091) := X"00000000";
ram_buffer(7092) := X"27BDFFD8";
ram_buffer(7093) := X"AFB10020";
ram_buffer(7094) := X"AFB0001C";
ram_buffer(7095) := X"AFBF0024";
ram_buffer(7096) := X"00808025";
ram_buffer(7097) := X"10800063";
ram_buffer(7098) := X"00A08825";
ram_buffer(7099) := X"10E00004";
ram_buffer(7100) := X"00000000";
ram_buffer(7101) := X"8E020050";
ram_buffer(7102) := X"00000000";
ram_buffer(7103) := X"ACE20000";
ram_buffer(7104) := X"92020054";
ram_buffer(7105) := X"24040002";
ram_buffer(7106) := X"24030002";
ram_buffer(7107) := X"304200FF";
ram_buffer(7108) := X"A2040054";
ram_buffer(7109) := X"10C3003C";
ram_buffer(7110) := X"2CC40003";
ram_buffer(7111) := X"14800031";
ram_buffer(7112) := X"24040003";
ram_buffer(7113) := X"10C40005";
ram_buffer(7114) := X"24040004";
ram_buffer(7115) := X"14C40004";
ram_buffer(7116) := X"00000000";
ram_buffer(7117) := X"1043004D";
ram_buffer(7118) := X"00000000";
ram_buffer(7119) := X"AE110050";
ram_buffer(7120) := X"24030001";
ram_buffer(7121) := X"10430006";
ram_buffer(7122) := X"24020001";
ram_buffer(7123) := X"8FBF0024";
ram_buffer(7124) := X"8FB10020";
ram_buffer(7125) := X"8FB0001C";
ram_buffer(7126) := X"03E00008";
ram_buffer(7127) := X"27BD0028";
ram_buffer(7128) := X"8E020028";
ram_buffer(7129) := X"00000000";
ram_buffer(7130) := X"10400004";
ram_buffer(7131) := X"240511BE";
ram_buffer(7132) := X"3C040100";
ram_buffer(7133) := X"0C40041F";
ram_buffer(7134) := X"24847C38";
ram_buffer(7135) := X"8F828014";
ram_buffer(7136) := X"00000000";
ram_buffer(7137) := X"10400026";
ram_buffer(7138) := X"26110004";
ram_buffer(7139) := X"3C040100";
ram_buffer(7140) := X"26050018";
ram_buffer(7141) := X"0C400441";
ram_buffer(7142) := X"24847D48";
ram_buffer(7143) := X"8F838010";
ram_buffer(7144) := X"8E02002C";
ram_buffer(7145) := X"8C63002C";
ram_buffer(7146) := X"00000000";
ram_buffer(7147) := X"0062102B";
ram_buffer(7148) := X"1040FFE6";
ram_buffer(7149) := X"24020001";
ram_buffer(7150) := X"8FA20038";
ram_buffer(7151) := X"00000000";
ram_buffer(7152) := X"10400036";
ram_buffer(7153) := X"00401825";
ram_buffer(7154) := X"8FBF0024";
ram_buffer(7155) := X"24020001";
ram_buffer(7156) := X"8FB10020";
ram_buffer(7157) := X"8FB0001C";
ram_buffer(7158) := X"AC620000";
ram_buffer(7159) := X"03E00008";
ram_buffer(7160) := X"27BD0028";
ram_buffer(7161) := X"24030001";
ram_buffer(7162) := X"14C3FFD6";
ram_buffer(7163) := X"00000000";
ram_buffer(7164) := X"8E030050";
ram_buffer(7165) := X"00000000";
ram_buffer(7166) := X"00718825";
ram_buffer(7167) := X"AE110050";
ram_buffer(7168) := X"1000FFD0";
ram_buffer(7169) := X"24030001";
ram_buffer(7170) := X"8E030050";
ram_buffer(7171) := X"00000000";
ram_buffer(7172) := X"24630001";
ram_buffer(7173) := X"AE030050";
ram_buffer(7174) := X"1000FFCA";
ram_buffer(7175) := X"24030001";
ram_buffer(7176) := X"0C40046F";
ram_buffer(7177) := X"02202025";
ram_buffer(7178) := X"8E04002C";
ram_buffer(7179) := X"8F828034";
ram_buffer(7180) := X"00000000";
ram_buffer(7181) := X"0044102B";
ram_buffer(7182) := X"10400003";
ram_buffer(7183) := X"00041080";
ram_buffer(7184) := X"AF848034";
ram_buffer(7185) := X"00041080";
ram_buffer(7186) := X"00441021";
ram_buffer(7187) := X"3C040100";
ram_buffer(7188) := X"00021080";
ram_buffer(7189) := X"24847D84";
ram_buffer(7190) := X"02202825";
ram_buffer(7191) := X"0C400441";
ram_buffer(7192) := X"00822021";
ram_buffer(7193) := X"1000FFCD";
ram_buffer(7194) := X"00000000";
ram_buffer(7195) := X"1000FFB7";
ram_buffer(7196) := X"00001025";
ram_buffer(7197) := X"3C040100";
ram_buffer(7198) := X"24051177";
ram_buffer(7199) := X"24847C38";
ram_buffer(7200) := X"AFA70014";
ram_buffer(7201) := X"0C40041F";
ram_buffer(7202) := X"AFA60010";
ram_buffer(7203) := X"8FA70014";
ram_buffer(7204) := X"8FA60010";
ram_buffer(7205) := X"1000FF95";
ram_buffer(7206) := X"00000000";
ram_buffer(7207) := X"24020001";
ram_buffer(7208) := X"AF828028";
ram_buffer(7209) := X"1000FFA9";
ram_buffer(7210) := X"00000000";
ram_buffer(7211) := X"27BDFFE0";
ram_buffer(7212) := X"AFB10014";
ram_buffer(7213) := X"AFB00010";
ram_buffer(7214) := X"AFBF001C";
ram_buffer(7215) := X"AFB20018";
ram_buffer(7216) := X"00808025";
ram_buffer(7217) := X"10800043";
ram_buffer(7218) := X"00A08825";
ram_buffer(7219) := X"24030002";
ram_buffer(7220) := X"92020054";
ram_buffer(7221) := X"A2030054";
ram_buffer(7222) := X"8E030050";
ram_buffer(7223) := X"304200FF";
ram_buffer(7224) := X"24630001";
ram_buffer(7225) := X"24040001";
ram_buffer(7226) := X"AE030050";
ram_buffer(7227) := X"10440007";
ram_buffer(7228) := X"00000000";
ram_buffer(7229) := X"8FBF001C";
ram_buffer(7230) := X"8FB20018";
ram_buffer(7231) := X"8FB10014";
ram_buffer(7232) := X"8FB00010";
ram_buffer(7233) := X"03E00008";
ram_buffer(7234) := X"27BD0020";
ram_buffer(7235) := X"8E020028";
ram_buffer(7236) := X"00000000";
ram_buffer(7237) := X"10400004";
ram_buffer(7238) := X"24051218";
ram_buffer(7239) := X"3C040100";
ram_buffer(7240) := X"0C40041F";
ram_buffer(7241) := X"24847C38";
ram_buffer(7242) := X"8F828014";
ram_buffer(7243) := X"00000000";
ram_buffer(7244) := X"10400015";
ram_buffer(7245) := X"26120004";
ram_buffer(7246) := X"3C040100";
ram_buffer(7247) := X"26050018";
ram_buffer(7248) := X"0C400441";
ram_buffer(7249) := X"24847D48";
ram_buffer(7250) := X"8F838010";
ram_buffer(7251) := X"8E02002C";
ram_buffer(7252) := X"8C63002C";
ram_buffer(7253) := X"00000000";
ram_buffer(7254) := X"0062102B";
ram_buffer(7255) := X"1040FFE5";
ram_buffer(7256) := X"00000000";
ram_buffer(7257) := X"12200021";
ram_buffer(7258) := X"24020001";
ram_buffer(7259) := X"8FBF001C";
ram_buffer(7260) := X"AE220000";
ram_buffer(7261) := X"8FB20018";
ram_buffer(7262) := X"8FB10014";
ram_buffer(7263) := X"8FB00010";
ram_buffer(7264) := X"03E00008";
ram_buffer(7265) := X"27BD0020";
ram_buffer(7266) := X"0C40046F";
ram_buffer(7267) := X"02402025";
ram_buffer(7268) := X"8E04002C";
ram_buffer(7269) := X"8F828034";
ram_buffer(7270) := X"00000000";
ram_buffer(7271) := X"0044102B";
ram_buffer(7272) := X"10400003";
ram_buffer(7273) := X"00041080";
ram_buffer(7274) := X"AF848034";
ram_buffer(7275) := X"00041080";
ram_buffer(7276) := X"00441021";
ram_buffer(7277) := X"3C040100";
ram_buffer(7278) := X"00021080";
ram_buffer(7279) := X"24847D84";
ram_buffer(7280) := X"02402825";
ram_buffer(7281) := X"0C400441";
ram_buffer(7282) := X"00822021";
ram_buffer(7283) := X"1000FFDE";
ram_buffer(7284) := X"00000000";
ram_buffer(7285) := X"3C040100";
ram_buffer(7286) := X"240511F2";
ram_buffer(7287) := X"0C40041F";
ram_buffer(7288) := X"24847C38";
ram_buffer(7289) := X"1000FFBA";
ram_buffer(7290) := X"24030002";
ram_buffer(7291) := X"AF828028";
ram_buffer(7292) := X"1000FFC0";
ram_buffer(7293) := X"00000000";
ram_buffer(7294) := X"27BDFFE0";
ram_buffer(7295) := X"AFBF001C";
ram_buffer(7296) := X"10800039";
ram_buffer(7297) := X"AFB00018";
ram_buffer(7298) := X"00808025";
ram_buffer(7299) := X"0C40041A";
ram_buffer(7300) := X"00000000";
ram_buffer(7301) := X"8F828030";
ram_buffer(7302) := X"00000000";
ram_buffer(7303) := X"14400024";
ram_buffer(7304) := X"00000000";
ram_buffer(7305) := X"92020054";
ram_buffer(7306) := X"24030002";
ram_buffer(7307) := X"304200FF";
ram_buffer(7308) := X"1043002A";
ram_buffer(7309) := X"00000000";
ram_buffer(7310) := X"00001025";
ram_buffer(7311) := X"8F838030";
ram_buffer(7312) := X"00000000";
ram_buffer(7313) := X"10600007";
ram_buffer(7314) := X"00000000";
ram_buffer(7315) := X"8F838010";
ram_buffer(7316) := X"00000000";
ram_buffer(7317) := X"8C630044";
ram_buffer(7318) := X"00000000";
ram_buffer(7319) := X"14600005";
ram_buffer(7320) := X"00000000";
ram_buffer(7321) := X"8FBF001C";
ram_buffer(7322) := X"8FB00018";
ram_buffer(7323) := X"03E00008";
ram_buffer(7324) := X"27BD0020";
ram_buffer(7325) := X"8F848010";
ram_buffer(7326) := X"8F858010";
ram_buffer(7327) := X"8C830044";
ram_buffer(7328) := X"00000000";
ram_buffer(7329) := X"2463FFFF";
ram_buffer(7330) := X"AC830044";
ram_buffer(7331) := X"8CA30044";
ram_buffer(7332) := X"00000000";
ram_buffer(7333) := X"1460FFF3";
ram_buffer(7334) := X"00000000";
ram_buffer(7335) := X"0C400415";
ram_buffer(7336) := X"AFA20010";
ram_buffer(7337) := X"8FA20010";
ram_buffer(7338) := X"1000FFEE";
ram_buffer(7339) := X"00000000";
ram_buffer(7340) := X"8F838010";
ram_buffer(7341) := X"8F828010";
ram_buffer(7342) := X"8C620044";
ram_buffer(7343) := X"00000000";
ram_buffer(7344) := X"24420001";
ram_buffer(7345) := X"AC620044";
ram_buffer(7346) := X"92020054";
ram_buffer(7347) := X"24030002";
ram_buffer(7348) := X"304200FF";
ram_buffer(7349) := X"1443FFD8";
ram_buffer(7350) := X"00000000";
ram_buffer(7351) := X"A2000054";
ram_buffer(7352) := X"1000FFD6";
ram_buffer(7353) := X"24020001";
ram_buffer(7354) := X"8F908010";
ram_buffer(7355) := X"1000FFC7";
ram_buffer(7356) := X"00000000";
ram_buffer(7357) := X"03E00008";
ram_buffer(7358) := X"00000000";
ram_buffer(7359) := X"27BDFFE8";
ram_buffer(7360) := X"AFBF0014";
ram_buffer(7361) := X"0C400178";
ram_buffer(7362) := X"00000000";
ram_buffer(7363) := X"0C400415";
ram_buffer(7364) := X"00000000";
ram_buffer(7365) := X"0C400187";
ram_buffer(7366) := X"00000000";
ram_buffer(7367) := X"0C40041A";
ram_buffer(7368) := X"00000000";
ram_buffer(7369) := X"1000FFFF";
ram_buffer(7370) := X"00000000";
ram_buffer(7371) := X"3C040100";
ram_buffer(7372) := X"24050070";
ram_buffer(7373) := X"0840041F";
ram_buffer(7374) := X"24847C58";
ram_buffer(7375) := X"27BDFFD8";
ram_buffer(7376) := X"AFB10018";
ram_buffer(7377) := X"AFBF0024";
ram_buffer(7378) := X"AFB30020";
ram_buffer(7379) := X"AFB2001C";
ram_buffer(7380) := X"AFB00014";
ram_buffer(7381) := X"0C4010EF";
ram_buffer(7382) := X"00808825";
ram_buffer(7383) := X"8F87805C";
ram_buffer(7384) := X"00000000";
ram_buffer(7385) := X"10E00073";
ram_buffer(7386) := X"3C040100";
ram_buffer(7387) := X"8F868050";
ram_buffer(7388) := X"00000000";
ram_buffer(7389) := X"02261024";
ram_buffer(7390) := X"1440005A";
ram_buffer(7391) := X"00000000";
ram_buffer(7392) := X"12200058";
ram_buffer(7393) := X"26310008";
ram_buffer(7394) := X"32220003";
ram_buffer(7395) := X"10400003";
ram_buffer(7396) := X"2402FFFC";
ram_buffer(7397) := X"02228824";
ram_buffer(7398) := X"26310004";
ram_buffer(7399) := X"12200051";
ram_buffer(7400) := X"00000000";
ram_buffer(7401) := X"8F858058";
ram_buffer(7402) := X"00000000";
ram_buffer(7403) := X"00B1102B";
ram_buffer(7404) := X"1440004C";
ram_buffer(7405) := X"27848060";
ram_buffer(7406) := X"8F908060";
ram_buffer(7407) := X"10000007";
ram_buffer(7408) := X"00000000";
ram_buffer(7409) := X"8E020000";
ram_buffer(7410) := X"00000000";
ram_buffer(7411) := X"10400008";
ram_buffer(7412) := X"00000000";
ram_buffer(7413) := X"02002025";
ram_buffer(7414) := X"00408025";
ram_buffer(7415) := X"8E030004";
ram_buffer(7416) := X"00000000";
ram_buffer(7417) := X"0071102B";
ram_buffer(7418) := X"1440FFF6";
ram_buffer(7419) := X"00000000";
ram_buffer(7420) := X"1207003C";
ram_buffer(7421) := X"00711023";
ram_buffer(7422) := X"8E080000";
ram_buffer(7423) := X"2C470011";
ram_buffer(7424) := X"26130008";
ram_buffer(7425) := X"14E0001F";
ram_buffer(7426) := X"AC880000";
ram_buffer(7427) := X"02119021";
ram_buffer(7428) := X"32430003";
ram_buffer(7429) := X"1460005A";
ram_buffer(7430) := X"00000000";
ram_buffer(7431) := X"AE420004";
ram_buffer(7432) := X"27848060";
ram_buffer(7433) := X"10000002";
ram_buffer(7434) := X"AE110004";
ram_buffer(7435) := X"00402025";
ram_buffer(7436) := X"8C820000";
ram_buffer(7437) := X"00000000";
ram_buffer(7438) := X"0052182B";
ram_buffer(7439) := X"1460FFFB";
ram_buffer(7440) := X"00000000";
ram_buffer(7441) := X"8C830004";
ram_buffer(7442) := X"00000000";
ram_buffer(7443) := X"00833021";
ram_buffer(7444) := X"12460053";
ram_buffer(7445) := X"00000000";
ram_buffer(7446) := X"8E430004";
ram_buffer(7447) := X"00000000";
ram_buffer(7448) := X"02433021";
ram_buffer(7449) := X"10460029";
ram_buffer(7450) := X"00000000";
ram_buffer(7451) := X"AE420000";
ram_buffer(7452) := X"8E030004";
ram_buffer(7453) := X"8F868050";
ram_buffer(7454) := X"10920002";
ram_buffer(7455) := X"00000000";
ram_buffer(7456) := X"AC920000";
ram_buffer(7457) := X"8F848054";
ram_buffer(7458) := X"00A31023";
ram_buffer(7459) := X"0044202B";
ram_buffer(7460) := X"10800002";
ram_buffer(7461) := X"AF828058";
ram_buffer(7462) := X"AF828054";
ram_buffer(7463) := X"00C31825";
ram_buffer(7464) := X"AE030004";
ram_buffer(7465) := X"0C4011C5";
ram_buffer(7466) := X"AE000000";
ram_buffer(7467) := X"32620003";
ram_buffer(7468) := X"1040000E";
ram_buffer(7469) := X"3C040100";
ram_buffer(7470) := X"2405012C";
ram_buffer(7471) := X"0C40041F";
ram_buffer(7472) := X"24847C70";
ram_buffer(7473) := X"8FBF0024";
ram_buffer(7474) := X"02601025";
ram_buffer(7475) := X"8FB2001C";
ram_buffer(7476) := X"8FB30020";
ram_buffer(7477) := X"8FB10018";
ram_buffer(7478) := X"8FB00014";
ram_buffer(7479) := X"03E00008";
ram_buffer(7480) := X"27BD0028";
ram_buffer(7481) := X"0C4011C5";
ram_buffer(7482) := X"00009825";
ram_buffer(7483) := X"8FBF0024";
ram_buffer(7484) := X"02601025";
ram_buffer(7485) := X"8FB2001C";
ram_buffer(7486) := X"8FB30020";
ram_buffer(7487) := X"8FB10018";
ram_buffer(7488) := X"8FB00014";
ram_buffer(7489) := X"03E00008";
ram_buffer(7490) := X"27BD0028";
ram_buffer(7491) := X"8F86805C";
ram_buffer(7492) := X"00000000";
ram_buffer(7493) := X"1046FFD5";
ram_buffer(7494) := X"00000000";
ram_buffer(7495) := X"8C460004";
ram_buffer(7496) := X"8C420000";
ram_buffer(7497) := X"00C31821";
ram_buffer(7498) := X"AE430004";
ram_buffer(7499) := X"1000FFD0";
ram_buffer(7500) := X"AE420000";
ram_buffer(7501) := X"24827DE8";
ram_buffer(7502) := X"3407FFF8";
ram_buffer(7503) := X"00473821";
ram_buffer(7504) := X"2403FFFC";
ram_buffer(7505) := X"00E33824";
ram_buffer(7506) := X"00E21823";
ram_buffer(7507) := X"AF808064";
ram_buffer(7508) := X"AF828060";
ram_buffer(7509) := X"ACE00004";
ram_buffer(7510) := X"ACE00000";
ram_buffer(7511) := X"AC430004";
ram_buffer(7512) := X"3C028000";
ram_buffer(7513) := X"AF87805C";
ram_buffer(7514) := X"AC877DE8";
ram_buffer(7515) := X"AF838054";
ram_buffer(7516) := X"AF838058";
ram_buffer(7517) := X"AF828050";
ram_buffer(7518) := X"1000FF7E";
ram_buffer(7519) := X"3C068000";
ram_buffer(7520) := X"3C040100";
ram_buffer(7521) := X"240500EC";
ram_buffer(7522) := X"0C40041F";
ram_buffer(7523) := X"24847C70";
ram_buffer(7524) := X"8E020004";
ram_buffer(7525) := X"8F858058";
ram_buffer(7526) := X"1000FFA0";
ram_buffer(7527) := X"00511023";
ram_buffer(7528) := X"8E460004";
ram_buffer(7529) := X"00809025";
ram_buffer(7530) := X"00661821";
ram_buffer(7531) := X"1000FFAC";
ram_buffer(7532) := X"AC830004";
ram_buffer(7533) := X"10800020";
ram_buffer(7534) := X"00000000";
ram_buffer(7535) := X"8C83FFFC";
ram_buffer(7536) := X"8F828050";
ram_buffer(7537) := X"27BDFFE0";
ram_buffer(7538) := X"AFB00014";
ram_buffer(7539) := X"00808025";
ram_buffer(7540) := X"00622024";
ram_buffer(7541) := X"AFBF001C";
ram_buffer(7542) := X"10800019";
ram_buffer(7543) := X"AFB10018";
ram_buffer(7544) := X"8E04FFF8";
ram_buffer(7545) := X"00000000";
ram_buffer(7546) := X"10800024";
ram_buffer(7547) := X"00021027";
ram_buffer(7548) := X"3C110100";
ram_buffer(7549) := X"26247C70";
ram_buffer(7550) := X"0C40041F";
ram_buffer(7551) := X"24050141";
ram_buffer(7552) := X"8E03FFFC";
ram_buffer(7553) := X"8F828050";
ram_buffer(7554) := X"00000000";
ram_buffer(7555) := X"00622024";
ram_buffer(7556) := X"10800005";
ram_buffer(7557) := X"00000000";
ram_buffer(7558) := X"8E04FFF8";
ram_buffer(7559) := X"00000000";
ram_buffer(7560) := X"10800015";
ram_buffer(7561) := X"00000000";
ram_buffer(7562) := X"8FBF001C";
ram_buffer(7563) := X"8FB10018";
ram_buffer(7564) := X"8FB00014";
ram_buffer(7565) := X"27BD0020";
ram_buffer(7566) := X"03E00008";
ram_buffer(7567) := X"00000000";
ram_buffer(7568) := X"3C110100";
ram_buffer(7569) := X"24050140";
ram_buffer(7570) := X"0C40041F";
ram_buffer(7571) := X"26247C70";
ram_buffer(7572) := X"8E02FFF8";
ram_buffer(7573) := X"00000000";
ram_buffer(7574) := X"1440FFE7";
ram_buffer(7575) := X"26247C70";
ram_buffer(7576) := X"8E03FFFC";
ram_buffer(7577) := X"8F828050";
ram_buffer(7578) := X"00000000";
ram_buffer(7579) := X"00432024";
ram_buffer(7580) := X"1080FFED";
ram_buffer(7581) := X"00000000";
ram_buffer(7582) := X"00021027";
ram_buffer(7583) := X"00431024";
ram_buffer(7584) := X"0C4010EF";
ram_buffer(7585) := X"AE02FFFC";
ram_buffer(7586) := X"8E05FFFC";
ram_buffer(7587) := X"8F828058";
ram_buffer(7588) := X"2610FFF8";
ram_buffer(7589) := X"00451021";
ram_buffer(7590) := X"AF828058";
ram_buffer(7591) := X"10000002";
ram_buffer(7592) := X"27838060";
ram_buffer(7593) := X"00401825";
ram_buffer(7594) := X"8C620000";
ram_buffer(7595) := X"00000000";
ram_buffer(7596) := X"0050202B";
ram_buffer(7597) := X"1480FFFB";
ram_buffer(7598) := X"00000000";
ram_buffer(7599) := X"8C640004";
ram_buffer(7600) := X"00000000";
ram_buffer(7601) := X"00643021";
ram_buffer(7602) := X"12060017";
ram_buffer(7603) := X"00000000";
ram_buffer(7604) := X"02052021";
ram_buffer(7605) := X"1044000A";
ram_buffer(7606) := X"00000000";
ram_buffer(7607) := X"AE020000";
ram_buffer(7608) := X"10700002";
ram_buffer(7609) := X"00000000";
ram_buffer(7610) := X"AC700000";
ram_buffer(7611) := X"8FBF001C";
ram_buffer(7612) := X"8FB10018";
ram_buffer(7613) := X"8FB00014";
ram_buffer(7614) := X"084011C5";
ram_buffer(7615) := X"27BD0020";
ram_buffer(7616) := X"8F84805C";
ram_buffer(7617) := X"00000000";
ram_buffer(7618) := X"1044FFF4";
ram_buffer(7619) := X"00000000";
ram_buffer(7620) := X"8C440004";
ram_buffer(7621) := X"8C420000";
ram_buffer(7622) := X"00852821";
ram_buffer(7623) := X"AE050004";
ram_buffer(7624) := X"1000FFEF";
ram_buffer(7625) := X"AE020000";
ram_buffer(7626) := X"00A42821";
ram_buffer(7627) := X"AC650004";
ram_buffer(7628) := X"1000FFE7";
ram_buffer(7629) := X"00608025";
ram_buffer(7630) := X"8F828058";
ram_buffer(7631) := X"03E00008";
ram_buffer(7632) := X"00000000";
ram_buffer(7633) := X"8F828054";
ram_buffer(7634) := X"03E00008";
ram_buffer(7635) := X"00000000";
ram_buffer(7636) := X"03E00008";
ram_buffer(7637) := X"00000000";
ram_buffer(7638) := X"28CA0008";
ram_buffer(7639) := X"1540005B";
ram_buffer(7640) := X"00801025";
ram_buffer(7641) := X"00A4C026";
ram_buffer(7642) := X"33180003";
ram_buffer(7643) := X"17000066";
ram_buffer(7644) := X"00043823";
ram_buffer(7645) := X"30E70003";
ram_buffer(7646) := X"10E00005";
ram_buffer(7647) := X"00C73023";
ram_buffer(7648) := X"88B80000";
ram_buffer(7649) := X"00A72821";
ram_buffer(7650) := X"A8980000";
ram_buffer(7651) := X"00872021";
ram_buffer(7652) := X"30D8003F";
ram_buffer(7653) := X"10D80026";
ram_buffer(7654) := X"00D83823";
ram_buffer(7655) := X"00873821";
ram_buffer(7656) := X"8CA80000";
ram_buffer(7657) := X"8CA90004";
ram_buffer(7658) := X"8CAA0008";
ram_buffer(7659) := X"8CAB000C";
ram_buffer(7660) := X"8CAC0010";
ram_buffer(7661) := X"8CAD0014";
ram_buffer(7662) := X"8CAE0018";
ram_buffer(7663) := X"8CAF001C";
ram_buffer(7664) := X"AC880000";
ram_buffer(7665) := X"AC890004";
ram_buffer(7666) := X"AC8A0008";
ram_buffer(7667) := X"AC8B000C";
ram_buffer(7668) := X"AC8C0010";
ram_buffer(7669) := X"AC8D0014";
ram_buffer(7670) := X"AC8E0018";
ram_buffer(7671) := X"AC8F001C";
ram_buffer(7672) := X"8CA80020";
ram_buffer(7673) := X"8CA90024";
ram_buffer(7674) := X"8CAA0028";
ram_buffer(7675) := X"8CAB002C";
ram_buffer(7676) := X"8CAC0030";
ram_buffer(7677) := X"8CAD0034";
ram_buffer(7678) := X"8CAE0038";
ram_buffer(7679) := X"8CAF003C";
ram_buffer(7680) := X"AC880020";
ram_buffer(7681) := X"AC890024";
ram_buffer(7682) := X"AC8A0028";
ram_buffer(7683) := X"AC8B002C";
ram_buffer(7684) := X"AC8C0030";
ram_buffer(7685) := X"AC8D0034";
ram_buffer(7686) := X"AC8E0038";
ram_buffer(7687) := X"AC8F003C";
ram_buffer(7688) := X"24840040";
ram_buffer(7689) := X"1487FFDE";
ram_buffer(7690) := X"24A50040";
ram_buffer(7691) := X"03003025";
ram_buffer(7692) := X"30D8001F";
ram_buffer(7693) := X"10D80013";
ram_buffer(7694) := X"00000000";
ram_buffer(7695) := X"8CA80000";
ram_buffer(7696) := X"8CA90004";
ram_buffer(7697) := X"8CAA0008";
ram_buffer(7698) := X"8CAB000C";
ram_buffer(7699) := X"8CAC0010";
ram_buffer(7700) := X"8CAD0014";
ram_buffer(7701) := X"8CAE0018";
ram_buffer(7702) := X"8CAF001C";
ram_buffer(7703) := X"24A50020";
ram_buffer(7704) := X"AC880000";
ram_buffer(7705) := X"AC890004";
ram_buffer(7706) := X"AC8A0008";
ram_buffer(7707) := X"AC8B000C";
ram_buffer(7708) := X"AC8C0010";
ram_buffer(7709) := X"AC8D0014";
ram_buffer(7710) := X"AC8E0018";
ram_buffer(7711) := X"AC8F001C";
ram_buffer(7712) := X"24840020";
ram_buffer(7713) := X"33060003";
ram_buffer(7714) := X"10D80007";
ram_buffer(7715) := X"03063823";
ram_buffer(7716) := X"00873821";
ram_buffer(7717) := X"8CAB0000";
ram_buffer(7718) := X"24840004";
ram_buffer(7719) := X"24A50004";
ram_buffer(7720) := X"1487FFFC";
ram_buffer(7721) := X"AC8BFFFC";
ram_buffer(7722) := X"18C00006";
ram_buffer(7723) := X"00863821";
ram_buffer(7724) := X"80A30000";
ram_buffer(7725) := X"24840001";
ram_buffer(7726) := X"24A50001";
ram_buffer(7727) := X"1487FFFC";
ram_buffer(7728) := X"A083FFFF";
ram_buffer(7729) := X"03E00008";
ram_buffer(7730) := X"00000000";
ram_buffer(7731) := X"30D80003";
ram_buffer(7732) := X"1306FFF5";
ram_buffer(7733) := X"30990003";
ram_buffer(7734) := X"1720FFF3";
ram_buffer(7735) := X"30B90003";
ram_buffer(7736) := X"1720FFF1";
ram_buffer(7737) := X"00D83823";
ram_buffer(7738) := X"00873821";
ram_buffer(7739) := X"8CAB0000";
ram_buffer(7740) := X"24840004";
ram_buffer(7741) := X"24A50004";
ram_buffer(7742) := X"1487FFFC";
ram_buffer(7743) := X"AC8BFFFC";
ram_buffer(7744) := X"1000FFE9";
ram_buffer(7745) := X"03003025";
ram_buffer(7746) := X"30E70003";
ram_buffer(7747) := X"10E00006";
ram_buffer(7748) := X"00C73023";
ram_buffer(7749) := X"88A30000";
ram_buffer(7750) := X"98A30003";
ram_buffer(7751) := X"00A72821";
ram_buffer(7752) := X"A8830000";
ram_buffer(7753) := X"00872021";
ram_buffer(7754) := X"30D8003F";
ram_buffer(7755) := X"10D80036";
ram_buffer(7756) := X"00D83823";
ram_buffer(7757) := X"00873821";
ram_buffer(7758) := X"88A80000";
ram_buffer(7759) := X"88A90004";
ram_buffer(7760) := X"88AA0008";
ram_buffer(7761) := X"88AB000C";
ram_buffer(7762) := X"88AC0010";
ram_buffer(7763) := X"88AD0014";
ram_buffer(7764) := X"88AE0018";
ram_buffer(7765) := X"88AF001C";
ram_buffer(7766) := X"98A80003";
ram_buffer(7767) := X"98A90007";
ram_buffer(7768) := X"98AA000B";
ram_buffer(7769) := X"98AB000F";
ram_buffer(7770) := X"98AC0013";
ram_buffer(7771) := X"98AD0017";
ram_buffer(7772) := X"98AE001B";
ram_buffer(7773) := X"98AF001F";
ram_buffer(7774) := X"AC880000";
ram_buffer(7775) := X"AC890004";
ram_buffer(7776) := X"AC8A0008";
ram_buffer(7777) := X"AC8B000C";
ram_buffer(7778) := X"AC8C0010";
ram_buffer(7779) := X"AC8D0014";
ram_buffer(7780) := X"AC8E0018";
ram_buffer(7781) := X"AC8F001C";
ram_buffer(7782) := X"88A80020";
ram_buffer(7783) := X"88A90024";
ram_buffer(7784) := X"88AA0028";
ram_buffer(7785) := X"88AB002C";
ram_buffer(7786) := X"88AC0030";
ram_buffer(7787) := X"88AD0034";
ram_buffer(7788) := X"88AE0038";
ram_buffer(7789) := X"88AF003C";
ram_buffer(7790) := X"98A80023";
ram_buffer(7791) := X"98A90027";
ram_buffer(7792) := X"98AA002B";
ram_buffer(7793) := X"98AB002F";
ram_buffer(7794) := X"98AC0033";
ram_buffer(7795) := X"98AD0037";
ram_buffer(7796) := X"98AE003B";
ram_buffer(7797) := X"98AF003F";
ram_buffer(7798) := X"AC880020";
ram_buffer(7799) := X"AC890024";
ram_buffer(7800) := X"AC8A0028";
ram_buffer(7801) := X"AC8B002C";
ram_buffer(7802) := X"AC8C0030";
ram_buffer(7803) := X"AC8D0034";
ram_buffer(7804) := X"AC8E0038";
ram_buffer(7805) := X"AC8F003C";
ram_buffer(7806) := X"24840040";
ram_buffer(7807) := X"1487FFCE";
ram_buffer(7808) := X"24A50040";
ram_buffer(7809) := X"03003025";
ram_buffer(7810) := X"30D8001F";
ram_buffer(7811) := X"10D8001B";
ram_buffer(7812) := X"00000000";
ram_buffer(7813) := X"88A80000";
ram_buffer(7814) := X"88A90004";
ram_buffer(7815) := X"88AA0008";
ram_buffer(7816) := X"88AB000C";
ram_buffer(7817) := X"88AC0010";
ram_buffer(7818) := X"88AD0014";
ram_buffer(7819) := X"88AE0018";
ram_buffer(7820) := X"88AF001C";
ram_buffer(7821) := X"98A80003";
ram_buffer(7822) := X"98A90007";
ram_buffer(7823) := X"98AA000B";
ram_buffer(7824) := X"98AB000F";
ram_buffer(7825) := X"98AC0013";
ram_buffer(7826) := X"98AD0017";
ram_buffer(7827) := X"98AE001B";
ram_buffer(7828) := X"98AF001F";
ram_buffer(7829) := X"24A50020";
ram_buffer(7830) := X"AC880000";
ram_buffer(7831) := X"AC890004";
ram_buffer(7832) := X"AC8A0008";
ram_buffer(7833) := X"AC8B000C";
ram_buffer(7834) := X"AC8C0010";
ram_buffer(7835) := X"AC8D0014";
ram_buffer(7836) := X"AC8E0018";
ram_buffer(7837) := X"AC8F001C";
ram_buffer(7838) := X"24840020";
ram_buffer(7839) := X"33060003";
ram_buffer(7840) := X"10D80008";
ram_buffer(7841) := X"03063823";
ram_buffer(7842) := X"00873821";
ram_buffer(7843) := X"88A30000";
ram_buffer(7844) := X"98A30003";
ram_buffer(7845) := X"24840004";
ram_buffer(7846) := X"24A50004";
ram_buffer(7847) := X"1487FFFB";
ram_buffer(7848) := X"AC83FFFC";
ram_buffer(7849) := X"10C0FF87";
ram_buffer(7850) := X"00863821";
ram_buffer(7851) := X"80A30000";
ram_buffer(7852) := X"24840001";
ram_buffer(7853) := X"24A50001";
ram_buffer(7854) := X"1487FFFC";
ram_buffer(7855) := X"A083FFFF";
ram_buffer(7856) := X"03E00008";
ram_buffer(7857) := X"00000000";
ram_buffer(7858) := X"28CA0008";
ram_buffer(7859) := X"1540003E";
ram_buffer(7860) := X"00801025";
ram_buffer(7861) := X"10A00007";
ram_buffer(7862) := X"00043823";
ram_buffer(7863) := X"00000000";
ram_buffer(7864) := X"30A500FF";
ram_buffer(7865) := X"00055200";
ram_buffer(7866) := X"00AA2825";
ram_buffer(7867) := X"00055400";
ram_buffer(7868) := X"00AA2825";
ram_buffer(7869) := X"30EA0003";
ram_buffer(7870) := X"11400003";
ram_buffer(7871) := X"00CA3023";
ram_buffer(7872) := X"A8850000";
ram_buffer(7873) := X"008A2021";
ram_buffer(7874) := X"30EA0004";
ram_buffer(7875) := X"11400003";
ram_buffer(7876) := X"00CA3023";
ram_buffer(7877) := X"AC850000";
ram_buffer(7878) := X"008A2021";
ram_buffer(7879) := X"30D8003F";
ram_buffer(7880) := X"10D80016";
ram_buffer(7881) := X"00D83823";
ram_buffer(7882) := X"00873821";
ram_buffer(7883) := X"AC850000";
ram_buffer(7884) := X"AC850004";
ram_buffer(7885) := X"AC850008";
ram_buffer(7886) := X"AC85000C";
ram_buffer(7887) := X"AC850010";
ram_buffer(7888) := X"AC850014";
ram_buffer(7889) := X"AC850018";
ram_buffer(7890) := X"AC85001C";
ram_buffer(7891) := X"AC850020";
ram_buffer(7892) := X"AC850024";
ram_buffer(7893) := X"AC850028";
ram_buffer(7894) := X"AC85002C";
ram_buffer(7895) := X"AC850030";
ram_buffer(7896) := X"AC850034";
ram_buffer(7897) := X"AC850038";
ram_buffer(7898) := X"AC85003C";
ram_buffer(7899) := X"24840040";
ram_buffer(7900) := X"1487FFEE";
ram_buffer(7901) := X"00000000";
ram_buffer(7902) := X"03003025";
ram_buffer(7903) := X"30D8001F";
ram_buffer(7904) := X"10D8000A";
ram_buffer(7905) := X"00000000";
ram_buffer(7906) := X"AC850000";
ram_buffer(7907) := X"AC850004";
ram_buffer(7908) := X"AC850008";
ram_buffer(7909) := X"AC85000C";
ram_buffer(7910) := X"AC850010";
ram_buffer(7911) := X"AC850014";
ram_buffer(7912) := X"AC850018";
ram_buffer(7913) := X"AC85001C";
ram_buffer(7914) := X"24840020";
ram_buffer(7915) := X"33060003";
ram_buffer(7916) := X"10D80005";
ram_buffer(7917) := X"03063823";
ram_buffer(7918) := X"00873821";
ram_buffer(7919) := X"24840004";
ram_buffer(7920) := X"1487FFFE";
ram_buffer(7921) := X"AC85FFFC";
ram_buffer(7922) := X"18C00004";
ram_buffer(7923) := X"00863821";
ram_buffer(7924) := X"24840001";
ram_buffer(7925) := X"1487FFFE";
ram_buffer(7926) := X"A085FFFF";
ram_buffer(7927) := X"03E00008";
ram_buffer(7928) := X"00000000";
ram_buffer(7929) := X"24820001";
ram_buffer(7930) := X"90830000";
ram_buffer(7931) := X"00000000";
ram_buffer(7932) := X"1460FFFD";
ram_buffer(7933) := X"24840001";
ram_buffer(7934) := X"03E00008";
ram_buffer(7935) := X"00821023";
ram_buffer(7936) := X"6D61696E";
ram_buffer(7937) := X"00000000";
ram_buffer(7938) := X"696E7075";
ram_buffer(7939) := X"74000000";
ram_buffer(7940) := X"74696D65";
ram_buffer(7941) := X"00000000";
ram_buffer(7942) := X"636F7079";
ram_buffer(7943) := X"00000000";
ram_buffer(7944) := X"2E2E2F2E";
ram_buffer(7945) := X"2E2F6672";
ram_buffer(7946) := X"65657274";
ram_buffer(7947) := X"6F732F71";
ram_buffer(7948) := X"75657565";
ram_buffer(7949) := X"2E630000";
ram_buffer(7950) := X"2E2E2F2E";
ram_buffer(7951) := X"2E2F6672";
ram_buffer(7952) := X"65657274";
ram_buffer(7953) := X"6F732F74";
ram_buffer(7954) := X"61736B73";
ram_buffer(7955) := X"2E630000";
ram_buffer(7956) := X"49444C45";
ram_buffer(7957) := X"00000000";
ram_buffer(7958) := X"2E2E2F2E";
ram_buffer(7959) := X"2E2F6672";
ram_buffer(7960) := X"65657274";
ram_buffer(7961) := X"6F732F70";
ram_buffer(7962) := X"6F72742E";
ram_buffer(7963) := X"63000000";
ram_buffer(7964) := X"2E2E2F2E";
ram_buffer(7965) := X"2E2F6672";
ram_buffer(7966) := X"65657274";
ram_buffer(7967) := X"6F732F68";
ram_buffer(7968) := X"6561705F";
ram_buffer(7969) := X"342E6300";
ram_buffer(7970) := X"00000100";
ram_buffer(7971) := X"01010001";
ram_buffer(7972) := X"00000000";
ram_buffer(7973) := X"00000000";
ram_buffer(7974) := X"00000000";
ram_buffer(7975) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
a6880bacb82dc3cbbf0ca4aa62702a12
| 0.627239 | 2.396648 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/cross_clk_sync_fifo_0.vhd
| 2 | 85,574 |
-------------------------------------------------------------------------------
-- cross_clk_sync_fifo_0.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cross_clk_sync_fifo_0.vhd
-- Version: v3.1
-- Description: This is the CDC logic when FIFO = 0.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_0 is
generic (
C_NUM_TRANSFER_BITS : integer;
Async_Clk : integer;
C_NUM_SS_BITS : integer--;
--C_AXI_SPI_CLK_EQ_DIFF : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
tx_empty_signal_handshake_req : in std_logic;
tx_empty_signal_handshake_gnt : out std_logic;
Tx_FIFO_Empty_cdc_from_axi : in std_logic;
Tx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_d1_reg_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spisel_pulse_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_pulse_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spiXfer_done_cdc_from_spi : in std_logic; -- = spiXfer_done_cdc_from_spi_clk, -- in
spiXfer_done_cdc_to_axi : out std_logic; -- = spiXfer_done_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
modf_strobe_cdc_from_spi : in std_logic; -- = modf_strobe_cdc_from_spi_clk, -- in
modf_strobe_cdc_to_axi : out std_logic; -- = modf_strobe_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
Slave_MODF_strobe_cdc_from_spi : in std_logic; -- = slave_MODF_strobe_cdc_from_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi : out std_logic; -- = slave_MODF_strobe_cdc_to_axi_clk ,-- out
--------------------------:-------------------------------
receive_Data_cdc_from_spi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_Data_cdc_from_spi_clk, -- in
receive_Data_cdc_to_axi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_data_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic;
--------------------------:-------------------------------
dtr_underrun_cdc_from_spi : in std_logic; -- = dtr_underrun_cdc_from_spi_clk, -- in
dtr_underrun_cdc_to_axi : out std_logic; -- = dtr_underrun_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
transmit_Data_cdc_from_axi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_from_axi_clk, -- in
transmit_Data_cdc_to_spi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_to_spi_clk -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1))
----------------------------
);
end entity cross_clk_sync_fifo_0;
architecture imp of cross_clk_sync_fifo_0 is
--------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d4 : std_logic;
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_to_spi_i : std_logic;
-- signal declaration
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
-- signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d3 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d4 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of SPISEL_D1_REG_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1 : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
-- SPI_AXI_EQUAL_GEN: AXI and SPI domain clocks are same
---------------------
--SPI_AXI_EQUAL_GEN: if C_AXI_SPI_CLK_EQ_DIFF = 0 generate
-----
--begin
-----
LOGIC_GENERATION_FDR : if (Async_Clk =0) generate
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI: process(Bus2IP_Clk) is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1')then
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= '1';
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= '1';
else
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d1;
end if;
end if;
end process TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI;
-----------------------------------------
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
-------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_3: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
-------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_SYNC_SPI_2_AXI_2: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_SPI_2_AXI_1: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_2: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_3: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
---------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
---------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
---------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P: process(Bus2IP_Clk) is
-------------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
receive_Data_cdc_from_spi_d1 <= receive_Data_cdc_from_spi;
receive_Data_cdc_from_spi_d2 <= receive_Data_cdc_from_spi_d1;
end if;
end process RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P;
-------------------------------------------
receive_Data_cdc_to_axi <= receive_Data_cdc_from_spi_d2;
-----------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-----------------------------------------------
TR_DATA_SYNC_AX2SP_GEN: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TR_DATA_SYNC_AX2SP_1: label is "TRUE";
-----
begin
-----
TR_DATA_SYNC_AX2SP_1: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TR_DATA_SYNC_AX2SP_2: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TR_DATA_SYNC_AX2SP_GEN;
transmit_Data_cdc_to_spi <= transmit_Data_cdc_from_axi_d2;
-----------------------------------------------
SPICR_0_LOOP_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1 : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1 : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
end generate LOGIC_GENERATION_FDR ;
--============================================================================================================
LOGIC_GENERATION_CDC : if (Async_Clk =1) generate
--============================================================================================================
-- Tx_FIFO_Empty_cdc_from_axi <= Tx_FIFO_Empty_cdc_from_axi;
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_cdc_to_spi;
-- Tx_FIFO_Empty_SPISR_cdc_from_spi <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
-- Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_cdc_to_axi;
-- spisel_d1_reg_cdc_from_spi <= spisel_d1_reg_cdc_from_spi;
-- spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_cdc_to_axi;
-- spisel_pulse_cdc_from_spi <= spisel_pulse_cdc_from_spi;
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_cdc_to_axi;
-- spiXfer_done_cdc_from_spi <= spiXfer_done_cdc_from_spi;
-- spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_cdc_to_axi;
-- modf_strobe_cdc_from_spi <= modf_strobe_cdc_from_spi;
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_cdc_to_axi;
-- Slave_MODF_strobe_cdc_from_spi <= Slave_MODF_strobe_cdc_from_spi;
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_cdc_to_axi;
-- receive_Data_cdc_from_spi <= receive_Data_cdc_from_spi;
-- receive_Data_cdc_to_axi <= receive_Data_cdc_cdc_to_axi;
-- drr_Overrun_int_cdc_from_spi <= drr_Overrun_int_cdc_from_spi;
-- drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_cdc_to_axi;
-- dtr_underrun_cdc_from_spi <= dtr_underrun_cdc_from_spi;
-- dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_cdc_to_axi;
-- transmit_Data_cdc_from_axi <= transmit_Data_cdc_from_axi;
-- transmit_Data_cdc_to_spi <= transmit_Data_cdc_cdc_to_spi;
-- SPICR_0_LOOP_cdc_from_axi <= SPICR_0_LOOP_cdc_from_axi;
-- SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_cdc_to_spi;
-- SPICR_1_SPE_cdc_from_axi <= SPICR_1_SPE_cdc_from_axi;
-- SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_cdc_to_spi;
-- SPICR_2_MST_N_SLV_cdc_from_axi <= SPICR_2_MST_N_SLV_cdc_from_axi;
-- SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_cdc_to_spi;
-- SPICR_3_CPOL_cdc_from_axi <= SPICR_3_CPOL_cdc_from_axi;
-- SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_cdc_to_spi;
-- SPICR_4_CPHA_cdc_from_axi <= SPICR_4_CPHA_cdc_from_axi;
-- SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_cdc_to_spi;
-- SPICR_5_TXFIFO_cdc_from_axi <= SPICR_5_TXFIFO_cdc_from_axi;
-- SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_cdc_to_spi;
-- SPICR_6_RXFIFO_RST_cdc_from_axi <= SPICR_6_RXFIFO_RST_cdc_from_axi;
-- SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_cdc_to_spi;
-- SPICR_7_SS_cdc_from_axi <= SPICR_7_SS_cdc_from_axi;
-- SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_cdc_to_spi;
-- SPICR_8_TR_INHIBIT_cdc_from_axi <= SPICR_8_TR_INHIBIT_cdc_from_axi;
-- SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_cdc_to_spi;
-- SPICR_9_LSB_cdc_from_axi <= SPICR_9_LSB_cdc_from_axi;
-- SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_cdc_to_spi;
-- SPICR_bits_7_8_cdc_from_axi <= SPICR_bits_7_8_cdc_from_axi;
-- SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_cdc_to_spi;
-- SR_3_modf_cdc_from_axi <= SR_3_modf_cdc_from_axi;
-- SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_cdc_to_spi;
-- SPISSR_cdc_from_axi <= SPISSR_cdc_from_axi;
-- SPISSR_cdc_to_spi <= SPISSR_cdc_cdc_to_spi;
--============================================================================================================
-- all the signals pass through FF with reset before CDC_SYNC module to initialise the value of the signal
-- at its reset state. As many signals coming from bram have initial value of XX.
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0') ,
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
--------------------------------------------------------------------------------------------------------------
---- -- TX_FIFO_EMPTY_STRETCH_1: process(Bus2IP_Clk)is
---- -- begin
---- -- if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
---- -- if(Soft_Reset_op = '1') then
---- -- Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
---- -- else
---- -- Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
---- -- Tx_FIFO_Empty_cdc_from_axi_int_2;
---- -- end if;
---- -- end if;
---- -- end process TX_FIFO_EMPTY_STRETCH_1;
----
---- TX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
---- generic map (
---- C_CDC_TYPE => 1, -- 2 is ack based level sync
---- C_RESET_STATE => 0 , -- no reset to be used in synchronisers
---- C_SINGLE_BIT => 1 ,
---- C_FLOP_INPUT => 0 ,
---- C_VECTOR_WIDTH => 1 ,
---- C_MTBF_STAGES => MTBF_STAGES_AXI2S
---- )
----
---- port map (
---- prmry_aclk => Bus2IP_Clk ,
---- prmry_resetn => Soft_Reset_op ,
---- prmry_in => Tx_FIFO_Empty_cdc_from_axi,--Tx_FIFO_Empty_cdc_from_axi_int_2,--Tx_FIFO_Empty_cdc_from_axi_d1 ,
---- scndry_aclk => EXT_SPI_CLK ,
---- prmry_vect_in => (others => '0' ),
---- scndry_resetn => Rst_from_axi_cdc_to_spi ,
---- scndry_out => Tx_FIFO_Empty_cdc_from_axi_d2 --Tx_FIFO_Empty_cdc_from_axi_d2--Tx_FIFO_Empty_cdc_to_spi
---- --scndry_out => Tx_FIFO_Empty_cdc_to_spi --Tx_FIFO_Empty_cdc_from_axi_d2--Tx_FIFO_Empty_cdc_to_spi
---- );
----
------ TX_FIFO_EMPTY_STRETCH_1_CDC: process(EXT_SPI_CLK)is
------ begin
------ if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
------
------ Tx_FIFO_Empty_cdc_from_axi_d3 <= Tx_FIFO_Empty_cdc_from_axi_d2;
------
------ end if;
------ end process TX_FIFO_EMPTY_STRETCH_1_CDC;
------ Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
----
---- TX_FIFO_EMPTY_STRETCH_1_CDC: process(EXT_SPI_CLK)is
---- begin
---- if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
----
---- Tx_FIFO_Empty_cdc_from_axi_d3 <= Tx_FIFO_Empty_cdc_from_axi_d2;
----
---- end if;
---- end process TX_FIFO_EMPTY_STRETCH_1_CDC;
---- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 or Tx_FIFO_Empty_cdc_from_axi_d3;
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_to_spi_i;
TX_FIFO_EMPTY_HANDSHAKE_REQ_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => tx_empty_signal_handshake_req,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => Tx_FIFO_Empty_cdc_to_spi_i
);
TX_FIFO_EMPTY_HANDSHAKE_GNT_SPI_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_to_spi_i,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => tx_empty_signal_handshake_gnt
);
----------------------------------------------------------------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
-----------------------------------------------------------------------------------------------------------
SPISEL_PULSE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
--spisel_pulse_cdc_from_spi_d1 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
--spisel_pulse_cdc_from_spi_d1 <= spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1_CDC;
SPISEL_PULSE_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_pulse_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_pulse_cdc_from_spi_d2
);
SPISEL_PULSE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
spisel_pulse_cdc_from_spi_d3 <= spisel_pulse_cdc_from_spi_d2;
end if;
end process SPISEL_PULSE_STRETCH_1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
--------------------------------------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d2 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 ,-- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2--spiXfer_done_cdc_to_axi
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3;
--------------------------------------------------------------------------------------------------------------
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
--modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2--modf_strobe_cdc_to_axi
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2 ;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3;
----------------------------------------------------------------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
-- Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
-- Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3;
-----------------------------------------------------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => receive_Data_cdc_from_spi,
scndry_aclk => Bus2IP_Clk,
prmry_in => '0',
scndry_resetn => Soft_Reset_op,
scndry_vect_out => receive_Data_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_4: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d3,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d4 xor drr_Overrun_int_cdc_from_spi_d3;
-------------------------------------------------------------------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
------------------------------------------------------------------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
----------------------------------------------------------------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
TR_DATA_SYNC_AX2SP_GEN_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => transmit_Data_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => transmit_Data_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SR_3_MODF_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
SPISSR_SYNC_GEN_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_SS_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => SPISSR_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => SPISSR_cdc_to_spi
);
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
SPICR_BITS_7_8_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
-----------------------------------------
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
|
bsd-3-clause
|
d70febd1973c1e09233dfa6c85cd0e10
| 0.430364 | 3.705946 | false | false | false | false |
makestuff/vga_test
|
vhdl/clk_gen/ep2c5/clk_gen_16MHz.vhdl
| 1 | 15,273 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_gen.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_gen IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END clk_gen;
ARCHITECTURE SYN OF clk_gen IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 16,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 62500,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=clk_gen",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "16.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "62500"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
17fb7bcc35dd93575d158b8b8427edb5
| 0.699928 | 3.357441 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/alu_defs.vhdl
| 1 | 1,786 |
-- Don't use this.
-- GHDL doesn't put signals of enumerated type into the .vcd signal trace
-- So we'd have to settle for constants when we want to display them.
-- If you find yourself in that position, comment out alu_op_t in arch_defs.vhdl
-- and use this one here instead.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package alu_defs is
subtype alu_op_t is std_logic_vector(4 downto 0);
constant ALU_ADD : alu_op_t := B"0_0000";
constant ALU_ADDU : alu_op_t := B"0_0001";
constant ALU_SUB : alu_op_t := B"0_0010";
constant ALU_SUBU : alu_op_t := B"0_0011";
constant ALU_AND : alu_op_t := B"0_0100";
constant ALU_OR : alu_op_t := B"0_0101";
constant ALU_NOR : alu_op_t := B"0_0110";
constant ALU_XOR : alu_op_t := B"0_0111";
constant ALU_LU : alu_op_t := B"0_1000";
constant ALU_SLL : alu_op_t := B"0_1001";
constant ALU_SRL : alu_op_t := B"0_1010";
constant ALU_SRA : alu_op_t := B"0_1011";
constant ALU_MULT : alu_op_t := B"0_1100";
constant ALU_MULTU : alu_op_t := B"0_1101";
constant ALU_DIV : alu_op_t := B"0_1110";
constant ALU_DIVU : alu_op_t := B"0_1111";
constant ALU_MFHI : alu_op_t := B"1_0000";
constant ALU_MFLO : alu_op_t := B"1_0001";
constant ALU_MTHI : alu_op_t := B"1_0010";
constant ALU_MTLO : alu_op_t := B"1_0011";
constant ALU_SLT : alu_op_t := B"1_0100";
constant ALU_SLTU : alu_op_t := B"1_0101";
constant ALU_EQ : alu_op_t := B"1_0110";
constant ALU_NE : alu_op_t := B"1_0111";
constant ALU_LEZ : alu_op_t := B"1_1000";
constant ALU_LTZ : alu_op_t := B"1_1001";
constant ALU_GTZ : alu_op_t := B"1_1010";
constant ALU_GEZ : alu_op_t := B"1_1011";
end package;
|
gpl-3.0
|
6a70ca55f63f84eff4c97fe6d2d77425
| 0.591265 | 2.710167 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/xip_status_reg.vhd
| 2 | 11,243 |
-------------------------------------------------------------------------------
-- SPI Status Register Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2011] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_status_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus. The file defines the logic for
-- status register in XIP mode.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-- C_S_AXI_DATA_WIDTH -- Native data bus width 32 bits only
-- C_NUM_SS_BITS -- Number of bits in slave select
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- STATUS REGISTER RELATED SIGNALS
--================================
-- REGISTER/FIFO INTERFACE
-- Bus2IP_SPISR_RdCE -- Status register Read Chip Enable
-- IP2Bus_SPISR_Data -- Status register data to PLB based on PLB read
-- SR_3_modf -- Mode fault error status flag
-- SR_4_Tx_Full -- Transmit register full status flag
-- SR_5_Tx_Empty -- Transmit register empty status flag
-- SR_6_Rx_Full -- Receive register full status flag
-- SR_7_Rx_Empty -- Receive register empty stauts flag
-- ModeFault_Strobe -- Mode fault strobe
-- SLAVE REGISTER RELATED SIGNALS
--===============================
-- Bus2IP_SPISSR_WrCE -- slave select register write chip enable
-- Bus2IP_SPISSR_RdCE -- slave select register read chip enable
-- Bus2IP_SPISSR_Data -- slave register data from PLB Bus
-- IP2Bus_SPISSR_Data -- Data from slave select register during PLB rd
-- SPISSR_Data_reg_op -- Data to SPI Module
-- Wr_ce_reduce_ack_gen -- commaon write ack generation signal
-- Rd_ce_reduce_ack_gen -- commaon read ack generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_status_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
------------------------
C_XIP_SPISR_REG_WIDTH : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------------
XIPSR_AXI_TR_ERR : in std_logic; -- bit 4 of XIPSR
XIPSR_CPHA_CPOL_ERR : in std_logic; -- bit 3 of XIPSR
XIPSR_MST_MODF_ERR : in std_logic; -- bit 2 of XIPSR
XIPSR_AXI_RX_FULL : in std_logic; -- bit 1 of XIPSR
XIPSR_AXI_RX_EMPTY : in std_logic; -- bit 0 of XIPSR
--------------------------
Bus2IP_XIPSR_WrCE : in std_logic;
Bus2IP_XIPSR_RdCE : in std_logic;
--------------------------
--IP2Bus_XIPSR_RdAck : out std_logic;
--IP2Bus_XIPSR_WrAck : out std_logic;
IP2Bus_XIPSR_Data : out std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
ip2Bus_RdAck : in std_logic
);
end xip_status_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of xip_status_reg is
----------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPSR_data_int : std_logic_vector(C_XIP_SPISR_REG_WIDTH-1 downto 0);
--signal ip2Bus_RdAck_core_reg : std_logic;
--signal ip2Bus_RdAck_core_reg_d1 : std_logic;
--signal ip2Bus_WrAck_core_reg : std_logic;
--signal ip2Bus_WrAck_core_reg_d1 : std_logic;
----------------------
begin
-----
-- XIPSR - 31 -- -- 5 4 3 2 1 0
-- <-- NA --> AXI CPOL_CPHA MODF Rx Rx
-- Transaction Error Error Error Full Empty
-- Default 0 0 0 0 0
-------------------------------------------------------------------------------
--XIPSR_CMD_ERR <= '0';
---------------------------------------
XIPSR_DATA_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
elsif(ip2Bus_RdAck = '1') then
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)<= (others => '0');
else
XIPSR_data_int((C_XIP_SPISR_REG_WIDTH-1) downto 0)
<= XIPSR_AXI_TR_ERR & -- bit 4
XIPSR_CPHA_CPOL_ERR &
XIPSR_MST_MODF_ERR &
XIPSR_AXI_RX_FULL &
XIPSR_AXI_RX_EMPTY ; -- bit 0
end if;
end if;
end process XIPSR_DATA_STORE_P;
--------------------------------------------------
XIPSR_REG_RD_GENERATE: for i in C_XIP_SPISR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPSR_Data(i) <= XIPSR_data_int(i) and Bus2IP_XIPSR_RdCE ; --and ip2Bus_RdAck_core_reg;
end generate XIPSR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
950a09c1695b20b0b798e4e51897e6c2
| 0.434315 | 4.909607 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_addr_cntl.vhd
| 4 | 41,582 |
----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
Use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
|
bsd-3-clause
|
22bfe49773b5cd5c66d24bca966af752
| 0.394498 | 4.970356 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
| 1 | 96,728 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
NwREbpoByAoA98RO0Xo5XQHSvmfc2x7Aw9t2ia9JNPUeRzJpiOUYYfKTpspBAw/hIvkRf/5ZLbe3
iCdefxqDug==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NnEHrtF9kTHW4PRxYeyQDMWdgL15s3/FFgbvkQk+/17p056vLtDkpl8bsVx5L+zdU96dxX1r5yTJ
wDVxnylDUX8D6/v6ag2xUeExXI+8gSTcSQo2U57VZM0T2FVonW/EJBm0HCu/Jshb4nhDcrLLuMBQ
unwWwozUXDkw8MakpV4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oBhuJ+nqLChcD3yuBkoIoTIy+Q5vkW7lL96BsvUMIWUWKIvbg4hMq4iPYZcM0162dD+Ylt1wSvWp
iX9kygbzVwM2jtPN5+44cFSpLz33tEssIllWQlPxSfqzkFcgWSiJEK7pkao/aXsrjnHdk3G53gZZ
YPxPp5psAESNJIkM3+V8eFXtjM/F4BpVTpyfyjKkxhU0rECCXu//eg/ZrGTC6a2Naq2UuvRW6JQ5
sjw50N9FMPfq1HNY0w2uVEV0ieGelZ0Po1p9iVPkaeoM4/m35qRJatzxkmEfUn8AUlEiDj9HP5iY
RMG0+HFkyj/hejHQ782JcIlk7Lv3KQEj4Yt08g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qHYu5l1IXfjjSDCXG+Tmr0jXvp/cg7vpyDyHUCKxvmB1apZcZo9Uk8tmBcgtS9vGSL81S93aiyLG
g/QCKPdXoZfM8KmAIcsnMuAEWtJ6a9/nQbrbiOKX5UXlm6RWmMRGbr9UTv0YHp3/uSRkZLb4rBBo
TWPqYGn7Bv7YT2rrMA4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
i47HGB+86buEfmt3w4kcTiNxkOqzl05nVPCi+IBbrpCTWxeS716xvQiRwgQUk+JGmlPrag65i++Z
I150Iuj2cjpwfXHrMgszfpSi9P0tYf5Ys/npwnQ2ZrXPGP//yUZVtlTONkHnRIWkQsPSYWWF1vOQ
T79sJ4pC3rxjkMC+SnHdC+dtIjUJ2sRf/bFK1nhYNT5nrar0AC5lIBU4dGI20QABjWPf5NdA2FWu
6a1gnMakcDoNPj71CcF3N97zoc1Jk10lCE3xyHyVq7jlBwBAAKzyjGKIgBqXXL9XRNnLtbbp+yS3
0IfmHY+yBDEzy15YJ3/dlxZCCHJ+8BjqaeGV/Q==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ie14k6kA9XHOrQJAX0a4M6DCQ1E1XJntZUT0CI72PUZIWOxOXE9ZpANYSXpWObCrcFodNWCSYwux
VfOK9hL8zATqtLayZwapqymBAYz8/R3QLegtwDwoMHjbeEhxRbePeoMizpZ3Y6AuFszbwbd7Mumv
wZtnrt0Yuz6tW6kOzoaY5AZn9guP009pUk9+j6f7OWmiQ1h70UVV7GrLTMkGK6285bakUiyEp5es
KfBVON7h5CtLLq/F1qnYhFfKjx84H7JvlXtgjZ60EYltZ0L58K1FX+7yOEinydhfsk3xQPjoL08b
Tja+f3wZz1MSWTyfi/ERf/JpYV70CYcykMyolg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 69472)
`protect data_block
zPi2en3afJbtvTfPPJPFhKxbSDtDu2SHJW2jcEo4vvAkEPGZJeEoHynrOZhAAa9I9zuRzRrcCaGX
3yqqUSTjudxs7H9Y2+qUFJhfGA/xqwlYry43QF3qQT4ufMpUA+eh/v8niC/4u6hxx6071YVK9y4B
uj3j6fxzVTHICjuZAsE7JQuusouUMcZnzWyhlbeK8wxB6JgnrYtiYOqwRaBGE4Wba7KXSdlvR+ee
9KF/TBe7hxURFLvKjNPxCPx6pD4x1NMutFcT6mQal+Dj3jtLRhTihC8LPCLZHe6dpuJO/FJxwgWY
89Xy569NUQ7uwexz1q43qEUqZtouFFsb95DysK2M9LLctd0cb8omBCTP/hfXwr6wHXHCT1Apmimt
lxIy6GkO5jqGfcGaNCT1w1vg490CewINOeiEQL+qewWHi47tYxJJbiIkA2hriBKW4QCDRDm+1U58
XlNJLnRyuHrjDYMlFUOZ0B3z9wYpZaqPOwb7aELfgrS5V2pZjVw+5jCTIkj9bKu+cC7BPbL0dpyO
t1k7ag3oEK62UBjtIiAzei3BPFoPi1XMz7EiHUGl/IVS8VJcOnqGVruE9b9m1bsLmWoPN12NWkX2
1dR3nCFbuMcP2L2AOizTaE8gigzsc+l0xGTcm1jqgkZ7vPsd5KS/kwNYeQBdXJFwshZQhsGzHMsh
NIpDrXdRcyKExiELkB4g/Qm8SgNNsOm0VKGU70DBiqBNTtxr7iVyC5+tp/yB4yXzUkJLy8kM3f/o
rqSRkK0v/l3V+wDRZIebANPlywh0ec7PNme4c5sSzCWdcHA5Btau129H2aSMS5VM7e+GVl7325Di
SmwuFBQvKuywatJpPG6Pi9q+Wckpda/G+CpAV+6QkSVHoqnGXjmtJshZttg2OIJIKXECXoEED1C/
deN5j+Ca9ve3xRyopQHAoa0aWZfrAed1KOOItLb4c4gmlGDYTVhPLvnNt+peME2JAd9nluxst3d+
LkAzs8vD2RZVY6uc2H88RHpboqiDulpTljSefB79N0cTHPLNM+bJib5wZobsXtmiDzs2F2JcN6R7
Gy4tHpFfEs68mxpAaprwT/lzLs/qDGYXlyk8jKNarI2QAYAb+QUWVTxClMrAfgWQUWYPsPIgTcRB
BLP428hf/hE/iVeedCV1XWuRgImcx0E8//3dLModfQxlckZZUj8rDiR7mRH4JC0cdayGE+CeLIvQ
NSgsvaYX4m/t9g+9Geqnawa4roIbRCHZGTvl9TEr9H53vAr8eXBljiC0teW6cH6NIr8H9LtCkRBI
sUY6JmMRTuNuu5a1kG1z6LXH8T0On3wTswNYDcydRE5nIFYVcV1y0HKeja8gAq3QhAdgt8V7gES+
GiyZRozQJadD4b1woWUBtykBFraVaYkZzOK7EMSAZM1r/qc3Lx4YzxXM8W21ilG7CO9xD3KruRoO
J5mFb3V9r89mDPHmcxS12n9ChjQLEbu+jSVtw+ahSWQ06tWWXo4ipSVGWoUr5xmwR88AGEpEId12
rErM23Cw2RNEladbuWkGG1eA0yjh0pzmqqPrO9LzdHZwn/Enl632H8ZTzCV/LxagyxD0TduGC5eA
81y2QLIUhdN41SBzFV3Etzdpdks6+YrPQIVUB94RPfmtJud86JaQM5sHcmMZWDHHl7SGFUkoj96E
iGc0VInAjIE8pSpFt8zEsd9INv+8joYn+zH/spqKNno4o5rOe/lIbwwErAChKuIQkxyS8OB63XCR
2ILcrc+zrBU8U0mBcYJXD37Kk0LfZNFVwrZOf4teFKhSNZmQIARSi3hHyjVVv0Pdf7vo9/t2cr/X
R9Z7mB9slGefewdNdMVdTM/4UcofhfwN0PXurQmB7bQYvJ7gtEBkrAz81srqurz0czI7rfT2Oj+K
zWgTyfhB8Er/i6B3oWbA8pIdm/0DBK6rNs9KDSY74EuFjoKOhJZDvRSfa5RhbxKmHXNj5ziq6olu
BtH2iXNEVV8TZH+QDNaKTMIr5TLQ9/QhB/fTa2VHUMY+TdVOe8nnI06AHr2fDWxjS2lCHrT+ItN/
eVmY/al9qZw3ZUBYX5dSO0lyDLXgFGiBQVApXFHKXdDK0fQ7OAZZSTeGZ4dXZPnH2RCDAUHI5cVy
uL6bIw5mi2QAeq99lCsrfGYFhreCXywUvzG6Xj/ZLlyizKFiTmUQbiFPHY6zd+xRNYSLFn/EkKW9
XDbjBzgiho2gMk6Az4fRjr0uLA45M712/1X74UbKP7hLYAvgeNyTTeeEqqgOKVMJ7JIZD2nCGzC4
D0ZwyviwiFPW6Qlpj2eL2Rhl2IkHBlOOUitE+gDpUSJvKgLL0uQ2EBHlHRTeipXrk3eApJ/qyC0V
k7Yuo/XoK8ws/iKqqK1897eN7EGtTvsWEfBuwQ693FcTSITSOSwDpFVpLq1n7ngNTjXjDFfO/sRO
kA/QBHzwHpoh2/wh4/Qy165nY5ai8stR9Hz1CBdv5zIar933qHXSpccKKinCAdWaR0KnxnnbotLN
wu6NeknWAtO/TxrwWy9CNhlHLNWHwBcUQmMl8WIq2g11gAJgfq7zWOz/rEE3tD/NibWT59M+BQ5y
xAn56eVwwW+CXT2TPsnoa445nCZSUUtpWUhfGENn3dTstOupIEPjLQtukVF+kMg2yjNbOZcrCEzU
63jFEofGic4DWXrRnv+2QaRUslTKIHoSvCArFhGzjig30RTLmXi1Ypd0Fziln+GJ5uG9swKvJVx9
4SgMSYMzoF+8697OX1dHPcOdhWixGWddWg1aGdxpBxblE5GzcNMDbmN59KkHOGoEVigC1BMQ0asy
StG3G+wYBWO9KX+XD/SsWYpRsS3OzrVxxXkIYXrVkANyhuV5EejBowv0Y4dW/iRLxwkPSlAfSmvT
ZXli2ar++nozwwiDUz2m3Hw9T6hEw6oHWxllRmhAU9nNzYOln2odM55DmmTw5/x1z5f48hxCYPzD
REXAdeINrJgscESen16E2prtukhiBCbMwF/g9WPNXFB4IOIR7Nvr6g4q5XUMeE9bh/SRLrTiHOzO
ekFzFpNeMI6yWv5Uyz1O3J/QjFkWH1HO2aEN8wfMKilpzvqY/kGXbCfZXVrZwXZ1I1H0G/MqQFOU
Yy0wQCxsrus2uhXoSR/USxLtfLRMXBaakGvVvyfODD5AIAePXqhPT2MCk5TdAJW9QajrO/f82cYW
A+a7u7My3iPR34/7EcF2F3SNRRCzcoP4b53aBjwaqQnaUdNL0IUsAu8vEQiXG/F5DStAJy7lYm5W
BrneStDzscv8ypbr10gZykKLd7MrqQK4Em9lOzz3cvhDr3t23YlIMutNGh+gKufls1z6+U+lePRl
+9znSlPoZPgH6mT/byym27zAFhnm3rCrk9Lsup/SYQEPA95q4+fdsQINPtPU5n69dxGBUjJqhPmO
1KanqTT9E3/6XYtiOA/o2IdMtQiSGf2qb/Ieirv8wrlY0Z1OWICyGqqnsbnw4RwYU+BFKJIrz7jF
6fvm1y1i6Tkhq+GiKPbIV2n5cnSBbS9UJleO6aqgJ8X1IBWRNYiWRukBNPCF/A1yq10MMMC9Qp5P
FybLqLDp9Kf+TUXEieRBJJNIBmPc4G5LWUaZ6qWoybbVp7hxozXVLHBG5I2SNS57+XAhrpkJew+z
EGNO/Z8h56E2DVJQe+YHP0TcqUe2IsnJ5IHg+10fsaVrqcaGH5nx6pZ6CkChECJ2DuQ6jnD/u+un
+v1SzKzgebVcVT8e360CAKuNJxb1raqExSIZAfs8mIatJE15IljhNPGiY00bINjKT9hUy0PbTj/t
e8c4KXI621ph4qNB0Nnzu/LRQfevZJ+Wct2SP/b1SokhTc9vt4CYdMH9KrTIwrdCXKnoVUh7KYIe
/kfvITsRPkrslGySBwwT4azk3BVA7MUluTyrOaf7KrOp21ugspU75JupjDIv26hyI40tqQTpLCBn
WwmlmV/DMDQrCctFpLwtqz3NiDnDsxC8FEqYWSiOymN6mcHRPK7kdk4L+U854lu2+vHCVI0OFlMz
WX7e6RYLB+GdkALpOR/fvyezV92lChq/a08Hj0QOHZPsFQKXQBjUu+a4FLJajQ9+tukm4SELLfou
rZZKd4lNBYNs18QncHDsaPy+jWBQCTrN40h7N3pnZ/bem3/PJ94IwYCA/K61dX10AGdhRmdJut/l
sjjcHcq+iF4nprrd1kWN+IN9X/gW88PdH+rXNgoawesBL53Z8+ZrFz2s+cbdxgdTZI7Evf0pvs++
u1/82C+sKqDq19qEk2Q4DNg2/TyHU03NbnIleWTtD+11Kq801OLQkxX/miEfjdbSV0gH6U8Ffv6i
MhYrHMaxHp+MVXGL+rzmVV8jTFxU1HC1JCMV5W363OtYzG5MUdA8ZqLLr5rdFz1IUrVs9/xMt+D6
Mrpwkl2g4HxEvKOHtlig1iFB9okmB/4RjmtBRBangtrHmfX0XaDljxEcY6FC0p8wvKKj57oVX8Mp
tkWGF969Wl7OcAwajuro5NCINKL69uV72Z/96/l6Mr/ki6IUe0WNVxCytUn48TixMl8hj1plU8mS
J0Jp0yaYE9xWd7ayOGzf5x3A95TRemlV8KF0wvPpaIwRXYGoOXEL+HfkDci/l4egfIWSEp8/9Quv
4/pP4WqgwEB9HXz8JP5SsIENPaAjPx0Y4EqXydGUZ2U7EhikIZ8YbQFi9aqWxln8iUjCvR5+w8SD
oD8gQhPevfrZ19oDWmJYGVGdtcllk4L10PzyUiPmheRfKMMzzNV/1ILxIRKiR+JRPLEFKap9EY5T
izSkBKZPyQJ8OzhAS4bwWpj5FjY07YjQLFMIQNBtlR61PL6yG/tsEy35wBTjo6iECVagtxhqj0yg
b2pj79Td+15benylRoBySy7sT/44X1I8knL9hRJXdfiqd9Pn8ChQ83V4U3NfVEzNGI3sRUgH8I2p
WC/RnMYpqcHNX4JEjpUtJzpBdFnApVl0Ye8GYsKPfWbe52Gmwxe1WZY2XpQ6E4w1on5NKpKDeP4z
7Njx8jfhYfCYML4q7ELqmRN64/cZgc063tz8IKu12BZEbh1KKw1WH+Q8EpStTKqmP9xB+CXd/J1h
VoCF20SB3TNQvzivuRPNT/uYD+HSfCFzMe5sRau7ds7MQs7o3Rp/jCDsD7aP1CmkvE9zjkmQwIT+
I7eDnEC2M2xs8YfsJBZk0EzoiIGuj/iNzjTZ69kvDMyRPP/llgyzLcX5fHwKvGVjqotqy4L0j77I
4L1mrxj2VX1XUsnAZj0M6lQwHjvX8HHdvoahFilTA2TtMjGFGJpYhe99BVzjFu7HFRX7pSk/oarB
oLxqQ28SOpQq0Xbus1Au1sNrau6uIq36RCCjsg8tGuZYiIGIiNtuoJrXMgOK04Rel0LMTrhdvCEj
sL6S3930pphIv4ndtHKji/x/D8bOihXEvhXzPHWsH91eiM4Yw8nKHMkTdpqaKgi3NhwWnAALdrU9
HNVpypG75bGEJNIqrbYwnonyUigK7hnIU7ggdiy07dJnpYeAZ3c74Nxh2EA2w8nn0FsHfneaTN+b
ZxdsaQ6mbWjL3vnMfbmPanAc9sDqBMN3nVNeCJJIkC3qP83dBYJrT8OESYlLjfxwgS47Zxp5QmmM
gKgh3gF3SaTp9TIQ6gzNKaFM0BseoeXu74dV3r/DjxaIA3zKqKxaFmWdkSTH5tJ49qfXECIulTRC
kc7e8SiTP/SStnMD87OX6QWhVXfHOURk71rwV9wje3Hd4DppDGOrTlYH/k+PnrkC2C9mKzfXDa3i
II+T84S0uyObcS4N+APrFqJDaSajBuoKDLpFOTuBe4AdLXh5ejFuxqa4z2eCIIuAA2c9MhpzNy+q
qzfwIhoUeFfS3ztW3NdYSYqgG2bZ/0CdOEOU9gYg4fv6k7hpd48Pm/rjgXXeDT9cdirstavvBw32
zysiEO13E1cDJGhL4HqK1BP7X9HeSfEN82zoRidrKJq4UbL9Y6uI17Gy41pouBc2t5z7O5xQtDAC
Ostwnk3XCfFybMmM5ALpP9DKS3gODctr4ZuwSZ7j/nD4+/jaHn+O33SZTAq8Dx86/0DM0iR0YZjE
rBuKjb9PdlUCJTaPqZYc6EHEjQTitICUE901Krl7DhfvuZheDQrpWvOwqG/xEzNcj54X//2DEOGY
8GCMdczOLmLr76hP4jVE9CuPIOmCQHQ2bq2T2fmHyQi8lCEM3K7q5G634O4TVyqoBWv8gXwBE6Gf
A96qRFfT1O+rzgF4WxCvZ+8mssE6DUzkM4h1nf+kDbTT1kJ/Xs0MAUTaHx/GVIOGvDAWcw3Sq61i
l3rGGfuygkhL/OEfAoJV1g3mVEH86OrGnGjnoaHJMcNpxAfMe3STcarUbN8CM1fPIOxVBzJySaUz
fXHBllJTTgmD3YPNbV6OX3hH3a4AiLYGgE31W1KY/uDY7mMQ6vOinELnNWhL+OjzTmFhG5npnaXj
KgptZECGoYQaJF1HnSIUinVOV4OALngpUnSdYJSdYLyLjRdM/LkClmYJkYhqlnpq9mAKcpbk7wlJ
+qegHZNErMuwxE6a23zD0s08GssZFAgS9p77enVSxysDIdD3ZPw2i4dOjJO1BHUBAHwoOaEFW7mC
mpp8693aA4GNOJrMO3E/kiZUmjtYoZ4b5CErp+7NKdr23URihfV9yJBHfurTrN/5OBv2GMlzuyKe
bKzdNGHeov4qmwv+8+xfxzF5sJdUXJetyfWN7kTLHMHPnrSCeLOmvuyDJszZ8GUm2OOay07pt5je
/T6K4g1YzHAoLuahIcSx2mxG+9CtTva87zuZ4l7I1+auc4CDc68OSur9EAkR0AaB2x+tb2s7/YSO
4O4bF7IizF4MYA8ygwU8Kfz05VF8OwyYbVmOTnIaWFCs7LFo+wC2lCORLJhTlBKrpNRrIpJhRcWU
Wpv9LSBCNCw1OmIxL7/H4TR3DY14aN7epPWL1V18PJFkIRjhzJxQDT9dM2WYLv/AXsuRnUygdnNc
kdhh8yWKAH9O3RdH2YRVZ1wh0ySGDSZd1F6lrWlpxfxR1ZFhICK8K045VMXl/ZhqO2vVwpIDexjR
LmmXz5sf84a6bgsUekbNNcKCNcrO4JPISoWT/+gXv23MhlocXcaiaHvsxSAz3MHD70QQFGKMerGM
U9FsW+U1tiLGbtCuH5GxU2eO5bJvozOXstimuB0I6rtQePH9UJ9zeuD9lGrSOlYt5sCgYNoBw87M
17O8A+9dKswrKtfEOEIe+kW7bRxP8WW2y+XUJqupoaTxxUAVn212ARZu3Yje+hCL8TaJKoVGG6FK
3u5vF5Lmk8BZBQV8j0R5zeE2Ir0BJuj9bcLALXPr/EqjF1xQcm3qUDb1HlaZT4VdldZ2aTGNLqnu
H5jaAqdzMOliU2svIg/+soFPipF2ciT37SuVeQ5yDYHX5Hr9TD1wkukRirDB7NIHn+DEfxXF+ovR
uO+ggXnj4ooVN3Gzd8CTZfqkTlnyd2XhDcUebjCk+NqgaQPErRrdKMRV3AXZkshwQiutnNIoIsOm
45DV866GYoIXNAI0huf6VRO7Nr87FmQe9opiSoXZ/D8ZbRKHSCx0jMAFSq//qapCSxarWebfi4F8
2RhnOnNTsIp7WaRmClHfErKXOTedoeGffRZ312mMmYSFC21mMppmJva0PqLPwsZ4bioCS0NXMTny
q0z7qUQpk0i8pPqeHRF/y6EpKsLv2ZFu42tDTUKDUdhcMOfC3B+DXc7J6+pkhquSM2rz3/QSgicK
XBRKBqMiBqQXb6xiUHIk4O6X4Rb400ZEkx28cFwNtPfqKCf8il87wq1j6Zu6svddWsL89OZdVCyG
2E/oObQqn0R1JcgHJhBMzGVnnSczE3zjQ2Fwf/YZFZ1Tx1h9VVIfKOBkFX43BjzNZcuT0WugHwuL
QMqeBn7CnbYloQzdSCcFFOIXg8VFvoRO6cwadEFhIUu/wqkYRGz2bzeNMKuUQNbz84M8NOrU9+CC
Oq//fQwuHOqvU1oncIx29LzdauVQFCDBxgAZn3qpo6fwVmpVl6ZNCz1HOQTysaV/IaZisevEJVHX
jfYUVuIQUfbqdlPX8FNwJY/eDZ/Zr/Mz87uexDJNLYPuLfPGZTuWE2qsJfAUyjC0xzSoi24wY0cY
6g3JRLMyyIIC8IGxTht37w+xVCGbbzfQKtfu/Q/FsGTBk9ORIMtWbmgXG5lrTZOEYzE1HC/4ZEyk
+E/MDT3Zll3HYYbgoUdN0bVhLmM3eeDEJ67/EVnKxurvXwF/W/BEZA/z31234se41vCw0UXK4xKU
9oLo9TvxLk+UNctaC8asBpmQtyQjY4jl+ebGsn23Ay21LlQfQeNGWDneyfN+lXj+cQOfuPzTV/2t
rt6r3OXnULRPXmTJqFs7v39HTOVP8WNBTJ23qe+dK93kLAo2UfFjruVONJjWKKw2G7Pd3ILgwfHm
75qlvYh1NNlUESgpVAQ4hwXdtOkYBp7U9AYULCkXWCgm84/QuqQ2p8vDOXyqaK/E7++Gy5pzpV07
rQGdP3HlFoaPgOM7Dqs/SrfyIXC12Kj9DTxcR2AHz5gXUgaw1OqdFF4acgMNvVzCkDVSgwyivj8g
/UXMQCYqet9Rm4LPib+p6Sd3IHaKfejmj3erUVIf3eSlwhsg8HhZp3EwHHJFiKHJ8GWO14NAbEsZ
NEkXTbHsAT/ZwEn8XjGZpmrCAurjih1wR2de3cZAwdFnDRDdgNvg8ikTFW1jhHuQkFITK4pmesZX
3GcAjtXyij7gC84YYTbBnc3SLe2NQwMLOeLVRXksDvCzCNeIs8rwyno2Asa3kzICRyg0cbO90um9
Tuy6z2/5iGWO99UCZkau+C7WauFOAuoP/DCryHEXZAvkWll0drD2jL1uHKUtZlR6pMR/vASNIk7B
sOl+5EeExPLG9XLxrPcnVOVOc0UWYLZJkWPy9Tx9zXYd3RqIwAfp4rIZXXqVSAJcm3tbOnGYyPMU
yPLyHo4gK/8U2OllbuA13k0fZD1kGzA/Ud8yNjNYehESDQZD/YlnG2xFp7KWzmylBT1kLn2GepTG
5S9WnLyY3rykWBeA4eKV02Z9ZEeejbswhD7u262eBGcpaUGJ1ucawQQsHRxJ/VwDTi6va7U8Mqpg
Mapo0nYfHiuIjibgaGo0jvyo23AhmhmycEtfDTd5RYOOxtEMlciZwNVla50acnET0/zMZr1pV3GQ
MKLb4jVbBV+aQfka+vyWhkUbLsRsC/RTHmNjm1du3jcYxo1v8Kgp0beMzW5LEiLExaTVFqBNJ7Zv
SaBgoHrHEu5am0ww8JMWfOI5gty8vaLDQudkwfDzDaQuERVqm9FsheTLXKXpn+43dMCsiD/KW4iD
pvn8fKwrTc8qH6w7wBhkkuNwPNral+igX8XlUD/NF4uUxeunSNDv0KJYHS2RCBnbTItKNYv/XQ60
ojlpjlgd2zOcYnJvNfjNT6t6S47rNMdYblxSX6rjpWowaCC9l1NxBZ630LXzDvetcfp+N5P2sYwh
but6QP0C/EwFazuxYHhqUkZGSGmrCpsjw37lXMxhwsT0gRzg3DVbC0UZ2K4kp1xX0pPl+4JWI8Gn
kd/pzI/jguDQH5zygFpg2wXcuR2f83ifWGFV7ynJBisIhhsf5YC4Y/SJdS/NPVNDcc3yo8axljUV
xrdusTpPPDuDGpOdyorgcM6k0e663dv1nWsD9w1V7DtYt5B5QvQb3HBfSmCUDivlAm9o5ZutYBIN
ZmwyM2f4esH19qoo4TkZ52K5TycoEaDc1mu8L9vPkycolvY3TzU8o0ecfxBO7/5hQJrNEq+X2IgF
ESahtIKJ+OYTwh/9E8Je+bfhqIztOOJZLuXiXnnpEb3j9iNW45KcBr1ZPzcO+IpgcY4ygBgIIhnq
7OYGRatr2VTW0vNXI8M1W9XaJjo3rp121pe3o1gEYAw9jqRndub1zARL/FEMtnABhxNou6WW+gUz
S+7/TGUwTnluyD2jXDcbwb3g5u0L7TRvpflTnbqzoUx+OI/IwfOy7boKqCBSnGz3GbUemtBN4+qR
qVOqJZMpRlX8cClYrQ7LiLN2J5ENiOUR2N62FC1omhqFCgenl5/QeTFGami8a9aJcRZD0LecGA3R
dDv5otzn5lLbSNsyq9NZ+nGHMyuB8wTC9GOLc9cZMp9jCH6mAkbG2lDL5/98PX0y18qg8OB/nOfO
Q1ktCk7zfijg/VPkP0ALuKTzOnM6Or1dgfRC84rXchaI8eR8T8dejGRF2oHGLA7CkLa5y4CpT+uD
bFOccmvkLIhRl5FFTGzbbclRhB+rZvn7Tq1cBp555Qy8GRVSxnSTPWWZN0kczRQfCNU/rK319Tf1
4FJz+39au6eLrn77tKl0L6VQX3ez+IlTdX+/JRQu/d9viijcesghmi7STQQFDE3CSQysEck+oyQt
tO7hREosA5nM1mRCN2hFZll6KN1u64h6prFuvixUOnHB+4MiLQtY4w8A39MycDwSsoAoBEO7YMLk
40py5V7/dDTxirrSXzzOWkkj/n4qNQhYuhCJmybNNFJbUq4Jjug4Oin8gJkeRvz1xmIcD+7NrGlr
GchyrNn/dT2hQtr1mcGZhWUmmGeBIC7mqEldi2BLU/oQUnbMgZoIkmQrTBm2VqEUL2OhUsaVoCD+
HgniPJ7XPqxzirAMefpXWgIpGoJEA9zZ0c2MlAI1IEC6QKD8P6KiR52mvb1RQrxBf4UXW+prwFMh
xhnfsfZB6PH6JdPS5ZnH+box/9DEFih4UwvKdvDvEPFl0wYxa89XBXyeRDmjXDlNbkI5tKc8ZMj5
YGUdbjXJi7lS4SX8GxJeorAsfSDF/qXHEJYKLU3zIdCTxmCA0uiOvR2lB/U5zdLJOeN+4M+MYc1r
/P4H8IXfcbmjqPnIbi+ZaSIMmjtkFCGC/07GBpG6Oc78lqVvGCWsr6nn75psnfv15YIQxJbTp8Ra
1CrlrmzzMloFLTfkic025IICldAo6xW0xT5ha0CNABGtmdk1g8/OKbNlB24U+5V54QtCTIK9zdLW
thF+ZXi4x3v7s1pOJk980J+kconI23cwYVIJNnSdLdEczi0srm9NLYZhB24wA+G7qDBtkTUtCB7L
eZwncR84NqKTgbAwo6W7kj4yV1P61mjRoqyyRm6dqYwDo2gP/7RDv5TZvYgnUxR1yNUXQ0Vvp/wu
zZQ4go8MHa/8RMXYGCm6sd1PWlUljwXa+LztPUqeGASA8R8B/5rmhaw3B7sfjv7/+r0FXSnGl1Ma
U8oOtl9Q7QdLoMdcmBtr2Yd+Psomjs3mKXfX9nAJpsa7LXeiuicH0Jae+zUvK7XNvUsIXEGuLVA9
RMN9GAKJJQR8iWU0oLQ0RA0j392T81ynDVyxyVu4NDEWQpfvNHewP06JQr7mGPbXV/tRpcVhd8MV
B/ku/CL+vup5piAQ6uAnO8mUcv/mcX4Sn4+ckK1I8XCzU7VFdRslJBWS+K0Il5IHu7BSxkUaaifW
4zFslEtQo1QucIBaoy2YNyCdXAxWvmsV1HoxSm3KVNv9LgUikh72noaRzqmBNDYiqeqAvVcI21fL
dHH00FIkKB315ozvESUY8Mepyru0n5tFlBZxnskNNz/L/NNG3TN+7x6N/9nIxjMSMDIcfcZ4ImOy
8OXSmfVnPLhuNxamsmY+Fz8qRlusyhC1o5b4fYUUKB9sDDsZc5UPYCjZpQg9yiLnhcjhpRLxilrq
DjCC0yM4LT6KJhH4j2ugGbxML2NRILlocnwpEyxzOOjiR0DPQCsYJdBBH2jMnD/zIjYJyxO6z8pH
GAo+dTQtISMZUKw5z+cvUPi0sIjxy0DgKoPIqjlv6nxgfo0qfg98ibVp/hdzJXYjkeEzaclMwqXr
BQ22frgOoM68No45FaLXeSBj0HhRJ1WMMdD/B5Yv5ehma44rXzkXlLKOKJeVgmqbzFvNeA4rXvEs
WBG+Wt+wXRRA2hR5SbUNMo/DJ77bqs+NgOC2MdzQSvRLQ6fjRkrVHtfwFd7PKlnbtpdsQ3auk9E/
epQLE5K3sIZKREzde7XTKh4Ec+92wnHErwQHYRZ02sqCPfVp3mJ2Sy5k8peLjB2yYhjhjkeKdAri
8A5oQItX3jllnyxs42NzAKRfd9OnYI7RsnLy8xtbgLVlLomZYQuONGcicXWzkvBVEI1iWdVTLPg8
6CU2L22zUraD1fs4+CkWMSu3q1u9T7u4766YFgcE2g+TcntGiHpMkCJX+jRNjysjUKgP/zWlO/Sx
4+dGqaPzpfAJexNUDnbqKGpoQJXvP3miBpvFPAkdSqbp3hebJj9CjWxd19SHiwIT3RotfDKqJGje
1tgAqlAPnV1VtMvVPEpwn5AfOT1yzGYd7i1GuPCBKt53xhTSYR7cGLRL0mGJtY1x6O+DPzRmKH00
the6sayPp/X2br+CRUmPd5aIClsVVKQdMhU7tl+uRDzADweK+IBinlaeiULqqfVfgi9VESPsOJx1
hLiDjr281ly8dMb3dkArIkXaCZdFlYSRbMfcs+AeyY7C47Nbll5u+AFSRLTSVSwknH2Ut+lwarMg
Z0RyTVN3xVd4WrKinoClbsszuWlfIBvFLkoDIboy8jUGnAcIXyZr1QdxJRKrx/RaWyamugp5IEBS
G2ay13pbQWKbi55OZfIcNeKJRMipVR7h3/sZyFxH9KdmG36Nw1dJYKiRwrdEMFlhzkYwBko8skLz
jSVKOuRybafRJmf6sUOgW4gA4sm4KqfIazTDYdVGhWo2oDBqv2psLhUpTDYYkcPVtrYQIs0FGoQO
70caGmk+zCFX1FzGQYcF2quZEHn2efjAMf9wvlcZNk0agz9Zx1DHCt0N3uS/RgLmDSdTHhFJcFVn
tF3j4CzZW+ZTNdJLxQ1yI1iktJwQJbY5JOvuBt9+DIAiahdRl6JYFYw/2K+4xJA0H2Zt6JRApRNw
JwPd9ooUeB4IxAPZqTixuuz7G1LOghYfHJ2GgNJkyoxeNGpq/ruYoLSRndNz1P4GY8Dnli8NGRgi
g6r2ahwc/7+lQpnJNVEBBtmuElpy53I6q6D/bzP776OoKaDoIxIEqgySzzoCzcxB2YP3iUivwAaX
ewUB7sBmrriGW1i59cF0/Jjs1i9vrqLTsbKErevDD+bwhwASJzimMWmq9wI6xf2TbAnrPu5yQ9xT
vI/ZQFzliTBIynmWuaL11Dz/FmRPrsGti6zKYyap0RDaVpZaYxsLmx6fqsf4FQOoOd8jNvruq9o3
S/tlRkA1YHT6U9nccSr68BQFOYUTBQzu9WXlTZjkrAV/TCxgBAohLx8tXxCHFuT01DyyqBV+TOoT
S6t9Y5DJpR6I4i2iMLcV0UyM0HL9YEcg0MqLnxVixJM9BBjlD74n/GJDJy4guJOLCaDYQ01ilWFO
oCvxALypLZiwllx+3btMrZFe2oiESW2tjDDAkPosubMgq9uc1D14qcA+yEy1Lv1VlrODXfqzqdmG
wid99oCTfwtdnQfwg2bU2OVSyaSvpePmWsN4XZMr8E2im10ved1iQHiD/N/QpeQdNAGHREOPjMl2
JuY2xFDeWDvH/jNOWFeDp1hT70UftvRBuyAMFvveyF2YJusCN3c+t+Kk+rJfvf1flKZTLrSH4wyX
tYPLC8hlOUYjXsGY8DW+6oJCMtJxGiqj5wHWfk6ytuvEG+i1S25UW6DfhYj8ZIdJVn+q1NPMyqgA
AcAKmDlVep8kfp66ixLupOELCKQEsGPP9rFnSWOeG0MFl9ZpyN/1iDjt5sU4PDvQ1I3t+myo7xni
PFSYOhlJCdwhTKUPE66LXxX+0gX15jMXDZ5xB3cHeHLc8nN/uRVb5XblxiykrraJX8kLnIOH1hMH
pbMsoRRaQUdgYi2aU6aYuXKa+rfqOCYTV1/qhh04c4ibuFQPZ7VmUs0UrakooWg6jvTdEsTbIUfP
QkGL88IivvTuMgMD9d02y5Ndv9GTfu0AZRXq8Krd+/9h7mjTkCw7ec6FV7ubAluQnZpp4gdZFprd
PktCnIVzEahr4ASTFurHrn8jEKoqeehwH8jIf/5D/hdJr9rNtwrGUn29lRl7Jjfqygwm7204cRv1
4PkCBex+wd6GEh9KGP1XcP5HY0AKksLaAjaDhi8eJYkYFe1N3fbSOBSU0s+gaQ7hGbuB4Jg9pmSF
6wQWp3kJ/aNqwg4FlHLV8HciqMa8CoIpY1jDS3ApApflgeB+cckh94p0l3Rw3NN8xDR0n8QlHW1t
/jQPsu6tz35wENmRM1E5pq3eDTPTEgb1l4ftxRY7w57lRGFmwwaLhzF5dJi7T8KGuVoFbN/w8E6x
nml8Pczms3kYZycUpoKDRX4G5N33Nx4rpRcUaLwKb3a/tYurSp0UF5PczdPbQb55beF1ojcTVh2r
BoPW6LDjO3iMAxgV/WMk2aHTC0ThmIwkOZGDEgDgiEv1IBnfgQvkkFMff3IhJVL/gsn8pRWkojs9
mA+gp5rfzNzGCk+iH7cgtjqjuxuEss8XoeRdvgrB8MciNWkrcdnXD2rVC30mTOaVsBeLTl6LoS66
UxZlCbxo3+GgoI1862N8RHPS29y7p4oYjgRzJvvyFvlOlgVUtFqjM12Hyh+wo1QPFz1sQXiG4ra4
syfEurvk4ICtI/f4Aidpg62D/MSR+FJrPHs5wIAa+VOSqrnvV7gHugrlaLHzplFsv+EVCAT0dZTY
w9DSGGs9ODqYyWw7Ltrqyp18uHwoQkusYMUkYxEl5HbWtkwgzw8vS4asFFZGzr2h/2+19YFFewyq
sfMZFyogUxx3u4TJisKJ1bd8RAe59yfadexfaJNF1lUSxcBRI9S3hTWaEMj54OIxsVEjqn5xaORa
noLhl9VK1YBBLHPcEhf6KrF6VaiIjUs542iyzWWegoRo87tl8BJ9+MsKPzGmfUcsnj3/eJtsj/zy
jRjUE+D16T2Z2mfNn4xqtie49hJbr4QOIUOWewX3YAU2eV44iAUI2cX7lddrFRbqn2oINjDqFVjF
0j6anjeQMmENm9MTEKAKxrdKezaKmvtdnHAhEsIRlSRrTieENWkO21ihavDnkwN0KcAmvtGWdVn8
wQSrnrGMTN8McOGWAIX2PVj0CdcxSQ/eal+OWed9U163ZbyZ+fMhCo0bDr1/mRkfzmVqhUd/5T2s
8Z/8AOPUwODVkysGsGmBUwNFVAued+N6rsRFmAtc+z68h5j7Z3pfvr0U0LkqSULQDZhZcln73qPv
YRCszqX3tDM7vCr0knVrkmr0aTF/mL8xJlRfpeajwKR+/OI5A+pdonx1y/lgvUdtiLiqo1HrGbB+
maOHjQGKX2GX4tSKBcY+G4pbR/nShWtLC1BeHSu0iaL4X19jvmrSMe5lh2NZVf0IqM4XoNZlXXVD
kybzLu4nqMq0oHHdbOhcUkhnVU1bu0B6YCbztbllBrIUk6ZLk4pAiiQJleG4jjO7c+81hjLLpgP6
3jY3RaWq3CWNV6rCfHaLPj73YAKeB0pjDFeUOtw5geES79Xs+TQJOhOUzDVwKFB2BV0ZLT6osS3k
6oJq5j9s23XQcHyc3VrOhhN+D6Q9wKNP48M34Mxk46yiEY9P6IhnfgaUbGBIXEZlP8vSPml6xPl+
+iU0kBLQsw3NVyWf/eBSZkkZN4k1dzshWojiSMANNF9zvPA5eMj3s9mmwUyrWMwHeFmjLaC58/mX
lnKAf7CNDVVjqHh21CrZP8TZYfVGS6ja6Ld52wVeVdmyszRdLmklmG+RzK0Kd52Wi0tRlP/6QHCZ
FroClWgoub/Q41XbiXBjk4AQ+5KlQqzos4f7glOsnuS2osE6AU2dSKeTnLinOOal6NS5ZOhA2OO7
PqeKbOPUYtT3287GAVHcEYdKlRV7kpnZbJAUVa6oBUH6kXaq/VAhl/rWz+zfOR7LoBimlQtM3ViM
/x3ROBln6ey3tjXQStvnWmrbD7xwm+mCfRkxd0e9mh3Yw/imuAqr75BJmoN1Vl2mUkesIVtLpLmo
HlEiY+mG0zqOonhZyYmNI6SXel8mPn+NxGkjO2VWI1rssJfvzu/J24ZVhCD1Tv2hSugrQbyVTj81
TNS/Rm/vTTmKOgNlgl3e8iS3IB0QIfsKdkeobx88zxUaBfwukjRfNC0ZRq+3p+8HX1O9Rkbc+sXz
hUEcIxq6PKdRDTCZYDsZj21jRmTE3sN+M/fRC6i9GltOGjtIyudc3GOXgcF+IKWW9TaK3PB6CxpI
/hk7rs4Rl9YTc+iAFg3kGYAKpH9tlyte6ihavto4mIHOm4zPGp8FrDHq8XIXbXwNGmq/O5JAMWCD
ec7T45XlLoVzhqaIXThJ4CRy1PKmN39WqqABcaAbSLPH+/qM/Xj5sviX8OTIl6exndSTfXhuVF+T
cEaf74a618FerMTnoQrglLHPqp7tzmcDMbp9ov/dLgPmlBLO0w0DxuhKHhBYwrGrRJPtUvUlmdxw
Bt5Z/taF4is0PYahiq89yQCzqW7nYd6jFY8+emtoarn3YJ0aHXr+4bnGL84Lzcu4Uujwxm3guAn8
9ETqTkL5l5jsYVETuVEathizeyYEEMtfkuLRORXlQWhUROqOlIo9+W0cTPYL+y8LCieLLAgMAVJ3
vF4IsQhIY50RLm2gMWL7t/GyWIKmrwtJWtelSGsRtgAN6+QZzY3zMRbUyrlGOki9ANHsvbgF7O8E
tfFcu4oOGfbAdLcj1gYFtX/7V1UExCFcTGf7x4/wZbDqvkvrh90tUHTWSVcQK/f4DqR8R55+nnRU
ZhTleVpdN5qhNewvmjMbjMzY0WWIBlPr3CgxzKr1T/lwjdszU/LRMPyAYPvHlsMgQT2qoanlgDLo
aeyzRKSq/1crSSH5A8ZUo6+7Wcc7gLTg1GiT1pfVccrGjwd30NzPmxmA6tV8kTK00dcm0k9fVtgx
mAYGiXjA5ovzuq3Ry5mrkIaKsTlsZCN53ATCPD3pHYP+fQrYUG8NTkA5v9TptaT3xV1lHGAMHJ7o
ceIu4Nf3FBx4xb1cYzX3fyVTGfoYJXmpeX9fWMyDCdimF+1+CVQG+ob/GbwHifWXhcRs7914z7ad
5FhVrjxu+KYvpebtZA+sZutDS/JgvYTqotx3QA/tpkADT+fDDHHypJW3aLvmkqdzatwwW7QS5R2T
MJYpNx8SDusCGC0gFp8xwIB3ZPvjdlXu9bi7Zvs3OAMrsg/l4PLgSEiYW/IyReZKu9Yoefm1/y8F
pGmBetCnA8rg4FxYGiwW4wSnwhwywgNK28k500NfILWmxlJmvrc6znfGCTq+6ptGOw+cTjaGcb3a
z6Qg3zEVj+LxWPCCeS1DiEK2pJZ+RRVFwcC7GTlJKFmgCbtL823yL2SZpPUFNnu8bn91IOG9RnKF
JX6EsTQ6QKJjSw4P0OXcBmqxW0a0p4MSt2ZCJw7t6+gM6jt4ViaL0K8lxHNo5dy6AHbgJrw6Hhv4
tYNlf5GOWO69ogV5MzmSKxAxfaFCxv5qcXdzMwUaqDaLv8OVNdcIBr0eEPSPfkcIXB4at4WzFhKo
qBRCquQHMARH9Vp9TbNprBgS1fW1gLTusyw7IoldC3NJMitqP/Md6A4Npib/YPN4naUJGCFJoiA+
6gCtq5KDb+cdQGuuQnXbLWC0nkF0z0p2zkxaagq6g33OgJxvAEyBd6996NlCYgQCW0RfzjgUKBnc
lLYY7eMlyGIGIorrNpfwchzYlsBTMQh/UG+UwgzuFXH7pBsyPd+CVmBLebSzRCHpwUn+qj6iLGFj
ONGvvkNYpuPq+p3AzdoOJV0cToQRy1xBoSzTBv0nHOoNCN7yxBDwrHbxSU+T2ykJQqH3ZI+NzqKx
QKq3kVNIpA2dr4Fl8s/GG3M3FoupqxH6UvVAdfHTosmEpR0OQwiQqHyjY/mOEN4i4OEuPoMLyet5
lxpRjzeFfT8WINaRVIEEP4Gxiu0lJXsvGpRi4NVrScRHOw/yc9qF5dhoHD3R2wJC3L3caKqDnoN/
QoqNoO1sz3HjVYDYcNgbEfbl+wiO1zD7TnYLdiZBDVsnOwZ2RRGIGbLQDNCDit5jQejDbfBT+lHk
1yNLSQ5PE2pORSbrtGvW8/KJ7p0/ZGQLiAUZw2GXxTGG1rSVjes52ski0kwFYvb8UfKxEpCcxuWY
2ucVstIiobJONBd791ehsAE8ANf7TRyONbn21Gn16pDAyJJUE6rwn2CBJNTIkbscLRsvCxtUj6Yx
w9vGBdt3z0ix9J8c42zMlA6BrQgGNx89H8adfPKXGU24rGgkSm+Gp65BoSPuBTBm3H6FoKvf93Mm
5EoGavFe2KplmwUXj7IkNdcwzK+DVSZ+IdhTzM2Wg056HN1VB3ZbdysL/9mV+u4+ex/xk/kBsjTp
rKm3l9CK0rRSNjRwzxmnQ6SAvH3aNq9xlIhLYhvbO/eUxCG/vQ6WFqcUIrJppUGQ/LnDBlgGrY77
MU6NSkQvWZQvkeqJqkLS7ElBybtFu2YhHb8EmKkpGwYwP5dWBg8kPg+qvzynUySwdqGPUyXCTCOS
nQ2s7G3Megm9SXnhSFeo5qzZK/zjvhyCaX5gQuRYETH+Y/4kE/CVOBGRACAfNLqngH9H+Lb/bvS4
ZGaOEzvWXvNRqEpammwnUeysFu7uDpEAdx2l5nAyB3l6FiTE9iFI8zRIO3G/q+YwE95gVUkWlUv+
ixCUowIxNIuD/zreYcVIbWNbMFS2c/VDraWYVZoxuYv7eCkCw97tjjFXIEawcSbL5DEWweN5UxEi
bc8x07d5S8xNwmf1P0m/E+GK0hyKEgbfgvAIyENNnD1YUYlvKiQ3H2E71Crkk9MclcEdMgTLKaKG
lwFKFmE3w9ZDRLhb71UO13qrQYDfHqx085d4GAB0ClXQQmWtkNxYd3BiaqjscotQFHmk6nv7O9gJ
gcPI2mlSzogyE0YiGyCRAbbsTN/bx8L5fuocTYp3uwECim2KCl+4m21KYBgjyo2Rijw/nZCyeYtD
MxGbtSQh1Jqm8YjH7yxffayANRz85zC0Dy2V9TGy6hwRho/6h6SMj/203aOHGehjxPyBqSdjsgY8
jSXzTD5WN9l6s0fLD8i62r5ThRY8nkRnqCZMJDNfAIPiCrQPfjx/yC5aNB3L7tBadU5r3Jh5tAGE
X6kOvbHjMjH62kiOlDFmdjkKVSN3IM1QSiNbCX9GNxBxmdFrq8hf0YmeF49vjTq1JZxkbDWRGMKj
rL3rtdDkRWGqCXpcOryb3rnHoo09LAG6Ui4frAjefyXWwUpN0QKYxKhkFHR88VIlzpOOiJqdnin8
Fqxveay+PWv1idaBepAgT+pBrvXbKRw7Ifh5azMNu33m6dtCaZ9syy/JDGueCbXMmSaHHGfIjP3p
cnyoOTCEYN/yAzoVpfE8yZehcOUTKWt63+Oaq/f2sVZ9ZgocrJpaV3cvdRJFV8/FMXA7xuogw0iK
2YWZfP18t4w+SGjOggLZ1p6FHcu24bqi58UFSgWIRtOyQmv/dfV+X5y6F/d7IzzJvW2A+9rNwWcN
JXuRc/6TCraUM+5jSVRAQUxjhV6SHBgLb975xbQ0zMmf/UHZhmgCWHy7LzsKZqfwydYouZnT8Hao
hhJ1qttr10tChgxH59cEz8VhsWllXW73pmDUVAqOU8QOhdXlN4jU2VPFGz9kf/Gbm9ydVHFhpcN0
vTzKd9PYF4LMmXk0/jR2RSJYeFYDpE4mbnhxUNu3+jchFn1J3d3M0+jHdMvw3KaFzrCmWe7PFwUK
wd5vHtYZOKJhn+/xas/LLM5NDfrj7LB3hNmnxz/ZkQzya2Et1PbwPSCfZ/EN32sCdiWl5Y/l1AHd
1Y8/V4e0rOXPyPYrEK72bpLrtsCrumcoQ9rBAUD8CBUnzGtfsaDFGDgrT4IQxudz8zh3qMWNs0cv
HeNvz2COLjdsqdxq3Bi3GlnG3dOxrCI64JZVz0d1JxT8PJMA/3XpFNlHgGFbHdXyNUNEifjj7lJW
z8hiPtzRoImHy3M/SwDAciFYkfKrUl2rvVDbD8ns7RBx/Fo/srXb6KB+VNy9fMftRY/K6k/0Duow
3lHSOqIsdlskcBjq5dtMuJ1bsRXVRZp+eZ225H76UVoLX4GTmf1vl39GJqX+b3pXeK+bjaKlwXdI
FGWcE8QSXWt2VTDd6/P/o5Rz1ckMFZygEP0PHeekhpF4klU7W3VYxHx/mkqmExIcOjgz11s2ObrD
mZ72Gq9on0eMVfGdbV/YfrUVRMQejFwiKDpql34DcIJu7HljVOjvNLc/QEjCitBR+5N1R1GVlNkl
WCqfqRsnC+cYVl1MbJOBLzS4rrnMzjfJBWScQVd+sff183OYQcTIn4IGn1os8fnVFeYDtfcUOJ8a
yRUPkAXBQKq0fh4Zi3dwBCzOxbQB6jh6J/3zlpHWtgXv2Ltr0EHajlQB2Jfvk0uN0QTTC/KhIEyX
I4jbKnM7Z4WtusYGS6JgZmDt80B8pl/ONf8kmZv9ASUGTlevun7+n/7ULhqD1Lt/V4lMc0OxL1o4
EFPdLZ0zl73rrZaCJSZ+WbBFk2v1TgLEqG7qgQQfmSXPibGbBLgQgdctCSSNQk7w+v5VRSUD/kaD
GP7aRAMcFvSO6HO0YfXOYQOtQw90KYBbLOJaxs86JbUrdYDnwbzYq4a8mig0tnjH9dYtP16/4dEI
+lopEyaWH7SW9qSmzAxMhxVN++L0CdiN+oSA2mdJhqaI9VufUCn5n0qXCo8V9TPA6jqPPxES4+QJ
EcSXvqlB7Ouv6TUdeEUWf7mRtIlYqu9fWuqTUmxHjw59H0hu0lDScOwaipyQsjLpAU3shmGZNj91
kSlEuBvgal8GJ2Xge8T/J2ifHtUWmO2q977NcITA/+7uolNXSKC6bALhFfAU6RAvOJDgLbQQdN8P
coS4FoZvdpW5N2IWFEAevlXDRTNvMgVufI0g5I+DByOojZrxLwvZcTSJDHxYpb4UpzcUEOpbb2X0
rhaEEQEM62TPePStZ2y9sJ9aDcidygyiVMdU4uENRZ1XENa+Uv+JUPqHsAMcDgJuUNYVT0PRHALS
nenBMVmAGaGfU4RVo+tM96llRd/7geYJqdl7AqY6fj1xCPtuyhRJi3zRcgPn3Of0o+KEraY0Oj3o
JqzcRt4GL2yxnojW+YhQGtWCsAqJJNNEFfPKXTkKW/sGDbNXEcZYrfEMva/ghKATPqgfxu/Knxa4
h/cM4wfv/t2+sARyHJJBNc538ksH2pdTRejriB8df1+VicG9CgfoAwgF1sSjE4j/B8xCSjLpgTU9
xppbPeXp8PPuPF4Foni9vVyf8Qn/4yuRwe0CqEnw385d87tjr4zycD2it7JdOPrfZ/Q6jV3seHn1
k7Kzlutvrbb4kBHzDE+aRrtACoR46nvojJZ7T7ffbE5hwV0G2UXueteIWjzywqkqUZNMCMV3QVe/
ZobGJm+/CL0TUQecmF7wKWWNjCFZWWo+NAinFnjj8zRTifJ0lxNm9vkr1eSWC+YcTSZx5Hs9HNmT
dQmCSyg/NmwBtiEEkmX2mBXe0+fYhw8n1JFBYqglEJnGUSKn4fgX/SGhinHYuzviq2o/xrvb4kFF
k0BsK9SPjwl+AGDi7JuyQ4bNn6FcSH7mpD1p3o8VjimNqbvpKxENT5M3THCWQh+uj8Z4/A3GFk8M
qAObKcfFg1nr3OIdhAu7M9bru61tmVcXGyuklsfMpQrkIKuan/F9QgmfYk3GWN3nRtW/LxiBc34x
4YnElYkR9lyYy8A5nEZCp1wmZyqt1qc2qIGVsdc+flWEXFWj3zSrbh7lY+RoaZW2C2A6xzceAl70
u/s7lHedW6rZcRbpcX2BwWBQg2FDXT3hcqmC95lePKGuZaPHnFrZPbQkPTLvluGFcXLhSAU3uKAu
0NGB3+twPt/fyNejppe9+N4bwRa43USTZpCiyDrnKggnrlnA/Qwj/c4ewug+oRSRCDFXNVX0Xcc9
4VVDh2Xgi3ou2S1VVoazahKEcdjJE2LesNVam8btzPIupCQfxtZzwc1jA+qKgMOYId7dQBR7d0NJ
kQnilfzX0uJ1I8DpaW6X/4ZVrTKbHlKQhZBImfs0wBBXEvSluAK5X4GBQrKl+HDvkZDRjcYaGtMW
m8DPfNTJx+5IPts5AZB2iFsH3yIg3JJSOGUuEbMmFFNVaQsDEsCrIoblvJRg+Uk2ESrn5vNdmV/Q
jPON67B5j0+prGhepxdqk9ftDuyxrSNSsKhRnMiLzs9UmduB1J4y4Nffay6dztTChdZnE23iY+Qo
pXSOtHxja951eeBuTwHbk3vQG1ZOAEbEbpPOF81sAdy+Ze154pjdVnieEvq49Ck6I0mWtApIY268
U2lOWPp2hpPY8/c9LUfUd1mxbpqKQqqiUPMDLZverWEVHHSiAhAmDuASRLv1ru/BgX+4XEiWZREz
UoLGuhbFkjYLAYia4XleWcS9ouMWyy+kIsUEs6sAA3E6efgulQfI++Gn0qyMgZrNAbN3mw3xkDxd
0fyw7CTZtwBgPYJgUTGWN4bLQsrgnpuUvaMUh84zafVhbkxAy993dbjvRhdL8H84s8XQJyNtuavv
d8e2+z8dFPNAfyOUHRx/ZoT5a6p/LjmTHOifIn7DgKvKrRztg57Y70JX5E9CifgZ8IcWvgHeQ3lE
OTvs5pkVljKQM6Z+1ibryJfgvm0wZPbAhZZKfZQnsyOK6jNKOPMrQNRQ2FtJt4iHc4vqfnEmcl/p
jblJsyiU0SQmzZU11tuiG4E1I5hGs+8E8kN4Z5cQr2hfKEiqNCYq7hLUT7iImLe21lMUot7cPmGp
qBwei+p/LMq6rFjcHWFEEjkJNAH9DtS3urBcOzGXJMIo+RsFxVFgbB23AeG9XcpI628fXqltTzTs
7wCduolb7RJ/b84uhBhXyYVuedmXv+076ut1s+Dk9g6Tdq3RjSdI4+9podEUP3SJXqX0d3idzoQY
7qifz+tj0fMaIj8MrkJnVAqjcRDbtxkHs/djuycOktHYYBtTKBZV3H4Kn2Tf1WPepFO8D9qF7Zl2
uTrfKBwzxZZgxeGsRCbm9RqcsYYaRK7+s8+gNFR44zU3ptW0gFcO4OQApa9REhSycUOy5vHk5mzU
7nJx1ZXTwiR3G1XsboKC0z5mXHs985sFh1EtHUzUlygZyW6QyDOZ/S2LGRYGpApDOMgsjdhHuLyh
MxeJmE69rxJjOYUZUOeUeyjJBo/JD/L9+jxZV+ZxiWv57Xo0uV9rmm+L0dUqgQTye3SM8uyoSD1Y
NHBmpAhoL4GwgOcSltMeERK03fMWJtdU8IRI2Jpa12i1RNGkLGUJuXeQu/biXa8Ip/egUWSccgT/
lKDGVLSNvcT429rPcHccAHAZTrC1nTEQ1s4Ls+0JTt8gIMWLwIPWJg2Q4MkIkxXaX2ELanOyH5qt
Cwg7lw4m7k814KlHVihdP597ADYz2xX4xhEfefwODVvVK8Z6K9Z3wCOu3MPWKYZX0GesKGRWFPdt
ZJAPdUEUd/8nfGi1HJh4p7h0xc1vVDR1TuPw2VxexLOWhIuOQ9t2WU67RyWQxDXcqII2ZuGUqsaJ
CI4zt6z8Zy9x/GBxPDDbeYvcH92vAUl5AxYATPHtEnGod0L/BoKQCtwH2RS3228ZP+2WKo37ztk7
aI+70byAa66QfZQw/YMk9nTtO5GVc3zVMGLyw5pRAMYGgkVpOt385DJAU65Vb9n9D9Oq3PnzRxpQ
jVJXHHZ61AGVaYp0B2VkCSc9d58mFV8mquG84aRTGA5MGfOg8rqzxTDPFOR3pvIAcXrK64JsOeAl
oIPCEaeYCfUlUOvlNK6MG5bfoKUu4pFYgmQl1tgus5GLlVEpJaYw+GCTOtZ5r28mY2zvIn394n/D
oGD1efMu7GHcBtn43Xr9p+qBnDzR2O3g8aXaPW2qNOsGRlQnvdF58W89q7blES+/8QWspKcIc+vO
DUtTDak5U0Kk90dUbadmIyNxT4Z1qcWOt9p9wGoOLFfwkKpKgOs+tE2vGP44TebX7NYNkVlnQdxF
wBUyLbED6zxTgPv6ixQLnfOnhD2gejTgQkW3Ho5NREL/mKiSKUHnrEqO3hk+2uC7lkC1SnzZO/ZV
iwsjZBOEvTHwFG1DVrY7MW1PTU+3iEVcLZNUf3OjC27Upf/MulW15Ea+MuWtzvO0OXrZY6jmEXHT
bYFAyvEc4FQaou8yK4D7tjLOAKYYq1HWV2IgBWVTzGusFtisEVpXkDQEORNkp2/vMrSLFz1Wws1g
fkV19amolDxBVbBzegGg55AgJlE+u7LBigb6uM8hdPlY2Q5wF/DTLCFJoPodpojAIkE9ogNseatr
y2buHA2amQauq9bL8Dn9zBuziqJsQuVUAR71RXg3mNZLFQaN/U5ATyNCsh+YHNzXrc6ViD9VPQ+j
0NG0SCHyJz7pPeKPMkX2Qhzv0Nc9RdNo/4M7zbWiDqKLiK2MMa7vbDmjJdpVbxiRIsY/J3NfkY9q
yx2Wfd5ZL6NEVThXU10/tB2gDez3VRiTm3EEovCUeM8+6gV4bOD2UdLmpUiRYWj70d64N9hRriSE
llM9WxR7KcaphRrvy8CYP5YGy8nAaKchb4Siazzj4riJdV3DxvF7SroOd2sYgjzJbfvUN+9EsgTs
thgDHd/gS0/kjmnLzZ6V59n3wGwsrZ888QKq9iAW+9Kkp98iwK2UluF+DgEW2EAEqn3IExGMWlk4
FajZuo96ThccUwcUa4Ki7IwiIPh8GSMUlGJlBchFiIEzIR4R4M8XSovdbz9L1ONKtfOyppNBQMQh
dO9n1jRpCp5oZRQVDnjaYBkeWQl9IL/dQtGQwIX1L2YR/HyLZjP4xRWtJ0RIeGcLec8o8wmppuA3
NuaLlL6EvFEPqIIAdzRrhuGQV0J2auQGWEB3XXB5QO/WocMEVzoHcFC+bthHF6nbFgYsOQVM7+py
poLYkGU0m7C6qB6scr9MB5jeM1+4O9eFsp8bT8FFyirgPYqfsD92s50XNgNuHLYb5kpYF2+G9wOJ
JvosYmekwEN5WQu5Hi+MOCmrvQ0bTCmVFtCjcSHcWMeQUBovp+LCWli04Y4Ngfa/l/kC37BKv2hH
OlQMuzQIJ8xiFbAvYOvU0cGlATOlZ4aLQv4WDJVG3NOzT0lFBIV9DMcRu1VEgCDGYOobEf9bSObU
K8YAR0YzbiS8wkmhA2a9qk/B1Gn9OKUuDLXomLExJQ1Px+kINCztoX0U9OV3+Meq1XLxMVIT9k9a
AZXSYGaqDAqSoj/v/IY091pn40jN4CLwVPYz0YIZTTvfNUS3y+yZeENt1A961htZ9hDnmB8gMiQE
HdxBrGsIVoOYVjElzAywRQddb3y+5cpTMmMe5mNwuk9VkwWh1nAgEoM3o5je0zayAufut2+lM1YG
lVMdkIZu8LOlyP+7VKhggSZSji2bNTyIug8dbBXOFdzABu2LXgGLshmTEy7LYRRLuYyZX9AFGQRs
YsUc3+mnpn8uLtOtm4PipLb2r5HPx/jZ5WvURyDf8RKemZ7anbIxYxCGgcz7nkg3KR1+5c1U3iGl
OWhxRq9xY4VqLpiFwq/fOyUec5XDZof79Sgn+xEdzqPpBdmyl5dtW0tyAaw4PGkvoOMP3zJRDY9t
2F37apIF7+wXvo9krNx3GR2547G9lk+wQ3XAOXnMw9CW3gprm4VWMkJIAFSEj1CWkqNAiKdLxRq6
LXYjUChj46tnUmF5C8zVbIEfYhXcoaANMcTHmeFKeKr57A8UyigdXrR75EkkCoS48gqcC3jkrxiu
0XUul8LSZhQnqcKDVtpnlbQCD3eDLqu5oCPFjXl6Vz50HvOyb0Ue0IlFSHlsnBjQZBT56qPLkNsc
9YqkQyHCBU7MftSoNvCKPNTExGd6aB0W7E8ZERj/egVVfyWeXfRJrRTgAS9yyxcXXIZijZg/S3Hx
le3MiAHu7A4jM0p+RLK9qTjXlskWKcGrIGZWRDnZqtod9zinxa2M1xav1HoiS0HqlxTWi7URwfJx
79pLkRyOy3Pmy42oK4pWhUPEkhj7S5pV+S6Ps8eK81roc2XEbJvKeb3VryjDI1G7o7kQhyiRwTyJ
mAdbm6b+SBTBGKFAL6yeuPFsy80MnpW+cSFPHQFUUt4oAgGdDvFJJ/Xr0Yg/1tk5MF312b9xWfDN
X38wnlghDfaJ7hZRBiwYBl48/aVcSa3+akPAlIc9+qhK/hTIiO87GMWAQYYju0iup37w7meNOx77
WWpkdiYXQXLDLDFAw8hfxTH66oMAo8ZPPvIaFgLeBwrL43d1OPnOkvQ3Uij8l+gbcpqN8Mw/Fr8a
l73qggnmNIKKoNhpoLKKko9va8vjJu3rGpbmEMphkcrkUI3GYMZUyZnIXM9Js2OXj74+QOPCQEXB
BSy8m8mY7RCynbN72Ths/T0tNDFXi77ihgL7C/bdNAWx8R4n0aZYs+Ii5zOe6aslAcbFq8IlslHi
hR+6nrgxZNdhKCVB/KlNh4+rR0tMPXb1mfUlLE96UXdngQHan2Gh/eUbqFWMjwT8/GxQTegr78Zs
Ggp7um7uV1tSi0RMAvaP06wnVmpVyqXFSlZ1f0S72YTlGCdy3OIdZ4uEcDyu3rzfsrAdf3frpDp3
oAqxD209HINdRP4SM1JY48wYRn2jkgGDqK/RPXC54zvbHoeKgWlHdIyd7Q+0MvRTQ0KjQhvBxl2W
blT/Nvblc3e8sjzcCo4T1NBs6KG3+mbaxlfCi0RJ0N5iS1SK5KPBezD+Cjaw+iIPTwGQXjkudXnR
ynTI2wW6uFigRLCghvzLwoKa8fdReufkF2Wd8fZjH1iWgqyPsnClMGdvEHjLLyDPUyGGPJM08jwS
tAMDYe0BQKVCkRrRUa5V+E25qgiu+plY6qte9jjaEmWfQMix+XHGbZ+0JkaOa9EwbAMVA7gGNCm9
8p2w5ExTwms9NgVpa2sdMtBkBV2qTtoPkir9dkyeEM/DUQfnkqZHvB8EprjX7i/3OQrVEt7bw1RD
8eon2I/sMR4M+gwsY3uK/sLmNJ69IEP4N63J/Xu10e2LtGAiKVulJmKX3feTDx1tbgK+Yq0/GdkT
BtmjN20+C8+55/o+n5ttalbNOcGJdW0QYd2mRfaTUjK4CX6ScOhDG7fALuEJoGzwchxyZf/8SzS0
ii5oQN5iCdHeuowvplZQnopDc2BqzRb+pCeyu6GdcEVfqxVPDGK2Y7wqJuQauKFZJ+xI+rZJbnAO
aKpAOPJfCfdYKSvjntMsuPFaCRqzgsXtNmS8Wm6YP88rOYIFk2LqS2RVEkF9WpDRo09+aGhNEXsO
cyvVDKudnpVhmHy2vGNR99Lucee6OPGQQeYebzTStLKI+wDr+Q23bf9vzGnIdReZHn/W+oJ5GaGC
C6cndjOayPmU+4W36XKxnuolBHo4R2XEpx/WUNae16lrPyc9LENwv6Kl6ZXMIEWE9D/45HTncrz8
Bf4pD+AECmuwKk03PNGUbn7D5n2DpSdcypRCxd18tuOmn1CFFwexcQeE1Ge0crEGfKeIB0hBKNci
tTVdp0LBR9cBFrUO8JVr6NdyS0nzWpQCaKnfIAO+oE6nyziWVEEGTbozljd9ZIJ23UBja25ixD7h
HT5I0KFIP7YUxCo87pBoRUK4qjFjG57QA4Hx0ns9V1wT14O0UCcxHmbRgF2aivgPffGfW9sO3Tbl
F2ywKQ5HwQepjn4j7oSSpLJ3WqoMMKo/3NN+++2g+q1WTakydkvLEYcSrbM8Il87sQS7DbR7dXnY
8dB7dzHPwb3HzEYJEwL4vlwsWPXRfuFdJQ0VePqy+5Cb1ElvkrWeeVoZQPukTcyD268ow4xt0502
pqxaDpMl8QSWBu1vz7c0b8yycJFsD0RXiaARQxhM0FiV0yKd2ToQYHvCLlrccwh0XUGNMPZdW9Hx
aZZ6XMEuHAiD50CoWXK6sCcGAwHOaW0Vxuo8MJsF8FU6CRGQDPW1Kk+s7+SwUAPb8YBEXS2RBn0v
TC5TRl37ucHW2eohfbovYjaM8foUzotnOmUkAK4NLCRMevLunvZEAHBTQvJc5YHIfrJPSmWDw2Yz
SdFqFDCixYPf/lV5XMPF9Ctkm6VeULqjqM04lODYACZe9H/JuyucubIQSnAmdBXCuLASIXWha9Zu
G8rmBfsQw1EOHmlXWNdgzqBVsPdmlEjh/I7fsgi18A1Rl++4fQlLAPUCPFdABYkBXwaZz4JUcra5
2WdqbR/vGXBsyJrYpCrb4U3kkcWqFzV1Dg2Mps2D7X6I8oRDjES4Fh6Tm4Brw3+Zm9DOenrsBEUC
qqXAhuJLA2eg6e6yuH5dA6dWwkgvOcXRo+399QcVYqJ0BgwA2gbC+1sy3SOt+Qf4PcCG67X8uK3m
ErIJXvkIPyPGk24/Mz0wZJptDhthdCOHebcOx5R6xSUPk1yGimpqIAj8LxXlI6fwFT/khPBuT6Rr
x0db1tZtzyRD/HOKa+wUyCAdw/s5COZI2SLVqtIJRqGNFG6vLxYMuikcC45AbXGUTjNYgv2yXBXO
KODpEEYvsyVsYQp0ehOU/CoSHxqheORf1thZXJgpKH1HkHA9QkjsZCSS/o09NQjoNJVQqM8T0DFa
X+xl3Xalt2elIwEAI9GYMe4VmJaUBhbWbEWDLFDFc4FgfbsqvQ9JPL23gQKhP98CKZS4G7T1Kmdn
EThiu+NDi662rb4a7GueBEpHz5jsayOtTHDJPT99kcU1IBgvRnpkfdwbNOavSg7LQ7XxjuZcSTcL
fU44NeiqzVPw0JFqmFkBB43iA3dnFADB9uq6P5O4PPSqOFWFB1YE7NggiFewzvzwfeFIODRjRFHr
fn1BOVP2yLnypzlqPAd8ynrlQCDvXXYbFW/cvsDU9KvMP6efKjgYoPpcs4DNqo+q6a42lczIXJNu
d9rZGa5z4NCcoUXMxAStnG4dpNxfeQJiWZu38+N/m1oBmkRe+ns30Hg/IPF19A9giW2tt8B6Iqft
hiUtTMUmV9oKUPs0OexhlJJi7kHCLKTkMr95EbtLyK5RIlXVt0KMgybEEEp714Ts11AADp/utAtv
eH0JPWpnglyvU0q+PNOVxPQtI/0/IRqSTGm8DYRC7AGNLQgHttsnWKlNSx/BLsvelyqIWwDGuntg
Ay13TSkZOt44jEaHSrBBNj1P9COiJjNiAXgO7DSOkYpdhG0I/dP0ehWxEHNsOAOI3jxx77ccZg+Q
NQXPdCZPj0hTzXWYuu4wFnlhK0s240GMBMDhtfSUEzpyCyrppX31DfpoCmipJYsz75RW2EkkZqfi
Qzf5ugN86/e9KvH1Dsc6k8XOXPkjdb4iu+0GQcoR1YgMXkcUWjxhgaXRMCW/n9AISE0bJnisCMmv
oz8eOd8XaaEWeSu6TeRSlI3b1nzGG5vhyBSM3OhtFzSknlEJrpXAjrB+Ejj04aaQGWZyo3gYI//x
6gg+wW3JTygn1DO/aS5eL7oiKgkzfy/n2zC4s8fJ3Lmad7GIrZx77LHbZArsCr+EMXLOCBJL/STm
uT6fSAnmqHiGHiF3TjHId2UWrTHpg/M5zRrhvSHKhL/PDHfEgvSCzmy0CUQPfYxKnzZvWeCMuvJx
FnkLlvLfYBWL8Jq+mrDXVrc4hLl1BkuUOL1XaOdyAcqXH6C7P1d3NRmtkfSZoYURX1Oa8t/iVEWT
7lbq1obifKtyyYsZRDUi9sqGPUIQb1SIwBW08YV2BTHwXNS0LZDiJ9zpbBc8ZrkdRauKdJZQu+9r
dSsw47g2rpWBf19bQhp0/A0kXTmsw5XBl+evlLgXnLS7b7GEY6PY6pUyByXeisHU5HBG9gTx4Izr
jGO3+6hE7VY79YH5mosp1yHmHZDkM5K3fEH03ifff28W7EB+0H/nm8rD4ek0Y5SpPS9IipMKoU7a
8h9tvTGu1YAxufyhL45VGS1Yl4p+E20BZTYlhKDd514EaFXcx9HuvzTRl98DwFnKz/JICy3y5Ogo
3eaKG9Y8J6vsrke2D1Vs504fulGLySGTQkKvB9GGiwDnaKSApKZU9tFKJQI0v3cZ6KVx4RWP8vOy
TQvbUkJ2x09tFlbrAExtX/qEXF/9rv/7xJPFT8G40+/RrHx4df9vJrGXXYui3122uF6giBrG3TT9
pqdYL2gA/VYReQ0E1ydFPFApwvCIKIhoq5jFGTASXEKtanQEykY36xqIeZyICf3upPD0sUt6Dc8v
1ERLZ3NXXTEKfBRow5YtYG/AMIeL9owvGuAHGVHYuDNExHl/M2xw0CPwQ9fawqmWgh6zm+ZySPJp
LTriJuEUKWh60pxGKGbaAQq+jx1UtcEUOXRlCX7aXlNMBVZYMl7Ijb9FS3m0+rkQ5/sLPthYdTQO
BoGzxa3skOsMq9VG9h+mR3MUfiLvbtJOHFJVJu74P3i0hTTXPLT5H20nyBgic3Ka3In9T8hzFp8/
KWGzdQ7c0vcnV84bAjlPZuL5CzTeuFwccsZCY1T6aazoL33IUcLHUFZqi5A53RdAkdcWYtgpDbeL
dRoK2Q18NqJG+ei9t8uaMpqHMF0RwkfaqobZB1w5Bc1JHtkIAF9emnah+ynuLU9SOxebRK17Hctt
cy8/nOLFR9fE0zaa1ES6DfOIt2I3va21tX0Otf3ezvm7LW+eeMoVDw8A8cH1nbWv+N8KhSaRVHDw
F0dFG4tNIc5YMezEM4LPnoRBeNqk5Dx5RtYJe0hKIV5/bFY7ZwBQHi4fJI3VG1P9aNAJjnwtFlEi
Smo1gxokp9r9ANkZyd2Ue8AuJMmlMBcGUlfcle+yudmfb7NeD1MfFXa28HzGPt6IRHiNEaylbiuo
h50QTpjjXvSL/blnHalsJl7bVqmq6apBtV7JED9ZV4vJOgRT6YtVzzw7KZ6L5ksJsufJm+4Rz/i1
2KGch9IM3qz4eBkxZnoqmt/CQH6H1UWqifG0Qkwqrp2rRllfay/6QbAMYn5NiIzIWaOF5dFvxJ1B
zacH8wwEIxhkQDaZu3N2SJ95AoWc5iNcQQUdNebtW7SEcJt8Rk6XmjPhgRiiWuYcVuWN9dIv7o4v
zTMxchgwxwF0Pr1dY/3iSn37IXGkLsSvW65QOfDbWL0Mp8GrIhhUWFFJR+/sajIWyrTb+kM/Wguu
Z9OSsyozqWM/diVBDAV3p4F7qmXIbKg8fMw0SyXuCUAjc9RdVh1PY3JAwX6ssM/FzI/eLLPQDWRu
sJiUagasjMTU5OsN/M2nrK1QM+1OQnEspZrfQg7Di54EIinx6tR3fxJWCdbsOKmVu/c00FULylSt
gCCmJjT+bNwIqpFPANEruKKh3gdhhwTmcsjBXYm84UBpxf+UE/iRU288YXY3WAfkr1w9P1AlwxLg
nUQH5+8nHF9P3n4ZPqUJRNqIr4+hBGiE+/blozN7IrOji1DHEfZYvxq75p0xhcwj5maF1zNySJi6
iJzbPIVfm4iT70IXChHuynMPKyELEjXDY4tn5ntsST78wIXluADV6Of3GO/95CU2NAIaR6XpGenz
QRy0wF2cX7V+SsrLCb0hqiGRMlHZ/yL8BzSuAbtvSO9NiuXANC7PUegL5Mr2wZ274bgftH40TNsU
S5FDqLPrTJfxU7nDL/fpzVq6tBBp3wyX6olSeiXIe2AuHn+eftvv2TBQnhJoOVrzwuXaOglacTHw
NUghKw8vGDUuk9U0Jc0d4ngn495nlCtxK9QasKqpHBtzjPe6djGGxOtjbf/8KFfvXS4T7CfD9m+r
4kzPFrdaZjO+zBwJEH8XlAVAfP9v/z8b90xYdJGIFG6+S5BmDZpBbmIQ+EmV9DfqWsty5DAdpBnd
Qc7TkKwZDrPOdsreZBSCf+WMi+Xdsla4a4xw+3Hgd9qGY+3gFHtxfad4GCh5u/6JzT/rT08mWdCA
lsXxmVdEprN2NPYOXEnOhXCHJOxsFV661RWzmOhncpSDWSwir5fuOw6ZxdEEHwl8Yh60fPyPxy0M
O9GwlUr4UyHjevAS7p3rQNKziP974krYFnPYYhl/eoy6KVWjXknRRy/dYNX3LjBhiuzEHysR594E
JOyet3tGrbaPrzKAsrIwN6RMmPkhFqXjVwKSiRhLqAs21YwBm4oljTRDKPmP4tlhKmDsrZAaJAOd
FIgBu45p/L4gizpviOgFM7yoOsn4L6w9n981ObQyp5Djq7zQEt2OAYcQBiTe9qZm/4oxNVhEemNO
7yKlUmYpKY2kJqU6WPhkV8gtv7VFRlVnYO6aa+uKOVq34q5MqZ81w+RKSEg5TmUoLAyONfeSYuAe
/SguoKNUeROwxAaTggxTVxmUMrMLyGnADmDRoLSj1pjSGTklHjqII2vr+Gov74I7MyOeVwssPq2R
nU+J7xVb8MSWzM8wiwIa8qAVmqUYsD+MKoa6SfcD6gDF1H4aCSmeeb/eY9dDnA0ODAkSF8jaOhdl
OU0gGB2OnYyerNg3Hf1KDw4K9XwnPwSrlyZj3GBXyX0zg5OqUsl4vBmEGQmkeFubdJOTBHDLm67S
pdlyNX0uYBgenqGLmIYPUUT2//Jdt20Esuqqy4yJw3lnS1CI/jraPJ+FtD1x7S8kxoaKSICeXPL7
t9J9eo48D8w736KJsbcM64wcF9sHfrED5bs4gxQQQusTDswSkqLSFytN7mtInn5A5Nsr8JmA3zHP
zXhBpHpseY5fBpjXJRC6fw1ipOxfQOoin0jwB3WsUpcKtRZhVU6ZKYewMIBQvaYjNG3Fy3lfUzDe
UrawwkDa0/IqknN89sD8B70PwJbmrBRCDjASqrf70OKOIuZAG9V00PhOBfQkyCTLa+mgUILTXlx/
R19U6zmKGJw+0gW5sll1iJTPDW8hNk9rr5BU0MdY/4WzfU1bsIVKTjrCWOv9SpC3Xe2dUhDlSC+n
DGhXkdnz5sr39LrPWyG1PATd7FYvGUllnECswPvOCrgC7fv3MQAEDibMhitmWXwBad91sbAm7v4d
aE0F7IEjPwrGAhmXSmi99gCmzAAFDdhgfJteIw1OVAqenCMM6+g+8xyT05TIPJjrf2o01G14O8Hl
SxTzMR42Mq8PWnoLb9hz1CWI2HCUkF/735aEJ8bE8ybt5FUIotOnv8WYgoRRe4e3T1IYcS9WLNtL
Mc5t5DCY+Gut+orH5783CUTcy6gIo3Nr40IAeQmu0XgmEcmfrDGl5sQ5M6U+Wv3VBMlD5nCfS7PS
NQtmCBWes83zPq1ZC7YwIP43htePXjxoGpyXQdf2/kmK9+x9dKpd7GhFOnCewe28yfZI4ctqhuOf
Sfk13OXmQIy7PlxnM9elO5rUWrJ/L6ZK6OBIt8EAFO2Np1hxO3B76w2zbZPKRFfhW/uX+lV/LaGG
0eyzwZWcvfgwWThZpEwJjToCXOhvRR8YvNC7P2qB265HxADx+Eab1Fve2cbs5GO6o0SSD0LogZFR
holvf9syivuzFUl4bahhLQZEcFu7ToGtICpw5RMM0BWQE1XNbQL3CgmXGeUTvJsiVc/jSD1tjJc+
asHDIcB0Kk1YrXl4Jec+gal5nEHFrTTXGEANkFoEWOD6QfFUp2HV8lpiESetLK3EEEezWMoIvuiJ
qbNSFZS7oL6HoiwPtNo0yi78G9D9DnNsW80nA7rdQj0XzSHmLkTIpRFzEar5cMbiZU/5YpKMs5jE
LsRxOakPcQHyTAx3ThIltwLUFO/8OqyRn7CIX20vCB+1ZZb1KgX4JR+GESt8aJK4z4IqxtOmlR6l
+IUuFFdsE0pzjLaelq9sJBT98LERcEfaoOJ/7NbCRzLyRRl9bjZh+RWL+cAPPwej0Mm3yv3medaO
o1ie3K25RqFUb1Fj5DMGIDy7TSmTyotZnhGQVY6H0YPRz+b7c4lHTkFTkUwoZvH2PFiWtBogEPq6
4rp7vWdI8gsym8PJgq0kneWt8jfp0w4l1PLZkWAb5x7B4ir8ccde1S9nR+rcEcRHrgK6U0Mhms17
LH/Z3wMHgnHu98WKD3Y7Vcq4ORVwUj2EQ5JVSO9HXVDCn/Kl2KYvNT2+W5R1Hw2PEl0R5KVeOMDY
gCKp2khtLQOYieazLIZFseeFWXClW7mMOo5QPdr4KkV/RzoFjrA/TERTpQ/pRC2zJlyriebE4wxR
RnPMufO7BNkYv0GJPrXO9cDiFLj7EsoOt1MIb9c6FNYNZtb5/8xTHeZGq//IzzzDWdDLbb4JDMmi
9DDbVVA0A1AsRr8elQE1hb9ce8LN4yrhrWI/PbOWEGUFmqTcbQ6QMBNptdlf8JXIVQHGvf9qVP+3
YOLgOQxAyMYQilWYTSXjQYSMygQfcKppy0Fs8CtPV575qI5fbopMexQvJvbxEhgkhiiSIZazVxWS
/yH2LkJhL/dA/Lrq1+CeJLjXEcb/ZlGEzKSRq78Kuk+T4AwaVDd5QoDJQ1kUSDPVITEehWbpI7I5
pbD8XXx46tqLEeoWcb1hg8O0s05QSRKAAbsLpw5fSAuPc6yRRengyvkr7oh1VtRu30vaAxSIZcg1
1Zdrn5vLNzbZ5QVk338D6XxFnig8y4vLX6IG5j+mPif7hxLs6TZ0ciKJlwhhsgwvXeEoMf8jXY/d
PWWcVybyNckc39gWUqBAPV+/DGrUA2RzGewC20wmuU8e2EcBwFBkvb4V+7JaZWvhhyhIzvCFFE1U
yWY7kPxQicw/84Gh9Q/XR3oQzBo+CokaaweuhPgD/9VTN4CfumCACXwpuwonaDi/VGZwB3PT26LE
SpYDzY+h9rxLnoxpjHiDxaJLotrEpbIn8yvBJf0J7V6GlW5rEV6hiYwNt66Y547CsDgDP8MKNF1s
Z9PQWZJpT9fRSxrvcRg55jsNTDydcrGA0HBbfqMLkfgHj2s23u6LszD31V5vk/hnmKvI2W4sE3XA
/ArU3cphhcZpbtThMfdnQ04e8+R8Py8BaS9QXKT02yNKziPe3Y/8LRvP1WkLJI4M/p8a+GWEE8nZ
e/gdb7ZjePHlcjXEEgSZjcvF0/9qYRmjVBaoEuaoZEWgWdKKFGvcS/XxShTMKQqnnYVJiMX8d+n6
W7Y5omlNZ6CZrWSEWS7YiUdQhk131bMiitkQpPajgynE/pglk1nYlA7uV75pAYAzArWobN/IhDR1
qnhdoU8JalnyN6i+7gJpwnPgvzRpYRMheK1wnSw1igpujUNa4GlV1FKHplkz/jO6LaVp4GENiTMW
znbJg/kDueYiB/FCy4M7pPdQexlJGZaoEdo3q8/CdyxSjEMdQYVVagPieb80C9dYcLKIB1jMeKdy
PGeHhk9dy4f8AnLjVKMamnU/YjEA5q12FyXDRjdQ9fOgOJe6QjkaY+xrCAGM8/RBSKwjIlfoqaBO
EAakzj9/8cO1tTfWEEIyoqzdJPBvI4xrun2oVGZNAMJqfOEH7VcGMbtIRvdMFL756KhHfdzIdWnl
YTzSQ/p8oXtkvES9pSt5a31wWh0ViJXgX1XSpTqXPEkGThyB45N9BUhDZ3EXIukB98UxI7Ld8Ei1
rcN4swoiNCrRIWpsc09tnNv8OI39s9srqd0DCioHQNiHbVq5JQptzn0E0oz5EsviIl+j5BDmS0a4
4uli6J736atDGoXS7n1xeNFEgGM6EP4zeZ5V8bb2g7q+tZWSOM7f9TgOlbhMOe745jOCm2CEwZDp
zlvsgyJLdIeU7TB3KrrCumWFn0T6oKl5hg/7jNXOx/Auu4mF4HMAytmndY8+vCpNrvQnRyavpXqS
QWu2PjP+v2kNJ4krFalCnq7qf0+5B6d80KTbZkOyf6UTQfUsYtAB+0TFWT4WgJWeYRIDIB2weFlP
VgbULgvXGzhoToKXlzxb6pra/PfZt7UIc1ahvj3xyk2wtp0LmZaZ3FMghLrH/C1EAkW9sEcDHV8o
ibu/skKMIcWHSRVPQOzNYP8m5ckuOEzYlnkwNktAEpFPUgyRYMnArIsI3HGAJmPJTpIZYQMs4Gex
3rzf7AFU8eWLUuguXFgp28FiuPik5jcFqaDv1HRsXJK55N7UX0ge3CoH/kJiYXqzSeonS+KvoXAR
Li73ABO4qBBfkcPA+pSPTWOM8YVyyUI0L0yre+Ize/NXn46oDFBYCtB52qAyMBxjUdgP7zodGq7g
PyJnJMZK6JPHEqSLqQ0KCwrgRixT1rbP2ZdeMdUMX0uAO3vE5EEoRjnX+KtmjIFKGDt9JTHHvIoa
pghZUi9TNpf92MOzbfeTtCWcIDzJVoCr14RLW80XDWX4ndH1RVaxOpF0VextJAnKwQdJgmoEE7Ll
9qLQPljwS3X792wuEQqapsegMlpsloJIuBhA8YJdw4c+ST9rM+yw95O4yk+2Ff0cy3yJ6kdpAgVX
P5hAbZe+MiB33HmTiXBsr0a+nwiLi5wCh01xN6QdEB93tScny8w5TxVmbSwASsK2wevwaPMY93Q+
Wc6sLT3fDMQA5lJwKAtoWKdPti0J4mBGv6o+OUDwE/yCs1jHme74j6/0YDh2gCT9q84HF3ZNlB0J
IeIDy6s6SJMyhQjIfagK2xPWf+mMPYy2PvgjMx9EF/o7l4Eiy636DhWGDL5ZdhAJin355cyHifPP
vaqzBkjJnn6vLbB5H1DluUoILyJAaGFp+TkUSIbj+CwNLV8K0h/ZdTeJIobYogU5p5iXCQagExTo
Sg2iN+tCsUysXAAxY7n3nQqmWlMf9ZbKp4e/N325Vcoklg1LnUsMmK13heeNYXoxenGCHbAK/j4O
g2laYA5VAk0hU69Y9+tIio1215BiNJtVadiVzBBxaVPTbUJzmOTfoAE5PPCUqJUvu0OBSIdSYxV3
qxWAkWMDZoMyleaL9fFk+3p22ea3oFaBr9ZZUpMBEPbPGVvUabX2yhHIh8Xhj9j6VvIZdJobbCjN
fCLYkTfeyy0AnRAkEX/risIcQibkSM8LwZJ9mO1zfq4RxUI7fjPTTaSiSSh0G/KlMvfMkrlbSPpn
YqvFxPzBQuJIVQ45iB+SvES5wxWhrDH1PhI4yzHYnUE/LvrqUqVKH/lYnmAM4nqNNgEn3FWXyM1s
6LRtO+vZtQ6ZajWj4UpQuI4s0aiVA4XRFTxU4n8CG4gbvYB3xhfSHt1iCbvmNUICoMKaE6ZMrbW0
HvEvpYWqLZtHJ7FiO8GE7kcrCmJF7Sl8wIpa/RFJiargYeDagOQIwkcwtHk1CxC97nvfRYXvjBaG
SnhaxkCy+b3UREs67dBpnKiYZ7gx+nNaVYqOn49pCVYdfZBBk7TEYpJHKD10i0dkZ1VtCrOFKY7I
qu9HW+yiyMZ7jvxmLLtQ3Uli63LHBSz52dH17kZD3r9Uogm3ZzpEBTmn3Gf0y0KU4NKsYqQUZqN/
QePQCJ+rgSZLI2Qrr6lo4MEnjmGRFfb4RpjbfdRhHNBhiwFg7XBQ5StEZWchU05GM7YDbKbv2jjZ
c5EYtY9KKBhSKP6PiPNCcS5xDj3+ElpjI2NxiseMVNcF50j2IOjGVwqBG8zeKz8ib4l1gYTyNAkt
49jJGAnjFK+C5jKM+qzmnxE7CcfQF7Kn9JoRZRHSNim0RQDrfJ+ugaS1gubZpk9GqbpkEyTdm5FD
ARnagCxsK8LW44l5yZ+4KIZLzum401Jnujhl0pkFdGxyI5T18xL5qLLFIQqFjLu9Uj5wzje3Gi0g
7Cz95LKHX8to2MlyjSnbK2wL3Pj63f25aWphEL3tAXMB+XfHCXEEBfoP2rVGDKhSIjUGyf647vDJ
+VlOz6PT2vYPNlRbgAQXL6a5UTxOmCysIBLkFIElGBfIZ3N97XLGdaFOLhCo/3HHw77kSLwT2r0i
mbD1aw7fDXpkjRqJejpALr1nIXaJVGlH2Pa9r1SQ0g5ZJ/jtWd8AyvuhpgOzjfUfsCjcM7ZjZzdy
lgC4KXd4nVAbV2q6D3DTh8QIZxo/JZNxOHZ/+AfqqzzG98ng0ZDG4C37IOu6vwWiYREvQTJ8S8V1
CjOKt8UMYVlKdOMNPDS+l8d1QPWaIcAZOAeMbc4k+Ujhvwq7WrCHHw1c5ZEtD+NcjRDNKpe/mpHN
zh422NOJvr7fmXDKk3obMqDEibUcww9OXyiJL7OUke9Sl+XN4oEk8LqNS0sHLZOawZzFjfuk7UuM
Gsj40brPf60FkNheYaXPLMnXSGt+BB5Fgx835tAmGY9jNx7hewe21ONTPCsyvmTNdxX/sjRsRL1I
3q5PjzrapkRfIfZCznKtgtv4ykib6K0bpLAMUbsl7pZdD07NwgS5tSWXpd8QrqoYMd8WvJeu50an
6tfv5PxtZ5wFHCKk/FrMxFP0Sc/IfwzOlsFZ2m8BREF5TziixedMvuRCOL9FMP7lKPors2waW3uk
px1DPqQF681cqeP0R4b715+rGfdV2VzU0atFhPLb7LkRgQE4ZDgzvINZ3ZEJUTYu3KQESTp/7TB9
ClNNymIZ6UFJ9VCADcXe9sSadDiAuSfdMfWL4SyGTlrGvOON2Q6kzMM5AOcVjRsF4mFF++ZfSZ1C
HbebsdAxVNRrFE772o8zO16Z7AbtuwHXvv3nJPVxhzezWrSTv456zP0Pf3Eb8UZSW95dwM0joU80
IS27gpIztDNnut9nlyp+sEMVt76GMmKoDraG/UZiLwetSAmyAnKoRiORB994/fgd0pC6DSaHZ1eP
tJXy+Zwd7Ae0D5O41qN17GnYqShdamEVgPP9WHOHlGP3b0rbkflFB9sN4pSKHuoXyv1CYclCt1KP
Em98Q1I+5Aw/b3c96RLcJbyj8jMpbZC2U4KFVv+ysElBPrP8lmK6K8FsUaUfjSlBiQrp2TeFzbld
La5zONsLc0bqnPlt4AzLfvgYK/pFTP3vs8ccjspAZv8ySzz4Elw2uDGUjVZAIZwKYqxQLW0ZLVKS
EQ31lZqZXUli2VZiA7284xKTbO68LzWAxkIFVq+zV9EF19GZtg9wySkJV5hOjIL6PYaztgCnyKpC
yv2wf0QK2Oq4LTrTQEQd1e395PtilGR1GgTeLb22RfPUEpH2ljf0+p1q8BLL4RlK/+Dvo02LBVc0
2HIL+FMRsqLFIz1cZ0wEaDCZfQLvNhWJ1ElrMQ3mXbbcD82MheDBdHVrlYRtWaPOBOnl4erskA7Q
pdE7zMGh6gNiGL5H5YvFypcWIPXKDxz01FlFt/mILc/H9M9g+XD66GW08t05BEL+okL8L3gXI8lg
wzUwjinSqG+i9L/Ow8iU64Clt+vwOvX4SRFhwWCSeRsoVGt9/AFOOdZh+/phpOUVVn0Ie3YBONCd
hAq7Yf0HNxHM6kPy95HWeiR3Bt/qt+cJXEY9G6z4aE5bAAx6y8tDfKUbL+4WOo9/XtjilWKRZTDY
Hpl+yNNbcmQec7qqAFo5MKvnv/cum6alh3o1Mw5395H/XN940tK4ixGeyjOsmqn4x4xkmYq+T/Ct
ZBD8dQrw4inRblo3jx+hAvEsoc4Ci1hWvd2HBVfR561kLPvkKR3MQaQmNAJ5fi3yGkRbGBu9Jy+B
Jz00c6R5BMc4mSmGo2pDjXmYbPsHsxjfYho8EikWX137SlDuPsuOtOsOe02THbzGZ1TnMKuCb2EJ
81BIUYuLpB+x1zfeb2VZxdK0dfhAJCAmrcfQ5f5MpzZDliE28xUuEhgaMqsmNJJNX82Y+kTgo4Ss
6EnpK7h9xfarGvGZ+dwXgf4aoGEwSGtmeJy6ChmDOPEchiayMuKQNqbRavRPwyoVIwdWknpSjEDW
qk/fq9zcw/OJUNYFGeN2Ld9fQvtltBVKFQsEHmAW4xKuJ+Z32zamPaCs45gWg3E1gGOcBivCVOpE
qdzUVdoPNnCX2IBzLq+bHmO3kEqy7q38i7InrJJQ8xtkRPBA+V8WSbsGfj+5+wszaqLDRiYB54LO
5LNat64QYS5wqgCgLxTtNdMlT+d91wz9QhmW4fOsLCKXFnXr2wgLuCxVND6qj5JZACW1vC855Hvj
SyVSBBHcxRDdalgmY8YZkKs+Ar0lifcvfaggfazHcfngsUtUl7c7cmGsgpaY54H/KJ8vq83LX864
zcb1UjxIQBX7a+lrMkA8sH3NgroEFw1Pf3vv+vbRzGD3G6/IEOGniDsZzO930wkJ8+syzTUmig5C
Y7fxB4cdGLOjqpSjvFxTE6C7VgHqqt1hx+QnlU/6V/oJvd7qdhdaTYJsT+UVIEw/hSMm+gAYL3Z7
W6Rw18gv/dFIaNFRr3g0SL/ZZhckmZ3wKAv3HjezLDxApvjTC8Q+82Li+QzgmRNg3mxyjVulAfcJ
rMtHlfAThL6nna1aP/U7qPr1DYeYGwgU4DWk9ddohRqRywq4Xa3yXwyxX9xEgG0nN8+mzGG265us
d8sWN2u9Ok5wEiLz6AIhco2c7zssQGaVE5cd0DgL9dwzVdqepqzuKZ/N/EUH5krdhLTys6mw6TOs
rTvRepphBzokXaCsn2T+X2odk0d+LUlyELZfoVmehY7RGLC5V43B5ghlkKkCFLAJez45hn81B29i
q+GqbtG/L5qgTSUk4CF1Frsxv/H59vEr1lvcXNE63uUMrnifmp0FE8aq3ZiJlGjDFyu0mdh5v/9P
hqNi6CgAdr5CDPH7CGH4HayEFtTmiuJzg5UAxYUPff7bgkuc5T177hkNjECjySWTvJHH11RPkAex
3Z7M2ha1EH6rrgFe8GXGUPTMF3Vm41ZlJm32N3OP/pBJPqtZ8BV+Blas48kqw+Ha8/GtxhXkW5KL
t0tZdXYF2ROozbTwHEFGZGOl6evSr9eY9Dkwm5KV1gzy53pPkGx8J8G/DtMguBDnTWXyoE98bA7B
s3jEg52lzP8kM7eqa6+BdVZG1Eq8JeR2CcdCwVhIk7UnM+5Urm8pNu0Veozh/bd200T2YfeeZmM2
ZNX/sdB7I5iUnRM4PqljVTZBnYbg5aqRuKCBdFh4X+ZOfBBrxAJB0y04qDF6GexcHF+WHwRXcT/i
xPH0JtMlmwF+zdkMCq1vjnsM2I+9LdfvHIgZdau6v80IOMtLQRm9XvgEu9eo7jVOX4s9A8Wwedij
f7lQEcrVie7BGIfbx9Gd53Y+oilUlQwz54YFm+cxZes2HORzUwFunmCWFmA6xxEdCCaXW0m6VfQL
B7G+Hmc1S7kZe3H8+MGdz2SsIRvAPhULFlXVHxFVguXcvJEAMmgesVBfdEre4TNZjL91PLPQKUC0
Qhpm1c2UFTBpeDs0F0IDfIJs86nZIZdxP2cTp/yqDght3ilBYnuKymoRrZdauxOOYUaJ4flzcAfg
NeNtwt1qBhBYcibEFJ0OknjiAaQUn2i6ZUtoqUNTegJJB0CiFheeAeoytqEXcOEJUUwKRkfDGIV7
PUULcn3932FNQimkn+SJv6+7FxjBMcFx130p71s4i7gos3/j5vfQa+MzJ5aiZrRf/JNpzniqIBzx
3HJvNP0wSfZUOyEEGOMRWGbVnH6DicR8TRhNwjyMjXlddJmE2f4w53UeFDUU5gyC+f6D775matkz
Ap/UGDs0T7C63nFX9NneRL2MV9KFx1QN4/UhgmK3ovLxX4D0b9w8YlksEAwP/unqC0bo1XSkgF++
TSrXnTUk6O4XQMFxLkgppJIXNXo6TvPcMI3NEYW2/ASTRS33vJJTHyzP8SBIgVaQs69fedMm5r0J
IwRja1jtyUug+fmkPmaCjYV5GU1zxWrUv91ZbEMmnHbSLpALAex9borDem9LsFLRFW4ASA/Tmw/g
lj15KnfNXVOCbASGzznl/3NTMRTl0y7HaywJU1WVXrk2anE+NRNGJvGDUbGiiVF2RPHxZ+9Djlm0
m/TAkIv2MVxvoVCr218xuY3lXFETvcT3XVR4LXVpElgX1/qYs65KjBpdtKd+wizCtvZmnN3aLI0u
HOtLdVNm8iR850CCKW2mtmsfHlvtoZhvTrgpd4fdDqouLCN4dGrZW9Hg2rJhVtIQF1yFhdT7LQ00
xLvZ627zuP7fuYMelfCXis+yp488bigkRzuYSmxCYT7qGBd9dTkGXMlfKaCbjDsxJGU5lOTSpUzz
KOaAXD8pjhGhenpdX73d2irISC5FLoXpxjJuZKN3O2RtUYBPzjpt2vaAQM7mkX3K9q88RnE0qE6p
XGrM9uUdksj9pFWWMvH67Try9ksPoonGaOJjjUliQlkkAxKiGY5aGzmDJsxJykq2rmoAIteVX05y
wMkFzNtvuRDwML16LwdqPb62QiRVX31LNYxZZzs5PW4rUC5lPtindmuG1oixeKQgmsMWaZfr39ki
BuYMeXJAWfsBfkU/2kTeyhZ46sFhXsvgbI/TyRu9wBNJqzKisb+OJWx7MR8SBng763O4oqx+p8A9
XriRGty1gqqBatcyqwYiZGXueOffJtm3+4oM8LmgkvEZM5zEX3lcWwT5bZsIJWNG48DAFPoeMsWa
JWFlTvYLTePnR4oMAfx4A/H2yTREAdspUQKGddTdUIIB6KhbkSAhwrOpj9I+ZjhgOsywntYkX6sa
oKnrsvFbaH/LEGF6U9eaYp2CGmOiA2n0D1ZZwZ83R3bTQHkrg2nCczBCj8OTv7BPvcHmk7qk0mp7
0+Bz+39AEq/h73qQ6AuUXnWU8WJa6ctDJil+CUQ2LdGVFSdfrWN3ar3uXI30jEGoABWmVMVARZ28
HggTSaqWTG1YfpiOtfsJf3u6VuJg/ofYciGH9m1+4DzCpzo7/N1aADX8XcPPQP/4c69GMJDYY31V
6+659VzO0SEM46Vvp9/re/L/N23PG7F6OrNTznDzKY0ZGxepRx6SXfKq9MQUPlYUCb2G7wu25Owr
B+Jkwjn0MVN9KPF7uzrjP5VA4tvWMd1wFrB9tdcnPOTQupMVv2ka2TD+ndhM6sSxjRZDEvpWfGB9
HO3jXtqqgm7VNDNgQFhZ5TxhnanqeAM3gmCGVh3/app9K3NHTp4y+mF31ddbxBFPf7th1jb246mR
Bfwc79g0zHP4jkEbA7/8c3fq3MhOa2DQwHAvu0EHtbpeXHlm9by4JugZG8P9cyUdhzkM+WhNgMz1
tCSeKC8SjaFi70bqJnLITZas0kMlqyEW8wGV3g7ByxdAYhQ6XpUMDnA34I9TayiJDsG1e+9PgHY0
0MW3PCyADncIxc3E3dun8infRM/+mvklRPQgaoVXG64fYGwcZoau2t403YN0YpUbWsuqdeG7y1ta
lWcGbccnY2SWpqq39jK358Pi/wdSqmA95JRX7ln6MFKe6ABWO8dYUZLIp4DjdZ5mOvdPSrrMBqJ0
ecNB+vLaT7coTJYeNzAf98LEp9DZVwGiX/NZiEqsp7AfaF8QkmviRz+gLp8BcHciBf9snaabdvUC
X4+nH342XQtZlkcjgvt2uQUP0mo6phQ9NglZt6+ettyqgrdIknpP8BqW3jbpioaMawyPM/g2dZNO
6q5W6+JZz4WTo5uWWfPAQ23NURFA4kxM1tkwwCBT21tVCWrPT2sIU7hfFMHHMFKOAsA/aXHVIZvc
EOVJSvuE5k3Ghqb3xbfSYv8Bm9wm8kN0+Scajl7RkITNvXLXQJvJVHBL+W/dzXFWvipjT+UPYv3Y
Bh7WbcM4wDvnpwCKduCoVTULqalWct6sSWkVlWkwnk2gyIr8JRsYaQo/Gg7klQzb7W1hr7ZtE7X4
0SgYf3IeyfQ7fbnvPXfQEwmr3jO3MrZPVeRKbQfNxN6R3fs9Lv6FNBFyNXQuuoeGdVZxshd0Zj/S
vacapow3oEw/a+j29QHhFrH4clhu3FlntV2l+KKMc/2uhhtT01TGQFfgRWuxzi9Wu0iFaPJgwHF1
qYlqFUBLqeiiKI3TVv6dbsnw/c2ZW2S8NSz0D52N+2gF4KdxTufAX92cN16X/vnSofI6gmAaHdJK
ikKmSauxpsAje+eF5kKHtnnoXwcnera0qJ+9DokaRv1dtXlQAsEb1C34GzSM66ReyvVGRjfFQrUn
jznCgR1bY00ga85ZTHFEcnajolsa6XyWeWZFGImckCIn62MYKvaV7zg9cAvRdC5Iamg15AfoGpe6
dhoD+v6WwjaWAgPP7snIm2Z56TWpQsm1JXSrYZYjNvks0fr3CxeYGnMd4J/xKOm/Fz8jYiW2q/cU
e8WiOYAUz45WOk2mG6J+C4k+YFi/mr5rpuKV6Z/UmXTn6GALJ5vhn+okAMp/X60g5A70Cb6x4DDI
U+cfhgWThJkmpwj2ftBUpk7gdUxqSwgYqSPkCggNS02aFlGQx0p9xhfoXm61smy/lJOafGXLhj3/
EMvl6rfBL6Qv/4ZP4BjEvmMEdfbIcZmupDE8KjDP2KtupercZCs1hPGaNGqX+3ahWn35aLuz5sS9
pJebxdlA8qY40KJmHAo3DzQQHKkFsJOeQbvGBMh8JcApPsrUzxX+stXLQiUfGjvjMQBBg8eAvBsR
jcgJVwL7hJWN2BX/dvwISHPy82Uy9XeAWrCnS0oIKOuHvl9Gyj7rKH4JFQLxQSeRRdB1W4tNxGZ7
Vxd/sXUiRD6z+j4VkiQUvDUDm38a+YAjl+vSxVNF+K4hxNJ0Lkqcnstp/E/rQlTKmEagJMu0+AUW
xf7IK9mfelaud7Zbfnchzv6628kddIpfTqU2ZChxUfPaYwqPbQHbctHskpw+U0dzwTMguFAmRr3L
bIkVgrxtHFSsmqqR2B3TiJ1gJWGhiu7+x8aQE90Xg6VDAsDWWycty8HtVOGQA9S3LiwXyAgeWIGe
z1O1DpurmASmoDHhxOEVr4zfPJqZ93pKiRwydS03W0LAjmhwFN+0AKj+9UiKADI6/MchWhuaIVe0
S7xERZzPT0pcOcdSl3foI50MkqjItP2SdxgO0mokDq0+u20hkSvdf0GnhEnuDviFZDVHfMQId8VD
J/MDhErpkKKPbO4/QjF4/zVvgDRYsfnLLbfTx6uZRc8LvJ6Ys8S0qbvFJjrKHVa3HuH+kqy5ui3/
TXdhWtUSragJVY5ziq4sPe661mVXrDuw1bMiqhqaQtOxkC764b9qApTSz0orIFp2rQidiQ+bMaRo
7zRm8zQNg7NVLO4oIMbNkjfgAS55aJlYSNp05WoedtGtPstTjrbwjK5xXEnVyLmDsx8mSlILo2hN
1TzxWD4enzENdmIixRRD6KtZD9MGGZeEKKetNUqBlxztAoqjxhiUUbAifHJgYSvtBRWdsdR7Hz6K
PIRuuMPthVYtz9nHK/p2zGKcSSAc+AN94Gezf47s5P2K636UBVwqNe45mNoLaoo/8sNMVfAelaOU
fyRrrPId6SZj05EOEmIAnrcISiTqwkU72We7ArmW2nu7v+5Csk2hkMm/6VUCDo+L+/qOfuA6PLKn
vG8z5y/Ys76h2ZeUWitZK05Zucqfj/t6nQtzy9mmTKrUUF+yV6vW3sCA7mPzk258glKA/rIToQxJ
xxbvP6OlEHYoFcteCmrsoadG1k1jOLwGHgKphB63ue7etb0AoCXfn1bk18RM/pYDz6pdtVB0Mi16
Y+DIsK3MScRlLN8jy8lzZZ5KjQ3lJXgYpjPoI5AQLFRNBq3rNm8W8NnWeCX3V3zj67yoYGZn/h/r
Woc4swuh3x2XJ5QLNpBUakFeOtCb7eHFpoGZ4fK6hE0/PLyBaU4pZdwpBn6uMtBALweWSkm5UpnG
ZNIq/P9xgHTxGt+JvfrCOxkFaAFA3lZJrUql11w+SVjHZw2D1Hb1tQzik5fdTxb0ICZQk0G79GIP
lOqMnWzbSr2zS2SLks5mvwfugwde7ux2tyzvKFGNjNzqtsmq6YjseO/cZqZLW3V2/fEZ5ue9z+7d
WJpAgfZkIUewfmsfanwEy9FdMPsI0fXuz1M/mY0BlwxlPNzv7WwqS+wSlCpiSJmJ0cGBF4n0TmZ9
XnT4HCcjql4Myb6uHQo6ljT8Gn+wpkVGHjblbQudqvgYp4ZgdJTS10VmY+oawLKi9Q+JmaQbgDjP
hjkXb7FNtEAbPU7Gwk1TGT21HnXzBBUb4w8d+xIICL+59Utky1noI5sNMssJqGfCxfJruJkc7hRm
MiWAhqTyhxriRr9rdomPPPjgXW82vZK7F504tyohiTAjOTHMhnt+fZAlnLmHLZr52jmXTOhJUJCv
J++hmgdjZ1j/Tn29kLSiqB6cks4haGK6uzniV9ilkpXBcfd+x6494kuZ3IZJ2H36utcRW1T+N6eB
vk/rQdb0yVXtgOI+YX/stoeiyETnkF33Jy4ZuR7b2c1f/E0o8eECpdGW9BgY06NG6KoujYvkXyYb
+W8FeEOTtAuEGy7ZDtrscws4+4o/BMxlKfpMZopcFoH/nOf2OIqAMuetx2RAxVu9pJYykkEoqCni
QReBkpsgCYe5xH6CvbEdMh1w1f2FqFtQNDPlqU4UQik7uPYII2ioDKVlg7GU0YYPXnGW8KHh9pul
8RI+KseJlOED8unXi59p9Kl/pxuqHB5lr7fllNRVchsN1XCcitDxlp7MsewSfWxqNiybiJJPOn1E
LIh3VR9IF5myoKXXMpRYcrYx3pmgJzB0SLM/EWGdrweMh8l03xBONn4iX6lleFT+tWGCmq9MTFmd
pc5lnk3ZZtx3yU8x6q2105yj8pHPBfquloLP37vqclh5gaf6u5RmPngcKkO/aNkp4Y1hVuDk1M8g
GzUYrtdzw1Vx6tweY4RnCtmYUd/gKNBcEcoiWanRrEOYhniYoNK8x9iFlR8EiqVhkMPopghe4LRy
8YkBaYx7y4t/o2gtlMcN07x4EX1OWJc8Xgt6rwf95CjeOwfUOOq/Fj2CPkvyO0Gfy2QgQuuIhx09
K7YHkOJT+7JYReFflYDIaGqnsUOn2bb5Uc0XDXQMdOTaI3FJzI56kLQYz9D3NR0sJhsExWrrjii+
sMWF1tefYJ58GrfhSq8fT7Y3e1j+k19CHQl06A5ovRj/d4NN+atqh/6xPWi+xMFwmiPWbpwXpn2h
ku4R6RdGWVmKlsOAUZh+barQrgMxDem1QnwvDLQdi0R+1RSVazA6lUlDsFaeO56udJ97FqaOf9Zy
q1OPpzDr1BOalCVtzKu8TOppGq/tOqzi1m1ufWns5d26TgX6vMGdqN/4brbdWXB/0Uaxemnvdes+
3LgCFKFIYC+dN7FE+rKKVIEjGpnm8QnfdnUBg/jRIuWD+lk5fG0Tt06VFbaIO23aSSj8W9EToPi0
rTLhPQLmsx1hcH8D1H/UJ6zP2uwhFm5IFcFz6y9bZz1xWUwEhZtVV0LmHnOCpwm70+Se2ikZiH4O
1QUoC9/d0+T+E+OD/HApX7PQiP1NtLql3TFHm4kq8NIiM8SCsIseKi6cptAQ4AolshayNjn0w1CH
hmUIV3kDI+4dIN53fxC2Q/W2FlbmtCANaPHrcBp6kJ664YLNSt4wuCyWVXQrg1YVrG6xdgdoNvRx
Z2zjcyuDcSlXi2Ry6oFln9PLSxCts3fXdvDytawpxULoPM1/PYYzi293MUccc3EVhJY30DTv5As7
0oWC+m5fL/fVf7LmBt2Ed8nbVVLnSotCApIwRJD3EFSCufe85TBrXA3GhBfLS+ad9su4cQgTS0V/
1rFN9LvBSh7bAqVIkn0LzE8ceetUk0BXRUNjZt+IiULmwCM5AbtRwl0prEPotlonWZRdJtH0MLzG
Ut0LRkMWUlWUNzXnGAS0j+KeOi4SznhoiSf62C4dGWiSbfUQ2AcWEkWYJz6aVWQ4zWZHWj1rYRIU
joItBmyvjQTKG3S6TlgKtt7dxL019bNYIZ78xsDbr2sNlLnNNm6yygc9FmDjC2VTUnF0NdaxCP0Q
y4J8QnWL73yLzzl0i3hFKEnKj0ARmaR9sr/W96uTv1dtqSuGk2ku2EtCEx+UEoCjZgRgz7BDPoMY
AivbepRpSWQe8aMycHtrTrNB1l3pgxg5tYM0sdRE/leqKWvpK/wxkSdWsQAzs7WMVVgLMOvPDP99
yZGoT+s0P6MSC/LmgxJ1lLg50LZS9azUnYGDAtTKNkkK7VLgk/MnPpWERBsGnCc2osH3lM/CxFBj
b2Xp5e+yR7K5ayKUKfdek7juKnTFeilW7vB3CALiyN35/uV3dAP7LLXP+3hi2NvirzOTPXgrIM0J
WFpmIv3GGCryKnPoVafy61N2r+50w+6EmYL+U1OxOza/SzG1kdKPIuiCjahxK3IDWkE3N+VjkeSw
7h0FNo64JK51ojv2KqdI75FCGkyStocfec5vo4/Sk3FpKLk/CFye9l/6INqUfZLIDpv+dnHXecIS
z189o1ISM+b57zMQnCbRN71b0Cuo/CVS+J+U4dzfqZLvnWwpSeL3ocWtacvHryx5bF+mFP/iIDom
n+yej9fxefqtHTfmIDtLIN+fiuYP3legAW5J8OU5B/aUMwkVBhekuPxjEm2PNIES1FI/V/P4s5mC
n0Kv8OqVaO/QSk8odob0yPYNvRA+lJxfFeATkgTY409guerWWAa0HJvgaJDAZwA9KEgsWvrztc9Y
1XwfDI2o5bxiSDqtUb2xKf81M2VC348vleKtuan544vPwcMiWr5mO7TYc1zy08h7zhWn+Q7YSyIx
dX4M0zSyJCKQF5slUESdUzvmE/tUW0aKGIjWDzya9fwx5kDiEuXdPep7BapBLLr1PKLYsgHKbnw/
MpaCX5yFCpwWOA+9vcvAHPNR8yyJeoYryF+UYHAFEPR29/Pw7/9A44ZgYodmjTWTa3BvrscBA5lc
ToyZh/kvb3MU0Fx9YbTV52tnH2FNq2Qyz/8Qiysy8cpwP+lfGKuwg/04zRDAbOPN9fm9UzDUNNHY
48ARqHzNRN5kn4diFzdyqKJZdx/q0l1c3kFhOmPVJeCMX2v3lLJBjw6caLD2Zfbrzi2GCFTt6Nvl
5eqq3XjJ3jvyZS5AwKUV3PNy6KwN1FJJzb2I51nalL9j5iDq8W3o/Fu6mjEtftkrsoupECM1sp1s
Jy5c3V3LEcwtTZQ93CwJKMc+DV4EKNXjiE8FZYO6xcjENPQFvyQOf56cL4koVByxTnNDFOsACF9I
XHn/XjfrkGPQcLFAm6kkQqL4v+cVmTad0wh91rvpffiZyHqEjlyyYeOqcv1Alb2iNI9QHSvQs+IP
LJ6dJ9ShlmhFtziRNea/Vn5baBX3bAc2j+4K6NrMP3Z7ebYtmjZPatcLSkVNCpzvPZw/TaDW0bh2
Bgezkeyf5Z7czftNbe66Jz7seLULhcIEanfKEtUjhqN+4MhqRki18kKkslz0HWVTpPGMV9NnEe+e
dy9GQ9YELHrLl3U92zefzCbhwdiqoW4CSFZVJt4lTWK2W9hl+9GaHe4PoqS2+YtqlTguDV0KIjQd
iSJXFOpxUk11NlpI2s16FyMyWLaP8XOfqBknCTJdzdOIqDIHCaYrVkTOdc6XoIxuBBVpu8lFDjJW
FjZkCoZvV4XYxSzltGWPuVRZZd1eUIkll56sjlG7l+uKlzqZGlkozbCqmzKjmnPaiIdjTn4SnrFz
4mpx/rnuT/iMvqltzkvMvD7vfs+m29YhYAygAFzDdcl7b52XzImXeNoJghGXQIbyDOk96JMPm0kt
Au4e0/Ht7PdtbLPOTnfdbkKwu95fW26Ghvev3fbC/c8edtMsYVtmuEmdPgAkzTEGwhZW3HZtL3Rq
wolfYejlBxW5CcbVPmtDrwsAyRRINFkwNnxVDswsc1052ab29W37xSJemj91YGmn6YVIlYw3zWL6
jWXvWXw23gpygH20WAkpBoesR65FNGVZEGYj+t7U+HC45xRNJAjVQm9G20g3tBjIN1cfLbqNfnIh
Uu1Wz6yb0ruJ6ffbjp4hAOxTWlUrjkoXHStkp476hAUmPuvYvnLLgdKB6xbHnTNIS+IrYojuIwKU
nO003UmMMDUMfpBwZEpRIRL9K6Ca95IMq83DU87BDuSAkH+5Ovca0zIkzlT0UaKeuEBIUVtPwS7Z
gcds7dg2tT/gFDXp+IYlTFomc6aFlcS7R/xet8PvHO4KjjH2JcsdLCVsP+LobGn2rEecPOM/iUKQ
tAcd4lUaVD1UiA+auciN6IQS+sjuVRB6Rjt07/imoJRao8AtTAdwvSRqpH+XE58Qp1twqlxnGX7r
KeOJiDHqHK4DMykhJqUGY/thdbg+oEZ/mBOo+9CxWk4dZCxEMbORVbdkES2gomc3FxczPKJMmtLQ
C+rudCaOfKsOzI43+tenY4Zu41roMPWLiN2LXkvWn09ZVMTqQcdZO9Z7ry+2eo9OIRiU9SBes91x
FiCxF2DepCGUo+WzRk3t+UYl2QrTR5OVxCHu75q5Vi4QrkuO8J0/XWqpQri4Y6RhVa/eojK+7rBL
9yOf6ui3LpgebCoSLl01VDL5n9zNpSNyAnwD49f1q7a8BBKl+lfTLYCylrGeaeuOiSQIivF3Napt
71C5tOH2y77N+Wf/ci90WTg0ClJMhNyAXzvImQYYqdBO8d5asnTKHwiuVosLrPAvcScpJ12SziPX
058QXHu+JyXV+6VD1Ca3EEx43jblQ5Q/mlrUSwcZSoGWwwLb8lJ5/mPwsSxfVFECXARWNj3Ci8WB
I90Wt1b5tnZbRzENLkVhTcsyQqUbsjOXcXdA59irfD1n2T+0OIdE3m29ALRZTdPWuburHsO6+jF8
31SPncCUZIeLiZxc5jGQrAUE36q+yGZOJwMDQRA1CTCfWyzlfxuHgvZ0LtRJx/yjitpwOYAhttEH
ZO4gIsENKUrEc6jDhjj9W64nMH6ywZgoHzKo7p3wAVNjAXaGIJuZQWuwRuV/rWZGRUZwBYFKrhGO
wVTHrpjPu9lSAt9ZYS4+CllU/qF+vgTxm/sjHdFjEIyxPgP0oNkO9KLMS1NFrfivz8UvoZvdVfcI
yJKY1pc9sLZT1DV6xSjbjpwmBPDoJF6UCQaKp0o0oTYWDPVcWV9Blgtyr1TYLluia8rQEb+J08KT
5tN9N5N6Dx2gRbjL6q16QiSRaTY2LCkeGs90JvkYD9LQWKV8OagA9cSZSFRSdFaQtARw4iZsrp8I
vGUmG8yJqz7fM6Sop3jNwIYwtBzBWBgd0bfZ6SQXN63F7b9nU99GEO/GVCmLvyab2WCu1cGruGd+
RoFEuFVlUJTIeehpxEcqHTx1wQaqRxp7YfHu6yKZru8FqyFOGJorQPf43rwAUE/D6YAMaGuftLS8
c5Bonl3fRLkre/DtMSGqWb1S9lVvkGP+f7nlS91rfEd4wPRJ1ja0R+Zrt7/C0yKCas/mOLIvqum9
2Dhd6VCgpfZw26iT5chAylnHVqvEDgbXGPcteSIeHPuNf6XRLlyOiY118iZznoqjx+I9RTfK46Nl
aHoyfbnlvA6ToxEOLyMVqm+k1lyI4Lgrm1IFTpLhD1Uo+RFr/bmTPAH8Sjc7pVIAwd/P3bwWsYnX
HoWTqrKXqMjgyiH8/F0r2HRdpr9nccdheox9Kz/Ni7DSxEy5SdShnWNh/BBDzqfZdLrOry9ymoyJ
BpyQaKH/nE2o/myHyT3/+Oj+jU4/iJ7Y2Hzfhm2bNwEeS9E7c+c1gMpVTF8i7FLuBOMVvgAIUWIs
qasiYYV4oRskVy1Pih1/pTcDSt8EQm2CSdo/BmuLXPVjmbpQzZdG+dvTgMMEweX83XJF1XUjWoeO
yqMCgVcHhDpUwHSvkZT9hyzcqg4V5YEbJkymD8rqwVF3ldJ/qgApoWJ7IZPOnKrLoU3ahNrsGW9L
W8Jw0ojUkoFvCzXRZU+fjWc3S2hW65NP43GYjU3rEqjJLxRxhl3M6AzNbU6aaM7t57GEm/EzNZW1
peAoLTLQxPinJcObGukYaFWJMDPu24YEd4Xgr7C0U5UARS4DtwywEFEwO5+UaQVRr8QeWtwklxlX
N+TkD9nWwmW3fYHGmoCeZ45pwQF4oZCGBsDBlhyF7TO01y2jFX2B/23x2oTO+El75D+ajAPBFJBL
Ztxc6akaDqXU+vI5RCIAD15zChQIGZKTgOHEQIM68wnBQ+UEY99tpOYNGlocUUhXSO8EKG4waQ1p
F4bdKsAIGLVNmwyBoYLGryItLZ8qWClyEf9lySQFHccf4VAjUfl+P7Wj/QhXEZgDW1nUIrTzQwGq
ycLTQI07rAD8zVy6+dTZsPXr3AIu7ZI6uu3Oeq7kRfunCEK7hKxtzGYqsPB6VqRbU0UYZVuo2ZpR
4QIPKjW1+9ShvWeW9zA6WF/AHbl/8k0/HxNI/qyXdOVxijg/cDcqy6L2XP/hBEatlPW2HImYz+2L
9zxBrvEfYbeG/kcWSsIchWneu2UfTojZ+vrNnrsSwDgBgfeG/fFI6Ep0X5vFA1b4Hi/iUTjqzIcH
C/piqQSnXRJQbACFUSWJkvDkcN3ldjDw/nPjo9SqCID7dglFtj8BCkjUmc0zooO7opLJNYOVVLdq
wRXOSbU7VhCKUtVm/yEDurVd+gGlHmENK1i3k+pHbhQF6RCtptBBZEqCCWMczMboO+v7EF+828iC
RK2JUWyhhGkZTiLkiUlqM7PFqX6OcjGkf2gnZ0mBN/moX8L4RqIhdJpuzlWS+UVzA11leZkFgQ6W
tYWgdyTorr86ZO86E4PzK4mXgqJ1yYXj0k1hT67EQUCQKgG8IzQi+Ty/R/l9BZyK+VmZGr+vInJL
ZfHaf2A/t9HCLuTIzSftQaEJbVqaBLpEwHTHPnDyxuLQWeT8Xtq29ZQSfKaB3sBQt1GG9qRxQaNI
QNDqu3LuaFqVmATmY3QkwjN+vGBr6V64bi9NllpjIfHCijv7Wyj/GlmEtJ6IlH6uqecEIYrhYFQF
Ct/JJgxHGGC6yodDPdaQqNtEW6tv7uiAH6Blr9mhPLARcOwolpg04gzZRGUykmlIZRJdMIWVZMOi
5nUyTDBx710fN+EyIE0KATj9J2bFL0+9AVoYB+8cL4oy9tLnw9BuDVHvXfXu6MmSp+puiyEzvSIk
JGXRrFlN/EvnEZdAv/Fci73+DnWwHW220aqpzDxae8RVtWo+1Z5rSRPLquYWJULJtGNe0d/lNT7m
wxNYay9w7AG8rPQ8HJhk+Yh3kcv9hsp+a1n3hacr44Lak6p6S0NsNHMPI4aca0Dr/XbxmmeDNEd2
81LJlQMYPDYzw786b8S8fzSfBZuApe7R2dFmS/ZzJWcwldatuOpFBSMpwFp2L97bXEKuN7m4hjpB
t+F8EA21APEjFzaHAXNPx/jeWugMY87ZDzGj1gM0nyUtUpTs+2NLVxrrVkRNEy8X7shp6bkrH4fb
OKo9dpsOU6xfeisToqFKo14Te88zs97owtwIPinRjmbAJDoGnhtUEXrWaTf9j7q/DCf/0TgsdtMn
2blpbPBrT/uGLEIN+or2tNFC0ur2p1nvoscJXLlYNskR1CN32hFHYeqABTgidwzyma66UtBRLQ2O
wRVF2YKNmEC5QrNaIMTD+hF5lQBL7V9MMuzEHoUkmieIh4f93t/WOdzw5tjgXCNQ2PKWsaXObthR
xDsIR8ZysgmCZyIaPsREyRcUvWF/9gE+19Jqhrc+vEULL+itEAH/nb1Ajy9ZzqJmImHM+80HZ4ie
GTZcXMta7fdRVQ+zTHApwVa5CoJTdRHlyPiy7eyGfh7KnkmQLljJgnDqnEArJBIypuZiPKmHKAxL
USfYYhJ3YI+O3xn3f7Ldpr5XWZXlPa0ncvP8N5HdCGqYG4g7vZpHj5jWxWIaq7I6MUpMb+0SINtj
r9XQUixTNh0XohCMxQKzpKr0tl06TJngFb3u2WZN7MPEPZwbOrMZeQMok14ns6idPR/NUMIm77KU
KrtiNcMB1lwP5kVOvKmQlnkG+0y06A8/6t1Fr/94dafAShsyMTwG908BGB29goP0EaSmI54n0Trd
dCEa48z/5OL20RL0zdWUP2Wk9fJV1bB0C/lYaYrMkOCXhwSrEL2jBPRnHZmvkR5jBCjJFX331kZD
ybVxLFtcFKTTZRnOXqeIUAhgR/83A7u3cOXxtX+N1ezVhkpp/tNYeMnW7spgJLxxQDdl7ybf0b2H
B0F/wTiZEPmn02WiAJe8pE31T3CGD1CKWyVKseBOnkLW3sbssRBm8ea5T8jU1FBScyz2U0i7nS//
/dI56981EmisVKzkrhDuMgUJSpC1/lGnUyxIigaBP9m4OAwjE3Ewp6c4zFY666Fx3eg61VF5luUj
z9fQXPf5k2q7ELD+wXplRv1mR9EiJ1XldfwLJm8dZjqXzaEZaHQZ/GPkTWEn2jPDpnYx4X3LfgVy
S3RVeEeJfdwGeCMqtCw5eVtHewY69rwCXE+8xOeGWSl9012BZqChsBb4K42+Xhsz/HzFX/OVPyUx
wFGueBlubUcwTrIe7jiDAkTIipC9PvL0sEIpDR/bH+WZXAOcRAApkRJuwgnTPOJVVW9MYsjaXGcg
wZZPruWm9t8sLdExIOZMt0+Y/+K8LcZUZjc3M0U8CUZnIeMcdgyBWDMdAkVqqTAGgZtIliD6/sCS
8mbWUfDhA47k63TEivmvl1g5UwPRfU7W+Fyu5XzA1gIWkhGLtKDRysRgO5Fkb/fyFanrqHZjtjB7
7jITok+NkOjivLoQdy01nARL9CM3DPp3COoDxt496QabpCdEcS7XKuNTsXSah/EX6whLZBbTQ/ko
ZcXxBvd8rCIHfR60mpmcfTifsYV98Tk6vq4gtqw58tP6X9ufCpXW4bDoMK9BoneDPoJWRF1l2XFK
063/l9wxbwjTv9ZtHUNL4nZ6WdLXuf/6FGqsLRQ3cvN04jFdX/qJ4a07WduCIX5rVG4zH37dXP23
neh2M6HhQb1/+Dd4at9Hk3BDBom9Rr0DJvNlwFEU0eRVRwayPGZO7Q70hOgcepotCh3MCOJhIslb
gcSub+oiYrL5ZRkbqINyCwptZeRH3F6vRJDDNZxY7ZPIRy71noPGIDvdSzvMD9J0XV8fQDsdGcqq
bJbVt7tMysxblIDUVuNFWcsF5CfzXSMe7CxE+mihECTVU/aHZvop7ZBDHjD9C0M7e8SKwVj+8sxR
ltWCI/NVL57aDdEHPLwCE8fmQRijl8tcf+5aXyQnv7pKtzTQ8eUHQuTGIjupTviLlh6kNAJRFVeW
ZECvweJOu2viMx2FbEbI5NTfvTd8XIaP5Hd8P4mWe3bv6Z1iUprdWQOygUGhesV//pxHMw4bMCnk
HtU4arSjaWscKQcorokU+7GGeVlMActjsuUYPGdMmqCkPoN7kyCsP4L/41EObaYdHpCjL3GQAil7
I/u5DaBU/jD5+N/TvqWGog3/9SeujxUrBZl0P4RzR6Kz06J/wtAwKbWy9lEjPkjrz8fJuzoo6FL/
rOz+sI2sFrFZ/sPoIoubBERAdFCEJHPYsVE3YN42kFaiihIucw07plMtBNibNG952Wqogrf6NKuT
CZvpKtM/S2netJHM+DTMa3kiSqy4770/iuon478MXF1/uGZJSYpN/ant7F3znnEziGSpCZA/pA/q
bouLTPPFxXzQYZ+ATE1CEmbEZW+IUWZFHgWxXYJdHK1TSHk0D1b+oHVdHL5vkQSiuUBzYL7+d97A
tVsqB3HIbAQoOq4HGkjozthJof+npTfvW3Z2Jp1QOjwIWewqitnQjfqA8A3A/C5ySnpXs7OtnsrH
jwg9KG/fBc7D7KVmxElCAuiWHUsxkPKBEqSACehJcx2qNryWqGf4kNWorPbtDzfYL1MK6MwlrgaH
pO+Q1UR2Xc9ztpNTGM+cfZZGvVAmNozoyAWE8Cf6FAP5fxs8oD2nlVQxr5wZ90GXxKlPpnEqOybA
sReaJBUCYyp5/59r0m+MeEjVhdIrh1LawMU6H7ZstU4Fpt1O1QI1Ed7ZqvYsud4zEJKiHdMj9mu7
o0tDNzwlYKcqfVUMHM4mF9GwobZrC5u6anUUh7mwojKlp48pgQg+6Qazr8tJEeDQrw/Vkpnedv7u
YcbAmT5Ca3xG1P+E2WSdlp4AF2eQtVp8voeTslgC1kjg28I5UyoAnvZQ1W2XzICvQ4fTwwPXpdeK
pf4FaIH7TMk69EqGlU+fg6pYFD7fIza/E/vwv0O5se/EpaXrksMRhXTNiUONF8RvRcsHdvBYN5fx
JvZz4DQzDFangdHhkch+wf7QH5afCoOxD0V/IM7P4eP+oowbioUlp+du4vhSJOPHoBXZq+Z+P1Vu
RmZegUg7BZoy+NTwtYqmAPxzQ2eQb7yWcv4Sml8sBTHQQnWohZsdoDLih+TnOO+Eh0zsfRG/Hv1C
/lroPE3VwxWi7yYR/0ybpZEp+riVIPfobYwujOylIYlPJzV1Qi7k3Yn4wxLEAFThUWgkMRkS1WVB
S4cuccaTRUaT2jVEz3o5dixNprpWXUUnPqZLPCpHq0fpjQ/XRU+uRsdZf4Ogbqz02cipdi/CFfDU
e/Y0J5C3ZVnC3tttXLgAGDTi/DACWtHXwceBXGrSQxcXY+S4F539E24umV2h4oJXows+LPdPv7K5
NcujjyBzeV9wigCP7cLdWiL0b4+Mi/KEbFz8VSB8tgRXc7wrj9uiquzE7wuFr1T5/b72iKANYwvf
dL2905fy0QU3OsZmLE6GXR1M/XqBdMCp8rCh2tTJF8E9YFrnkCTsynpBYzqTqNSs9pl6HqogDRTf
/JO2vO9IXe4haDBwWmCCX7xUOs98f5hB+ZNoiq7vmtTptm7rmW7ztE5fM1NhSPz77wMzCIkDO4TW
apXVIcvzOXqxN5uZgvmm+vB/mCrjEpL9k5QNN7ec+SocU/zx/sr33bwsV9wI1pKGtVOIw858bbzx
QOhldTArwe+haRTOILowQOGX+9uwdcXzB9NHLfhgbg3liFMoP6hZOpYAoE8Da/isbk2vwcR/MipD
xeOzb0uwnTAjI+k/vT3IHg1Huc/Io2/4bOCsUAK57RDA26t6MO3xXMTuOAXdq8WZw+yVjUlrqNzh
t2mM4pStENp5oWnIfKCd8ULEYS/1QVmNzc6n76c46B7OS6Y/ziKCvVxtoATlKP7qtfEr4bf9QzSC
46OwlGjWPuITZUNkNXN+Z8ZoK6RfX/3znv1y3btCVWyCe+gKQlhmQTrsH9DBt6gVUYORVes12yJX
sNKt1imvqW99hOI0pT+FISGr0EdsTS9H/1UQ88lD61WLcufkqhmbbjyObPbiOLq8Gy980leXBNLg
yIU96IrKtkUU8ksjNjmHz+LJd1BJj0TYsxEVKFkAqwIQnwMxlei6oALXBlE0JIzjbpXR8Tc2Gt03
o6W/NWYpfra8FU26HABI6Hn0zpoXTFyoYCF9e+cood/BeKB1azEX/er4/qWZVb/315pTsLMTx5Mj
LSZ5PmMaoYdcBNJnyKb2JAj5iqdurvesqKbwhe6Q90fDOTXQ/qga0TiLN4BqCEyYB6I7viYAhICG
fKD6ZdyNI7Zx4eoh38IuhuYEs13KC3JLwFj+4y2h5Rex5KtP0fk1dyNvXleeyE0/7PqDyrmETgZS
nWAuK0xem4HeEGJmWQXxolLki4EryC34FrDsotMQvT0rtcQvISYQFXB5fjZ3bUgEg2kZpdCU/M0L
P6ST9MDjZwMpy69BYLSEQgolFoQxO1lpsmpMYeH7oSi9Yc1rLjGI1AN0e/pPDNUJ57ogj9VHCoH5
CwQIPaYrqAtbrksXSdDul4Gp8HQ9JWmQXGWJpBxg6fgmd5lTkWbRkBSCUgcuTzXqDz2IJJBQ/Dx8
1+dAB5hRy/PFUGu5MIHx5FPtZbwCZtIc2n38v68dgyCqn9qIeGQapvG2MGATn1xtuJK/4F4npBc0
+PxvoCrrQl6HHnGubyS+NM3+HNIQ8sIOnKOPRJl7hjhQCVCmeJIz4ZKGWguT6if2yxoJBtmUtvTZ
o+LAEzgFT1pgRb7wM7m6wqUjraGsmyVTupE2AMamd048pmUJnzRqctTqwLhR+Jq/9hAEKft75Xbz
M8zmGCiL9i0+LWQ/It/cwIYuyFKCJghdTOwxzPNcVkG/V7W2bS/V3NMfuQH3BQi5JaP0IIyNCctg
q7jYuIJTQgKVSTgM7Idl+7VHzM4NECGq7JCMLnX5KHWaswQMu0WbqOTXXsH5CMRoeEMa+krSiJdl
hJHg7+3aQwD6SEUmGGGn42EwFducLjxzbTRZOqn1/LjblM5CufBuKfhirnqR090MfXB//Aggkbfm
ZjfaHg8g9OJOEbO9XIjaZ3ayOYCiKlpPXdjQhYWWuVzj+coYKlYN7D9i3L1KYc/ljlx2oBunVt8e
YsV5nH8Cb7WxsBadfvRfJnPgVzwjdHV9/aGxLEnxOsnO1rB29SWPpYfxUzJeMHw3+JJ1F3pDL/3r
PXfUV3XyBQNtxWKZ5d13/HH5CtLfNeYhcNcuLV6vuXZCm0GIhXQB7V4RJQyeArOpFMabmiTClm6n
+wFjjIRFWBkxQvWDkdz7a3d9nfTunsEpnfJNeoiKB6obz1XYlD/K/OoI6yOw06P5FWeRriSMCigN
sXQP70NQBvY1D6oTkaAjv2vaEH7tz3sgJLRvsfY75CNij6EoAcBDq6D4bWuEFCKaGa6xs4g/3sS8
CLxih8QTLkH5Cur/VZCjSFArrkccshNbAodOm9wI19CVAFFqkOCRKb2v7TR6cE0ozFx3FI8Wed2g
AC0kpDOgXm1sF4OXX/BJLYuTyyh69usi2Oz8lnJQd1EeQBYJXLSe6ydiJLpzRrtzuSOz3CdjgmXp
DfqcSMNDJJUsg6g1PiX0Bh9zf93Fg/kRwuNnFsXfjDUtIcseJq5PAW7HZIo6CYNKlFtaeDoznvZa
5hoTz2CREMVljH7pv4kwsrGNZvdNRHc3C+IxSGIh8srvQbuIYU/FG1dNAhXdOYrOTlBhghTvHdti
PZOtcf7chQHiuBW8CbwQGPjiUz1xAmTlTHLa0ZbET9ThiPQEiP4b9EVYPXDtdTddJcjcGkdhxMtE
MhA83lwJEZcE3vysCkUFeofRcUAPHIbLOIy6cBcZFF8dXusIAbr7UWrZ0rH1wCAz9wWGPPiKxNIx
/vct3sKMgwNOY5wMg8DucenQ1HDZH9T5rs8jbTXhUmEOeHX/2zTKNwAZ+tKZaZTkSWkAI5065K8U
lNcCWh57T/Y1P6VdBKLtxCA7168qkQ0w/3OfX7K1nFL4kZ+kH5CsxzlIf4WwDiblB8WrYixYCksh
RBFXk5IrueJ2FHfUtLm6inZokpq4SpBy0S9Gu7yOmkKYMZJ7ohF3CKWWzI4SHTFb5EZWBW1+kAOQ
kE5s58v77aRLULD6Xx21gTG1uV3E5ABBzAhcpiM7dRLqWXzoQWuUf7hgmTFxPHnCxfELe0zvZH63
VOWLF3o1BeDHaTQ+6+dqfxNg30BGb5b0eg3yZyX+TUG8HruD7os8OoBikaNEsSbE51+D5H+jZsDu
i+pKti1jSScQd44YzjOeJKngY9M4GDEJfS9N7ApGppDCrfHhBb7LXhDjdTTIDkac3/QyXO1A/1zI
pyln3HQbqfbVp2NB6heKoQcU7NZIY/T1ifqyR0EwDZeStJVrpeKDTGMmMgEDci2hpOJxfKkmwlyC
pZqOecTz7m5foWkmEchPD6lkfcA+dgiXG0TLh6D5WII4H6hiYOhsQcq+jdaa7CUfN3bUAh9sPJK+
pHhfbgemfvttE2uiLJCOqtKA+yubdobkEtEtwlAmIGX26XQCzE41QEMumYN8RzWQFIkrRyWGuZRL
ynTbPGVjhC7hHVBgQ8Cc1ro/aVJL3OLK+02SYSYh17h5DS05lSbwAJLGlPS1Z3AkTeGKjXnhOCgA
fHcl6BPRNgjohtrLxxFfRMNb1ek405S0UCFS51YHA/FttafnRMtQ2+pJIGveEAyLPPEr0IQ29Uz3
y3cdCIq3VkJ5tVwZGAYZmM+rgZWCrVJ9hYeq4TfKCim4lM74eZJsWa9aiNmyrO3ZBDHB19X1EsST
4fHxMKQq60T+9ZRPacvxNN8q5HMObZpBTjrfkoo+PMiEdeW4S4wyNZT6MqOI02CFH1mxYWWJIOVb
lVRM8LmMR4NllpPOajqct7pjQ9vmOoZsuhgLa7xxwDzRjIvzMwdk5rg4Gr/QgdkhEy2qEP3jcvnO
fDNxe5t/BabaEkguqAszKq0uUVzWEtY7qud7dBTP6Ysw83Zk6Qc/toPjrruqFSMHgcQ0RixVlHpO
TnEnsFdKKTBPJesKrMkN3a7CnG5vGhu2YONCrSEmripTMu7D1PBqXBJxXlbvfq1Xt61f+ouUiNCY
6dJ3XMaWe765NN+GEeW50KiOcXyUcKYnb1rlkGm4j4b7WeTc2Fi7gyPU46ARx9g8eqwm9f86uU/v
bZwSpEzwbW2Pg+DEk+/lbYIWV7pbpRYjz76ywdjtMwhvfqtPfYYBmTNd1cCY6qJ9BpgG6WKsToDd
JiFIGu+yPCyBjXonIz/wZ1XjzEUqz7Eu0X0hfmVUjpR/49WRiyW05s9RYjXYZJLFJVjm97yPW666
bSiHrIHWlh1TLd2cNnIqW2bfW7qnxE0H+xKTiEtKt7/4f0dI+TqPDTJAlDc0XSrl8tWkM2+DdSZc
Iw3t+YP18lhtywDlr0XcnHBS030b9UNUa+KfQatEF57pXAKfnqOAZbW4lD6qKnxL5OO21jkEJFXl
mZtMuHp3XJ2AIEL8JT7csiq2lUY1TDSdPzIl4whu977f6tJ+Qs/cdxbgvYKTbZNCz4kjv2sZ5rtQ
3/Ov38OYTxgRx1+93ThtACYqN0tC9DG04/H6Phg9ZFtMGvR3aqV/y87GEseo2lnDm369V95JEl7V
tCDtEu0DjCU61R2e3LVulk5pL6A7EMlaQtohTQWVTR9UKZVQQVt84zKH8sWGYfVYFWIJqRHjV7KQ
PWfJ5GTNE9MRL7INBmqf9/wC1YhhCcPT5snF9qLTVJhpDVtrT1ZxDtSge6ReO2objfJpieJ9WLkY
j6M/UNSSwJBAf8Y628+6RP07RRj3XVj8Bvrzsk+TDyOj7ikk1/JKFvBnOtSj154Ky2PMrxqBdc+n
D3MWoxTxGoJ7Nb41KH8ldjZ1rvMHelqDkFtSd2TWIO7tY3Qz4uYzD4usJoKngJwqp/V2KVDFikBO
zCrv/h3uhwAfvJttGY8rpWUwgMkusDaBLovr7yLB+OiERzFtnBCSxu8O9YwC4GIdZe+6X5tUDfsJ
TQpbGatF4OVtEvw2bv9Vy241JYsn7Snt3LF3ide+Jc8Iq0lRs+W61qipbqutS8e/q0VveZBEL0xE
vDzL4daGVVi65WtqY++UiQ+J4UDGqyvwFqgPnyZd02+9kXGxeGvLcDPMrNI2N3i6iRuBg8cYXmSt
vSpDk+9xSuDO/1uvp+OIo++NRMv7hwZCnAP6EFxfYsnMcN5ZrLQ/LrF3/1N8w6UWpXt5XZ4scUP5
dG6RBW5PiroC+GKsX90Pm6TE/jrbBLbZzPj1+cbyPnXGEu68v9cnBsZRF/5ItpTRuQh7CPDGGQqJ
2bx8xjZvMIMgPPr5Q1QaVlKtVPn1WgzdT2taam2hi3S8ycFcpQruhSZEzTFgBrd1zETjm3T2F2iJ
1xIFXDfLXOK7JjTkdH7AsdGmA9OoZJ/2PiObD42iepxvIIPg4Gxy9CZjjU9pF/UHgUu/0GX49T2M
qxVtzPX/6Dfy6AGM57yVxCOy06jcR0jfbw1+xLPOyND/9MH8ncbDZ6vewsrUF7TP+nAU1qDMaux6
MuOdTMSnBD1XkPz1ZX8ZojWdhY4WHcZO6qHA15x40TMzPyxqTlUwju9j+TARtqarwFdHIBC4jk0Z
J8edEbZErlzo8Bh+/2zC6W/Pv8o65X4FwvKJjkiWwwJzopELzKdTwacTEuKlLmqj5o/KzZax/3ZJ
wGpKJfYXvyXnEX+ZDt/0JxkfkHtGaIHoM50oAqI27AEuLLrQ3juSwj1o0OItvv1S30kIgRKY11kN
H+aYz1oBfvQWEDDq6bsLjXsZNqOvqVr69HqS7PujDCQlitChRCgvqLa3XaUvQKTjPZdfNUQ8/w1j
VmnTiItdp/Sbjd61XRaBTk8bZ+JpbQks5/YTts+cDAsXfoXZmRsIxJ502G82hfyMvIryL4K3j5Bw
6g6pjAmvvNnZCSLxpB5wvvoh9K1zDH7IPUV1RQVnuBTHxRKWm0Yu3gFr3LFb7uY3AFc+r1egTyIn
F1J38mXJW58uQrirEVizGZuGo9ShvjXZ4XKSEPJde/x51Zpop9T+H6pYeDsfPwepaBaq172h/8Dw
5ALovaWYVhvp1yHR6yw0dXv3h6BPDOQIdSoR9uejThbK7ybAO2xN9tkwpSljElt+VVBrKlrBkphm
8OMmDfQnKEL5M0xA5rsNQR92iNR+ioY51vGeSoT2d7XoMWMD8fFvq04+Bpch+mlM1FGxoa05aKQh
bXrUSLf9lF9xCKzjzQXMtB167UBIPlSN4aDYcp7OfmLWJrEjIaEUSO8Cjoq2p8d648mfKiRBd7ww
GHEYT+rCeYi56Sahf6AUCfj6YboMzYrjx//QQesAltnTM9X897R1qtRq+YXDzVmACxD7i8FRykz+
MR1wbaMLqaXm98ksvbJEHxi483v2qi7ELsckmnHKP9AMilJE76/50HC7StV9f35H501+eP7vyXFl
IZry4+7QeB1zFlGQud289N+tNMOo9QLZsPXKZk8r6qcyqtf7ef6iDQOjAo3Anu7vHd/1+Wew7Hr7
mbqigItJm8Z7MBue6tAkgA3CqjuaiuEj13A4bQzPbYwxU8RkO41JC/Ug+TrbTOe7wesRmj31sOYb
x8807AgS5kHsHTfFQ8DO/+3f6GyjeWUNAOBuvvbVWmnioCmf6DuZJuBDnEEZxst/Iefbntxlb6pu
QpECICCFmHo1e36krsDDpo4Ou8kZseCeYVeGh72UiA4lnTrdbTl7yE21jv4JblElhJgb3ubXN59F
46+Y+9uPZ1XXI/U7zwJu3qmOXWLgykPUK2td2NGPRvE+m00hckJwzo9NnoZ8QrRNaVIaBWUyKsIu
Jk6BgNqUmmiudS2Qfk5WGSJ6fDF0M+m6NPd1tmVF1GE9Mb4U0bqq6X6UGYfgukRYnbGjxTqQOiPE
EguH4OgAp57I/A981Ex+ldCwr7Vwj0/5PL0NndhlHsKYjtfxPMKf10QkjvoCfleflMNEqB2K0fG0
1nCsdDV1teJwTNrzTG4TfQW7YLd84phu/YXmAUfXnsUqsm6II6v6WNfphoziywldwZTbJwrQ72sb
qKdruw7f9xvKLJboKMoXK0tsnCwwOZwRu4yS2LQq3LLi/G5EkRMX3Q1iUbpwVanzftU65H5APyqU
Vzhm1fzpyqNwa6JaoZTKiRdqqd/t7vmRarLm8sOIl/wwXm4M1REFvwQB9J47kRmSnhGzNaez/mM9
5vnTI1+rGAYeNM3lYhovr0pfnP28i76ZOU4twqde4+n/KlQFv0kIBPGUw8Y2eMdNtwH/IKh4XaPi
McAnJaSVuY2fRvpH01oAU9Di6uwa26aSnlS4TWU/B5Ua/DSTlAE0AuoDigGI+4C1tLmxdtCDPIAn
AdCv36RmJhmkjiKWdqxx4pUHVy1Ehhq3NHXUWzmvT/FflsG5jhMUtK9xEKTJ+4xwtgyuV8EqusUv
Gzfhwd8bDMiYsxSshCVFRBAesou0M1Yi5JqIzR/JslQsNTCHdngjfOCgnass+/Zbez6QLO+HTDf2
TOp3yGRAp+5Eeb5ZuBCBovpcX0O8UGMX+uw0N7dEs3r5Je48e/9E9vJ6YU6ThPToX6toTRgRf2E8
1fHv8MjmjHAwczc9J5cSfooOO+/0pTAZ++McDqP8xUMX4LObl0CnMVm96ZB5FLGKXWN1q8vUYqyi
RUSw/oipEVKURooQdZgcG1cod/CjSebj11sPOLKLxna81ATYoCOMnh9xYFfoDinPjhxTH0phGPO3
ZDMe4OpOATA2z8NtVYiaAfZ1y1IKQGdSERuy7nVAhQVJmGfGuGd7U4T7x4lkmqTyiDCmg88bZ2I+
WnpVnUNfglWHdm81SZ2HMLVu3rpPArd+BEhQauyiSt+lbCe2tK376AjUlzD0IIcwB4cLaJF6n8Vk
DKqocVTmkIhTWFpCNDcXn70v9U34Ry3jlafhWItiBjGPCu1KNvyZQNkMMNK/lhrhT9MkXbkrOJwC
YGhXgV5A04BeVvVTCp2UtEvYVkhH6AUR5mxZll2SilGZQxSDPxlXUL4QNPcuCwGZET6qams4P76s
pbTCt3ezAyR/7qH2Oz/TAFsIa/gyl20LSJ4a3nYQPkmiiTqymcy4LqvuYl17/SKzMOz3NZoSb6fL
ZbE60RM/1be3K2nP1FKZzJZ36OzOo80NPqPv6aY9UDrMDfRkb46KORgO1klb1Rh3PtPo09rBNObR
Xky+uquCH4WZ+bVwXFx+Uw5+0UjAoMgIYdj54fBzS11QtX48ll1CVpIfWLZ0R5zfAXIsshral66r
aCdk23ETOHPvhKwH2jG+8PBjz81iAuCsiIF4WPR7c7iFyiAXHZDY4js1QWWa+SV93t3yV35Ozpt8
N/cerpM7PXvebm6JV7LaihhA4I5yhEEi3WtZND7H+8mQnEGuVjPBvQfVb6qcI9Gj3dNkB42ZfRwg
OZkpkYZdDZwnNNlCavWKGFN2GYoquozHwI5B/S6FY2SRnsT1WlqUqmMHc50Ao/cB8lFhq49MrN2h
OGcJRFICk0BuE8zaLMUnw19eUWS+D2WV2GPsHwgqMyLT2jXL0HM6doMUG2C0VfUrL+q7n/fcHcvS
QzTf53fj2rFX/FGaolKj1soA32mSsRdpfPCfzBAIc3siVwficthfI2PNi6Qm/nkOq7u4q3nghRHd
AQwx5YIJ2KL/kP/K34xnk9yeo6dNwOpLtieJgxsIQZIXjAg2DKHJYWTEUI/IAzgtCuINIXsWIaMj
QwqzOeG16Yo5vNiJcDU3hiJ4T1GZJC3H3yeXjUjyzdEJ+WXlEXMFG5SAwAXXpVnlMazriTrcvH67
3A4nkF8QpPRw1x0X0B8m5oeZqSPdOM0MyWMTlZ6a86v37JWk7G2M9XOvAiVrbIP6J8libkoMQYF7
GBR68Icr5SrwFxFVKyTC8F0mSsHw2Lf+2lri6bMOqFnNwqQiGRk+fBTKYVPL4NpxVsvVfnLfcvBY
rpvPIhIliZRHEnKVDq6FBNPVYPORUcC+zjSBlKHbz6mu412O0yj8fYobwYlmxlUbKiuUCKtpt4VB
hZ+nEp0PXt60T7AjNRHcxVp4a+llgyqo/Qts0khJ+s5glzePz3vyhUCT2FLN8cBWh1QZNje6SvWQ
kdUZSIOxKA3Gam79aKPaP2HYtGnG1KO/w+aWbyslk2MwW5BUK7ZfwZrIjn3i/iY5zKH5XY5ZvdV1
1+GpJ8qoo7DXd9f+SpFNiw0aDaU+ljakUXuWbNRCO0Tr9gzBzwzi0gHbnP7LchXqM39jj0m3J21r
LXVSSi/6d4OLZSaiq13xO26n0ZPZUzmTBcxknS3i+LJ6Zw9ijEpYRZvGNinxixMDXSluuQ7PczOv
oCnIn5OwrejJ6OdtG6bltpV2WTCtTsZ/luX9jgcoDWQ5RmT9dNQ6N0r7yrBEoZRcJVsXFH8WPqmy
g95bZiHjiezRucSMU3iRsou+70Tb/xUtDBx1royLkNq31Q7GVxOwiUAd2s0PgCyJHJ8f0veKRza/
EbU8aD5cl7T4I+9w7Kou1oP4XDdHNu14+Y4Pu6P6zbNmjdE6NqOIC2JFIRbMPr45Vk8NxCL0DK/4
xlv/q1VjdzQb1c1sgoF6nLKmHzOKwtBcC9AXjM5Z+K7Ggf2hBb98+xhcaNQ3gQDC2r7CzW5cksjw
HYGn/7WtzgfgrUSNvTxdnBotOgXsCyyEDvdCm3t5lO/9bAcefB5JsSkdg6ShZzIaHU1iaLMryGBo
ymNm8aO5b8TOG1Zv3EozRRZLS5qXNxfPu7KZZHRVWYGlhtnLMnh/BC1VWDeEBQ/4Yq93+/kKr7P2
ek9PChpRhD5AeDEQRN2PgbumGGfrHEa44CvbSdDDo9tz3qtL3Y0Y6ExbglvAWYaYCxIVaII0snzS
39chHvwqsS/BS70tYLcklt5YyM8FpZ/2e043sICWVlh1BYLH2ZtUaqRTHF6sJL5apSmuGoCm5jkd
1DBJ1FTkZfg4kfbgl+9FKe/EK6cuKdc/IxG76Pm6xGDZcwPjnj6qTmZ4Zrk8I6x9Z28RPaGRwd5o
B0kRTjbDkJLSV1P4sVZzFihWVUisfQrHgH5DerkqzjnAm4fQISIBuGSxrU5Cu+UmNxHHdpGO+yro
5ByVdfYI2aXdARTVRR0OQczrQga9tJe3U+UANqFeeAIDCaBHGFpPWsYBJJGFfTgScH9PtnPRns+Q
86xPpvByber6EHgh+9fgjeOJWZLEdR1DjmKSDq6LdgCSza8fgyVA9W/N57E3CQ6/X9B9S1CqeL4G
jih0ZeZs396U+W1hh1cEP1dmrVuo1gsqFdyptnVFpNdraUYt27Z8zyDsBjg+9WI7OQJ6WT8cq50M
sBXxbsJ/DcNL3jJKpPiz5vM/TsRJvtYer4pSuA5petoGYL7FrhltLogAgbsp/L8w8lmAM156kc9B
DdJ7/pDiuAHWhkIeL12UMRrPzMJcUkadurUi6R9afaSziZBOMxnJPZSYg2dqpaN+OxLvp3gGIH0o
RSMDY41xzHRqSpuHryZgAHEChwJkRvYjzCPtFV8SQ3GrFcgj5QkP/eixILD4GEPBHbT7eUVaKKnV
N7IRAXqJytxujO20Zj0dtGIc9hfNgTdlnDstAXltcqcD9odITBpsQbS/dTFDmHlTTGSRI1hQNpVT
6P3pwyEb1rZoTAt8CrNJxgGEJ5JcCCA+pgfTG7JPlW2nFt9oGYncS+e2yEmbNN3AwWRk34Z41E5u
+c3tbUelFCMPjtymbJRUWQnEa9zmHlsNccgE/YxedXwBx8nvT+Bnlj969QwmQXwyonNDU+xVWoq6
1tOHnd5xBa5OQoSA4srSQ1rQsgCfb6Yar0XuU2XboM6e9TYJeVCfXFpxtDQ4loJlgzRXnR2JW7Uh
U0ZqrXy4iHZsOBs4Oa5PBndBdOBinQP8ErV0DJfpLfl3O1GwdbBZm9wpolm7TmP/JtcP7I62sRa4
LjdyYN9v1Fb77V+jBhE+Jd0lTy3MI0lxHX1gYVrL+LBk/6vtfLHgwDEzTCGe0GVNcugQtlD9Ar7U
FayybO+mWvU/Lny82Dk4Umm8OwgqHub6gOV5OXbaF8RYePvWHScoi2Oh3o3EIXJmZyS4kL0miotH
szYCWEeDqN/a+Luzaki4IJd+pSaj3tp3S3s/LIUnNQCKUzKhesvv+lFNJGzCbM4qeDG+KSpt0mEN
R5o1JBZkLnS2ItF15aZ5/mWW3pfdS2dmcxAiG5P9Egw49/SeQZBr/x0wzxZM+ECo6ZztKqz9ofTZ
MkSbT4Ovj0KzhamEm94oIudgM+NHtU7GrH5ZNcpSeUSY8ajgJwRxCEQJkNRtn/BlU7CcKNbe0jMh
y35tZK72hn0YGTn+V2zwzIjGBVTUap+/fYgK5sSaZqPZf7UtPCTannmpRP/DY1iNe4h23njK2cRQ
MARvyBSzL7Wf11QvurEu6GD/DWsHYc3CvUZV4ClJe/r2I9ymFIUr2FI4fKhB7zuQ+zAJUM3trZwI
WETErab4JdB0f1af4ldl+b8f6MjTchh/YpmWsOV2PazcsU29va0CCPI8CUE8mGq/Bk33MGwPQVUM
sakBHJx9MInWHWgEZhLNFKiaLZIxuyYBMGOAeXybb9tYrodeEf8Gpc2C91mQWs0xrDg8nWK9MYtR
BJvQtkJAnTiQiQd6otJlKCCSX39hOpNCF8ze6fX85FUvowqIdoepyifU0/RBEua+++JPbdFRUjUw
2CDBmcyCavXjYgPvL+rq9GCiQphFxxJHHn4HuLm0tOip84hj/91l2iPcaHUtJ6HgifeSQ1FojLGC
mbwfqucIvoF6eEvQpFwbZliOEMPIO/ZMzGdJxh2YdCexhxKSVZ39gwFRYIum3XpPNR25OnqUsudz
NWoPQounjsUppYW0YuqY/ZFThKbF2IQh9IvUJQfudXLbByKg+bajn+8kn+82kCyBgAXGAIK5/zRF
EVdQD8T8KQ69gfjVYWrX5AEJ1u4ocloHGWNf/aEPhQ4/bexNgarIW49G1sI+xb7CKfrlgCn4fjR6
uvFycbwPfFasZaAhA8BaSIFGE6Iqn/1omvuJs+U6NeaN5756Ai2NTrEGK9Aqs9RQhV7EWURuNJVQ
h6hKBaBl8OJ7lZxjqWCqDBNMUBWHU+4cWJqq3m2GikqJ6GgqU88Yumzk4eocycP8JBc8ulXP5DRK
es4P2bmuQIjCOHZdmt4zQ9z2xVpeuvabtOC2x8SW/j+zEnpLu9Faw654RJOBfV1ccfoBFfltU96B
fbIb2dHOSyi7DhXqMgP1yTHIVrxjew4dCWNbdav4ziXp09rJOyhF1kjCi8QB5sQStxnWFjgyO/9u
LJsnUxGzlLMXTds7o5OdSkj1alfvQULMk5PVz+g1qYEPTZrvvITCjQmnCo5VaJWu5PYL69Yzv9uC
cBn0G+JuSX7vGC5J5kus5BaNUIxGlvkvYBDTeyT1cdhb9oOD4Twz5zpg37WjudrDyJr9o2Y8SHyH
TgBl4nNAc2SuDvXgCfX5NBrursRu0hUg57EsGeNtvPIIqYVtdzQgJT0jr3fVyAQKztbYAVgkSCB2
Y/5njdPyVmeNaZsvrJZf5peqQVPjXE5A1ve1g2xCT59M9dCI44Xzyif7dnhGIzHBwahNQbDN1zQR
1AChWAQwcWdsoxEhbGnh/JL89N1xGnD7BdhWnQpGrkPeIs4MnnXfSru3uVnzb54xTM+uhDc/Rz9z
ZGFKv9ex21FHtPDgOmBeUGpvvhGtMLp8usZpucDw4OotuCMftLR+CzzQKRbbNOcCHq8qiAjIfNFX
EJ2nqSSNnBQ/CQUR7Ha6YtGHyrJ3F/0w739EU9aEIkag8H9PcEqph+TXjyXf8H3OabFYB8zFvj5h
vdW1LOlLaWqtoOMmuS1y16HHU4sgJgibHHRfgQAI6XAb4t+Bibun5La3IhrgBs2gBSAHqhMU3lwX
7RnA96hLrXcSt0WiruyJRaRuZXc1dRpFcZJ1GDh1WEfg0Niz2JTi4JYnFPtb5pQbP6pl+TB78AF5
+R8bKlM2yYH8o0RY1ihmSMCGw000khZOV5vrBAkCI8GBp48kGjh9KEuTk5VuKy0+WiMj74CHDAuT
kZkSYAnuc896tLB5Y4C+sns1OtnNnNiD5iTDkqETP2nJIjBmFMG1eX17jb8wQJAUYZSJgiMRWMpz
6fhRusxwlmjL7qWn0eGMs0FnWgzR3Z1m1c3x6chwUY43KWMIAgOGwHnCiJYbSLHbJ/dVq798kdx5
jTKC5vx9DECT/Mw3JUiGzMi6pKn9t1bJaKJFyG+3tKWLzRFKJ8imcEyYgaDAMLNRVE6BoZ08vO/5
Ms4LKJrsgVkZjT31t+HMsh3cTp4wuOFbjj2WeMhznBOpVqnwiFwg33GLHE1uTAD+DnlEBMitXeFd
gC+c2sn3SCpIWoJ9atk6JmMbLeVTzMOS7hJXSDcqnSbzWU9YogWqRrEVRylxBl3chlGMt4MOgvJJ
5KBv5vZ4e+Yg9ZgrRiZiQpOUogAn4MQvQd2P6+2L4osqQvNw18sx1EBBvrP6Nt/oSmiEnLb4EPV9
u99mpSvSrh3K9zMhJWA26n6VS13uA/Z9HY1RGl1+4yf0xBSbFmX1Vk25UNDusQeYJsJoGVsXuVV+
JoWLB547cJqg/ZDg+9La+plsgFxL8xjbAkhvHKH848s9SlL3PjYVRtkNaAv7OozdCEd3mGd+OGNy
th4K28bdFlh0wUfQFZ+XOOapqujJX2ltG/oBMdCZeXyokdDqGKdoT1UKhFJc1JwcV6UXnajt3PA2
9DANXX6Z0BNH7Cm8pqICnzVGanR52DqD1IWr4GzVn5MahtRuSNYq5A9LNqWXCJAvN8CLTdsbWLCq
icP/iGgZP0XDPH+IQUllFKfof27ImkYzlDSGb09k6Z2Ji52jnu4Wy31r2/iTudca1beNLu3tJxI7
1S1iyiyx/+Kgtc2xJTORMOSpwOt1Zw01t2aivs8Nwz4pDDL50L7cCwC9BRarP24o86PImr7kfOG7
/bvsz7aF2Dw8ljtI2T1ZxO6KveQOYaW5dmAZNYnxLclgibngz7iPwMHinqlI+0GTtNr560n5wQrF
bsg0dcInLUJHzqaj/ynPj3bA6YHhRkS+o+/2+EHBoD1BmuWN+vy2hBWr4KrXdVb8o7E3BnA/wiwS
+A3dzzY6rv+0pQCgZsvdH/s1htRsppxK6w6SQ6p4klXKv4X1xvYiaDPSU1I0vXYbAdqsZq5gxV95
bksf1GOhdrzNDNG26lvyI+4LfX5Qu0ZlIc7AYcAlKHYdSNNUFai4V1fT5Cl2TAy+H/YoIwVcPTFX
8gQONxXUyU5gAU2TwGt+dZQqLziLC6gtjvRW+vcqwOksGHTWZHtymV7BuCGSOaR5G4cLNM9OHZR/
by5xzi7Qy63r29kwhEu4rtPJZohnHH+5N1K0ArexA6GmPH52mRG1NYvBOTwUcxHOOLSSFggGJoNj
FXeUEUtpCphrarotcTD0a45XNUALJCKeIb6NjmDqkb6UNVb4UgyddetkXKj2y7P3ef2dJ0BSaH0F
tBYxTeNYiMFS3B1meDIqXh9xHQw9sKml5p/J1zWnCXCzlxmHllF1EdSIgsn0smeGpI2L9hLUvzUS
45tY2+3vTHf8r43Z5B7NwqqsULTx/PA++cL8H62Ku8k725fQP7FwHKa8o52yV8AuZiwPpYFy32uE
H3v0dzWeleWxmO50MATWSq0RCnBcBOZDW3Zahmmh4RCn2hB5jf7mmnDgrhpvTens+nwrOhpMMQpD
mQ1UJZLxwJuhqtSZl5VbuM+9nxgsGgdwqFWe1v4PLykG1YX3mJgL9eC3xtlmamVe3kVr3KO1GaNY
R6Q0j6pUXxGlE8QaAf2+ggIrlxu34vrmTo6TyZJf4e0TbtzT5btBKlHeO0KW5YlCF9jVwMfMyDxT
BGU9p3Kmcn5ZmRXbZJLb6cZ0GvkgDjfCuNwU3Wd/+DwH6rDwYfoL+NDpBgX/SPZChgP/oEXfa21r
j9lEEyYp0kzGfWoTthzbz76DM+EybF+VJjKTuvdVoe+80aReiDAxojt7pkmld14uQZqtp/SGoFNy
ywzbBkbs4rEMSRKTzjAkywzS2vjcVk3Q9VLQZKV+y7jIN3g48L+5THbhIgMCmVuAA9+IyPHMgihy
CHNOK6a2Kv8tDtwDcg26zXF0oEDRryhhwL56q424MA8jhDjYdzyfB6Mq7vdACZAAoKIhdDsoN+h8
0OxuQfx4u++YH7FY8HFdqEGIAQWWQK10Cm0Nn/sgsM6Ewvth9S3JngWG2vs46HB0M6TZRwLag9yr
W3ochN1QBaIdF0CgzSJGkf49NwKfZjSiX5f707L84fP/MNDlUBTo7D31E1maOuTHwXIHi4rJlQJJ
uI1AY00ezaiSuYN/yoPSA56cdjZhC2bXbPZedfCwaA+oRJaIkZICS5wMyIEw1D75niSVB8Jzhswh
6/MXt3q2ul+dkeycX6/fZsPHfXhwsYmGWoiNDfh8bAyGCN2Nyo3Z52dRLUPkFVNRYoQGPzfz+CnX
IKbylymJvbwpQwm5uKfr0HKqlkVgVV/FfaQf3R+rBvzrFyieAJJyTfq5pGT+UlwaRd/53fTr+eWp
AmWYadwx9noEDV/l3z7G8WPw3spaVqhXNJXkRBq8yX5U1SGZmKNJsHscNMOdTX3T7wSGF/pXSVN+
CD4T/HXEtiHQ4RhVrK8WCo+K0VE7xeMv4r9rz0vVfZgsMsKWMIYQpTKEKedirwe03YKItzWRZ5YU
YhXNgggHIBbsHAKRsEHZLp56qsF5se8QPFHWNRJNjejs8tZ3qAOBeTR4QKQnU61aGxbYRpqTlvYr
pHmzqo/6fRm4zYR1sKpHPGcspNZlpzQGe3dIdA3AzFG5Elil4HZtn6nKXqhP/Eh76BGAXozsaNeR
5r1WwY+55voxv7etdk4gBzYUkeaTVj6El0iBz9Uwxy/ZvsvcCo3S7WZDlaCQBg8wrVijHeERDgtv
Ge3JwskMzgzmAXMgCDUph/AElrxJQ8kRNMAUTJk2nVHIqM+rjUySeOEkEGQ55jHrG9hCmIivgz1r
x7igaZTU6QLwC7KCsrhpY3FYHHNghz206sBzRGskXuxqPK4TDwlUxMsbEHk1feykF3JFufGSIv36
WMsl3nTS/e3x6LhAhmxDcaLWuXBnyh1sBuh9t3MVljYXHkwK7FWa/EdWB+LSGPY25PPRK6n/bP+m
ewBs6CJgv+zzY+MQ+CJIiCdD1Imopt+/Xqo0EfesyJfK4h1ns/4N38iKttYfGUh9K9nyqwHbBg5c
t8b5vDB+qP3MRiTM8FayLNsOm2Me3j4EmYygjhgMPXvaF6+Iv+KZnS3zBEjvVcFFjcaKk1Hq7zNE
zQs8fAk1bbl92emBltist34Bj8u1TN4y3C+nmluEv3cb0wo5m8qhZcMCRUH4Ln4ucUP/ZO99uGMd
YvZmpUa5S3DN/gkW18Q87ZWGJtE4nIZ5CNB3+P7o7y8pqtqHyHkRna3lzFChIu7HEdDNUODTJda1
rBRTuDVy1fH+ThsWj3ejf8EAbuOSiD5yi6NdA+MGnoUzPzI3CH5K69xTzhshNX8zcbul6bQ7rsRf
pOVCLMuVOAq8JqBiK7Z8GbJZOr7VFF4sYhpKkdAL1hbf4OJHLbvAdtAQhq65x8+sTa8rDHL7orZ9
+iv3NkNBgFsDtnxRxBI4vb/E36+1mVsdQBSyOt+eGPcARJJ1waRyDnJd3ovJwuvJcE4FNtdm4FHa
5pgsmVP2/LpVjVgUISchadTYj7fN01FcD+DzxkqYbSiPyHmKg9QDLbkROLqGysepVGFyY7BhYEHo
pPFxX32E7q3FdCgqYsQdo750kdnqAXVPRwnk7r8krviTYkRmxTEDrXqFY7k1KIweC3DNoJhfAQjW
Uf2TZKYH7/nA6rRjq+uQLODM72mN4wFVJPlXu57oHJWockQA3MtUzPLieOVxZoN41WYhNFFybl/T
p4Bm8b0kHcqcIQS0BOZT3AtWhrUgYuEARLmKe8UZhD1vSuHD6YHJf3df/QxIx2eETUZoYldknAAm
nnO+poN7Aul097Luyn4Wh0FlT+kqCGhAYM0INQ6WOTyUyAwPIv9653dGADakyw+T22huPKsyz8sf
RiCwoL9whtH3QaYo+9d85zVCpamnF83i4y6t1dcgu8gHauJbIQ0fNS1ilsPQruqeQgq0GwBEHbHK
PUHr4UmvlzLHF2J3VrfN6UKPq/3JtXvqVx/OE2EHwbttDQVUY7lSKZi7VFUz00fnkw+Yqo9ymVo0
/EI2HeiKt+xab4KSK/bSPbUJclWQC6KtxQyemp03xRZVDpawy0b3jsypGG8giZGomwTo3xFeZr8k
oI0RUsBAanG16iYcwLQEYqeD71J2RwcWzEfzrWuPBa7lrECNvuVZe9pP33oUVJHCmzmzOek95j8s
+WMF4I9RkXtgnnmmktXxV3FhWfar1onp3Xy0M1n0GfseMTKdw++L7Ay+EDXUNv/X8BDat1NinAor
kHCi3ieKOrEpkp0TbkbMK1jtto9IA0BsVlD6C7e5Vtdf6cgpldsaDp0dmWEzDjvX2Iqn22pAwKcT
4T04WxDwYHHTcCZMM9oTgRWybjDcUa3c+f0q4Qk3+Soi1UvMGEoDy3p803pf5V2m1SkKsXzXQDpo
bJDYN0Cbwa81AY0GDLVky78MY7qKJCkmJkN4Bn35LOEQbvN8CTKC1p7a+jozWe6LjuwnKXsFvc1F
pfix+4bjOMFWgKWxcvuzt2bxqcaqjPHRLvps7RpmywILUVKZczz30rI7oCv/arWNsx2ClvdO+V1L
TQB4S1g+/qL0/QAdDjJgasDTYVET82zbT0X3bmCMt+YN+J2BbZ6CcTJAlObIkD4+2UV7UUIFeBiA
V+PNpSiRrO8ZyZCBftcJnxWKxNBCdBEyMS4LEP+DBefTsmXTcE792ZU5yFiXe+WUuCuut3V+kT5C
05VSidf0fvF995lE+kzHlQMhjULU+ys+EPFQsMmXOCbLHRJ2Q9/c9yMUZL1DlDJfKt4BGe/x7Hyi
Kxr/nFUF+6cOAFrZm1LPSsmAOmwktAGJUxtrl/itHz1hVx1LDlRfyg3+gTBnpABPfwxL/vqut9nx
0v2wAI6y8yRm/LEIpIcu0zdq6CREY7CHMysd7+Om0C8r+x5u16djw1gUI/mfO21Ts91+B0tUk4zR
mPd3lUE463A7tlZMyO23qsL/ODwT4KLvSCaB/pgYHACPj+vVQmNaYtgt7Rv2vTmzT92847qU82q+
jedDl0hQ4hjl2TP6/sChRuTPo2i9XNhmy3Mwl6leOzx1EN0TWS7tX8BRwADhZS08LZR6gxk9j8PL
vCa8JiKhAUScNlp84+ZQOsw2aGRf0XDJxg3+EIaQN2COyXO+s4HU6G/xmYOnuNRJhytp4bZEAyd+
DEj2QpZL87FE9CmgQ6yE4NK0uFhh3I6ArQvMziZCNlj7hbxCDEMDwqzokoiwAQyYhfMP17KELyf3
bDkKwyT3evxoYt1S+vj1gVwHIZVefcL5n37dVXx8tc4rsj22P0n8XjEUjNhb724BvlRSixPhwxf+
bC5r3nGEgvvW7RK2D0232h9WgP8CU8A/ooXKE8hWV4eKDz/Kf/2hvGK1NWkuTWCqsq3zNphU6Hkc
nYtV2v5J34Jtxa5RH6pQMPQdq+LnD5KF+D7R98lzmfdwAqcskh6hNNfrmJIaGbVzEn626wQpn244
wE/s+9mxu6IHRhBoQfIxhvGFceawjFKalrOjacQc0rMSnArSOPhgvkgxnP/lgDn+oBsHBMqLKskA
6JtNM1fxAJ/auLDcSD5AKPeZPp7hZIKKiJk06wsnZ3987511tkjLehT3sIsJgGSfqKqWZ6pghYMF
7043HmwH9lYOvDRLmZ9Cu6a4rMqWQSnTYbfQTau0C4xAFGlfaBLxhiUD9IACrIe1j47Rh38tAj8P
1bPN9q7Duoccwu9xThLvTwE0NpfhrrjImnDNjarzv9XeCabW343ywZB/O0GxKqk6Xr/AKHNiChpG
4rOaNdaDvFPaE6YvphO+c+HAONMAY1uAwiq+SLk/pmwRjpAYHbzLTRx1z4Zt7+3IKoTUsx7bAB/6
/miBWhRzspH2O1QDcQOfWkLt9WfRDWgaLF4RdY+lYxetn2anHOnGYdwKtsPWZR22PrWNq6mY60g6
w1TjcBvUWjIQY2Lf8gKqHI7SVDusMMOfzl5Ld29W9y1qq3/pZWg52l/W4UidftWKwlJblaNYDJSy
MiiVPlmuxelhiRQJr7zXbgkqBUPmufjIYhcrv8/YFjYiSW4RkZB00Ih5iEOgnAzgROq6RZWiiapf
ut/I2pnzwhBnyoFotnQq5UTGUDVf3L6j3ueGeer+fG4da5lZyIXyn84rfYZSwYzqnaG2oK2TciaJ
egBxGovOIRMVfNo4ouvgrTDqgeAPemVuMqa94RKJojeGbmqO6bLkf6Q4uljtgND1B0WHN/pK5T1L
L5b1pU78aS6MBTxYt6G+q5KBIKn8fcey2bcwsp7aV5nnYoG4d1VNZ2CxDIZSDzvS+rbBOdMVJxGN
zVrqZVHfygKMKuTjmvLztbQ2i9ovDtvpi9By1DXSAi8wLepJ27S0lA9rfISusRovKAXDPo55d+U9
4DJKaEi8a66diCS1V052ukuql0b5BOpXeIP3460rFI4zfLTEKmlkwode1Ohm0K9bl8A3KXda/wEi
3sA4nixXhnWmutK4gp6HKdydORan/ouVE6GEXY++PF2ZVoJQg2lv8eOzSJlu2FNroFeFxmINrREF
1Hn6Vn4HV9c6SkSJp44VwwIX5JNPFto5MFz1UlYCiW44iGUICO49mKW7R9Tx1c6Y4Buy8BBxDpI2
kHZu94LOABZ/ttIIbEAd8YCHiU9Aye4E8cIH8UhdgfMrkBU0axtMYYqXgl6GLWdkIasvgN+Acc88
2a6IsmgTeEYBKSIHPO1d4G9nWqgkTAxW5LTNbOgKT5l4LqiPXOu/IjF+wuoeH98Sri9BebZ0pglj
baxaD+i8akAzymEs91ESggOuWY52P0/z8UuMKJe21j8MrhOM9v8qpUmTkurJn68zns0ZQilbHQel
3UHxdsJWk8G/iJvQoCEtm4SJxY++wHeYyQwKE4DS/YjoHtS2/4efEXgGDgVfErfApP6S4KNqiPdg
39kGKUtn9PYFTwriP2o/ccDi1zC20t0nEEaQoqDI9Qa7JxbJZcyMQqbJwtzI7WCsJYwQEySef2+C
3Um//bpawNau0GTd3CS/BGFV9Kt60NwLgYyqIcJxc1L2U7N4fwaLErhxXADePKr3IKrfn7vJ4x29
AqF1W1L7Sa60E+zzyta/fLYxCwqRQ1AVHCKoqDBOJ05zIwFogXzHFNIeF2aMKSgHZinJfVIdYIqp
Pypci15ePPm4uuhCRYTEjY1lCc1o6Bt/swx1l7p2hb2TcHa4KyDrJ+S8zC5kK0dqpFfn0xTRbMSa
pgLfFOUshPyDkPmVETfTr4hxis2LDCVa/8DHoJnSxB6G3AY5Hs2SA9+zMjaGsLyJvMLoEjxVnCui
hUz4YG5tCx9OZVR8C+W5/z+z+tc1y6Pni6jmOr1GMNDJDPuOxBsusF/6L34v1oLT+SwTf/feZpjF
NsXNmMFIq0rpD+KPJ3tAMV4vgDg/qIO26uCYkhu5QkxHKO43AFXX3jtP6TU7Y31o3IXV9RuTviSG
W9vcTpzk/bYxdzMReTys94zWod7mWBsNbVBQVAiwj6BPekmnfxJwZMnoHLcRjY7gRAm4q1BKr7FV
n4gMtwmI3vH9ruZzV2Dt0IyBnq0ictO0T8F7hcwnoaulcmb+9NKeoRJ5jXm3iKijfx3J82nvos22
i+NaQUGMy2w/JHTpgeVDleh4E/hZJJz4BGmw3AK3aKb7ablESVdiIfm9VuP104g3M5GhGqZQqr+T
QK+Of2EW0rwotRUrbHInknN0mqsKaTpy5DWFk+E7psSiKa6wT7Uo3Alzu+IJICPZ98oKpRLY6p3A
F4Nw1tgLRYyuXO89yR0E0txrMhEC29Vl7xKltK9/Ce4biFKZxiw2tAlRbSdS0pJn/sV4nF//Lj/G
b3/YzxUQ/J2JKT8EW3JVdb+64V9EEk//i3x/Uykt9bDFuKQiGHf0AOEW+eTHwMkH8S1jqk6o3XzY
aKWCHYY6KuVyTD6c9YY0hMGkxfFGjhadbNRvjT377oKj8Da/FqToDYgJMvor//TgxPB/5V3sSjY5
tIIJR1VW77I9mNqcSMTrrsk+ob/Bq3TnyCWcz5CqdrFuCqC2ByP6Sz65a1bhRB2PSH+KVUJnHG5H
6rwYVSxfrY/svbnZEM4tHAFTq5tA2p0ydTQM5zCfeaHWBD8rRavtquNhakNM4xpG6uYPdRZuWslP
KEzFP740CFxMu19vTy+TXsO2oG533mnX5REeaPjxbtSRxpnKuOfvLiFSQle/+NWGPLfBbcfIwLbK
OxtHBSkmNgabXHoUuNjObZOWXwWQBpzh9lbohAsnc2MrB+Zb5M3U1PsIaiLjOl80wU1ZTCJk/OUd
tffB5zT60RnfNlFuTzuX+XD4THIhleon18/NjImyzJfSubMEGBNWEo4Q+xqqmzGKh4xcdIsLAzvN
rbf5taYmmdgpsMoaiOMUFml2lOoqxYZ8kRv3rCtRvjBiZ8+eOM8unxk/HxZC3+hnyWFLWYdiraz7
GfbXNj6Sh70Ty1hRfkHggbXgvWlUZNlr5puAT8ksD1ZLc+J/ENv0T1CYxqi6hCcLy2BXFrnRRMnY
83hlBQKbYNOLaPcVXOGP1MaKh+JaPTy8FDC/1fUm5AdsninasvUGe9pSVKkAqoU+hnWYwTOhMy10
8KKGxReDnVXXq7yX0Wd/qhZIeIA5Ih58W/m3qpj9born6nVeieXMCYu6vacEImJeP6VIrJf+5Y7c
/wqhmG56dFaltDv+9EItHZ3qjHMQWouZZr8/CH3gR0LRLgGwc3dcBXoIQD8DOesJyI937IbAsUzB
y089i9gEM0ZSj8WEQPiYGvrvCmJlmp/6EzYFoOnDVj486jK/EM1Vb2P6wS8I2VWO12TSWoqYm16G
GjgUioP+tuAa29/YUn/vbsRYdwJos5lwPb+tj5y/gyapeMwUdMPW56G/zN6JtnIQ0NyJtx6wVVSy
4rL+V1VpPOkMPchOSCsx4TVBoIJRuKdLa+iZUf6zJDwJwAK5kwlNykGmvGuHzvuXlLwaAiTTRxS4
VRMi6rBONkym9GHetQsHXikuV3p0UapOlNH8TzRw+/XXLPK8W295z1CYyl37tjeVXPi4s+X/cXnk
XMl6d7wYE9oL7VzH61fLRYHRFdphYDu6tek6qNkU0inVJON8Oql9Hpbgfkdcnf7XnsdTBQOOC0sz
vypSIiD5Rl+OrpwopwqppqQm2NWE9raUJXQhJbyvWh/qK08G2ZOVNb02gyp/A/EbiOTP3S5J/w3V
1kirt8v4T8i/navDsSu5Ol9SjqFZ31HUyqsyes4uQ9gFlnKHJ72lMrO6WLG/COcmYbfzt2qwatrX
0wCCFgd+RILvEwfzSB23VG/P+0KcDspvbju7LgB5KSkU7OruB+XubOeg59CmFHDuhoEueX52vggC
ot+8ulrxD534UqoPWr49wyg7UjAOrhYFCSTEgfaKqbDnig9HhPoqos3Nwu0ZxCNRRIBttvJi7zHp
3S5bLRLkUVI8RNpEgW+6aNrwgh1GfIHyhTeqAM41SF6X1VPT9qF7nI58vpSO4gNngNF0i8bUpn6U
9x7QhijCMQo4Bqsl0Qas5JKPfmLvl0Ro6KIrockXLMYr8jR8uaNiGzXk95IqJ/zaZBUInaWFf13F
+3UPxzseJA6L1QFh3uFg9WMc9wMwR+2mYxarRS5X3JdLgZvTcFyh8+9YKPaDJRfb9jObv/IApmzx
sDt5BcJ5m5kJ2sufs6D6h47P5GePmcIp6UOmO+h2ZJWgn2FzR9EeDup2RUJIN+LNrEPgJ+axKL3M
okeIflznDttuzZsfCbAUFDN34OEEGe1peAW7aSe/5t9svzRmDKOMEbJjrw/0+xb49OiGg/kbBnNQ
lICXZqMwyBoZhGXjMrPTfahy254a1IHVnWgXf293Gmh8VGUNw1I4abchXtlIo3EyrPglO4oRYfqK
2jloyfGpO3hn7F5+U+K/GgQNcENyWSS4FafuuiKFG12zwqOgvlUrI+Nu1iZ5gTymbNGIJUQcljaK
xWseMt+dVPmg2kpYbXAsogwLfKje2F6cEkLo7/3hrSTvw/YUT/H4p1Ia10YK4f6e0aDKbTGX+Pak
W4TVyVJX4ykMdk8t+7HLDAAFJ09IWO5e6MyXxkLBgz1LYJiS06buG0I+6snD8czVpmISLyh/Anv1
ozhHtNISoZfnTo0tdHOS5dB7ZD3YfFZy6Fq8Ds5WyhdQIOuEom1GjkukqTgakwKcLiDIlLibvmZB
b33zC8PEHqVJpanOpDUlD/OVkvD4oKVH+SkX7+xE8eJKGnqC/ml38UETG6u+ES8k/5jsVCQmVH6W
d/FjRhI78QxxTPU8z2iGwLJONoSjp/2AEbwN99YWPpsVcAmR9/L6o89rWmakHBxp7edF+HdUFZ/h
ZqXqn1k8LpR7aTMTddmjlz3rkBDkDcOoWAKGS5irhM1nPfoGub6R5Ly11X3Rec7cHidgg/raFrAP
+hAR7UxxBc8rmiHDQZMlCqUQl5gj/qeUXuvTw9s7ihVpp27zgW+sOXb6fTuhyc9r2WnxJcenGeL7
OrQRVO+D0r1V4UPAoD5gO28aUiAzSJOb9p085iGn2jXt0AwUoZajEtpxUJZEiTwq8cG/DJ68HLMp
lYuFF74Z1quEDoYMIXC+AAB+bUqiLZfdcYiY8yCATGPKnwDURnrGJFoBgB8ajLzwanobWhcf4ur8
cJBrkOKPZMBK4f8PiHd58EVDyTAWBZAb4/iZFmJ+loSlD8iP0jyf+f1nUQiOnsclAHMjrAYkeOeH
AgsHZJvkso8QUBScrwCGnZ1Cd6cEy2+61+i0+2rGAF/incaHuMg0lwVgaF+p/ELqmAHivv9uOnsf
CkW5pUtiPkoBIU/IuPqnV17tNZ8Kg1SYz8seXOpFyihChg+RH2zKVgN/AmrbPacF3ychczHMiHOi
/ST56PEuvwIfXHY1rT47XGwK4Vo3A7VKz4xCnPkl1amH6g43ZomLrqJO2stnPIH4KyH4wMVU9Rnu
BGUl3Dab1mvTkLhwYl4zM5JM5J2uX3aWOLTKUZlEgqvjvSpSpQs+R0yQsvhN7SFrG9OvPgo1aW/4
hvhKwsrCVK96/2DEndsJSmkNR1h9Ovkicd0qpMHIvoGfg46t/MAIdB5A/vq7KJ8HrYl4DTzZLury
ueBBA8TvOVGIXRH1nRmcVRW6fmZVSgZ2cqUQEyp6niqOfmbJ6IoEQr8axPfw9ZkBCTK9d5gHPRh8
XHrbHtnaJ0ruDFX38RHV0ga8ggdGDuXkYXmkZziE2/HzfOSV4cXbVnS7TL2+JL3+eq8Wc+K/nMvo
Q3Hm75z17uxjazr77Hkv6l5YbNjRYfTXFX6DaR6ZUJxnzJlJgRJhth+Axok3ETTUuST2uim/1CTv
3dp17UIxuGs0u8C7tZ84QJoayi1Pw1wIAuTrdyv+E+dtGemuA/jhTExdipbbh5E9um0h+gkR2fWc
wXCRNARPTeZW+cL9YlxQxAh/Ol8Z6ZQq47pEttILPv1zq+Rwcd2seWwLLrBrAAFyRQuVVzRLONQV
V/T5ZaASaXPGVe8Z/n8cnPnmSRVmKz44ZnMUFvfdDRaQA0A3FaflYAIzu4bKvNESUb4cBk0Qn8JG
w5DHyDFBedYlwd+NJJiO9jSNsfKHBtiXRoICTz8sm+zi/Q8TpIdnXcwshRwmmELoRNcdRibAqhiE
2kH7mBTgEhK0RygKI0PBhWwbcj7BqWlMoed7bEYSVTUdUKXuroh7jychV+yZLkkvN/F8O/KDTzeE
vYJeFMHDGQ02HCFHV6+Pryj93f7kuwAY7ZU1igxhjLIUTwvFxGAJkUojetV/f7w45fGX4YrzVLfJ
EJ9cKFgrAf7LDCfHNW/5NVA97IPolCTAfuMSuBDXsNMFDrGXZoG78ISqdOzxg5tLwHyp2wEfD0rd
F3IWIPeRqpxG4Icc+JtbFZIaRsHab+05CLZMe75iY36fGWSlGdP0qdnFsFwwMoWujgWk3hsko+MN
dAzSXBI3smO+2jkLVAMgmIwkxy/eogKR9PZ1B4GyXZvf66odgGE7HMjHTv/j8m6Gej/rWVGRvrka
Bb4z8msf6CAe0YM9i2L9gXpPCzdRnIyKd2nXEIOWbu3aRszIfUGw6oYZg6rg5+RqRfNMdVkn96Ti
ePBBoT2zOeiAsii5OnUlAJhZgb90MgFdyIcOBufecnQkegD6zGHkpSEqyXvNlf2pHKMlBy/QRA1a
jVqB3NpAfS/wb5ydObl7QOV2uLCywhHh8XXZkPH4AlERjfvSW8/wWSzZLa5h44TViZQPu15pNtah
y6gayHHpV3wrRKbmBgJeYML349PhBOBdEF1M59TzjXZWV+WPk6wZgYsC9DE8c4y2Com6dUCFyj75
pUFE3kL+Amh5xKwD0yUPYfHU7jrOPI+KlsyTYhLdpfuSP56pSI/eP1MD+W9a7hZeRdpUf/A3sAvl
4+eEAam+FsBqA62ESgfwcWvlXjXBW6aMsCJkfAX+oPwgvHk6a35O/5ya2B0Nj8MXw3unVRuPjtqZ
jmv9cOx9h2bOZ2u52iYqNDVC18WHMaTr6ezc1FzndK7zIhgVBx5pBt8G0wg0hOlo1cmq5oLkCD90
bG32C4rLzCF7PGaZgvRHK+lFrf1EqtkKRnqm4NPg5J4haG8cLFNMVALtKyOAUPNxqmjCWSFLuKnA
CvHLqhStQOx1O4EFeaUqmj35n2olJBGdCG+1t9KYoWvv7FLT10xDpmtDehJ5Q6qw1msx7hYGy9bs
t+ecatnKwcnhOiyVWb/uGwsn1eSYAB0AkHhwwTwqx4Vt9lIyw/Ifk7B0zNVEvEjg+DKymyfDdwTT
PJF8F3kggx4NEdiFPDNnVhnqsjWnn+giQd0qY6eZg2CcVsVLqPt3zj5guYiIaNGiK8j9+n2TFfVX
X7gmmn8GdhQ+xp6zY/wg/ERo0ZgMrm0DFeVbNW+a5kGHdkWu4ZsUVx+Kb59bN7upfjAJFZ1NOKeP
DtyyyShfMJ0ff4RVEZaptoyIOqJkG8pD0xzaP6z1pHA72O8Hcy3Q+NFabyqVYjWJgqVoxgtadQzf
iUGfmchLSEyXbMyBxDg7dziHywjJqJpBQNWBrNaq80+PtnvGzbnKfvWUUOi8lnrJa7e3G/hCz1kh
ZTutgVpXtlM3j0S4uUrE3Z4jr9mB2RMwzg1/W03x5mmQEfRebS+/1IZmRtR8PXZOC0x4dPpyhq9c
8myaYDPoOehA5C1xDfSJcWSqN/azQmMpdcBFGOXrf+/ZftJW2S6wqp6gm1J+R4oeJbAB6JIt4mjM
hHHc6d2RQwLMmF8N7TYELtcVA/uFCINtEJ7Wd7ZfxsmiMxCqEn3wQTnUip7eVDHGqU3+OoLSGm3/
W1oDwh68Fb3FVGmW/Z+TT5PpVxLM+07Gpjx0TfXTQbCH8ZrCs9CJcgm81LQlc1ClWHCB3cHjLQQd
oLGUVnwxyTPxNThfdaFYdWCmiShExeKm7sH0KKACN0kSAkMUrsjLqVeqWuLT6oGEf4r8BLsPgv25
fE/hRnvltjlKhMT+gummWoBPeCIMNJwzQN21S+V3448cpZB+e2mA4uOfmg5415VE2fs141pAZvgn
KPbCLiQSz+zT9sWIfjk3CbKvuhjaf4Reln2Wh5CP/hulA3GDxhnYj47JMLIVqLXwfJET93/ZydLw
FguzZzy6Gb8nsukm8wNOHJJnOEUI5eKvQA3ATRzvhhH3uMlNqJncXYsJ0wLompgwxCWq1AbN54fc
AHANUV6WnKGI/Lv1GlYzPravlXVIRVABi1YyqZigfm5CVIRuMdDIFss3GSUMuO+CVPLjLYSnqxrE
R9oF+Rz96QWGM/8d9nF4dUAjbtg8rnsfgT7ihMWXxGgRBcj3WRHZJDNGlYwY5AqVMkul/YwVeT4P
lSe66ATvrJDukWB8dwL6lLX/poZ6uUprRKA+IUo5mjuWILH0Mr8vuTFY7di5g/tLbF4ySXwGb7T0
o8LBgyDd9VqRt+qyNDMDUdLeXkI1c7V+FhL+DrFYBRQI6Oo8+Q8Sh+WRdLmE/armQZxXTacW4Fp0
D8gD1IFjlXV59Wsx+BPGRmY2sF2d+sypaRNmAwBfW26+HIkZJ25/Uv2rJjHFrHqUddcJILDVPTpG
rdDJ6W9ew9zLjr7jw7pdo54J4SVyY1ueWs6gaYIUYCVMWFl7Om4KY6gNG4ll3qla6y71HXyfQR8u
/m0alsj+db3TEo58jjExs2uaKwJib4p/+w4qTsp1+4KcFxFfJyUdwYrr+UDJDyO5j438MT/dkpdP
/KMJ6fINCrxFA8rH3f0nVGCpXRDi191jbYgMVBJwuUD4HZxgvqGIiO1JTD7TU/oZ8/XpVVWiZyQN
ijeZUtI7Tfvw0xab9DNU0jsXprbKqX17X7MFR552+Nkg85G03unfPKGNTxWio7at9oJRB+N9r0Iy
PkUDzt6OtBiszDTLrDCnCiog1Q1MDSbArbhYDq8LCGzErcQFRpV8LXj33Rlx7c0S4ITmZ0mbcb7L
0KULmcuszRQ8FyvvSwX4ITC65d5aH70NVjc/o0r12vwInKGtjnLRTXLO4uKPPMx0LNYs3h2Ek3+B
TUAJ/cQekcLg+vLuRJ2Uh0pskdDgc0/KkY8AsZSBbciGiavTZ7tT9u3DDlbAhpITDpkZcFd7h0i0
9lUMWM8PW8LpApOK3gSnRmDwp5W6m7EewDD+rYamfMpWqjwY0m0SrQ+GBgUFoozQDHQ8EbfgOng4
AdFvVNZgCJTX2sz0bTkviLCzohMI8Bh4BSycHBNAGSeWdrRC4uzuTXNoRnogd6pBMOaLDV4Zi7v0
EThv+eCR/jFB0bu3w5yp24hU4f9aTXfp6D05W3vOU3/LcaMvk0WDOhgtSbGL6AEY5vwiiKvT3qYE
7fYCIcr7ZJUfAPiRpOQ9RA03iv0RymDScStPjDV9Ky7V8kmu1oRbRUHNPj0xlSxAwQNXzK9A73kV
mREoglBTXB/Z1xFe/sVja3jzN+ogjmAPt3w4MAbrDZ+uDnKRpATLphijvw4c3wEJrlSFnguL2rci
SMiS6AOyhXZZFbs0OLeEe3BpMkjA3DcPlV+VWxpTyZwk//ujtn/zkyZ2CF7P2E7xyhODQUjvyAZA
HySZ7c+NE0o++brWsQFI7BHm0Ud/7ihb/akrh1JvKKpi7NE3CXFsC08dHW0FUXqO88xrXAwIU7J6
5lkBvbpBbjnI4lCdJBGyN5OVrX1GzUUUFaZwGalxIoLfaMLs5ZS/L/PSiQek+M3ewohWYuxse8NZ
pYxhwIDz24R+diddtnCyKZDIm9NH7IDpgZhquMWVqH6gp5dl5B/G2zbUOTzMhqaRvh9lDmqttRzH
vxxXHdPInJdAFcfrHs+r7UGw6oAGGp2kkGyuBErUPOS/nH5pnbVAu4nLcvxbFrfA1dn9qfacJg93
sRG2dd97UcmrbJo1D3LB+JXY9PTiPl42rOJ793iTujfeHy/aS+vpZlknk0ODR8d+nPGP4Cd4vv5h
b5UPMwQDJ+Xzi8cgHo5e2JX20Z+Wr45ZPKFqBTaWFrOjMwxujSSnk3yFAYJK4Z6NM30Yvdj6/1/E
LXM+Iv+Q9JtIqiGH6Cpak7aQTNFSYbzLytuLeSBdEwCv2UU2K901JYlbRzdxE3ULjqe4uxD7HelX
/V/Y6lsDDyP3po/EbhiM+RfV+H/oPoSnRLhzoZIJ694KiFqVc05VgD1aGDYu+8EMIAuuY+fbVJ61
p3qyGS4FozrEkz6Z8Is+w/KUto8YNJ99tlfy5I8FZv48rmnffF6hIcyrLtW3IkQ480d1HlkAaYqm
+qMidBEQyfZC3+f80mFyIxV0WFqDLxEsJZSB/mwfK8Mnyxzhk1r9E5ma5TgTWqQ3ZB0HOOp9o50B
YfmkTjMRODjAdVwRxQJHmZu23B8ogb2LyK0XGpo1D7Pmc37500qDKWB7u38jhqrekfGxVeOcp46p
TPHA42Rneat5aEvcVGvLpyWiQFz0sH72EGaQQQswIGjNC1M8dg6JeIfnzeclo+rZRQMnHYgoTg8D
L9kSejCVLs8gpFDjMOSN2BY+J8tFLUDGoKIskcCqPtE92GoZxDZawHJJokrFA95kO+ZIMvmdp3e4
2frDoE+WK5OzClaZrCw/P4ePPrixB3Vqn9NsZkj3c/9h5iW4yJ39ooWECnPd3d8MOXUKOD48Fftu
RdGZgDAzy+JsCPCxukOWFbPVoCwTAKDPEcZHA1vpnpB30m0RpMDxbaQikzHVkYFE/srW+f/NW+eU
+u6lEY+/SJYiRTXGaZNXP1iy/AvVWOZ5eF0UqrTcQCUt08VaCv/L+FnH20ZTb1wjoDqQ0tLk+dji
fS1US0aMhb2cBztVvrhM8PbdQxJdZss9Yb9sAPF6lpfPcDDwTxNJu4vpzfyIMGf6tZdUcP4ymAqj
T+onxckJkLfYh6z+WOyXLplg3XRPm08gME0ckTZ65bpVt697Dotbipw8I2mxcgEPYyWbSHz/rk6r
qQ6Hj6tsZzyWm+zQX/CB5J2jaUjxhQEo3kWDUw7jD0EeKwk40x+xW9enRpbwWEZDDCaOodjNPCne
WkGcCepblBTU0LIRentqBoAAKnO4j8WMaJaWoaGWVglItUBjPEzBm9Gxq7vGCkCLN1hzEaMwgOpP
robl9ox6JH73jgIB4kUZFDl5NaF0XgDxCbNlFVzWfjKjxV/hlXHxqQORoI+3JBNoPNAjTh14NG7W
dW8IprtXUswiqGwT8fISOuFOb0cFU2bUa2pILV8X6GVKJYVT1rNFXgSC7fKgYE14+LXfvABD1Rog
f4G0dW19tr50mOuhyFiaUYmR36gy7Qjvn1OtszL7jARxkmkLtDPoZaG4DPPZztf3LRiEqtNF7K5n
/y0FdH2xyCe1W1NkOXsjr4nW07N+3qsQ7ceKct0hX3M0EjR+qnJJmQrDBZHgSlVozlR3KtZKMf6X
RUeSuYPDaW2WolsJy6mCPrV2AXNqoeNjuy1rSVhR/GcuUuGPSNukSY3gtIOdK912UGNACw3tqrjf
gFMRt+IdO2qsFxBZdaZEFu8BDj06BFXmwBMip8Ngx50cXJNefmZuZ166Y2QqKVawV55tFCH/HWiW
S08N4hdnEzacx2s5v1zuvTRvaffx0xFmoGSr7BuEvoZ9xnjeUjumDvt1WjQvGfSlTc/X6NbN2AER
S/ioKiTqJLgSpiBXhgLvROYQ8ND2624tDdnar05SU4xvl2Vs4Kj7mBS0B+FK66ZBLQD1589UTBL1
NOOK+7lRQpftiBiQaOO/xK8pvJKHq8ldmMEDpg91vITFxNE+Ew+ZK7l+4a8UmYbGD25AP5zoP6lb
1ghu+0nvwTGLk8oCCeYio6oTdlFDtZ/xRZm7UR+Pe92WlOKY1GcW1yve0jVLBzqrngHr+3BK02tq
fvBPf440olHKvvr7z7L1HWBhqvlt+8Lhq02thGXrStZ8PinMF8JFERBysprrAtEwJ+5EM2o0L4zT
1jkyCmJsB+C6kh9A8Nm7Vi4kSAfDyB3CYN+7dWM+EQ4V6AQhOHb5yPi1Fu8AS7BLsup/XSgeWVRL
OSgPZ3/RRDDjaTyGgp1dGP+Ajmn5loOCO+cnLYN1rfaZ40nWs+7kYyUJJy+vhoeYjJ3h25AEJdUM
8T6M+FusSB8l7NuBGY89D6f66g9J6H4Iuy0eigqfLHfvQuOdC6WtzPgwpAZIAo8B1Q5gfH6RtbvT
P4YPUzos29/dspI/16HVuWbDmUaZhrcZEs6QShDoGnMsUtE++5stMKuCyJHjGjSFhl/ijm4to+kx
27WPyDbqXQeRgvRl5nXQGlVR/AyjYBGlEy77whGMYQhLrpYgJXmgxAKQjCXZdNrfT3kFtSKIvwYW
VFQsA+nhtDCxw1h5kd8ej+VElY+Z8jLSLY1WG9VMNB8pKAIWWveO3knOZ5I29bkhU3UbCBcyaWz8
Wnakwad2dwLSwJhdfJzv0bNlxP2cCM7q9wGVO8/HnMvIPcsZUepxOetCoXXr4x1TDjBlqYz/yuF1
dQhsKe4cRsMKAtAVl8PURKwv9Z8qYg/etM7+gmCU1JK0ng09LW+p+nfMWTJpKglixSWIu9GdvKPp
hX3TDGpEdecVi2El13Hoop/ZF1wI7Lf4n7XIS/V0C431wQq/E8iTaU/iKfq9mnnTY6fgFo7z9ie2
chKNemTs49pF91sOeMSiWfm9AS9hgEDtEv7ztJyfuFgvVsL4oiG/RCxXxJ1UAdUob0/LAo5WyWy1
6gQrWdyKJMnDtHAkmgEXmR5qidGI5HNVTV0O+2CukkHnblFtQ0lb/fKBJXAd6sRrR5xiI5ldOf1g
o8juAHO29e6mMbhpNALeMwcbQGEAj3KHGYpHFXafGxZOn7pL4CIR8qvIsrlH5XLi3EiAgV9Y+865
KPieMVyosaa6+sf0rF8ggLatvfViDX8S/SGRXT2BOXtmzoATx6izxudYIBcB6tv7xevSmIgu4vht
rNVYSRbnRFhlHbAfytabV4QEJjNWrcIFXsb0hUZS83qWbMtSwH/PwUZj4iXslAzyHGliGSaTQ+yk
IROXSnrRErQShEw2jvd1LuRiCT36ShKlNcKXnfHMCEbYBWpe8WmFUoKrtwFERXe6VRhgfKG5S4vR
uIgdRv4y1df1RClUtYPBgi3M3EkJ5DCZqQikPIZF9swIcAg5X27EtXwJwosV8+vjbsjVtZB0nBn7
vumloYYyRE9dW4r20be+VWeBtPCosD9q8bOjRD1BwTkxQwxgz+4+YLKf3tA4ftXu1DLZdHErgoSn
SnkcxDiq5FuFPb3nhGQ9P1CSqBfK/I6GMhwlICjdNakR6LZehm419qSUWyVOKpLbYZbGiZKImqWF
7EYfdBSLEhZ0Prrlr0mQng/bb/v5FCPBOjJn/vnB7Cx2u6EI0pd8xxDQxMPcMh2L/2WBlBo8tBPx
0GaJavBZq2GvT9qJJLWbIBTIGWnGZYfArXMlMDMfcvlQpKz85dET+lF3pm9fDRzoupASFt1pmm1o
uvy1J0jw4scro2lXp8Jq/ikzB2HOaRmV6WIaiElpLNeKP+NCDYrJQ2xKjyIEpM74JD0+EbOAYjjC
+HznrFa6zOgBiUYOAGTcFXUujpbXpnHmgkFQ17va4BEw2ivixB+SC1wRz1dAsYs9wUBLjH9aiVTV
Z8NRWZLy5F74/qgRbqwyW4ghX9rfcGFZ9HOq/LGOud3N10ZPv5Gp9JunSiAMD0q2QIbLDEw38sDv
bV9gk1AvyUhqd5cunyQx8WplAiCFTwVQfuf3/hIZM+A6zLpsr3VEG5qInfGStqHDnq9Gzk8IEPgF
XPrfKC2N+mtqDYZYfl+Ozy5PieKSvOXfd/p8ESi8iWwY9aLagE8pAzVp+eM3qwjx/8u4CNK08dq9
RhwJ4zN17OBkjlAyS615GsdMpF11df1aqHYwF8N9BhQsTC/8sscR4S1erjo3fMXxGyGLZeheMQtD
6EFYRJdl4VLK3INDzZISm5Qo7raGkfZIppwUpd5wXQ/23Gx1hIWmfm+eTQbzvaya+9mZqbdBo8Eb
iExF2J74WcBgBiei3Ho98gOOoUgZjC+Ns9fs3LkTmTXagLVaAHZORotIaulHBZ3pOH6/+nMN7oD3
lMabNjFWZmVhTDsyt5T2yNH96S571t3NSpfiNLuCGHWGM1jmk07erlaB8lwj5rXmSEAmsc0kOsUC
1ITAd/cCccXVvI1cyBUwy/ak40O5dhB5NMMndHXXQujvVgW9Wn6RneaS2MwtLUhmVeUXXzb1GOT0
L++mOO5OgeCwl27QnAWwEpprN3s5atVNejFt6TvkelCXocOAAGGjvF1U6Q1Dc49EKQiLksjL4lGA
tIZGEq/vXE9Cx4JlRAe6hT9REXidykW/9Xuiw8NyjmhAtsSnLimM8DobWhejPGqOPra/55dOiG6u
04aJrM9IaSIPMmuW51CdrwNW8aHSBNBNyRHw+HnWIsHH1TukHXUwioJIZ/IwSAY5rq9iewHviofP
gP0uWiCu/SGygQh1lpDZukjhqe+hEWOqJWTEBcQwZJmLsxvjwP20IsxC7iwrjQ3d0gr4537me4PR
MQvWBcUR+xXDpBDzhlGkcMSfnkpBPuRqgADLy/kO6m2dL/uO6QDeCdl8DHmc2wtoixUxaiSsK2eq
DM6HJgixScJSteQ8hoZrkHx7K9BeRGGmmCAmV1TYYtFgGIAiirwH/W+oV94J7GtRYLR8Oj2mV7pH
P0XObvx8NqSLS6V6xHy/6WBoYkwLOHaEHOUXTlY4gVsCefsnIoQXCo0yOHzwbEYbxf2z524/4iqE
l/0aW/xsU2ppa0c9D3Jmc4273NND7m59vtqZc8DKM8qQK0Y2QehshOb7V2m6usojY3FFtaRn9NKv
L4nteMkBDttwXJvUno/DgUKeJ/c70kRLipwBDT7tQawFcY6A3VAI3GzTPphV/48MQc0sMBBxFhK3
hV5NKWVgGjz55SKXTXFwf18SZUPVka+7HwjyoRDIsIi6JNy8YdfJ2Og/rKg0g+RpzbFd3kc5bYkK
gH4CElh4XglbCtiQ/EOxL6+wuxBeNNHz2QNE8NldscW1/V6LuQR3IBUYWSKmoeAQ8FcAtml/wOxw
Gg/0sebEW6mLy0F+8FnPGH0wwUZleucEW/GV0hJr3p5HARS7YKcbqoAyE6L75bNEltnenMECiBjM
09hwVMUxmkpAJxhRsjxlWpQfgA/mZIVbuDrbaUmn6qenfcqXw8b1r/dQhNtuPZL1PXvRye9OIRdv
3uCkexBXKFJnwDvVwQcIFIXFIBjWLKUlIM8TIc6hAS+kvHpfogT8nhg5sk99zV5Q7/vMG6j1TLIk
K5LhKGBMpLePha0XBYKAkkVdn+mFwZuIVl4GnjkJqubaXDr/CAD01/8tqzBticYB237bIPUSQOqg
0m87N4XA4wadlLCdPSSXwIlYb9CyPSzPDtzcDIWoWYopHT09D2yD9xz2UyDjQglKvEBld73A7N8n
8hhh7XOfQjcjqKntvglzXEmvAJHSY1bhjUU3S+g+MUrf+Z6DetwxdrtFG+hinFScC/uJZkUZaaUK
hFa6INidBggADT5eP/KRVSmPf8YVa7vhlCZRm6sp80daRWy4BhVCBecq6h4oqlLB96PEI4fykguS
zVw/JtlAdfX4lV/v8KgfsYo9RJwooIRwelvEfEAw3d6p9oaiht2qtUQOqck4fn0TDGS70LJChl/z
rTa6tRdHnBY+4ikMLqP3ANeaXkXAsmj2LnEkbITTSIKnhuVShMgMIQNd5XXZ6d1BLwD5RpU6BGma
yew4i3hTAlEtHVaEYu80DrSzRBwhCyNZDsnfXvzmhThV2+qBHvtNaWqAd0tdC2JJaidl9VKjXkcX
/XQ7iLdVoKI2lCHhoiQIgYMKYtJboSHbdvy3agn1HBwB79yyFkzAKFmPgdIDHt5RH8L61XmU4KF8
0RarVCozpKf412tGeNLZxiaPeOu5G3ZlDAIwQMGFJ86ZNsnGllHajyn1muyb7bXS2O6vSNeKim26
TLAfbjASKb9Wn6+DYJqDPNkikqjkbLRIeuFgY2gi1+AXUqMJ1fvRW+luH5SWSOvNLIsl+Dl1yLMg
eykdODgTmDnLdMc9XAl3it+7avFEvG7qT43+6xLgU322+ccTR+9hOgMKrqlmToJe/5s3GfHABNWA
uc62KmBTMLWgrBDIsoegdzc1i6gMrNeqGaV1VzDJnqyaLjvWC6t1zCYKcn9h86yiGuNY93vncZTK
afkBMEpPa2JELxC9K/d3bdtR2u3xGpo+IdTSEKI52rX2f8yuVG3DpkC0x5uAK0f5a90qmPWcRYeu
xsUPlLWc+q0ivmILsrDca2LQ53ll54Fza4hJ7IT5Azl6DyOjrwsFO6KTsfRpsLOjIGx+nGX3y/IJ
J4uUwB01wSYDOuN8Su3+1EV2ANB0xpDYfmxvx+eead+2IKijElxKIVwSvJTmjhiNGp+ujr+6fNa6
Sv07ZLBQQwCy+llys82RRFb3WDMRw5iKuejmECzEobPe+ckWk8h3B2B3ZSIJvtdCwjHu0pDvP627
vtPp9z3DmsjDDgr4Cv8Y3qn2skZSX29uIqs9nBFwJzjdhHULQnhYcRk2zavPWfJBl4meEV+T6F0i
eG/PFARwVjg/8wtTF5+9n6GU4EfPPrldptNYWBh4aZkrkw5V7+HBuW6qaCZJnq4sJ5dr+aiFufYM
KEpw/iZYG2DxruH1HBXvfTgR9hHOeFQTT6iaRfFTERW2c5rfkMzt8BNytmQdOgXA6rfZdoeTk4F8
6MxwdTZRM3DvVCfAGHfhz2AuUI0g0+c9pOurP9tP5Zsqtos7rgJw+6CXNtqUeVFkBTBiVlvizdTK
zZFoqTcgX+gD6zFv3eVgg/G1z1WlXOhZ1y2z/5QswHakHobRpU3Z3Z7pmn2RIKNTXGG8TAJ3yVYj
zcTLZe+3bQW28ZMpbjbtFFXZVU1Lxczac9CkpOhFz+mZgwIPb5SB970n5pc4R4Whthb3dzodaDAJ
fX4aQJiowgF13xjSpf9K5fFO4Vl7r6ZJMkLBoIuzvNWfIDejYRpNR+jJ8A2zbWikpGsO92rDgbRZ
Go1YxD5EHmFR8GkGw/8FtaW6oI03vRuOA9QYA0+F6OaCk8pJK055Rb9hr++OexD8DyYa7/kLKmOB
hy7bLGoRY4lnSXjWs9Fb+BvEmXWI+pEsUQ87C5KOW0odB+xRxm1Nu6r7vuXoiFhvhkB48ToWUIrR
C16351VuGdWzRg5WxTPMr4ssLcN25kxRPvk/SmPSxR3Lj2CR+0oz3D+vJyOkf8/3tcYNGYvpchXD
oiAacpQVF8Smr9w0tUpysuQ/8SjBorE6P/2ujJFEitI3ahXIK/qKuZX3FxAPbl+gN7KmH8YAeLR5
3Ih3vCHkQlHnyG3YQcx8TLiKOUQ0/7uwL2aqWzpbjCdBJX1qYhP+pLBhvn4XqDEZkMnwbh8s2SzW
JYCsI7oP36A8B4oa8Z1hoUma3TkPxL6WrZJBDlDySKGl36ZUSyntupbCpOynF+/c4sYCcvvhD4Z9
EORgUMXcNwHBBh13UlLukyCs38lNZtgDjyS5L03iXsUyPJNvF0H2lqgXsy4c2kYM2jgfO0T0BlJs
YJzYqbSGonTY6OSb/CQIOTxIU6wTbXVhTmKa9qwabUI5hUl76nXiPShDTY3MnDw+0VS+b92K4uwY
1/vZAOEfj5/ly+Bd35F92QjXiDmRgiIzAMGq6ZuiB2PFEZgvwPuy5Y9pu7ZH0o4WzAAQLy3Lq3ea
LaTRyDbcv38oxEVqEAh6kWBkryTsfipkr47tYaK+0Vb8t1sHcD1qVRYhnL+tROJbFdQbI2rU4w5M
Ov0RWN/7TcvXqAKxShvJAyeelRnVD6qZ0UzW0N971rtfQoNnXTgCukvdA+1XoYRo5QuEtvqldFUz
lj+VCS98A+bmDxsv3pocb5i9DlFjG2eUGTX83/LzkGXMRtD4iSROOpYD1vs241FKl2vssa6uOWee
gyTDt+kI1LdXcc+u+3TsXq75Ex0HVZ/Ab0PRyWkFvWBIyLeswjmVrM8wVIBP6H5d3DEvgyfciI9R
wFe/NIvhx20LzShzJfT0yvUR7etYh08Cx4AIqkZcf80hbMY3Qq5uqQGs4/bBVQ/orOE7gFAvHbvH
vLsgBZQx8iZMh52R54bbhn86qY5LBRUsDthQvNlNpv/XqhDEoV+0q+Ybu2eX6xTWYJ+mflOtVezD
HmeibmulxTGdTw1gdKH6GTGuoIUFHgeCzSWc8goNB+ASMSpVxK/nosapwd2ycw==
`protect end_protected
|
apache-2.0
|
6b794b516dfbfb677491c2d1e76676f4
| 0.951824 | 1.83932 | false | false | false | false |
Ttl/pic16f84
|
testbenches/cpu_core_tb.vhd
| 1 | 1,683 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cpu_core_tb IS
END cpu_core_tb;
ARCHITECTURE behavior OF cpu_core_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
clk : IN std_logic;
reset : IN std_logic;
porta : INOUT std_logic_vector(4 downto 0);
portb : INOUT std_logic_vector(7 downto 0);
pc_out : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal porta : std_logic_vector(4 downto 0);
signal portb : std_logic_vector(7 downto 0);
signal pc_out : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cpu_core
Generic map(instruction_file => "scripts/instructions.mif")
PORT MAP (
clk => clk,
reset => reset,
porta => porta,
portb => portb,
pc_out => pc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
88b113c56da0c0b44624b8a2e59758df
| 0.598336 | 3.74833 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/MEM.vhdl
| 1 | 1,233 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.utils.all;
entity MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end;
architecture struct of memoryAccess is
component RegCaster is
port (input : in word_t;
SignExtend : in ctrl_t;
size : in ctrl_memwidth_t;
extended : out word_t
);
end component;
signal size : ctrl_memwidth_t;
begin
top_size <= MemRead_in or MemWrite_in;
size <= MemRead_in or MemWrite_in; -- because top_size is out port
top_addr <= Address_in;
top_wr <= high_if(MemWrite_in /= WIDTH_NONE);
top_din <= WriteData_in;
RegCaster1: RegCaster
port map(
input => top_dout,
SignExtend => MemSex_in,
Size => size,
extended => ReadData_in
);
end struct;
|
gpl-3.0
|
c44d91e147262d30857ccfea6876a0ae
| 0.577453 | 3.563584 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd
| 4 | 44,262 |
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset;
use axi_datamover_v5_1_9.axi_datamover_cmd_status;
use axi_datamover_v5_1_9.axi_datamover_scc;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl;
use axi_datamover_v5_1_9.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_9.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32));
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_9.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
bsd-3-clause
|
490553f00e2990bf8e169ab29204ec34
| 0.448805 | 4.137022 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/mult_gen_v12_0_10/hdl/mult_gen_v12_0.vhd
| 1 | 10,054 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mTuRmqVHB9Pd+fDwv4R3Ygqcmr6OzGVdNIhxQBkfT0OGwnACWlyeV9xllXu64+HzFsB8TiqMFlsC
Yn4e3wHRvQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NjNOByy+XzjjXWI6+Pf7KhGvpzeWIadiSYEWOiYSWJr7mLTUigDZ+cbc0JwCE6uBALr9grTS3XS7
hX7DRIsourQ8CY+B0gm1ppylH4fcNW0XX7ahyshhjMBcJhND+5+Bo/16IgnzkqLC1FwFduhNHPeU
BaBK3c+2soTS6rb6tuU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
TnWbccTs2ucu7d71cQOlOLyWDgeOy8Mz6h38ykHrlQbWGmcr3sT9EOTe5asO1pq4V/8+Ak4DOjG6
JX5+IMIPjF9iyBgwCEe0dbskLdJYUybLmMuLr+LwJNXrFWrmPROIPIF0dKR3BzTbSKPrLHulgix7
vPQB8+mUj+A1sPj9lM445LYgNcHP1Gl0zqO1TN1sk+Js2O/N+lGqg7glsHSbKtuXiqYTs8WvfYke
muTwvIuhCm0Zl4uVBs1joT7AMhIKT2IB5vFYVd5DOZhh8xh/ojNvdgxMH+OS1xFehVOzvsjFG0/5
5seTFmX4KcpFsZRxRmliTcGDqK8MAhM5my1qww==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
tiyD1/Hk8ORLx1tdpDusLSOszK6jrl6rHfUVQRczXwRO+OYnrdxoiht8xv6jKR9M/qlPo43YX/mY
lq1IzlvhoqS7rjw/I7mGSSPCrO0Q1mbhkK04UoYYbWmzZLypOBiP0G794IothlmpL/CCZ95shueg
BG9/MQW3hxvRy2hxU7E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
B9cyV578fMbM9N7FHlqnqw2ULx9mShNZYbGme9ZvhBL4YADv+T5MDhZcLKDpDHg1ukLJchMgwkNp
7jCHnZF9Qya9g/mqAcS8TX6OBMrvjA3FmXtjDhkjWT9wDhXVC7WUEh/yrJizAm0mwnak8jvy0kaN
w/sTs1mhuN/i8Yohrs2GOWYtztObOZQ+bZdxdStgD8m0CBxMj7ibB2Wmg94HAN2QtSGKQIRfa/4z
swtmvhXn9rlJ9q5GQZC5Lk785MQ7hEqkw85SIqrAPkV/1rWny14mQ94TqjkJUKj5MgZI0sxk1O6i
JyohbfBpKq3Jjtbqyih1dj3c6Tqau3qTcXQ04A==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHi4FiVi88VXOFbBiCHv5hg3iWgqs2U+9sWxx7xpf+8QQZ7pHjPel7Vp7EsD4TVwZ0P3nkYO3Gfx
fiAgh5oBcNdTxhbD6EORRouzcq4pqW/B2h7LtGKib+6EucRnGDoD5GqLmtry3RcG17+O0iAfVPVb
jXD6BecljCzJdJ7PKbV69nHvxl50OFbtUAcf77bkLvxJt2lkmwiXgkuSDgjiEdtSx1q9s6LJjTz2
G0vLgq/PY1oZJZYpOaOah7XmKIS4YFf2zG74wxzHBQu76G8iXskfeV8UZ1QqCHWxaPWjJy8tl8b2
HDdH2bj8ET/Pc5jmuHygY90CQPThKiKHF/ILkA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5312)
`protect data_block
0Mvo2BuqgCII2EYCVBL4JMYNdHD0kF6a4IDJunL+4dSbHCKEXJ144UlRNRglSeqxjXfLgxq18xIm
L+9TfWxrFsWjtaBRs20o813k92htKYcLP9HUxh0W93OX22TXrt4suDHFhR802UUdFuiwokve3CnV
4IJdtY6M/Rc2SU2LEd98txGy+05Y7uQKaHrvemwe3Trv+w65YP5aVCemD9jNsct1DmBUXJDWWQBa
veoDE1r8oV6hUkfJ49gyiSwWqpLaFlJkI5+nOYPB6ruvK5dqysvOxwqerFjKsViua1K5sT+l6yKb
ZgAlbZ7JTa8RnIyJGTXGU4/xlldz323L3T9Keb3tQgj+rqaE1j16FfmvlkYMioPoVCCKG8iIXIun
AsnVzkdgiXLXLEPWPmC+Ds4UPlT83srWLP1OkWDVBY1bLXfuezZYoilDasCUNgq/TpmRVpNPyq49
NEVJY7luxwHdv89O5BhWJP+zTOQNy1sQzS63tEW743qvXye17TGbyG7YmfSkuv9uChbhrcm+E0bv
gmYOVU61U6nHJLGPZeT92yraivpy6C+6r1igQz2vlsomdMML7sGe0rEVOfMWzOaYB+qCsIDKog7l
oEyN/iUFRP75edfS0DrMHxK3HriaWmlGrZRFadpUwU9gQiGYHdsIX47zS/kRaU1bei3b7bzlDBLH
G7U6T9YjygpKV7UMmxZLfg+Az12INupswNLHMAr4IBbng/EoQKwYEbVdS95dXMNhRen1beR8+K8s
cFSavL9jnnGG+zwSfFzcbLS0axLJ7mDj0v4sPYTraRG5Q3LzsLctJVD8h6MeDQVHS8m0iGiajwJM
hZqF7JqXgKh3eGoQPzYRoihw4UahdfsDhlLM6BjXhzrZc02LSCzt++4jGWKks5i9fHyJp4FUYicM
JArsaIBbmvyXpqi34md1Ut5VgpK7C/4UuHHBdhwzTYq4woHaSYSCR9OnNboI0Y38aG2IEFN83P5Y
eSbikTEXrVHygvGNCKOO5iqcAZfilNkXH+izTNh6ElhkCAGNH9gSd8mKkbXgMy8zGVS5euXYwhwD
2AYl28VQLW+JCovzjjWMS9DrQxr/+NsAAF/5g46IkfC/bhPwwlzoKszDTM0rUmB2DVgZO2vsGnEu
B6ICIfkC+4euJHu+eNayaZi7Rgx0kOUVFT9jRbZnL3yf+VqdX5TQP+bSRmRf/a7F7D8V+aE/G6gM
kxhBRs6ZZmG1VY1cxNmEQgkYlRyLkfEEP/81nZflSceV0e1KP92G2JuUmLuVsdANNseZj59TU3qm
ohCyLmN5FxhnCF92a1Os17QzWHFifQYP+O9gzLx0QEYPdt7GzKNhDKW54rvt5sAzz0+m1NEuPjzD
C9dcc4OQNtVYwI2XGjqf66Fba1LKp6xJIoG2F5kWrTBmeymAun8g5R3VyX+jGqZg5NC/Q0iJQ/pw
iD8kxYDAkFDxUgBJvI8JsY8R4AXHCQkfYAGyq3eCxyr9MzTG6lvWfQHbyuDsuVOFfyJmh5TmiTKI
+hyChuN8NJVsXsn99Lbcy9p0xlGQRDtfENsRr+2OI8HfCOVyycpElYGdM+IDyIVFb5tWX80g7uQo
GHsYCDB9weoKQkUvb6wEGE0Z8+j7HscM/UUtJYic3ZYnqXTK5Unt5VVreJAyOpN/mf0gbzAHdOWa
BNFlUYfHbxaArV2rkUw6QgKpBjVUD4CFsMQkKQTCiq57tVwyrWl1O9i7foH60ZbPqpHm4WS2sseG
p9AuaOJZesSxz55daNizb0T5CqcyS/VF0R5G5GhuvaJFScyoI7+LhDWsTGESntMHa/KH4Tas31Pd
y4o/Vvd5wAuTzS9p3nd0BTHZ1SrNVg9LNwHRxmitn2LPPXKnOTUZNB2LCbGK2nvAXUYrkI1a9kWO
CBcqh5Bixv5ZMuByRN/LZPidy24u8eKt+u0u2ovCvU9/DJ/BfAJWtXit9w+BarhOQu8YoodNhOGd
tQksOpzfaTacIvk9/0cNRqHJ60hOI/YhTjp5rnApQaqpSNvWS2w6apkvm1cVId7/imDBcBBJxbkI
ansT08wtnLMqYs32/fO9xnL2beCBhJpgA0C+/3KARQMrldxGWZfI5ELMnx+tsbS7lfeC3wHRMlb3
nTZSvoz2jc/vV6Tecl3pLALXlyid9cjk86bsZXZHsL3hEaILR51QuXpkjqYamYX5ObyM14z6RZYP
iXbVsHFsvL/1JuiSlZ4f3STqDyngvI8PRkjXUgE2reiqlqOK77uSvf/YOLPms3v3GwJGTleh868J
lOV+QoBa2thsfsAqimoI5N0lvlSiMWBWoMFqPEr1q44PaZYhsuwhB5PSSObml2pnEJcpO+SvZH6H
1xmNqw3hj1Ae6jCuV2gYFG+olNAxrzl/+Ikmo2XxBIHm6V765Z68oUK/SYhQo3g754+Nd3KIY+Dx
qAWN9wkvassr0zTVSvGewvSxi2EkWyVwlii5TLV744PM9QoLU6IPDwgWHElkQLHkFJ/fD19gQ3EH
Kq1Y6co4HMW6dM1/VlzaUAT//pBQX+caSoXUuBJXbApA3n5X/E5CjOXDQs1L4eSj296WnR/XSw8n
bDW/5V4rPp6cc0bhxLO5+A8sIBfbXSQe6hMezl8yoVbwbtvqepBsTYimPQoRZxuRsGkAd1hYNUze
jIQ43S+D4fooKGlaPijI++N1+smFAjWiXx3KaN73WlBfkEieeGl4zocYsAa2H1uoj/M4Vf2pEqwT
pFAogK8yIugzWAKmHMYw500i89UnrIyCMBiXOmR+Oz39w8lqBxiPLjVQ8hv6Ap0cfwoo/ZGU7Ak9
8ErZh8ibUNyJP1En5MgkYIUEwHpUxdoXy2zJBt2sqmul3uo92Um0m7iV5TzeP04jUq9IrbYJ92ym
5Qq8hSU1iFgQsTu1clX7RGcbuEUUC025Gh7u24m9aJ1yXqx5zZiTeZlEguiNVnS8pa3MjFtdGPVN
3QbPvt7QbNkoXpy3gLeB1KDjyUcbfG99A61ga3jf2UCHkWwKuuD2BNnMJCkhrR2m2qNd46Lk0788
lPcdXpXQ0A/xJFOsq3/Mrig54FepDSygamgYsEk74/o9xBiguZp16gsHFMH6BtS/x9uy2fctPfjR
xn3fsYN7s0PMZw94U0DtJ8Hw8M26ZwDWyROwOM/rhArghvg+Ny+H5+DYSo7nFSbL0oeYU8LMYbo8
zmNs97aO5IkqBZw7RvXCFaVoyE/0fM4n05hqoGjWEMVxW20Sk1Iu1K4mUp8zozmuUTCNb9f9o1F0
aPxCjvdmZxsLhJhFX7Vx0rrig0H/m34YQ4q8yAnFW+QeoNe8GuWaN02cv1cS9pfAGigR7JPiax9X
5Z3Bb3EP6JEH9AZa4OD0lhj3j6SIYXw/YWcqHhYMbWvUKEGePovE8nUAFx9SgY/5ID2Kb1xX0360
A4N7z8jUwWAffhmp080hmwuAMn3A/abXd5c4k/EWW46PcWAVnlnB6n1f7g1mXvPWykoCXp4QcRiC
jUqqc/yT0PyLf84BQAB96JWMCZaOqER24RADDjeIi4IrynP+W697NXhO5Lnf4+AceYbRbe8VPcbv
55R7RDvA5c68TgtsKuyvMIm4uE4IRKo6jQPetQx9z2+dR+LsTVbANakDT6ddhqgByt6W4/yTpoLK
GRPq35tkzAjJxybCs+/fSK4nuG8H6IKmO7hnEmE7oMuTJ1AHhrtvEJIhxhS4XDn4yZMe7Zv3aBWK
KzID5W8ApYDt47nvZJspCjlfih0Do+88e4R+N/6+pDmSARusb7jXGzZZZbbOferbXj+s0QLM8IrP
qDKCIV/w2dVl+F6+A6XYXdjJCHkBQQ7a95Zpm7ETXvbHoLnix7sIyxpThxwZ5kygF0ujI/mzKPQz
Ih7wgtue+yGgk03ImGngROT3HwsksBIfvvUreN1bFjjPHneu6drDUZCJD3JMhMWf6jws5Kmi/2Uv
wwTyGx7duI/5w4WpIXK6oZMCwhCEV9LghZ16FyGGwyJwp818+BXtaMzJXsvHPvO7v1HeApV+8aVE
A6ZmM63sG2sVB4zgn9nN9fS/ics8pJGPPHdMDt8zVpbrxl5FN8FUBMDjVKzoaBo8UOdYepexlSHF
/gHFTOE+NLuzNZ8CdDGlPdznyxhwhai+00uVWYVLT9M1oTZrVdQUS7/21okNXrbJvzXbGh0tUgiJ
AbsqKzIpPaP7s9aaK1tsH41NY0tPGeqkUuCFgXomypabRydk+u3+QB6Tg9SbA+KZbkzJRSgbE4FG
ZuvZ+X3gYR1fp9dw1m/R3ye+VK+NwcJIfaFe/gRjBWeMY2riIevweHXcalCF6Bt0jNIx0V7Seu6B
pOFqRQJ5C8y3OQBMw404kS5bgPRoomszuhhjSW+c6VM5xAgCP9zlBsLCkBZ1ysaNkoaWlldhj9A6
OsIAJ++Ie6ki4v8AQ2PbMrIQNYM1g6mFN3DEDKkS8Bipf77IBvJcw7iZuKmCiPhC6Br0z7ah+SJY
E+LX8tVGAByaJgRuFymUAKYF0a4mZ0t2AqEdUBITCjiOP1RCCtOhx6i2ENqlrrpL8d1IFwZDb0VZ
QaV82T+ShLa79ggUnH0lbE4YnMuZplTHeNyBBCi7oNyKemwPT9hLVS7IZJb+CIZoyTgGX6R10zyb
hIvDIpsBigU+KpZTBl8fSHRBIt69S83MBZbLwRAEqMDN1cKijTppVdLsWi8daYXh71tjbNQm1C6C
5j8qE8Z+E3eXsW67eh9pBRSCjfrbr48kgudAVU9I1RjadcdxrsSPNCtRJ/XuwmwiqpaPcXzi7XnC
nez/PeI/n8DcCCqiGPcF3q4QDxGA2OekhxPqlOCQXnDfzvJ+TDuRhMT0d5Af3BC4xWp5DQ40hm3W
WnDILmdvZeZ42P4DrPZGesbRia2XtO2ZWPe0JpZRbopbFckE01DvRkgFPaHwba9NEJKzTbQv3E54
bNi24Rj+q8rhM28lEe2G1Bc26XJ07AQ98OdU2+j16jA2T/6saDZ2ahHZAinKLlMJtf+lRmgFFjek
YV4BTlaP5ML9Ik4U3X4XyKiCNYSLf6KMbwOzu8e9G7Ib43DWWVSs4aqoI8PUsJrTC1WTTcKyKSZq
ZXdHA9H7AofDYg4TxamkwPGr1UEfWLMnwBrvxbW5N98IK7ty1jTcS9WaAuZ/X1f7+S86fax8hOpH
JyCSUuoSjElJgOuh1mi51DumVVSVJypben0+HnCpv6EKwOSBaWQsZQK6QMWXWNSQEfZEYNfAKhNA
SZ1eQ1wVguOwSvfY0zi221+p5U0ZDqcivfRRH5mLf/vwVwo3tjOIbQM9ukV3ozHxKh+xu0D+G3Ak
LDk9TUMz8zEHUkSKH7nftTAYCN1TIw5cs4NMcwMyT4iQzbGamWOoxBnDhVBZ8My1c1cvAsfFtzP/
PaB3/0tccdeYzQpuGeBZun0uTRXEc9QQS9DBIm56AfY7hbSp7O/NeQmmq5EpYCQW94casjGBjquy
IONKnxXoiHgAHBbUnksSn7F9nBLR2ea8tXRefrRaCA8U8j83mrxvxXsiGHWTQdAeJF2WGLzZnEML
p6Bf4UuYGXPDpDw53X1+Tv0EX7Gok7Ccp+ma6IItFJNjooBEHXYmfVyLxbYR8ng0TbvyQNxBhb0p
c5YbNo2u0OosbOZok8b5/uv8by92eXmftof8KAFT0mE0FdHCRKCGbKy49Y1XEamXOVT5dm3H4kWI
XxTxeGpxGgPNzwQ3LZxC2ky7xiiVp2KOX0BalSfje191QsuTzdHo4Zq7KJe90VLhNxjLjE9WA/U1
yxtToH5fcbTgzvYCBQz5Wt7RHedj2iVrqpiARF5OfkMgOTo7O8QXnyr7DO/c5waDHd0wjbTMEcDq
05HefL6F+ye6QmwUL0k86KCzrceyDQImLMjFTBu6OAvr1iWgbHO13eMshp33lVVMul0jruOY71fh
iuSiinRqOKzAkOksl4yg5AfpGnCyO2HQ2c8tNfwUfVDWAvEMchCEgi8tqN9RS4P3xz+4Z97Bu/Mu
ehp+u8n4nz1rhuAgRfyWIdpsOP02eS25a3ZWehw47KLEeLJEGk8fuBUUe6U9bFzE2/uf6aNykXy0
r655gQUrshTBgIeQ5sn+NaVtWH81Y1HT7rBHGz7BWQ4DTOkQyzhdWNWsVw29lTokGC9nfDsUMDZq
fPyyl+ZjaikMEpPXzqjil7XDG4kiss2TwXzQhdbvrfv1PYgCQvnpBd+XFtDJaqj8taLRFvv3ljH3
Hu9N2vrzPaqtSHKckRheqFaq1eiY+zvqeejOqFrvkG9vWQckMrZ7QNAy13OHAlaivJBzEd1vFEoT
gvD8yryDlsUMa3WYsQQKmqMecwC7ouhgOmYEv8+7FpBjcuicAstcroL+8doWlCq5MDUpfBLyoS6n
IjXBZ/F2gX2jzTT5j2H6aUMrNxQDGZGYhNG8JiiuBedH8pLeYjtTlPIFpPb/yxJte4ULztenylT5
KFSURA3bQneQ0zhhfLMrp6+vBKfp1aRJ2By/4In3N8yL1IxBZn7sYW9+3RqxB2oioaxG6NXeLTrC
1ThvFmPkR7cpchRjpycBYCJ2HyyrI3BO8fMytXXEpvcAcfRZxN4bo5+/3dvn62XcKIKlFXIvnWsF
bdrPW0mu553coiBkgtOrNFY3NCYJTGs0Me+ivhKNqmMCUL4QSNtrF9zamGnHLcPRFyDytMvTpMJL
/JGRDcrs8H8AJs0aI+r9U4UJB7NMlNxqtqWmVz4pjoLNqrU7D7mAd2+jZ6ooV47N2gIWNWZb0Mhc
BDGYptWkhmwNG+hleuIZQwUU48XZqXAU4/uO5da2HWcPN4fVPzFop+NWasPKhaS3aWS+x2+bCqBV
AJvkALKAWw+d3i+5ZsG1D0lOL9F0Ri8zHTECif+KQLFBAqGQj+SehhLF546gbCxVy/AeiL57JX7a
bAG4vvNgH5reBdNReEOj0geJwhltXVECV4Rf4QBVs0VL5xsYveAxeTsfvzr5UcIIr+1Hn2ODiLX/
vacHkz5KM6frGoLpIbNlGpSIR7ONxhXzLW0SdttQoDNnCiMWzOU8v4bxFMk2ptY/9fAzyOdJCF65
UeADrwju4xv2nDY=
`protect end_protected
|
apache-2.0
|
0595e3febf8a4bc3e96af963f614a6e7
| 0.920927 | 1.927161 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/roms/vga.vhdl
| 1 | 1,628 |
-- Generated by tools/generate-rom.pl
-- Template: https://www.xilinx.com/support/answers/8183.html
-- But changed manually afterwards
library ieee;
use ieee.std_logic_1164.all;
use work.txt_utils.all;
use work.arch_defs.all;
use work.utils.all;
entity rom_vga is
port ( a: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0);
en: in std_logic
);
attribute syn_romstyle : string;
attribute syn_romstyle of z : signal is "select_rom";
end rom_vga;
architecture rtl of rom_vga is
signal my_z : word_t;
begin
z <= my_z when en = '1' else HI_Z;
process(a)
begin
if en = '1' then
printf("Address = %s\n", a);
case a is
-- _start:
-- FIXME the first instruction won't be executed.
-- No idea why, so keep that in mind and place a nop there or something
-- 00000000 <_start>:
when X"0000_0000" => my_z <= X"00000000"; -- nop
when X"0000_0004" => my_z <= X"3c1c1000"; -- lui gp,0x1000
when X"0000_0008" => my_z <= X"00001025"; -- move v0,zero
when X"0000_000c" => my_z <= X"3442001c"; -- ori v0,v0,0x1c
when X"0000_0010" => my_z <= X"a3820000"; -- sb v0,0(gp)
when X"0000_0014" => my_z <= X"83820000"; -- lb v1,0(gp)
when X"0000_0018" => my_z <= X"08000000"; -- j 0 <_start>
when others => null;
end case;
end if;
end process;
end rtl;
|
gpl-3.0
|
d917219b20408598269ddf7bf081d79f
| 0.512899 | 3.3706 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover.vhd
| 4 | 74,538 |
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_9.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_9.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_9.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_9.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_9.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_9.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_9.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_9.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
bsd-3-clause
|
34d92aec82f12f15f83c106b9dcc080a
| 0.402788 | 4.165065 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_1_0/mig_wrap_proc_sys_reset_1_0_sim_netlist.vhdl
| 1 | 31,810 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
-- mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_cdc_sync;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_1_0_cdc_sync_0 : entity is "cdc_sync";
end mig_wrap_proc_sys_reset_1_0_cdc_sync_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_upcnt_n;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_lpf;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.mig_wrap_proc_sys_reset_1_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.mig_wrap_proc_sys_reset_1_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => Q,
I2 => lpf_exr,
I3 => lpf_asr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end mig_wrap_proc_sys_reset_1_0_sequence_psr;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.mig_wrap_proc_sys_reset_1_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is "virtex7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of mig_wrap_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
end mig_wrap_proc_sys_reset_1_0_proc_sys_reset;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.mig_wrap_proc_sys_reset_1_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.mig_wrap_proc_sys_reset_1_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mig_wrap_proc_sys_reset_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mig_wrap_proc_sys_reset_1_0 : entity is "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mig_wrap_proc_sys_reset_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mig_wrap_proc_sys_reset_1_0 : entity is "proc_sys_reset,Vivado 2016.4";
end mig_wrap_proc_sys_reset_1_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_1_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.mig_wrap_proc_sys_reset_1_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
mit
|
9da7ec476c71856e33d5d4ec8b77bdcf
| 0.569821 | 2.854963 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd
| 4 | 11,936 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
bsd-3-clause
|
a2609b43a4670eee4a4d7dce44259558
| 0.454675 | 4.420741 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_reset.vhd
| 4 | 39,337 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
bsd-3-clause
|
9beb23aea61d15a18624dc30c0621008
| 0.461576 | 4.131604 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer_control_bridge.vhd
| 1 | 3,863 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 31, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Timer Control Register Bridge.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! The Timer Control Register Bridge entity acts as a register
--! stage between the AXI4-Lite Controllers and the Timer Core's
--! Controller. This is only needed to ensure the acknowledgement
--! can only be set high for a single clock cycle, as required by
--! the Controller.
entity plasoc_timer_control_bridge is
generic (
-- Slave AXI4-Lite parameters.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
timer_width : integer := 16; --! Defines the width of the Trigger and Tick Value registers.
start_bit_loc : integer := 0; --! For the Start bit, defines the bit location in the Control register.
reload_bit_loc : integer := 1; --! For the Reload bit, defines the bit location in the Control register.
ack_bit_loc : integer := 2; --! For the Acknowledge bit, defines the bit location in the Control register.
done_bit_loc : integer := 3 --! For the Done bit, defines the bit location in the Control register.
);
port (
-- Global interface.
clock : in std_logic; --! Defines the AXI4-Lite Address Width.
nreset : in std_logic; --! Reset on low.
-- Controller interface.
start : out std_logic := '0'; --! Starts the operation when high.
reload : out std_logic := '0'; --! Enables reloading when high.
ack : out std_logic := '0'; --! Sets Done low if the core is running with Reload.
done : in std_logic; --! If Start is high and Tick Value equals Trigger Value, Done is set high.
-- Register interface.
reg_in_valid : in std_logic; --! When high, enables writing of the Control register.
reg_in_control : in std_logic_vector(axi_data_width-1 downto 0); --! New data for the Control register.
reg_out_control : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0') --! Current data for the Control register.
);
end plasoc_timer_control_bridge;
architecture Behavioral of plasoc_timer_control_bridge is
begin
-- Adds a register stage between the axi interfaces and the timer controller.
process (clock)
begin
-- Perform operations in synch with rising edge of clock.
if rising_edge(clock) then
-- Reset on low.
if nreset='0' then
reg_out_control <= (others=>'0');
start <= '0';
reload <= '0';
ack <= '0';
-- Normal operation when reset is high.
else
-- Sample control in interface when valid data is available.
if reg_in_valid='1' then
-- Set the start control signal and corresponding control out bit.
start <= reg_in_control(start_bit_loc);
reg_out_control(start_bit_loc) <= reg_in_control(start_bit_loc);
-- Set the read control signal and corresponding control out bit.
reload <= reg_in_control(reload_bit_loc);
reg_out_control(reload_bit_loc) <= reg_in_control(reload_bit_loc);
-- Set the ack control signal.
ack <= reg_in_control(ack_bit_loc);
else
-- The default state of the acknowledgement should be low.
ack <= '0';
end if;
-- Sample the done bit.
reg_out_control(done_bit_loc) <= done;
end if;
end if;
end process;
end Behavioral;
|
mit
|
c063950e22c957eb6d9e350f28af36cc
| 0.575718 | 4.340449 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma.vhd
| 4 | 126,887 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
-- coverage off
max_value := "11100";
-- coverage on
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value := 32;
end if;
return(addr_value);
end function width_calc;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant ADDR_WIDTH : integer := width_calc (C_M_AXI_SG_ADDR_WIDTH);
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 4;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
constant CMD_WIDTH : integer := ((8*C_ENABLE_MULTI_CHANNEL)+ ADDR_WIDTH+ CMD_BASE_WIDTH) ;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
signal bd_eq : std_logic;
signal m_axi_sg_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_sg_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_mm2s_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_s2mm_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1_8.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1_8.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1_2.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_ACTUAL_ADDR => C_M_AXI_SG_ADDR_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr_internal ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr_internal ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ,
bd_eq => bd_eq
);
m_axi_sg_awaddr <= m_axi_sg_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_araddr <= m_axi_sg_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1_8.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1_8.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1_8.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1_8.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1_8.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1_8.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1_9.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_CMD_WIDTH => CMD_WIDTH,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr_internal ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr_internal ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
bsd-3-clause
|
58cfd5ca64be371dff0c84519c72fa83
| 0.438493 | 3.785073 | false | false | false | false |
tmeissner/cryptocores
|
ctraes/sim/vhdl/tb_ctraes.vhd
| 1 | 4,567 |
-- ======================================================================
-- AES Counter mode testbench
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use std.env.all;
entity tb_ctraes is
end entity tb_ctraes;
architecture sim of tb_ctraes is
constant C_NONCE_WIDTH : natural range 64 to 96 := 96;
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_start : std_logic := '0';
signal s_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1) := (others => '0');
signal s_key : std_logic_vector(0 to 127) := (others => '0');
signal s_datain : std_logic_vector(0 to 127) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptin : std_logic;
signal s_dataout : std_logic_vector(0 to 127);
signal s_validout : std_logic := '0';
signal s_acceptout : std_logic := '0';
procedure cryptData(datain : in std_logic_vector(0 to 127);
key : in std_logic_vector(0 to 127);
iv : in std_logic_vector(0 to 127);
start : in boolean;
final : in boolean;
dataout : out std_logic_vector(0 to 127);
bytelen : in integer) is
begin
report "VHPIDIRECT cryptData" severity failure;
end procedure;
attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
variable v_data : std_logic_vector(0 to 127);
begin
for i in 0 to 15 loop
for y in 0 to 7 loop
v_data((i*8)+y) := datain((i*8)+7-y);
end loop;
end loop;
return v_data;
end function;
begin
i_ctraes : entity work.ctraes
generic map (
NONCE_WIDTH => C_NONCE_WIDTH
)
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
nonce_i => s_nonce,
key_i => s_key,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptin,
data_o => s_dataout,
valid_o => s_validout,
accept_i => s_acceptout
);
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
process is
variable v_key : std_logic_vector(0 to 127);
variable v_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1);
variable v_datain : std_logic_vector(0 to 127);
variable v_dataout : std_logic_vector(0 to 127);
variable v_random : RandomPType;
begin
v_random.InitSeed(v_random'instance_name);
wait until s_reset = '1' and rising_edge(s_clk);
-- ENCRYPTION TESTs
report "Test CTR-AES encryption";
s_start <= '1';
v_nonce := v_random.RandSlv(s_nonce'length);
v_key := v_random.RandSlv(128);
for i in 0 to 31 loop
v_datain := v_random.RandSlv(128);
s_validin <= '1';
s_key <= v_key;
s_nonce <= v_nonce;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), swap(v_nonce & 32x"0"), i = 0, i = 31, v_dataout, v_datain'length/8);
wait until s_acceptin = '1' and rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
wait until s_validout = '1' and rising_edge(s_clk);
s_acceptout <= '1';
assert s_dataout = swap(v_dataout)
report "Encryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
severity failure;
wait until rising_edge(s_clk);
s_acceptout <= '0';
end loop;
-- Watchdog
wait for 100 ns;
report "Simulation finished without errors";
finish(0);
end process;
end architecture sim;
|
gpl-2.0
|
e8338272e6468509c4e495e36aee3da5
| 0.582877 | 3.510377 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/async_ram.vhdl
| 1 | 2,246 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.utils.all;
use work.memory_map.all;
use work.txt_utils.all;
entity async_ram is
generic (
MEMSIZE :integer := 8
);
port (
address : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
en : in std_logic
);
end entity;
architecture behav of async_ram is
signal data_out : word_t;
type ram_t is array (integer range <>)of byte_t;
signal mem : ram_t (0 to MEMSIZE-1);
signal mem_word0 : word_t;
constant NOCARE : byte_t := (others => '-');
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
-- FIXME use size of ram for masking
memwrite: process (address, din, en, wr)
variable index : natural;
begin
index := vtou(address and not mmap(mmap_ram).base);
if en = '1' and wr = '1' then
case size is
when WIDTH_BYTE => mem(index ) <= din( 7 downto 0);
when WIDTH_HALF => mem(index+0) <= din(15 downto 8);
mem(index+1) <= din(7 downto 0);
when WIDTH_WORD => mem(index+0) <= din(31 downto 24);
mem(index+1) <= din(23 downto 16);
mem(index+2) <= din(15 downto 8);
mem(index+3) <= din( 7 downto 0);
when others => null;
end case;
end if;
end process;
memread: process (address, en, wr, size, mem)
variable index : natural;
begin
index := vtou(address and not mmap(mmap_ram).base);
-- printf(ANSI_GREEN & " iNDEX is %d\n", index);
if en = '1' and wr = '0' then
case size is
when WIDTH_BYTE => data_out <= NOCARE & NOCARE & NOCARE & mem(0);
when WIDTH_HALF => data_out <= NOCARE & NOCARE & mem(0) & mem(1);
when WIDTH_WORD => data_out <= mem(0) & mem(1) & mem(2) & mem(3);
when others => null;
end case;
end if;
end process;
mem_word0 <= mem(0) & mem(1) & mem(2) & mem(3); -- this is crappy
end behav;
|
gpl-3.0
|
9b6fe503e6d84485e9d914b099dec50c
| 0.501781 | 3.537008 | false | false | false | false |
makestuff/dvr-connectors
|
conv-8to16/vhdl/conv_8to16.vhdl
| 1 | 2,528 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_8to16 is
port(
-- System clock
clk_in : in std_logic;
reset_in : in std_logic;
-- 8-bit data coming in
data8_in : in std_logic_vector(7 downto 0);
valid8_in : in std_logic;
ready8_out : out std_logic;
-- 16-bit data going out
data16_out : out std_logic_vector(15 downto 0);
valid16_out : out std_logic;
ready16_in : in std_logic
);
end entity;
architecture rtl of conv_8to16 is
type StateType is (
S_WAIT_MSB,
S_WAIT_LSB
);
signal state : StateType := S_WAIT_MSB;
signal state_next : StateType;
signal msb : std_logic_vector(7 downto 0) := (others => '0');
signal msb_next : std_logic_vector(7 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WAIT_MSB;
msb <= (others => '0');
else
state <= state_next;
msb <= msb_next;
end if;
end if;
end process;
-- Next state logic
--process(state, msb, data8_in, valid8_in)
process(state, msb, data8_in, valid8_in, ready16_in)
begin
state_next <= state;
msb_next <= msb;
valid16_out <= '0';
case state is
-- Wait for the LSB to arrive:
when S_WAIT_LSB =>
ready8_out <= ready16_in; -- ready for data from 8-bit side
data16_out <= msb & data8_in;
if ( valid8_in = '1' and ready16_in = '1' ) then
valid16_out <= '1';
state_next <= S_WAIT_MSB;
end if;
-- Wait for the MSB to arrive:
when others =>
ready8_out <= '1'; -- ready for data from 8-bit side
data16_out <= (others => 'X');
if ( valid8_in = '1' ) then
msb_next <= data8_in;
state_next <= S_WAIT_LSB;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
40f73fbf6b49f125010dd98e6e85cf90
| 0.638845 | 2.98818 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_lite_if.vhd
| 4 | 61,580 |
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
library lib_cdc_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
bsd-3-clause
|
1ad152b1005a967883da77d2dd8e43fe
| 0.42634 | 4.120717 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/hdl/mig_wrap_wrapper.vhd
| 1 | 9,280 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
--Date : Mon Mar 27 01:47:30 2017
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target mig_wrap_wrapper.bd
--Design : mig_wrap_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_wrapper is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
sys_rst : in STD_LOGIC
);
end mig_wrap_wrapper;
architecture STRUCTURE of mig_wrap_wrapper is
component mig_wrap is
port (
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_cas_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
sys_rst : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC
);
end component mig_wrap;
begin
mig_wrap_i: component mig_wrap
port map (
ACLK => ACLK,
ARESETN => ARESETN,
DDR2_addr(12 downto 0) => DDR2_addr(12 downto 0),
DDR2_ba(2 downto 0) => DDR2_ba(2 downto 0),
DDR2_cas_n => DDR2_cas_n,
DDR2_ck_n(0) => DDR2_ck_n(0),
DDR2_ck_p(0) => DDR2_ck_p(0),
DDR2_cke(0) => DDR2_cke(0),
DDR2_cs_n(0) => DDR2_cs_n(0),
DDR2_dm(1 downto 0) => DDR2_dm(1 downto 0),
DDR2_dq(15 downto 0) => DDR2_dq(15 downto 0),
DDR2_dqs_n(1 downto 0) => DDR2_dqs_n(1 downto 0),
DDR2_dqs_p(1 downto 0) => DDR2_dqs_p(1 downto 0),
DDR2_odt(0) => DDR2_odt(0),
DDR2_ras_n => DDR2_ras_n,
DDR2_we_n => DDR2_we_n,
S00_ARESETN => S00_ARESETN,
S00_AXI_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_arid(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_arlock(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
S00_AXI_arready => S00_AXI_arready,
S00_AXI_arregion(3 downto 0) => S00_AXI_arregion(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
S00_AXI_arvalid => S00_AXI_arvalid,
S00_AXI_awaddr(31 downto 0) => S00_AXI_awaddr(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_awburst(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_awcache(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_awid(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_awlen(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_awlock(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_awprot(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_awqos(3 downto 0),
S00_AXI_awready => S00_AXI_awready,
S00_AXI_awregion(3 downto 0) => S00_AXI_awregion(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_awsize(2 downto 0),
S00_AXI_awvalid => S00_AXI_awvalid,
S00_AXI_bid(3 downto 0) => S00_AXI_bid(3 downto 0),
S00_AXI_bready => S00_AXI_bready,
S00_AXI_bresp(1 downto 0) => S00_AXI_bresp(1 downto 0),
S00_AXI_bvalid => S00_AXI_bvalid,
S00_AXI_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_rid(3 downto 0),
S00_AXI_rlast => S00_AXI_rlast,
S00_AXI_rready => S00_AXI_rready,
S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
S00_AXI_rvalid => S00_AXI_rvalid,
S00_AXI_wdata(31 downto 0) => S00_AXI_wdata(31 downto 0),
S00_AXI_wlast => S00_AXI_wlast,
S00_AXI_wready => S00_AXI_wready,
S00_AXI_wstrb(3 downto 0) => S00_AXI_wstrb(3 downto 0),
S00_AXI_wvalid => S00_AXI_wvalid,
clk_ref_i => clk_ref_i,
sys_rst => sys_rst
);
end STRUCTURE;
|
mit
|
3ff764b25d522eb6556cb6aa4c48e61f
| 0.607112 | 2.860666 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/testbench_vivado_0.vhd
| 1 | 10,953 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the testbench for simulating the
--! Plasma-SoC.
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
use work.boot_pack.all;
entity testbench_vivado_0 is
generic ( gpio_width : integer := 16; input_delay : time := 0 ns );
end testbench_vivado_0;
architecture Behavioral of testbench_vivado_0 is
component axiplasma_wrapper is
generic (
lower_app : string := "boot";
upper_app : string := "main";
upper_ext : boolean := false);
port(
raw_clock : in std_logic; -- 100 MHz on the Nexys 4.
raw_nreset : in std_logic;
gpio_output : out std_logic_vector(default_data_out_width-1 downto 0);
gpio_input : in std_logic_vector(default_data_in_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC);
end component;
constant clock_period : time := 10 ns;
constant uart_period : time := 104167 ns;
constant time_out_threshold : integer := 2**30;
subtype gpio_type is std_logic_vector(gpio_width-1 downto 0);
signal raw_clock : std_logic := '1';
signal raw_nreset : std_logic := '0';
signal gpio_output : gpio_type;
signal gpio_input : gpio_type := (others=>'0');
signal uart_tx : std_logic;
signal uart_clock : std_logic := '1';
signal uart_tx_data_avail : std_logic := '0';
signal uart_tx_data_ack : std_logic := '0';
signal uart_tx_started : boolean := false;
signal uart_tx_counter : integer range 0 to 8 := 0;
signal uart_tx_buffer : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_tx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx : std_logic;
signal uart_rx_enable : std_logic := '0';
signal uart_rx_done : std_logic := '0';
signal uart_rx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx_counter : integer range 0 to 9 := 0;
signal boot_checksum : std_logic_vector(7 downto 0) := (others=>'0');
begin
axiplasma_wrapper_inst : axiplasma_wrapper
port map (
raw_clock => raw_clock,
raw_nreset => raw_nreset,
gpio_output => gpio_output,
gpio_input => gpio_input,
uart_tx => uart_tx,
uart_rx => uart_rx,
DDR2_addr => open,
DDR2_ba => open,
DDR2_cas_n => open,
DDR2_ck_n => open,
DDR2_ck_p => open,
DDR2_cke => open,
DDR2_cs_n => open,
DDR2_dm => open,
DDR2_dq => open,
DDR2_dqs_n => open,
DDR2_dqs_p => open,
DDR2_odt => open,
DDR2_ras_n => open,
DDR2_we_n => open);
raw_clock <= not raw_clock after clock_period/2;
raw_nreset <= '1' after 10*clock_period+input_delay;
-- Get uart_tx
uart_clock <= not uart_clock after uart_period/2;
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_tx_started then
uart_tx_counter <= uart_tx_counter+1;
if uart_tx_counter=8 then
uart_tx_data <= uart_tx_buffer;
uart_tx_started <= false;
else
uart_tx_buffer(uart_tx_counter) <= uart_tx;
end if;
elsif uart_tx='0' then
uart_tx_started <= true;
uart_tx_counter <= 0;
end if;
if uart_tx_data_ack='1' then
uart_tx_data_avail <= '0';
elsif uart_tx_started and uart_tx_counter=8 then
uart_tx_data_avail <= '1';
end if;
end if;
end process;
-- Set uart_rx
uart_rx_done <= '1' when uart_rx_counter=9 else '0';
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_rx_enable='1' then
if uart_rx_counter/=9 then
uart_rx_counter <= uart_rx_counter+1;
if uart_rx_counter=0 then
uart_rx <= '0';
elsif uart_rx_counter<= 8 then
uart_rx <= uart_rx_data(uart_rx_counter-1);
end if;
else
uart_rx <= '1';
end if;
else
uart_rx_counter <= 0;
uart_rx <= '1';
end if;
end if;
end process;
process
constant word_width : integer := 32;
subtype byte_type is std_logic_vector(7 downto 0);
subtype word_type is std_logic_vector(word_width-1 downto 0);
constant BOOT_LOADER_START_WORD : word_type := x"f0f0f0f0";
constant BOOT_LOADER_ACK_SUCCESS_BYTE : byte_type := x"01";
constant BOOT_LOADER_ACK_FAILURE_BYTE : byte_type := x"02";
constant BOOT_LOADER_STATUS_MORE : byte_type := x"01";
constant BOOT_LOADER_STATUS_DONE : byte_type := x"02";
constant BOOT_LOADER_CHECKSUM_DIVISOR : integer := 230;
variable word : word_type;
variable byte : byte_type;
variable app_data : ram_type := load_hex;
variable app_ptr : integer := 0;
procedure set_uart_rx( byte : in byte_type ) is
begin
uart_rx_data <= byte;
uart_rx_enable <= '1';
wait until uart_rx_done='1';
wait for uart_period;
uart_rx_enable <= '0';
wait for uart_period;
end;
procedure set_uart_word ( word : in word_type ) is
begin
for each_byte in 0 to word_width/8-1 loop
set_uart_rx(word(7+each_byte*8 downto each_byte*8));
end loop;
end;
procedure get_uart_tx is
begin
wait until uart_tx_data_avail='1';
wait for uart_period;
byte := uart_tx_data;
uart_tx_data_ack <= '1';
wait for uart_period;
uart_tx_data_ack <= '0';
wait for uart_period;
end;
begin
-- wait until raw_nreset='1';
-- wait until gpio_output=X"0001";
-- wait for 2 ms;
-- set_uart_word(BOOT_LOADER_START_WORD);
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- while true loop
-- -- instruction
-- word := app_data(app_ptr);
-- set_uart_word(word);
-- -- checksum
-- word := std_logic_vector(unsigned(word) mod BOOT_LOADER_CHECKSUM_DIVISOR);
-- boot_checksum <= word(7 downto 0);
-- set_uart_rx(word(7 downto 0));
-- -- status
-- app_ptr := app_ptr+1;
-- --if app_ptr=ram_size then
-- if app_ptr=13 then
-- set_uart_rx(BOOT_LOADER_STATUS_DONE);
-- exit;
-- else
-- set_uart_rx(BOOT_LOADER_STATUS_MORE);
-- end if;
-- -- ack
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- end loop;
wait;
end process;
-- Run testbench application.
process
-- This procedure should force the simulation to stop if a
-- problem becomes apparent.
procedure assert_procedure( state : boolean; mesg : string ) is
variable breaksimulation : std_logic_vector(0 downto 0);
begin
if not state then
assert False report mesg severity error;
breaksimulation(1) := '1';
end if;
end;
-- The procedure sets a single specified bit of the gpio input interface.
procedure set_gpio_input( gpio_index : integer ) is
variable gpio_input_buff : gpio_type := (others=>'0');
begin
gpio_input_buff(gpio_index) := '1';
gpio_input <= gpio_input_buff;
wait for clock_period;
end;
-- Waits for the corresponding output response. If it takes too long,
-- it is assumed there is an error and the simulation should end as a result.
procedure wait_for_gpio_output is
variable assert_counter : integer := 0;
begin
while gpio_output/=gpio_input loop
assert_procedure( state => assert_counter/=time_out_threshold, mesg => "Timeout occurred." );
assert_counter := assert_counter+1;
wait for clock_period;
end loop;
wait for clock_period;
end;
begin
wait until raw_nreset='1';
wait until gpio_output=X"0001";
wait for 500 us;
gpio_input <= X"0003" after input_delay;
wait for 2 ms;
gpio_input <= X"00f3" after input_delay;
wait for 2 ms;
while True loop
gpio_input <= X"00f1" after input_delay;
wait for 50 us;
gpio_input <= X"00f0" after input_delay;
wait for 50 us;
gpio_input <= X"00f5" after input_delay;
wait for 50 us;
gpio_input <= X"00ff" after input_delay;
wait for 50 us;
gpio_input <= X"05f7" after input_delay;
wait for 50 us;
gpio_input <= X"10f0" after input_delay;
wait for 50 us;
end loop;
wait;
end process;
end Behavioral;
|
mit
|
67c3adb5bfd2d20a95c9c0c570664f5c
| 0.506893 | 3.851266 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/axiplasma_wrapper.vhd
| 1 | 112,807 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Wrapper Plasma-SoC Top Module.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.plasoc_cpu;
use work.plasoc_int_pack.plasoc_int;
use work.plasoc_int_pack.default_interrupt_total;
use work.plasoc_timer_pack.plasoc_timer;
use work.plasoc_gpio_pack.plasoc_gpio;
use work.plasoc_gpio_pack.default_data_out_width;
use work.plasoc_gpio_pack.default_data_in_width;
use work.plasoc_uart_pack.plasoc_uart;
use work.plasoc_0_crossbar_wrap_pack.plasoc_0_crossbar_wrap;
use work.plasoc_0_crossbar_wrap_pack.clogb2;
use work.plasoc_axi4_full2lite_pack.plasoc_axi4_full2lite;
entity axiplasma_wrapper is
generic (
lower_app : string := "boot";
upper_app : string := "none";
upper_ext : boolean := true);
port(
raw_clock : in std_logic; -- 100 MHz on the Nexys 4.
raw_nreset : in std_logic;
gpio_output : out std_logic_vector(default_data_out_width-1 downto 0);
gpio_input : in std_logic_vector(default_data_in_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC);
end axiplasma_wrapper;
architecture Behavioral of axiplasma_wrapper is
component mig_wrap_wrapper is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
sys_rst : in STD_LOGIC);
end component;
-- Component declarations.
component bram is
generic (
select_app : string := "none"; -- jump, boot, main
address_width : integer := 18;
data_width : integer := 32;
bram_depth : integer := 65536);
port(
bram_rst_a : in std_logic;
bram_clk_a : in std_logic;
bram_en_a : in std_logic;
bram_we_a : in std_logic_vector(data_width/8-1 downto 0);
bram_addr_a : in std_logic_vector(address_width-1 downto 0);
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0);
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0'));
end component;
component axi_cdma_0 is
port (
m_axi_aclk : in std_logic;
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
cdma_introut : out std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(5 downto 0);
s_axi_lite_wready : out std_logic;
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bready : in std_logic;
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_arready : out std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_araddr : in std_logic_vector(5 downto 0);
s_axi_lite_rready : in std_logic;
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_arready : in std_logic;
m_axi_arvalid : out std_logic;
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_rready : out std_logic;
m_axi_rvalid : in std_logic;
m_axi_rdata : in std_logic_vector(31 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic;
m_axi_awready : in std_logic;
m_axi_awvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_wready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wdata : out std_logic_vector(31 downto 0);
m_axi_wstrb : out std_logic_vector(3 downto 0);
m_axi_wlast : out std_logic;
m_axi_bready : out std_logic;
m_axi_bvalid : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
cdma_tvect_out : out std_logic_vector(31 downto 0));
end component;
component clk_wiz_0 is
port (
aclk : out std_logic;
ddr_aclk : out std_logic;
resetn : in std_logic;
locked : out std_logic;
raw_clock : in std_logic);
end component;
component proc_sys_reset_0 is
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
mb_debug_sys_rst : in std_logic;
dcm_locked : in std_logic;
mb_reset : out std_logic;
bus_struct_reset : out std_logic_vector(0 downto 0);
peripheral_reset : out std_logic_vector(0 downto 0);
interconnect_aresetn : out std_logic_vector(0 downto 0);
peripheral_aresetn : out std_logic_vector(0 downto 0));
end component;
component axi_bram_ctrl_0 is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awid : in std_logic_vector(0 downto 0);
s_axi_awaddr : in std_logic_vector(15 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(0 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(0 downto 0);
s_axi_araddr : in std_logic_vector(15 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(0 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector(3 downto 0);
bram_addr_a : out std_logic_vector(15 downto 0);
bram_wrdata_a : out std_logic_vector(31 downto 0);
bram_rddata_a : in std_logic_vector(31 downto 0));
end component;
component axi_bram_ctrl_1 is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awid : in std_logic_vector(0 downto 0);
s_axi_awaddr : in std_logic_vector(17 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(0 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(0 downto 0);
s_axi_araddr : in std_logic_vector(17 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(0 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector(3 downto 0);
bram_addr_a : out std_logic_vector(17 downto 0);
bram_wrdata_a : out std_logic_vector(31 downto 0);
bram_rddata_a : in std_logic_vector(31 downto 0));
end component;
constant axi_address_width : integer := 32;
constant axi_data_width : integer := 32;
constant axi_master_amount : integer := 5;
constant axi_slave_amount : integer := 2;
constant axi_slave_id_width : integer := 0;
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
constant axi_lite_address_width : integer := 16; -- a misnomer.
constant axi_ram_address_width : integer := 18;
constant axi_ram_depth : integer := 65536;
signal aclk : std_logic;
signal ddr_aclk : std_logic;
signal aresetn : std_logic_vector(0 downto 0);
signal cross_aresetn : std_logic_vector(0 downto 0);
signal dcm_locked : std_logic;
signal cpu_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_axi_full_awlock : std_logic;
signal cpu_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_axi_full_awvalid : std_logic;
signal cpu_axi_full_awready : std_logic;
signal cpu_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_axi_full_wlast : std_logic;
signal cpu_axi_full_wvalid : std_logic;
signal cpu_axi_full_wready : std_logic;
signal cpu_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_axi_full_bvalid : std_logic;
signal cpu_axi_full_bready : std_logic;
signal cpu_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_axi_full_arlock : std_logic;
signal cpu_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_axi_full_arvalid : std_logic;
signal cpu_axi_full_arready : std_logic;
signal cpu_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_axi_full_rlast : std_logic;
signal cpu_axi_full_rvalid : std_logic;
signal cpu_axi_full_rready : std_logic;
signal cdma_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdma_axi_full_awlen : std_logic_vector(7 downto 0);
signal cdma_axi_full_awsize : std_logic_vector(2 downto 0);
signal cdma_axi_full_awburst : std_logic_vector(1 downto 0);
signal cdma_axi_full_awlock : std_logic;
signal cdma_axi_full_awcache : std_logic_vector(3 downto 0);
signal cdma_axi_full_awprot : std_logic_vector(2 downto 0);
signal cdma_axi_full_awqos : std_logic_vector(3 downto 0);
signal cdma_axi_full_awregion : std_logic_vector(3 downto 0);
signal cdma_axi_full_awvalid : std_logic;
signal cdma_axi_full_awready : std_logic;
signal cdma_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdma_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cdma_axi_full_wlast : std_logic;
signal cdma_axi_full_wvalid : std_logic;
signal cdma_axi_full_wready : std_logic;
signal cdma_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_bresp : std_logic_vector(1 downto 0);
signal cdma_axi_full_bvalid : std_logic;
signal cdma_axi_full_bready : std_logic;
signal cdma_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdma_axi_full_arlen : std_logic_vector(7 downto 0);
signal cdma_axi_full_arsize : std_logic_vector(2 downto 0);
signal cdma_axi_full_arburst : std_logic_vector(1 downto 0);
signal cdma_axi_full_arlock : std_logic;
signal cdma_axi_full_arcache : std_logic_vector(3 downto 0);
signal cdma_axi_full_arprot : std_logic_vector(2 downto 0);
signal cdma_axi_full_arqos : std_logic_vector(3 downto 0);
signal cdma_axi_full_arregion : std_logic_vector(3 downto 0);
signal cdma_axi_full_arvalid : std_logic;
signal cdma_axi_full_arready : std_logic;
signal cdma_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdma_axi_full_rresp : std_logic_vector(1 downto 0);
signal cdma_axi_full_rlast : std_logic;
signal cdma_axi_full_rvalid : std_logic;
signal cdma_axi_full_rready : std_logic;
signal bram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal bram_axi_full_awlen : std_logic_vector(7 downto 0);
signal bram_axi_full_awsize : std_logic_vector(2 downto 0);
signal bram_axi_full_awburst : std_logic_vector(1 downto 0);
signal bram_axi_full_awlock : std_logic;
signal bram_axi_full_awcache : std_logic_vector(3 downto 0);
signal bram_axi_full_awprot : std_logic_vector(2 downto 0);
signal bram_axi_full_awqos : std_logic_vector(3 downto 0);
signal bram_axi_full_awregion : std_logic_vector(3 downto 0);
signal bram_axi_full_awvalid : std_logic;
signal bram_axi_full_awready : std_logic;
signal bram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal bram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal bram_axi_full_wlast : std_logic;
signal bram_axi_full_wvalid : std_logic;
signal bram_axi_full_wready : std_logic;
signal bram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_bresp : std_logic_vector(1 downto 0);
signal bram_axi_full_bvalid : std_logic;
signal bram_axi_full_bready : std_logic;
signal bram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal bram_axi_full_arlen : std_logic_vector(7 downto 0);
signal bram_axi_full_arsize : std_logic_vector(2 downto 0);
signal bram_axi_full_arburst : std_logic_vector(1 downto 0);
signal bram_axi_full_arlock : std_logic;
signal bram_axi_full_arcache : std_logic_vector(3 downto 0);
signal bram_axi_full_arprot : std_logic_vector(2 downto 0);
signal bram_axi_full_arqos : std_logic_vector(3 downto 0);
signal bram_axi_full_arregion : std_logic_vector(3 downto 0);
signal bram_axi_full_arvalid : std_logic;
signal bram_axi_full_arready : std_logic;
signal bram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal bram_axi_full_rresp : std_logic_vector(1 downto 0);
signal bram_axi_full_rlast : std_logic;
signal bram_axi_full_rvalid : std_logic;
signal bram_axi_full_rready : std_logic;
signal bram_bram_rst_a : STD_LOGIC;
signal bram_bram_clk_a : STD_LOGIC;
signal bram_bram_en_a : STD_LOGIC;
signal bram_bram_we_a : STD_LOGIC_VECTOR(axi_data_width/8-1 DOWNTO 0);
signal bram_bram_addr_a : STD_LOGIC_VECTOR(axi_lite_address_width-1 DOWNTO 0);
signal bram_bram_wrdata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0);
signal bram_bram_rddata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0);
signal ram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal ram_axi_full_awlen : std_logic_vector(7 downto 0);
signal ram_axi_full_awsize : std_logic_vector(2 downto 0);
signal ram_axi_full_awburst : std_logic_vector(1 downto 0);
signal ram_axi_full_awlock : std_logic;
signal ram_axi_full_awcache : std_logic_vector(3 downto 0);
signal ram_axi_full_awprot : std_logic_vector(2 downto 0);
signal ram_axi_full_awqos : std_logic_vector(3 downto 0);
signal ram_axi_full_awregion : std_logic_vector(3 downto 0);
signal ram_axi_full_awvalid : std_logic;
signal ram_axi_full_awready : std_logic;
signal ram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal ram_axi_full_wlast : std_logic;
signal ram_axi_full_wvalid : std_logic;
signal ram_axi_full_wready : std_logic;
signal ram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_bresp : std_logic_vector(1 downto 0);
signal ram_axi_full_bvalid : std_logic;
signal ram_axi_full_bready : std_logic;
signal ram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal ram_axi_full_arlen : std_logic_vector(7 downto 0);
signal ram_axi_full_arsize : std_logic_vector(2 downto 0);
signal ram_axi_full_arburst : std_logic_vector(1 downto 0);
signal ram_axi_full_arlock : std_logic;
signal ram_axi_full_arcache : std_logic_vector(3 downto 0);
signal ram_axi_full_arprot : std_logic_vector(2 downto 0);
signal ram_axi_full_arqos : std_logic_vector(3 downto 0);
signal ram_axi_full_arregion : std_logic_vector(3 downto 0);
signal ram_axi_full_arvalid : std_logic;
signal ram_axi_full_arready : std_logic;
signal ram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_rresp : std_logic_vector(1 downto 0);
signal ram_axi_full_rlast : std_logic;
signal ram_axi_full_rvalid : std_logic;
signal ram_axi_full_rready : std_logic;
signal ram_axi_full_arlock_slv : std_logic_vector (0 downto 0);
signal ram_axi_full_awlock_slv : std_logic_vector (0 downto 0);
signal ram_axi_full_arid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_awid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_bid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_rid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_bram_rst_a : std_logic;
signal ram_bram_clk_a : std_logic;
signal ram_bram_en_a : std_logic;
signal ram_bram_we_a : std_logic_vector(axi_data_width/8-1 downto 0);
signal ram_bram_addr_a : std_logic_vector(axi_ram_address_width-1 downto 0);
signal ram_bram_wrdata_a : std_logic_vector(axi_data_width-1 downto 0);
signal ram_bram_rddata_a : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_awlen : std_logic_vector(7 downto 0);
signal int_axi_full_awsize : std_logic_vector(2 downto 0);
signal int_axi_full_awburst : std_logic_vector(1 downto 0);
signal int_axi_full_awlock : std_logic;
signal int_axi_full_awcache : std_logic_vector(3 downto 0);
signal int_axi_full_awprot : std_logic_vector(2 downto 0);
signal int_axi_full_awqos : std_logic_vector(3 downto 0);
signal int_axi_full_awregion : std_logic_vector(3 downto 0);
signal int_axi_full_awvalid : std_logic;
signal int_axi_full_awready : std_logic;
signal int_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_full_wlast : std_logic;
signal int_axi_full_wvalid : std_logic;
signal int_axi_full_wready : std_logic;
signal int_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_bresp : std_logic_vector(1 downto 0);
signal int_axi_full_bvalid : std_logic;
signal int_axi_full_bready : std_logic;
signal int_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_arlen : std_logic_vector(7 downto 0);
signal int_axi_full_arsize : std_logic_vector(2 downto 0);
signal int_axi_full_arburst : std_logic_vector(1 downto 0);
signal int_axi_full_arlock : std_logic;
signal int_axi_full_arcache : std_logic_vector(3 downto 0);
signal int_axi_full_arprot : std_logic_vector(2 downto 0);
signal int_axi_full_arqos : std_logic_vector(3 downto 0);
signal int_axi_full_arregion : std_logic_vector(3 downto 0);
signal int_axi_full_arvalid : std_logic;
signal int_axi_full_arready : std_logic;
signal int_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_rresp : std_logic_vector(1 downto 0);
signal int_axi_full_rlast : std_logic;
signal int_axi_full_rvalid : std_logic;
signal int_axi_full_rready : std_logic;
signal timer_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_awlen : std_logic_vector(7 downto 0);
signal timer_axi_full_awsize : std_logic_vector(2 downto 0);
signal timer_axi_full_awburst : std_logic_vector(1 downto 0);
signal timer_axi_full_awlock : std_logic;
signal timer_axi_full_awcache : std_logic_vector(3 downto 0);
signal timer_axi_full_awprot : std_logic_vector(2 downto 0);
signal timer_axi_full_awqos : std_logic_vector(3 downto 0);
signal timer_axi_full_awregion : std_logic_vector(3 downto 0);
signal timer_axi_full_awvalid : std_logic;
signal timer_axi_full_awready : std_logic;
signal timer_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_full_wlast : std_logic;
signal timer_axi_full_wvalid : std_logic;
signal timer_axi_full_wready : std_logic;
signal timer_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_bresp : std_logic_vector(1 downto 0);
signal timer_axi_full_bvalid : std_logic;
signal timer_axi_full_bready : std_logic;
signal timer_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_arlen : std_logic_vector(7 downto 0);
signal timer_axi_full_arsize : std_logic_vector(2 downto 0);
signal timer_axi_full_arburst : std_logic_vector(1 downto 0);
signal timer_axi_full_arlock : std_logic;
signal timer_axi_full_arcache : std_logic_vector(3 downto 0);
signal timer_axi_full_arprot : std_logic_vector(2 downto 0);
signal timer_axi_full_arqos : std_logic_vector(3 downto 0);
signal timer_axi_full_arregion : std_logic_vector(3 downto 0);
signal timer_axi_full_arvalid : std_logic;
signal timer_axi_full_arready : std_logic;
signal timer_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_rresp : std_logic_vector(1 downto 0);
signal timer_axi_full_rlast : std_logic;
signal timer_axi_full_rvalid : std_logic;
signal timer_axi_full_rready : std_logic;
signal gpio_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_awlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_awsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_awburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_awlock : std_logic;
signal gpio_axi_full_awcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_awqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_awregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_awvalid : std_logic;
signal gpio_axi_full_awready : std_logic;
signal gpio_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_full_wlast : std_logic;
signal gpio_axi_full_wvalid : std_logic;
signal gpio_axi_full_wready : std_logic;
signal gpio_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_bvalid : std_logic;
signal gpio_axi_full_bready : std_logic;
signal gpio_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_arlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_arsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_arburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_arlock : std_logic;
signal gpio_axi_full_arcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_arqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_arregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_arvalid : std_logic;
signal gpio_axi_full_arready : std_logic;
signal gpio_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_rlast : std_logic;
signal gpio_axi_full_rvalid : std_logic;
signal gpio_axi_full_rready : std_logic;
signal cdmareg_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdmareg_axi_full_awlen : std_logic_vector(7 downto 0);
signal cdmareg_axi_full_awsize : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_awburst : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_awlock : std_logic;
signal cdmareg_axi_full_awcache : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_awprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_awqos : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_awregion : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_awvalid : std_logic;
signal cdmareg_axi_full_awready : std_logic;
signal cdmareg_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdmareg_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cdmareg_axi_full_wlast : std_logic;
signal cdmareg_axi_full_wvalid : std_logic;
signal cdmareg_axi_full_wready : std_logic;
signal cdmareg_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_bresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_bvalid : std_logic;
signal cdmareg_axi_full_bready : std_logic;
signal cdmareg_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdmareg_axi_full_arlen : std_logic_vector(7 downto 0);
signal cdmareg_axi_full_arsize : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_arburst : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_arlock : std_logic;
signal cdmareg_axi_full_arcache : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_arprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_arqos : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_arregion : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_arvalid : std_logic;
signal cdmareg_axi_full_arready : std_logic;
signal cdmareg_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdmareg_axi_full_rresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_rlast : std_logic;
signal cdmareg_axi_full_rvalid : std_logic;
signal cdmareg_axi_full_rready : std_logic;
signal timer_extra_0_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_extra_0_axi_full_awlen : std_logic_vector(7 downto 0);
signal timer_extra_0_axi_full_awsize : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_awburst : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_awlock : std_logic;
signal timer_extra_0_axi_full_awcache : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_awprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_awqos : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_awregion : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_awvalid : std_logic;
signal timer_extra_0_axi_full_awready : std_logic;
signal timer_extra_0_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_extra_0_axi_full_wlast : std_logic;
signal timer_extra_0_axi_full_wvalid : std_logic;
signal timer_extra_0_axi_full_wready : std_logic;
signal timer_extra_0_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_bresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_bvalid : std_logic;
signal timer_extra_0_axi_full_bready : std_logic;
signal timer_extra_0_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_extra_0_axi_full_arlen : std_logic_vector(7 downto 0);
signal timer_extra_0_axi_full_arsize : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_arburst : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_arlock : std_logic;
signal timer_extra_0_axi_full_arcache : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_arprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_arqos : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_arregion : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_arvalid : std_logic;
signal timer_extra_0_axi_full_arready : std_logic;
signal timer_extra_0_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_full_rresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_rlast : std_logic;
signal timer_extra_0_axi_full_rvalid : std_logic;
signal timer_extra_0_axi_full_rready : std_logic;
signal uart_axi_full_awid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_awlen : std_logic_vector(7 downto 0);
signal uart_axi_full_awsize : std_logic_vector(2 downto 0);
signal uart_axi_full_awburst : std_logic_vector(1 downto 0);
signal uart_axi_full_awlock : std_logic;
signal uart_axi_full_awcache : std_logic_vector(3 downto 0);
signal uart_axi_full_awprot : std_logic_vector(2 downto 0);
signal uart_axi_full_awqos : std_logic_vector(3 downto 0);
signal uart_axi_full_awregion : std_logic_vector(3 downto 0);
signal uart_axi_full_awvalid : std_logic;
signal uart_axi_full_awready : std_logic;
signal uart_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_full_wlast : std_logic;
signal uart_axi_full_wvalid : std_logic;
signal uart_axi_full_wready : std_logic;
signal uart_axi_full_bid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_bresp : std_logic_vector(1 downto 0);
signal uart_axi_full_bvalid : std_logic;
signal uart_axi_full_bready : std_logic;
signal uart_axi_full_arid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_arlen : std_logic_vector(7 downto 0);
signal uart_axi_full_arsize : std_logic_vector(2 downto 0);
signal uart_axi_full_arburst : std_logic_vector(1 downto 0);
signal uart_axi_full_arlock : std_logic;
signal uart_axi_full_arcache : std_logic_vector(3 downto 0);
signal uart_axi_full_arprot : std_logic_vector(2 downto 0);
signal uart_axi_full_arqos : std_logic_vector(3 downto 0);
signal uart_axi_full_arregion : std_logic_vector(3 downto 0);
signal uart_axi_full_arvalid : std_logic;
signal uart_axi_full_arready : std_logic;
signal uart_axi_full_rid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_rresp : std_logic_vector(1 downto 0);
signal uart_axi_full_rlast : std_logic;
signal uart_axi_full_rvalid : std_logic;
signal uart_axi_full_rready : std_logic;
signal int_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal int_axi_lite_awprot : std_logic_vector(2 downto 0);
signal int_axi_lite_awvalid : std_logic;
signal int_axi_lite_awready : std_logic;
signal int_axi_lite_wvalid : std_logic;
signal int_axi_lite_wready : std_logic;
signal int_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_lite_bvalid : std_logic;
signal int_axi_lite_bready : std_logic;
signal int_axi_lite_bresp : std_logic_vector(1 downto 0);
signal int_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal int_axi_lite_arprot : std_logic_vector(2 downto 0);
signal int_axi_lite_arvalid : std_logic;
signal int_axi_lite_arready : std_logic;
signal int_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal int_axi_lite_rvalid : std_logic;
signal int_axi_lite_rready : std_logic;
signal int_axi_lite_rresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_axi_lite_awprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_awvalid : std_logic;
signal timer_axi_lite_awready : std_logic;
signal timer_axi_lite_wvalid : std_logic;
signal timer_axi_lite_wready : std_logic;
signal timer_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_lite_bvalid : std_logic;
signal timer_axi_lite_bready : std_logic;
signal timer_axi_lite_bresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_axi_lite_arprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_arvalid : std_logic;
signal timer_axi_lite_arready : std_logic;
signal timer_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal timer_axi_lite_rvalid : std_logic;
signal timer_axi_lite_rready : std_logic;
signal timer_axi_lite_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal gpio_axi_lite_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_awvalid : std_logic;
signal gpio_axi_lite_awready : std_logic;
signal gpio_axi_lite_wvalid : std_logic;
signal gpio_axi_lite_wready : std_logic;
signal gpio_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_lite_bvalid : std_logic;
signal gpio_axi_lite_bready : std_logic;
signal gpio_axi_lite_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal gpio_axi_lite_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_arvalid : std_logic;
signal gpio_axi_lite_arready : std_logic;
signal gpio_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal gpio_axi_lite_rvalid : std_logic;
signal gpio_axi_lite_rready : std_logic;
signal gpio_axi_lite_rresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal cdmareg_axi_lite_awprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_lite_awvalid : std_logic;
signal cdmareg_axi_lite_awready : std_logic;
signal cdmareg_axi_lite_wvalid : std_logic;
signal cdmareg_axi_lite_wready : std_logic;
signal cdmareg_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdmareg_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cdmareg_axi_lite_bvalid : std_logic;
signal cdmareg_axi_lite_bready : std_logic;
signal cdmareg_axi_lite_bresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal cdmareg_axi_lite_arprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_lite_arvalid : std_logic;
signal cdmareg_axi_lite_arready : std_logic;
signal cdmareg_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal cdmareg_axi_lite_rvalid : std_logic;
signal cdmareg_axi_lite_rready : std_logic;
signal cdmareg_axi_lite_rresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal uart_axi_lite_awprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_awvalid : std_logic;
signal uart_axi_lite_awready : std_logic;
signal uart_axi_lite_wvalid : std_logic;
signal uart_axi_lite_wready : std_logic;
signal uart_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_lite_bvalid : std_logic;
signal uart_axi_lite_bready : std_logic;
signal uart_axi_lite_bresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal uart_axi_lite_arprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_arvalid : std_logic;
signal uart_axi_lite_arready : std_logic;
signal uart_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_rvalid : std_logic;
signal uart_axi_lite_rready : std_logic;
signal uart_axi_lite_rresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_extra_0_axi_lite_awprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_lite_awvalid : std_logic;
signal timer_extra_0_axi_lite_awready : std_logic;
signal timer_extra_0_axi_lite_wvalid : std_logic;
signal timer_extra_0_axi_lite_wready : std_logic;
signal timer_extra_0_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_extra_0_axi_lite_bvalid : std_logic;
signal timer_extra_0_axi_lite_bready : std_logic;
signal timer_extra_0_axi_lite_bresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_extra_0_axi_lite_arprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_lite_arvalid : std_logic;
signal timer_extra_0_axi_lite_arready : std_logic;
signal timer_extra_0_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_lite_rvalid : std_logic;
signal timer_extra_0_axi_lite_rready : std_logic;
signal timer_extra_0_axi_lite_rresp : std_logic_vector(1 downto 0);
signal cpu_int : std_logic;
signal int_dev_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal timer_int : std_logic;
signal gpio_int : std_logic;
signal cdma_int : std_logic;
signal uart_int : std_logic;
signal timer_extra_0_int : std_logic;
begin
int_dev_ints(0) <= timer_int;
int_dev_ints(1) <= gpio_int;
int_dev_ints(2) <= cdma_int;
int_dev_ints(3) <= uart_int;
int_dev_ints(4) <= timer_extra_0_int;
cdma_axi_full_awlock <= '0';
cdma_axi_full_arlock <= '0';
ram_axi_full_arlock_slv(0) <= ram_axi_full_arlock;
ram_axi_full_awlock_slv(0) <= ram_axi_full_awlock;
ram_axi_full_arid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_arid;
ram_axi_full_awid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_awid;
ram_axi_full_bid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_bid;
ram_axi_full_rid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_rid;
-- Clock instantiation.
clk_wiz_inst : clk_wiz_0
port map (
aclk => aclk,
ddr_aclk => ddr_aclk,
resetn => raw_nreset,
locked => dcm_locked,
raw_clock => raw_clock);
-- Reset core instantiation.
proc_sys_reset_inst : proc_sys_reset_0
PORT map (
slowest_sync_clk => aclk,
ext_reset_in => raw_nreset,
aux_reset_in => '0',
mb_debug_sys_rst => '0',
dcm_locked => dcm_locked,
mb_reset => open,
bus_struct_reset => open,
peripheral_reset => open,
interconnect_aresetn => cross_aresetn,
peripheral_aresetn => aresetn);
-- Crossbar instantiation.
plasoc_0_crossbar_wrap_inst : plasoc_0_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_axi_full_awid,
cpu_s_axi_awaddr => cpu_axi_full_awaddr,
cpu_s_axi_awlen => cpu_axi_full_awlen,
cpu_s_axi_awsize => cpu_axi_full_awsize,
cpu_s_axi_awburst => cpu_axi_full_awburst,
cpu_s_axi_awlock => cpu_axi_full_awlock,
cpu_s_axi_awcache => cpu_axi_full_awcache,
cpu_s_axi_awprot => cpu_axi_full_awprot,
cpu_s_axi_awqos => cpu_axi_full_awqos,
cpu_s_axi_awregion => cpu_axi_full_awregion,
cpu_s_axi_awvalid => cpu_axi_full_awvalid,
cpu_s_axi_awready => cpu_axi_full_awready,
cpu_s_axi_wdata => cpu_axi_full_wdata,
cpu_s_axi_wstrb => cpu_axi_full_wstrb,
cpu_s_axi_wlast => cpu_axi_full_wlast,
cpu_s_axi_wvalid => cpu_axi_full_wvalid,
cpu_s_axi_wready => cpu_axi_full_wready,
cpu_s_axi_bid => cpu_axi_full_bid,
cpu_s_axi_bresp => cpu_axi_full_bresp,
cpu_s_axi_bvalid => cpu_axi_full_bvalid,
cpu_s_axi_bready => cpu_axi_full_bready,
cpu_s_axi_arid => cpu_axi_full_arid,
cpu_s_axi_araddr => cpu_axi_full_araddr,
cpu_s_axi_arlen => cpu_axi_full_arlen,
cpu_s_axi_arsize => cpu_axi_full_arsize,
cpu_s_axi_arburst => cpu_axi_full_arburst,
cpu_s_axi_arlock => cpu_axi_full_arlock,
cpu_s_axi_arcache => cpu_axi_full_arcache,
cpu_s_axi_arprot => cpu_axi_full_arprot,
cpu_s_axi_arqos => cpu_axi_full_arqos,
cpu_s_axi_arregion => cpu_axi_full_arregion,
cpu_s_axi_arvalid => cpu_axi_full_arvalid,
cpu_s_axi_arready => cpu_axi_full_arready,
cpu_s_axi_rid => cpu_axi_full_rid,
cpu_s_axi_rdata => cpu_axi_full_rdata,
cpu_s_axi_rresp => cpu_axi_full_rresp,
cpu_s_axi_rlast => cpu_axi_full_rlast,
cpu_s_axi_rvalid => cpu_axi_full_rvalid,
cpu_s_axi_rready => cpu_axi_full_rready,
cdma_s_axi_awid => cdma_axi_full_awid,
cdma_s_axi_awaddr => cdma_axi_full_awaddr,
cdma_s_axi_awlen => cdma_axi_full_awlen,
cdma_s_axi_awsize => cdma_axi_full_awsize,
cdma_s_axi_awburst => cdma_axi_full_awburst,
cdma_s_axi_awlock => cdma_axi_full_awlock,
cdma_s_axi_awcache => cdma_axi_full_awcache,
cdma_s_axi_awprot => cdma_axi_full_awprot,
cdma_s_axi_awqos => cdma_axi_full_awqos,
cdma_s_axi_awregion => cdma_axi_full_awregion,
cdma_s_axi_awvalid => cdma_axi_full_awvalid,
cdma_s_axi_awready => cdma_axi_full_awready,
cdma_s_axi_wdata => cdma_axi_full_wdata,
cdma_s_axi_wstrb => cdma_axi_full_wstrb,
cdma_s_axi_wlast => cdma_axi_full_wlast,
cdma_s_axi_wvalid => cdma_axi_full_wvalid,
cdma_s_axi_wready => cdma_axi_full_wready,
cdma_s_axi_bid => cdma_axi_full_bid,
cdma_s_axi_bresp => cdma_axi_full_bresp,
cdma_s_axi_bvalid => cdma_axi_full_bvalid,
cdma_s_axi_bready => cdma_axi_full_bready,
cdma_s_axi_arid => cdma_axi_full_arid,
cdma_s_axi_araddr => cdma_axi_full_araddr,
cdma_s_axi_arlen => cdma_axi_full_arlen,
cdma_s_axi_arsize => cdma_axi_full_arsize,
cdma_s_axi_arburst => cdma_axi_full_arburst,
cdma_s_axi_arlock => cdma_axi_full_arlock,
cdma_s_axi_arcache => cdma_axi_full_arcache,
cdma_s_axi_arprot => cdma_axi_full_arprot,
cdma_s_axi_arqos => cdma_axi_full_arqos,
cdma_s_axi_arregion => cdma_axi_full_arregion,
cdma_s_axi_arvalid => cdma_axi_full_arvalid,
cdma_s_axi_arready => cdma_axi_full_arready,
cdma_s_axi_rid => cdma_axi_full_rid,
cdma_s_axi_rdata => cdma_axi_full_rdata,
cdma_s_axi_rresp => cdma_axi_full_rresp,
cdma_s_axi_rlast => cdma_axi_full_rlast,
cdma_s_axi_rvalid => cdma_axi_full_rvalid,
cdma_s_axi_rready => cdma_axi_full_rready,
bram_m_axi_awid => bram_axi_full_awid,
bram_m_axi_awaddr => bram_axi_full_awaddr,
bram_m_axi_awlen => bram_axi_full_awlen,
bram_m_axi_awsize => bram_axi_full_awsize,
bram_m_axi_awburst => bram_axi_full_awburst,
bram_m_axi_awlock => bram_axi_full_awlock,
bram_m_axi_awcache => bram_axi_full_awcache,
bram_m_axi_awprot => bram_axi_full_awprot,
bram_m_axi_awqos => bram_axi_full_awqos,
bram_m_axi_awregion => bram_axi_full_awregion,
bram_m_axi_awvalid => bram_axi_full_awvalid,
bram_m_axi_awready => bram_axi_full_awready,
bram_m_axi_wdata => bram_axi_full_wdata,
bram_m_axi_wstrb => bram_axi_full_wstrb,
bram_m_axi_wlast => bram_axi_full_wlast,
bram_m_axi_wvalid => bram_axi_full_wvalid,
bram_m_axi_wready => bram_axi_full_wready,
bram_m_axi_bid => bram_axi_full_bid,
bram_m_axi_bresp => bram_axi_full_bresp,
bram_m_axi_bvalid => bram_axi_full_bvalid,
bram_m_axi_bready => bram_axi_full_bready,
bram_m_axi_arid => bram_axi_full_arid,
bram_m_axi_araddr => bram_axi_full_araddr,
bram_m_axi_arlen => bram_axi_full_arlen,
bram_m_axi_arsize => bram_axi_full_arsize,
bram_m_axi_arburst => bram_axi_full_arburst,
bram_m_axi_arlock => bram_axi_full_arlock,
bram_m_axi_arcache => bram_axi_full_arcache,
bram_m_axi_arprot => bram_axi_full_arprot,
bram_m_axi_arqos => bram_axi_full_arqos,
bram_m_axi_arregion => bram_axi_full_arregion,
bram_m_axi_arvalid => bram_axi_full_arvalid,
bram_m_axi_arready => bram_axi_full_arready,
bram_m_axi_rid => bram_axi_full_rid,
bram_m_axi_rdata => bram_axi_full_rdata,
bram_m_axi_rresp => bram_axi_full_rresp,
bram_m_axi_rlast => bram_axi_full_rlast,
bram_m_axi_rvalid => bram_axi_full_rvalid,
bram_m_axi_rready => bram_axi_full_rready,
ram_m_axi_awid => ram_axi_full_awid,
ram_m_axi_awaddr => ram_axi_full_awaddr,
ram_m_axi_awlen => ram_axi_full_awlen,
ram_m_axi_awsize => ram_axi_full_awsize,
ram_m_axi_awburst => ram_axi_full_awburst,
ram_m_axi_awlock => ram_axi_full_awlock,
ram_m_axi_awcache => ram_axi_full_awcache,
ram_m_axi_awprot => ram_axi_full_awprot,
ram_m_axi_awqos => ram_axi_full_awqos,
ram_m_axi_awregion => ram_axi_full_awregion,
ram_m_axi_awvalid => ram_axi_full_awvalid,
ram_m_axi_awready => ram_axi_full_awready,
ram_m_axi_wdata => ram_axi_full_wdata,
ram_m_axi_wstrb => ram_axi_full_wstrb,
ram_m_axi_wlast => ram_axi_full_wlast,
ram_m_axi_wvalid => ram_axi_full_wvalid,
ram_m_axi_wready => ram_axi_full_wready,
ram_m_axi_bid => ram_axi_full_bid,
ram_m_axi_bresp => ram_axi_full_bresp,
ram_m_axi_bvalid => ram_axi_full_bvalid,
ram_m_axi_bready => ram_axi_full_bready,
ram_m_axi_arid => ram_axi_full_arid,
ram_m_axi_araddr => ram_axi_full_araddr,
ram_m_axi_arlen => ram_axi_full_arlen,
ram_m_axi_arsize => ram_axi_full_arsize,
ram_m_axi_arburst => ram_axi_full_arburst,
ram_m_axi_arlock => ram_axi_full_arlock,
ram_m_axi_arcache => ram_axi_full_arcache,
ram_m_axi_arprot => ram_axi_full_arprot,
ram_m_axi_arqos => ram_axi_full_arqos,
ram_m_axi_arregion => ram_axi_full_arregion,
ram_m_axi_arvalid => ram_axi_full_arvalid,
ram_m_axi_arready => ram_axi_full_arready,
ram_m_axi_rid => ram_axi_full_rid,
ram_m_axi_rdata => ram_axi_full_rdata,
ram_m_axi_rresp => ram_axi_full_rresp,
ram_m_axi_rlast => ram_axi_full_rlast,
ram_m_axi_rvalid => ram_axi_full_rvalid,
ram_m_axi_rready => ram_axi_full_rready,
int_m_axi_awid => int_axi_full_awid,
int_m_axi_awaddr => int_axi_full_awaddr,
int_m_axi_awlen => int_axi_full_awlen,
int_m_axi_awsize => int_axi_full_awsize,
int_m_axi_awburst => int_axi_full_awburst,
int_m_axi_awlock => int_axi_full_awlock,
int_m_axi_awcache => int_axi_full_awcache,
int_m_axi_awprot => int_axi_full_awprot,
int_m_axi_awqos => int_axi_full_awqos,
int_m_axi_awregion => int_axi_full_awregion,
int_m_axi_awvalid => int_axi_full_awvalid,
int_m_axi_awready => int_axi_full_awready,
int_m_axi_wdata => int_axi_full_wdata,
int_m_axi_wstrb => int_axi_full_wstrb,
int_m_axi_wlast => int_axi_full_wlast,
int_m_axi_wvalid => int_axi_full_wvalid,
int_m_axi_wready => int_axi_full_wready,
int_m_axi_bid => int_axi_full_bid,
int_m_axi_bresp => int_axi_full_bresp,
int_m_axi_bvalid => int_axi_full_bvalid,
int_m_axi_bready => int_axi_full_bready,
int_m_axi_arid => int_axi_full_arid,
int_m_axi_araddr => int_axi_full_araddr,
int_m_axi_arlen => int_axi_full_arlen,
int_m_axi_arsize => int_axi_full_arsize,
int_m_axi_arburst => int_axi_full_arburst,
int_m_axi_arlock => int_axi_full_arlock,
int_m_axi_arcache => int_axi_full_arcache,
int_m_axi_arprot => int_axi_full_arprot,
int_m_axi_arqos => int_axi_full_arqos,
int_m_axi_arregion => int_axi_full_arregion,
int_m_axi_arvalid => int_axi_full_arvalid,
int_m_axi_arready => int_axi_full_arready,
int_m_axi_rid => int_axi_full_rid,
int_m_axi_rdata => int_axi_full_rdata,
int_m_axi_rresp => int_axi_full_rresp,
int_m_axi_rlast => int_axi_full_rlast,
int_m_axi_rvalid => int_axi_full_rvalid,
int_m_axi_rready => int_axi_full_rready,
timer_m_axi_awid => timer_axi_full_awid,
timer_m_axi_awaddr => timer_axi_full_awaddr,
timer_m_axi_awlen => timer_axi_full_awlen,
timer_m_axi_awsize => timer_axi_full_awsize,
timer_m_axi_awburst => timer_axi_full_awburst,
timer_m_axi_awlock => timer_axi_full_awlock,
timer_m_axi_awcache => timer_axi_full_awcache,
timer_m_axi_awprot => timer_axi_full_awprot,
timer_m_axi_awqos => timer_axi_full_awqos,
timer_m_axi_awregion => timer_axi_full_awregion,
timer_m_axi_awvalid => timer_axi_full_awvalid,
timer_m_axi_awready => timer_axi_full_awready,
timer_m_axi_wdata => timer_axi_full_wdata,
timer_m_axi_wstrb => timer_axi_full_wstrb,
timer_m_axi_wlast => timer_axi_full_wlast,
timer_m_axi_wvalid => timer_axi_full_wvalid,
timer_m_axi_wready => timer_axi_full_wready,
timer_m_axi_bid => timer_axi_full_bid,
timer_m_axi_bresp => timer_axi_full_bresp,
timer_m_axi_bvalid => timer_axi_full_bvalid,
timer_m_axi_bready => timer_axi_full_bready,
timer_m_axi_arid => timer_axi_full_arid,
timer_m_axi_araddr => timer_axi_full_araddr,
timer_m_axi_arlen => timer_axi_full_arlen,
timer_m_axi_arsize => timer_axi_full_arsize,
timer_m_axi_arburst => timer_axi_full_arburst,
timer_m_axi_arlock => timer_axi_full_arlock,
timer_m_axi_arcache => timer_axi_full_arcache,
timer_m_axi_arprot => timer_axi_full_arprot,
timer_m_axi_arqos => timer_axi_full_arqos,
timer_m_axi_arregion => timer_axi_full_arregion,
timer_m_axi_arvalid => timer_axi_full_arvalid,
timer_m_axi_arready => timer_axi_full_arready,
timer_m_axi_rid => timer_axi_full_rid,
timer_m_axi_rdata => timer_axi_full_rdata,
timer_m_axi_rresp => timer_axi_full_rresp,
timer_m_axi_rlast => timer_axi_full_rlast,
timer_m_axi_rvalid => timer_axi_full_rvalid,
timer_m_axi_rready => timer_axi_full_rready,
gpio_m_axi_awid => gpio_axi_full_awid,
gpio_m_axi_awaddr => gpio_axi_full_awaddr,
gpio_m_axi_awlen => gpio_axi_full_awlen,
gpio_m_axi_awsize => gpio_axi_full_awsize,
gpio_m_axi_awburst => gpio_axi_full_awburst,
gpio_m_axi_awlock => gpio_axi_full_awlock,
gpio_m_axi_awcache => gpio_axi_full_awcache,
gpio_m_axi_awprot => gpio_axi_full_awprot,
gpio_m_axi_awqos => gpio_axi_full_awqos,
gpio_m_axi_awregion => gpio_axi_full_awregion,
gpio_m_axi_awvalid => gpio_axi_full_awvalid,
gpio_m_axi_awready => gpio_axi_full_awready,
gpio_m_axi_wdata => gpio_axi_full_wdata,
gpio_m_axi_wstrb => gpio_axi_full_wstrb,
gpio_m_axi_wlast => gpio_axi_full_wlast,
gpio_m_axi_wvalid => gpio_axi_full_wvalid,
gpio_m_axi_wready => gpio_axi_full_wready,
gpio_m_axi_bid => gpio_axi_full_bid,
gpio_m_axi_bresp => gpio_axi_full_bresp,
gpio_m_axi_bvalid => gpio_axi_full_bvalid,
gpio_m_axi_bready => gpio_axi_full_bready,
gpio_m_axi_arid => gpio_axi_full_arid,
gpio_m_axi_araddr => gpio_axi_full_araddr,
gpio_m_axi_arlen => gpio_axi_full_arlen,
gpio_m_axi_arsize => gpio_axi_full_arsize,
gpio_m_axi_arburst => gpio_axi_full_arburst,
gpio_m_axi_arlock => gpio_axi_full_arlock,
gpio_m_axi_arcache => gpio_axi_full_arcache,
gpio_m_axi_arprot => gpio_axi_full_arprot,
gpio_m_axi_arqos => gpio_axi_full_arqos,
gpio_m_axi_arregion => gpio_axi_full_arregion,
gpio_m_axi_arvalid => gpio_axi_full_arvalid,
gpio_m_axi_arready => gpio_axi_full_arready,
gpio_m_axi_rid => gpio_axi_full_rid,
gpio_m_axi_rdata => gpio_axi_full_rdata,
gpio_m_axi_rresp => gpio_axi_full_rresp,
gpio_m_axi_rlast => gpio_axi_full_rlast,
gpio_m_axi_rvalid => gpio_axi_full_rvalid,
gpio_m_axi_rready => gpio_axi_full_rready,
cdma_m_axi_awid => cdmareg_axi_full_awid,
cdma_m_axi_awaddr => cdmareg_axi_full_awaddr,
cdma_m_axi_awlen => cdmareg_axi_full_awlen,
cdma_m_axi_awsize => cdmareg_axi_full_awsize,
cdma_m_axi_awburst => cdmareg_axi_full_awburst,
cdma_m_axi_awlock => cdmareg_axi_full_awlock,
cdma_m_axi_awcache => cdmareg_axi_full_awcache,
cdma_m_axi_awprot => cdmareg_axi_full_awprot,
cdma_m_axi_awqos => cdmareg_axi_full_awqos,
cdma_m_axi_awregion => cdmareg_axi_full_awregion,
cdma_m_axi_awvalid => cdmareg_axi_full_awvalid,
cdma_m_axi_awready => cdmareg_axi_full_awready,
cdma_m_axi_wdata => cdmareg_axi_full_wdata,
cdma_m_axi_wstrb => cdmareg_axi_full_wstrb,
cdma_m_axi_wlast => cdmareg_axi_full_wlast,
cdma_m_axi_wvalid => cdmareg_axi_full_wvalid,
cdma_m_axi_wready => cdmareg_axi_full_wready,
cdma_m_axi_bid => cdmareg_axi_full_bid,
cdma_m_axi_bresp => cdmareg_axi_full_bresp,
cdma_m_axi_bvalid => cdmareg_axi_full_bvalid,
cdma_m_axi_bready => cdmareg_axi_full_bready,
cdma_m_axi_arid => cdmareg_axi_full_arid,
cdma_m_axi_araddr => cdmareg_axi_full_araddr,
cdma_m_axi_arlen => cdmareg_axi_full_arlen,
cdma_m_axi_arsize => cdmareg_axi_full_arsize,
cdma_m_axi_arburst => cdmareg_axi_full_arburst,
cdma_m_axi_arlock => cdmareg_axi_full_arlock,
cdma_m_axi_arcache => cdmareg_axi_full_arcache,
cdma_m_axi_arprot => cdmareg_axi_full_arprot,
cdma_m_axi_arqos => cdmareg_axi_full_arqos,
cdma_m_axi_arregion => cdmareg_axi_full_arregion,
cdma_m_axi_arvalid => cdmareg_axi_full_arvalid,
cdma_m_axi_arready => cdmareg_axi_full_arready,
cdma_m_axi_rid => cdmareg_axi_full_rid,
cdma_m_axi_rdata => cdmareg_axi_full_rdata,
cdma_m_axi_rresp => cdmareg_axi_full_rresp,
cdma_m_axi_rlast => cdmareg_axi_full_rlast,
cdma_m_axi_rvalid => cdmareg_axi_full_rvalid,
cdma_m_axi_rready => cdmareg_axi_full_rready,
uart_m_axi_awid => uart_axi_full_awid,
uart_m_axi_awaddr => uart_axi_full_awaddr,
uart_m_axi_awlen => uart_axi_full_awlen,
uart_m_axi_awsize => uart_axi_full_awsize,
uart_m_axi_awburst => uart_axi_full_awburst,
uart_m_axi_awlock => uart_axi_full_awlock,
uart_m_axi_awcache => uart_axi_full_awcache,
uart_m_axi_awprot => uart_axi_full_awprot,
uart_m_axi_awqos => uart_axi_full_awqos,
uart_m_axi_awregion => uart_axi_full_awregion,
uart_m_axi_awvalid => uart_axi_full_awvalid,
uart_m_axi_awready => uart_axi_full_awready,
uart_m_axi_wdata => uart_axi_full_wdata,
uart_m_axi_wstrb => uart_axi_full_wstrb,
uart_m_axi_wlast => uart_axi_full_wlast,
uart_m_axi_wvalid => uart_axi_full_wvalid,
uart_m_axi_wready => uart_axi_full_wready,
uart_m_axi_bid => uart_axi_full_bid,
uart_m_axi_bresp => uart_axi_full_bresp,
uart_m_axi_bvalid => uart_axi_full_bvalid,
uart_m_axi_bready => uart_axi_full_bready,
uart_m_axi_arid => uart_axi_full_arid,
uart_m_axi_araddr => uart_axi_full_araddr,
uart_m_axi_arlen => uart_axi_full_arlen,
uart_m_axi_arsize => uart_axi_full_arsize,
uart_m_axi_arburst => uart_axi_full_arburst,
uart_m_axi_arlock => uart_axi_full_arlock,
uart_m_axi_arcache => uart_axi_full_arcache,
uart_m_axi_arprot => uart_axi_full_arprot,
uart_m_axi_arqos => uart_axi_full_arqos,
uart_m_axi_arregion => uart_axi_full_arregion,
uart_m_axi_arvalid => uart_axi_full_arvalid,
uart_m_axi_arready => uart_axi_full_arready,
uart_m_axi_rid => uart_axi_full_rid,
uart_m_axi_rdata => uart_axi_full_rdata,
uart_m_axi_rresp => uart_axi_full_rresp,
uart_m_axi_rlast => uart_axi_full_rlast,
uart_m_axi_rvalid => uart_axi_full_rvalid,
uart_m_axi_rready => uart_axi_full_rready,
timer_extra_0_m_axi_awid => timer_extra_0_axi_full_awid,
timer_extra_0_m_axi_awaddr => timer_extra_0_axi_full_awaddr,
timer_extra_0_m_axi_awlen => timer_extra_0_axi_full_awlen,
timer_extra_0_m_axi_awsize => timer_extra_0_axi_full_awsize,
timer_extra_0_m_axi_awburst => timer_extra_0_axi_full_awburst,
timer_extra_0_m_axi_awlock => timer_extra_0_axi_full_awlock,
timer_extra_0_m_axi_awcache => timer_extra_0_axi_full_awcache,
timer_extra_0_m_axi_awprot => timer_extra_0_axi_full_awprot,
timer_extra_0_m_axi_awqos => timer_extra_0_axi_full_awqos,
timer_extra_0_m_axi_awregion => timer_extra_0_axi_full_awregion,
timer_extra_0_m_axi_awvalid => timer_extra_0_axi_full_awvalid,
timer_extra_0_m_axi_awready => timer_extra_0_axi_full_awready,
timer_extra_0_m_axi_wdata => timer_extra_0_axi_full_wdata,
timer_extra_0_m_axi_wstrb => timer_extra_0_axi_full_wstrb,
timer_extra_0_m_axi_wlast => timer_extra_0_axi_full_wlast,
timer_extra_0_m_axi_wvalid => timer_extra_0_axi_full_wvalid,
timer_extra_0_m_axi_wready => timer_extra_0_axi_full_wready,
timer_extra_0_m_axi_bid => timer_extra_0_axi_full_bid,
timer_extra_0_m_axi_bresp => timer_extra_0_axi_full_bresp,
timer_extra_0_m_axi_bvalid => timer_extra_0_axi_full_bvalid,
timer_extra_0_m_axi_bready => timer_extra_0_axi_full_bready,
timer_extra_0_m_axi_arid => timer_extra_0_axi_full_arid,
timer_extra_0_m_axi_araddr => timer_extra_0_axi_full_araddr,
timer_extra_0_m_axi_arlen => timer_extra_0_axi_full_arlen,
timer_extra_0_m_axi_arsize => timer_extra_0_axi_full_arsize,
timer_extra_0_m_axi_arburst => timer_extra_0_axi_full_arburst,
timer_extra_0_m_axi_arlock => timer_extra_0_axi_full_arlock,
timer_extra_0_m_axi_arcache => timer_extra_0_axi_full_arcache,
timer_extra_0_m_axi_arprot => timer_extra_0_axi_full_arprot,
timer_extra_0_m_axi_arqos => timer_extra_0_axi_full_arqos,
timer_extra_0_m_axi_arregion => timer_extra_0_axi_full_arregion,
timer_extra_0_m_axi_arvalid => timer_extra_0_axi_full_arvalid,
timer_extra_0_m_axi_arready => timer_extra_0_axi_full_arready,
timer_extra_0_m_axi_rid => timer_extra_0_axi_full_rid,
timer_extra_0_m_axi_rdata => timer_extra_0_axi_full_rdata,
timer_extra_0_m_axi_rresp => timer_extra_0_axi_full_rresp,
timer_extra_0_m_axi_rlast => timer_extra_0_axi_full_rlast,
timer_extra_0_m_axi_rvalid => timer_extra_0_axi_full_rvalid,
timer_extra_0_m_axi_rready => timer_extra_0_axi_full_rready,
aclk => aclk,
aresetn => cross_aresetn(0));
plasoc_cpu_inst : plasoc_cpu
port map (
aclk => aclk,
aresetn => aresetn(0),
intr_in => cpu_int,
axi_awid => cpu_axi_full_awid,
axi_awaddr => cpu_axi_full_awaddr,
axi_awlen => cpu_axi_full_awlen,
axi_awsize => cpu_axi_full_awsize,
axi_awburst => cpu_axi_full_awburst,
axi_awlock => cpu_axi_full_awlock,
axi_awcache => cpu_axi_full_awcache,
axi_awprot => cpu_axi_full_awprot,
axi_awqos => cpu_axi_full_awqos,
axi_awregion => cpu_axi_full_awregion,
axi_awvalid => cpu_axi_full_awvalid,
axi_awready => cpu_axi_full_awready,
axi_wdata => cpu_axi_full_wdata,
axi_wstrb => cpu_axi_full_wstrb,
axi_wlast => cpu_axi_full_wlast,
axi_wvalid => cpu_axi_full_wvalid,
axi_wready => cpu_axi_full_wready,
axi_bid => cpu_axi_full_bid,
axi_bresp => cpu_axi_full_bresp,
axi_bvalid => cpu_axi_full_bvalid,
axi_bready => cpu_axi_full_bready,
axi_arid => cpu_axi_full_arid,
axi_araddr => cpu_axi_full_araddr,
axi_arlen => cpu_axi_full_arlen,
axi_arsize => cpu_axi_full_arsize,
axi_arburst => cpu_axi_full_arburst,
axi_arlock => cpu_axi_full_arlock,
axi_arcache => cpu_axi_full_arcache,
axi_arprot => cpu_axi_full_arprot,
axi_arqos => cpu_axi_full_arqos,
axi_arregion => cpu_axi_full_arregion,
axi_arvalid => cpu_axi_full_arvalid,
axi_arready => cpu_axi_full_arready,
axi_rid => cpu_axi_full_rid,
axi_rdata => cpu_axi_full_rdata,
axi_rresp => cpu_axi_full_rresp,
axi_rlast => cpu_axi_full_rlast,
axi_rvalid => cpu_axi_full_rvalid,
axi_rready => cpu_axi_full_rready);
int_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => int_axi_full_awid,
s_axi_awaddr => int_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => int_axi_full_awlen,
s_axi_awsize => int_axi_full_awsize,
s_axi_awburst => int_axi_full_awburst,
s_axi_awlock => int_axi_full_awlock,
s_axi_awcache => int_axi_full_awcache,
s_axi_awprot => int_axi_full_awprot,
s_axi_awqos => int_axi_full_awqos,
s_axi_awregion => int_axi_full_awregion,
s_axi_awvalid => int_axi_full_awvalid,
s_axi_awready => int_axi_full_awready,
s_axi_wdata => int_axi_full_wdata,
s_axi_wstrb => int_axi_full_wstrb,
s_axi_wlast => int_axi_full_wlast,
s_axi_wvalid => int_axi_full_wvalid,
s_axi_wready => int_axi_full_wready,
s_axi_bid => int_axi_full_bid,
s_axi_bresp => int_axi_full_bresp,
s_axi_bvalid => int_axi_full_bvalid,
s_axi_bready => int_axi_full_bready,
s_axi_arid => int_axi_full_arid,
s_axi_araddr => int_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => int_axi_full_arlen,
s_axi_arsize => int_axi_full_arsize,
s_axi_arburst => int_axi_full_arburst,
s_axi_arlock => int_axi_full_arlock,
s_axi_arcache => int_axi_full_arcache,
s_axi_arprot => int_axi_full_arprot,
s_axi_arqos => int_axi_full_arqos,
s_axi_arregion => int_axi_full_arregion,
s_axi_arvalid => int_axi_full_arvalid,
s_axi_arready => int_axi_full_arready,
s_axi_rid => int_axi_full_rid,
s_axi_rdata => int_axi_full_rdata,
s_axi_rresp => int_axi_full_rresp,
s_axi_rlast => int_axi_full_rlast,
s_axi_rvalid => int_axi_full_rvalid,
s_axi_rready => int_axi_full_rready,
m_axi_awaddr => int_axi_lite_awaddr,
m_axi_awprot => int_axi_lite_awprot,
m_axi_awvalid => int_axi_lite_awvalid,
m_axi_awready => int_axi_lite_awready,
m_axi_wvalid => int_axi_lite_wvalid,
m_axi_wready => int_axi_lite_wready,
m_axi_wdata => int_axi_lite_wdata,
m_axi_wstrb => int_axi_lite_wstrb,
m_axi_bvalid => int_axi_lite_bvalid,
m_axi_bready => int_axi_lite_bready,
m_axi_bresp => int_axi_lite_bresp,
m_axi_araddr => int_axi_lite_araddr,
m_axi_arprot => int_axi_lite_arprot,
m_axi_arvalid => int_axi_lite_arvalid,
m_axi_arready => int_axi_lite_arready,
m_axi_rdata => int_axi_lite_rdata,
m_axi_rvalid => int_axi_lite_rvalid,
m_axi_rready => int_axi_lite_rready,
m_axi_rresp => int_axi_lite_rresp);
timer_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => timer_axi_full_awid,
s_axi_awaddr => timer_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => timer_axi_full_awlen,
s_axi_awsize => timer_axi_full_awsize,
s_axi_awburst => timer_axi_full_awburst,
s_axi_awlock => timer_axi_full_awlock,
s_axi_awcache => timer_axi_full_awcache,
s_axi_awprot => timer_axi_full_awprot,
s_axi_awqos => timer_axi_full_awqos,
s_axi_awregion => timer_axi_full_awregion,
s_axi_awvalid => timer_axi_full_awvalid,
s_axi_awready => timer_axi_full_awready,
s_axi_wdata => timer_axi_full_wdata,
s_axi_wstrb => timer_axi_full_wstrb,
s_axi_wlast => timer_axi_full_wlast,
s_axi_wvalid => timer_axi_full_wvalid,
s_axi_wready => timer_axi_full_wready,
s_axi_bid => timer_axi_full_bid,
s_axi_bresp => timer_axi_full_bresp,
s_axi_bvalid => timer_axi_full_bvalid,
s_axi_bready => timer_axi_full_bready,
s_axi_arid => timer_axi_full_arid,
s_axi_araddr => timer_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => timer_axi_full_arlen,
s_axi_arsize => timer_axi_full_arsize,
s_axi_arburst => timer_axi_full_arburst,
s_axi_arlock => timer_axi_full_arlock,
s_axi_arcache => timer_axi_full_arcache,
s_axi_arprot => timer_axi_full_arprot,
s_axi_arqos => timer_axi_full_arqos,
s_axi_arregion => timer_axi_full_arregion,
s_axi_arvalid => timer_axi_full_arvalid,
s_axi_arready => timer_axi_full_arready,
s_axi_rid => timer_axi_full_rid,
s_axi_rdata => timer_axi_full_rdata,
s_axi_rresp => timer_axi_full_rresp,
s_axi_rlast => timer_axi_full_rlast,
s_axi_rvalid => timer_axi_full_rvalid,
s_axi_rready => timer_axi_full_rready,
m_axi_awaddr => timer_axi_lite_awaddr,
m_axi_awprot => timer_axi_lite_awprot,
m_axi_awvalid => timer_axi_lite_awvalid,
m_axi_awready => timer_axi_lite_awready,
m_axi_wvalid => timer_axi_lite_wvalid,
m_axi_wready => timer_axi_lite_wready,
m_axi_wdata => timer_axi_lite_wdata,
m_axi_wstrb => timer_axi_lite_wstrb,
m_axi_bvalid => timer_axi_lite_bvalid,
m_axi_bready => timer_axi_lite_bready,
m_axi_bresp => timer_axi_lite_bresp,
m_axi_araddr => timer_axi_lite_araddr,
m_axi_arprot => timer_axi_lite_arprot,
m_axi_arvalid => timer_axi_lite_arvalid,
m_axi_arready => timer_axi_lite_arready,
m_axi_rdata => timer_axi_lite_rdata,
m_axi_rvalid => timer_axi_lite_rvalid,
m_axi_rready => timer_axi_lite_rready,
m_axi_rresp => timer_axi_lite_rresp);
gpio_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => gpio_axi_full_awid,
s_axi_awaddr => gpio_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => gpio_axi_full_awlen,
s_axi_awsize => gpio_axi_full_awsize,
s_axi_awburst => gpio_axi_full_awburst,
s_axi_awlock => gpio_axi_full_awlock,
s_axi_awcache => gpio_axi_full_awcache,
s_axi_awprot => gpio_axi_full_awprot,
s_axi_awqos => gpio_axi_full_awqos,
s_axi_awregion => gpio_axi_full_awregion,
s_axi_awvalid => gpio_axi_full_awvalid,
s_axi_awready => gpio_axi_full_awready,
s_axi_wdata => gpio_axi_full_wdata,
s_axi_wstrb => gpio_axi_full_wstrb,
s_axi_wlast => gpio_axi_full_wlast,
s_axi_wvalid => gpio_axi_full_wvalid,
s_axi_wready => gpio_axi_full_wready,
s_axi_bid => gpio_axi_full_bid,
s_axi_bresp => gpio_axi_full_bresp,
s_axi_bvalid => gpio_axi_full_bvalid,
s_axi_bready => gpio_axi_full_bready,
s_axi_arid => gpio_axi_full_arid,
s_axi_araddr => gpio_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => gpio_axi_full_arlen,
s_axi_arsize => gpio_axi_full_arsize,
s_axi_arburst => gpio_axi_full_arburst,
s_axi_arlock => gpio_axi_full_arlock,
s_axi_arcache => gpio_axi_full_arcache,
s_axi_arprot => gpio_axi_full_arprot,
s_axi_arqos => gpio_axi_full_arqos,
s_axi_arregion => gpio_axi_full_arregion,
s_axi_arvalid => gpio_axi_full_arvalid,
s_axi_arready => gpio_axi_full_arready,
s_axi_rid => gpio_axi_full_rid,
s_axi_rdata => gpio_axi_full_rdata,
s_axi_rresp => gpio_axi_full_rresp,
s_axi_rlast => gpio_axi_full_rlast,
s_axi_rvalid => gpio_axi_full_rvalid,
s_axi_rready => gpio_axi_full_rready,
m_axi_awaddr => gpio_axi_lite_awaddr,
m_axi_awprot => gpio_axi_lite_awprot,
m_axi_awvalid => gpio_axi_lite_awvalid,
m_axi_awready => gpio_axi_lite_awready,
m_axi_wvalid => gpio_axi_lite_wvalid,
m_axi_wready => gpio_axi_lite_wready,
m_axi_wdata => gpio_axi_lite_wdata,
m_axi_wstrb => gpio_axi_lite_wstrb,
m_axi_bvalid => gpio_axi_lite_bvalid,
m_axi_bready => gpio_axi_lite_bready,
m_axi_bresp => gpio_axi_lite_bresp,
m_axi_araddr => gpio_axi_lite_araddr,
m_axi_arprot => gpio_axi_lite_arprot,
m_axi_arvalid => gpio_axi_lite_arvalid,
m_axi_arready => gpio_axi_lite_arready,
m_axi_rdata => gpio_axi_lite_rdata,
m_axi_rvalid => gpio_axi_lite_rvalid,
m_axi_rready => gpio_axi_lite_rready,
m_axi_rresp => gpio_axi_lite_rresp);
cdmareg_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => cdmareg_axi_full_awid,
s_axi_awaddr => cdmareg_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => cdmareg_axi_full_awlen,
s_axi_awsize => cdmareg_axi_full_awsize,
s_axi_awburst => cdmareg_axi_full_awburst,
s_axi_awlock => cdmareg_axi_full_awlock,
s_axi_awcache => cdmareg_axi_full_awcache,
s_axi_awprot => cdmareg_axi_full_awprot,
s_axi_awqos => cdmareg_axi_full_awqos,
s_axi_awregion => cdmareg_axi_full_awregion,
s_axi_awvalid => cdmareg_axi_full_awvalid,
s_axi_awready => cdmareg_axi_full_awready,
s_axi_wdata => cdmareg_axi_full_wdata,
s_axi_wstrb => cdmareg_axi_full_wstrb,
s_axi_wlast => cdmareg_axi_full_wlast,
s_axi_wvalid => cdmareg_axi_full_wvalid,
s_axi_wready => cdmareg_axi_full_wready,
s_axi_bid => cdmareg_axi_full_bid,
s_axi_bresp => cdmareg_axi_full_bresp,
s_axi_bvalid => cdmareg_axi_full_bvalid,
s_axi_bready => cdmareg_axi_full_bready,
s_axi_arid => cdmareg_axi_full_arid,
s_axi_araddr => cdmareg_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => cdmareg_axi_full_arlen,
s_axi_arsize => cdmareg_axi_full_arsize,
s_axi_arburst => cdmareg_axi_full_arburst,
s_axi_arlock => cdmareg_axi_full_arlock,
s_axi_arcache => cdmareg_axi_full_arcache,
s_axi_arprot => cdmareg_axi_full_arprot,
s_axi_arqos => cdmareg_axi_full_arqos,
s_axi_arregion => cdmareg_axi_full_arregion,
s_axi_arvalid => cdmareg_axi_full_arvalid,
s_axi_arready => cdmareg_axi_full_arready,
s_axi_rid => cdmareg_axi_full_rid,
s_axi_rdata => cdmareg_axi_full_rdata,
s_axi_rresp => cdmareg_axi_full_rresp,
s_axi_rlast => cdmareg_axi_full_rlast,
s_axi_rvalid => cdmareg_axi_full_rvalid,
s_axi_rready => cdmareg_axi_full_rready,
m_axi_awaddr => cdmareg_axi_lite_awaddr,
m_axi_awprot => cdmareg_axi_lite_awprot,
m_axi_awvalid => cdmareg_axi_lite_awvalid,
m_axi_awready => cdmareg_axi_lite_awready,
m_axi_wvalid => cdmareg_axi_lite_wvalid,
m_axi_wready => cdmareg_axi_lite_wready,
m_axi_wdata => cdmareg_axi_lite_wdata,
m_axi_wstrb => cdmareg_axi_lite_wstrb,
m_axi_bvalid => cdmareg_axi_lite_bvalid,
m_axi_bready => cdmareg_axi_lite_bready,
m_axi_bresp => cdmareg_axi_lite_bresp,
m_axi_araddr => cdmareg_axi_lite_araddr,
m_axi_arprot => cdmareg_axi_lite_arprot,
m_axi_arvalid => cdmareg_axi_lite_arvalid,
m_axi_arready => cdmareg_axi_lite_arready,
m_axi_rdata => cdmareg_axi_lite_rdata,
m_axi_rvalid => cdmareg_axi_lite_rvalid,
m_axi_rready => cdmareg_axi_lite_rready,
m_axi_rresp => cdmareg_axi_lite_rresp);
uart_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => uart_axi_full_awid,
s_axi_awaddr => uart_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => uart_axi_full_awlen,
s_axi_awsize => uart_axi_full_awsize,
s_axi_awburst => uart_axi_full_awburst,
s_axi_awlock => uart_axi_full_awlock,
s_axi_awcache => uart_axi_full_awcache,
s_axi_awprot => uart_axi_full_awprot,
s_axi_awqos => uart_axi_full_awqos,
s_axi_awregion => uart_axi_full_awregion,
s_axi_awvalid => uart_axi_full_awvalid,
s_axi_awready => uart_axi_full_awready,
s_axi_wdata => uart_axi_full_wdata,
s_axi_wstrb => uart_axi_full_wstrb,
s_axi_wlast => uart_axi_full_wlast,
s_axi_wvalid => uart_axi_full_wvalid,
s_axi_wready => uart_axi_full_wready,
s_axi_bid => uart_axi_full_bid,
s_axi_bresp => uart_axi_full_bresp,
s_axi_bvalid => uart_axi_full_bvalid,
s_axi_bready => uart_axi_full_bready,
s_axi_arid => uart_axi_full_arid,
s_axi_araddr => uart_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => uart_axi_full_arlen,
s_axi_arsize => uart_axi_full_arsize,
s_axi_arburst => uart_axi_full_arburst,
s_axi_arlock => uart_axi_full_arlock,
s_axi_arcache => uart_axi_full_arcache,
s_axi_arprot => uart_axi_full_arprot,
s_axi_arqos => uart_axi_full_arqos,
s_axi_arregion => uart_axi_full_arregion,
s_axi_arvalid => uart_axi_full_arvalid,
s_axi_arready => uart_axi_full_arready,
s_axi_rid => uart_axi_full_rid,
s_axi_rdata => uart_axi_full_rdata,
s_axi_rresp => uart_axi_full_rresp,
s_axi_rlast => uart_axi_full_rlast,
s_axi_rvalid => uart_axi_full_rvalid,
s_axi_rready => uart_axi_full_rready,
m_axi_awaddr => uart_axi_lite_awaddr,
m_axi_awprot => uart_axi_lite_awprot,
m_axi_awvalid => uart_axi_lite_awvalid,
m_axi_awready => uart_axi_lite_awready,
m_axi_wvalid => uart_axi_lite_wvalid,
m_axi_wready => uart_axi_lite_wready,
m_axi_wdata => uart_axi_lite_wdata,
m_axi_wstrb => uart_axi_lite_wstrb,
m_axi_bvalid => uart_axi_lite_bvalid,
m_axi_bready => uart_axi_lite_bready,
m_axi_bresp => uart_axi_lite_bresp,
m_axi_araddr => uart_axi_lite_araddr,
m_axi_arprot => uart_axi_lite_arprot,
m_axi_arvalid => uart_axi_lite_arvalid,
m_axi_arready => uart_axi_lite_arready,
m_axi_rdata => uart_axi_lite_rdata,
m_axi_rvalid => uart_axi_lite_rvalid,
m_axi_rready => uart_axi_lite_rready,
m_axi_rresp => uart_axi_lite_rresp);
timer_extra_0_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => timer_extra_0_axi_full_awid,
s_axi_awaddr => timer_extra_0_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => timer_extra_0_axi_full_awlen,
s_axi_awsize => timer_extra_0_axi_full_awsize,
s_axi_awburst => timer_extra_0_axi_full_awburst,
s_axi_awlock => timer_extra_0_axi_full_awlock,
s_axi_awcache => timer_extra_0_axi_full_awcache,
s_axi_awprot => timer_extra_0_axi_full_awprot,
s_axi_awqos => timer_extra_0_axi_full_awqos,
s_axi_awregion => timer_extra_0_axi_full_awregion,
s_axi_awvalid => timer_extra_0_axi_full_awvalid,
s_axi_awready => timer_extra_0_axi_full_awready,
s_axi_wdata => timer_extra_0_axi_full_wdata,
s_axi_wstrb => timer_extra_0_axi_full_wstrb,
s_axi_wlast => timer_extra_0_axi_full_wlast,
s_axi_wvalid => timer_extra_0_axi_full_wvalid,
s_axi_wready => timer_extra_0_axi_full_wready,
s_axi_bid => timer_extra_0_axi_full_bid,
s_axi_bresp => timer_extra_0_axi_full_bresp,
s_axi_bvalid => timer_extra_0_axi_full_bvalid,
s_axi_bready => timer_extra_0_axi_full_bready,
s_axi_arid => timer_extra_0_axi_full_arid,
s_axi_araddr => timer_extra_0_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => timer_extra_0_axi_full_arlen,
s_axi_arsize => timer_extra_0_axi_full_arsize,
s_axi_arburst => timer_extra_0_axi_full_arburst,
s_axi_arlock => timer_extra_0_axi_full_arlock,
s_axi_arcache => timer_extra_0_axi_full_arcache,
s_axi_arprot => timer_extra_0_axi_full_arprot,
s_axi_arqos => timer_extra_0_axi_full_arqos,
s_axi_arregion => timer_extra_0_axi_full_arregion,
s_axi_arvalid => timer_extra_0_axi_full_arvalid,
s_axi_arready => timer_extra_0_axi_full_arready,
s_axi_rid => timer_extra_0_axi_full_rid,
s_axi_rdata => timer_extra_0_axi_full_rdata,
s_axi_rresp => timer_extra_0_axi_full_rresp,
s_axi_rlast => timer_extra_0_axi_full_rlast,
s_axi_rvalid => timer_extra_0_axi_full_rvalid,
s_axi_rready => timer_extra_0_axi_full_rready,
m_axi_awaddr => timer_extra_0_axi_lite_awaddr,
m_axi_awprot => timer_extra_0_axi_lite_awprot,
m_axi_awvalid => timer_extra_0_axi_lite_awvalid,
m_axi_awready => timer_extra_0_axi_lite_awready,
m_axi_wvalid => timer_extra_0_axi_lite_wvalid,
m_axi_wready => timer_extra_0_axi_lite_wready,
m_axi_wdata => timer_extra_0_axi_lite_wdata,
m_axi_wstrb => timer_extra_0_axi_lite_wstrb,
m_axi_bvalid => timer_extra_0_axi_lite_bvalid,
m_axi_bready => timer_extra_0_axi_lite_bready,
m_axi_bresp => timer_extra_0_axi_lite_bresp,
m_axi_araddr => timer_extra_0_axi_lite_araddr,
m_axi_arprot => timer_extra_0_axi_lite_arprot,
m_axi_arvalid => timer_extra_0_axi_lite_arvalid,
m_axi_arready => timer_extra_0_axi_lite_arready,
m_axi_rdata => timer_extra_0_axi_lite_rdata,
m_axi_rvalid => timer_extra_0_axi_lite_rvalid,
m_axi_rready => timer_extra_0_axi_lite_rready,
m_axi_rresp => timer_extra_0_axi_lite_rresp);
bram_cntrl_inst : axi_bram_ctrl_0
port map (
s_axi_aclk => aclk,
s_axi_aresetn => aresetn(0),
s_axi_awid => bram_axi_full_awid,
s_axi_awaddr => bram_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => bram_axi_full_awlen,
s_axi_awsize => bram_axi_full_awsize,
s_axi_awburst => bram_axi_full_awburst,
s_axi_awlock => bram_axi_full_awlock,
s_axi_awcache => bram_axi_full_awcache,
s_axi_awprot => bram_axi_full_awprot,
s_axi_awvalid => bram_axi_full_awvalid,
s_axi_awready => bram_axi_full_awready,
s_axi_wdata => bram_axi_full_wdata,
s_axi_wstrb => bram_axi_full_wstrb,
s_axi_wlast => bram_axi_full_wlast,
s_axi_wvalid => bram_axi_full_wvalid,
s_axi_wready => bram_axi_full_wready,
s_axi_bid => bram_axi_full_bid,
s_axi_bresp => bram_axi_full_bresp,
s_axi_bvalid => bram_axi_full_bvalid,
s_axi_bready => bram_axi_full_bready,
s_axi_arid => bram_axi_full_arid,
s_axi_araddr => bram_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => bram_axi_full_arlen,
s_axi_arsize => bram_axi_full_arsize,
s_axi_arburst => bram_axi_full_arburst,
s_axi_arlock => bram_axi_full_arlock,
s_axi_arcache => bram_axi_full_arcache,
s_axi_arprot => bram_axi_full_arprot,
s_axi_arvalid => bram_axi_full_arvalid,
s_axi_arready => bram_axi_full_arready,
s_axi_rid => bram_axi_full_rid,
s_axi_rdata => bram_axi_full_rdata,
s_axi_rresp => bram_axi_full_rresp,
s_axi_rlast => bram_axi_full_rlast,
s_axi_rvalid => bram_axi_full_rvalid,
s_axi_rready => bram_axi_full_rready,
bram_rst_a => bram_bram_rst_a,
bram_clk_a => bram_bram_clk_a,
bram_en_a => bram_bram_en_a,
bram_we_a => bram_bram_we_a,
bram_addr_a => bram_bram_addr_a,
bram_wrdata_a => bram_bram_wrdata_a,
bram_rddata_a => bram_bram_rddata_a);
bram_inst : bram
generic map (
select_app => lower_app,
address_width => axi_lite_address_width,
data_width => axi_data_width,
bram_depth => 1024 )
port map (
bram_rst_a => bram_bram_rst_a,
bram_clk_a => bram_bram_clk_a,
bram_en_a => bram_bram_en_a,
bram_we_a => bram_bram_we_a,
bram_addr_a => bram_bram_addr_a,
bram_wrdata_a => bram_bram_wrdata_a,
bram_rddata_a => bram_bram_rddata_a);
gen_int_mm :
if upper_ext=false generate
ram_cntrl_inst : axi_bram_ctrl_1
port map (
s_axi_aclk => aclk,
s_axi_aresetn => aresetn(0),
s_axi_awid => ram_axi_full_awid,
s_axi_awaddr => ram_axi_full_awaddr(axi_ram_address_width-1 downto 0),
s_axi_awlen => ram_axi_full_awlen,
s_axi_awsize => ram_axi_full_awsize,
s_axi_awburst => ram_axi_full_awburst,
s_axi_awlock => ram_axi_full_awlock,
s_axi_awcache => ram_axi_full_awcache,
s_axi_awprot => ram_axi_full_awprot,
s_axi_awvalid => ram_axi_full_awvalid,
s_axi_awready => ram_axi_full_awready,
s_axi_wdata => ram_axi_full_wdata,
s_axi_wstrb => ram_axi_full_wstrb,
s_axi_wlast => ram_axi_full_wlast,
s_axi_wvalid => ram_axi_full_wvalid,
s_axi_wready => ram_axi_full_wready,
s_axi_bid => ram_axi_full_bid,
s_axi_bresp => ram_axi_full_bresp,
s_axi_bvalid => ram_axi_full_bvalid,
s_axi_bready => ram_axi_full_bready,
s_axi_arid => ram_axi_full_arid,
s_axi_araddr => ram_axi_full_araddr(axi_ram_address_width-1 downto 0),
s_axi_arlen => ram_axi_full_arlen,
s_axi_arsize => ram_axi_full_arsize,
s_axi_arburst => ram_axi_full_arburst,
s_axi_arlock => ram_axi_full_arlock,
s_axi_arcache => ram_axi_full_arcache,
s_axi_arprot => ram_axi_full_arprot,
s_axi_arvalid => ram_axi_full_arvalid,
s_axi_arready => ram_axi_full_arready,
s_axi_rid => ram_axi_full_rid,
s_axi_rdata => ram_axi_full_rdata,
s_axi_rresp => ram_axi_full_rresp,
s_axi_rlast => ram_axi_full_rlast,
s_axi_rvalid => ram_axi_full_rvalid,
s_axi_rready => ram_axi_full_rready,
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
ram_inst : bram
generic map (
select_app => upper_app,
address_width => axi_ram_address_width,
data_width => axi_data_width,
bram_depth => axi_ram_depth)
port map (
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
end generate;
gen_ext_mm :
if upper_ext=true generate
mig_wrap_wrapper_inst :
mig_wrap_wrapper
port map (
ACLK => aclk,
ARESETN => cross_aresetn(0),
DDR2_addr => DDR2_addr,
DDR2_ba => DDR2_ba,
DDR2_cas_n => DDR2_cas_n,
DDR2_ck_n => DDR2_ck_n,
DDR2_ck_p => DDR2_ck_p,
DDR2_cke => DDR2_cke,
DDR2_cs_n => DDR2_cs_n,
DDR2_dm => DDR2_dm,
DDR2_dq => DDR2_dq,
DDR2_dqs_n => DDR2_dqs_n,
DDR2_dqs_p => DDR2_dqs_p,
DDR2_odt => DDR2_odt,
DDR2_ras_n => DDR2_ras_n,
DDR2_we_n => DDR2_we_n,
S00_ARESETN => aresetn(0),
S00_AXI_araddr => ram_axi_full_araddr,
S00_AXI_arburst => ram_axi_full_arburst,
S00_AXI_arcache => ram_axi_full_arcache,
S00_AXI_arid => ram_axi_full_arid_slv,
S00_AXI_arlen => ram_axi_full_arlen,
S00_AXI_arlock => ram_axi_full_arlock_slv,
S00_AXI_arprot => ram_axi_full_arprot,
S00_AXI_arqos => ram_axi_full_arqos,
S00_AXI_arready => ram_axi_full_arready,
S00_AXI_arregion => ram_axi_full_arregion,
S00_AXI_arsize => ram_axi_full_arsize,
S00_AXI_arvalid => ram_axi_full_arvalid,
S00_AXI_awaddr => ram_axi_full_awaddr,
S00_AXI_awburst => ram_axi_full_awburst,
S00_AXI_awcache => ram_axi_full_awcache,
S00_AXI_awid => ram_axi_full_awid_slv,
S00_AXI_awlen => ram_axi_full_awlen,
S00_AXI_awlock => ram_axi_full_awlock_slv,
S00_AXI_awprot => ram_axi_full_awprot,
S00_AXI_awqos => ram_axi_full_awqos,
S00_AXI_awready => ram_axi_full_awready,
S00_AXI_awregion => ram_axi_full_awregion,
S00_AXI_awsize => ram_axi_full_awsize,
S00_AXI_awvalid => ram_axi_full_awvalid,
S00_AXI_bid => ram_axi_full_bid_slv,
S00_AXI_bready => ram_axi_full_bready,
S00_AXI_bresp => ram_axi_full_bresp,
S00_AXI_bvalid => ram_axi_full_bvalid,
S00_AXI_rdata => ram_axi_full_rdata,
S00_AXI_rid => ram_axi_full_rid_slv,
S00_AXI_rlast => ram_axi_full_rlast,
S00_AXI_rready => ram_axi_full_rready,
S00_AXI_rresp => ram_axi_full_rresp,
S00_AXI_rvalid => ram_axi_full_rvalid,
S00_AXI_wdata => ram_axi_full_wdata,
S00_AXI_wlast => ram_axi_full_wlast,
S00_AXI_wready => ram_axi_full_wready,
S00_AXI_wstrb => ram_axi_full_wstrb,
S00_AXI_wvalid => ram_axi_full_wvalid,
clk_ref_i => ddr_aclk,
sys_rst => raw_nreset);
end generate;
plasoc_int_inst : plasoc_int
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
cpu_int => cpu_int,
dev_ints => int_dev_ints,
axi_awaddr => int_axi_lite_awaddr,
axi_awprot => int_axi_lite_awprot,
axi_awvalid => int_axi_lite_awvalid,
axi_awready => int_axi_lite_awready,
axi_wvalid => int_axi_lite_wvalid,
axi_wready => int_axi_lite_wready,
axi_wdata => int_axi_lite_wdata,
axi_wstrb => int_axi_lite_wstrb,
axi_bvalid => int_axi_lite_bvalid,
axi_bready => int_axi_lite_bready,
axi_bresp => int_axi_lite_bresp,
axi_araddr => int_axi_lite_araddr,
axi_arprot => int_axi_lite_arprot,
axi_arvalid => int_axi_lite_arvalid,
axi_arready => int_axi_lite_arready,
axi_rdata => int_axi_lite_rdata,
axi_rvalid => int_axi_lite_rvalid,
axi_rready => int_axi_lite_rready,
axi_rresp => int_axi_lite_rresp);
plasoc_timer_inst : plasoc_timer
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
axi_awaddr => timer_axi_lite_awaddr,
axi_awprot => timer_axi_lite_awprot,
axi_awvalid => timer_axi_lite_awvalid,
axi_awready => timer_axi_lite_awready,
axi_wvalid => timer_axi_lite_wvalid,
axi_wready => timer_axi_lite_wready,
axi_wdata => timer_axi_lite_wdata,
axi_wstrb => timer_axi_lite_wstrb,
axi_bvalid => timer_axi_lite_bvalid,
axi_bready => timer_axi_lite_bready,
axi_bresp => timer_axi_lite_bresp,
axi_araddr => timer_axi_lite_araddr,
axi_arprot => timer_axi_lite_arprot,
axi_arvalid => timer_axi_lite_arvalid,
axi_arready => timer_axi_lite_arready,
axi_rdata => timer_axi_lite_rdata,
axi_rvalid => timer_axi_lite_rvalid,
axi_rready => timer_axi_lite_rready,
axi_rresp => timer_axi_lite_rresp,
done => timer_int);
plasoc_gpio_inst : plasoc_gpio
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
data_in => gpio_input,
data_out => gpio_output,
int => gpio_int,
axi_awaddr => gpio_axi_lite_awaddr,
axi_awprot => gpio_axi_lite_awprot,
axi_awvalid => gpio_axi_lite_awvalid,
axi_awready => gpio_axi_lite_awready,
axi_wvalid => gpio_axi_lite_wvalid,
axi_wready => gpio_axi_lite_wready,
axi_wdata => gpio_axi_lite_wdata,
axi_wstrb => gpio_axi_lite_wstrb,
axi_bvalid => gpio_axi_lite_bvalid,
axi_bready => gpio_axi_lite_bready,
axi_bresp => gpio_axi_lite_bresp,
axi_araddr => gpio_axi_lite_araddr,
axi_arprot => gpio_axi_lite_arprot,
axi_arvalid => gpio_axi_lite_arvalid,
axi_arready => gpio_axi_lite_arready,
axi_rdata => gpio_axi_lite_rdata,
axi_rvalid => gpio_axi_lite_rvalid,
axi_rready => gpio_axi_lite_rready,
axi_rresp => gpio_axi_lite_rresp);
axi_cdma_inst : axi_cdma_0
PORT map (
m_axi_aclk => aclk,
s_axi_lite_aclk => aclk,
s_axi_lite_aresetn => aresetn(0),
cdma_introut => cdma_int,
s_axi_lite_awaddr => cdmareg_axi_lite_awaddr(5 downto 0),
s_axi_lite_awvalid => cdmareg_axi_lite_awvalid,
s_axi_lite_awready => cdmareg_axi_lite_awready,
s_axi_lite_wvalid => cdmareg_axi_lite_wvalid,
s_axi_lite_wready => cdmareg_axi_lite_wready,
s_axi_lite_wdata => cdmareg_axi_lite_wdata,
s_axi_lite_bvalid => cdmareg_axi_lite_bvalid,
s_axi_lite_bready => cdmareg_axi_lite_bready,
s_axi_lite_bresp => cdmareg_axi_lite_bresp,
s_axi_lite_araddr => cdmareg_axi_lite_araddr(5 downto 0),
s_axi_lite_arvalid => cdmareg_axi_lite_arvalid,
s_axi_lite_arready => cdmareg_axi_lite_arready,
s_axi_lite_rdata => cdmareg_axi_lite_rdata,
s_axi_lite_rvalid => cdmareg_axi_lite_rvalid,
s_axi_lite_rready => cdmareg_axi_lite_rready,
s_axi_lite_rresp => cdmareg_axi_lite_rresp,
m_axi_arready => cdma_axi_full_arready,
m_axi_arvalid => cdma_axi_full_arvalid,
m_axi_araddr => cdma_axi_full_araddr,
m_axi_arlen => cdma_axi_full_arlen,
m_axi_arsize => cdma_axi_full_arsize,
m_axi_arburst => cdma_axi_full_arburst,
m_axi_arprot => cdma_axi_full_arprot,
m_axi_arcache => cdma_axi_full_arcache,
m_axi_rready => cdma_axi_full_rready,
m_axi_rvalid => cdma_axi_full_rvalid,
m_axi_rdata => cdma_axi_full_rdata,
m_axi_rresp => cdma_axi_full_rresp,
m_axi_rlast => cdma_axi_full_rlast,
m_axi_awready => cdma_axi_full_awready,
m_axi_awvalid => cdma_axi_full_awvalid,
m_axi_awaddr => cdma_axi_full_awaddr,
m_axi_awlen => cdma_axi_full_awlen,
m_axi_awsize => cdma_axi_full_awsize,
m_axi_awburst => cdma_axi_full_awburst,
m_axi_awprot => cdma_axi_full_awprot,
m_axi_awcache => cdma_axi_full_awcache,
m_axi_wready => cdma_axi_full_wready,
m_axi_wvalid => cdma_axi_full_wvalid,
m_axi_wdata => cdma_axi_full_wdata,
m_axi_wstrb => cdma_axi_full_wstrb,
m_axi_wlast => cdma_axi_full_wlast,
m_axi_bready => cdma_axi_full_bready,
m_axi_bvalid => cdma_axi_full_bvalid,
m_axi_bresp => cdma_axi_full_bresp,
cdma_tvect_out => open);
plasoc_uart_inst : plasoc_uart
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
axi_awaddr => uart_axi_lite_awaddr,
axi_awprot => uart_axi_lite_awprot,
axi_awvalid => uart_axi_lite_awvalid,
axi_awready => uart_axi_lite_awready,
axi_wvalid => uart_axi_lite_wvalid,
axi_wready => uart_axi_lite_wready,
axi_wdata => uart_axi_lite_wdata,
axi_wstrb => uart_axi_lite_wstrb,
axi_bvalid => uart_axi_lite_bvalid,
axi_bready => uart_axi_lite_bready,
axi_bresp => uart_axi_lite_bresp,
axi_araddr => uart_axi_lite_araddr,
axi_arprot => uart_axi_lite_arprot,
axi_arvalid => uart_axi_lite_arvalid,
axi_arready => uart_axi_lite_arready,
axi_rdata => uart_axi_lite_rdata,
axi_rvalid => uart_axi_lite_rvalid,
axi_rready => uart_axi_lite_rready,
axi_rresp => uart_axi_lite_rresp,
tx => uart_tx,
rx => uart_rx,
status_in_avail => uart_int);
plasoc_timer_extra_0_inst : plasoc_timer
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
axi_awaddr => timer_extra_0_axi_lite_awaddr,
axi_awprot => timer_extra_0_axi_lite_awprot,
axi_awvalid => timer_extra_0_axi_lite_awvalid,
axi_awready => timer_extra_0_axi_lite_awready,
axi_wvalid => timer_extra_0_axi_lite_wvalid,
axi_wready => timer_extra_0_axi_lite_wready,
axi_wdata => timer_extra_0_axi_lite_wdata,
axi_wstrb => timer_extra_0_axi_lite_wstrb,
axi_bvalid => timer_extra_0_axi_lite_bvalid,
axi_bready => timer_extra_0_axi_lite_bready,
axi_bresp => timer_extra_0_axi_lite_bresp,
axi_araddr => timer_extra_0_axi_lite_araddr,
axi_arprot => timer_extra_0_axi_lite_arprot,
axi_arvalid => timer_extra_0_axi_lite_arvalid,
axi_arready => timer_extra_0_axi_lite_arready,
axi_rdata => timer_extra_0_axi_lite_rdata,
axi_rvalid => timer_extra_0_axi_lite_rvalid,
axi_rready => timer_extra_0_axi_lite_rready,
axi_rresp => timer_extra_0_axi_lite_rresp,
done => timer_extra_0_int);
end Behavioral;
|
mit
|
e7b9f10f05a8110633d6f582e18a2ee5
| 0.587357 | 3.30357 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/axi_qspi_xip_if.vhd
| 2 | 474,141 |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_qspi_xip_if.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_qspi_xip_if.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core
-- in XIP mode.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity axi_qspi_xip_if is
generic(
-- General Parameters
C_FAMILY : string := "virtex7";
Async_Clk : integer := 0;
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_SPI_MEM_ADDR_BITS : integer ; -- default is 24 bit, options are 24 or 32 bits
-------------------------
-- C_AXI4_CLK_PS : integer := 10000;--AXI clock period
-- C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_XIP_FIFO_DEPTH : integer := 64;-- Fixed value for XIP mode.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- Fixed 8 bit for XIP mode
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters
--*C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer ;-- range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_0100_0000", -- IP user0 base address
X"0000_0000_01FF_FFFF" -- IP user0 high address
);
C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
2,
1 -- User0 CE Number
)
);
port(
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
Rst_to_spi : in std_logic;
S_AXI4_ARESET : in std_logic;
-------------------------------
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR : in std_logic;
TO_XIPSR_trans_error : out std_logic;
--------------------------------
TO_XIPSR_mst_modf_err : out std_logic;
TO_XIPSR_axi_rx_full : out std_logic;
TO_XIPSR_axi_rx_empty : out std_logic;
XIPCR_1_CPOL : in std_logic;
XIPCR_0_CPHA : in std_logic;
-------------------------------
--*SPI port interface * --
-------------------------------
IO0_I : in std_logic; -- MOSI signal in standard SPI
IO0_O : out std_logic;
IO0_T : out std_logic;
-------------------------------
IO1_I : in std_logic; -- MISO signal in standard SPI
IO1_O : out std_logic;
IO1_T : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
---------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL : in std_logic;
-----
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
-----
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic
---------------------------------
);
end entity axi_qspi_xip_if;
--------------------------------------------------------------------------------
architecture imp of axi_qspi_xip_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0; -- 3/29/2013
constant ACTIVE_LOW_RESET : std_logic := '0';
constant CMD_BITS_LENGTH : integer:= 8; -- 3/29/2013
-----
-- code coverage -- function assign_addr_bits (logic_info : integer) return integer is
-- code coverage -- variable addr_width_24 : integer:= 24;
-- code coverage -- variable addr_width_32 : integer:= 32;
-- code coverage -- begin
-- code coverage -- if logic_info = 0 then -- old logic for 24 bit addressing
-- code coverage -- return addr_width_24;
-- code coverage -- else
-- code coverage -- return addr_width_32;
-- code coverage -- end if;
-- code coverage -- end function assign_addr_bits;
signal nm_wr_en_CMD : std_logic_vector(7 downto 0);
signal nm_4byte_addr_en_CMD : std_logic_vector(7 downto 0);
type NM_WR_EN_STATE_TYPE is
(NM_WR_EN_IDLE, -- decode command can be combined here later
NM_WR_EN,
NM_WR_EN_DONE
);
signal nm_wr_en_cntrl_ps : NM_WR_EN_STATE_TYPE;
signal nm_wr_en_cntrl_ns : NM_WR_EN_STATE_TYPE;
signal wr_en_under_process : std_logic;
signal wr_en_under_process_d1 : std_logic;
signal load_wr_en, wr_en_done_reg : std_logic;
signal wr_en_done_d1, wr_en_done_d2 : std_logic;
signal wr_en_done : std_logic;
signal data_loaded, cmd_sent : std_logic;
type NM_32_BIT_WR_EN_STATE_TYPE is
(NM_32_BIT_IDLE, -- decode command can be combined here later
NM_32_BIT_EN,
NM_32_BIT_EN_DONE
);
signal nm_sm_4_byte_addr_ps : NM_32_BIT_WR_EN_STATE_TYPE;
signal nm_sm_4_byte_addr_ns : NM_32_BIT_WR_EN_STATE_TYPE;
signal four_byte_en_under_process : std_logic;
signal four_byte_addr_under_process_d1 : std_logic;
signal load_4_byte_addr_en, four_byte_en_done, four_byte_en_done_reg : std_logic;
-----
-- constant declaration
constant FAST_READ : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00001011"; -- 0B
constant FAST_READ_DUAL_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="00111011"; -- 3B
constant FAST_READ_QUAD_IO : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0):="10111011"; -- BB
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_XIP_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH : integer := clog2(C_XIP_FIFO_DEPTH);
constant XIP_MIN_SIZE : std_logic_vector(31 downto 0):= X"00ffffff";-- 24 bit address
--constant XIP_ADDR_BITS : integer := 24;
constant XIP_ADDR_BITS : integer := C_SPI_MEM_ADDR_BITS; -- assign_addr_bits(NEW_LOGIC);
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
constant ACTIVE_HIGH_RESET : std_logic := '1';
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
constant ALL_1 : std_logic_vector(0 to RX_FIFO_CNTR_WIDTH-1)
:= (others => '0');
signal updown_cnt_en_rx,down_cnt_en_rx : std_logic;
type AXI_IF_STATE_TYPE is
(
IDLE, -- decode command can be combined here later
RD_BURST
);
signal xip_sm_ps: AXI_IF_STATE_TYPE;
signal xip_sm_ns: AXI_IF_STATE_TYPE;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
HPM_DUMMY,
ADDR_SEND,
TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,
TEMP_DATA_SEND,
DATA_RECEIVE,
TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ns : STATE_TYPE;
signal qspi_cntrl_ps : STATE_TYPE;
type WB_STATE_TYPE is
(WB_IDLE, -- decode command can be combined here later
WB_WR_HPM,
WB_DONE
);
signal wb_cntrl_ns : WB_STATE_TYPE;
signal wb_cntrl_ps : WB_STATE_TYPE;
signal valid_decode : std_logic;
signal s_axi_arready_cmb : std_logic;
signal temp_i : std_logic;
signal SS_frm_axi : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_int : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal SS_frm_axi_reg : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst : std_logic; --_vector(1 downto 0);
signal axi_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal size_length : std_logic_vector(1 downto 0);
signal S_AXI4_RID_reg : std_logic_vector(C_S_AXI4_ID_WIDTH-1 downto 0);
signal XIP_ADDR : std_logic_vector(XIP_ADDR_BITS-1 downto 0);
signal one_byte_transfer : std_logic;
signal two_byte_transfer : std_logic;
signal four_byte_transfer: std_logic;
signal dtr_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal write_length : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal dtr_cntr_empty : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal last_data : std_logic;
signal rd_error_int : std_logic;
signal Data_From_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal S_AXI4_RRESP_i : std_logic_vector(1 downto 0);
signal S_AXI4_RDATA_i : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
-- signal s_axi_rvalid_i : std_logic;
signal s_axi_rvalid_cmb : std_logic;
signal xip_pr_state_idle : std_logic;
signal pr_state_idle : std_logic;
signal rready_i : std_logic;
signal wrap_around_to_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal Rx_FIFO_Empty : std_logic;
signal IO0_T_cntrl_axi : std_logic;
signal IO1_T_cntrl_axi : std_logic;
signal IO2_T_cntrl_axi : std_logic;
signal IO3_T_cntrl_axi : std_logic;
signal SCK_T_cntrl_axi : std_logic;
signal load_axi_data_frm_axi : std_logic;
--signal Transmit_addr_int : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal Rx_FIFO_rd_ack : std_logic;
signal Data_To_Rx_FIFO : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal store_date_in_drr_fifo : std_logic;
--signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_almost_Full : std_logic;
signal Rx_FIFO_almost_Empty : std_logic;
--signal pr_state_idle : std_logic;
signal spiXfer_done_frm_spi_clk: std_logic;
signal mst_modf_err_frm_spi_clk: std_logic;
signal wrap_around_frm_spi_clk : std_logic;
signal one_byte_xfer_frm_axi_clk : std_logic;
signal two_byte_xfer_frm_axi_clk : std_logic;
signal four_byte_xfer_frm_axi_clk : std_logic;
signal load_axi_data_frm_axi_clk : std_logic;
--signal Transmit_Addr_frm_axi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_frm_axi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0);-- 3/30/2013
signal CPOL_frm_axi_clk : std_logic;
signal CPHA_frm_axi_clk : std_logic;
signal SS_frm_axi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_frm_axi_clk : std_logic; -- _vector(1 downto 0);
signal type_of_burst_frm_axi : std_logic; -- _vector(1 downto 0);
signal axi_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_frm_axi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal load_axi_data_to_spi_clk : std_logic;
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0); -- 3/30/2013
signal Transmit_Addr_to_spi_clk : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- 3/30/2013
signal last_7_addr_bits : std_logic_vector(7 downto 0);
signal CPOL_to_spi_clk : std_logic;
signal CPHA_to_spi_clk : std_logic;
signal SS_to_spi_clk : std_logic_vector(C_NUM_SS_BITS-1 downto 0);
signal type_of_burst_to_spi : std_logic;
signal type_of_burst_to_spi_clk : std_logic;
signal axi_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal dtr_length_to_spi_clk : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal wrap_around_to_axi_clk : std_logic;
signal spi_addr : std_logic_vector(31 downto 0);
signal spi_addr_i : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_int : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
signal spi_addr_wrap_1 : std_logic_vector(XIP_ADDR_BITS-1 downto 0); -- (23 downto 0);
--signal Transmit_Addr_to_spi_clk : std_logic_vector(23 downto 0);
signal load_wrap_addr : std_logic;
signal wrap_two : std_logic;
signal wrap_four : std_logic;
signal wrap_eight : std_logic;
signal wrap_sixteen : std_logic;
signal SPIXfer_done_int : std_logic;
signal size_length_cntr : std_logic_vector(1 downto 0);
signal size_length_cntr_fixed : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal cmd_addr_sent : std_logic;
signal SR_5_Tx_Empty, SR_5_Tx_Empty_d1, SR_5_Tx_Empty_d2 : std_logic;
signal wrap_around : std_logic;
signal rst_wrap_around : std_logic;
--signal pr_state_idle : std_logic;
signal one_byte_xfer_to_spi_clk : std_logic;
signal two_byte_xfer_to_spi_clk : std_logic;
signal four_byte_xfer_to_spi_clk : std_logic;
--signal store_date_in_drr_fifo : std_logic;
signal Data_To_Rx_FIFO_int : std_logic_vector(C_S_AXI4_DATA_WIDTH-1 downto 0);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal receive_Data_int : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
--signal Data_To_Rx_FIFO : std_logic_vector(7 downto 0);
--signal load_axi_data_to_spi_clk : std_logic;
signal Tx_Data_d1 : std_logic_vector(31 downto 0);
signal Tx_Data_d2 : std_logic_vector(39 downto 0);
signal internal_count : std_logic_vector(3 downto 0);
signal SPI_cmd : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);
signal Transmit_Data : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Data_Dir : std_logic;
signal Data_Mode_1 : std_logic;
signal Data_Mode_0 : std_logic;
signal Data_Phase : std_logic;
signal Quad_Phase : std_logic;
signal Addr_Mode_1 : std_logic;
signal Addr_Mode_0 : std_logic;
signal Addr_Bit : std_logic;
signal Addr_Phase : std_logic;
signal CMD_Mode_1 : std_logic;
signal CMD_Mode_0 : std_logic;
--signal cmd_addr_cntr : std_logic_vector(2 downto 0);
--signal cmd_addr_sent : std_logic;
signal transfer_start : std_logic;
signal last_bt_one_data : std_logic;
--signal SPIXfer_done_int : std_logic;
signal actual_SPIXfer_done_int : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
--signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
--signal SPIXfer_done_int : std_logic;
signal mode_1 : std_logic;
signal mode_0 : std_logic;
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
--signal receive_Data_int : std_logic_vector(7 downto 0);
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal sck_o_int : std_logic;
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal Shift_Reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal pr_state_cmd_ph : std_logic;
--signal qspi_cntrl_ps : std_logic;
signal stop_clock : std_logic;
signal stop_clock_reg : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
--signal pr_state_idle : std_logic;
--signal pr_state_cmd_ph : std_logic;
--signal SPIXfer_done_int_pulse : std_logic;
signal no_slave_selected : std_logic;
--signal rst_wrap_around : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal addr_cnt1 : std_logic_vector(1 downto 0);
signal pr_state_addr_ph : std_logic;
signal SS_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal IO0_T_cntrl_spi : std_logic;
signal MODF_strobe_int : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal MODF_strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal sck_o_in : std_logic;
--signal SCK_O_reg : std_logic;
signal slave_mode : std_logic;
--signal pr_state_non_idle : std_logic;
signal mst_modf_err_to_axi_clk : std_logic;
signal mst_modf_err_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi4_clk : std_logic;
signal Rx_FIFO_Full_to_axi_clk : std_logic;
signal Rx_FIFO_Full : std_logic;
signal Rx_FIFO_Full_org : std_logic;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : std_logic;
signal Rx_FIFO_Empty_Synced_in_AXI_domain : std_logic;
signal one_byte_xfer : std_logic;
signal two_byte_xfer : std_logic;
signal four_byte_xfer : std_logic;
signal XIP_trans_error : std_logic;
signal XIP_trans_cdc_to_error : std_logic;
signal load_cmd : std_logic;
signal load_cmd_to_spi_clk : std_logic;
--signal load_axi_data_frm_axi_clk : std_logic;
signal load_cmd_frm_axi_clk : std_logic;
signal axi_len_two : std_logic;
signal axi_len_four : std_logic;
signal axi_len_eight : std_logic;
signal axi_len_sixteen : std_logic;
signal reset_inversion : std_logic;
signal new_tr : std_logic;
signal SR_5_Tx_Empty_int : std_logic;
signal only_last_count : std_logic;
signal rx_fifo_cntr_rst, rx_fifo_not_empty : std_logic;
signal store_date_in_drr_fifo_d1 : std_logic;
signal store_date_in_drr_fifo_d2 : std_logic;
signal store_date_in_drr_fifo_d3 : std_logic;
signal xip_ns_state_idle : std_logic;
signal wrap_around_d1 : std_logic;
signal wrap_ack : std_logic;
signal wrap_ack_1 : std_logic;
signal wrap_around_d2 : std_logic;
signal wrap_around_d3 : std_logic;
signal start_after_wrap : std_logic;
signal store_last_b4_wrap : std_logic;
signal wrp_addr_len_16_siz_32 : std_logic;
signal wrp_addr_len_8_siz_32 : std_logic;
signal wrp_addr_len_4_siz_32 : std_logic;
signal wrp_addr_len_2_siz_32 : std_logic;
signal wrp_addr_len_16_siz_16 : std_logic;
signal wrp_addr_len_8_siz_16 : std_logic;
signal wrp_addr_len_4_siz_16 : std_logic;
signal wrp_addr_len_2_siz_16, start_after_wrap_d1 : std_logic;
signal SS_O_1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal WB_wr_en_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_sr_DATA : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal WB_wr_hpm_CMD : std_logic_vector(C_NUM_TRANSFER_BITS-1 downto 0);-- (7 downto 0);
signal wb_wr_en_done : std_logic;
signal wb_wr_sr_done : std_logic;
signal wb_wr_sr_data_done : std_logic;
signal wb_wr_hpm_done : std_logic;
signal load_wr_en_cmd : std_logic;
signal load_wr_sr_cmd : std_logic;
signal load_wr_sr_d0 : std_logic;
signal load_wr_sr_d1 : std_logic;
signal load_rd_sr : std_logic;
signal load_wr_hpm : std_logic;
signal wb_hpm_done : std_logic;
signal wb_hpm_done_reg : std_logic;
signal dis_sr_5_empty_reg : std_logic;
signal dis_sr_5_empty : std_logic;
signal wb_hpm_done_frm_spi,wb_hpm_done_frm_spi_clk,wb_hpm_done_to_axi : std_logic;
signal hpm_under_process : std_logic;
signal hpm_under_process_d1 : std_logic;
signal s_axi_rlast_cmb : std_logic;
signal store_date_in_drr_fifo_en : std_logic;
signal XIP_trans_error_cmb, XIP_trans_error_d1, XIP_trans_error_d2, XIP_trans_error_d3 : std_logic;
signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
signal arready_d1, arready_d2, arready_d3 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
signal axi4_tr_over_d3 : std_logic;
signal last_data_acked_int_2 : std_logic;
signal XIP_trans_error_int_2 : std_logic;
signal s_axi_arready_int_2 : std_logic;
-- signal XIP_trans_error_cmb : std_logic;
-- signal axi4_tr_over_d1, axi4_tr_over_d2 : std_logic;
-- signal arready_d1, arready_d2, arready_d3 : std_logic;
-- signal XIPSR_CPHA_CPOL_ERR_d1, XIPSR_CPHA_CPOL_ERR_d2 : std_logic;
-- signal axi4_tr_over_d3 : std_logic;
-- signal last_data_acked_int_2 : std_logic;
-- signal XIP_trans_error_int_2 : std_logic;
-- signal s_axi_arready_int_2 : std_logic;
signal Rx_FIFO_Empty_d1, Rx_FIFO_Empty_d2 : std_logic;
signal XIPSR_CPHA_CPOL_ERR_4 : std_logic;
--signal mst_modf_err_to_axi4clk: std_logic;
signal xip_done : std_logic;
signal en_xip : std_logic;
signal new_tr_at_axi4 : std_logic;
signal axi4_tr_over : std_logic;
signal fifo_ren :std_logic;
--attribute ASYNC_REG : string;
--attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
--attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
--attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
constant MTBF_STAGES_AXI2AXILITE : integer range 0 to 6 := 4 ;
-----
begin
-----
S_AXI4_WREADY <= '0';
S_AXI4_BID <= (others => '0');
S_AXI4_BRESP <= (others => '0');
S_AXI4_BVALID <= '0';
S_AXI4_AWREADY<= '0';
RX_FIFO_EMPTY_SYNC_AXI4_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_AXI_domain
);
RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
Rx_FIFO_Full <= Rx_FIFO_Full_org and not Rx_FIFO_Empty_Synced_in_SPI_domain;
valid_decode <= S_AXI4_ARVALID and xip_pr_state_idle;
reset_inversion <= not S_AXI4_ARESET;
-- address decoder and CS generation in AXI interface
I_DECODER : entity axi_quad_spi_v3_2_8.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => XIP_ADDR_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => XIP_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK, -- in std_logic;
Bus_rst => reset_inversion, -- in std_logic;
Address_In_Erly => S_AXI4_ARADDR(XIP_ADDR_BITS-1 downto 0), -- in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly => s_axi_arready_cmb, -- in std_logic;
Bus_RNW => valid_decode, -- in std_logic;
Bus_RNW_Erly => valid_decode, -- in std_logic;
CS_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
Clear_CS_CE_Reg => temp_i, -- in std_logic;
RW_CE_ld_enable => s_axi_arready_cmb, -- in std_logic;
CS_for_gaps => open, -- out std_logic;
-- Decode output signals
CS_Out => SS_frm_axi,
RdCE_Out => open,
WrCE_Out => open
);
-------------------------------------------------
STORE_AXI_ARBURST_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- S_AXI4_ARESET is already inverted and made active high
type_of_burst <= '0';-- "01"; -- default is INCR burst
elsif(s_axi_arready_cmb = '1')then
type_of_burst <= S_AXI4_ARBURST(1) ;
end if;
end if;
end process STORE_AXI_ARBURST_P;
-----------------------
S_AXI4_ARREADY_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_ARREADY <= '0';
else
S_AXI4_ARREADY <= s_axi_arready_cmb;
end if;
end if;
end process S_AXI4_ARREADY_P;
-- S_AXI4_ARREADY <= s_axi_arready_cmb;
STORE_AXI_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
axi_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
axi_length <= S_AXI4_ARLEN;
end if;
end if;
end process STORE_AXI_LENGTH_P;
---------------------------------------------------
STORE_AXI_SIZE_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
size_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
size_length <= S_AXI4_ARSIZE(1 downto 0);
end if;
end if;
end process STORE_AXI_SIZE_P;
-------------------------------------------------------------------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RID_reg <= (others=> '0');
elsif(s_axi_arready_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_ARID when (s_axi_arready_cmb = '1') else S_AXI4_RID_reg; --kar S_AXI4_RID_reg
-----------------------------
OLD_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(23 downto 0);-- support for 24 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate OLD_LOGIC_GEN;
---------------------------
NEW_LOGIC_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
STORE_AXI_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
XIP_ADDR <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
XIP_ADDR <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- support for 24 or 32 bit address
end if;
end if;
end process STORE_AXI_ADDR_P;
end generate NEW_LOGIC_GEN;
---------------------------
------------------------------------------------------------------------------
ONE_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
one_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
one_byte_xfer <= not(or_reduce(S_AXI4_ARSIZE(1 downto 0)));
end if;
end if;
end process ONE_BYTE_XFER_P;
TWO_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
two_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
two_byte_xfer <= S_AXI4_ARSIZE(0);
end if;
end if;
end process TWO_BYTE_XFER_P;
FOUR_BYTE_XFER_P:process(S_AXI4_ACLK) is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
four_byte_xfer <= '0';
elsif(s_axi_arready_cmb = '1')then
four_byte_xfer <= S_AXI4_ARSIZE(1);
end if;
end if;
end process FOUR_BYTE_XFER_P;
---------------------------------------------------------------------------------
STORE_DTR_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
dtr_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
dtr_length <= S_AXI4_ARLEN;-- + "00000001";
-- elsif(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then
--elsif(Rx_FIFO_rd_ack = '1') then
elsif(fifo_ren = '1') then
dtr_length <= dtr_length - '1';
end if;
end if;
end process STORE_DTR_LENGTH_P;
-----------------------------------------------------
STORE_WRITE_LENGTH_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then -- if(xip_sm_ps = IDLE)then
write_length <= (others => '0');
elsif(s_axi_arready_cmb = '1')then
write_length <= S_AXI4_ARLEN + "00000001";
elsif(spiXfer_done_to_axi_1 = '1')then
write_length <= write_length - '1';
end if;
end if;
end process STORE_WRITE_LENGTH_P;
-----------------------------------------------------
--dtr_cntr_empty <= or_Reduce(dtr_length);
-----------------------------------------------------
last_bt_one_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 1))) and
dtr_length(0) and
S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(dtr_length(C_NUM_TRANSFER_BITS-1 downto 0)));
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI4_ACLK, -- in
Rst => S_AXI4_ARESET, -- '0', -- in
-- coverage off
Load_In => ALL_1, -- in
-- coverage on
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => s_axi_arready_cmb,-- in
----------------
Count_Down => down_cnt_en_rx, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= s_axi_arready_cmb or
spiXfer_done_to_axi_1 or
(down_cnt_en_rx); -- this is to make the counter enable for decreasing.
down_cnt_en_rx <= S_AXI4_RREADY and s_axi_rvalid_i;
only_last_count <= not(or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0))) and
last_data_cmb;
rx_fifo_not_empty <= or_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto 0));
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
last_data_acked <= '0';
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then -- AXI Ready and Rlast active
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then-- AXI not Ready and Rlast active, then hold the RLAST signal
last_data_acked <= '1';
else
last_data_acked <=(last_data_cmb and
Rx_FIFO_rd_ack);
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= '1' when (last_data_cmb='1' and S_AXI4_ARESET /= ACTIVE_HIGH_RESET ) else '0';--last_data_acked;
--------------------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
S_AXI4_RRESP_i <= (others => '0');
--karS_AXI4_RDATA_i <= (others => '0');
else-- if(S_AXI4_RREADY = '1' )then -- and (Rx_FIFO_Empty = '0')then
S_AXI4_RRESP_i <= --(rd_error_int or mst_modf_err_to_axi_clk) & '0';
(mst_modf_err_to_axi4_clk) & '0';
--karS_AXI4_RDATA_i <= Data_From_Rx_FIFO;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
--------------------------------
S_AXI4_RRESP <= (mst_modf_err_to_axi4_clk) & '0';--S_AXI4_RRESP_i;
S_AXI4_RDATA <= Data_From_Rx_FIFO;--S_AXI4_RDATA_i;
-------------------------------
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
--karS_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar s_axi_rvalid_i <= '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '1')) then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
--kar s_axi_rvalid_i <= '0';--not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack; -- '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '0')) then -- and (s_axi_rvalid_i = '1') then -- AXI Ready and Rlast active
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack; -- '0';
--kar elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
--kar s_axi_rvalid_i <= s_axi_rvalid_i;
--kar else
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);--Rx_FIFO_rd_ack;
--kar end if;
--kar end if;
--karend process S_AXI_RVALID_I_P;
-----------------------------
--karS_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar s_axi_rvalid_i <= '0';
--kar else
--kar s_axi_rvalid_i <= not(Rx_FIFO_Empty);
--kar end if;
--kar end if;
--kar end process S_AXI_RVALID_I_P;
s_axi_rvalid_i <= not(Rx_FIFO_Empty);
S_AXI4_RVALID <= s_axi_rvalid_i;
fifo_ren <= S_AXI4_RREADY and s_axi_rvalid_i;
-- -----------------------------
--fifo_non_empty <= not(Rx_FIFO_Empty);
-----------------------------
-- REN_Generation : below process generates the Fifo_Ren
----------------------
--karREN_Generation : process (S_AXI4_ACLK) is
--kar begin
--kar if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
--kar if (S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
--kar fifo_ren <= '0';
--kar elsif(S_AXI4_RREADY = '1' and (s_axi_rvalid_i = '1')) then
--kar fifo_ren <= '1';
--kar else
--kar fifo_ren <= '0';--Rx_FIFO_rd_ack;
--kar end if;
--kar end if;
--karend process REN_Generation;
-----------------------------
xip_pr_state_idle <= '1' when xip_sm_ps = IDLE else '0';
xip_ns_state_idle <= '1' when xip_sm_ns = IDLE else '0';
rready_i <= S_AXI4_RREADY and not last_data_cmb;
------------------------------------------------------------------------------
XIP_trans_error_cmb <= not(or_reduce(S_AXI4_ARBURST)) and (S_AXI4_ARVALID);
-- XIP_TR_ERROR_PULSE_STRETCH_1: single pulse for AXI4 transaction error
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of XIP_TRANS_ERROR_AXI2AXI4_CDC : label is "TRUE";
--attribute ASYNC_REG of Rx_FIFO_Empty_AXI42AXI : label is "TRUE";
attribute ASYNC_REG of CPHA_CPOL_ERR_AXI2AXI4_CDC : label is "TRUE";
attribute ASYNC_REG of ARREADY_PULSE_AXI42AXI_CDC: label is "TRUE";
attribute ASYNC_REG of AXI4_TR_OVER_AXI42AXI_CDC : label is "TRUE";
begin
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
-------------------------------------
XIP_TRANS_ERROR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d1,
C => S_AXI_ACLK,
D => XIP_trans_error_int_2,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d2,
C => S_AXI_ACLK,
D => XIP_trans_error_d1,
R => S_AXI_ARESETN
);
XIP_TRANS_ERROR_AXI2AXI4_2: component FDR
generic map(INIT => '0'
)port map (
Q => XIP_trans_error_d3,
C => S_AXI_ACLK,
D => XIP_trans_error_d2,
R => S_AXI_ARESETN
);
XIP_trans_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
------------------------------------------------------------------------------
--mst_modf_err_to_axi <= mst_modf_err_d2;
-- TO XIP Status Register
-- LAST_DATA_PULSE_STRETCH_1: single pulse for AXI4 transaction completion
LAST_DATA_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
-------------------------------------
AXI4_TR_OVER_AXI42AXI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d1,
C => S_AXI_ACLK,
D => last_data_acked_int_2,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d2,
C => S_AXI_ACLK,
D => axi4_tr_over_d1,
R => S_AXI_ARESETN
);
AXI4_TR_OVER_AXI42AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => axi4_tr_over_d3,
C => S_AXI_ACLK,
D => axi4_tr_over_d2,
R => S_AXI_ARESETN
);
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
-------------------------------------------------------------
-- ARREADY_PULSE_STRETCH_1: single pulse for AXI4 transaction acceptance
ARREADY_PULSE_STRETCH_1: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
-------------------------------------
ARREADY_PULSE_AXI42AXI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d1,
C => S_AXI_ACLK,
D => s_axi_arready_int_2,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_2: component FDR
generic map(INIT => '1'
)port map (
Q => arready_d2,
C => S_AXI_ACLK,
D => arready_d1,
R => S_AXI_ARESETN
);
ARREADY_PULSE_AXI42AXI_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => arready_d3,
C => S_AXI_ACLK,
D => arready_d2,
R => S_AXI_ARESETN
);
new_tr_at_axi4 <= arready_d2 xor arready_d3;
-------------------------------------
------------------------------------------------------------------------------
-- CPHA_CPOL_ERR_AXI2AXI4_CDC: CDC flop at cross clock boundary
CPHA_CPOL_ERR_AXI2AXI4_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d1,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR,
R => S_AXI4_ARESET
);
CPHA_CPOL_ERR_AXI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => XIPSR_CPHA_CPOL_ERR_d2,
C => S_AXI4_ACLK,
D => XIPSR_CPHA_CPOL_ERR_d1,
R => S_AXI4_ARESET
);
XIPSR_CPHA_CPOL_ERR_4 <= XIPSR_CPHA_CPOL_ERR_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
--=================================================================================
XIP_TR_ERROR_PULSE_STRETCH_1_P: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
XIP_trans_error_int_2 <= '0';
else
XIP_trans_error_int_2 <= XIP_trans_error_cmb xor
XIP_trans_error_int_2;
end if;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1_P;
XIP_TRANS_ERROR_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIP_trans_error_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => XIP_trans_error_d2
);
XIP_TR_ERROR_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
XIP_trans_error_d3 <= XIP_trans_error_d2 ;
end if;
end process XIP_TR_ERROR_PULSE_STRETCH_1;
XIP_trans_cdc_to_error <= XIP_trans_error_d2 xor XIP_trans_error_d3;
XIP_trans_error <= XIP_trans_cdc_to_error;
--=================================================================================
LAST_DATA_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
last_data_acked_int_2 <= '0';
--axi4_tr_over_d1 <= '0';
else
last_data_acked_int_2 <= last_data_acked xor
last_data_acked_int_2;
--axi4_tr_over_d1 <= last_data_acked_int_2;
end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1_CDC;
AXI4_TR_OVER_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => last_data_acked_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => axi4_tr_over_d2
);
LAST_DATA_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
axi4_tr_over_d3 <= axi4_tr_over_d2 ;
-- end if;
end if;
end process LAST_DATA_PULSE_STRETCH_1;
axi4_tr_over <= axi4_tr_over_d2 xor axi4_tr_over_d3;
--=================================================================================
ARREADY_PULSE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
s_axi_arready_int_2 <= '1';
--arready_d1 <= '0';
else
s_axi_arready_int_2 <= s_axi_arready_cmb xor
s_axi_arready_int_2;
--arready_d1 <= s_axi_arready_int_2;
end if;
end if;
end process ARREADY_PULSE_STRETCH_1_CDC;
ARREADY_PULSE_AXI42AXI: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => s_axi_arready_int_2 ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => arready_d2
);
ARREADY_PULSE_STRETCH_1: process(S_AXI_ACLK)is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK= '1') then
arready_d3 <= arready_d2;
-- end if;
end if;
end process ARREADY_PULSE_STRETCH_1;
new_tr_at_axi4 <= arready_d2 xor arready_d3;
--==================================================================================
CPHA_CPOL_ERR_AXI2AXI4: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2AXILITE
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => XIPSR_CPHA_CPOL_ERR ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0') ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => XIPSR_CPHA_CPOL_ERR_4
);
--==================================================================================
end generate LOGIC_GENERATION_CDC;
TO_XIPSR_axi_rx_empty <= Rx_FIFO_Empty_Synced_in_AXI_domain;
--XIPSR_RX_EMPTY_P: process(S_AXI_ACLK)is
--begin
-- if(S_AXI_ACLK'event and S_AXI_ACLK = '1')then
-- if(S_AXI_ARESETN = ACTIVE_HIGH_RESET) then
-- TO_XIPSR_axi_rx_empty <= '1';
-- elsif(axi4_tr_over = '1')then
-- TO_XIPSR_axi_rx_empty <= '1';
-- elsif(new_tr_at_axi4 = '1')then
-- TO_XIPSR_axi_rx_empty <= '0';
-- end if;
-- end if;
--end process XIPSR_RX_EMPTY_P;
-------------------------------------
TO_XIPSR_trans_error <= XIP_trans_error;
TO_XIPSR_mst_modf_err <= mst_modf_err_to_axi_clk;
TO_XIPSR_axi_rx_full <= Rx_FIFO_Full_to_axi_clk;
-- XIP_PS_TO_NS_PROCESS: stores the next state memory
XIP_PS_TO_NS_PROCESS: process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
xip_sm_ps <= IDLE;
else
xip_sm_ps <= xip_sm_ns;
end if;
end if;
end process XIP_PS_TO_NS_PROCESS;
-----------------------------
-- XIP_SM_P: below state machine is AXI interface state machine and controls the
-- acceptance of new transaction as well as monitors data transaction
XIP_SM_P:process(
xip_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_RREADY ,
S_AXI4_ARBURST ,
XIP_trans_error_cmb ,
mst_modf_err_to_axi4_clk,
Rx_FIFO_Full_to_Axi4_clk,
XIPSR_CPHA_CPOL_ERR_4 ,
Rx_FIFO_Empty ,
wb_hpm_done_to_axi ,
spiXfer_done_to_axi_1 ,
last_data_cmb ,
Rx_FIFO_rd_ack ,--,
last_data_acked
--wrap_around_to_axi_clk ,
--last_bt_one_data_cmb ,
--Rx_FIFO_Empty ,
--only_last_count ,
--rx_fifo_not_empty ,
--rx_fifo_count ,
)is
begin
-----
s_axi_arready_cmb <= '0';
load_axi_data_frm_axi <= '0';
load_cmd <= '0';
s_axi_rlast_cmb <= '0';
s_axi_rvalid_cmb <= '0';
last_data <= '0';
--IO0_T_cntrl_axi <= '1';
--IO1_T_cntrl_axi <= '1';
--IO2_T_cntrl_axi <= '1';
--IO3_T_cntrl_axi <= '1';
--SCK_T_cntrl_axi <= '1';
temp_i <= '0';
case xip_sm_ps is
when IDLE => --if(XIP_cmd_error = '0') then
if(S_AXI4_ARVALID = '1') and
(XIP_trans_error_cmb = '0') and
(mst_modf_err_to_axi4_clk = '0') and
(Rx_FIFO_Full_to_axi4_clk = '0') and
(XIPSR_CPHA_CPOL_ERR_4 = '0') and
(Rx_FIFO_Empty = '1') and
(wb_hpm_done_to_axi = '1')
then
s_axi_arready_cmb <= S_AXI4_ARVALID;
load_axi_data_frm_axi <= S_AXI4_ARVALID;
load_cmd <= S_AXI4_ARVALID;
xip_sm_ns <= RD_BURST;
else
xip_sm_ns <= IDLE;
end if;
when RD_BURST =>
--if(last_data_cmb = '1') and (Rx_FIFO_rd_ack = '1') then--(rx_fifo_count = "000001") then
if (last_data_acked = '1') then
if(S_AXI4_RREADY = '1') then
temp_i <= '1';
xip_sm_ns <= IDLE;
else
xip_sm_ns <= RD_BURST;
end if;
else
xip_sm_ns <= RD_BURST;
end if;
-- coverage off
when others => xip_sm_ns <= IDLE;
-- coverage on
end case;
end process XIP_SM_P;
----------------------
-- AXI_24_BIT_ADDR_STORE_GEN: stores 24 bit axi address
AXI_24_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(23 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_24_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- AXI_32_BIT_ADDR_STORE_GEN: stores 32 bit axi address
AXI_32_BIT_ADDR_STORE_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013 updated for 32 or 24 bit addressing modes
begin
LOAD_TRANSMIT_ADDR_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if(S_AXI4_ARESET = ACTIVE_HIGH_RESET) then
Transmit_addr_int <= (others => '0');
elsif(load_axi_data_frm_axi = '1') then
Transmit_addr_int <= S_AXI4_ARADDR(C_SPI_MEM_ADDR_BITS-1 downto 0);-- & XIPCR_7_0_CMD;
end if;
end if;
end process LOAD_TRANSMIT_ADDR_P;
end generate AXI_32_BIT_ADDR_STORE_GEN;
-----------------------------------------
-- 24/32-bit --
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full_org
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
-------------------------------------------------------------------------------
XIP_RECEIVE_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg
generic map(
-- 3/30/2013 starts
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- 3/30/2013 ends
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer := 16;
C_FIFO_DEPTH => C_XIP_FIFO_DEPTH , -- : integer := 256;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT, -- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT, -- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => fifo_ren , --S_AXI4_RREADY , -- : in std_logic := '0';
Rd_clk => S_AXI4_ACLK , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => store_date_in_drr_fifo_en , --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => open, -- Rx_FIFO_wr_ack_open, -- : out std_logic;
------
Full => Rx_FIFO_Full_org, --Rx_FIFO_Full, -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => Rst_to_spi ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => rd_error_int , -- : out std_logic;
Wr_err => open -- : out std_logic
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- from SPI clock
spiXfer_done_frm_spi_clk <= store_date_in_drr_fifo_en; --spiXfer_done_int;
mst_modf_err_frm_spi_clk <= not SPISEL_sync; -- 9/7/2013 -- MODF_strobe; -- 9/7/2013
--wrap_around_frm_spi_clk <= wrap_around;
wb_hpm_done_frm_spi_clk <= wb_hpm_done;
-- from AXI clocks
--size_length_frm_axi_clk <= size_length;
one_byte_xfer_frm_axi_clk <= one_byte_xfer;
two_byte_xfer_frm_axi_clk <= two_byte_xfer;
four_byte_xfer_frm_axi_clk <= four_byte_xfer;
load_axi_data_frm_axi_clk <= load_axi_data_frm_Axi;-- 1 bit
Transmit_Addr_frm_axi_clk <= Transmit_addr_int; -- 24 bit
load_cmd_frm_axi_clk <= load_cmd;
CPOL_frm_axi_clk <= XIPCR_1_CPOL; -- 1 bit
CPHA_frm_axi_clk <= XIPCR_0_CPHA; -- 1 bit
SS_frm_axi_clk <= SS_frm_axi; -- _reg; -- based upon C_NUM_SS_BITS
type_of_burst_frm_axi_clk <= type_of_burst; -- 1 bit signal take MSB only to differentiate WRAP and INCR burst
axi_length_frm_axi_clk <= axi_length; -- 8 bit used for WRAP transfer
dtr_length_frm_axi_clk <= dtr_length; -- 8 bit used for internbal counter
XIP_CLK_DOMAIN_SIGNALS:entity axi_quad_spi_v3_2_8.xip_cross_clk_sync
generic map(
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
Async_Clk => Async_Clk ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEM_ADDR_BITS => XIP_ADDR_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,
S_AXI4_ACLK => S_AXI4_ACLK ,
S_AXI4_ARESET => S_AXI4_ARESET ,
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
Rst_from_axi_cdc_to_spi => Rst_to_spi ,
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk ,
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1 ,
----------------------------
mst_modf_err_cdc_from_spi => mst_modf_err_frm_spi_clk ,
mst_modf_err_cdc_to_axi => mst_modf_err_to_axi_clk ,
mst_modf_err_cdc_to_axi4 => mst_modf_err_to_axi4_clk ,
----------------------------
one_byte_xfer_cdc_from_axi => one_byte_xfer_frm_axi_clk ,
one_byte_xfer_cdc_to_spi => one_byte_xfer_to_spi_clk ,
----------------------------
two_byte_xfer_cdc_from_axi => two_byte_xfer_frm_axi_clk ,
two_byte_xfer_cdc_to_spi => two_byte_xfer_to_spi_clk ,
----------------------------
four_byte_xfer_cdc_from_axi => four_byte_xfer_frm_axi_clk ,
four_byte_xfer_cdc_to_spi => four_byte_xfer_to_spi_clk ,
----------------------------
load_axi_data_cdc_from_axi => load_axi_data_frm_axi_clk ,
load_axi_data_cdc_to_spi => load_axi_data_to_spi_clk ,
----------------------------
Transmit_Addr_cdc_from_axi => Transmit_Addr_frm_axi_clk ,
Transmit_Addr_cdc_to_spi => Transmit_Addr_to_spi_clk ,
----------------------------
load_cmd_cdc_from_axi => load_cmd_frm_axi_clk ,
load_cmd_cdc_to_spi => load_cmd_to_spi_clk ,
----------------------------
CPOL_cdc_from_axi => CPOL_frm_axi_clk ,
CPOL_cdc_to_spi => CPOL_to_spi_clk ,
----------------------------
CPHA_cdc_from_axi => CPHA_frm_axi_clk ,
CPHA_cdc_to_spi => CPHA_to_spi_clk ,
------------------------------
SS_cdc_from_axi => SS_frm_axi_clk ,
SS_cdc_to_spi => SS_to_spi_clk ,
----------------------------
type_of_burst_cdc_from_axi => type_of_burst_frm_axi_clk ,
type_of_burst_cdc_to_spi => type_of_burst_to_spi_clk ,
----------------------------
axi_length_cdc_from_axi => axi_length_frm_axi_clk ,
axi_length_cdc_to_spi => axi_length_to_spi_clk ,
----------------------------
dtr_length_cdc_from_axi => dtr_length_frm_axi_clk ,
dtr_length_cdc_to_spi => dtr_length_to_spi_clk , --,
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full ,
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk ,
Rx_FIFO_Full_cdc_to_axi4 => Rx_FIFO_Full_to_axi4_clk ,
----------------------------
wb_hpm_done_cdc_from_spi => wb_hpm_done_frm_spi_clk ,
wb_hpm_done_cdc_to_axi => wb_hpm_done_to_axi
);
-------------------------------------------------------------------------------
-- STORE_NEW_TR_P: This process is used in INCR and WRAP to check for any new transaction from AXI
STORE_NEW_TR_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1') -- needed for enabling 32 bit addressing mode
or (load_wr_en = '1') -- needed for write enabling before enabling the 32 bit addressing mode
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_32_BIT_ADDR_GEN;
---------------------------------------------
STORE_NEW_TR_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_NEW_TR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
new_tr <= '0';
elsif( (load_axi_data_to_spi_clk = '1')
or (load_wr_hpm = '1')
-- or (load_wr_en = '1')
) then
new_tr <= '1';
elsif(SR_5_Tx_Empty_int = '1') then --(wrap_around = '0' and qspi_cntrl_ns = IDLE)then
new_tr <= '0';
end if;
end if;
end process STORE_NEW_TR_P;
-------------------------------------
end generate STORE_NEW_TR_24_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- STORE_INITAL_ADDR_P: The address frm AXI should be stored in the SPI environment
-- as the address generation logic will work in this domain.
STORE_24_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
-------------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= "00000000" & Transmit_Addr_to_spi_clk;-- (31 downto 8);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= "00000000" & spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
-------------------------------------
end generate STORE_24_BIT_SPI_ADDR_GEN;
-----------------------------------------
STORE_32_BIT_SPI_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate -- 3/30/2013
begin
-----
----------------------------------
STORE_INITAL_ADDR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
spi_addr <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
spi_addr <= Transmit_Addr_to_spi_clk;-- (31 downto 0);
elsif(load_wrap_addr = '1')then -- and (type_of_burst_to_spi = '1') then
spi_addr <= spi_addr_wrap;
end if;
end if;
end process STORE_INITAL_ADDR_P;
----------------------------------
end generate STORE_32_BIT_SPI_ADDR_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- below signals will store the length of AXI transaction in the SPI domain
axi_len_two <= not(or_Reduce(axi_length_to_spi_clk(3 downto 1))) and
axi_length_to_spi_clk(0);
axi_len_four <= not(or_Reduce(axi_length_to_spi_clk(3 downto 2))) and
and_reduce(axi_length_to_spi_clk(1 downto 0));
axi_len_eight <= not(axi_length_to_spi_clk(3)) and
and_Reduce(axi_length_to_spi_clk(2 downto 0));
axi_len_sixteen <= and_reduce(axi_length_to_spi_clk(3 downto 0));
-------------------------------------------------------------------------------
-- below signals store the WRAP information in SPI domain
wrap_two <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_two = '1')
else
'0';
wrap_four <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_four = '1')
else
'0';
wrap_eight <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_eight = '1')
else
'0';
wrap_sixteen <= '1' when (type_of_burst_to_spi_clk = '1' and
axi_len_sixteen = '1')
else
'0';
-------------------------------------------------------------------------------
-- SPI_ADDRESS_REG: This process stores the initial address coming from the AXI in
-- two registers. one register will store this address till the
-- transaction ends, while other will be updated based upon type of
-- transaction as well as at the end of each SPI transfer. this is
-- used for internal use only.
SPI_24_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(23 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(23 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(23 downto 0) <= spi_addr_int(23 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 1) <= spi_addr_i(23 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 2) <= spi_addr_i(23 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(23 downto 3) <= spi_addr_i(23 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(23 downto 4) <= spi_addr_i(23 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(23 downto 5) <= spi_addr_i(23 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(23 downto 6) <= spi_addr_i(23 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(23 downto 0) <= spi_addr_i(23 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
----------------------------------
end generate SPI_24_BIT_ADDRESS_REG_GEN;
----------------------------------------
SPI_32_BIT_ADDRESS_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
SPI_ADDRESS_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_i <= (others => '0');
spi_addr_int <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_i <= Transmit_Addr_to_spi_clk(31 downto 0);
spi_addr_int <= Transmit_Addr_to_spi_clk(31 downto 0);
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_int(31 downto 0) <= spi_addr_int(31 downto 0) + '1';
case size_length_cntr is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 1) <= spi_addr_i(31 downto 1);
spi_addr_i(0) <= not (spi_addr_i(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0001";
else
spi_addr_i <= spi_addr_i + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 2) <= spi_addr_i(31 downto 2);
spi_addr_i(1 downto 0) <= spi_addr_i(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <= spi_addr_i(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <= spi_addr_i(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <= spi_addr_i(4 downto 0) + "00010";
else
spi_addr_i <= spi_addr_i + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_i(31 downto 3) <= spi_addr_i(31 downto 3);
spi_addr_i(2 downto 0) <=spi_addr_i(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_i(31 downto 4) <= spi_addr_i(31 downto 4);
spi_addr_i(3 downto 0) <=spi_addr_i(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_i(31 downto 5) <= spi_addr_i(31 downto 5);
spi_addr_i(4 downto 0) <=spi_addr_i(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_i(31 downto 6) <= spi_addr_i(31 downto 6);
spi_addr_i(5 downto 0) <=spi_addr_i(5 downto 0) + "000100";
else
spi_addr_i <= spi_addr_i + "0100";
end if;
-- coverage off
when others =>
spi_addr_i <= spi_addr_i;
-- coverage on
end case;
-- below is address generation for the INCR mode
elsif (type_of_burst_to_spi_clk = '0') and
(SPIXfer_done_int_pulse_d2 = '1') and
(cmd_addr_sent = '1') then
spi_addr_i(31 downto 0) <= spi_addr_i(31 downto 0) + '1';
end if;
end if;
end if;
end process SPI_ADDRESS_REG;
end generate SPI_32_BIT_ADDRESS_REG_GEN;
----------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
SPI_24_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(23 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 1) <= spi_addr_wrap(23 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 2) <= spi_addr_wrap(23 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(23 downto 3) <= spi_addr_wrap(23 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(23 downto 4) <= spi_addr_wrap(23 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(23 downto 5) <= spi_addr_wrap(23 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(23 downto 6) <= spi_addr_wrap(23 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
end generate SPI_24_WRAP_ADDR_REG_GEN;
--------------------------------------
SPI_32_WRAP_ADDR_REG_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
--variable xfer : std_logic_vector(2 downto 0);
begin
-- xfer := four_byte_xfer_to_spi_clk & two_byte_xfer_to_spi_clk & one_byte_xfer_to_spi_clk;
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap <= (others => '0');
else
if (load_cmd_to_spi_clk = '1') then
spi_addr_wrap <= Transmit_Addr_to_spi_clk(31 downto 0);
elsif(wrap_ack_1 = '1') then
spi_addr_wrap <= spi_addr_wrap_1;
-- below is address generation for the WRAP mode
elsif (type_of_burst_to_spi_clk = '1') and
(store_date_in_drr_fifo = '1') and
(cmd_addr_sent = '1') then
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 1) <= spi_addr_wrap(31 downto 1);
spi_addr_wrap(0) <= not (spi_addr_wrap(0));
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0001";
else
spi_addr_wrap <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 2) <= spi_addr_wrap(31 downto 2);
spi_addr_wrap(1 downto 0) <= spi_addr_wrap(1 downto 0) + "10";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <= spi_addr_wrap(2 downto 0) + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <= spi_addr_wrap(3 downto 0) + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <= spi_addr_wrap(4 downto 0) + "00010";
else
spi_addr_wrap <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap(31 downto 3) <= spi_addr_wrap(31 downto 3);
spi_addr_wrap(2 downto 0) <=spi_addr_wrap(2 downto 0) + "100";
elsif(wrap_four = '1') then
spi_addr_wrap(31 downto 4) <= spi_addr_wrap(31 downto 4);
spi_addr_wrap(3 downto 0) <=spi_addr_wrap(3 downto 0) + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap(31 downto 5) <= spi_addr_wrap(31 downto 5);
spi_addr_wrap(4 downto 0) <=spi_addr_wrap(4 downto 0) + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap(31 downto 6) <= spi_addr_wrap(31 downto 6);
spi_addr_wrap(5 downto 0) <=spi_addr_wrap(5 downto 0) + "000100";
else
spi_addr_wrap <= spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process SPI_WRAP_ADDR_REG;
----------------------------------
end generate SPI_32_WRAP_ADDR_REG_GEN;
--------------------------------------
-------------------------------------------------------------------------------
-- SPI_WRAP_ADDR_REG: this is separate process used for WRAP address generation
LOAD_SPI_WRAP_ADDR_REG : process(EXT_SPI_CLK) is
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE) then
spi_addr_wrap_1 <= (others => '0');
else
if (wrap_around = '1') then
-- below is address generation for the WRAP mode
case size_length_cntr_fixed is
when "00" => -- 8-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + '1';
elsif(wrap_four = '1') then -- the byte address increment will take 2 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "01";
elsif(wrap_eight = '1') then -- the byte address increment will take 3 address bits
spi_addr_wrap_1 <= spi_addr_wrap + "001";
elsif(wrap_sixteen = '1') then -- the byte address increment will take 4 address bits for 16's wrap
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0001";
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "10";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "010";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <= spi_addr_wrap + "00010";
else
spi_addr_wrap_1 <= spi_addr_wrap + "0010";
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "100";
elsif(wrap_four = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
elsif(wrap_eight = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "00100";
elsif(wrap_sixteen = '1') then
spi_addr_wrap_1 <=spi_addr_wrap + "000100";
else
spi_addr_wrap_1 <=spi_addr_wrap + "0100";
end if;
-- coverage off
when others =>
spi_addr_wrap_1 <= spi_addr_wrap;
-- coverage on
end case;
end if;
end if;
end if;
end process LOAD_SPI_WRAP_ADDR_REG;
-------------------------------------------------------------------------------
-- WRAP_AROUND_GEN_P : WRAP boundary detection logic
WRAP_AROUND_GEN_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if( (Rst_to_spi = '1')
or(rst_wrap_around = '1')
) then
wrap_around <= '0';
elsif(type_of_burst_to_spi_clk = '1')then
case size_length_cntr_fixed is
when "00" => -- byte transfer
if(wrap_two = '1') and
(spi_addr_wrap(1) = '1') and
(store_date_in_drr_fifo = '1')then -- then
wrap_around <= --spi_addr_wrap(1) and
not SR_5_Tx_Empty;
elsif(wrap_four = '1') and
(spi_addr_wrap(1 downto 0) = "11") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 2 address bits
wrap_around <= --and_reduce(spi_addr_wrap(1 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_eight = '1') and
(spi_addr_wrap(2 downto 0) = "111") and
(store_date_in_drr_fifo = '1')then -- then -- the byte address increment will take 3 address bits
wrap_around <= --and_reduce(spi_addr_wrap(2 downto 0)) and
not SR_5_Tx_Empty;
elsif(wrap_sixteen = '1') and
(spi_addr_wrap(3 downto 0) = "1111") and
(store_date_in_drr_fifo = '1')then -- the byte address increment will take 4 address bits for 16's wrap
wrap_around <= --and_reduce(spi_addr_wrap(3 downto 0)) and
not SR_5_Tx_Empty;
else
wrap_around <= '0';
end if;
when "01" => -- 16-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(1 downto 0) = "10") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_16;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(2 downto 0) = "110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_16;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(3 downto 0) = "1110") and (store_date_in_drr_fifo = '1')then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_16;
elsif(wrap_sixteen = '1') then -- and (spi_addr_wrap(4 downto 0) = "11110") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_16;
else
wrap_around <= '0';
end if;
when "10" => -- 32-bit access
if(wrap_two = '1') then -- and (spi_addr_wrap(2 downto 0) = "100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_2_siz_32;
elsif(wrap_four = '1') then -- and (spi_addr_wrap(3 downto 0) = "1100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_4_siz_32;
elsif(wrap_eight = '1') then -- and (spi_addr_wrap(4 downto 0) = "11100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_8_siz_32;
elsif(wrap_sixteen = '1') then --and (spi_addr_wrap(5 downto 0) = "111100") and (store_date_in_drr_fifo = '1') then
wrap_around <= not SR_5_Tx_Empty and
store_date_in_drr_fifo and
wrp_addr_len_16_siz_32;
else
wrap_around <= '0';
end if;
-- coverage off
when others => wrap_around <= wrap_around;
-- coverage on
end case;
end if;
end if;
end process WRAP_AROUND_GEN_P;
-------------------------------------------------------------------------------
load_wrap_addr <= wrap_around;
wrp_addr_len_16_siz_32 <= '1' when (spi_addr_wrap(5 downto 0) = "111100") else '0';
wrp_addr_len_8_siz_32 <= '1' when (spi_addr_wrap(4 downto 0) = "11100") else '0';
wrp_addr_len_4_siz_32 <= '1' when (spi_addr_wrap(3 downto 0) = "1100") else '0';
wrp_addr_len_2_siz_32 <= '1' when (spi_addr_wrap(2 downto 0) = "100") else '0';
-----------------------------------------------------------------------------------
wrp_addr_len_16_siz_16 <= '1' when (spi_addr_wrap(4 downto 0) = "11110") else '0';
wrp_addr_len_8_siz_16 <= '1' when (spi_addr_wrap(3 downto 0) = "1110") else '0';
wrp_addr_len_4_siz_16 <= '1' when (spi_addr_wrap(2 downto 0) = "110") else '0';
wrp_addr_len_2_siz_16 <= '1' when (spi_addr_wrap(1 downto 0) = "10") else '0';
-----------------------------------------------------------------------------------
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytes are transferred from SPI.
LEN_CNTR_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000011";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_24_BIT_GEN;
---------------------------------
LEN_CNTR_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
LEN_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
length_cntr <= (others => '0');
elsif(load_wr_hpm='1') then
length_cntr <= "00000000";
elsif(load_cmd_to_spi_clk = '1')then
length_cntr <= dtr_length_to_spi_clk;
elsif((SPIXfer_done_int = '1') and
(((size_length_cntr = "00") and
(cmd_addr_sent = '1')
)or
(hpm_under_process_d1 = '1') or (wr_en_under_process_d1 = '1'))
)then
length_cntr <= length_cntr - "00000001";
end if;
end if;
end process LEN_CNTR_P;
-----------------------
end generate LEN_CNTR_32_BIT_GEN;
---------------------------------
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process or wr_en_under_process) and
not(or_reduce(length_cntr)) and
SPIXfer_done_int_pulse);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1') then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
SR_5_TX_EMPTY_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SR_5_Tx_Empty_int<= (not(or_reduce(length_cntr)) and
store_date_in_drr_fifo and
cmd_addr_sent)
or
(-- (hpm_under_process_d1 or wr_en_under_process_d1) and
(hpm_under_process
--or wr_en_under_process
)
and
not(
or_reduce(length_cntr))
and
SPIXfer_done_int_pulse
);
-- LEN_CNTR_P: This is data length counter. this counter will start decrementing
-- only when the first 4 bytesfor 24 bit addressing and 5 bytes for 32 bit addressing mode are transferred from SPI.
SR_5_TX_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty <= '1';
elsif(load_cmd_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
SR_5_Tx_Empty <= '0';
elsif(SR_5_Tx_Empty_int = '1')then
SR_5_Tx_Empty <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_P;
end generate SR_5_TX_EMPTY_24_BIT_ADDR_GEN;
-------------------------------------------
DELAY_FIFO_EMPTY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
SR_5_Tx_Empty_d1 <= '1';
SR_5_Tx_Empty_d2 <= '1';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
SR_5_Tx_Empty_d2 <= SR_5_Tx_Empty_d1;
end if;
end if;
end process DELAY_FIFO_EMPTY_P;
-------------------------------------------------------------------------------
last_bt_one_data <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0);
-------------------------------------------------------------------------------
SIZE_CNTR_LD_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
size_length_cntr_fixed <= (others => '0');
size_length_cntr <= (others => '0');
elsif(
(pr_state_idle = '1') or ((SPIXfer_done_int = '1') and
(size_length_cntr = "00"))
)then
--if(one_byte_xfer_to_spi_clk = '1' )then
-- size_length_cntr_fixed <= "00";
-- size_length_cntr <= "00"; -- 1 byte
--els
if(two_byte_xfer_to_spi_clk = '1')then
size_length_cntr_fixed <= "01";
size_length_cntr <= "01"; -- half word
elsif(four_byte_xfer_to_spi_clk = '1') then
size_length_cntr_fixed <= "10";
size_length_cntr <= "11"; -- word
else
size_length_cntr_fixed <= "00";
size_length_cntr <= "00"; -- other and one_byte_xfer_to_spi_clk = '1' is merged here
end if;
elsif(SPIXfer_done_int = '1') and
(one_byte_xfer_to_spi_clk = '0')and
(cmd_addr_sent = '1') then -- (size_length_cntr /= "00") then
size_length_cntr <= size_length_cntr - "01";
end if;
end if;
end process SIZE_CNTR_LD_SPI_CLK_P;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
store_date_in_drr_fifo <= not(or_reduce(size_length_cntr)) and
SPIXfer_done_int and
cmd_addr_sent;
-------------------------------------------------------------------------------
STORE_STROBE_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') then
store_date_in_drr_fifo_d1 <= '0';
store_date_in_drr_fifo_d2 <= '0';
store_date_in_drr_fifo_d3 <= '0';
else
store_date_in_drr_fifo_d1 <= store_date_in_drr_fifo;
store_date_in_drr_fifo_d2 <= store_date_in_drr_fifo_d1;
store_date_in_drr_fifo_d3 <= store_date_in_drr_fifo_d2;
end if;
end if;
end process STORE_STROBE_SPI_CLK_P;
-------------------------------------------------------------------------------
MD_12_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
begin
-----
--------------------------------------------------------------------
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate WB_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate NM_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
STORE_DATA_24_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_24_BIT_ADDRESS_GEN;
-------------------------------------------
STORE_DATA_32_BIT_ADDRESS_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
store_date_in_drr_fifo_en <= store_date_in_drr_fifo_d3;
end generate STORE_DATA_32_BIT_ADDRESS_GEN;
-------------------------------------------
end generate SP_FIFO_WR_EN_GEN;
--------------------------------------------------------------------
end generate MD_12_WR_EN_TO_FIFO_GEN;
MD_0_WR_EN_TO_FIFO_GEN: if C_SPI_MODE = 0 generate
begin
-----
WB_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 1 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate WB_FIFO_WR_EN_GEN;
NM_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 2 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate NM_FIFO_WR_EN_GEN;
SP_FIFO_WR_EN_GEN: if C_SPI_MEMORY = 3 generate
begin
-----
store_date_in_drr_fifo_en <= store_date_in_drr_fifo;
end generate SP_FIFO_WR_EN_GEN;
end generate MD_0_WR_EN_TO_FIFO_GEN;
-------------------------------------------------------------------------------
SHIFT_TX_REG_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
elsif(load_wr_hpm = '1') then
Tx_Data_d1(31 downto 24) <= WB_wr_hpm_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk; -- & SPI_cmd;-- (31 downto 8);
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap;--spi_addr_i & SPI_cmd;
elsif(SPIXfer_done_int = '1')then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & "11111111";
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
end generate SHIFT_TX_REG_24_BIT_GEN;
-------------------------------------------------------
SHIFT_TX_REG_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SHIFT_TX_REG_SPI_CLK_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1')then
Tx_Data_d1 <= (others => '0');
--last_7_addr_bits <= (others => '0');
elsif(load_wr_en = '1') then
Tx_Data_d1(31 downto 24) <= "00000110"; ---nm_wr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_wr_hpm = '1')then
Tx_Data_d1(31 downto 24) <= "10110111"; ---nm_4byte_addr_en_CMD;
Tx_Data_d1(23 downto 0) <= (others => '0');
elsif(load_axi_data_to_spi_clk = '1')then
Tx_Data_d1 <= SPI_cmd & Transmit_Addr_to_spi_clk(31 downto 8); -- & SPI_cmd;-- (31 downto 8);
last_7_addr_bits <= Transmit_Addr_to_spi_clk(7 downto 0);
-- internal_count <= (others => '0');
elsif(wrap_around = '1') then
Tx_Data_d1 <= SPI_cmd & spi_addr_wrap(31 downto 8);--spi_addr_i & SPI_cmd;
last_7_addr_bits <= spi_addr_wrap(7 downto 0);
elsif(SPIXfer_done_int = '1') then -- and internal_count < "0101")then
Tx_Data_d1 <= --"11111111" & -- Tx_Data_d1(7 downto 0) &
-- --Tx_Data_d1(31 downto 8);
-- Tx_Data_d1(31 downto 8);
Tx_Data_d1(23 downto 0) & -- Transmit_Addr_to_spi_clk(7 downto 0);
-- spi_addr_wrap(7 downto 0);
last_7_addr_bits(7 downto 0);
-- internal_count <= internal_count + "0001";
--elsif(SPIXfer_done_int = '1' and internal_count = "0101") then
-- Tx_Data_d1 <= (others => '1');
end if;
end if;
end process SHIFT_TX_REG_SPI_CLK_P;
Transmit_Data <= Tx_Data_d1(31 downto 24);
-- STORE_INFO_P:process(EXT_SPI_CLK)is
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
-- if(Rst_to_spi = '1')then
-- data_loaded <= '0';
-- cmd_sent <= '0';
-- elsif(load_axi_data_to_spi_clk = '1' or wrap_around = '1) then
-- data_loaded <= '1';
-- elsif(data_loaded = '1' and SPIXfer_done_int = '1') then
-- cmd_sent <= '1';
-- end if;
-- end if;
-- end process STORE_INFO_P;
end generate SHIFT_TX_REG_32_BIT_GEN;
-------------------------------------------------------
-- Transmit_Data <= Tx_Data_d1(31 downto 24);
-------------------------------------------------------
-------------------------------------------------------------------------------
STD_MODE_CONTROL_GEN: if C_SPI_MODE = 0 generate
-----
begin
-----
WB_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 1 generate
-----------
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_hpm_done <= '1';
load_wr_en <= '0';-- 4/12/2013 applicable only for Numonyx memories
---- Std mode command = 0x0B - Fast Read
SPI_cmd <= "00001011"; -- FAST_READ
-- |<---- cmd error
-- WB 000 000 0100 0<-cmd error
-- NM 000 000 0100 0
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is applicable only for Winbond memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-----------------------------------------
end generate WB_MEM_STD_MD_GEN;
------------------------
--------------------------------------------------------------------------
NM_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg ) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_NM_24_BIT_GEN;
STD_SPI_CMD_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_NM_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_STD_MD_GEN;
------------------------
SP_MEM_STD_MD_GEN: if C_SPI_MODE = 0 and C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
---- Std mode command = 0x0B - Fast Read
STD_SPI_CMD_SP_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "00001011";-- FAST_READ - 0x0Bh
-- |<---- cmd error
-- NM 000 000 0100 0
four_byte_en_done <= '1';
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--case wb_hpm_done is
-- -- when "00"|"01" => -- write enable is under process
-- when '0' => -- write enable and/or Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- when "01" => -- Enable 4 byte addressing is under process
-- -- Data_Dir <= '0';
-- -- Data_Mode_1 <= '0';
-- -- Data_Mode_0 <= '0';
-- -- Data_Phase <= '0';
-- -- --------------------
-- -- Quad_Phase <= '0';-- permanent '0'
-- -- --------------------
-- -- Addr_Mode_1 <= '0';
-- -- Addr_Mode_0 <= '0';
-- -- Addr_Bit <= '0';
-- -- Addr_Phase <= '0';
-- -- --------------------
-- -- CMD_Mode_1 <= '0';
-- -- CMD_Mode_0 <= '0';
-- -- when "10" => -- write enable is done and enable 4 byte addressing is also done
-- when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- -- coverage off
-- when others =>
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- -- coverage on
--end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
end generate STD_SPI_CMD_SP_24_BIT_GEN;
STD_SPI_CMD_SP_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "00001100";-- FAST_READ_4Byte - 0x0Ch
-- |<---- cmd error
-- NM 000 000 0100 0
--end generate STD_SPI_CMD_NM_32_BIT_GEN;
--NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
--begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
SP_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process SP_PS_TO_NS_PROCESS;
----------------------------------
--
SP_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process SP_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
SP_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process SP_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
SP_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process SP_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
---------------------------------------------------------------------
--end generate NM_EN_32_ADDR_MD_GEN;
end generate STD_SPI_CMD_SP_32_BIT_GEN;
---------------------------------------
-- wb_hpm_done <= four_byte_en_done;
--Data_Dir <= '0';
--Data_Mode_1 <= '0';
--Data_Mode_0 <= '0';
--Data_Phase <= '0';
----------------------
--Quad_Phase <= '0';-- permanent '0'
----------------------
--Addr_Mode_1 <= '0';
--Addr_Mode_0 <= '0';
--Addr_Bit <= '0';
--Addr_Phase <= '1';
----------------------
--CMD_Mode_1 <= '0';
--CMD_Mode_0 <= '0';
---------------------------
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int = '1') and (cmd_addr_cntr = "110")then
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-2) downto 0) &
IO1_I ; --MISO_I;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
CMD_ADDR_24_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 5 transactions are of
-- CMD, A0, A1, A2 and dummy. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. Tihs is for 24 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1') then -- and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_24_BIT_CNTR_GEN;
--------------------------------------
CMD_ADDR_32_BIT_CNTR_GEN : if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- * -- -----
-- * -- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- * -- -----
-- * -- begin
-- * -- -----
-- * -- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- * -- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- * -- receive_Data_int <= (others => '0');
-- * -- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1') then -- and (cmd_addr_cntr = "111")then
-- * -- receive_Data_int <= rx_shft_reg_mode_0011;
-- * -- end if;
-- * -- end if;
-- * -- end process RECEIVE_DATA_STROBE_PROCESS;
-- CMD_ADDR_CNTR_P: in each SPI transaction, the first 6 transactions are of
-- CMD, A0, A1, A2, A3 and dummy. Total 6 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 6 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing mode only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (wrap_around = '1') then
cmd_addr_cntr <= "000";
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1' and store_date_in_drr_fifo_d3 = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= wrap_around;
elsif(SPIXfer_done_int = '1' and wb_hpm_done = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_32_BIT_CNTR_GEN;
--------------------------------------
-- TWO_BIT_CNTR_P: This is specifically used for HW data storage
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (wrap_around = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_STD_MD_GEN;
end generate STD_MODE_CONTROL_GEN;
-------------------------------------------------------------------------------
DUAL_MODE_CONTROL_GEN: if C_SPI_MODE = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);-----
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
WB_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 1 generate
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => --load_wr_en_cmd <= '1';
load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
-- WB 0011 000 100 0
-- NM 0011 000 100 0<-cmd error
-- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1'; -- <- '0' for DOFR, '1' for DIOFR
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate WB_MEM_DUAL_MD_GEN;
---------------=============-------------------------------------------
NM_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 2 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "101")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "111")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate NM_MEM_DUAL_MD_GEN;
SP_MEM_DUAL_MD_GEN: if C_SPI_MEMORY = 3 generate
-----
begin
-----
--wb_hpm_done <= '1';
---- Dual mode command = 0x3B - DOFR
--SPI_cmd <= "00111011";
--------------------------------------------------------
DUAL_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
---------------------------
SPI_cmd <= "10111011"; -- 0xBB - DIOFR
wb_hpm_done <= '1';
---------------------------
Data_Dir <= '0';-- for BB
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------
end generate DUAL_SPI_CMD_NM_24_GEN;
------------------------------------
DUAL_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
SPI_cmd <= "10111100"; -- 0xBCh - DIOFR_4Byte
end generate DUAL_SPI_CMD_NM_32_GEN;
------------------------------------
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '1';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '1';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
end generate NM_EN_32_ADDR_MD_GEN;
--------------------------------------
-- -- WB 0011 000 100 0
-- -- NM 0011 000 100 0<-cmd error
-- -- NM 0011 010 100 0<-cmd error -- For 0xbbh DIOFR
-- 0011 011 100 0
-- Data_Dir <= '0';<-- for BB -- '0';<-- for BC
-- Data_Mode_1 <= '0'; -- '0';
-- Data_Mode_0 <= '1'; -- '1';
-- Data_Phase <= '1'; -- '1';
-- -------------------- --
-- Quad_Phase <= '0';-- permanent '0' -- '0';
-- -------------------- --
-- Addr_Mode_1 <= '0'; -- '0';
-- Addr_Mode_0 <= '1'; -- '1';
-- Addr_Bit <= '0'; -- '1';
-- Addr_Phase <= '1'; -- '1';
-- -------------------- --
-- CMD_Mode_1 <= '0'; -- '0'
-- CMD_Mode_0 <= '0'; -- '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-3) downto 0) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "100")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is 4 byte addessing mode of NM memory.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (store_last_b4_wrap = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (store_last_b4_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
----------------------------------------------
STORE_RX_DATA_32_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d3 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_32_BIT_ADDR;
STORE_RX_DATA_24_BIT_ADDR: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
end generate STORE_RX_DATA_24_BIT_ADDR;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
end generate SP_MEM_DUAL_MD_GEN;
end generate DUAL_MODE_CONTROL_GEN;
QUAD_MODE_CONTROL_GEN: if C_SPI_MODE = 2 generate
-----
begin
-----
-- WB 0011 0101 00 0<-cmd error
-- NM 001100101 00 0<-cmd error
WB_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 1 generate
signal cmd_addr_cntr : std_logic_vector(2 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
-----
begin
-----
wb_wr_hpm_CMD <= "10100011"; -- 0xA3 h HPM mode
--
----------------------------------------------------
WB_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
wb_cntrl_ps <= WB_IDLE;
hpm_under_process_d1 <= '0';
else
wb_cntrl_ps <= wb_cntrl_ns;
hpm_under_process_d1 <= hpm_under_process;
end if;
end if;
end process WB_PS_TO_NS_PROCESS;
----------------------------------
--
WB_DUAL_CNTRL_PROCESS: process(
wb_cntrl_ps ,
SPIXfer_done_int_pulse,
SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty
) is
-----
begin
-----
load_wr_en_cmd <= '0';
load_wr_sr_cmd <= '0';
load_wr_sr_d0 <= '0';
load_wr_sr_d1 <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
case wb_cntrl_ps is
when WB_IDLE => load_wr_hpm <= '1';
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
when WB_WR_HPM => if (SR_5_Tx_Empty = '1')then
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
else
hpm_under_process <= '1';
wb_cntrl_ns <= WB_WR_HPM;
end if;
when WB_DONE => if (Rst_to_spi = '1') then
wb_cntrl_ns <= WB_IDLE;
else
wb_hpm_done <= '1';
wb_cntrl_ns <= WB_DONE;
end if;
end case;
end process WB_DUAL_CNTRL_PROCESS;
---- Quad mode command = 0x6B - QOFR Read
-- SPI_cmd <= "01101011";
-- 0101 000 100 0
---- Quad mode command = 0xEB - QIOFR Read
SPI_cmd <= "11101011";
-- 0101 100 100 0 -- QUAD_IO_FAST_RD
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';-- '0' for QOFR and '1' for QIOFR
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
---------------------------------------------------------------------
--RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_WB_GEN;
---------------------------------------------------------------------
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 4 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or (load_axi_data_to_spi_clk = '1') then
cmd_addr_cntr <= "000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
----------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
----------------------------
end generate WB_MEM_QUAD_MD_GEN;
-- NM 0011 0 0101 00 0<-cmd error
NM_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 2 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK, wb_hpm_done, wr_en_done_reg) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1000")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "1001")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate NM_MEM_QUAD_MD_GEN;
--------------------------------
SP_MEM_QUAD_MD_GEN:if C_SPI_MEMORY = 3 generate
signal cmd_addr_cntr : std_logic_vector(3 downto 0);
signal hw_wd_cntr : std_logic_vector(1 downto 0);
begin
-----
--wb_hpm_done <= '1';
---- Quad mode command = 0x6B - QOFR Read - 0xEBh
--SPI_cmd <= -- "01101011";
-- 0101 1 000100 0
QUAD_SPI_CMD_NM_24_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
SPI_cmd <= "11101011"; -- QIOFR
-- 0101 1 100100 0
wb_hpm_done <= '1';
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate QUAD_SPI_CMD_NM_24_GEN;
QUAD_SPI_CMD_NM_32_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
SPI_cmd <= "11101100"; -- QIOFR_4Byte 0xECh
-- 0101 1 100100 0
end generate QUAD_SPI_CMD_NM_32_GEN;
NM_EN_32_ADDR_MD_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
nm_wr_en_CMD <= "00000110"; -- 0x06 h Write Enable
nm_4byte_addr_en_CMD <= "10110111"; -- 0xB7 h Enable 4 Byte Addressing Mode
----------------------------------------------------
NM_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_wr_en_cntrl_ps <= NM_WR_EN_IDLE;
wr_en_under_process_d1 <= '0';
wr_en_done_reg <= '0';
else
nm_wr_en_cntrl_ps <= nm_wr_en_cntrl_ns;
wr_en_under_process_d1 <= wr_en_under_process;
wr_en_done_reg <= wr_en_done;
end if;
end if;
end process NM_PS_TO_NS_PROCESS;
----------------------------------
--
NM_WR_EN_CNTRL_PROCESS: process(
nm_wr_en_cntrl_ps ,
--SPIXfer_done_int_pulse,
--SPIXfer_done_int ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_reg
) is
-----
begin
-----
--load_wr_en_cmd <= '0';
--load_wr_sr_cmd <= '0';
--load_wr_sr_d0 <= '0';
--load_wr_sr_d1 <= '0';
load_wr_en <= '0';
wr_en_done <= '0';
wr_en_under_process <= '0';
case nm_wr_en_cntrl_ps is
when NM_WR_EN_IDLE => --load_wr_en_cmd <= '1';
load_wr_en <= '1';
wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
when NM_WR_EN => if (SR_5_Tx_Empty = '1')then
--wr_en_done <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
else
--wr_en_under_process <= '1';
nm_wr_en_cntrl_ns <= NM_WR_EN;
end if;
wr_en_done <= SR_5_Tx_Empty;
wr_en_under_process <= not SR_5_Tx_Empty;
when NM_WR_EN_DONE => if (Rst_to_spi = '1') then
nm_wr_en_cntrl_ns <= NM_WR_EN_IDLE;
else
nm_wr_en_cntrl_ns <= NM_WR_EN_DONE;
end if;
wr_en_done <= wr_en_done_reg;
end case;
end process NM_WR_EN_CNTRL_PROCESS;
----------------------------------------------------
NM_4_BYTE_PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
nm_sm_4_byte_addr_ps <= NM_32_BIT_IDLE;
--four_byte_addr_under_process_d1 <= '0';
hpm_under_process_d1 <= '0';
wr_en_done_d1 <= '0';
wr_en_done_d2 <= '0';
wb_hpm_done_reg <= '0';
else
nm_sm_4_byte_addr_ps <= nm_sm_4_byte_addr_ns;
hpm_under_process_d1 <= hpm_under_process;
--four_byte_en_done_reg <= four_byte_en_done;
wr_en_done_d1 <= wr_en_done_reg; -- wr_en_done;
wr_en_done_d2 <= wr_en_done_d1;
wb_hpm_done_reg <= wb_hpm_done;
end if;
end if;
end process NM_4_BYTE_PS_TO_NS_PROCESS;
----------------------------------
--
NM_4_BYTE_ADDR_EN_PROCESS: process(
nm_sm_4_byte_addr_ps ,
Rst_to_spi ,
SR_5_Tx_Empty ,
wr_en_done_d2 ,
wb_hpm_done_reg
) is
-----
begin
-----
-- load_4_byte_addr_en <= '0';
load_wr_hpm <= '0';
wb_hpm_done <= '0';
hpm_under_process <= '0';
four_byte_en_done <= '0';
four_byte_en_under_process <= '0';
case nm_sm_4_byte_addr_ps is
when NM_32_BIT_IDLE => if (wr_en_done_d2 = '1') then
--load_wr_hpm <= '1';
--hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
else
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
end if;
load_wr_hpm <= wr_en_done_d2;
hpm_under_process <= wr_en_done_d2;
when NM_32_BIT_EN => if (SR_5_Tx_Empty = '1') then
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
else
-- hpm_under_process <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN;
end if;
wb_hpm_done <= SR_5_Tx_Empty;
hpm_under_process <= not(SR_5_Tx_Empty);
when NM_32_BIT_EN_DONE => if(Rst_to_spi = '1')then
nm_sm_4_byte_addr_ns <= NM_32_BIT_IDLE;
else
-- if (SR_5_Tx_Empty = '1')then
-- --four_byte_en_done <= '1';
-- wb_hpm_done <= '1';
-- else
-- -- four_byte_en_under_process <= '1';
-- hpm_under_process <= '1';
-- end if;
-- four_byte_en_done <= four_byte_en_done_reg;
-- wb_hpm_done <= '1';
nm_sm_4_byte_addr_ns <= NM_32_BIT_EN_DONE;
end if;
wb_hpm_done <= wb_hpm_done_reg;
end case;
end process NM_4_BYTE_ADDR_EN_PROCESS;
--------------------------------------
DRIVE_CONTROL_SIG_P: process(EXT_SPI_CLK) is -- wb_hpm_done, wr_en_done_reg) is
variable temp: std_logic_vector(1 downto 0);
begin
temp := wb_hpm_done & wr_en_done_reg;
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
case wb_hpm_done is
-- when "00"|"01" => -- write enable is under process
when '0' => -- write enable and/or Enable 4 byte addressing is under process
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- when "01" => -- Enable 4 byte addressing is under process
-- Data_Dir <= '0';
-- Data_Mode_1 <= '0';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '0';
-- --------------------
-- Quad_Phase <= '0';-- permanent '0'
-- --------------------
-- Addr_Mode_1 <= '0';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '0';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
-- when "10" => -- write enable is done and enable 4 byte addressing is also done
when '1' => -- write enable and enable 4 byte addressing is also done
Data_Dir <= '0';
Data_Mode_1 <= '1';
Data_Mode_0 <= '0';
Data_Phase <= '1';
--------------------
Quad_Phase <= '1';-- permanent '0'
--------------------
Addr_Mode_1 <= '1';
Addr_Mode_0 <= '0';
Addr_Bit <= '1';
Addr_Phase <= '1';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage off
when others =>
Data_Dir <= '0';
Data_Mode_1 <= '0';
Data_Mode_0 <= '0';
Data_Phase <= '0';
--------------------
Quad_Phase <= '0';-- permanent '0'
--------------------
Addr_Mode_1 <= '0';
Addr_Mode_0 <= '0';
Addr_Bit <= '0';
Addr_Phase <= '0';
--------------------
CMD_Mode_1 <= '0';
CMD_Mode_0 <= '0';
-- coverage on
end case;
end if;
end process DRIVE_CONTROL_SIG_P;
--------------------------------
end generate NM_EN_32_ADDR_MD_GEN;
-------------------------------------
-- Data_Dir <= '0';
-- Data_Mode_1 <= '1';
-- Data_Mode_0 <= '0';
-- Data_Phase <= '1';
-- --------------------
-- Quad_Phase <= '1';-- for NM this is 0
-- --------------------
-- Addr_Mode_1 <= '1';
-- Addr_Mode_0 <= '0';
-- Addr_Bit <= '0';
-- Addr_Phase <= '1';
-- --------------------
-- CMD_Mode_1 <= '0';
-- CMD_Mode_0 <= '0';
---------------------------------------------------------------------
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
--RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
--begin
-----
RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse = '1') then
receive_Data_int <= rx_shft_reg_mode_0011;
elsif(SPIXfer_done_int_pulse_d1 = '1') then
receive_Data_int <= receive_Data_int
((C_NUM_TRANSFER_BITS-5) downto 0) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
--end generate RECEIVE_DATA_NM_GEN;
-----------------------------------------------------------------------------
CMD_ADDR_NM_24_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 5 transactions are of
-- CMD, A0, A1, A2. Total 4 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 4 bytes are transferred.
-- below counter is for that purpose only. This is for 24 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0110")then
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_24_BIT_GEN;
------------------------------------
CMD_ADDR_NM_32_BIT_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-- CMD_ADDR_CNTR_P: in each SPI transaction, the firs 6 transactions are of
-- CMD, A0, A1, A2, A3. Total 5 bytes need to be removed from the
-- calculation of total no. of pure data bytes.
-- the actual data from the SPI memory will be stored in the
-- receive FIFO only when the first 5 bytes are transferred.
-- below counter is for that purpose only. This is for 32 bit addressing of NM memories only.
CMD_ADDR_CNTR_P:process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_to_spi = '1') or
(load_axi_data_to_spi_clk = '1') or
(store_last_b4_wrap = '1') then
cmd_addr_cntr <= "0000";--(others => '1');
cmd_addr_sent <= '0';
elsif(pr_state_idle = '1')then
cmd_addr_cntr <= "0000";
cmd_addr_sent <= store_last_b4_wrap;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(cmd_addr_cntr = "0111")then -- note the differene in counter value
cmd_addr_sent <= '1';
else
cmd_addr_cntr <= cmd_addr_cntr + "0001";
cmd_addr_sent <= '0';
end if;
end if;
end if;
end process CMD_ADDR_CNTR_P;
end generate CMD_ADDR_NM_32_BIT_GEN;
------------------------------------
TWO_BIT_CNTR_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') or (start_after_wrap = '1') then
hw_wd_cntr <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1')then
hw_wd_cntr <= hw_wd_cntr + "01";
end if;
end if;
end process TWO_BIT_CNTR_P;
---------------------------
STORE_RX_DATA_SPI_CLK_P:process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(load_axi_data_to_spi_clk = '1') then
Data_To_Rx_FIFO_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1') and (cmd_addr_sent = '1') then
if(one_byte_xfer_to_spi_clk = '1') then
case spi_addr_i(1 downto 0) is
when "00" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 8) &
receive_Data_int;
when "01" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 16)&
receive_Data_int &
Data_To_Rx_FIFO_int(7 downto 0);
when "10" =>
Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(31 downto 24)&
receive_Data_int &
Data_To_Rx_FIFO_int(15 downto 0);
when "11" =>
Data_To_Rx_FIFO_int <= receive_Data_int &
Data_To_Rx_FIFO_int(23 downto 0);
when others => null;
end case;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '0') then -- adjustment for half word
if(spi_addr_i(1) = '0') then
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);-- & receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= receive_Data_int & Data_To_Rx_FIFO_int(15 downto 8);-- & receive_Data_int;
else
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);-- & receive_Data_int;
Data_To_Rx_FIFO_int(31 downto 16)<= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 24);-- & receive_Data_int;
end if;
elsif (two_byte_xfer_to_spi_clk = '1') and (type_of_burst_to_spi_clk = '1') then -- adjustment for half word
if(hw_wd_cntr = "00") then -- fill in D0
Data_To_Rx_FIFO_int(31 downto 8) <= Data_To_Rx_FIFO_int(31 downto 8);
Data_To_Rx_FIFO_int(7 downto 0) <= receive_Data_int;
elsif(hw_wd_cntr = "01")then -- fill in D1
Data_To_Rx_FIFO_int(31 downto 16) <= Data_To_Rx_FIFO_int(31 downto 16);
Data_To_Rx_FIFO_int(15 downto 8) <= receive_Data_int;
Data_To_Rx_FIFO_int(7 downto 0) <= Data_To_Rx_FIFO_int(7 downto 0);
elsif(hw_wd_cntr = "10")then -- fill in D2
Data_To_Rx_FIFO_int(31 downto 24) <= Data_To_Rx_FIFO_int(31 downto 24);
Data_To_Rx_FIFO_int(23 downto 16) <= receive_Data_int;
Data_To_Rx_FIFO_int(15 downto 0) <= Data_To_Rx_FIFO_int(15 downto 0);
else
Data_To_Rx_FIFO_int(31 downto 24) <= receive_Data_int;
Data_To_Rx_FIFO_int(23 downto 0) <= Data_To_Rx_FIFO_int(23 downto 0);
end if;
else -- adjustment for complete word
--Data_To_Rx_FIFO_int <= Data_To_Rx_FIFO_int(23 downto 0) & receive_Data_int;
Data_To_Rx_FIFO_int <= receive_Data_int & Data_To_Rx_FIFO_int(31 downto 8);
end if;
end if;
end if;
end process STORE_RX_DATA_SPI_CLK_P;
----------------------------
Data_To_Rx_FIFO <= Data_To_Rx_FIFO_int;
---------------------------------------
--------------------------------
end generate SP_MEM_QUAD_MD_GEN;
end generate QUAD_MODE_CONTROL_GEN;
WRAP_DELAY_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
wrap_around_d1 <= '0';
wrap_around_d2 <= '0';
wrap_around_d3 <= '0';
--wrap_around_d4 <= '0';
else
wrap_around_d1 <= wrap_around;
wrap_around_d2 <= wrap_around_d1;
wrap_around_d3 <= wrap_around_d2;
--wrap_around_d4 <= wrap_around_d3;
end if;
end if;
end process WRAP_DELAY_P;
wrap_ack <= (not wrap_around_d2) and wrap_around_d1;
wrap_ack_1 <= (not wrap_around_d3) and wrap_around_d2;
start_after_wrap <= wrap_around_d2 and (not wrap_around_d1) and not SR_5_Tx_Empty;
store_last_b4_wrap <= wrap_around_d3 and (not wrap_around_d2);
--xsfer_start_aftr_wrap <= wrap_around_d4 and (not wrap_around_d3);
DELAY_START_AFTR_WRAP:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
start_after_wrap_d1 <= '0';
else
start_after_wrap_d1 <= start_after_wrap;
end if;
end if;
end process DELAY_START_AFTR_WRAP;
----------------------------------
TRANSFER_START_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1')-- or
--(wr_en_under_process_d1 = '1' and wr_en_done = '1')
then
transfer_start <= '0';
elsif (load_axi_data_to_spi_clk = '1')
or (start_after_wrap_d1 = '1')
or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_24_BIT_ADDR_GEN;
TRANSFER_START_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-----
TRANSFER_START_P:process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
transfer_start <= '0';
elsif(wrap_around = '1') then -- and (actual_SPIXfer_done_int = '1')then
transfer_start <= '0';
elsif(hpm_under_process_d1 = '1' and wb_hpm_done = '1') or
(wr_en_under_process_d1 = '1' and wr_en_done = '1')then
transfer_start <= '0';
elsif(load_axi_data_to_spi_clk = '1') or
(start_after_wrap_d1 = '1') or
(load_wr_hpm = '1') or
(load_wr_en = '1') then
transfer_start <= '1';
elsif(SR_5_Tx_Empty_int = '1') then
transfer_start <= '0';
end if;
end if;
end process TRANSFER_START_P;
end generate TRANSFER_START_32_BIT_ADDR_GEN;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
transfer_start_pulse <= --transfer_start and (not transfer_start_d1);
--transfer_start_d2 and (not transfer_start_d3);
transfer_start and (not(transfer_start_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (load_axi_data_to_spi_clk = '1') then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
-- RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
-- begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SPIXfer_done_int <= '0';
elsif(transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- -- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- -- data register
-- --------------------------------
-- -- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- -- due to the serial input being captured on the falling edge of the PLB
-- -- clock. this is purely required for dealing with the real SPI slave memories.
-- RECEIVE_DATA_NM_GEN: if C_SPI_MEMORY = 2 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') then -- and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_NM_GEN;
-- -----------------------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- RECEIVE_DATA_WB_GEN: if C_SPI_MEMORY = 1 and C_SPI_MODE /=0 generate
-- begin
-- -----
-- RECEIVE_DATA_STROBE_PROCESS: process(EXT_SPI_CLK)
-- -----
-- begin
-- -----
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- if(load_axi_data_to_spi_clk = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
-- receive_Data_int <= (others => '0');
-- elsif(SPIXfer_done_int_pulse_d1 = '1') and (cmd_addr_sent = '1')then
-- receive_Data_int <= rx_shft_reg_mode_0011;
-- end if;
-- end if;
-- end process RECEIVE_DATA_STROBE_PROCESS;
-- end generate RECEIVE_DATA_WB_GEN;
-----------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
---------------attribute IOB : string;
---------------attribute IOB of QSPI_SCK_T : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) or (transfer_start = '0') or (store_last_b4_wrap = '1') then -- (wrap_ack_1 = '1')then
Count <= (others => '0');
elsif(SPIXfer_done_int = '1')then
Count <= (others => '0');
elsif((Count(COUNT_WIDTH) = '0') and
((CPOL_to_spi_clk and CPHA_to_spi_clk) = '0')) then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
SCK_SET_RESET_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm,
load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1') or (load_wr_en = '1')then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm,
load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1') or (load_wr_en = '1') then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_32_BIT_ADDR_GEN;
-------------------------------------------
SCK_SET_RESET_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
begin
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
SPIXfer_done_int,
transfer_start_pulse,--,
load_axi_data_to_spi_clk,
wrap_ack_1,
load_wr_hpm--,
--load_wr_en
) is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1') or (load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Set <= (CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL_to_spi_clk,
CPHA_to_spi_clk,
transfer_start_pulse,
SPIXfer_done_int,
load_axi_data_to_spi_clk,
load_wr_hpm--,
--load_wr_en
)is
-----
begin
-----
if(SPIXfer_done_int = '1')or(load_axi_data_to_spi_clk = '1')or(load_wr_hpm = '1')
--or (load_wr_en = '1')
then
Sync_Reset <= not(CPOL_to_spi_clk xor CPHA_to_spi_clk);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
end generate SCK_SET_RESET_24_BIT_ADDR_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (Sync_Reset = '1') or
(new_tr = '0') or (wrap_ack_1 = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if (Rst_to_spi = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then -- SPIXfer_done_int_pulse_d2
if (Rst_to_spi = RESET_ACTIVE) then -- or (wrap_ack_1 = '1')then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d2='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
QSPI_NM_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 2))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 2
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_NM_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_SP_MEM_DATA_CAP_GEN: if (C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 3))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 3
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= Quad_Phase;--pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_SP_MEM_DATA_CAP_GEN;
----------------------------------
QSPI_WINBOND_MEM_DATA_CAP_GEN: if (
(C_SPI_MODE = 0 and (C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1))
or
(
( C_SPI_MODE = 1
or
C_SPI_MODE = 2
)
and
C_SPI_MEMORY = 1
)) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate QSPI_WINBOND_MEM_DATA_CAP_GEN;
------------------------------------------------------
--------------------------------
XIP_STD_DUAL_MODE_WB_MEM_GEN: if (
(C_SPI_MODE = 0 or C_SPI_MODE = 1) and
(
(C_SPI_MEMORY = 1 or C_SPI_MEMORY = 0)
)
)generate
--------------------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
) or (wrap_ack_1 = '1') then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND =>
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= '1';
if(no_slave_selected = '1') or
(wrap_around = '1')then
qspi_cntrl_ns <= IDLE;
stop_clock <= wrap_ack_1;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_NM_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 2 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
Quad_Phase ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_NM_MEM_GEN;
--------------------------------
--------------------------------------------------
XIP_STD_DUAL_MODE_SP_MEM_GEN: if ((C_SPI_MODE = 1 or C_SPI_MODE = 0) and
(C_SPI_MEMORY = 3 or C_SPI_MEMORY = 0)
)generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(((SR_5_Tx_Empty='1') and
(Data_Phase='0')) or (wrap_ack_1 = '1')
)then
if (no_slave_selected = '1') or (wrap_ack_1 = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1') or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_STD_DUAL_MODE_SP_MEM_GEN;
--------------------------------------------------
XIP_QUAD_MODE_WB_MEM_GEN: if (
C_SPI_MODE = 2 and
C_SPI_MEMORY = 1
)
generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected ,
---------------------
wrap_around ,
transfer_start ,
wrap_ack_1 ,
wb_hpm_done ,
hpm_under_process_d1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
--------------
rst_wrap_around <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(hpm_under_process_d1 = '1')then
qspi_cntrl_ns <= HPM_DUMMY;
elsif(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when HPM_DUMMY => IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
if(SR_5_Tx_Empty='1') then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= HPM_DUMMY;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
if(no_slave_selected = '1')or (wrap_ack_1 = '1')then
stop_clock <= wrap_ack_1;
qspi_cntrl_ns <= IDLE;
else
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate XIP_QUAD_MODE_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
XIP_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 2 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
XIP_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and C_SPI_MEMORY = 3 generate
-------------------
begin
-----
--------------------------------------------------
PS_TO_NS_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
QSPI_CNTRL_PROCESS: process(
---------------------
--CMD_decoded ,
new_tr,
CMD_Mode_1 ,
CMD_Mode_0 ,
--CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps ,
---------------------
wrap_around ,
transfer_start_d1 ,
transfer_start ,
wrap_ack_1
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
-------------
rst_wrap_around <= '0';
-------------
case qspi_cntrl_ps is
when IDLE => if(--(CMD_decoded = '1') and
(SR_5_Tx_Empty = '0') and -- this will be used specially in case of WRAP transactions
(transfer_start = '1')and
(new_tr = '1')
--(CMD_Error = '0') -- proceed only when there is no command error
)then
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
qspi_cntrl_ns <= ADDR_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1') or (wrap_ack_1 = '1')then
rst_wrap_around <= wrap_ack_1;
--if(no_slave_selected = '1') or (wrap_around = '1')then
stop_clock <= wrap_ack_1 or SR_5_Tx_Empty;
qspi_cntrl_ns <= IDLE;
--else
-- stop_clock <= SR_5_Tx_Empty;
-- qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
--end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
--else
-- stop_clock <= '0';
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate XIP_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
--SCK_O <= SCK_O_reg;
--SS_O <= SS_to_spi_clk;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
SS_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty_d1 = '0') and -- Length counter is not exited
(transfer_start = '1') and
(wrap_ack = '0') and -- no wrap around
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
)
else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => EXT_SPI_CLK,
D => SS_tri_state_en_control
);
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (SR_5_Tx_Empty = '0') and -- Length counter is not exited
(transfer_start = '1') and -- 4/14/2013
(wrap_ack = '0') and -- no wrap around-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
--(MODF_strobe_int ='0') -- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => EXT_SPI_CLK,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault -- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => EXT_SPI_CLK,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
--(MODF_strobe_int = '0')-- no mode fault-- 9/7/2013
(SPISEL_sync = '1') -- 9/7/2013
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => EXT_SPI_CLK,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => EXT_SPI_CLK,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(EXT_SPI_CLK)
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if((Rst_to_spi = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif(
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
SS_O_24_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 24 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (SR_5_Tx_Empty ='1') then
SS_O <= (others => '1');
elsif(hpm_under_process_d1 = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_24_BIT_ADDR_GEN;
----------------------------------
SS_O_32_BIT_ADDR_GEN: if C_SPI_MEM_ADDR_BITS = 32 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
if(Rst_to_spi = RESET_ACTIVE) then
SS_O <= (others => '1');
elsif(wrap_ack_1 = '1') or (store_last_b4_wrap = '1') or (transfer_start = '0' and SR_5_Tx_Empty_d1='1') then
SS_O <= (others => '1');
elsif(hpm_under_process = '1') or (wr_en_under_process = '1') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= (SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
elsif(store_last_b4_wrap = '0') then
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= not(SS_to_spi_clk(C_NUM_SS_BITS-1-i));
end loop;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
end generate SS_O_32_BIT_ADDR_GEN;
----------------------------------
no_slave_selected <= and_reduce(SS_to_spi_clk((C_NUM_SS_BITS-1) downto 0));
-------------------------------------------------------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL_to_spi_clk ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
--(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= '0'; -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => EXT_SPI_CLK, -- Clock input
CE => '1', -- Clock enable input
R => Rst_to_spi, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL_to_spi_clk ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') -- and
--(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL_to_spi_clk;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(EXT_SPI_CLK)
-----
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Rst_to_spi = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0')-- or -- dont allow sck to go out when
--(Mst_N_Slv = '0')
)then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
--end generate RATIO_NOT_EQUAL_4_GENERATE;
end generate RATIO_OF_2_GENERATE;
end architecture imp;
-------------------------------------------------------------------------------
|
bsd-3-clause
|
270338c36aa43420b69402170e0850de
| 0.350847 | 4.464605 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/sim/mig_wrap_proc_sys_reset_0_0.vhd
| 1 | 5,866 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY mig_wrap_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_0_0;
ARCHITECTURE mig_wrap_proc_sys_reset_0_0_arch OF mig_wrap_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "virtex7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_0_0_arch;
|
mit
|
f1813913e11305914529fa0bbc4e2c3a
| 0.706444 | 3.57465 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_register_s2mm.vhd
| 4 | 174,357 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register_s2mm.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register_s2mm is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
tdest_in : in std_logic_vector (5 downto 0) ;
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc1_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc2_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc3_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc4_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc5_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc6_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc7_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc8_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc9_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc10_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc11_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc12_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc13_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc14_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc15_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register_s2mm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant SGCTL_INDEX : integer := 0;
constant DMACR_INDEX : integer := 1; -- DMACR Register index
constant DMASR_INDEX : integer := 2; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index
constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index
constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index
constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index
constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index
constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index
constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index
constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index
constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index
constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index
constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index
constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index
constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index
constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index
constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index
constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index
constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index
constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index
constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index
constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index
constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index
constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index
constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index
constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index
constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index
constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index
constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index
constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index
constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index
constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index
constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index
constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index
constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index
constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index
constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index
constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index
constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index
constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index
constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index
constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index
constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index
constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index
constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index
constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index
constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index
constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index
constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index
constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index
constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index
constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index
constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index
constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index
constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index
constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index
constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index
constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index
constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index
constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index
constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index
constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index
constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 7;
constant BUFF_ADDRESS_MSB_INDEX : integer := 8;
constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_64_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc1_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc2_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc3_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc4_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc5_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc6_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc7_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc8_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc9_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc10_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc11_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc12_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc13_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc14_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc15_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal update_curdesc1 : std_logic := '0';
signal update_curdesc2 : std_logic := '0';
signal update_curdesc3 : std_logic := '0';
signal update_curdesc4 : std_logic := '0';
signal update_curdesc5 : std_logic := '0';
signal update_curdesc6 : std_logic := '0';
signal update_curdesc7 : std_logic := '0';
signal update_curdesc8 : std_logic := '0';
signal update_curdesc9 : std_logic := '0';
signal update_curdesc10 : std_logic := '0';
signal update_curdesc11 : std_logic := '0';
signal update_curdesc12 : std_logic := '0';
signal update_curdesc13 : std_logic := '0';
signal update_curdesc14 : std_logic := '0';
signal update_curdesc15 : std_logic := '0';
signal dest0 : std_logic := '0';
signal dest1 : std_logic := '0';
signal dest2 : std_logic := '0';
signal dest3 : std_logic := '0';
signal dest4 : std_logic := '0';
signal dest5 : std_logic := '0';
signal dest6 : std_logic := '0';
signal dest7 : std_logic := '0';
signal dest8 : std_logic := '0';
signal dest9 : std_logic := '0';
signal dest10 : std_logic := '0';
signal dest11 : std_logic := '0';
signal dest12 : std_logic := '0';
signal dest13 : std_logic := '0';
signal dest14 : std_logic := '0';
signal dest15 : std_logic := '0';
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal error_pointer_set1 : std_logic := '0';
signal error_pointer_set2 : std_logic := '0';
signal error_pointer_set3 : std_logic := '0';
signal error_pointer_set4 : std_logic := '0';
signal error_pointer_set5 : std_logic := '0';
signal error_pointer_set6 : std_logic := '0';
signal error_pointer_set7 : std_logic := '0';
signal error_pointer_set8 : std_logic := '0';
signal error_pointer_set9 : std_logic := '0';
signal error_pointer_set10 : std_logic := '0';
signal error_pointer_set11 : std_logic := '0';
signal error_pointer_set12 : std_logic := '0';
signal error_pointer_set13 : std_logic := '0';
signal error_pointer_set14 : std_logic := '0';
signal error_pointer_set15 : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal tail_update_lsb : std_logic := '0';
signal tail_update_msb : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal halt_free : std_logic := '0';
signal tmp11 : std_logic := '0';
signal sig_cur_updated : std_logic := '0';
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
halt_free <= '1';
end generate GEN_MULTI_CH;
GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
halt_free <= dmasr_i(DMASR_HALTED_BIT);
end generate GEN_NOMULTI_CH;
GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate
begin
update_curdesc1 <= '0';
update_curdesc2 <= '0';
update_curdesc3 <= '0';
update_curdesc4 <= '0';
update_curdesc5 <= '0';
update_curdesc6 <= '0';
update_curdesc7 <= '0';
update_curdesc8 <= '0';
update_curdesc9 <= '0';
update_curdesc10 <= '0';
update_curdesc11 <= '0';
update_curdesc12 <= '0';
update_curdesc13 <= '0';
update_curdesc14 <= '0';
update_curdesc15 <= '0';
end generate GEN_DESC_UPDATE_FOR_SG;
dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0';
dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0';
dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0';
dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0';
dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0';
dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0';
dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0';
dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0';
dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0';
dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0';
dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0';
dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0';
dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0';
dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0';
dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0';
dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0';
GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate
update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0';
update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0';
update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0';
update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0';
update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0';
update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0';
update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0';
update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0';
update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0';
update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0';
update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0';
update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0';
update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0';
update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0';
update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0';
end generate GEN_DESC_UPDATE_FOR_SG_CH;
GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_64_i & buffer_address_i ;
end generate GEN_DA_ADDR_EQL64;
GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate GEN_DA_ADDR_EQL32;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
buffer_length <= buffer_length_i ;
curdesc1_lsb <= curdesc1_lsb_i ;
curdesc1_msb <= curdesc1_msb_i ;
taildesc1_lsb <= taildesc1_lsb_i ;
taildesc1_msb <= taildesc1_msb_i ;
curdesc2_lsb <= curdesc2_lsb_i ;
curdesc2_msb <= curdesc2_msb_i ;
taildesc2_lsb <= taildesc2_lsb_i ;
taildesc2_msb <= taildesc2_msb_i ;
curdesc3_lsb <= curdesc3_lsb_i ;
curdesc3_msb <= curdesc3_msb_i ;
taildesc3_lsb <= taildesc3_lsb_i ;
taildesc3_msb <= taildesc3_msb_i ;
curdesc4_lsb <= curdesc4_lsb_i ;
curdesc4_msb <= curdesc4_msb_i ;
taildesc4_lsb <= taildesc4_lsb_i ;
taildesc4_msb <= taildesc4_msb_i ;
curdesc5_lsb <= curdesc5_lsb_i ;
curdesc5_msb <= curdesc5_msb_i ;
taildesc5_lsb <= taildesc5_lsb_i ;
taildesc5_msb <= taildesc5_msb_i ;
curdesc6_lsb <= curdesc6_lsb_i ;
curdesc6_msb <= curdesc6_msb_i ;
taildesc6_lsb <= taildesc6_lsb_i ;
taildesc6_msb <= taildesc6_msb_i ;
curdesc7_lsb <= curdesc7_lsb_i ;
curdesc7_msb <= curdesc7_msb_i ;
taildesc7_lsb <= taildesc7_lsb_i ;
taildesc7_msb <= taildesc7_msb_i ;
curdesc8_lsb <= curdesc8_lsb_i ;
curdesc8_msb <= curdesc8_msb_i ;
taildesc8_lsb <= taildesc8_lsb_i ;
taildesc8_msb <= taildesc8_msb_i ;
curdesc9_lsb <= curdesc9_lsb_i ;
curdesc9_msb <= curdesc9_msb_i ;
taildesc9_lsb <= taildesc9_lsb_i ;
taildesc9_msb <= taildesc9_msb_i ;
curdesc10_lsb <= curdesc10_lsb_i ;
curdesc10_msb <= curdesc10_msb_i ;
taildesc10_lsb <= taildesc10_lsb_i ;
taildesc10_msb <= taildesc10_msb_i ;
curdesc11_lsb <= curdesc11_lsb_i ;
curdesc11_msb <= curdesc11_msb_i ;
taildesc11_lsb <= taildesc11_lsb_i ;
taildesc11_msb <= taildesc11_msb_i ;
curdesc12_lsb <= curdesc12_lsb_i ;
curdesc12_msb <= curdesc12_msb_i ;
taildesc12_lsb <= taildesc12_lsb_i ;
taildesc12_msb <= taildesc12_msb_i ;
curdesc13_lsb <= curdesc13_lsb_i ;
curdesc13_msb <= curdesc13_msb_i ;
taildesc13_lsb <= taildesc13_lsb_i ;
taildesc13_msb <= taildesc13_msb_i ;
curdesc14_lsb <= curdesc14_lsb_i ;
curdesc14_msb <= curdesc14_msb_i ;
taildesc14_lsb <= taildesc14_lsb_i ;
taildesc14_msb <= taildesc14_msb_i ;
curdesc15_lsb <= curdesc15_lsb_i ;
curdesc15_msb <= curdesc15_msb_i ;
taildesc15_lsb <= taildesc15_lsb_i ;
taildesc15_msb <= taildesc15_msb_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Key Hole write bit (3)
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest0 = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_lsb_i <= (others => '0');
error_pointer_set1 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set1 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set1 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then
curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set1 <= '0';
end if;
end if;
end if;
end process CURDESC1_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then
taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC1_LSB_REGISTER;
end generate GEN_DESC1_REG_FOR_SG;
GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_lsb_i <= (others => '0');
error_pointer_set2 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set2 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set2 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then
curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set2 <= '0';
end if;
end if;
end if;
end process CURDESC2_LSB_REGISTER;
TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then
taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC2_LSB_REGISTER;
end generate GEN_DESC2_REG_FOR_SG;
GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_lsb_i <= (others => '0');
error_pointer_set3 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set3 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set3 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then
curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set3 <= '0';
end if;
end if;
end if;
end process CURDESC3_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then
taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC3_LSB_REGISTER;
end generate GEN_DESC3_REG_FOR_SG;
GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_lsb_i <= (others => '0');
error_pointer_set4 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set4 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set4 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then
curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set4 <= '0';
end if;
end if;
end if;
end process CURDESC4_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then
taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC4_LSB_REGISTER;
end generate GEN_DESC4_REG_FOR_SG;
GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_lsb_i <= (others => '0');
error_pointer_set5 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set5 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set5 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then
curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set5 <= '0';
end if;
end if;
end if;
end process CURDESC5_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then
taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC5_LSB_REGISTER;
end generate GEN_DESC5_REG_FOR_SG;
GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_lsb_i <= (others => '0');
error_pointer_set6 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set6 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set6 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then
curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set6 <= '0';
end if;
end if;
end if;
end process CURDESC6_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then
taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC6_LSB_REGISTER;
end generate GEN_DESC6_REG_FOR_SG;
GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_lsb_i <= (others => '0');
error_pointer_set7 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set7 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set7 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then
curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set7 <= '0';
end if;
end if;
end if;
end process CURDESC7_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then
taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC7_LSB_REGISTER;
end generate GEN_DESC7_REG_FOR_SG;
GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_lsb_i <= (others => '0');
error_pointer_set8 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set8 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set8 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then
curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set8 <= '0';
end if;
end if;
end if;
end process CURDESC8_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then
taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC8_LSB_REGISTER;
end generate GEN_DESC8_REG_FOR_SG;
GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_lsb_i <= (others => '0');
error_pointer_set9 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set9 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set9 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then
curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set9 <= '0';
end if;
end if;
end if;
end process CURDESC9_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then
taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC9_LSB_REGISTER;
end generate GEN_DESC9_REG_FOR_SG;
GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_lsb_i <= (others => '0');
error_pointer_set10 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set10 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set10 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then
curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set10 <= '0';
end if;
end if;
end if;
end process CURDESC10_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then
taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC10_LSB_REGISTER;
end generate GEN_DESC10_REG_FOR_SG;
GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_lsb_i <= (others => '0');
error_pointer_set11 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set11 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set11 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then
curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set11 <= '0';
end if;
end if;
end if;
end process CURDESC11_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then
taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC11_LSB_REGISTER;
end generate GEN_DESC11_REG_FOR_SG;
GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_lsb_i <= (others => '0');
error_pointer_set12 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set12 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set12 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then
curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set12 <= '0';
end if;
end if;
end if;
end process CURDESC12_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then
taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC12_LSB_REGISTER;
end generate GEN_DESC12_REG_FOR_SG;
GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_lsb_i <= (others => '0');
error_pointer_set13 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set13 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set13 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then
curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set13 <= '0';
end if;
end if;
end if;
end process CURDESC13_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then
taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC13_LSB_REGISTER;
end generate GEN_DESC13_REG_FOR_SG;
GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_lsb_i <= (others => '0');
error_pointer_set14 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set14 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set14 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then
curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set14 <= '0';
end if;
end if;
end if;
end process CURDESC14_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then
taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC14_LSB_REGISTER;
end generate GEN_DESC14_REG_FOR_SG;
GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_lsb_i <= (others => '0');
error_pointer_set15 <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set15 <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set15 <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then
curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set15 <= '0';
end if;
end if;
end if;
end process CURDESC15_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then
taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC15_LSB_REGISTER;
end generate GEN_DESC15_REG_FOR_SG;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
elsif(sg_updt_error = '1' and dest0 = '1')then
curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate
CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc1_msb_i <= (others => '0');
elsif(error_pointer_set1 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then
curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest1 = '1')then
-- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then
curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then
curdesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC1_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc1_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then
taildesc1_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC1_MSB_REGISTER;
end generate GEN_DESC1_MSB_FOR_SG;
GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate
CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc2_msb_i <= (others => '0');
elsif(error_pointer_set2 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then
curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest2 = '1')then
-- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then
curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then
curdesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC2_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc2_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then
taildesc2_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC2_MSB_REGISTER;
end generate GEN_DESC2_MSB_FOR_SG;
GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate
CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc3_msb_i <= (others => '0');
elsif(error_pointer_set3 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then
curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest3 = '1')then
-- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then
curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then
curdesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC3_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc3_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then
taildesc3_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC3_MSB_REGISTER;
end generate GEN_DESC3_MSB_FOR_SG;
GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate
CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc4_msb_i <= (others => '0');
elsif(error_pointer_set4 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then
curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest4 = '1')then
-- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then
curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then
curdesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC4_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc4_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then
taildesc4_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC4_MSB_REGISTER;
end generate GEN_DESC4_MSB_FOR_SG;
GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate
CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc5_msb_i <= (others => '0');
elsif(error_pointer_set5 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then
curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest5 = '1')then
-- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then
curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then
curdesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC5_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc5_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then
taildesc5_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC5_MSB_REGISTER;
end generate GEN_DESC5_MSB_FOR_SG;
GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate
CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc6_msb_i <= (others => '0');
elsif(error_pointer_set6 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then
curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest6 = '1')then
-- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then
curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then
curdesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC6_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc6_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then
taildesc6_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC6_MSB_REGISTER;
end generate GEN_DESC6_MSB_FOR_SG;
GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate
CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc7_msb_i <= (others => '0');
elsif(error_pointer_set7 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then
curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest7 = '1')then
-- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then
curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then
curdesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC7_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc7_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then
taildesc7_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC7_MSB_REGISTER;
end generate GEN_DESC7_MSB_FOR_SG;
GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate
CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc8_msb_i <= (others => '0');
elsif(error_pointer_set8 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then
curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest8 = '1')then
-- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then
curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then
curdesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC8_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc8_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then
taildesc8_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC8_MSB_REGISTER;
end generate GEN_DESC8_MSB_FOR_SG;
GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate
CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc9_msb_i <= (others => '0');
elsif(error_pointer_set9 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then
curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest9 = '1')then
-- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then
curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then
curdesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC9_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc9_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then
taildesc9_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC9_MSB_REGISTER;
end generate GEN_DESC9_MSB_FOR_SG;
GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate
CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc10_msb_i <= (others => '0');
elsif(error_pointer_set10 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then
curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest10 = '1')then
-- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then
curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then
curdesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC10_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc10_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then
taildesc10_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC10_MSB_REGISTER;
end generate GEN_DESC10_MSB_FOR_SG;
GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate
CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc11_msb_i <= (others => '0');
elsif(error_pointer_set11 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then
curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest11 = '1')then
-- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then
curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then
curdesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC11_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc11_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then
taildesc11_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC11_MSB_REGISTER;
end generate GEN_DESC11_MSB_FOR_SG;
GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate
CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc12_msb_i <= (others => '0');
elsif(error_pointer_set12 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then
curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest12 = '1')then
-- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then
curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then
curdesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC12_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc12_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then
taildesc12_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC12_MSB_REGISTER;
end generate GEN_DESC12_MSB_FOR_SG;
GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate
CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc13_msb_i <= (others => '0');
elsif(error_pointer_set13 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then
curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest13 = '1')then
-- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then
curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then
curdesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC13_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc13_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then
taildesc13_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC13_MSB_REGISTER;
end generate GEN_DESC13_MSB_FOR_SG;
GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate
CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc14_msb_i <= (others => '0');
elsif(error_pointer_set14 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then
curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest14 = '1')then
-- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then
curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then
curdesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC14_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc14_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then
taildesc14_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC14_MSB_REGISTER;
end generate GEN_DESC14_MSB_FOR_SG;
GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate
CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc15_msb_i <= (others => '0');
elsif(error_pointer_set15 = '0')then
-- Scatter Gather Fetch Error
if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then
curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1' and dest15 = '1')then
-- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then
curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then
curdesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC15_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc15_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then
taildesc15_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC15_MSB_REGISTER;
end generate GEN_DESC15_MSB_FOR_SG;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to the extra registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15);
end generate GENERATE_MULTI_CH;
GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
-- Added dest so that BD can be dynamically updated
GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or
(axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or
(axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or
(axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or
(axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or
(axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or
(axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or
(axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or
(axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or
(axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or
(axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or
(axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or
(axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or
(axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or
(axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or
(axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15);
end generate GENERATE_NO_MULTI_CH1;
GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate
tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0);
end generate GENERATE_NO_MULTI_CH2;
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif (tail_update_msb = '1' and tdest_in(5) = '0')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
-- Extending this to new registers
curdesc1_msb_i <= (others => '0');
taildesc1_msb_i <= (others => '0');
curdesc2_msb_i <= (others => '0');
taildesc2_msb_i <= (others => '0');
curdesc3_msb_i <= (others => '0');
taildesc3_msb_i <= (others => '0');
curdesc4_msb_i <= (others => '0');
taildesc4_msb_i <= (others => '0');
curdesc5_msb_i <= (others => '0');
taildesc5_msb_i <= (others => '0');
curdesc6_msb_i <= (others => '0');
taildesc6_msb_i <= (others => '0');
curdesc7_msb_i <= (others => '0');
taildesc7_msb_i <= (others => '0');
curdesc8_msb_i <= (others => '0');
taildesc8_msb_i <= (others => '0');
curdesc9_msb_i <= (others => '0');
taildesc9_msb_i <= (others => '0');
curdesc10_msb_i <= (others => '0');
taildesc10_msb_i <= (others => '0');
curdesc11_msb_i <= (others => '0');
taildesc11_msb_i <= (others => '0');
curdesc12_msb_i <= (others => '0');
taildesc12_msb_i <= (others => '0');
curdesc13_msb_i <= (others => '0');
taildesc13_msb_i <= (others => '0');
curdesc14_msb_i <= (others => '0');
taildesc14_msb_i <= (others => '0');
curdesc15_msb_i <= (others => '0');
taildesc15_msb_i <= (others => '0');
curdesc1_lsb_i <= (others => '0');
taildesc1_lsb_i <= (others => '0');
curdesc2_lsb_i <= (others => '0');
taildesc2_lsb_i <= (others => '0');
curdesc3_lsb_i <= (others => '0');
taildesc3_lsb_i <= (others => '0');
curdesc4_lsb_i <= (others => '0');
taildesc4_lsb_i <= (others => '0');
curdesc5_lsb_i <= (others => '0');
taildesc5_lsb_i <= (others => '0');
curdesc6_lsb_i <= (others => '0');
taildesc6_lsb_i <= (others => '0');
curdesc7_lsb_i <= (others => '0');
taildesc7_lsb_i <= (others => '0');
curdesc8_lsb_i <= (others => '0');
taildesc8_lsb_i <= (others => '0');
curdesc9_lsb_i <= (others => '0');
taildesc9_lsb_i <= (others => '0');
curdesc10_lsb_i <= (others => '0');
taildesc10_lsb_i <= (others => '0');
curdesc11_lsb_i <= (others => '0');
taildesc11_lsb_i <= (others => '0');
curdesc12_lsb_i <= (others => '0');
taildesc12_lsb_i <= (others => '0');
curdesc13_lsb_i <= (others => '0');
taildesc13_lsb_i <= (others => '0');
curdesc14_lsb_i <= (others => '0');
taildesc14_lsb_i <= (others => '0');
curdesc15_lsb_i <= (others => '0');
taildesc15_lsb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_64_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_64_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then
buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
|
bsd-3-clause
|
5f24a6e8f88903c155f0336e02cf3f3c
| 0.445316 | 4.182627 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_sim_netlist.vhdl
| 1 | 32,517 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 24 22:16:07 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/Nexys4/rtl_project/rtl_project.srcs/sources_1/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_cdc_sync : entity is "cdc_sync";
end mig_wrap_proc_sys_reset_0_0_cdc_sync;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_cdc_sync_0 : entity is "cdc_sync";
end mig_wrap_proc_sys_reset_0_0_cdc_sync_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_upcnt_n : entity is "upcnt_n";
end mig_wrap_proc_sys_reset_0_0_upcnt_n;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_lpf : entity is "lpf";
end mig_wrap_proc_sys_reset_0_0_lpf;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.mig_wrap_proc_sys_reset_0_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.mig_wrap_proc_sys_reset_0_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_sequence_psr : entity is "sequence_psr";
end mig_wrap_proc_sys_reset_0_0_sequence_psr;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.mig_wrap_proc_sys_reset_0_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "proc_sys_reset";
end mig_wrap_proc_sys_reset_0_0_proc_sys_reset;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.mig_wrap_proc_sys_reset_0_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.mig_wrap_proc_sys_reset_0_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mig_wrap_proc_sys_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mig_wrap_proc_sys_reset_0_0 : entity is "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mig_wrap_proc_sys_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mig_wrap_proc_sys_reset_0_0 : entity is "proc_sys_reset,Vivado 2016.4";
end mig_wrap_proc_sys_reset_0_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.mig_wrap_proc_sys_reset_0_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
mit
|
e3fc5d00ed23bfdd000efb9e92c649cf
| 0.573546 | 2.85713 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/synth/mig_wrap_proc_sys_reset_0_0.vhd
| 1 | 6,620 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mig_wrap_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_0_0;
ARCHITECTURE mig_wrap_proc_sys_reset_0_0_arch OF mig_wrap_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mig_wrap_proc_sys_reset_0_0_arch : ARCHITECTURE IS "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_0_0_arch;
|
mit
|
3782fad2126fe1efcd40717bcd27f96f
| 0.712991 | 3.462343 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm.vhd
| 4 | 17,023 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
entity axi_dma_s2mm is
generic (
C_FAMILY : string := "virtex7"
);
port (
clk_in : in std_logic;
sg_clk : in std_logic;
resetn : in std_logic;
reset_sg : in std_logic;
s2mm_tvalid : in std_logic;
s2mm_tlast : in std_logic;
s2mm_tdest : in std_logic_vector (4 downto 0);
s2mm_tuser : in std_logic_vector (3 downto 0);
s2mm_tid : in std_logic_vector (4 downto 0);
s2mm_tready : in std_logic;
desc_available : in std_logic;
-- s2mm_eof : in std_logic;
s2mm_eof_det : in std_logic_vector (1 downto 0);
ch2_update_active : in std_logic;
tdest_out : out std_logic_vector (6 downto 0); -- to select desc
same_tdest : out std_logic; -- to select desc
-- to DM
s2mm_desc_info : out std_logic_vector (13 downto 0);
-- updt_cmpt : out std_logic;
s2mm_tvalid_out : out std_logic;
s2mm_tlast_out : out std_logic;
s2mm_tready_out : out std_logic;
s2mm_tdest_out : out std_logic_vector (4 downto 0)
);
end entity axi_dma_s2mm;
architecture implementation of axi_dma_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
signal first_data : std_logic;
signal first_stream : std_logic;
signal first_stream_del : std_logic;
signal last_received : std_logic;
signal first_received : std_logic;
signal first_received1 : std_logic;
signal open_window : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal fifo_wr : std_logic;
signal last_update_over_int : std_logic;
signal last_update_over_int1 : std_logic;
signal last_update_over : std_logic;
signal ch_updt_over_int : std_logic;
signal ch_updt_over_int_cdc_from : std_logic;
signal ch_updt_over_int_cdc_to : std_logic;
signal ch_updt_over_int_cdc_to1 : std_logic;
signal ch_updt_over_int_cdc_to2 : std_logic;
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
--ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to1 : SIGNAL IS "true";
signal fifo_rd : std_logic;
signal first_read : std_logic;
signal first_rd_en : std_logic;
signal fifo_rd_int : std_logic;
signal first_read_int : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal s2mm_desc_info_int : std_logic_vector (13 downto 0);
signal updt_cmpt : std_logic;
signal tdest_capture : std_logic_vector (4 downto 0);
signal noread : std_logic;
signal same_tdest_b2b : std_logic;
signal fifo_reset : std_logic;
begin
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
ch_updt_over_int_cdc_from <= '0';
else --if (sg_clk'event and sg_clk = '1') then
ch_updt_over_int_cdc_from <= ch2_update_active;
end if;
end if;
end process;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
ch_updt_over_int_cdc_to <= '0';
ch_updt_over_int_cdc_to1 <= '0';
ch_updt_over_int_cdc_to2 <= '0';
else --if (clk_in'event and clk_in = '1') then
ch_updt_over_int_cdc_to <= ch_updt_over_int_cdc_from;
ch_updt_over_int_cdc_to1 <= ch_updt_over_int_cdc_to;
ch_updt_over_int_cdc_to2 <= ch_updt_over_int_cdc_to1;
end if;
end if;
end process;
updt_cmpt <= (not ch_updt_over_int_cdc_to1) and ch_updt_over_int_cdc_to2;
-- process (sg_clk)
-- begin
-- if (resetn = '0') then
-- ch_updt_over_int <= '0';
-- elsif (sg_clk'event and sg_clk = '1') then
-- ch_updt_over_int <= ch2_update_active;
-- end if;
-- end process;
-- updt_cmpt <= (not ch2_update_active) and ch_updt_over_int;
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
last_update_over_int <= '0';
last_update_over_int1 <= '0';
noread <= '0';
-- else --if (sg_clk'event and sg_clk = '1') then
last_update_over_int1 <= last_update_over_int;
elsif (s2mm_eof_det(1) = '1' and noread = '0') then
last_update_over_int <= '1';
noread <= '1';
elsif (s2mm_eof_det(0) = '1') then
noread <= '0';
last_update_over_int <= '0';
elsif (fifo_empty = '0') then -- (updt_cmpt = '1') then
last_update_over_int <= '0';
else
last_update_over_int <= last_update_over_int;
end if;
end if;
-- end if;
end process;
last_update_over <= (not last_update_over_int) and last_update_over_int1;
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
fifo_rd_int <= '0';
first_read <= '0';
-- else --if (sg_clk'event and sg_clk = '1') then
elsif (last_update_over_int = '1' and fifo_rd_int = '0') then
fifo_rd_int <= '1';
else
fifo_rd_int <= '0';
end if;
end if;
end process;
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
first_read_int <= '0';
else --if (sg_clk'event and sg_clk = '1') then
first_read_int <= first_read;
end if;
end if;
end process;
first_rd_en <= first_read and (not first_read_int);
fifo_rd <= last_update_over_int; --(fifo_rd_int or first_rd_en);
-- process (clk_in)
-- begin
-- if (resetn = '0') then
-- first_data <= '0';
-- first_stream_del <= '0';
-- elsif (clk_in'event and clk_in = '1') then
-- if (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- no tlast
-- first_data <= '1'; -- just after the system comes out of reset
-- end if;
-- first_stream_del <= first_stream;
-- end if;
-- end process;
first_stream <= (s2mm_tvalid and (not first_data)); -- pulse when first stream comes after reset
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
first_received1 <= '0';
first_stream_del <= '0';
else --if (clk_in'event and clk_in = '1') then
first_received1 <= first_received; --'0';
first_stream_del <= first_stream;
end if;
end if;
end process;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
last_received <= '0';
first_received <= '0';
tdest_capture <= (others => '0');
first_data <= '0';
-- else --if (clk_in'event and clk_in = '1') then
elsif (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- first stream afetr reset
s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest;
tdest_capture <= s2mm_tdest; -- latching tdest on first beat
first_data <= '1'; -- just after the system comes out of reset
elsif (s2mm_tlast = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for last beat
last_received <= '1';
first_received <= '0';
s2mm_desc_info_int <= s2mm_desc_info_int;
elsif (last_received = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for following first beat
last_received <= '0';
first_received <= '1';
tdest_capture <= s2mm_tdest; -- latching tdest on first beat
s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest;
else
s2mm_desc_info_int <= s2mm_desc_info_int;
last_received <= last_received;
if (updt_cmpt = '1') then
first_received <= '0';
else
first_received <= first_received; -- hold the first received until update comes for previous tlast
end if;
end if;
end if;
end process;
fifo_wr <= first_stream_del or (first_received and not (first_received1)); -- writing the tdest,tuser,tid into FIFO
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
tdest_out_int <= "0100000";
same_tdest_b2b <= '0';
-- else --if (clk_in'event and clk_in = '1') then
elsif (first_received = '1' or first_stream = '1') then
if (first_stream = '1') then -- when first stream is received, capture the tdest
tdest_out_int (6) <= not tdest_out_int (6); -- signifies a new stream has come
tdest_out_int (5 downto 0) <= '0' & s2mm_tdest;
same_tdest_b2b <= '0';
-- elsif (updt_cmpt = '1' or (first_received = '1' and first_received1 = '0')) then -- when subsequent streams are received, pass the latched value of tdest
-- elsif (first_received = '1' and first_received1 = '0') then -- when subsequent streams are received, pass the latched value of tdest
-- Following change made to allow b2b same channel pkt
elsif ((first_received = '1' and first_received1 = '0') and (tdest_out_int (4 downto 0) /= tdest_capture)) then -- when subsequent streams are received, pass the latched value of tdest
tdest_out_int (6) <= not tdest_out_int (6);
tdest_out_int (5 downto 0) <= '0' & tdest_capture; --s2mm_tdest;
elsif (first_received = '1' and first_received1 = '0') then
same_tdest_b2b <= not (same_tdest_b2b);
end if;
else
tdest_out_int <= tdest_out_int;
end if;
end if;
end process;
tdest_out <= tdest_out_int;
same_tdest <= same_tdest_b2b;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
open_window <= '0';
-- else --if (clk_in'event and clk_in = '1') then
elsif (desc_available = '1') then
open_window <= '1';
elsif (s2mm_tlast = '1') then
open_window <= '0';
else
open_window <= open_window;
end if;
end if;
end process;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
s2mm_tvalid_out <= '0';
s2mm_tready_out <= '0';
s2mm_tlast_out <= '0';
s2mm_tdest_out <= "00000";
-- else --if (clk_in'event and clk_in = '1') then
elsif (open_window = '1') then
s2mm_tvalid_out <= s2mm_tvalid;
s2mm_tready_out <= s2mm_tready;
s2mm_tlast_out <= s2mm_tlast;
s2mm_tdest_out <= s2mm_tdest;
else
s2mm_tready_out <= '0';
s2mm_tvalid_out <= '0';
s2mm_tlast_out <= '0';
s2mm_tdest_out <= "00000";
end if;
end if;
end process;
fifo_reset <= not (resetn);
-- s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest;
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => 14,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => 31,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 5,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 5,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => s2mm_desc_info_int,
Wr_en => fifo_wr,
Wr_clk => clk_in,
Rd_en => fifo_rd,
Rd_clk => sg_clk,
Ainit => fifo_reset,
Dout => s2mm_desc_info,
Full => fifo_Full,
Empty => fifo_empty,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => open,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
end implementation;
|
bsd-3-clause
|
5e64308de34cc7cf2ed310ae578ec984
| 0.515597 | 3.577012 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_core_interface.vhd
| 2 | 167,628 |
-------------------------------------------------------------------------------
-- qspi_core_interface Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_core_interface.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
-- use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library interrupt_control_v3_1_4;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
-------------------------------------------------------------------------------
entity qspi_core_interface is
generic(
C_FAMILY : string;
C_SUB_FAMILY : string;
C_SELECT_XPM : integer := 1;
C_UC_FAMILY : integer;
C_S_AXI_DATA_WIDTH : integer;
Async_Clk : integer;
----------------------
-- local parameters
C_NUM_CE_SIGNALS : integer;
----------------------
-- SPI parameters
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_FIFO_DEPTH : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SHARED_STARTUP : integer range 0 to 1 := 0;
C_TYPE_OF_AXI4_INTERFACE : integer;
----------------------
-- local constants
C_FIFO_EXIST : integer;
C_SPI_NUM_BITS_REG : integer;
C_OCCUPANCY_NUM_BITS : integer;
----------------------
-- local constants
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
----------------------
-- local constants
C_SPICR_REG_WIDTH : integer;
C_SPISR_REG_WIDTH : integer;
C_LSB_STUP : integer
);
port(
EXT_SPI_CLK : in std_logic;
------------------------------------------------
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
------------------------------------------------
Bus2IP_BE : in std_logic_vector(0 to ((C_S_AXI_DATA_WIDTH/8)-1));
Bus2IP_RdCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_WrCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------------------------------
IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
------------------------------------------------
burst_tr : in std_logic;
rready : in std_logic;
WVALID : in std_logic;
--SPI Ports
SCK_I : in std_logic;
SCK_O : out std_logic;
SCK_T : out std_logic;
------------------------------------------------
IO0_I : in std_logic;
IO0_O : out std_logic;
IO0_T : out std_logic;
------------------------------------------------
IO1_I : in std_logic;
IO1_O : out std_logic;
IO1_T : out std_logic;
------------------------------------------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
------------------------------------------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
------------------------------------------------
SPISEL : in std_logic;
------------------------------------------------
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
SS_T : out std_logic;
------------------------------------------------
IP2INTC_Irpt : out std_logic;
------------------------------------------------
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
di : out std_logic_vector(1 downto 0); -- output
dts : in std_logic_vector(1 downto 0); -- input
do : in std_logic_vector(1 downto 0); -- input
-- fcsbo : in std_logic; -- input
-- fcsbts : in std_logic; -- input
clk : in std_logic; -- input
gsr : in std_logic; -- input
gts : in std_logic; -- input
keyclearb : in std_logic; -- input
pack : in std_logic; -- input
usrcclkts : in std_logic; -- input
usrdoneo : in std_logic; -- input
usrdonets : in std_logic -- input
);
end entity qspi_core_interface;
-------------------------------------------------------------------------------
------------
architecture imp of qspi_core_interface is
------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- function definition
----------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- constant definition
constant NEW_LOGIC : integer := 0;
-- These constants are indices into the "CE" arrays for the various registers.
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant SWRESET : natural := 16; -- at address C_BASEADDR + 40 h
constant SPICR : natural := 24; -- 17; -- at address C_BASEADDR + 60 h
constant SPISR : natural := 25; -- 18;
constant SPIDTR : natural := 26; -- 19;
constant SPIDRR : natural := 27; -- 20;
constant SPISSR : natural := 28; -- 21;
constant SPITFOR : natural := 29; -- 22;
constant SPIRFOR : natural := 30; -- 23; -- at address C_BASEADDR + 78 h
constant REG_HOLE : natural := 31; -- 24; -- at address C_BASEADDR + 7C h
--Startup Signals
signal str_IO0_I : std_logic;
signal str_IO0_O : std_logic;
signal str_IO0_T : std_logic;
signal str_IO1_I : std_logic;
signal str_IO1_O : std_logic;
signal str_IO1_T : std_logic;
signal di_int : std_logic_vector(3 downto 0); -- output
signal di_int_sync : std_logic_vector(3 downto 0); -- output
signal dts_int : std_logic_vector(3 downto 0); -- input
signal do_int : std_logic_vector(3 downto 0); -- input
--SPI MODULE SIGNALS
signal spiXfer_done_int : std_logic;
signal dtr_underrun_int : std_logic;
signal modf_strobe_int : std_logic;
signal slave_MODF_strobe_int : std_logic;
--OR REGISTER/FIFO SIGNALS
--TO/FROM REG/FIFO DATA
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Extra bit required for signal Register_Data_ctrl
signal register_Data_cntrl_int :std_logic_vector(0 to (C_SPI_NUM_BITS_REG+1));
signal register_Data_slvsel_int:std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_SPICR_Data_int :std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal IP2Bus_SPISR_Data_int :std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal IP2Bus_Receive_Reg_Data_int :std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal IP2Bus_Data_received_int:
std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal IP2Bus_SPISSR_Data_int : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
--STATUS REGISTER SIGNALS
signal sr_3_MODF_int : std_logic;
signal Tx_FIFO_Full_int : std_logic;
signal sr_5_Tx_Empty_int : std_logic;
signal tx_empty_signal_handshake_req : std_logic;
signal tx_empty_signal_handshake_gnt : std_logic;
signal sr_6_Rx_Full_int : std_logic;
signal Rc_FIFO_Empty_int : std_logic;
--RECEIVE AND TRANSMIT REGISTER SIGNALS
signal drr_Overrun_int : std_logic;
signal dtr_Underrun_strobe_int : std_logic;
--FIFO SIGNALS
signal rc_FIFO_Full_strobe_int : std_logic;
signal rc_FIFO_occ_Reversed_int :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_occ_Reversed_int_2 :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_Data_Out_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_6_Rx_Full_int_1 : std_logic;
signal FIFO_Empty_rx_1 : std_logic;
signal FIFO_Empty_rx : std_logic;
signal data_Exists_RcFIFO_int : std_logic;
signal tx_FIFO_Empty_strobe_int : std_logic;
signal tx_FIFO_occ_Reversed_int : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal tx_FIFO_occ_Reversed_int_2 : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal data_Exists_TxFIFO_int : std_logic;
signal data_Exists_TxFIFO_int_1 : std_logic;
signal data_From_TxFIFO_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_FIFO_less_half_int : std_logic;
signal Tx_FIFO_Full_int_1 : std_logic;
signal FIFO_Empty_tx : std_logic;
signal data_From_TxFIFO_int_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_occ_msb : std_logic;
signal tx_occ_msb_1 : std_logic:= '0';
signal tx_occ_msb_2 : std_logic;
signal tx_occ_msb_3 : std_logic;
signal tx_occ_msb_4 : std_logic;
signal reset_TxFIFO_ptr_int : std_logic;
signal reset_TxFIFO_ptr_int_to_spi : std_logic;
signal reset_RcFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal ip2Bus_Data_Reg_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_occupancy_int: std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_SS_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
-- interface between signals on instance basis
signal bus2IP_Reset_int : std_logic;
signal bus2IP_Data_for_interrupt_core : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2Bus_Error_int : std_logic;
signal ip2Bus_WrAck_int : std_logic;-- := '0';
signal ip2Bus_RdAck_int : std_logic;-- := '0';
signal ip2Bus_IntrEvent_int : std_logic_vector
(0 to (C_IP_INTR_MODE_ARRAY'length-1));
signal transmit_ip2bus_error : std_logic;
signal receive_ip2bus_error : std_logic;
-- SOFT RESET SIGNALS
signal reset2ip_reset_int : std_logic;
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
-- INTERRUPT SIGNALS
signal intr_ip2bus_data : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_error : std_logic;
signal ip2bus_error_RdWr : std_logic;
--
signal wr_ce_reduce_ack_gen: std_logic;
--
signal rd_ce_reduce_ack_gen : std_logic;
--
signal control_bit_7_8_int : std_logic_vector(0 to 1);
signal spisel_pulse_o_int : std_logic;
signal Interrupt_WrCE_sig : std_logic_vector(0 to 1);
signal IPIF_Lvl_Interrupts_sig : std_logic;
signal spisel_d1_reg : std_logic;
signal Mst_N_Slv_mode : std_logic;
-----
signal bus2ip_intr_rdce : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_intr_wrce : std_logic_vector(INTR_LO to INTR_HI);
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal intr_controller_rd_ce_or_reduce : std_logic;
signal intr_controller_wr_ce_or_reduce : std_logic;
signal wr_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_WrAck_core_reg_d1 : std_logic;
signal ip2Bus_WrAck_core_reg : std_logic;
signal rd_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_RdAck_core_reg_d1 : std_logic;
signal ip2Bus_RdAck_core_reg : std_logic;
signal SPISR_0_CMD_Error_int : std_logic;
signal SPISR_1_LOOP_Back_Error_int : std_logic;
signal SPISR_2_MSB_Error_int : std_logic;
signal SPISR_3_Slave_Mode_Error_int : std_logic;
signal SPISR_4_CPOL_CPHA_Error_int : std_logic;
signal SPISR_Ext_SPISEL_slave_int : std_logic;
signal SPICR_5_TXFIFO_RST_int : std_logic;
-- signal SPICR_6_RXFIFO_RST_int : std_logic;
signal pr_state_idle_int : std_logic;
signal Quad_Phase_int : std_logic;
signal SPICR_0_LOOP_frm_axi :std_logic;
signal SPICR_0_LOOP_to_spi :std_logic;
signal SPICR_1_SPE_frm_axi :std_logic;
signal SPICR_1_SPE_to_spi :std_logic;
signal SPICR_2_MST_N_SLV_frm_axi :std_logic;
signal SPICR_2_MST_N_SLV_to_spi :std_logic;
signal SPICR_3_CPOL_frm_axi :std_logic;
signal SPICR_3_CPOL_to_spi :std_logic;
signal SPICR_4_CPHA_frm_axi :std_logic;
signal SPICR_4_CPHA_to_spi :std_logic;
signal SPICR_5_TXFIFO_frm_axi :std_logic;
signal SPICR_5_TXFIFO_to_spi :std_logic;
--signal SPICR_6_RXFIFO_RST_frm_axi:std_logic;
--signal SPICR_6_RXFIFO_RST_to_spi :std_logic;
signal SPICR_7_SS_frm_axi :std_logic;
signal SPICR_7_SS_to_spi :std_logic;
signal SPICR_8_TR_INHIBIT_frm_axi:std_logic;
signal SPICR_8_TR_INHIBIT_to_spi :std_logic;
signal SPICR_9_LSB_frm_axi :std_logic;
signal SPICR_9_LSB_to_spi :std_logic;
signal SPICR_bits_7_8_frm_spi :std_logic;
signal SPICR_bits_7_8_to_axi :std_logic;
signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : std_logic;
signal rx_fifo_full_to_spi_clk : std_logic;
signal tx_fifo_empty_to_axi_clk : std_logic;
signal tx_fifo_full : std_logic;
signal spisel_d1_reg_to_axi_clk : std_logic;
signal spicr_bits_7_8_frm_axi_clk : std_logic_vector(1 downto 0);
signal spicr_8_tr_inhibit_to_spi_clk : std_logic;
signal spicr_9_lsb_to_spi_clk : std_logic;
signal spicr_bits_7_8_to_spi_clk : std_logic_vector(0 to 1);
signal spicr_0_loop_frm_axi_clk : std_logic;
signal spicr_1_spe_frm_axi_clk : std_logic;
signal spicr_2_mst_n_slv_frm_axi_clk : std_logic;
signal spicr_3_cpol_frm_axi_clk : std_logic;
signal spicr_4_cpha_frm_axi_clk : std_logic;
signal spicr_5_txfifo_rst_frm_axi_clk : std_logic;
signal spicr_6_rxfifo_rst_frm_axi_clk : std_logic;
signal spicr_7_ss_frm_axi_clk : std_logic;
signal spicr_8_tr_inhibit_frm_axi_clk : std_logic;
signal spicr_9_lsb_frm_axi_clk : std_logic;
signal Tx_FIFO_wr_ack_1 : std_logic;
signal rst_to_spi_int : std_logic;
signal spicr_0_loop_to_spi_clk : std_logic;
signal spicr_1_spe_to_spi_clk : std_logic;
signal spicr_2_mas_n_slv_to_spi_clk : std_logic;
signal spicr_3_cpol_to_spi_clk : std_logic;
signal spicr_4_cpha_to_spi_clk : std_logic;
signal spicr_5_txfifo_rst_to_spi_clk : std_logic;
signal spicr_6_rxfifo_rst_to_spi_clk : std_logic;
signal spicr_7_ss_to_spi_clk : std_logic;
signal sr_3_modf_to_spi_clk : std_logic;
signal sr_3_modf_frm_axi_clk : std_logic;
signal data_from_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Bus2IP_WrCE_d1 : std_logic;
signal Bus2IP_WrCE_d2 : std_logic;
signal Bus2IP_WrCE_d3 : std_logic;
signal Bus2IP_WrCE_pulse_1 : std_logic;
signal Bus2IP_WrCE_pulse_2 : std_logic;
signal Bus2IP_WrCE_pulse_3 : std_logic;
signal data_to_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_fifo_wr_ack : std_logic;
-- signal ext_spi_clk : std_logic;
signal tx_fifo_rd_ack_open : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal c_wr_count_width : std_logic;
signal rx_fifo_wr_ack_open : std_logic;
signal data_from_rx_fifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal rx_fifo_rd_ack : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal SPISSR_frm_axi_clk : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal modf_strobe_frm_spi_clk : std_logic;
signal modf_strobe_to_axi_clk : std_logic;
signal dtr_underrun_frm_spi_clk : std_logic;
signal dtr_underrun_to_axi_clk : std_logic;
signal data_to_rx_fifo : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_d1_reg_frm_spi_clk : std_logic;
signal Mst_N_Slv_mode_frm_spi_clk: std_logic;
signal Mst_N_Slv_mode_to_axi_clk : std_logic;
signal SPICR_2_MST_N_SLV_to_spi_clk : std_logic;
signal spicr_5_txfifo_frm_axi_clk : std_logic;
signal spicr_5_txfifo_to_spi_clk: std_logic;
signal reset_RcFIFO_ptr_frm_axi_clk : std_logic;
-- signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal SPIXfer_done_Rx_Wr_en, SPIXfer_done_rd_tx_en: std_logic;
signal Tx_FIFO_Empty_SPISR_frm_spi_clk : std_logic;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : std_logic;
signal Tx_FIFO_Empty_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_frm_axi_clk : std_logic;
signal Rx_FIFO_Full_int,Rx_FIFO_Full_i,RX_one_less_than_full, not_Tx_FIFO_FULL : std_logic;
signal updown_cnt_en_tx, updown_cnt_en_rx : std_logic;
signal TX_one_less_than_full : std_logic;
signal tx_cntr_xfer_done : std_logic;
signal Tx_FIFO_one_less_to_Empty, Tx_FIFO_Full_i: std_logic;
signal Tx_FIFO_Empty_i, Tx_FIFO_Empty_int : std_logic;
signal Tx_FIFO_Empty_frm_axi_clk : std_logic;
signal rx_fifo_empty_i : std_logic;
signal Rx_FIFO_Empty_int : std_logic;
signal IP2Bus_WrAck_1 : std_logic;
signal ip2Bus_WrAck_core_reg_1 : std_logic;
signal IP2Bus_RdAck_1 : std_logic;
signal ip2Bus_RdAck_core_reg_1 : std_logic;
signal IP2Bus_Error_1 : std_logic;
signal ip2Bus_Data_1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)) ;
signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
signal rx_fifo_reset, tx_fifo_reset : std_logic;
signal reg_hole_wr_ack: std_logic;
signal reg_hole_rd_ack: std_logic;
signal read_ack_delay_1: std_logic;
signal read_ack_delay_2: std_logic;
signal read_ack_delay_3: std_logic;
signal read_ack_delay_4: std_logic;
signal read_ack_delay_5: std_logic;
signal read_ack_delay_6: std_logic;
signal read_ack_delay_7: std_logic;
signal read_ack_delay_8: std_logic;
signal write_ack_delay_1: std_logic;
signal write_ack_delay_2: std_logic;
signal write_ack_delay_3: std_logic;
signal write_ack_delay_4: std_logic;
signal write_ack_delay_5: std_logic;
signal write_ack_delay_6: std_logic;
signal write_ack_delay_7: std_logic;
signal write_ack_delay_8: std_logic;
signal error_ack_delay_1: std_logic;
signal error_ack_delay_2: std_logic;
signal error_ack_delay_3: std_logic;
signal error_ack_delay_4: std_logic;
signal error_ack_delay_5: std_logic;
signal error_ack_delay_6: std_logic;
signal error_ack_delay_7: std_logic;
signal error_ack_delay_8: std_logic;
signal IO2_O_int : std_logic;
signal IO2_T_int : std_logic;
signal IO3_O_int : std_logic;
signal IO3_T_int : std_logic;
signal IO2_I_int : std_logic;
signal IO3_I_int : std_logic;
signal fcsbo_int : std_logic;
signal SS_O_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_T_int : std_logic;
signal SS_I_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal fcsbts_int : std_logic;
----RX_FIFO_FULL Logic signals
signal Rx_FIFO_Full_Fifo_org : std_logic;
signal Rx_FIFO_Full_Fifo : std_logic;
signal Rx_FIFO_Full_Fifo_d1 : std_logic;
signal Rx_FIFO_Full_Fifo_d1_synced : std_logic;
signal Rx_FIFO_Full_Fifo_d1_synced_i : std_logic;
signal Rx_FIFO_Full_Fifo_d1_flag : std_logic;
signal Rx_FIFO_Full_Fifo_pos_flag : std_logic;
signal Rx_FIFO_Full_Fifo_d1_sig : std_logic;
--------------------------------------------------------------------------------
begin
-----
DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1)
generate
-----
begin
-----
---
DI_INT_IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(3),
C => EXT_SPI_CLK,
D => di_int(3) --MOSI_I
);
DI_INT_IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(2),
C => EXT_SPI_CLK,
D => di_int(2) -- MISO_I
);
DI_INT_IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(1),
C => EXT_SPI_CLK,
D => di_int(1)
);
-----------------------
DI_INT_IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(0),
C => EXT_SPI_CLK,
D => di_int(0)
);
---
fcsbo_int <= SS_O_int(0);
fcsbts_int <= SS_T_int;
NUM_SS : if (C_NUM_SS_BITS = 1) generate
begin
SS_O <= (others => '0');
SS_T <= '0';
end generate NUM_SS;
NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate
begin
SS_I_int <= SS_I((C_NUM_SS_BITS-1) downto 1) & '1';
SS_O <= SS_O_int((C_NUM_SS_BITS-1) downto 1);
SS_T <= SS_T_int;
end generate NUM_SS_G1;
str_IO0_I <= di_int_sync(0);
do_int(0) <= str_IO0_O;
dts_int(0) <= str_IO0_T ;
str_IO1_I <= di_int_sync(1);
do_int(1) <= str_IO1_O;
dts_int(1) <= str_IO1_T;
DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate
begin
di <= di_int_sync(3) & di_int_sync(2);
do_int(2) <= do(0);
do_int(3) <= do(1);
dts_int(2) <= dts(0);
dts_int(3) <= dts(1);
--do <= do_int(3) & do_int(1);
--dts <= dts_int(3) & dts_int(1);
end generate DATA_OUT_NQUAD;
DATA_OUT_QUAD: if C_SPI_MODE = 2 generate
begin
--di <= "00";--di_int_sync(3) & di_int_sync(2);
IO2_I_int <= di_int_sync(2);
do_int(2) <= IO2_O_int;--do(2);
do_int(3) <= IO3_O_int;--do(1);
--do <= do_int(3) & do_int(1);
IO3_I_int <= di_int_sync(3);
dts_int(2) <= IO2_T_int;--dts_int(3) & dts_int(1);
dts_int(3) <= IO3_T_int;--dts_int(3) & dts_int(1);
end generate DATA_OUT_QUAD;
end generate DATA_STARTUP_EN;
DATA_STARTUP_DIS : if (C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0))
generate
-----
begin
-----
str_IO0_I <= IO0_I;
IO0_O <= str_IO0_O;
IO0_T <= str_IO0_T;
str_IO1_I <= IO1_I;
IO1_O <= str_IO1_O;
IO1_T <= str_IO1_T;
fcsbo_int <= '0';
fcsbts_int <= '0';
SS_O <= SS_O_int;
SS_T <= SS_T_int;
SS_I_int <= SS_I;
end generate DATA_STARTUP_DIS;
-----------------------------------
-- Combinatorial operations for SPI
-----------------------------------
---- A write to read only register wont have any effect on register.
---- The transaction is completed by generating WrAck only.
not_Tx_FIFO_FULL <= not Tx_FIFO_Full;
Interrupt_WrCE_sig <= "00";
IPIF_Lvl_Interrupts_sig <= '0';
LEGACY_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error_1 <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
REG_ERR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_Error <= '0';
else
IP2Bus_Error <= IP2Bus_Error_1;
end if;
end if;
end process REG_ERR_ACK_P;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
--end generate WR_ACK_OR_REDUCE_FIFO_1_GEN;
-----------------------------------------
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg_1;
-------------------------------------------------
-- common WrAck to IPIF
IP2Bus_WrAck_1 <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
ip2Bus_WrAck_core_reg;-- or
--Tx_FIFO_wr_ack; -- newly added
REG_WR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_WrAck <= '0';
else
IP2Bus_WrAck <= IP2Bus_WrAck_1;
end if;
end if;
end process REG_WR_ACK_P;
-------------------------------------------------
--end generate LEGACY_MD_WR_ACK_GEN;
-------------------------------------------------
--LEGACY_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
--begin
-----
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck_1 <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg;
REG_RD_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_RdAck <= '0';
else
IP2Bus_RdAck <= IP2Bus_RdAck_1;
end if;
end if;
end process REG_RD_ACK_P;
---------------------------------------------------
end generate LEGACY_MD_WR_RD_ACK_GEN;
-------------------------------------------------
ENHANCED_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register; -- register hole
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg;--_1;
-------------------------------------------------
-- common WrAck to IPIF
-- in the enhanced mode for FIFO, the IP2bus_Wrack is provided by the enhanced mode statemachine only.
IP2Bus_WrAck <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
(ip2Bus_WrAck_core_reg and (not burst_tr));-- or
--(Tx_FIFO_wr_ack and burst_tr); -- newly added
-------------------------------------------------
--ENHANCED_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
--begin
-----
FIFO_NO_RD_CE_GEN: if C_FIFO_EXIST = 0 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_NO_RD_CE_GEN;
FIFO_YES_RD_CE_GEN: if C_FIFO_EXIST = 1 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
--Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_YES_RD_CE_GEN;
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
--ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg; --_1;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg or
(Rx_FIFO_rd_ack and rready);
-----------------------------------------------------
end generate ENHANCED_MD_WR_RD_ACK_GEN;
-------------------------------------------------
--=============================================================================
TX_FIFO_OCC_DATA_FIFO_16: if C_FIFO_DEPTH = 16 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty); --(FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_16;
--------------------------------------
TX_FIFO_OCC_DATA_FIFO_256: if C_FIFO_DEPTH = 256 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(4)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(5)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(6)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(7)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);-- (FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(4)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(5)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(6)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(7)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_256;
--*****************************************************************************
ip2Bus_Data_occupancy_int(0 to (C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS-1))
<= (others => '0');
ip2Bus_Data_occupancy_int((C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS)
to (C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 or
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1;
-------------------------------------------------------------------------------
-- SPECIAL_CASE_WHEN_SS_NOT_EQL_32 : The Special case is executed whenever
-- C_NUM_SS_BITS is less than 32
-------------------------------------------------------------------------------
SPECIAL_CASE_WHEN_SS_NOT_EQL_32: if(C_NUM_SS_BITS /= 32) generate
-----
begin
-----
ip2Bus_Data_SS_int(0 to (C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS-1))
<= (others => '0');
end generate SPECIAL_CASE_WHEN_SS_NOT_EQL_32;
---------------------------------------------
ip2Bus_Data_SS_int((C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS) to
(C_S_AXI_DATA_WIDTH-1)) <= IP2Bus_SPISSR_Data_int;
-------------------------------------------------------------------------------
ip2Bus_Data_Reg_int(0 to C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH-1) <= (others => '0');
ip2Bus_Data_Reg_int(C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH to C_S_AXI_DATA_WIDTH-1)
<= IP2Bus_SPISR_Data_int or -- SPISR - 11 bit
('0' & IP2Bus_SPICR_Data_int); -- SPICR - 10 bit
-------------------------------------------------------------------------------
-----------------------
Receive_Reg_width_is_32: if(C_NUM_TRANSFER_BITS = 32) generate
-----------------------
begin
-----
IP2Bus_Data_received_int <= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_32;
-----------------------------------------
---------------------------
Receive_Reg_width_is_not_32: if(C_NUM_TRANSFER_BITS /= 32) generate
---------------------------
begin
-----
IP2Bus_Data_received_int(0 to C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS-1)
<= (others => '0');
IP2Bus_Data_received_int((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to
(C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_not_32;
-----------------------------------------
-------------------------------------------------------------------------------
LEGACY_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
ip2Bus_Data_1 <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
REG_IP2BUS_DATA_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_Data <= (others => '0');
else
ip2Bus_Data <= ip2Bus_Data_1;
end if;
end if;
end process REG_IP2BUS_DATA_P;
end generate LEGACY_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
ENHANCED_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
ip2Bus_Data <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
end generate ENHANCED_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
--Bus2IP_Clk => Bus2IP_Clk ,-- in std_logic;
Soft_Reset_frm_axi => reset2ip_reset_int,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------
-- NO_FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 0
--------------------------------------
NO_FIFO_EXISTS: if(C_FIFO_EXIST = 0) generate
----------------------------------
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal modf_strobe_frm_spi_clk : std_logic;
-- signal modf_strobe_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal receive_data_frm_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_data_to_axi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_frm_axi_clk: std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_to_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_fifo_0 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal drr_Overrun_int_frm_spi_clk: std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
-----
begin
-----
Rx_FIFO_rd_ack <= '0';
Tx_FIFO_Full <= '0';
--------------------------------------------------------------------------
-- I_RECEIVE_REG : INSTANTIATE RECEIVE REGISTER
--------------------------------------------------------------------------
QSPI_RX_TX_REG: entity axi_quad_spi_v3_2_8.qspi_receive_transmit_reg
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int, -- in
--SPI Receiver signals -- From AXI clock
Bus2IP_Receive_Reg_RdCE => Bus2IP_RdCE(SPIDRR), -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
IP2Bus_Receive_Reg_Data => IP2Bus_Receive_Reg_Data_int, -- out
--SPI module ports From SPI clock
SPIXfer_done => spiXfer_done_to_axi_clk,--spiXfer_done_int,-- in
SPI_Received_Data => receive_data_to_axi_clk,--receive_Data_int,-- in vec
-- receive & transmit reg signals
-- DRR_Overrun => drr_Overrun_int,-- drr_Overrun_int,-- out
SR_7_Rx_Empty => Rx_FIFO_Empty_i, -- out
-- From AXI clock
Bus2IP_Transmit_Reg_Data=> Bus2IP_Data, -- in vec
Bus2IP_Transmit_Reg_WrCE=> Bus2IP_WrCE(SPIDTR), -- in
Wr_ce_reduce_ack_gen => wr_ce_reduce_ack_gen, -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen, -- in
--SPI Transmitter signals from AXI clock
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
--SPI module ports
DTR_underrun => dtr_underrun_to_axi_clk,--dtr_underrun_int,-- in
SR_5_Tx_Empty => sr_5_Tx_Empty_int, -- out
tx_empty_signal_handshake_req => tx_empty_signal_handshake_req, -- out
tx_empty_signal_handshake_gnt => tx_empty_signal_handshake_gnt, -- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
Transmit_Reg_Data_Out => transmit_Data_fifo_0--transmit_Data_int -- out vec
);
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
spiXfer_done_frm_spi_clk <= spiXfer_done_int ;-- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int ;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int;-- from SPI module
receive_data_frm_spi_clk <= Data_To_Rx_FIFO ; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
transmit_Data_frm_axi_clk <= transmit_Data_fifo_0; -- From AXI clock
Tx_FIFO_Empty_frm_axi_clk <= sr_5_Tx_Empty_int;
Tx_FIFO_Empty_SPISR_frm_spi_clk <= sr_5_Tx_Empty_int;
--Rx_FIFO_Empty_int <= Rx_FIFO_Empty;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty_i;
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
CROSS_CLK_FIFO_0_INST:entity axi_quad_spi_v3_2_8.cross_clk_sync_fifo_0
generic map(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
Async_Clk => Async_Clk ,
--C_AXI_SPI_CLK_EQ_DIFF => C_AXI_SPI_CLK_EQ_DIFF,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK,
Bus2IP_Clk => Bus2IP_Clk ,
Soft_Reset_op => reset2ip_reset_int,
Rst_from_axi_cdc_to_spi => Rst_to_spi_int, -- out std_logic;
----------------------------------------------------------
tx_empty_signal_handshake_req => tx_empty_signal_handshake_req,
tx_empty_signal_handshake_gnt => tx_empty_signal_handshake_gnt,
Tx_FIFO_Empty_cdc_from_axi => Tx_FIFO_Empty_frm_axi_clk,
Tx_FIFO_Empty_cdc_to_spi => Tx_FIFO_Empty,
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------------------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk , -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk , -- out
----------------------------------------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk, -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------------------------------------
Slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk ,-- out
----------------------------------------------------------
receive_Data_cdc_from_spi => receive_Data_frm_spi_clk, -- in
receive_Data_cdc_to_axi => receive_data_to_axi_clk, -- out
----------------------------------------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk, -- in
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk, -- out
----------------------------------------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk, -- out
----------------------------------------------------------
transmit_Data_cdc_from_axi => transmit_Data_frm_axi_clk, -- in
transmit_Data_cdc_to_spi => transmit_Data_to_spi_clk, -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk ,-- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int -- out
----------------------------
);
Data_From_TxFIFO <= transmit_Data_to_spi_clk;
rc_FIFO_Full_strobe_int <= '0';
rc_FIFO_occ_Reversed_int <= (others => '0');
rc_FIFO_Data_Out_int <= (others => '0');
data_Exists_RcFIFO_int <= '0';
tx_FIFO_Empty_strobe_int <= '0';
tx_FIFO_occ_Reversed_int <= (others => '0');
data_Exists_TxFIFO_int <= '0';
data_From_TxFIFO_int <= (others => '0');
tx_FIFO_less_half_int <= '0';
reset_TxFIFO_ptr_int <= '0';
reset_RcFIFO_ptr_int <= '0';
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
Tx_FIFO_Full_int <= not(sr_5_Tx_Empty_int); -- Tx_FIFO_Empty_to_axi_clk);
Rx_FIFO_Full_int <= not(Rx_FIFO_Empty_i);
Rx_FIFO_Full_Fifo <= not(Rx_FIFO_Empty_i);
Rx_FIFO_Full_Fifo_d1_synced <= not(Rx_FIFO_Empty_i);
--------------------------------------------------------------------------
bus2IP_Data_for_interrupt_core(0 to 14) <= Bus2IP_Data(0 to 14);
bus2IP_Data_for_interrupt_core(15 to 22) <= (others => '0');
-- below code manipulates the bus2ip_data going towards interrupt control
-- unit. In FIFO=0, case bit 23 and 25 of IPIER are not applicable.
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 22 23 31
-- <---NA---> <-used->
-- 23 24 25 26 27 28 29 30 31
-- DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- NA-fifo-0 NA -fifo-0
bus2IP_Data_for_interrupt_core(23) <= '0'; -- DRR_Not_Empty bit in IPIER/IPISR
bus2IP_Data_for_interrupt_core(24) <= Bus2IP_Data(24);
bus2IP_Data_for_interrupt_core(25) <= '0'; -- Tx FIFO Half Empty
bus2IP_Data_for_interrupt_core(26 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(26 to (C_S_AXI_DATA_WIDTH-1));
--------------------------------------------------------------------------
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(12) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(11) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(10) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(9) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(8) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk; -- spisel_pulse_o_int;
ip2Bus_IntrEvent_int(6) <= '0'; --
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int_to_axi_clk;
ip2Bus_IntrEvent_int(4) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int;
ip2Bus_IntrEvent_int(2) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; -- slave_MODF_strobe_int;
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int;
end generate NO_FIFO_EXISTS;
-------------------------------------------------------------------------------
-- FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 1
-------------------------------------------------------------------------------
FIFO_EXISTS: if(C_FIFO_EXIST = 1) generate
------------------------------
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant TX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
constant ZERO_TX_FIFO_CNT : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d1: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d2: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal Tx_FIFO_Empty_1 : std_logic;
signal Tx_FIFO_Empty_intr : std_logic;
signal IP2Bus_RdAck_receive_enable : std_logic;
signal IP2Bus_WrAck_transmit_enable : std_logic;
constant ALL_0 : std_logic_vector(0 to TX_FIFO_CNTR_WIDTH-1)
:= (others => '1');
signal data_Exists_RcFIFO_int_d1: std_logic;
signal data_Exists_RcFIFO_pulse : std_logic;
--signal FIFO_Empty_rx : std_logic;
--signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
--signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
--signal spisel_d1_reg_frm_spi_clk : std_logic;
--signal spisel_d1_reg_to_axi_clk : std_logic;
signal tx_occ_msb_111 : std_logic:= '0';
signal tx_occ_msb_11 : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal Rx_FIFO_Empty_frm_axi_clk : std_logic;
signal Rx_FIFO_Empty_to_spi_clk : std_logic;
signal Tx_FIFO_Full_frm_axi_clk : std_logic;
signal Tx_FIFO_Full_to_spi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal SR_3_modf_frm_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal spiXfer_done_to_axi_d1 : std_logic;
signal updown_cnt_en : std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
signal drr_Overrun_int_frm_spi_clk: std_logic;
-----
begin
-----
SPISR_0_CMD_Error_frm_spi_clk <= SPISR_0_CMD_Error_int;
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int; -- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int; -- spi module
--Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full; -- from Async Receive FIFO
----RX_FIFO_FULL Logic signals
Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full_Fifo; -- from Async Receive FIFO
Tx_FIFO_Empty_frm_spi_clk <= Tx_FIFO_Empty_intr; -- Tx_FIFO_Empty; -- from Async Transmit FIFO
spiXfer_done_frm_spi_clk <= spiXfer_done_int; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
Tx_FIFO_Empty_SPISR_frm_spi_clk <= Tx_FIFO_Empty;-- from TX FIFO for SPI Status register
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
-- SPICR_6_RXFIFO_RST_frm_axi_clk<= SPICR_6_RXFIFO_RST_frm_axi_clk; -- from SPICR
reset_RcFIFO_ptr_frm_axi_clk <= reset_RcFIFO_ptr_int; -- from AXI clock
Rx_FIFO_Empty_frm_axi_clk <= Rx_FIFO_Empty; -- from Async Receive FIFO AXI side
Tx_FIFO_Full_frm_axi_clk <= Tx_FIFO_Full; -- from Async Transmit FIFO AXI side
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
--CLK_CROSS_I:
CLK_CROSS_I:entity axi_quad_spi_v3_2_8.cross_clk_sync_fifo_1
generic map(
C_FAMILY => C_FAMILY ,
C_FIFO_DEPTH => C_FIFO_DEPTH ,
Async_Clk => Async_Clk ,
C_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK , -- in std_logic;
Bus2IP_Clk => Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => reset2ip_reset_int ,
--Soft_Reset_op => Soft_Reset_op , -- in std_logic;
Rst_cdc_to_spi => Rst_to_spi_int , -- out std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi => SPISR_0_CMD_Error_frm_spi_clk ,
SPISR_0_CMD_Error_cdc_to_axi => SPISR_0_CMD_Error_to_axi_clk ,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------
Mst_N_Slv_mode_cdc_from_spi => Mst_N_Slv_mode_frm_spi_clk , -- in
Mst_N_Slv_mode_cdc_to_axi => Mst_N_Slv_mode_to_axi_clk , -- out
----------------------------
slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk, -- in
slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk , -- out
----------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk , -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk, -- in
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk , -- out
----------------------------
Rx_FIFO_Full_cdc_from_axi => Rx_FIFO_Full_frm_axi_clk, -- in
Rx_FIFO_Full_cdc_to_spi => Rx_FIFO_Full_to_spi_clk , -- out
----------------------------
reset_RcFIFO_ptr_cdc_from_axi => reset_RcFIFO_ptr_frm_axi_clk, -- in
reset_RcFIFO_ptr_cdc_to_spi => reset_RcFIFO_ptr_to_spi_clk , -- out
----------------------------
Rx_FIFO_Empty_cdc_from_axi => Rx_FIFO_Empty_frm_axi_clk , -- in
Rx_FIFO_Empty_cdc_to_spi => Rx_FIFO_Empty_to_spi_clk , -- out
----------------------------
Tx_FIFO_Empty_cdc_from_spi => Tx_FIFO_Empty_frm_spi_clk, -- in
Tx_FIFO_Empty_cdc_to_axi => Tx_FIFO_Empty_to_Axi_clk, -- out
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_cdc_from_axi => Tx_FIFO_Full_frm_axi_clk,-- in
Tx_FIFO_Full_cdc_to_spi => Tx_FIFO_Full_to_spi_clk ,-- out
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk, -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk, -- out
----------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk , -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int, -- out
----------------------------
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1,
----------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk,
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk
----------------------------
);
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 17 18 31
-- <---NA---> <-used->
-- 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-- CMD_ Loop_Bk MSB Slave_Mode CPOL_CPHA DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- Error Error Error Error Error _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- In Slave
-- mode_only
-- <---------------------------------------> <------------------------------------------------------------->
-- In C_SPI_MODE 1 or 2 only Present in all conditions
-- IPISR Write
-- when FIFO = 1,all other the IPIER, IPISR interrupt bits are applicable based upon the SPI mode.
-- DRR_Not_Empty bit (bit 23) - available only in case of core is selected in
-- slave mode and control register mst_n_slv bit is '0'.
-- Slave_select_mode bit-available only in case of core is selected in slave mode
-- common assignment to SPI_MODE 1/2 and SPI_MODE = 0
bus2IP_Data_for_interrupt_core(0 to 17) <= Bus2IP_Data(0 to 17);
DUAL_MD_IPISR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22) <= Bus2IP_Data(18 to 22);
end generate DUAL_MD_IPISR_GEN;
---------------------------------------------
STD_MD_IPISR_GEN: if C_SPI_MODE = 0 generate
-----------------------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22)<= (others => '0');
end generate STD_MD_IPISR_GEN;
------------------------------------------------
bus2IP_Data_for_interrupt_core(23) <= Bus2IP_Data(23) and -- exists only when FIFO = exists AND
((not spisel_d1_reg_to_axi_clk) --spisel_d1_reg)
or -- core is selected by asserting SPISEL by ext. master AND
(not SPICR_2_MST_N_SLV_frm_axi_clk) --Mst_N_Slv_mode) -- core is in slave mode
);
bus2IP_Data_for_interrupt_core(24 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(24 to (C_S_AXI_DATA_WIDTH-1));
--
----------------------------------------------------
-- _____|------------- data_Exists_RcFIFO_int
-- ________|---------- data_Exists_RcFIFO_int_d1
-- _____|--|__________ data_Exists_RcFIFO_pulse
----------------------------------------------------
DRR_NOT_EMPTY_PULSE_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
data_Exists_RcFIFO_int_d1 <= '0';
else
data_Exists_RcFIFO_int_d1 <= not rx_fifo_empty_i; -- data_Exists_RcFIFO_int;
end if;
end if;
end process DRR_NOT_EMPTY_PULSE_P;
------------------------------------
data_Exists_RcFIFO_pulse <= not rx_fifo_empty_i and
(not data_Exists_RcFIFO_int_d1);
------------------------------------
---------------------------------------------------------------------------
DUAL_MD_INTR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
signal SPISR_4_CPOL_CPHA_Error_d1 : std_logic;
signal SPISR_3_Slave_Mode_Error_d1 : std_logic;
signal SPISR_2_MSB_Error_d1 : std_logic;
signal SPISR_1_LOOP_Back_Error_d1 : std_logic;
signal SPISR_0_CMD_Error_d1 : std_logic;
signal SPISR_4_CPOL_CPHA_Error_pulse : std_logic;
signal SPISR_3_Slave_Mode_Error_pulse: std_logic;
signal SPISR_2_MSB_Error_pulse : std_logic;
signal SPISR_1_LOOP_Back_Error_pulse : std_logic;
signal SPISR_0_CMD_Error_pulse : std_logic;
-----
begin
-----
INTR_UPPER_BITS_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
SPISR_0_CMD_Error_d1 <= '0';
SPISR_1_LOOP_Back_Error_d1 <= '0';
SPISR_2_MSB_Error_d1 <= '0';
SPISR_3_Slave_Mode_Error_d1 <= '0';
SPISR_4_CPOL_CPHA_Error_d1 <= '0';
else
SPISR_0_CMD_Error_d1 <= SPISR_0_CMD_Error_to_axi_clk; -- SPISR_0_CMD_Error_int;
SPISR_1_LOOP_Back_Error_d1 <= SPISR_1_LOOP_Back_Error_int; -- from SPICR
SPISR_2_MSB_Error_d1 <= SPISR_2_MSB_Error_int; -- from SPICR
SPISR_3_Slave_Mode_Error_d1 <= SPISR_3_Slave_Mode_Error_int;-- from SPICR
SPISR_4_CPOL_CPHA_Error_d1 <= SPISR_4_CPOL_CPHA_Error_int; -- from SPICR
end if;
end if;
end process INTR_UPPER_BITS_P;
------------------------------------
SPISR_0_CMD_Error_pulse <= SPISR_0_CMD_Error_to_axi_clk -- SPISR_0_CMD_Error_int
and (not SPISR_0_CMD_Error_d1);
SPISR_1_LOOP_Back_Error_pulse <= SPISR_1_LOOP_Back_Error_int
and (not SPISR_1_LOOP_Back_Error_d1);
SPISR_2_MSB_Error_pulse <= SPISR_2_MSB_Error_int
and (not SPISR_2_MSB_Error_d1);
SPISR_3_Slave_Mode_Error_pulse <= SPISR_3_Slave_Mode_Error_int
and (not SPISR_3_Slave_Mode_Error_d1);
SPISR_4_CPOL_CPHA_Error_pulse <= SPISR_4_CPOL_CPHA_Error_int
and (not SPISR_4_CPOL_CPHA_Error_d1);
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= SPISR_0_CMD_Error_pulse;
ip2Bus_IntrEvent_int(12) <= SPISR_1_LOOP_Back_Error_pulse;
ip2Bus_IntrEvent_int(11) <= SPISR_2_MSB_Error_pulse;
ip2Bus_IntrEvent_int(10) <= SPISR_3_Slave_Mode_Error_pulse;
ip2Bus_IntrEvent_int(9) <= SPISR_4_CPOL_CPHA_Error_pulse ;
end generate DUAL_MD_INTR_GEN;
--------------------------------------------
STD_MD_INTR_GEN: if C_SPI_MODE = 0 generate
-----------------------
begin
-----
ip2Bus_IntrEvent_int(13) <= '0';
ip2Bus_IntrEvent_int(12) <= '0';
ip2Bus_IntrEvent_int(11) <= '0';
ip2Bus_IntrEvent_int(10) <= '0';
ip2Bus_IntrEvent_int(9) <= '0';
end generate STD_MD_INTR_GEN;
-----------------------------------------------
ip2Bus_IntrEvent_int(8) <= data_Exists_RcFIFO_pulse and
((not spisel_d1_reg_to_axi_clk) -- spisel_d1_reg)
or
(not SPICR_2_MST_N_SLV_frm_axi_clk) -- Mst_N_Slv_mode)
);
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk;-- and not SPICR_2_MST_N_SLV_frm_axi_clk; -- spisel_pulse_o_int;-- spi_module
ip2Bus_IntrEvent_int(6) <= tx_FIFO_less_half_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(4) <= rc_FIFO_Full_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(2) <= tx_FIFO_Empty_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; --slave_MODF_strobe_int;-- spi_module
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int; -- spi_module
--Combinatorial operations
reset_TxFIFO_ptr_int <= reset2ip_reset_int or SPICR_5_TXFIFO_RST_frm_axi_clk;
reset_TxFIFO_ptr_int_to_spi <= Rst_to_spi_int or SPICR_5_TXFIFO_to_spi_clk;
--reset_RcFIFO_ptr_int <= Rst_to_spi_int or SPICR_6_RXFIFO_RST_to_spi_clk; -- SPICR_6_RXFIFO_RST_int;
reset_RcFIFO_ptr_int <= reset2ip_reset_int or SPICR_6_RXFIFO_RST_frm_axi_clk;
sr_5_Tx_Empty_int <= not (data_Exists_TxFIFO_int);
Rc_FIFO_Empty_int <= Rx_FIFO_Empty;--not (data_Exists_RcFIFO_int);
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
RX_RD_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_RdAck_receive_enable <= (rd_ce_reduce_ack_gen and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_LEG_MD_GEN;
RX_RD_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
begin
-----
IP2Bus_RdAck_receive_enable <= --(rd_ce_reduce_ack_gen and
(rready and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_ENHAN_MD_GEN;
-- Receive FIFO Logic
rx_fifo_reset <= Rst_to_spi_int or reset_RcFIFO_ptr_to_spi_clk;
RX_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg --axi_quad_spi_v3_2_8_0.async_fifo_fg --lib_fifo_v1_0_5_4.async_fifo_fg
generic map(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => spiXfer_done_int, --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => Rx_FIFO_wr_ack_open , -- : out std_logic;
------
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => IP2Bus_RdAck_receive_enable , -- : in std_logic := '0';
Rd_clk => Bus2IP_Clk , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Full => Rx_FIFO_Full_Fifo_org , -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => Rx_FIFO_occ_Reversed , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => rx_fifo_reset, -- reset_RcFIFO_ptr_to_spi_clk ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
Rx_FIFO_Full_Fifo <= Rx_FIFO_Full_Fifo_org and not Rx_FIFO_Empty_Synced_in_SPI_domain;
RX_FULL_DELAY_PROCESS: process(EXT_SPI_CLK) is
----------------------
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi_int = '1') then
Rx_FIFO_Full_Fifo_d1 <= '0';
else
Rx_FIFO_Full_Fifo_d1 <= Rx_FIFO_Full_Fifo;
end if;
end if;
end process RX_FULL_DELAY_PROCESS;
RX_FULL_EDGE_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Rx_FIFO_Full_Fifo_d1_flag <= '0';
else
Rx_FIFO_Full_Fifo_d1_flag <= Rx_FIFO_Full_Fifo_d1_synced;
end if;
end if;
end process RX_FULL_EDGE_PROCESS;
Rx_FIFO_Full_Fifo_pos_flag <= Rx_FIFO_Full_Fifo_d1_synced and (not Rx_FIFO_Full_Fifo_d1_flag);
--Rx_FIFO_Full_Fifo_neg_flag <= (not Rx_FIFO_Full_Fifo_d1_synced) and Rx_FIFO_Full_Fifo_d1_flag;
RX_FULL_GEN_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Rx_FIFO_Full_Fifo_d1_sig <= '0';
elsif(IP2Bus_RdAck_receive_enable = '1' and Rx_FIFO_Full_Fifo_d1_synced = '1')then
Rx_FIFO_Full_Fifo_d1_sig <= '0';
elsif(Rx_FIFO_Full_Fifo_pos_flag = '1') then
Rx_FIFO_Full_Fifo_d1_sig <= '1';
end if;
end if;
end process RX_FULL_GEN_PROCESS;
----------------------------------
RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Full_Fifo_d1,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced
);
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => reset_RcFIFO_ptr_int, -- in
----------------
Count_Down => IP2Bus_RdAck_receive_enable, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
--updown_cnt_en_rx <= IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1;
--fifo_full_f_int <= Rx_FIFO_Full_Fifo_d1_synced when
--updown_cnt_en_rx <= ((not spiXfer_done_to_axi_1) and IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int and (not Rx_FIFO_Full_Fifo_d1_synced)) or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not Rx_FIFO_Full_Fifo_d1_synced) and (not Rx_FIFO_Full_int));
updown_cnt_en_rx <= ((not spiXfer_done_to_axi_1) and IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int and (not (Rx_FIFO_Full_Fifo_d1_sig or Rx_FIFO_Full_Fifo_pos_flag))) or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not (Rx_FIFO_Full_Fifo_d1_sig or Rx_FIFO_Full_Fifo_pos_flag)) and (not Rx_FIFO_Full_int));
-- updown_cnt_en_rx <= (IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int)
-- or (spiXfer_done_to_axi_1 and (not Rx_FIFO_Full_int))
-- or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not Rx_FIFO_Full_int));
RX_one_less_than_full <= and_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto RX_FIFO_CNTR_WIDTH-RX_FIFO_CNTR_WIDTH+1)) and
(not rx_fifo_count(0))and spiXfer_done_to_axi_1;
RX_FULL_EMP_MD_12_INTR_GEN: if C_SPI_MODE /= 0 generate
-----
--signal rx_fifo_empty_i : std_logic;
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
RX_FIFO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then --(drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then --(drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(RX_one_less_than_full = '1' and
spiXfer_done_to_axi_1 = '1' and
rx_fifo_empty_i = '0')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
end generate RX_FULL_EMP_MD_12_INTR_GEN;
------------------------------------
RX_FULL_EMP_MD_0_GEN: if C_SPI_MODE = 0 generate
--signal rx_fifo_empty_i : std_logic;
-----
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
-------------------------------------------
RX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_i <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(Rx_FIFO_Full_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(RX_one_less_than_full = '1')then
Rx_FIFO_Full_i <= '1';
end if;
end if;
end process RX_FIFO_ABT_TO_FULL_P;
-------------------------------------
RX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_i = '1')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
---------------------------------
Rx_FIFO_Full <= Rx_FIFO_Full_int;
end generate RX_FULL_EMP_MD_0_GEN;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty or Rx_FIFO_Empty_i;
-----------------------------------------------------------------------------
-- AXI Clk domain -- __________________ SPI clk domain
--Din --|AXI clk |-- Dout
--Wr_en --| |-- Rd_en
--Wr_clk --| |-- Rd_clk
--| |--
--Tx_FIFO_Full --| Tx FIFO |-- Tx_FIFO_Empty
--Tx_FIFO_almost_Full --| |-- Tx_FIFO_almost_Empty
--Tx_FIFO_occ_Reversed --| |-- Tx_FIFO_rd_ack
--Tx_FIFO_wr_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
TX_TR_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
Bus2IP_WrCE(SPIDTR)
) and
(not Tx_FIFO_Full);-- after 100 ps;
end generate TX_TR_EN_LEG_MD_GEN;
TX_TR_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
signal local_tr_en : std_logic;
begin
-----
--IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
-- Bus2IP_WrCE(SPIDTR)
-- ) and
-- (not Tx_FIFO_Full)
-- when burst_tr = '0' else
-- (Bus2IP_WrCE(SPIDTR)
-- and
-- (not Tx_FIFO_Full));-- after 100 ps;
local_tr_en <= Bus2IP_WrCE(SPIDTR) and (not Tx_FIFO_Full);
--local_tr_en1 <= Bus2IP_WrCE_d1 and (not Tx_FIFO_Full);
TR_EN_P:process(wr_ce_reduce_ack_gen,
local_tr_en,
burst_tr,
WVALID)is
begin
if(burst_tr = '1') then
IP2Bus_WrAck_transmit_enable <= local_tr_en and WVALID; -- Bus2IP_WrCE_d1 and (not Tx_FIFO_Full); --local_tr_en;
else
IP2Bus_WrAck_transmit_enable <= local_tr_en and wr_ce_reduce_ack_gen;
end if;
end process TR_EN_P;
end generate TX_TR_EN_ENHAN_MD_GEN;
Data_To_TxFIFO <= Bus2IP_Data((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to(C_S_AXI_DATA_WIDTH-1));-- after 100 ps;
-- Transmit FIFO Logic
tx_fifo_reset <= reset2ip_reset_int or reset_TxFIFO_ptr_int;
TX_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg -- entity axi_quad_spi_v3_2_8_0.async_fifo_fg -- lib_fifo_v1_0_5_4.async_fifo_fg
generic map
(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map
(
-- writing will be through AXI clock
Wr_clk => Bus2IP_Clk , -- : in std_logic := '1';
Din => Data_To_TxFIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => IP2Bus_WrAck_transmit_enable, -- : in std_logic := '1';
Wr_ack => Tx_FIFO_wr_ack , -- : out std_logic;
------
-- reading will be through SPI clock
Rd_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Dout => Data_From_TxFIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => SPIXfer_done_rd_tx_en , -- : in std_logic := '0';
Rd_ack => Tx_FIFO_rd_ack_open , -- : out std_logic;
------
Full => Tx_FIFO_Full , -- : out std_logic;
Empty => Tx_FIFO_Empty , -- : out std_logic;
Almost_full => Tx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Tx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => reset_TxFIFO_ptr_int ,--Tx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => Tx_FIFO_occ_Reversed , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
--tx_occ_msb <= tx_fifo_count(TX_FIFO_CNTR_WIDTH-1); -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
--tx_occ_msb_1 <= (tx_fifo_count(TX_FIFO_CNTR_WIDTH-1));-- and not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-2 downto 0))) ;--
--and not Tx_FIFO_Empty_SPISR_to_axi_clk;-- and not Tx_FIFO_Full_int; -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
tx_occ_msb_11 <= (tx_fifo_count);
FIFO_16_OCC_MSB_GEN: if C_FIFO_DEPTH = 16 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(3);
end generate FIFO_16_OCC_MSB_GEN;
FIFO_256_OCC_MSB_GEN: if C_FIFO_DEPTH = 256 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(7);
end generate FIFO_256_OCC_MSB_GEN;
TX_OCC_MSB_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_occ_msb_2 <= '0';
tx_occ_msb_3 <= '0';
tx_occ_msb_4 <= '0';
else
tx_occ_msb_2 <= tx_occ_msb_1;
tx_occ_msb_3 <= tx_occ_msb_2;
tx_occ_msb_4 <= tx_occ_msb_3;
end if;
end if;
end process TX_OCC_MSB_P;
tx_occ_msb <= tx_occ_msb_4 and not Tx_FIFO_Empty_SPISR_to_axi_clk;
data_Exists_TxFIFO_int <= not (Tx_FIFO_Empty);
-----------------------------------------------------------
TX_FIFO_EMPTY_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => TX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en, -- in
----------------
Count_Load => reset_TxFIFO_ptr_int, -- in
----------------
Count_Down => spiXfer_done_to_axi_1, -- in
Count_Out => tx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en <= IP2Bus_WrAck_transmit_enable xor spiXfer_done_to_axi_1;
----------------------------------------
TX_FULL_EMP_INTR_MD_12_GEN: if C_SPI_MODE /=0 generate
-----
begin
-----
Tx_FIFO_Empty_intr <= not (or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk); -- and ( Tx_FIFO_Empty);
Tx_FIFO_Full_int <= Tx_FIFO_Full;
end generate TX_FULL_EMP_INTR_MD_12_GEN;
----------------------------------------
----------------------------------------
TX_FULL_EMP_INTR_MD_0_GEN: if C_SPI_MODE =0 generate
-----
begin
-----
-- Tx_FIFO_one_less_to_Empty <= not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- --and (tx_fifo_count(0))
-- and spiXfer_done_to_axi_1;--tx_cntr_xfer_done_to_axi_1_clk; --
-- --------------------------------------------
-- TX_FIFO_ABT_TO_EMPTY_P:process(Bus2IP_Clk)is
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_Empty_int = '1')then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_one_less_to_Empty = '1') or then
-- Tx_FIFO_Empty_i <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_ABT_TO_EMPTY_P;
-- --------------------------------------
-- TX_FIFO_EMPTY_P: process(Bus2IP_Clk)is
-- begin
-- -----
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_int = '1' and spiXfer_done_to_axi_1 = '1')then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_i = '1')then
-- Tx_FIFO_Empty_int <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_EMPTY_P;
--------------------------------
-- Tx_FIFO_Empty_intr <= Tx_FIFO_Empty_int and spiXfer_done_to_axi_1;
--------------------------------
TX_FIFO_CNTR_DELAY_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_fifo_count_d1 <= (others => '0');
tx_fifo_count_d2 <= (others => '0');
spiXfer_done_to_axi_d1 <= '0';
else
tx_fifo_count_d1 <= tx_fifo_count;
tx_fifo_count_d2 <= tx_fifo_count_d1;
spiXfer_done_to_axi_d1 <= spiXfer_done_to_axi_1;
end if;
end if;
end process TX_FIFO_CNTR_DELAY_P;
Tx_FIFO_Empty_intr <= (not (or_reduce(tx_fifo_count_d2(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_d1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk));
TX_one_less_than_full <= and_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto TX_FIFO_CNTR_WIDTH-TX_FIFO_CNTR_WIDTH+1)) and
(not tx_fifo_count(0))and IP2Bus_WrAck_transmit_enable;
-------------------------------------------
TX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_i <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(Tx_FIFO_Full_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(TX_one_less_than_full = '1')then
Tx_FIFO_Full_i <= '1';
end if;
end if;
end process TX_FIFO_ABT_TO_FULL_P;
----------------------------------
TX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_int <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_int = '1' and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_i = '1') then -- and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '1';
end if;
end if;
end process TX_FIFO_FULL_P;
---------------------------
end generate TX_FULL_EMP_INTR_MD_0_GEN;
----------------------------------------
-------------------------------------------------------------------------------
-- I_FIFO_IF_MODULE : INSTANTIATE FIFO INTERFACE MODULE
-------------------------------------------------------------------------------
Rx_FIFO_Full_Fifo_d1_synced_i <= Rx_FIFO_Full_Fifo_d1_synced and (not Rx_FIFO_Empty);
FIFO_IF_MODULE_I: entity axi_quad_spi_v3_2_8.qspi_fifo_ifmodule
generic map
(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int, -- in
-- Slave attachment ports from AXI clock
Bus2IP_RcFIFO_RdCE => Bus2IP_RdCE(SPIDRR),-- axiclk -- in
Bus2IP_TxFIFO_WrCE => Bus2IP_WrCE(SPIDTR),-- axi clk -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen,-- axi clk -- in
-- FIFO ports
Data_From_TxFIFO => Data_From_TxFIFO ,-- spi clk -- in vec
Data_From_Rc_FIFO => Data_From_Rx_FIFO ,-- axi clk -- in vec
Tx_FIFO_Data_WithZero => transmit_Data_int ,-- spi clk -- out vec
IP2Bus_RX_FIFO_Data => IP2Bus_Receive_Reg_Data_int, -- out vec
---------------------
--Rc_FIFO_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full => Rx_FIFO_Full_Fifo_d1_synced_i, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full_strobe => rc_FIFO_Full_strobe_int, -- out
---------------------
Tx_FIFO_Empty => Tx_FIFO_Empty_intr , -- Tx_FIFO_Empty_to_Axi_clk, -- sr_5_Tx_Empty_int,-- spi clk -- in
Tx_FIFO_Empty_strobe => tx_FIFO_Empty_strobe_int, -- out
---------------------
Rc_FIFO_Empty => Rx_FIFO_Empty_int, -- 13-09-2012 rx_fifo_empty_i, -- Rx_FIFO_Empty , -- Rc_FIFO_Empty_int, -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
Tx_FIFO_Full => Tx_FIFO_Full_int, -- in
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
---------------------
Tx_FIFO_Occpncy_MSB => tx_occ_msb, -- in
Tx_FIFO_less_half => tx_FIFO_less_half_int, -- out
---------------------
DTR_underrun => dtr_underrun_to_axi_clk,-- dtr_underrun_int,-- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
---------------------
SPIXfer_done => spiXfer_done_to_axi_1, -- spiXfer_done_int, -- in
rready => rready
-- DRR_Overrun_reg => drr_Overrun_int -- out
);
-------------------------------------------------------------------------------
-- TX_OCCUPANCY_I : INSTANTIATE TRANSMIT OCCUPANCY REGISTER
-------------------------------------------------------------------------------
TX_OCCUPANCY_I: entity axi_quad_spi_v3_2_8.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPITFOR), -- in
--FIFO port
IP2Reg_OCC_Data => tx_fifo_count, -- tx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Tx_FIFO_OCC_Reg_Data_int -- out vec
);
-------------------------------------------------------------------------------
-- RX_OCCUPANCY_I : INSTANTIATE RECEIVE OCCUPANCY REGISTER
-------------------------------------------------------------------------------
RX_OCCUPANCY_I: entity axi_quad_spi_v3_2_8.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS--,
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPIRFOR), -- in
--FIFO port
IP2Reg_OCC_Data => rx_fifo_count, --rx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Rx_FIFO_OCC_Reg_Data_int -- out vec
);
end generate FIFO_EXISTS;
--------------------------------------------
-- LOGIC_FOR_MD_0_GEN: in stantiate the original SPI module when the core is configured in Standard SPI mode.
------------------------------
LOGIC_FOR_MD_0_GEN: if C_SPI_MODE = 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
-----
begin
-----
-- un used IO2 and IO3 O/P ports are tied to 0 and T ports are tied to '1'
DATA_STARTUP_USED : if C_USE_STARTUP = 1 generate
-----
begin
-----
-- IO2_O <= do(2);
-- IO2_T <= dts(2);
-- IO3_O <= do(3);
-- IO3_T <= dts(3);
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SPISR_0_CMD_Error_int <= '0'; -- no command error when C_SPI_MODE= 0
end generate DATA_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
PACK => pack, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets -- SRDONETS -- 1-bit input
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
----------------------------------------------------------------------------
-- SPI_MODULE_I : INSTANTIATE SPI MODULE
----------------------------------------------------------------------------
SPI_MODULE_I: entity axi_quad_spi_v3_2_8.qspi_mode_0_module
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_FIFO_EXIST => C_FIFO_EXIST
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK, -- in
Soft_Reset_op => Rst_to_spi_int, -- in
------------------------
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk,--_int,
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk,--_int,
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int,
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk,--_int,
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk,--_int,
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_to_spi_clk, -- SPICR_5_TXFIFO_RST_to_spi_clk,--_int,
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int,
SPICR_7_SS => SPICR_7_SS_to_spi_clk,--_int,
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int,
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk,--_int,
------------------------
Rx_FIFO_Empty_i_no_fifo => Rx_FIFO_Empty_i, -- in
SR_3_MODF => SR_3_modf_to_spi_clk, -- in
SR_5_Tx_Empty => Tx_FIFO_Empty, -- sr_5_Tx_Empty_int, -- in
Slave_MODF_strobe => slave_MODF_strobe_int, -- out
MODF_strobe => modf_strobe_int, -- out
Slave_Select_Reg => register_Data_slvsel_int, -- already updated -- in vec
Transmit_Data => Data_From_TxFIFO, -- transmit_Data_int, -- in vec
Receive_Data => Data_To_Rx_FIFO, -- receive_Data_int, -- out vec
SPIXfer_done => spiXfer_done_int, -- out
-- SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
DTR_underrun => dtr_underrun_int, -- out
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--SPI Ports
SCK_I => SCK_I, -- in
SCK_O_reg => SCK_O_int, -- out
SCK_T => SCK_T, -- out
MISO_I => str_IO1_I, --IO0_I, -- MOSI_I, -- in std_logic; -- MISO
MISO_O => str_IO1_O,--IO0_O, -- MOSI_O, -- out std_logic;
MISO_T => str_IO1_T, --IO0_T, -- MOSI_T, -- out std_logic;
MOSI_I => str_IO0_I,--MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
MOSI_O => str_IO0_O,--IO1_O, -- MISO_O, -- out std_logic; -- MOSI
MOSI_T => str_IO0_T,--IO1_T, -- MISO_T, -- out std_logic;
--MISO_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in
--MISO_O => IO1_O, -- MISO_O, -- out
--MISO_T => IO1_T, -- MISO_T, -- out
--MOSI_I => IO0_I, -- MOSI_I, -- in
--MOSI_O => IO0_O, -- MOSI_O, -- out
--MOSI_T => IO0_T, -- MOSI_T, -- out
SPISEL => SPISEL, -- in
SS_I => SS_I_int, -- in
SS_O => SS_O_int, -- out
SS_T => SS_T_int, -- out
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
control_bit_7_8 => SPICR_bits_7_8_to_spi_clk, -- in vec
Mst_N_Slv_mode => Mst_N_Slv_mode ,
--Rx_FIFO_Full => Rx_FIFO_Full_to_spi_clk,
Rx_FIFO_Full => Rx_FIFO_Full_Fifo,
DRR_Overrun_reg => drr_Overrun_int, -- out
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk,
tx_cntr_xfer_done => tx_cntr_xfer_done
);
-------------
end generate LOGIC_FOR_MD_0_GEN;
----------------------------------------
-- LOGIC_FOR_MD_12_GEN: to generate the functionality for mode 1 and 2.
------------------------------
LOGIC_FOR_MD_12_GEN: if C_SPI_MODE /= 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
signal Data_Dir_int : std_logic;
signal Data_Mode_1_int : std_logic;
signal Data_Mode_0_int : std_logic;
signal Data_Phase_int : std_logic;
signal Addr_Mode_1_int : std_logic;
signal Addr_Mode_0_int : std_logic;
signal Addr_Bit_int : std_logic;
signal Addr_Phase_int : std_logic;
signal CMD_Mode_1_int : std_logic;
signal CMD_Mode_0_int : std_logic;
signal CMD_Error_int : std_logic;
signal CMD_decoded_int : std_logic;
signal Dummy_Bits_int : std_logic_vector(3 downto 0);
-----
begin
-----
LOGIC_FOR_C_SPI_MODE_1_GEN: if C_SPI_MODE = 1 generate
-------
begin
-------
-- DATA_STARTUP_USED_MODE1 : if C_USE_STARTUP = 1 generate
-- -----
-- begin
-- -----
-- IO2_O <= do(2);
-- IO2_T <= dts(2);
-- IO3_O <= do(3);
-- IO3_T <= dts(3);
-- --IO2_I_int <= di(2);-- assign default value as this bit is not used in thid mode
-- IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
-- --IO3_I_int <= di(3);-- assign default value as this bit is not used in thid mode
-- IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
--end generate DATA_STARTUP_USED_MODE1;
--
--DATA_NOSTARTUP_USED_MODE1 : if C_USE_STARTUP = 0 generate
-- -----
-- begin
-- -----
IO2_O <= '0'; -- not used in the logic
IO3_O <= '0'; -- not used in the logic
IO2_T <= '1'; -- disable the tri-state buffers
IO3_T <= '1'; -- disable the tri-state buffers
IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
--end generate DATA_NOSTARTUP_USED_MODE1;
end generate LOGIC_FOR_C_SPI_MODE_1_GEN;
---------------------------------------
LOGIC_FOR_C_SPI_MODE_2_GEN: if C_SPI_MODE = 2 generate
-------
begin
-------
DATA_STARTUP_USED_MODE2 : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate
-----
begin
-----
di <= "00";
end generate DATA_STARTUP_USED_MODE2;
DATA_NOSTARTUP_USED_MODE2 : if (C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) generate
-----
begin
-----
IO2_I_int <= IO2_I; -- assign this bit from the top level port
IO2_O <= IO2_O_int;
IO2_T <= IO2_T_int;
IO3_I_int <= IO3_I; -- assign this bit from the top level port
IO3_O <= IO3_O_int;
IO3_T <= IO3_T_int;
end generate DATA_NOSTARTUP_USED_MODE2;
end generate LOGIC_FOR_C_SPI_MODE_2_GEN;
---------------------------------------
SPISR_0_CMD_Error_int <= CMD_Error_int;
dtr_underrun_int <= '0'; -- SPI MODE 1 & 2 are master modes, so DTR under run wont be present
slave_MODF_strobe_int <= '0'; -- SPI MODE 1 & 2 are master modes, so the slave mode fault error wont appear
Mst_N_Slv_mode <= '1';
-------------------------------------------------------
-- SCK_O <= SCK_O_int; -- output from the core
-- MISO_I_int <= IO1_I; -- input to the core
-- *
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
PACK => pack, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets -- SRDONETS -- 1-bit input
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
-- *
-- Add instance for Look up table logic
SPI_MODE_1_LUT_LOGIC_I: entity axi_quad_spi_v3_2_8.qspi_look_up_logic
-------------
generic map
(
C_FAMILY => C_FAMILY ,
C_SPI_MODE => C_SPI_MODE ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SELECT_XPM => C_SELECT_XPM ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int , -- : in std_logic;
TXFIFO_RST => reset_TxFIFO_ptr_int_to_spi, -- : in std_logic;
-------------------- --
DTR_FIFO_Data_Exists=> data_Exists_TxFIFO_int, -- : in std_logic;
Data_From_TxFIFO => Data_From_TxFIFO , -- : in std_logic_vector
-- (0 to (C_NUM_TRANSFER_BITS-1))
pr_state_idle => pr_state_idle_int , --
-------------------- --
Data_Dir => Data_Dir_int , -- : out std_logic;
Data_Mode_1 => Data_Mode_1_int , -- : out std_logic;
Data_Mode_0 => Data_Mode_0_int , -- : out std_logic;
Data_Phase => Data_Phase_int , -- : out std_logic;
-------------------- --
Quad_Phase => Quad_Phase_int ,
-------------------- --
Addr_Mode_1 => Addr_Mode_1_int , -- : out std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- : out std_logic;
Addr_Bit => Addr_Bit_int , -- : out std_logic;
Addr_Phase => Addr_Phase_int , -- : out std_logic;
-------------------- --
CMD_Mode_1 => CMD_Mode_1_int , -- : out std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- : out std_logic;
CMD_Error => CMD_Error_int , -- : out std_logic;
-------------------- -- -
CMD_decoded => CMD_decoded_int -- : out std_logic
);
---------
SPI_MODE_CONTROL_LOGIC_I: entity axi_quad_spi_v3_2_8.qspi_mode_control_logic
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SUB_FAMILY => C_SUB_FAMILY
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK , -- Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => Rst_to_spi_int , -- in std_logic;
-------------------- , --
DTR_FIFO_Data_Exists => data_Exists_TxFIFO_int , -- in std_logic;
Slave_Select_Reg => register_Data_slvsel_int , -- already updated -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data => Data_From_TxFIFO,--transmit_Data_int , -- already updated -- in std_logic_vector(0 to (C_NUM_TRANSFER_BITS
Receive_Data => Data_To_Rx_FIFO , -- out std_logic_vector(0 to (C_NUM_TRANSFER_BITS
--Data_To_Rx_FIFO_1 => Data_To_Rx_FIFO_1,
SPIXfer_done => spiXfer_done_int , -- already updated -- out std_logic;
SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
MODF_strobe => modf_strobe_int , -- already updated
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--------------------- --
SR_3_MODF => SR_3_modf_to_spi_clk , -- in std_logic;
SR_5_Tx_Empty => Tx_FIFO_Empty , -- sr_5_Tx_Empty_int -- in std_logic;
--SR_6_Rx_Full => Rx_FIFO_Full , -- in
pr_state_idle => pr_state_idle_int , --
--------------------- -- from control register
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk ,--SPICR_0_LOOP_int , -- in std_logic;
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk ,--_int , -- in std_logic;
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int , -- in std_logic;
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk ,--_int , -- in std_logic;
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk ,--_int , -- in std_logic;
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_7_SS => SPICR_7_SS_to_spi_clk ,--_int , -- in std_logic;
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int , -- in std_logic;
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk ,--_int , -- in std_logic;
--------------------- --
--------------------- -- from look up table
Data_Dir => Data_Dir_int , -- in std_logic;
Data_Mode_1 => Data_Mode_1_int , -- in std_logic;
Data_Mode_0 => Data_Mode_0_int , -- in std_logic;
Data_Phase => Data_Phase_int ,
---------------------
--Dummy_Bits => Dummy_Bits_int , -- in std_logic_vector(3 downto 0);
Quad_Phase => Quad_Phase_int ,
--------------------- -- in std_logic;
Addr_Mode_1 => Addr_Mode_1_int , -- in std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- in std_logic;
Addr_Bit => Addr_Bit_int , -- in std_logic;
Addr_Phase => Addr_Phase_int , -- in std_logic;
---------------------
CMD_Mode_1 => CMD_Mode_1_int , -- in std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- in std_logic;
CMD_Error => CMD_Error_int , -- in std_logic;
--------------------- --
CMD_decoded => CMD_decoded_int , -- in std_logic;
--SPI Interface --
SCK_I => SCK_I, -- in std_logic;
SCK_O_reg => SCK_O_int, -- out std_logic;
SCK_T => SCK_T, -- out std_logic;
--
IO0_I => str_IO0_I, --IO0_I, -- MOSI_I, -- in std_logic; -- MISO
IO0_O => str_IO0_O,--IO0_O, -- MOSI_O, -- out std_logic;
IO0_T => str_IO0_T, --IO0_T, -- MOSI_T, -- out std_logic;
IO1_I => str_IO1_I,--MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
IO1_O => str_IO1_O,--IO1_O, -- MISO_O, -- out std_logic; -- MOSI
IO1_T => str_IO1_T,--IO1_T, -- MISO_T, -- out std_logic;
--
IO2_I => IO2_I_int, -- -- in std_logic;
IO2_O => IO2_O_int, -- -- out std_logic;
IO2_T => IO2_T_int, -- -- out std_logic;
--
IO3_I => IO3_I_int, -- -- in std_logic;
IO3_O => IO3_O_int, -- -- out std_logic;
IO3_T => IO3_T_int, -- -- out std_logic;
--
SPISEL => SPISEL, -- in std_logic;
--
SS_I => SS_I_int, -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_O => SS_O_int, -- out std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_T => SS_T_int, -- out std_logic;
--
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
Control_bit_7_8 => SPICR_bits_7_8_to_spi_clk , -- in std_logic_vector(0 to 1) --(7 to 8)
Rx_FIFO_Full => Rx_FIFO_Full_Fifo,
DRR_Overrun_reg => drr_Overrun_int,
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk
);
-------------
end generate LOGIC_FOR_MD_12_GEN;
------------------------------------------
--------------------------------------------------------------------------------
CONTROL_REG_I: entity axi_quad_spi_v3_2_8.qspi_cntrl_reg
generic map
(
--------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
--------------------------
-- Number of bits in regis
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
--------------------------
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH,
--------------------------
C_SPI_MODE => C_SPI_MODE
--------------------------
)
port map
( -- in
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int,
---------------------------
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen, -- in
Bus2IP_SPICR_WrCE => Bus2IP_WrCE(SPICR), -- in
Bus2IP_SPICR_RdCE => Bus2IP_RdCE(SPICR), -- in
Bus2IP_SPICR_data => Bus2IP_Data, -- in vec
---------------------------
SPICR_0_LOOP => SPICR_0_LOOP_frm_axi_clk, -- out
SPICR_1_SPE => SPICR_1_SPE_frm_axi_clk, -- out
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_frm_axi_clk, -- out
SPICR_3_CPOL => SPICR_3_CPOL_frm_axi_clk, -- out
SPICR_4_CPHA => SPICR_4_CPHA_frm_axi_clk, -- out
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_frm_axi_clk, -- out
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_frm_axi_clk, -- out
SPICR_7_SS => SPICR_7_SS_frm_axi_clk, -- out
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_frm_axi_clk, -- out
SPICR_9_LSB => SPICR_9_LSB_frm_axi_clk, -- out
-- to Status Register
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int, -- out
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int, -- out
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int, -- out
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int, -- out
---------------------------
IP2Bus_SPICR_Data => IP2Bus_SPICR_Data_int, -- out vec
---------------------------
Control_bit_7_8 => SPICR_bits_7_8_frm_axi_clk -- out vec
---------------------------
);
-------------------------------------------------------------------------------
-- STATUS_REG_I : INSTANTIATE STATUS REGISTER
-------------------------------------------------------------------------------
STATUS_REG_MODE_0_GEN: if C_SPI_MODE = 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2_8.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => '0' , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
--SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_Fifo_d1_synced, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_0_GEN;
STATUS_REG_MODE_12_GEN: if C_SPI_MODE /= 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2_8.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => SPISR_0_CMD_Error_to_axi_clk , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
--SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_Fifo_d1_synced, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_12_GEN;
-------------------------------------------------------------------------------
-- SOFT_RESET_I : INSTANTIATE SOFT RESET
-------------------------------------------------------------------------------
SOFT_RESET_I: entity axi_quad_spi_v3_2_8.soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the PLBv46 Slave Single Bus
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => Bus2IP_Reset, -- in
Bus2IP_WrCE => Bus2IP_WrCE(SWRESET), -- in
Bus2IP_Data => Bus2IP_Data, -- in
Bus2IP_BE => Bus2IP_BE, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset_int, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
-------------------------------------------------------------------------------
-- INTERRUPT_CONTROL_I : INSTANTIATE INTERRUPT CONTROLLER
-------------------------------------------------------------------------------
bus2ip_intr_rdce <= "0000000" &
Bus2IP_RdCE(7) &
Bus2IP_RdCE(8) &
'0' &
Bus2IP_RdCE(10)&
"00000";
bus2ip_intr_wrce <= "0000000" &
Bus2IP_WrCE(7) &
Bus2IP_WrCE(8) &
'0' &
Bus2IP_WrCE(10)&
"00000";
------------------------------------------------------------------------------
intr_controller_rd_ce_or_reduce <= or_reduce(Bus2IP_RdCE(0 to 6)) or
Bus2IP_RdCE(9) or
or_reduce(Bus2IP_RdCE(11 to 15));
------------------------------------------------------------------------------
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_controller_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_controller_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
------------------------------------------------------------------------------
intr_controller_wr_ce_or_reduce <= or_reduce(Bus2IP_WrCE(0 to 6)) or
Bus2IP_WrCE(9) or
or_reduce(Bus2IP_WrCE(11 to 15));
------------------------------------------------------------------------------
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_controller_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_controller_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
------------------------------------------------------------------------------
INTERRUPT_CONTROL_I: entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => 16,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => false,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => reset2ip_reset_int, -- in
Bus2IP_Data => bus2IP_Data_for_interrupt_core, -- in vec
Bus2IP_BE => Bus2IP_BE, -- in vec
Interrupt_RdCE => bus2ip_intr_rdce, -- in vec
Interrupt_WrCE => bus2ip_intr_wrce, -- in vec
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intrs
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => ip2Bus_IntrEvent_int, -- in
Intr2Bus_DevIntr => IP2INTC_Irpt, -- out
Intr2Bus_DBus => intr_ip2bus_data, -- out vec
Intr2Bus_WrAck => intr_ip2bus_wrack, -- out
Intr2Bus_RdAck => intr_ip2bus_rdack, -- out
Intr2Bus_Error => intr_ip2bus_error, -- out
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
--------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
5f0161d196634bb9b9e902aa9f5b2102
| 0.449149 | 3.653777 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd
| 4 | 59,962 |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_s2mm_dre;
use axi_datamover_v5_1_9.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_9.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
bsd-3-clause
|
f1e6a008fc4ffc73e655a75933fcd58f
| 0.427371 | 4.893259 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/uart/uart_rx.vhdl
| 1 | 3,441 |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity uart_rx is
port (
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
baud_tick : in std_logic;
rx_done_tick : out std_logic;
rx_data : out std_logic_vector( 7 downto 0 )
);
end entity;
architecture behav of uart_rx is
type STATE is (IDLE, START, DATA, STOP);
signal state_reg : STATE;
signal state_next : STATE;
signal baud_reg : std_logic_vector( 4 downto 0 );
signal baud_next : std_logic_vector( 4 downto 0 );
signal n_reg : std_logic_vector( 3 downto 0 );
signal n_next : std_logic_vector( 3 downto 0 );
signal d_reg : std_logic_vector( 7 downto 0 );
signal d_next : std_logic_vector( 7 downto 0 );
begin
a: process (clk, reset) is
begin
if ( reset = '1' ) then
state_reg <= IDLE;
baud_reg <= (others => '0');
n_reg <= (others => '0');
d_reg <= (others => '0');
elsif (clk'EVENT and (clk = '1')) then
state_reg <= state_next;
baud_reg <= baud_next;
n_reg <= n_next;
d_reg <= d_next;
end if;
end process;
b: process
begin
state_next <= state_reg;
rx_done_tick <= '0';
baud_next <= baud_reg;
n_next <= n_reg;
d_next <= d_reg;
case ( state_reg ) is
when
IDLE =>
if ( rx = '0' ) then
state_next <= START;
baud_next <= "00000";
end if;
when
START =>
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"8" ) ) then
state_next <= DATA;
baud_next <= "00000";
n_next <= "0000";
end if;
end if;
when
DATA =>
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( baud_reg = X"10" ) then
d_next <= ( rx & d_reg(7 downto 1 ) );
n_next <= vec_increment(n_reg);
baud_next <= "00000";
else
if ( ( n_reg = X"8" ) ) then
state_next <= STOP;
end if;
end if;
end if;
when
STOP =>
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
state_next <= IDLE;
rx_done_tick <= '1';
end if;
end if;
end case;
end process;
rx_data <= d_reg;
end;
|
gpl-3.0
|
efb7d383e7f9571d066834034e9c73b1
| 0.37896 | 4.19123 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/control.vhd
| 1 | 15,703 |
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH;
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
mit
|
1a94497b49e327d8572839840a0ddbae
| 0.526078 | 3.094797 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm_cmdsts_if.vhd
| 4 | 22,874 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_cmdsts_if is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_ENABLE_QUEUE : integer range 0 to 1 := 1
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : out std_logic ; --
--
s2mm_packet_eof : out std_logic ; --
--
s2mm_sts_received_clr : in std_logic ; --
s2mm_sts_received : out std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8)-1 downto 0); --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
s2mm_brcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_done : out std_logic ; --
s2mm_error : out std_logic ; --
s2mm_interr : out std_logic ; --
s2mm_slverr : out std_logic ; --
s2mm_decerr : out std_logic ; --
s2mm_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_s2mm_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal s2mm_slverr_i : std_logic := '0';
signal s2mm_decerr_i : std_logic := '0';
signal s2mm_interr_i : std_logic := '0';
signal s2mm_error_or : std_logic := '0';
signal s2mm_packet_eof_i : std_logic := '0';
signal smpl_dma_overflow : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s2mm_slverr <= s2mm_slverr_i;
s2mm_decerr <= s2mm_decerr_i;
s2mm_interr <= s2mm_interr_i or smpl_dma_overflow;
s2mm_packet_eof <= s2mm_packet_eof_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when s2mm_desc_cmplt = '1' and s2mm_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_HOLD_NO_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
-- s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
end generate GEN_HOLD_NO_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
elsif(sts_tready = '1' and m_axis_s2mm_sts_tvalid = '1')then
sts_tready <= '0';
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_s2mm_sts_tready <= sts_tready;
log_status <= '1' when m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0'
else '0';
-- Status stream is included, and using the rxlength from the status stream and in Scatter Gather Mode
DETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_SG_USE_STSAPP_LENGTH = 1
and C_INCLUDE_SG = 1) or (C_MICRO_DMA = 1) generate
begin
-- Bytes received not available in determinate byte mode
s2mm_brcvd <= (others => '0');
-- Simple DMA overflow not used in Scatter Gather Mode
smpl_dma_overflow <= '0';
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on status received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGEOF_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
end generate DETERMINATE_BTT_MODE;
-- No Status Stream or not using rxlength from status stream or in Simple DMA Mode
INDETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_SG_USE_STSAPP_LENGTH = 0
or C_INCLUDE_SG = 0) and (C_MICRO_DMA = 0) generate
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - C_SG_LENGTH_WIDTH);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
begin
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_brcvd <= m_axis_s2mm_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT);
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on statis received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
-- If in Simple DMA mode then generate overflow flag
GEN_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 0 generate
REG_OVERFLOW : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_dma_overflow <= '0';
-- If status received and TLAST bit is NOT set then packet is bigger than
-- BTT value commanded which is an invalid command
elsif(log_status = '1' and m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0')then
smpl_dma_overflow <= '1';
end if;
end if;
end process REG_OVERFLOW;
end generate GEN_OVERFLOW_SMPL_DMA;
-- If in Scatter Gather Mode then do NOT generate simple dma mode overflow flag
GEN_NO_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 1 generate
begin
smpl_dma_overflow <= '0';
end generate GEN_NO_OVERFLOW_SMPL_DMA;
end generate INDETERMINATE_BTT_MODE;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
s2mm_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error_or <= s2mm_slverr_i or s2mm_decerr_i or s2mm_interr_i or smpl_dma_overflow;
-- Log errors into a global error output
S2MM_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((s2mm_error_or = '1')
or (stale_desc = '1' and s2mm_cmnd_wr='1'))then
s2mm_error <= '1';
end if;
end if;
end process S2MM_ERROR_PROCESS;
end implementation;
|
bsd-3-clause
|
1acf10940aa9b178da9ff91a5e3de1df
| 0.451954 | 4.289947 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_register.vhd
| 4 | 49,418 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_ADDRESS_MSB_INDEX : integer := 7;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i_64 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_i_64 & buffer_address_i ;
end generate BUFF_ADDR_EQL64;
BUFF_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate BUFF_ADDR_EQL32;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH - 1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i_64 <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_i_64 <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUFF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
|
bsd-3-clause
|
36ad661301f8a2ede78da9cb9f6fca14
| 0.43383 | 4.421797 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0.vhd
| 2 | 17,726 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dT0n33fVnNUpQ9hdUJ21pQ07JL/A+hQ+akHpYLJ0tJl1OCyN91JNiVj1uX9X4v2wX5ow6Eh6RlHI
4nWMfK4cDg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
eIF5HHwAQuc7Jskz3KWFt77PolzF6ZBnLJ3Icr482UYi8h/abAEz1HmAvaC3W7342G60kojo3rsn
KxU588I2E4G1bW/tp0z/96j7XQ2CvXJoN27S13/L4r6I0bmzjRHfCSfyW2dXzpbgmxyjEOyPUawv
yKRJIbT9ge+B6o5k26w=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IfzIQakSG0h8PJJd5Ba1I6bkofE61ofsB+TERQg6AzGKwyfkAJIBIIsZ/Qr2QhrwjNBgXtdlhlUq
mhwbWwFB9aeycO9sqBiVESXdbSlClBYnvZWVql61AJYXKRMfldUhx4v3N1/Rtn7mBa8F4rJsZXND
w/0NEZV6M7sf3EjybP4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
PAMD7VKJwNgScNcDo2tcN0Z8RDeTS//JKr2TbEKhYXHldSCb6cFaN9iqGbhcv48a1BdmSTbTvPrq
C5+sINq/IwqAgiETMNKL7PNxI3viz0FIMxClmIgtwGgwsK2u3I5S96xi4X9/LzsyzBv5oE0Y18Jg
CaVjaH9lVRy2wSbn9zj/L5heIhZC1W/j2ooVyO7buMFB2HGj3zMRvoXi3cBtCwd3dYeYDiNTHU8L
P3eimX2Nia3nhEHO7EWIdgE29XHq66J0qpEaKnakjoSF+ArQx0dRK54Z9vHlpmpEK7kPPm+U7ge7
K2VekDZXtVX3F+Nyb9ipQ1qMvPGMB/ItIWgk4Q==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
V9KR2UnqKEmo5s+sH/tzdwRnmlxYrZHuaRZPwYR86xJsAHi4ngp0aBIYJZZJwcszN/Lo1BIdZmmw
8NfCjBm0BsWh/w9psZVZEM7Wnkvr2OQ4qw2qam2DmyMgXLAOJX/xJvf2f6U96zU3UDcP3XMy2ooi
ZrWyYgfZBlRnfkQF0kKkvQloS+IDbE59yH1t9YDSQ0CBB0hDVQgcFzVcie8JictQFSw+VFQEm1rF
taB9IFCxLlnshp132fDKRgxr5EfYUMUfzadU2/7rwXmMV9Ex9LuEQuvn+9Ogt63i0Wg5+nTKp1fK
/E2m2cWVPSgVirwrmm3qKXRV4xrZ9/N8+wLpuQ==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qnHa0krfIgqY08IiMXydzDUrP2UAPg+c0lUmYN4oii33G6Ib7reBNJfe3pSr0bh9Y14mQHQUyyAW
2LaRzuzaNogaBSSmavUYK06o5CLIYj/j2+hoNzFX1TRq7IbEp1Mv2gYua/uYeSuhYIQHo+dQVtfP
XrkTYgOwDU7gkv1fB5wbq5ZY9Ck2TPFfoE4eAVQP6H6tXEN5Zmo6Q6c1G7JB0ig4wSt14qH2t+Vq
ZuarG9cJUp4jej2S+gYyizT43I/wBDil7gWnb/cPAbTfoBE5TKWs0hMoK2nFR8IqRoBeA7flw2pq
jJ482Jx5K6TS1yfGXqAoKt+aeh8wXPth61LcZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
`protect data_block
IJgMK8uk0zQjE3p/HtF207IqNCaZbbPDDYquiXxJUO++gbQ6aQ639uyY/4ibE+dy7fEg2LSFEXEm
9nO0bIA78u1BnVmPqK7DzKjgmRQHAi50b6f/C0ka834ZU+8mZAMPVWQ84ViNpXYiy5T/5BQO0p15
JNWoHLfrRAflYJqmDlKqhfG2eaMFXK3gCG9YpdNxM0MutOLts5IH8XUMQpxTps3DzD7GgNy+/tr6
TjzGQws5uOPhcB5EMhnbcXo+0hVIqEfj81OPJ29j04gYD00lCdbJj7S/qpclw9Chr6mxkF9gu/rI
8bh2fKci4g9bgtBg2sDh6qCxBcvHTlT1zXE2Ifac5N+0CXQrYCCQx+iVhRpH5VkUNjPHTvuMSClk
mvXdY5mrcVX58R3RunlrHHVPVYUO+jPGVK6+SIUzBi4RbSTVyC/kVUnmkbeyqGV0J87zRqUui+2J
Bw3l2vcjDQ2mXz04edafnIIvi/KQVcbxcVRTwcct/vBpAbIWwwR31N6w6pu4ZhPw5AbMCpHKqpIf
7Pud7hdVuKYGOc81/p3ROOlBOm9EBq4u6gxkqy220U8xcEo2LKtarQWpYPO59HbPyQ55lmfc6hTf
kJv/KwX7KCNp/L3kFXOWw+RzNdIw8bnJZL+ChwHU2dehoj8r7paShm3y/SPk1ai9T/XuvVBAyosw
gQeeplzY1s+0GKsQZgWz2DKULFKVWtujszF1XlAThS9dyNWmzJuRbdwEcwmRGHaLZwTXdJLUs5Iw
Y/JFbKrX24LhfcyREKkR2oCb65mUnGJSIK+UDznwRqBLLkKrPK2ae7cMeLD4p60x2TQUYJgc6DEB
DfFVXNUhmwXmI2/fWKgm6ql0pD+/B+V+L2WM+8s/PANNqrPLPkTohTGbKwM4txSFXTuyuPwB3pyj
vn4bTyFCV9thDRMvExq+TaMUj0bVZml0I4LHpKpqpXiHdf465Mq70S5nYgVKxtKU9pKKzJvguTBc
QRvQXCv4+3rfUbrqrKYYNyDxt5/8xTAQ+3Eus72IUg5+4/DHDZbN9peD9bHCrUaAu50ixZ5cTabx
en9m8qfXnkJI2kadfFHVFZbuSwJ7yOV2fXtznO1TelifEAA6cwx8o97k8U4CSdNK/xd0t8GoGj57
qYANUK/34Yrzvg4EMW76raxvxoYeWH4BOvKJk75eqFB8LAvKec5pP+DnaIpmcFoMcJ0Ep+bSBSOs
KGXOjwwv/cmkXVpuaahSIPkBYE7NSGzKT0WgJSmk20TlHklF5ByXNu9O5uYinIJW9srkEJUHcVyK
rRKEpvn8IhH03sIEgWCcnfoF1QOQJXdWpTw3B00mm9yOPtGXSnPJaH5kz2c7KLZhDh+jpUGtTQcS
iOBsmhovWQitqr8nEf1H74Uerfno28g5Pj5HkCK0UHwu2c4GcEV7/ThAx0Fj9fGYo+X0b8nAbj6g
u0/WysyMKjJZdHV0I3R9jMzeqRk9Fh2n6H8ndKT7usyH5XgkPsgcFFth+DrdZ8rCpRP8Q4m4xXPU
sYoVGUnZnyzgMFFf/nrebbTKC9WE1Zg+MSKzRlEi576G4zos4Xz49dQwQZVv8F2WAX4TyjGk6ZOj
a9n35IsjndBHA+jTNztS4gZ4ket406V7lDlsijy2S3lpuIfwJQgjS6lHw36sCEpJWsCkhwnw0yT1
piggx23e0Q9KicjtRT7qzzIe1m+hT1Z5pscHFylq0Qe58KAnr9OPCg1KvHweLd5ygJrEsudTP8ao
iSme5Dxk81nsaVB7k+CXhD99jhujza37okP4mm1bQhNkn4DnPtT8QIkuNM+fonK7hceke5rwWc+n
c+wvemAHNrURFQ30gKgdrXcJz0AaavjC1gQnecL0XHwtDNLoMoK5MalSLZQScFzNEzySUGtfELJz
ZH7lnfW8KtAlpLEcpbDoCOEmVf5qx+fVyl8yB/xZzjT5sPikWhZ0tz43G+0cir8sIbxBRM5cCbUq
HXojXRuRrT5UTs8cxJjCu796xsCER6sZBqlOxKfDdQQB6K6L+R6PfcfU9ycjGbqxMmnJMA8jubfN
Hq0mFi9EeettVXWAXQQq03pVQ5U9D+As7yDBnQSPLfNGWWY3PLbTM7hYX+eDLUgjDVXpNaVPXY+y
Cm9QTItemfnM3jLNbQWAHMOg0D0BIJbffYaiz3Idlsw3mP83tI0o3Vlzul0B8wBSpdDmcWr4TAmb
NGo+6pv5Jd4jqOPE1Q8mugdxMJhp9eqnCD0yhMIRXPPj2cQJ/GBC5u2y3vcYNgdZIK1JCVKUD+Ei
8ugGJZSrCUZtCe+nYmQJ7gTFzpEJmg0y+efWH0xpk8EIabZ/TSoOARKPeMVmhPD+KT2oEmhDHkPi
YkeKELCCgmO2y9iA4NDSNubMJY+IEeCH+0GLLqUIiDcLZc2uSPJyUGMQy3GLa07UTfn6RhE9e9WY
NowAW7YMPQpKzanBr7NWlJjtjEHSzd/nhoUn+4osatCfxH4b65oATLQoBlexE8tNtftM18227gXQ
xPLy0DAPyQiXt24SCvvmX2ey6YC9p9jBOsENQYjGQCCXfbc0WpZ9jnBpadHDreGE3w9sKWbvZbBW
VlFiYsq+bMPdzxxpfLGMlH0T/UgjeRIKeLmSIN4CFI0Dc7Yd+akhCgqy7Zs/67crciK8PNvtGfeI
0xDkwGRrlF927slYIepXc78uZfGaTkntaZAIBP9SDzhRMHnGBykgA42+5+xVNt9RGrWA1ObKst0d
FDoHFjQAoA+LWwX5Luyz/dfK64HWkjMesubA+8bLY5ta6aLMftL16fT9MrTFw2HT2vzEeJQ/QPUo
B1Wl2ZpXG92JSPSV3PrCwyevLKZ04UiauChxwn3nnhyp3zsUNUQFR2OIZXodu3jGQAV9N82HOWwN
P56wWIOfXwbeeKF+/0uj6umh/Ys71oShPU0Sfv2mWTSXI66epsx97eTlrwUuKH+n6Zsid2jX/wJc
fIaGG7UzQCMRvOSdysMmU8lKf0xOlh0ZJ4gSH2c4MIRgtO1dUkCRf+X+0f2CduoRT52JfDIpr1hT
6LtQg2ZAUF4fkj8fugkjGR6qhUXRLSeP4segMTdnIGiGS48FZqWFm4wdFg/9M3OCOQ7LAQhozVHm
JWhW2cxWtyNjC/KxVHZtx7o5SOrUGvTtuoNmJnuK8pk6H6xXX/KV9zEoH8rSpD2XVqVNMkk+6J6h
vbL/JTn+wx+2ZPsApeFJkLiwyh0KlG6gRvwMyotZiznWlU0My4z3tFRmhi64Ey3YyrsXXLxIkvBp
LOYG3GIfnaeMsu4zYPHCYAQCrlOLdpO0QtAG6RJW2tTuV3T/fV++h8PU8hUFFOS0Uarcb9nZ5uXd
2nlfgdllXnvhC4/yljr+xAXzhZsr/XQ+fdCmg8l8R06sUafQODMBZSHy2u6OUNplPK/jT4Dvjarr
yN5mk7oDUqMHugssm+8Abh6Bs2CjzKxRsqn+QoHtWJkPzTZXEoC/VgmieGbSm6aZV3//o47tNM4x
1LDi7oGPZaOUoPTNA6QG1r7O99/p+qCojSsXRXUT84TPRnyFiW45gi5wYcwGEcHeSHs5CEJ06AU7
Oe0xaFtp3HAs+izwkSHZKJrPVkAjt/eV0KO3zbMBy2JOjBZX6hVpatPWYlGp4A1ORXsPQUgpn5D7
qa1TVnT3BZFZW3isLga5w0iPaqMJqX+MjJ0VIDvRRDzm5HlMzLsdfTuFBJkB3Nvq9mLM4DaKXCgr
Wem2bRHRn7NVSOK5ImvF0lzUG0xgG7E3YALhdFnVJUVR0lmeZiz/IbJPfnBxxuFHfJhBOb8WPbQp
aGfzg+FzOYRJQQtovO9Qhr5jhz7bz84dMJehluesDvuXwkevj03Nc5TJALA2568kXP0Jb4pHkQ65
glE+A3iFyf8A5wzIoHGs0vQM6hcOTV6VWnsVQLX4iIiye42eshgImmtk1fdCzKKeuKGaKxf6Yaeq
R1BcP/4TPWkg8kfLGvaNt9aMxu4AU+2JD6pG0cLd6v57DR5pk0h4PnTvhy30tOAt9zg6kvDvI5pM
oHmMz+baJKCrncomrFVE1ZpeXZSeftkLYyc/IyjAV3oqOSy5gYtIqqRSl0wPkkjhNcSqGeUU9mHD
Bj0Z6PgeXyvWP/Gm2c/2TIiG/eBs2/WdTrlp9RQlme1io3042ckN2C1kaVM5zTie1QvXtpUJG9Ms
6WeM+L5UklC3FtZiSjQPypv5RRufFVhqe8DTUEPIp6yj08f20zwgnFMf2Zbd8jBO2WK9NMylDcrE
mSCojeeDcEmUqaimxUYKrJqKBrvMe5JWec+QD3gEEDOF7BJfAyLJ1VsLOcX3iQWSCuJENE6sZ/HL
fCuJDtKj4uxrU64ZSCm2yb+vyIUBKTV+JbhF9qMedZBJI2xUHnkfw9Brt7a3pKMmwta0wRCP4f7s
ofM94+QAhWlvQxbma4DrYLZcgHbWVxEX1P1HXvI91W8jUOdxC5+FLKheXDYktq1yEY2HrvFfiGAg
lXLKPTgV3a/2Q342r9VKRBeJXhSY9R1dvJ0fnb+x04rXG2PWnDwM6BYJPBFGk+7wrfHU/YzRf9G9
0VFXAojz1MpaKybWym61hivEweeslkmAqAv1/aH/zK/0I4+UuUSTbrV+D8o0hloCfp/kM2alrUqZ
GZZC/E+W+0a1uFEJ4tsNyQSNsSoLhtYIrxfQUuY09BjsJoQEPfJBYOWHbv6Kh+uMdP5P0n37GCok
RaxzACfZQs+m8T7W5SpSq6m1cJ19/nAOQK26oaW0u1swrD1oJpRFp9C7TqQ6eYXxw8XJfs319wgX
86U6OS00H9tWZA5/sR17zYUPe6uHaW2hH4OwEqUYQFzCf+t9eLvZJxb0GiTlz/zITa5JPAvoz7QN
V/iMMhhdXgtUnxUvLMfH6C/SVDMJBMmi3By4spwr+89ugCQrsDX4l0x/yHjSoe3nkVpCG3UEfeZF
yNqyW5wwxgbPiLGPEExvJjob+pVrkQR/BdintKv9iK51KxNQuxoKe6/g2t4S0gKPWIZ+49Cmsjfv
Gw7bc2VKda4DnsV/U0EtoYaVRybaYpOqQYSB3jj5PTLq1IJ/Kgpp0UUnFkO5Jc0dHEM/fPEsRlMU
4KTYbzrycQR2QXzEjfpGlQxhFVPCmVVrAUhWR5FKSZhv2zn0huTuCcQhS7If8GxTITRhVi6kr9PF
42X5aZGEotyZLhkvBc2liMsPAGZ3r3inGo87ne8lnPkZFUsaCid+rPJfevNRJGWJBxsxbfUzKyUM
W5JxG5EDKvKAI3QtRlcfrInPttkcU2DS8bamfnd2mHiSQVJM2aeQJl06t8c6sZLslweyxyU9J+PD
xiDtT0CCxrm3/Ahkn+ebVzjjpLafo+G6v0f8yxYtyCuc7IqmWLQmoLriaA2APNNhbMdPIUdqoFcI
uJkjuHj0BNHJCxLnL32x9P31SoocgOGH3Atx7rQBJFufhD8bsQoMmleDcfWXQX/4gmVYL0pUiYkS
ohH2VDkr46zcBZQu6/wzMcFojbyTA3PN3Eoy0LfHmWv8cZeax+dEjjlMm5F0WZkZwjp9fk2gQpRG
C2Zy03E3wsBTcZ5W9PiTE/l4OqIwHp7QXO5J4GBHSVNn/RH0WuaSktAErd4STLpzLn59uj67xi5S
jzbZhzkUz56tVq+IfFiYQEMKg7Zu2hLlE4pfW0zeQCkGmkiIPS/gH4pu8VOmHuiwzQtx+jSpXTE0
wmP1bvoLIBUUjBHEemXE9RCL3P4Uc6/DC9HnOWe/+k7nosunE5Bwhcr2+PL3on7VchGILTeTHq9f
9SF1H8L1aqx2ouBUGDoM0f5iA7FnBJ2APJGtyDBW03s6V9CvFA6yTlSPlbfy4lJNCACnx2WxRV/g
QXudsVBWHbRKmXN/Pu7S+A3sS15XTncgvuPc9JWwP9dP2RZ7p9M5iVz82tth7bqL9OHWwJgy8/IJ
WGcwj59aQOxhjyWCp/w9Ud7S0Q0UweJkIyCSj3+TBawLt7f22blwno3m8amgQFPeFz5dcKrb+Kuz
KmtJNv1rx0xNi5F467DYB4zAqdyD5YQdJrEGkNnQzHIutIaVIg4sIIqzX/HwV5k0Zyqtp1SpLNiS
VF2dJIz1yu/qqqTtfe9XiOBxTMHzG1b3t6ft1VTy+E/seNNd/cysTKXnLsG3YQuNeXKSiS2lbPc3
wvgQBb8aIJIZojfb8/YKepxwWr2P5jbAhkwkMFljDCa9Hu9IMG6DHdOlxB60keNsnvQjvE3MEYPb
/yWLR40PbDk2PR1Gi1t8AyDDAWj0lqOga3L1b4Em6BgF3fZsQHTrhevGHw2UTxj49ZJTLH8gz+7l
6HDOP1VeZGXMN+QiT6SwYUdEsDt+iMVHZ4aQbnp1sbbj+0Ct0DSLQTvy6PpYiMNZ+tc4SkkFKLJp
MkRvGW07tg+E17vcRAb7zO8MwVV/x/Nkz4Q45BYM0wJbj86RxlUjtwUQxFQRCStLajy+bPlUQ5zt
+8qKTNsp6QzTNzFr8YZkX98S/AxA2nImUE9zNQhd0Zr514MWuunrPdNJrSb+YkOAJiAgzou33d35
W1wIs8VssPxhXVgtoognMnXBSFZFMYXkfdajWxKqsOcO1KLvfc+M/+qmH1VwvLvxyCk3dhUe0tVN
a9/Lp2ZamVWOFxAH0WceULOD0UjF8FmrKc2PcIm8lwNwNosHH8yBQNzdK8BorKCakYiB2pOr2I25
HkvODEXteFMSyVYm+CUjHUOEOSlBo6oKWkVtDFkDwMzlRJeBl1X0P6Qroaai08UtDQT1GnSuSFKT
wfbKpNZd3ytBY6CxC5qQlAoGLYTitMZTTMX934vVha9VInHV717ScEo7+87587+Dd3v+33nLG8fX
9MLg6h7L78+xDf1W0i7I/iyRHBzD8LSanLGtc80s6aCaTKFn2AXT3LORU8uOBVUvEHNPwRE16rGg
4+XhjW7jLwIWQLOvc5gYCn6QUzq7Qzm7h/mL3zO4r1fC3WVO7u8Xsygs/DdSFkgp+4VnOXOhK8N4
0WKVVYjjTnVR2o3H/+o5+38vgF0pq3Cc8LGQwUosy3XCcL/EofAU3OKQMYDu58JjpzSpH81IJ4Ow
F1sIFjDcyF3OE3B1Yi8Ze8oXkUefebTQ+U9HzSER0NN+lIHAWTamPcPLjivXrqPvDIgYw8yvt7uR
QOkQZJ4BHD5nGrzt9uH5ttXBDN2YcMXTBkZtgf2h2TNQ6EMsjS01op6DTFc0YQOIz/s9dWdjUKyt
fpVvVr0JHc0lco25bUVVi2gsbH4ItUg2A71KkaMwhfzmtRxSr7L1157ZFlkCu6y5dDV6krZjw3/0
acH+qQ2muEdx7PPhslpqdUSPav5auUNeibm3UYeO9ACjkoXcVKpjO1/7/k1s46oU5Evam/iatBOW
m83sLY9PakGATvnZV3IB/H1s16jTU7+a+KbOFeQQlc2/tQvDEeh4T5IL0TtyIUsFO3Bvcx28SFvV
hBFodESPA/xB5FhOxrodwG/t8wtAd61sJOl1Y0xtUUR9IRIt5lvLk7l+WXGWhxoh3zBV1mhmffob
dqIqIJ7odpSJr19tRCTHi5646OHObUN4xrTlVk07iYvQ9B0qnSrnFei4T/zNNY+c20pMq/Vmll9d
MD3MBWcZA52NmO8mBCoXwwTzz4WwsjT9hA8VVCGJY0VMO21NiygUZ468Ttkgwf1pTFITGYXB6dpA
Cq0FKpuchlto2alH+9rEk7OzhvXIRVA4CpvgFCuFErK2/IbrcaEOHxPrQQ1wCafKlZLClA388QdT
NlXazQ7Y6eYZMONcJooeCCq7RPiPIOtNJPYWRX5ETaa53vDO5svYpeXnDpeZY8f/eHXXO0oKSLQD
k7dt/YH+E/OgtmaTrIMG2Ncc/5kZPlyLjP9BiSdqKsAM1QwwOomcNNBpiD6pB6uCECBFPSuqoKnV
+d+RFATVilVh1LrbqMoyF0UCKtSqXQBmfeNigYKvC0PUqFizs116bsHbovngXwr+/WfmfUs6B2a7
T++HCAXKCc5qRHM6ZKvoQXY7UCFVLbdztFvkjgh9R1ANWzMtlCdSI8gGVSNnhOQSkmylnDSAPxly
KUCWdjARmE9F3yKgf0irRAvQy+dWnmw9Vyuz+hGuKNX7FxAq6O7nd9/5uxtwtPiH/NoQChMBMr4I
ZZQQmvVX54f70CYyynDu6elk/JnqysEabqK9j7QLuYuq6YSDs7RyVX2TvYlayE68nqklHtNjLsPO
XmyPHkjxBgvpevQGntEqvkI4KpO6WhjRc//AcpHHyI93bUeCvyQXaMXbBx9IQRcjlHcWWXOGvYqm
OOHbnjcwkhlLoINw5XKro50059hl53j+jQdoo2imfcoTxK0CzkmmUBgw5nMVEA0xQKr67hGPUORk
w9xVPBDLul5LxiB/1OVdYHLa91KJzkoxFzJbpeywWVbHXK0sMYa2wnkMrsJPW/LAWvWseE/4atjk
RVKbllrqwcZcgYo9HIt04MrzKyB6vtUPOfoOFh5Ez+bE2ybjpnmnAwRJ8vcOEGGqkEjm6GPBzcZY
EFcYEFLESw9VeWNec1Qy6LryLiIHAm1WWoSGGqJxSUvrzlsOf5/DzKgM5SMSYUUzlQ7Q3vCrC9t3
StNzNXA8/jvVJm4WhJHd9PcrmCyRvXjwgdPL0w9/aN1JAh2Q+7bkHMfs+F3tZlYa4yyYfD7di39x
4PG50uE17IhemQbrphDUJNbSG7O/E7zDH+Owj81qQoZJy0H3L2eT9RYgJHpW7sjtaWl9oyjqUT8f
Cc0zTTaQmsx8jIOPes+nb7jNTDJNyhANKb02ka+IEs1IjjxVrpwds6LV7BMyBokvxbfek1ZdMx57
+DjNVxw3oO19ZKohZiyIVehSCMY9HD1F2J6Vd9iQa4mZynmMypgYZgITorvZPe7H11Ik9/XC77l8
XpKns3627s2Vxto0DMRuI9qlTS0y+L1+NIUOM9Q337O5AHo7hQ/S0u3IoambwatNyZ6xx0K8ePPw
5SlRYgZe+TwPlT8E5oYConSElR7O7cgGRMqka2Ch+1+fU71/01A5wJwMpONH6ND+AkdRA9ZCY/Zc
6HEmL4T/Y70RXnwTJQTcUT+Ae8cMuxVtQVdIaU5aq79xXXDzK+5MN2vHVx0fg5arcXDr9FbhP0pO
IJI+CHa2BeoBHG+zXIhFe2dY2dKUzqitJDOjQGiwXOpvXDcVrO/h/2nLxFPv6LPB7QJ1dINlXnUh
ptkZWiaIOwGAvQih5DXdbIt6pMkGwO05r41X2O/Nt/GfI05GFs6Qr1JxXgTOZQQ0lGqgc7dQvBwE
xDpY9BPVCvjgqCUkzXWkCuzRJZ6Dn9rjNH6ACqoACCjoauxI2inISrfU6UZ92xO4xvOwTmJH83LJ
XFjh86h+jNFQuZP8AFh5ZuCTR3a1IvmpAPVfPA/g0ZrY+erTiQeyPPk2QZC5xzSxzuvTwyKQrkcf
9gbTvahPYe3Ck+90yf69OzgfL5/ligINYVN/t2GS8P9qDkJK3hRqs7PCl0MQYDbHXZ+Ao628GDDo
d8jc+wsumrtkGg1dOU5IscG8hRx9nwyt4ZGBRfmh/Fr324DRCSPccRBKTCLYFoGDzgsbbYWbv2N3
jm3CoLbmfgdaT1JuBKYcmBp9jYc3fGexWF6TNmRMkZzwbZeWil3OWOaKWwC1/oMkt/UPQx1IkKXz
PQGCQFpXZStQv7Y0am2K44A5ktjN5CJj8YNnnHbqIyua4XIV3fiyhX3Q3hW6ncdgw9ALksPuUVx9
oDiYFchpW3VVq6pg96Lr0l9K0a6YFrX0EFEQPwYLnoFmYG8Lzz/Y/lJ4iFn7ZFZZFaJM0AnVlZbU
ByHXM6QIxZlm72yGm6rjUN6J7HCZpPxfbiMlYydLYZhkX0ZL/57O6p20yKRKci8OgomGecgtM73O
dP2z7dCCCvjjoGtiiGufTx3qgFvtXdE55vbwfLGYtFG3xDfKBJB6THjRsbEkq95srHspKfbuF7Qe
C25UdI67xibqQA4lTde+33tn4vBA+jYT5GVlgpENctev6F5dupJvEl2JLpMcVkd90wWJi/I2Ofc2
FSKbCnzuAMaIW7yQN+dC3wXXRzk+Fe0uYxCNoqS3qKSeb+q1iY9Nbs1xKdKOhuDG5iqQun+49CF1
62+1w0CfKUF/mZrigKCiPKlLGo2dAjat6O09KejL2jmvoZRtlOmv/nGMWFNgiWnNRiDvCVI+a0VP
fXqsgl80wa7V2O1MiDj+GXG+0PRYjyXc0fQEjHcqjjkuzGnx4XFFCy6lLJ4S5dXU1Cuj8EvcDBrO
KCTaP1DuNZ+2FV2SXzhPnTBoUpH2esg6F+/fzTdohtl4gS2VMiM2X5PP+kQubz8d1VYPAQjLdlnX
A7HSIgnM1EuPblsDIB3dsy/JmlaFcRjm5ECkzQn7hDBwXjon8iYLX4PwOHszvpuQFJMKlyrGd1if
1XwTAO5cN5Z2Nvywc8IXOayAEV7x4r7Dh36JUIjeMNkQIEhSquuNdXhfAT+dqfjv3EjwILzAxTp+
6wL+wO/9f15Ha4SIkVtcxshvLjx69HUGEba/3Ugv51BCeYv6hijIy6HT3Mc3Lhd82WlDQff3i42O
agUWreKu3kplphfGgl8j6kQ7QuB9f7h5+Pj/J2WW0Gni2EzCQafC0oLufA/hUrptLTBnmgM0pbjF
011YQ+oNfQByq2Yuz4xBcPXphfhEfAdd7/7w8K3TZiVrBVN28dFzjJMdhAW+8CUrXlLnSrIfdQ8k
UdN9CxCh0wa9XrfAX6foIjhMbQyY4PDyPCLAEhQP8EfWohx4AyuTHcFE0udq+YTP/fMECXqP1j+L
7FiAuBapWbvVAnrGqfDbjInKlxLdG6hGnG5IO11jykGl5KNt2LmNeD/cbpDqf6CjmDNtfR/lfTa6
+rmMCbSWOs7tS4m5hT2VNKwQtAxUOnhe2F74ckKx/B3fIjMSSqvP7SLXfM/LuPhwKxVr/AQzFpMe
JILkDiJvwkrLDekBP487bSrBoRRfwxONWczbiyDvmtzMj2TwxG8EwskMQRs8Or+UbTEjPnzfbaaT
V5AQR5dzJL2a4AOORTD9aWZKMi5qgWifv5S85EPUdWTBYzLJzJfUFzd+8sj9exs4YQexP3uZkMRv
1ZGS8WHyRITpaaHpaC63Q5zvuGsg3TVCEK0wpK7IQjRL5jQRoi7zUCmoLR946JPJv/0MWlexmMuE
TgcMC74lAsQfnA5FJAj22sZwFbbrN7/d8Y/va795tFB/vznMilVu1MAe+m9DmnVglRp6k8hsR4Cg
mlEIgz7A9rNr2E+7agFXRbggdEx+23QKdPGjRSIGtu9l79mGYwdEACT+06bAM2uT0TRW5OFCpAca
9ofvBEWpbr0RfZPpeYnn0U72wxjh08aUhdCE+rediwp94rz4rt8JRt2TUL/0GUolf4LcyRVNPQq+
kQBxv4kuLTgvWHO8LdLQYpKTZh1lDf9jwHMdWVHMIPerBCJ4f0SweE/IgA5ujRgvpYIMYkefRQPp
w5o1nsDoWjFrt4dhwQmilY9PfR3C7UddujNbqnf0co+fCgFEdeplRtWQ7xhrzaMiGVHfOwkIjfsZ
/N3opNuAjQjjgz7xdzG70EvRH6BxPxkLf6Mf5r/EKJeMdEXKZhhjTAqI+6mG4pPHOtJB8Aa1+/9h
Sj+ZkGWLqFCs0qoL0m7ILvXWFg+0u0rdqi+WmmPIA4aQn/1dVR3Gat280VZaCh5qHOosqiKYeoFm
1SGi18wDe7sTU9R3d/Mm55Pw+a8hbAAX/i5hNKBE6E3HowWmKCDVkuP0OOtSabjUSvkJip16jBLS
q7jOwYRerjgdA+FfkLn/BQlCq+vDndfvXapsNZAzKc2sEvz5zIcA923vwBsNczA7rk/UFs4ZBQa+
ennB4qNprLSLvICbEafO8a3lwnXHSCLZ/s7YlEPrpUOtbMDk9zTFeYzvViaLbbe02rwQocxELEhX
pUJ5169Folp+/BfIjRwNh4NBIdHQRBQRBQBJIZ5Snd7isx4fxX7fwLh9biWSAhz7adCfBqmX0Tgt
ViyBZbwSJ6L3G6As7c0McXjddJe/WZNX8yYiKL+pjEU1IL1WGhVgYhxwcHn9bu5P7H/Pmfkkpb/o
kxmo1tp0iARO5Mgo52ZSCPRAlIIOOGuJtFOPeoFGVkpEuXDu/QA2RLrsaxYKDnrOpIeyfAfsxmRA
hNP/TXegTBvXh86Q13Y5zmM5eYQgf/ihTqj69vBUROqqzrMcBBi13rLGgX3ks8iwrKZqV4y465QR
qv2DmJ/QlVC0wEHUTuPV+YFj+Gj5zvguKEjODOoEE9+6O7EeGrtmMA48efq1e2GGWQoB/xbeMwgV
gfXHeGeXQy+39iAPDc7dOS0h4QiIdkOOZGQYUBTZiG39DAKJZYpxEQfFRm5kZ2PQOYaLyp0sOTWr
JcHWXutXqFS07x2xMLpx+q2lWx+54amQxjZH/UJvg9VOSB9WFH3rpFqmG0aHNj3J/qJYeccMjwdY
7gYOsGnzXt/nLa+IdYq0d7dIg/tKhdBoFYZOMB9x8vtrVVBs+VFEZcDkfYoUoaT7Gep5v+VGwCxz
3LacwjtKpvTHICApTsTj2nXFefC0Twu5Yy3JWIsagNAcPC1EDK+RdJtL7wXPLV0RYIaknliSKjyt
Y+S5i2M8GqNLMSYVWhVufptrGaylja5StK+I5PzTmB+c9stlxHyZuan90I1sHWNueaSjeppCXmcx
c9+4pfz4yW2CP/rD8Bh/Slc0Xh0U9enxnRwgPcBnWxYbxWddCRys1dMMs1CyL5D+AVhXimr4NXLZ
77bEQ7CjfLYIGhO8xEeXTsgawwoQL55RVwW8ozOCITCgFlFkASvytJBEKyAJezDVc9xDL2ZhG402
unvJ+hBKCv3eUPC8NYbgHgdV2iQZzawWZ4HTIfvLTWVZGHEsqvoSZ/p54TUyL4IB+mXOv8ujMMEH
ECGyFc/nZSinYb3pN4d0h2PAVPMoIHtlGOs+9WabVJc5OVy9rEw3FTR+O8qw26v2ivHdhbuc14kj
TxTCdDBPGWXIkRtP1WQ8Gbqc3gAH7h1S9b/ZNGaNsygcyGwMw9ryjyGlBNLNoSXe2wNIhVPd87um
dSgC8kMOvc0RZpxUnt/Tc58WwaCPMwJLnpMsWHjN5bmZPnBw4QyvLRwUwDXMFoBO9p/nmhlrQ1WC
66ERXYR+ePNIUVo7qQjCe5znvZzQHamKIQwBx8HpLt5czLGWsYne5F1BZZpLMTeZr1w+25WKkvXQ
Ox36oPuZs/843cmLxqThPTlustIrTpnPX2lVzCiuutMHB5fLRbAQNoJfIAXZKf5q1CQAkRJYQr7X
YIhvqVmsjD1YMrZGkNOtmZ8kt6YXZUebxZ13M1uE5GE3KXpNHslHIC3B6/TED5HWHrzeZFlnjRlp
3l7jLzhVEmi0bh3ZIxAUZIgzkVDC5JPS0RcfYb66LdE//1gedCY83XGQ7OHFsSn604C3etkGTg16
9KmvwR5yPzXE/uTbyp9XUujcKyu103o/olUGciKN3BDcc4xboZIKt5dgnv7U8askzz8VSP05xiyt
F2YTobyGMZI77fmp37qGs8P83ri9Pf4rETDdtfRh7k1cyfIEkUhNziL8MpGnpyNKezqC6cV4ocuc
0f2HuTwQC9H9VRWiIQ3UrhV1bO9pNYKl7joO838RvqBkvKMbSF6tm0If5wiVBk86d+oTAcaF+skR
S2gPh8UMpj/AzaP9IR4W9dFTWg08BWKY6OS3MhnAzVg7KWabSVoc9y4tkm525G5tu4Tuy3zBvXhB
oQG6c/B/7EX4xp5HEL4mnpr2YJBmlhRBNvuDrKtpdTGQcJtHDRIFdyIiyrwWYLUTsmZXmCDMlZJC
iDiGmHdydRf+feN154Yjjnsz06T0KAOA7cb+uK1jwDT32lnwwL6SZ5eKZvxm3kwVqG/AII6cJX/o
b0/1Y0iun1eimMfY5CROSvhBLSrCLOw0eQ8r9gUbY9ZL96+Bx/xvbyRoLuLXsh4L3WKqy1sE22MC
0LuT62QElGQNifUprNm58Qb6wWxrEyAmEj23xK/cTSz3rb9hDAF8uQ/Nf9LLSZSqBAYit1FiWFkH
FS+Cj2Oi3rPI324apKQHUYQqhgqMVzQ0M3Cgp/UcnjmYFuOe8cOpggooLWUGZ3rAuW1CTg+zWdKn
osArK3DF7xVnD6YksanQheG3SAcpULu9H2i3w+Sep4GMUFNUQ2HbAMgRscEtDuj5o4m0ZVpmWes2
LMSXhHrTfSnxyq3qyXpbZ+efid2fw05FUApNOTGvIiyZfGZscDlRbCxiyQcHoADQBnLBjHxH69ct
s2XtxoPaij7L4ul6McEk0Z1BRcq9AFqU/MXyNQplzOso86mB5mEezGMKj/47EFGGwVRKAdXZ+T4S
iqJXEY7zmVJ3gkSytX9MjaWS7+dCRaos6ohf2BMe7BlTXP5VMUjVZi1+acG59NLpv7mBR6rBWvYv
RFLQR1k9IWYmmeaXJxbzdt3cjQictPKp7EYuCxhs+zsnQJ11vKpkJdn0ZFeZW9JOR05lcrolDeZS
2mVdXJ6/CAO6xrJ7dPFjgc08/tSJNV4T32KcgUh0kOGMMghDklO4IKWepZfnskRNhLNeaArjFeca
h9hNXiGdRLcD2EPZI5fy+VkO+ECzj2tDw7hFFS2HQMeyK1LiljYljWzIVSVL8ADO
`protect end_protected
|
bsd-3-clause
|
fabeaae625402e6476e97b5d2b1896ad
| 0.935067 | 1.88896 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_final.vhd
| 1 | 16,123 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_final is
port (
clock : in std_logic;
I : in std_logic_vector(31 downto 0);
Vactofk : in std_logic_vector(31 downto 0);
Pdashofk : in std_logic_vector(31 downto 0);
Yofk : in std_logic_vector(31 downto 0);
Vactofkplusone : out std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_final;
architecture struct of k_ukf_final is
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_d is
port (
Vactofk : in std_logic_vector(31 downto 0);
Voc : in std_logic_vector(31 downto 0);
clock : in std_logic;
D : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_b is
port (
q : in std_logic_vector(31 downto 0);
A : in std_logic_vector(31 downto 0);
k : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
clock : in std_logic;
B : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Uofk is
port (
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactofk : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
clock : in std_logic;
Uofk : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vactcapofk is
port (
clock : in std_logic;
Vactofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapofk : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_sigma is
port (
clock : in std_logic;
Pdashofk : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
sigma : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vsigactofkofzero is
port (
clock : in std_logic;
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Vsigactofkofzero : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vsigactofkofone is
port (
clock : in std_logic;
Vactcapofkofone : in std_logic_vector(31 downto 0);
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Vsigactofkofone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vsigactofkoftwo is
port (
clock : in std_logic;
Vactcapofkoftwo : in std_logic_vector(31 downto 0);
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vactcapdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Wofmofzero : in std_logic_vector(31 downto 0);
Wofmofone : in std_logic_vector(31 downto 0);
Wofmoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Pdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Q : in std_logic_vector(31 downto 0);
Pdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vrefofkplusone is
port (
clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Yofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_refsigma is
port (
clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
refsigma : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vsigrefofkofall is
port (
clock : in std_logic;
Vrefofkplusone : in std_logic_vector(31 downto 0);
refsigma : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : out std_logic_vector(31 downto 0);
Vsigrefofkofone : out std_logic_vector(31 downto 0);
Vsigrefofkoftwo : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vrefcapofkplusone is
port (
clock : in std_logic;
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
Wofmofzero : in std_logic_vector(31 downto 0);
Wofmofone : in std_logic_vector(31 downto 0);
Wofmoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_PofVrefofVref is
port (
clock : in std_logic;
R : in std_logic_vector(31 downto 0);
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
PofVrefofVref : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_PofVactofVref is
port (
clock : in std_logic;
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
PofVactofVref : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Kofkplusone is
port (
clock : in std_logic;
PofVrefofVrefinv : in std_logic_vector(31 downto 0);
PofVactofVref : in std_logic_vector(31 downto 0);
Kofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vactcapofkplusone is
port (
clock : in std_logic;
Vrefofkplusone : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Pofkplusone is
port (
clock : in std_logic;
Kofkplusone : in std_logic_vector(31 downto 0);
PofVrefofVref : in std_logic_vector(31 downto 0);
Pdashofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_div IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Voc : std_logic_vector(31 downto 0) := "01000001101100000000000000000000";
signal e : std_logic_vector(31 downto 0) := "00100000001111010010000101111011";
signal A : std_logic_vector(31 downto 0) := "00111110011111000101000001001000";
signal k : std_logic_vector(31 downto 0) := "00011001100001011000011000000000";
signal T : std_logic_vector(31 downto 0) := "01000011100101001000000000000000";
signal Isc : std_logic_vector(31 downto 0) := "00111111101001100110011001100110";
signal M : std_logic_vector(31 downto 0) := "00111011000000110001001001101111";
signal N : std_logic_vector(31 downto 0) := "00111111010111011011001111010000";
signal Wofmofzero : std_logic_vector(31 downto 0) := "10111110101010101010101010011111";
signal Wofmofone : std_logic_vector(31 downto 0) := "00111111001010101010101010110000";
signal Wofmoftwo : std_logic_vector(31 downto 0) := "00111111001010101010101010110000";
signal Wofcofzero : std_logic_vector(31 downto 0) := "01000000000110101010101010101100";
signal Wofcofone : std_logic_vector(31 downto 0) := "00111111001010101010101010110000";
signal Wofcoftwo : std_logic_vector(31 downto 0) := "00111111001010101010101010110000";
signal Q : std_logic_vector(31 downto 0) := "00111000110100011011011100010111";
signal R : std_logic_vector(31 downto 0) := "00111100001000111101011100001010";
signal X1 : std_logic_vector(31 downto 0) := "00111111100000000000000000000000";
signal X2,X3,X4,X5,X6,X7,Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11,Z12,Z13,Z14,Z15,Z16,Z17,Z18,Z19 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_d port map
( clock => clock,
Vactofk => Vactofk,
Voc => Voc,
D => Z1);
M2 : k_ukf_b port map
( clock => clock,
q => e,
A => A,
k => k,
T => T,
B => Z2);
M3 : k_ukf_Uofk port map
( clock => clock,
D => Z1,
B => Z2,
I => I,
Isc => Isc,
Vactofk => Vactofk,
Uofk => Z3);
M4 : k_ukf_Vactcapofk port map
( clock => clock,
Vactofk => Vactofk,
M => M,
Uofk => Z3,
Vactcapofk => Z4);
M5 : k_ukf_sigma port map
( clock => clock,
Pdashofk => Pdashofk,
T => N,
sigma => Z5);
M6 : k_ukf_d port map
( clock => clock,
Vactofk => Z4,
Voc => Voc,
D => X3);
M7 : k_ukf_Vsigactofkofzero port map
( clock => clock,
I => I,
Isc => Isc,
Vactcapofk => Z4,
M => M,
D => X3,
B => Z2,
Vsigactofkofzero => Z6);
M8 : k_ukf_add port map
( clock => clock,
dataa => Z4,
datab => Z5,
result => X4);
M9 : k_ukf_d port map
( clock => clock,
Vactofk => X4,
Voc => Voc,
D => X5);
M10 : k_ukf_Vsigactofkofone port map
( clock => clock,
Vactcapofkofone => X4,
I => I,
Isc => Isc,
D => X5,
B => Z2,
M => M,
Vsigactofkofone => Z7);
M11 : k_ukf_sub port map
( clock => clock,
dataa => Z4,
datab => Z5,
result => X6);
M12 : k_ukf_d port map
( clock => clock,
Vactofk => X6,
Voc => Voc,
D => X7);
M13 : k_ukf_Vsigactofkoftwo port map
( clock => clock,
Vactcapofkoftwo => X6,
I => I,
Isc => Isc,
D => X7,
B => Z2,
M => M,
Vsigactofkoftwo => Z8);
M14 : k_ukf_Vactcapdashofkplusone port map
( clock => clock,
Vsigactofkofzero => Z6,
Vsigactofkofone => Z7,
Vsigactofkoftwo => Z8,
Wofmofzero => Wofmofzero,
Wofmofone => Wofmofone,
Wofmoftwo => Wofmoftwo,
Vactcapdashofkplusone => Z9);
M15 : k_ukf_Pdashofkplusone port map
( clock => clock,
Vsigactofkofzero => Z6,
Vsigactofkofone => Z7,
Vsigactofkoftwo => Z8,
Wofcofzero => Wofcofzero,
Wofcofone => Wofcofone,
Wofcoftwo => Wofcoftwo,
Q => Q,
Vactcapdashofkplusone => Z9,
Pdashofkplusone => Z10);
M16 : k_ukf_Vrefofkplusone port map
( clock => clock,
M => M,
Yofk => Yofk,
Vactcapofk => Z4,
Vrefofkplusone => Z11);
M17 : k_ukf_refsigma port map
( clock => clock,
Pdashofkplusone => Z10,
T => N,
refsigma => Z12);
M18 : k_ukf_Vsigrefofkofall port map
( clock => clock,
Vrefofkplusone => Z11,
refsigma => Z12,
Vsigrefofkofzero => Z13,
Vsigrefofkofone => Z14,
Vsigrefofkoftwo => Z15);
M19 : k_ukf_Vrefcapofkplusone port map
( clock => clock,
Vsigrefofkofzero => Z13,
Vsigrefofkofone => Z14,
Vsigrefofkoftwo => Z15,
Wofmofzero => Wofmofzero,
Wofmofone => Wofmofone,
Wofmoftwo => Wofmoftwo,
Vrefcapofkplusone => Z16);
M20 : k_ukf_PofVrefofVref port map
( clock => clock,
R => R,
Wofcofzero => Wofcofzero,
Wofcofone => Wofcofone,
Wofcoftwo => Wofcoftwo,
Vsigrefofkofzero => Z13,
Vsigrefofkofone => Z14,
Vsigrefofkoftwo => Z15,
Vrefcapofkplusone => Z16,
PofVrefofVref => Z17);
M21 : k_ukf_PofVactofVref port map
( clock => clock,
Wofcofzero => Wofcofzero,
Wofcofone => Wofcofone,
Wofcoftwo => Wofcoftwo,
Vsigrefofkofzero => Z13,
Vsigrefofkofone => Z14,
Vsigrefofkoftwo => Z15,
Vrefcapofkplusone => Z16,
Vsigactofkofzero => Z6,
Vsigactofkofone => Z7,
Vsigactofkoftwo => Z8,
Vactcapdashofkplusone => Z9,
PofVactofVref => Z18);
M22 : k_ukf_div port map
( clock => clock,
dataa => X1,
datab => Z17,
result => X2);
M23 : k_ukf_Kofkplusone port map
( clock => clock,
PofVrefofVrefinv => X2,
PofVactofVref => Z18,
Kofkplusone => Z19);
M24 : k_ukf_Vactcapofkplusone port map
( clock => clock,
Vrefofkplusone => Z11,
Vrefcapofkplusone => Z16,
Kofkplusone => Z19,
Vactcapdashofkplusone => Z9,
Vactcapofkplusone => Vactofkplusone);
M25 : k_ukf_Pofkplusone port map
( clock => clock,
Kofkplusone => Z19,
PofVrefofVref => Z17,
Pdashofkplusone => Z10,
Pofkplusone => Pofkplusone);
end struct;
|
gpl-2.0
|
4658cdfc6863eebbe3d682e98f060616
| 0.573901 | 3.628854 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP_Bonus_feu_rouge/L3TP5/fsm_tb.vhd
| 1 | 2,053 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:24 10/03/2014
-- Design Name:
-- Module Name: /home/m1/dubiez/Documents/AEO_TP/TP_Bonus/L3TP5/fsm_tb.vhd
-- Project Name: L3TP5
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fsm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fsm_tb IS
END fsm_tb;
ARCHITECTURE behavior OF fsm_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fsm
PORT(
clk : IN std_logic;
Led_i : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fsm PORT MAP (
clk => clk,
led => led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
157671f2d4f07d13f7b198555370de4c
| 0.59133 | 3.895636 | false | true | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_pcc.vhd
| 4 | 103,940 |
-------------------------------------------------------------------------------
-- axi_datamover_pcc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_pcc.vhd
--
-- Description:
-- This file implements the DataMover Predictive Command Calculator (PCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_pcc is
generic (
C_IS_MM2S : Integer range 0 to 1 := 0;
-- This parameter tells the PCC module if it is a MM2S
-- instance or a S2MM instance.
-- 0 = S2MM Instance
-- 1 = MM2S Instance
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE Aligment output ports
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the used portion of the BTT field
-- of the input command
C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the Indeterminate BTT mode is enabled
C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32;
-- Indicates the Native transfer width to use for all
-- transfer calculations. This will either be the DataMover
-- input Stream width or the AXI4 MMap data width depending
-- on DataMover parameterization.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1
-- Indicates the width of the starting address offset
-- bus passed to Store and Forward functions
);
port (
-- Clock and Reset input ----------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------------
-- Master Command FIFO/Register Interface --------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
--------------------------------------------------------------------------------------
-- Address Channel Controller Interface -----------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
---------------------------------------------------------------------------
-- Data Channel Controller Interface ------------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap data --
-- width). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_drr : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_sequential : Out std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the MM2S DRE --
--
mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the MM2S DRE --
-------------------------------------------------------------------------------------
-- Output flag indicating that a calculation error has occured ----------------------
--
calc_error : Out std_logic; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------------------------
-- Special DRE Controller Interface --------------------------------------------
--
dre2mstr_cmd_ready : In std_logic ; --
-- Indication from the S2MM DRE Controller that it can --
-- accept another command. --
--
mstr2dre_cmd_valid : out std_logic ; --
-- The next command valid indication to the S2MM DRE --
-- Controller. --
--
mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The source (S2MM Stream) alignment for the S2MM DRE --
--
mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; --
-- The destinstion (S2MM MMap) alignment for the S2MM DRE --
--
mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; --
-- The BTT value output to the S2MM DRE. This is needed for --
-- Scatter operations. --
--
mstr2dre_drr : out std_logic ; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : out std_logic ; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2dre_cmd_cmplt : Out std_logic ; --
-- The last child tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : out std_logic ; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
-------------------------------------------------------------------------------------
-- Store and Forward Support Start Offset ---------------------------------------------
--
mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) --
-- Relays the starting address offset for a transfer to the Store and Forward --
-- functions incorporating upsizer/downsizer logic --
---------------------------------------------------------------------------------------
);
end entity axi_datamover_pcc;
architecture implementation of axi_datamover_pcc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declarations -------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 1 =>
temp_dbeat_residue_width := 0;
when 2 =>
temp_dbeat_residue_width := 1;
when 4 =>
temp_dbeat_residue_width := 2;
when 8 =>
temp_dbeat_residue_width := 3;
when 16 =>
temp_dbeat_residue_width := 4;
when 32 =>
temp_dbeat_residue_width := 5;
when 64 =>
temp_dbeat_residue_width := 6;
when others => -- 128-byte transfers
temp_dbeat_residue_width := 7;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_burstcnt_offset
--
-- Function Description:
-- Calculates the bit offset from the residue bits needed to detirmine
-- the load value for the burst counter.
--
-------------------------------------------------------------------
function funct_get_burst_residue_width (max_burst_len : integer) return integer is
Variable temp_burst_residue_width : Integer := 0;
begin
case max_burst_len is
when 256 =>
temp_burst_residue_width := 8;
when 128 =>
temp_burst_residue_width := 7;
when 64 =>
temp_burst_residue_width := 6;
when 32 =>
temp_burst_residue_width := 5;
when 16 =>
temp_burst_residue_width := 4;
when 8 =>
temp_burst_residue_width := 3;
when 4 =>
temp_burst_residue_width := 2;
when others => -- assume 2 dbeats
temp_burst_residue_width := 1;
end case;
Return (temp_burst_residue_width);
end function funct_get_burst_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_axi_size
--
-- Function Description:
-- Calculates the AXI SIZE Qualifier based on the data width.
--
-------------------------------------------------------------------
function func_get_axi_size (native_dwidth : integer) return std_logic_vector is
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Variable temp_size : std_logic_vector(2 downto 0) := (others => '0');
begin
case native_dwidth is
when 8 =>
temp_size := AXI_SIZE_1BYTE;
when 16 =>
temp_size := AXI_SIZE_2BYTE;
when 32 =>
temp_size := AXI_SIZE_4BYTE;
when 64 =>
temp_size := AXI_SIZE_8BYTE;
when 128 =>
temp_size := AXI_SIZE_16BYTE;
when 256 =>
temp_size := AXI_SIZE_32BYTE;
when 512 =>
temp_size := AXI_SIZE_64BYTE;
when others => -- 1024 bit dwidth
temp_size := AXI_SIZE_128BYTE;
end case;
Return (temp_size);
end function func_get_axi_size;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_ls_index
--
-- Function Description:
-- Calculates the Ls index of the Store and Forward
-- starting offset bus based on the User Stream Width.
--
-------------------------------------------------------------------
function funct_get_sf_offset_ls_index (stream_width : integer) return integer is
Variable lvar_temp_ls_index : Integer := 0;
begin
case stream_width is
when 8 =>
lvar_temp_ls_index := 0;
when 16 =>
lvar_temp_ls_index := 1;
when 32 =>
lvar_temp_ls_index := 2;
when 64 =>
lvar_temp_ls_index := 3;
when 128 =>
lvar_temp_ls_index := 4;
when 256 =>
lvar_temp_ls_index := 5;
when 512 =>
lvar_temp_ls_index := 6;
when others => -- 1024
lvar_temp_ls_index := 7;
end case;
Return (lvar_temp_ls_index);
end function funct_get_sf_offset_ls_index;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_BTT_WIDTH : integer := C_BTT_USED;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_DSA_WIDTH : integer := 6;
Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1;
Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
----------------------------------------------------------------------------------------
-- Command calculation constants
Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH);
Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8;
Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN;
Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT;
Constant LEN_WIDTH : integer := 8; -- 8 bits fixed
Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1;
Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN);
Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH;
Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH);
Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH);
Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH;
Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH);
Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH);
Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH);
Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice
Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH;
Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH);
Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH);
Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH;
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH);
Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH);
Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1;
-- Type Declarations --------------------------------------------
type PCC_SM_STATE_TYPE is (
INIT,
WAIT_FOR_CMD,
CALC_1,
CALC_2,
CALC_3,
WAIT_ON_XFER_PUSH,
CHK_IF_DONE,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT;
Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT;
signal sig_sm_halt_ns : std_logic := '0';
signal sig_sm_halt_reg : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns : std_logic := '0';
signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0';
signal sig_sm_pop_input_reg_ns : std_logic := '0';
signal sig_sm_pop_input_reg : std_logic := '0';
signal sig_sm_ld_calc1_reg_ns : std_logic := '0';
signal sig_sm_ld_calc1_reg : std_logic := '0';
signal sig_sm_ld_calc2_reg_ns : std_logic := '0';
signal sig_sm_ld_calc2_reg : std_logic := '0';
signal sig_sm_ld_calc3_reg_ns : std_logic := '0';
signal sig_sm_ld_calc3_reg : std_logic := '0';
signal sig_parent_done : std_logic := '0';
signal sig_ld_xfer_reg : std_logic := '0';
signal sig_ld_xfer_reg_tmp : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
-- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
-- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
-- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
-- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
-- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0');
----------------------------------------------------------------------------------------
-- Burst Buster signals
signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_last_xfer_valid_im1 : std_logic := '0';
signal sig_brst_cnt_eq_zero_im0 : std_logic := '0';
signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0';
signal sig_brst_cnt_eq_one_im0 : std_logic := '0';
signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0';
signal sig_brst_residue_eq_zero : std_logic := '0';
signal sig_brst_residue_eq_zero_reg : std_logic := '0';
signal sig_no_btt_residue_im0 : std_logic := '0';
signal sig_no_btt_residue_ireg1 : std_logic := '0';
signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
-- Input command register
signal sig_push_input_reg : std_logic := '0';
signal sig_pop_input_reg : std_logic := '0';
signal sig_input_burst_type_reg : std_logic := '0';
signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_input_drr_reg : std_logic := '0';
signal sig_input_eof_reg : std_logic := '0';
signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_input_reg_empty : std_logic := '0';
signal sig_input_reg_full : std_logic := '0';
-- Output qualifier Register
-- signal sig_ld_output : std_logic := '0';
signal sig_push_xfer_reg : std_logic := '0';
signal sig_pop_xfer_reg : std_logic := '0';
signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_type_reg : std_logic := '0';
signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000";
signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_drr_reg : std_logic := '0';
signal sig_xfer_eof_reg : std_logic := '0';
signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_is_seq_reg : std_logic := '0';
signal sig_xfer_cmd_cmplt_reg : std_logic := '0';
signal sig_xfer_calc_err_reg : std_logic := '0';
signal sig_xfer_reg_empty : std_logic := '0';
signal sig_xfer_reg_full : std_logic := '0';
-- Address Counter
signal sig_ld_addr_cntr : std_logic := '0';
signal sig_incr_addr_cntr : std_logic := '0';
signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
-- misc
signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_slice : std_logic := '0';
signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000";
signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_drr_slice : std_logic := '0';
signal sig_cmd_eof_slice : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_calc_error_pushed : std_logic := '0';
-- PCC2 stuff
signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_im2 : std_logic := '0';
signal sig_first_xfer_im0 : std_logic := '0';
signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover : std_logic := '0';
signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_btt_lt_b2mbaa_im0 : std_logic := '0';
signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0';
signal sig_btt_eq_b2mbaa_im0 : std_logic := '0';
signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0';
signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0';
-- Unaligned start address support
signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0');
signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_aligned_im0 : std_logic := '0';
signal sig_addr_aligned_ireg1 : std_logic := '0';
-- S2MM DRE Support
signal sig_cmd2dre_valid : std_logic := '0';
signal sig_clr_cmd2dre_valid : std_logic := '0';
signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_dre_eof_reg : std_logic := '0';
-- Long Timing path breakup intermediate registers
signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0');
signal sig_xfer_len_eq_0_ireg3 : std_logic := '0';
signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsh_rollover_im3 : std_logic := '0';
signal sig_mmap_reset_reg : std_logic := '0';
----------------------------------------------------------
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sig_calc_error_reg;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and
sig_input_reg_empty and
not(sig_calc_error_pushed);
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_xfer_tag_reg ;
mstr2addr_addr <= sig_xfer_addr_reg;
mstr2addr_len <= sig_xfer_len_reg ;
mstr2addr_size <= sig_xfer_size ;
mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported
mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported
mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sig_xfer_calc_err_reg;
mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_xfer_tag_reg ;
mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_xfer_len_reg ;
mstr2data_strt_strb <= sig_xfer_strt_strb_reg;
mstr2data_last_strb <= sig_xfer_end_strb_reg ;
mstr2data_drr <= sig_xfer_drr_reg ;
mstr2data_eof <= sig_xfer_eof_reg ;
mstr2data_sequential <= sig_xfer_is_seq_reg ;
mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg;
mstr2data_cmd_valid <= sig_cmd2data_valid ;
mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE
mstr2data_calc_error <= sig_xfer_calc_err_reg ;
-- Assign the DRE Controller Qualifiers
mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE
mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE
mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE
mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE
mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE
mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE
mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MM2S_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the MM2S use case.
--
------------------------------------------------------------
DO_MM2S_CASE : if (C_IS_MM2S = 1) generate
begin
mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
end generate DO_MM2S_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_S2MM_CASE
--
-- If Generate Description:
-- Assigns the auxillary DRE Control Source and Destination
-- ports for the S2MM use case.
--
------------------------------------------------------------
DO_S2MM_CASE : if (C_IS_MM2S = 0) generate
begin
mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE
mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE
end generate DO_S2MM_CASE;
-- Store and Forward Support Start Offset (used by Packer/Unpacker logic)
mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX);
-- Start internal logic.
-- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines)
sig_cmd_user_slice <= cache2mstr_command(7 downto 4);
sig_cmd_cache_slice <= cache2mstr_command(3 downto 0);
sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX);
sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX);
sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX);
-- Check for a zero length BTT (error condition)
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
sig_xfer_size <= SIZE_TO_USE;
-----------------------------------------------------------------
-- Reset fanout control
-----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_REG
--
-- Process Description:
-- Registers the input reset to reduce fanout. This module
-- has a high number of register bits to reset.
--
-------------------------------------------------------------
IMP_RESET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_reset_reg <= mmap_reset;
end if;
end process IMP_RESET_REG;
-----------------------------------------------------------------
-- Input xfer register design
sig_push_input_reg <= not(sig_sm_halt_reg) and
cmd2mstr_cmd_valid and
sig_input_reg_empty and
not(sig_calc_error_reg);
sig_pop_input_reg <= sig_sm_pop_input_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_QUAL
--
-- Process Description:
-- Implements the input command qualifier holding register
--
-------------------------------------------------------------
REG_INPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_input_reg = '1' or
sig_calc_error_pushed = '1') then
sig_input_cache_type_reg <= (others => '0');
sig_input_user_type_reg <= (others => '0');
sig_input_burst_type_reg <= '0';
sig_input_tag_reg <= (others => '0');
sig_input_dsa_reg <= (others => '0');
sig_input_drr_reg <= '0';
sig_input_eof_reg <= '0';
sig_input_reg_empty <= '1';
sig_input_reg_full <= '0';
elsif (sig_push_input_reg = '1') then
sig_input_cache_type_reg <= sig_cmd_cache_slice;
sig_input_user_type_reg <= sig_cmd_user_slice;
sig_input_burst_type_reg <= sig_cmd_type_slice;
sig_input_tag_reg <= sig_cmd_tag_slice;
sig_input_dsa_reg <= sig_cmd_dsa_slice;
sig_input_drr_reg <= sig_cmd_drr_slice;
sig_input_eof_reg <= sig_cmd_eof_slice;
sig_input_reg_empty <= '0';
sig_input_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_QUAL;
----------------------------------------------------------------------
-- Calculation Error Logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_FLOP
--
-- Process Description:
-- Implements the flop for the Calc Error flag, Once set,
-- the flag cannot be cleared until a reset is issued.
--
-------------------------------------------------------------
IMP_CALC_ERROR_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_reg <= '0';
elsif (sig_push_input_reg = '1' and
sig_calc_error_reg = '0') then
sig_calc_error_reg <= sig_btt_is_zero;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CALC_ERROR_PUSHED
--
-- Process Description:
-- Implements the flop for generating a flag indicating the
-- calculation error flag has been pushed to the addr and data
-- controllers.
--
-------------------------------------------------------------
IMP_CALC_ERROR_PUSHED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_calc_error_pushed <= '0';
elsif (sig_push_xfer_reg = '1' and
sig_calc_error_pushed = '0') then
sig_calc_error_pushed <= sig_calc_error_reg;
else
Null; -- hold the current state
end if;
end if;
end process IMP_CALC_ERROR_PUSHED;
---------------------------------------------------------------------
-- Strobe Generator Logic
sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3
When (sig_first_xfer_im0 = '1')
Else (others => '1');
sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3
When (sig_xfer_len_eq_0_ireg3 = '1' and
sig_first_xfer_im0 = '1')
else sig_xfer_end_strb_ireg3
When (sig_last_xfer_valid_im1 = '1')
Else (others => '1');
----------------------------------------------------------
-- Intermediate registers for STBGEN Fmax path
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen inputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_strbgen_addr_ireg2 <= (others => '0');
sig_strbgen_bytes_ireg2 <= (others => '0');
sig_finish_addr_offset_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ;
sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ;
sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_REGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_STBGEN_OUT_REGS
--
-- Process Description:
-- Intermediate registers for Strobegen outputs to break
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_STBGEN_OUT_REGS : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_xfer_strt_strb_ireg3 <= (others => '0');
sig_xfer_end_strb_ireg3 <= (others => '0');
sig_xfer_len_eq_0_ireg3 <= '0';
elsif (sig_sm_ld_calc3_reg = '1') then
sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2;
sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ;
sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_STBGEN_OUT_REGS;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr_ireg2 ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes_ireg2 ,
strb_out => sig_xfer_strt_strb_im2
);
-- The ending address offset is 1 less than the calculated
-- starting address for the next sequential transfer.
sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) -
STRBGEN_ADDR_SLICE_1);
------------------------------------------------------------
-- Instance: I_END_STRB_GEN
--
-- Description:
-- End Strobe generator instance. Generates asserted strobe
-- bits from byte offset 0 to the ending byte offset.
--
------------------------------------------------------------
I_END_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 1 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH
)
port map (
start_addr_offset => STRBGEN_ADDR_0 ,
end_addr_offset => sig_last_addr_offset_im2 ,
num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1
strb_out => sig_xfer_end_strb_im2
);
-----------------------------------------------------------------
-- Output xfer register design
sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty);
-- Data taking xfer after Addr and DRE
sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or
-- Addr taking xfer after Data and DRE
(sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or
-- DRE taking xfer after Data and ADDR
(sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or
-- data and Addr taking xfer after DRE
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or
-- Addr and DRE taking xfer after Data
(sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or
-- Data and DRE taking xfer after Addr
(sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or
-- Addr, Data, and DRE all taking xfer
(sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_OUTPUT_QUAL
--
-- Process Description:
-- Implements the output xfer qualifier holding register
--
-------------------------------------------------------------
REG_OUTPUT_QUAL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
(sig_pop_xfer_reg = '1' and
sig_push_xfer_reg = '0')) then
-- sig_xfer_cache_reg <= (others => '0');
-- sig_xfer_user_reg <= (others => '0');
-- sig_xfer_addr_reg <= (others => '0');
-- sig_xfer_type_reg <= '0';
-- sig_xfer_len_reg <= (others => '0');
-- sig_xfer_tag_reg <= (others => '0');
-- sig_xfer_dsa_reg <= (others => '0');
-- sig_xfer_drr_reg <= '0';
-- sig_xfer_eof_reg <= '0';
-- sig_xfer_strt_strb_reg <= (others => '0');
-- sig_xfer_end_strb_reg <= (others => '0');
-- sig_xfer_is_seq_reg <= '0';
-- sig_xfer_cmd_cmplt_reg <= '0';
-- sig_xfer_calc_err_reg <= '0';
-- sig_xfer_btt_reg <= (others => '0');
-- sig_xfer_dre_eof_reg <= '0';
sig_xfer_reg_empty <= '1';
sig_xfer_reg_full <= '0';
elsif (sig_push_xfer_reg = '1') then
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
-- sig_xfer_addr_reg <= sig_xfer_address_im0 ;
-- end if;
-- sig_xfer_type_reg <= sig_input_burst_type_reg ;
-- sig_xfer_cache_reg <= sig_input_cache_type_reg ;
-- sig_xfer_user_reg <= sig_input_user_type_reg ;
-- sig_xfer_len_reg <= sig_xfer_len_im2 ;
-- sig_xfer_tag_reg <= sig_input_tag_reg ;
-- sig_xfer_dsa_reg <= sig_input_dsa_reg ;
-- sig_xfer_drr_reg <= sig_input_drr_reg and
-- sig_first_xfer_im0 ;
-- sig_xfer_eof_reg <= sig_input_eof_reg and
-- sig_last_xfer_valid_im1 ;
-- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
-- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
-- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
-- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
-- sig_calc_error_reg ;
-- sig_xfer_calc_err_reg <= sig_calc_error_reg ;
-- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
-- sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
sig_xfer_reg_empty <= '0';
sig_xfer_reg_full <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_OUTPUT_QUAL;
-- if (sig_input_burst_type_reg = '0') then
-- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh;
-- else
sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else
sig_addr_cntr_lsh_kh ;
-- end if;
sig_xfer_type_reg <= sig_input_burst_type_reg ;
sig_xfer_cache_reg <= sig_input_cache_type_reg ;
sig_xfer_user_reg <= sig_input_user_type_reg ;
sig_xfer_len_reg <= sig_xfer_len_im2 ;
sig_xfer_tag_reg <= sig_input_tag_reg ;
sig_xfer_dsa_reg <= sig_input_dsa_reg ;
sig_xfer_drr_reg <= sig_input_drr_reg and
sig_first_xfer_im0 ;
sig_xfer_eof_reg <= sig_input_eof_reg and
sig_last_xfer_valid_im1 ;
sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ;
sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ;
sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ;
sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or
sig_calc_error_reg ;
sig_xfer_calc_err_reg <= sig_calc_error_reg ;
sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ;
sig_xfer_dre_eof_reg <= sig_input_eof_reg ;
--------------------------------------------------------------
-- BTT Counter Logic
sig_ld_btt_cntr <= sig_ld_addr_cntr;
-- sig_decr_btt_cntr <= sig_incr_addr_cntr;
-- above signal is using the incr_addr_cntr signal and hence cannot be
-- used if burst type is Fixed
sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR
--
-- Process Description:
-- Bytes to transfer counter implementation.
--
-------------------------------------------------------------
IMP_BTT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_btt_cntr_im0 <= (others => '0');
elsif (sig_ld_btt_cntr = '1') then
sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice);
Elsif (sig_decr_btt_cntr = '1') Then
sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH);
else
null; -- hold current state
end if;
end if;
end process IMP_BTT_CNTR;
-- Convert to logic vector for the S2MM DRE use
-- The DRE will only use this value prior to the first
-- decrement of the BTT Counter. Using this saves a separate
-- BTT register.
sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0);
-- Rip the Burst Count slice from BTT counter value
sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX);
sig_brst_cnt_eq_zero_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_0)
Else '0';
sig_brst_cnt_eq_one_im0 <= '1'
When (sig_burst_cnt_slice_im0 = BRST_CNT_1)
Else '0';
-- Rip the BTT residue field from the BTT counter value
sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0);
-- Check for transfer length residue of zero prior to subtracting 1
sig_no_btt_residue_im0 <= '1'
when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Unaligned address compensation
-- Add the number of starting address offset byte positions to the
-- final byte change value needed to calculate the AXI LEN field
sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0);
sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 +
RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH);
-- adjust the address increment down by 1 byte to compensate
-- for the LEN requirement of being N-1 data beats
sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE;
-- Rip the new transfer length value
sig_xfer_len_im2 <= STD_LOGIC_VECTOR(
RESIZE(
sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto
DBEAT_RESIDUE_WIDTH),
LEN_WIDTH)
);
-- Check to see if the new xfer length is zero (1 data beat)
sig_xfer_len_eq_0_im2 <= '1'
when (sig_xfer_len_im2 = XFER_LEN_ZERO)
Else '0';
-- Check for Last transfer condition
--sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and
sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and
--sig_no_btt_residue_im0 and
sig_no_btt_residue_ireg1 and
-- sig_addr_aligned_im0) or -- always the last databeat case
sig_addr_aligned_ireg1) or -- always the last databeat case
-- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining
((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining
-- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0)));
(sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1)));
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--
-- General Address Counter Logic (applies to any address width of 32 or greater
-- The address counter is divided into 2 16-bit segements for 32-bit address support. As the
-- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit
-- addressing.
--
----------------------------------------------------------------------------------------------------
-- Rip the LS bits of the LS Address Counter for the StrobeGen
-- starting address offset
sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
-- Check if the calcualted address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat
sig_addr_incr_ge_bpdb_im1 <= '1'
When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH))
Else '0';
-- If the calculated address increment (in bytes) is greater than the
-- number of bytes that can be transfered per data beat, then clip the
-- strobegen byte value to the number of bytes per data beat, else use the
-- increment value.
sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1))
when (sig_addr_incr_ge_bpdb_im1 = '1')
else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0));
--------------------------------------------------------------------------
-- Address Counter logic
sig_ld_addr_cntr <= sig_push_input_reg;
-- don't increment address cntr if type is '0' (non-incrementing)
sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and
-- sig_input_burst_type_reg;
sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0);
sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) -
RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH);
sig_addr_aligned_im0 <= '1'
when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0)
Else '0';
-- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less
-- than or equal to the remaining bytes to transfer. If it is, then at least
-- two tranfers have to be scheduled.
sig_btt_lt_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
sig_btt_eq_b2mbaa_im0 <= '1'
when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and
(sig_brst_cnt_eq_zero_im0 = '1'))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_REG1
--
-- Process Description:
-- Intermediate register stage 1 for Address Counter
-- derivative calculations.
--
-------------------------------------------------------------
IMP_IM_REG1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= (others => '0');
sig_addr_aligned_ireg1 <= '0' ;
sig_btt_lt_b2mbaa_ireg1 <= '0' ;
sig_btt_eq_b2mbaa_ireg1 <= '0' ;
sig_brst_cnt_eq_zero_ireg1 <= '0' ;
sig_brst_cnt_eq_one_ireg1 <= '0' ;
sig_no_btt_residue_ireg1 <= '0' ;
elsif (sig_sm_ld_calc1_reg = '1') then
sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ;
sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ;
sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ;
sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ;
sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0;
sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ;
sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ;
else
null; -- hold state
end if;
end if;
end process IMP_IM_REG1;
-- Select the address counter increment value to use
sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH)
--When (sig_btt_lt_b2mbaa_im0 = '1')
When (sig_btt_lt_b2mbaa_ireg1 = '1')
--else sig_bytes_to_mbaa_im0
else sig_bytes_to_mbaa_ireg1
when (sig_first_xfer_im0 = '1')
else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH);
-- calculate the next starting address after the current
-- xfer completes
sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1;
-- Predict next transfer's address offset for the Strobe Generator
sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0));
sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- Determine if an address count lsh rollover is going to occur when
-- jumping to the next starting address by comparing the MS bit of the
-- current address lsh to the MS bit of the predicted address lsh .
-- A transition of a '1' to a '0' is a rollover.
sig_addr_lsh_rollover_im3 <= '1'
when (
(sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and
(sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0')
)
Else '0';
----------------------------------------------------------
-- Intermediate registers for reducing the Address Counter
-- Increment timing path
----------------------------------------------------------
-- calculate the next starting address after the current
-- xfer completes using intermediate register values
sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2;
sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_ADDRINC_REG
--
-- Process Description:
-- Intermediate registers for address counter increment to
-- break long timing paths.
--
-------------------------------------------------------------
IMP_IM_ADDRINC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1;
else
null; -- hold state
end if;
end if;
end process IMP_IM_ADDRINC_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_IM_PREDICT_ADDR_REG
--
-- Process Description:
-- Intermediate register for predicted address to break up
-- long timing paths.
--
-------------------------------------------------------------
IMP_IM_PREDICT_ADDR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_predict_addr_lsh_ireg3 <= (others => '0');
elsif (sig_sm_ld_calc3_reg = '1') then
sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2;
else
null; -- hold state
end if;
end if;
end process IMP_IM_PREDICT_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_ADDR_STUFF
--
-- Process Description:
-- Implements a general register for address counter related
-- things.
--
-------------------------------------------------------------
REG_ADDR_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= (others => '0');
elsif (sig_sm_ld_calc2_reg = '1') then
sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1;
else
null; -- hold state
end if;
end if;
end process REG_ADDR_STUFF;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_LSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_lsh_im0 <= (others => '0');
sig_addr_cntr_lsh_kh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0));
sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice;
Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then
sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3;
else
null; -- hold current state
end if;
end if;
end process IMP_LSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSH_ADDR_CNTR
--
-- Process Description:
-- Least Significant Half Address counter implementation.
--
-------------------------------------------------------------
IMP_MSH_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_addr_cntr_im0_msh <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1') then
sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_MSH_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIRST_XFER_FLOP
--
-- Process Description:
-- Implements the register flop for the first transfer flag.
--
-------------------------------------------------------------
IMP_FIRST_XFER_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_incr_addr_cntr = '1') then
sig_first_xfer_im0 <= '0';
elsif (sig_ld_addr_cntr = '1') then
sig_first_xfer_im0 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIRST_XFER_FLOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_32
--
-- If Generate Description:
-- Implements the Address segment merge logic for the 32-bit
-- address width case. The address counter segments are split
-- into two 16-bit sections to improve Fmax convergence.
--
--
------------------------------------------------------------
GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate
begin
-- Populate the transfer address value by concatonating the
-- address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
end generate GEN_ADDR_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_32_LE_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 32 bits and less than
-- or equal to 48 bits. In this case, an additional counter segment
-- is implemented (segment 3) that is variable width of 1
-- to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and
C_ADDR_WIDTH <= 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
begin
-- Populate the transfer address value by concatonating the
-- 3 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Adress Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter MSH (Segment 2) is at max value and will rollover
-- at the next increment interval for the counter. Registering
-- this signal and using it for the Seg 3 increment logic only
-- works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 counter to go to
-- max and the next increment operation that can bump segment 3.
--
-------------------------------------------------------------
IMP_SEG2_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
end if;
end if;
end process IMP_SEG2_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
end generate GEN_ADDR_GT_32_LE_48;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_GT_48
--
-- If Generate Description:
-- Implements the additional Address Counter logic for the case
-- when the address width is greater than 48 bits and less than
-- or equal to 64. In this case, an additional 2 counter segments
-- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits
-- and segment 4 is variable width of 1 to 16 bits.
--
------------------------------------------------------------
GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate
-- Local constants
Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH;
Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH);
Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1');
Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48;
Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH);
Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47;
Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32;
Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1;
Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48;
-- Local Signals
signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0');
signal lsig_acntr_msh_eq_max : std_logic := '0';
signal lsig_acntr_msh_eq_max_reg : std_logic := '0';
signal lsig_acntr_seg3_eq_max : std_logic := '0';
signal lsig_acntr_seg3_eq_max_reg : std_logic := '0';
signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0');
begin
-- Populate the transfer address value by concatonating the
-- 4 address counter segments
sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) &
STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) &
STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) &
STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0);
-- See if the MSH (Segment 2) of the Address Counter is at a max value
lsig_acntr_msh_eq_max <= '1'
when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX)
Else '0';
-- See if the Segment 3 of the Address Counter is at a max value
lsig_acntr_seg3_eq_max <= '1'
when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG2_3_EQ_MAX_REG
--
-- Process Description:
-- Implements a register for the flag indicating the address
-- counter segments 2 and 3 are at max value and will rollover
-- at the next increment interval for the counter. Registering
-- these signals and using themt for the Seg 3/4 increment logic
-- only works because there is always at least a 1 clock time gap
-- between the increment causing the segment 2 or 3 counter to go
-- to max and the next increment operation.
--
-------------------------------------------------------------
IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_acntr_msh_eq_max_reg <= '0';
lsig_acntr_seg3_eq_max_reg <= '0';
else
lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max;
lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max;
end if;
end if;
end process IMP_SEG2_3_EQ_MAX_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG3_ADDR_CNTR
--
-- Process Description:
-- Segment 3 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG3_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg3_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto
SEG3_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1') then
lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG3_ADDR_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEG4_ADDR_CNTR
--
-- Process Description:
-- Segment 4 of the Address counter implementation.
--
-------------------------------------------------------------
IMP_SEG4_ADDR_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
lsig_seg4_addr_cntr <= (others => '0');
elsif (sig_ld_addr_cntr = '1') then
lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto
SEG4_ADDR_RIP_LS_INDEX));
Elsif (sig_incr_addr_cntr = '1' and
sig_addr_lsh_rollover_im3 = '1' and
lsig_acntr_msh_eq_max_reg = '1' and
lsig_acntr_seg3_eq_max_reg = '1') then
lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE;
else
null; -- hold current state
end if;
end if;
end process IMP_SEG4_ADDR_CNTR;
end generate GEN_ADDR_GT_48;
-- Addr and data Cntlr FIFO interface handshake logic ------------------------------
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DRE_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Valid control
-- to the DRE Module (S2MM DRE Only).
--
-- Note that the S2MM DRE only needs to be loaded with a command
-- for each parent command, not every child command.
--
-------------------------------------------------------------
CMD2DRE_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_clr_cmd2dre_valid = '1') then
sig_cmd2dre_valid <= '0';
elsif (sig_sm_ld_xfer_reg_ns = '1' and
sig_first_xfer_im0 = '1') then
sig_cmd2dre_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DRE_VALID_FLOP;
-------------------------------------------------------------------------
-- PCC State machine Logic
-------------------------------------------------------------
-- Combinational Process
--
-- Label: PCC_SM_COMBINATIONAL
--
-- Process Description:
-- PCC State Machine combinational implementation
--
-------------------------------------------------------------
PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state ,
sig_parent_done ,
sig_push_input_reg ,
sig_pop_xfer_reg ,
sig_calc_error_pushed)
begin
-- SM Defaults
sig_pcc_sm_state_ns <= INIT;
sig_sm_halt_ns <= '0';
sig_sm_ld_xfer_reg_ns <= '0';
sig_sm_pop_input_reg_ns <= '0';
sig_sm_ld_calc1_reg_ns <= '0';
sig_sm_ld_calc2_reg_ns <= '0';
sig_sm_ld_calc3_reg_ns <= '0';
case sig_pcc_sm_state is
--------------------------------------------
when INIT =>
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_halt_ns <= '1';
--------------------------------------------
when WAIT_FOR_CMD =>
If (sig_push_input_reg = '1') Then
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
else
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
End if;
--------------------------------------------
when CALC_1 =>
sig_pcc_sm_state_ns <= CALC_2;
sig_sm_ld_calc2_reg_ns <= '1';
--------------------------------------------
when CALC_2 =>
sig_pcc_sm_state_ns <= CALC_3;
sig_sm_ld_calc3_reg_ns <= '1';
--------------------------------------------
when CALC_3 =>
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
sig_sm_ld_xfer_reg_ns <= '1';
--------------------------------------------
when WAIT_ON_XFER_PUSH =>
if (sig_pop_xfer_reg = '1') then
sig_pcc_sm_state_ns <= CHK_IF_DONE;
else -- wait until output register is loaded
sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH;
end if;
--------------------------------------------
when CHK_IF_DONE =>
If (sig_calc_error_pushed = '1') then -- Internal error, go to trap
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
elsif (sig_parent_done = '1') Then -- done with parent command
sig_pcc_sm_state_ns <= WAIT_FOR_CMD;
sig_sm_pop_input_reg_ns <= '1';
else -- Still breaking up parent command
sig_pcc_sm_state_ns <= CALC_1;
sig_sm_ld_calc1_reg_ns <= '1';
end if;
--------------------------------------------
when ERROR_TRAP =>
sig_pcc_sm_state_ns <= ERROR_TRAP;
sig_sm_halt_ns <= '1';
--------------------------------------------
when others =>
sig_pcc_sm_state_ns <= INIT;
end case;
end process PCC_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PCC_SM_REGISTERED
--
-- Process Description:
-- PCC State Machine registered implementation
--
-------------------------------------------------------------
PCC_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1') then
sig_pcc_sm_state <= INIT;
sig_sm_halt_reg <= '1' ;
sig_sm_pop_input_reg <= '0' ;
sig_sm_ld_calc1_reg <= '0' ;
sig_sm_ld_calc2_reg <= '0' ;
sig_sm_ld_calc3_reg <= '0' ;
else
sig_pcc_sm_state <= sig_pcc_sm_state_ns ;
sig_sm_halt_reg <= sig_sm_halt_ns ;
sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns;
sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ;
sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ;
sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ;
end if;
end if;
end process PCC_SM_REGISTERED;
------------------------------------------------------------------
-- Transfer Register Load Enable logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_XFER_REG_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
LD_XFER_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_xfer_reg = '1') then
sig_ld_xfer_reg <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP;
LD_XFER_REG_FLOP1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_pop_xfer_reg = '1') then
sig_ld_xfer_reg_tmp <= '0';
Elsif (sig_sm_ld_xfer_reg_ns = '1') Then
sig_ld_xfer_reg_tmp <= '1';
else
null; -- hold current state
end if;
end if;
end process LD_XFER_REG_FLOP1;
------------------------------------------------------------------
-- Parent Done flag logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: PARENT_DONE_FLOP
--
-- Process Description:
-- Sample and Hold FLOP for signaling a load of the output
-- xfer register.
--
-------------------------------------------------------------
PARENT_DONE_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_mmap_reset_reg = '1' or
sig_push_input_reg = '1') then
sig_parent_done <= '0';
Elsif (sig_ld_xfer_reg_tmp = '1') Then
sig_parent_done <= sig_last_xfer_valid_im1;
else
null; -- hold current state
end if;
end if;
end process PARENT_DONE_FLOP;
end implementation;
|
bsd-3-clause
|
263573c3b69b93d938dc2ef587bb73cb
| 0.456523 | 4.283006 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/TX_FIFO/sim/TX_FIFO.vhd
| 1 | 34,855 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY TX_FIFO IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END TX_FIFO;
ARCHITECTURE TX_FIFO_arch OF TX_FIFO IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF TX_FIFO_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 1,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 1,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 1,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 1,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 41,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => s_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser => m_axis_tuser,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_overflow => axis_overflow,
axis_underflow => axis_underflow
);
END TX_FIFO_arch;
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bsd-3-clause
|
fbb539e0afb4c6eb7b3db35d5ce21e82
| 0.611046 | 3.067412 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_gpio_pack.vhd
| 1 | 2,983 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's GPIO Core. Please refer to the documentation
--! in plasoc_gpio.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_gpio_pack is
constant default_data_in_width : integer := 16;
constant default_data_out_width : integer := 16;
constant default_axi_control_offset : integer := 0;
constant default_axi_control_enable_bit_loc : integer := 0;
constant default_axi_control_ack_bit_loc : integer := 1;
constant default_axi_data_in_offset : integer := 4;
constant default_axi_data_out_offset : integer := 8;
constant axi_resp_okay : std_logic_vector := "00";
component plasoc_gpio is
generic (
data_in_width : integer := default_data_in_width;
data_out_width : integer := default_data_out_width;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_control_offset : integer := default_axi_control_offset;
axi_control_enable_bit_loc : integer := default_axi_control_enable_bit_loc;
axi_control_ack_bit_loc : integer := default_axi_control_ack_bit_loc;
axi_data_in_offset : integer := default_axi_data_in_offset;
axi_data_out_offset : integer := default_axi_data_out_offset
);
port (
aclk : in std_logic;
aresetn : in std_logic;
data_in : in std_logic_vector(data_in_width-1 downto 0);
data_out : out std_logic_vector(data_out_width-1 downto 0);
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
int : out std_logic);
end component;
end;
|
mit
|
3d3bdfc2ce3b6efa17535c6c5d08733a
| 0.564868 | 3.879064 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_Roulette/ipcore_dir/timer/example_design/timer_exdes.vhd
| 1 | 5,154 |
-- file: timer_exdes.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity timer_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end timer_exdes;
architecture xilinx of timer_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
component timer is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : timer
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2));
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen)) begin
if (rising_edge(clk(count_gen))) then
if (reset_int = '1') then
counter(count_gen) <= (others => '0') after TCQ;
else
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
|
gpl-2.0
|
3bc0001210e715976fd827b11e2a9bbe
| 0.630384 | 4.298582 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/TX_FIFO/synth/TX_FIFO.vhd
| 1 | 39,959 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY TX_FIFO IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END TX_FIFO;
ARCHITECTURE TX_FIFO_arch OF TX_FIFO IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF TX_FIFO_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF TX_FIFO_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF TX_FIFO_arch : ARCHITECTURE IS "TX_FIFO,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF TX_FIFO_arch: ARCHITECTURE IS "TX_FIFO,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=1,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=1,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=1,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=1,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=41,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 1,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 1,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 1,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 1,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 41,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => s_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser => m_axis_tuser,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_overflow => axis_overflow,
axis_underflow => axis_underflow
);
END TX_FIFO_arch;
|
bsd-3-clause
|
d1e7efd8f3b71563fa5f01ddf95f6df4
| 0.630596 | 2.916502 | false | false | false | false |
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