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AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/pass_through_bram.vhd
| 1 | 5,031 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: Pass-through filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter passes the video signals from input to output.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Pass-through architecture
architecture Behavioral of Video_Box is
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
type ram_type is array (2**(C_S_AXI_ADDR_WIDTH-ADDR_LSB)-1 downto 0)
of std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal ram: ram_type:= (
others => (others =>'0'));
begin
--the user can edit the rgb values here
USER_LOGIC <= RGB_IN_reg;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
ram(to_integer(unsigned(loc_addr))) <= S_AXI_WDATA;
end if;
end if;
end process;
reg_data_out <= ram(to_integer(unsigned(axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB))));
end Behavioral;
--End Pass-through architecture
|
bsd-3-clause
|
37957a2e03303698f9157cff68183d80
| 0.623932 | 3.119033 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_mem_reader.vhd
| 1 | 2,463 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mem_reader IS
END tb_mem_reader;
ARCHITECTURE behavior OF tb_mem_reader IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mem_reader
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FrameLen : IN std_logic_vector(10 downto 0);
FrameIval : IN std_logic_vector(27 downto 0);
BusPkt : OUT std_logic;
BusData : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal FrameLen : std_logic_vector(10 downto 0) := (others => '0');
signal FrameIval : std_logic_vector(27 downto 0) := (others => '0');
--Outputs
signal BusPkt : std_logic;
signal BusData : std_logic_vector(7 downto 0);
signal Clk_o : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
Clk_o <= transport Clk after 8 ns;
-- Instantiate the Unit Under Test (UUT)
uut: mem_reader PORT MAP (
Clk => Clk,
Rst => Rst,
FrameLen => FrameLen,
FrameIval => FrameIval,
BusPkt => BusPkt,
BusData => BusData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
FrameLen <= b"000" & X"4c";
FrameIval <= ( 7 => '1', others => '0' );
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
db9bcdf814ccd79545539bbe188eb68b
| 0.630532 | 3.648889 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/generic_async_fifo_wrapper.vhd
| 1 | 9,289 |
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Generic asynchronous FIFO wrapper
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: generic_async_fifo (generic_async_fifo_wrapper.vhd)
--
-- author: Matthieu Cattin ([email protected])
--
-- date: 05-12-2011
--
-- version: 1.0
--
-- description: Wrapper to use Xilinx Coregen FIFOs instead of generic FIFOs
-- from Generics RAMs and FIFOs collection.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library work;
use work.wshexp_core_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component fifo_32x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_32x512;
component fifo_64x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_64x512;
component fifo_96x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(95 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(95 downto 0);
full : out std_logic;
empty : out std_logic;
--valid : out std_logic;
prog_full : out std_logic);
end component fifo_96x512;
component fifo_128x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(127 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(127 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_128x512;
signal rst : std_logic;
begin
-- Active high reset for FIFOs
rst <= not(rst_n_i);
-- Assign unused outputs
wr_empty_o <= '0';
wr_almost_empty_o <= '0';
wr_count_o <= (others => '0');
rd_full_o <= '0';
rd_almost_full_o <= '0';
rd_almost_empty_o <= '0';
rd_count_o <= (others => '0');
gen_fifo_32bit : if g_data_width = 32 generate
cmp_fifo_32x512 : fifo_32x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 10)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_32bit;
gen_fifo_64bit : if g_data_width = 64 generate
cmp_fifo_64x512 : fifo_64x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
--valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_64bit;
gen_fifo_96bit : if g_data_width = 96 generate
cmp_fifo_96x512 : fifo_96x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
--valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_96bit;
gen_fifo_128bit : if g_data_width = 128 generate
cmp_fifo_128x512 : fifo_128x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_128bit;
end syn;
|
gpl-3.0
|
701e7925b8e29e8f3c4180e91e252cde
| 0.451717 | 3.762252 | false | false | false | false |
metaspace/ghdl_extra
|
lfsr4/BIST_addsub.vhdl
| 1 | 3,484 |
-- file : BIST_addsub.vhdl
-- version : jeu. nov. 4 00:49:28 CET 2010
-- this file implements a combinatorial unit, injects a fault and compares
-- the result with a reference unit.
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BIST_addsub is
end BIST_addsub;
architecture BIST of BIST_addsub is
signal result, clk, reset : std_ulogic;
signal operandes : std_ulogic_vector(66 downto 1);
signal result_dut, result_ref : std_ulogic_vector(33 downto 1);
begin
-- the test vector generator
lfsr : entity work.lfsr4
generic map(size => 66)
port map (
clk => clk,
reset => reset,
lfsr => operandes);
-- operandes(1) : add/substract
-- operandes(2) : carry in
-- operandes(34 downto 3) : substractend
-- operandes(66 downto 35) : addend
-- reference add/sub unit
reference: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
-- A-B = A+(-B) = A+(not B + 1) :
if (operandes(1) = '1') then
substractend := not substractend;
end if;
-- calcule l'addition avec les retenues
res := unsigned(addend) + unsigned(substractend);
-- écrit la retenue sortante mais pas entrante
result_ref <= std_ulogic_vector(res(34 downto 2));
end process;
-- add/sub with a fault
faulty: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
if (operandes(1) = '1') then
substractend := not substractend;
end if;
res := unsigned(addend) + unsigned(substractend);
-- fault injection :
if (operandes(34 downto 28) = "0110110") then
res(33) := '1';
end if;
result_dut <= std_ulogic_vector(res(34 downto 2));
end process;
process
function sulv2txt(s : std_ulogic_vector) return string is
variable t : string(s'range);
variable u : string(3 downto 1);
begin
for i in s'range loop
u := std_ulogic'image(s(i));
t(i) := u(2);
end loop;
return t;
end sulv2txt;
variable r : std_ulogic_vector(33 downto 1);
begin
clk <= '0';
reset <= '1';
wait for 1 ns;
reset <= '0';
for i in 1 to 100000 loop
clk <= '1'; wait for 1 ns;
clk <= '0'; wait for 1 ns;
r := result_ref xor result_dut;
if (r /= (33 downto 1=>'0')) then
report integer'image(i) & " : " & sulv2txt(operandes) & " - " & sulv2txt(r);
end if;
end loop;
wait;
end process;
end BIST;
|
gpl-3.0
|
54e76e102fff2a82aecae8f7d5f62cc3
| 0.638243 | 3.666316 | false | false | false | false |
metaspace/ghdl_extra
|
fb/lissajous.vhdl
| 1 | 1,793 |
-- file : lissajous.vhdl
-- created by Yann Guidon / ygdes.com
-- version 2010/06/05
-- lissajous.vhdl : example program for the use of the framebuffer package
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library work;
use work.fb_ghdl.all;
library ieee;
use ieee.math_real.all;
entity lissajous is
end lissajous;
architecture courbes of lissajous is
signal x,y : integer := 0;
begin
process -- generateur x
variable accumulateur: real := 0.0;
begin
wait for 10000 ns;
accumulateur := accumulateur + 0.001;
x <= integer(real(fbx-1) * (0.5+ (0.5*sin(accumulateur))));
end process;
process -- generateur y
variable accumulateur: real := 0.0;
begin
wait for 4141 ns;
accumulateur := accumulateur + 0.001;
y <= integer(real(fby-1) * (0.5+(0.5*cos(accumulateur))));
end process;
-- affiche le point quand une coordonnee change
process(x,y)
variable couleur : integer := -1;
begin
pixel(y,x) := couleur;
couleur := couleur-1;
-- backup
if (couleur=-3500000) then
save_pixels("lissajous.raw24");
assert false severity failure;
end if;
end process;
end courbes;
|
gpl-3.0
|
aa360ab89292f6f374133bd7c915afb2
| 0.692694 | 3.550495 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Multiplier.vhd
| 1 | 3,786 |
------------------------------------------------------
------------------------------------------------------
-- Description: --
-- Implementation of a simple multiplier --
-- --
-- Generics: --
-- X_WIDTH - Width of the input x --
-- X_FRACTION - Width of the fractional part of x --
-- Y_WIDTH - Width of the input y --
-- Y_FRACTION - Width of the fractional part of y --
-- S_WIDTH - Desired width of the output s --
-- S_FRACTION - Desired width of the fractional --
-- part of s --
-- --
-- Input/Output: --
-- x - First factor --
-- y - Second factor --
-- s - Product --
-- --
------------------------------------------------------
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier is
generic (X_WIDTH : natural := 16;
X_FRACTION : natural := 14;
Y_WIDTH : natural := 16;
Y_FRACTION : natural := 14;
S_WIDTH : natural := 16;
S_FRACTION : natural := 13);
port(x : in std_logic_vector(X_WIDTH-1 downto 0);
y : in std_logic_vector(Y_WIDTH-1 downto 0);
s : out std_logic_vector(S_WIDTH-1 downto 0));
end Multiplier;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Multiplier is
-- Functions -----------------------------------------------------------------
function paddedLength(old_width : integer ;upper_limit : integer) return integer is
begin
if(upper_limit > old_width) then
return upper_limit;
else
return old_width;
end if;
end paddedLength;
-- Constants -----------------------------------------------------------------
constant UPPER_LIMIT : integer := X_FRACTION+Y_FRACTION-S_FRACTION+S_WIDTH-1;
constant LOWER_LIMIT : integer := X_FRACTION+Y_FRACTION-S_FRACTION;
constant X_LENGTH : integer := paddedLength(X_WIDTH, UPPER_LIMIT);
constant Y_LENGTH : integer := paddedLength(Y_WIDTH, UPPER_LIMIT);
-- Signals -------------------------------------------------------------------
signal x_padded : std_logic_vector(X_LENGTH-1 downto 0);
signal y_padded : std_logic_vector(Y_LENGTH-1 downto 0);
signal product : std_logic_vector(X_LENGTH + Y_LENGTH - 1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Fill upper bits if necessary
x_padder:
if(UPPER_LIMIT > X_WIDTH) generate
x_padded(UPPER_LIMIT-1 downto X_WIDTH) <= (others => x(X_WIDTH-1));
end generate x_padder;
y_padder:
if(UPPER_LIMIT > Y_WIDTH) generate
y_padded(UPPER_LIMIT-1 downto Y_WIDTH) <= (others => y(Y_WIDTH-1));
end generate y_padder;
-- Put the input onto the multiplier
x_padded(X_WIDTH-1 downto 0) <= x;
y_padded(Y_WIDTH-1 downto 0) <= y;
-- Multiply and cast result into appropriate size
product <= std_logic_vector(signed(x_padded) * signed(y_padded));
s <= product(UPPER_LIMIT downto LOWER_LIMIT);
end architecture;
|
mit
|
3c713109d2ec221b971c641b23caef24
| 0.41046 | 4.936115 | false | false | false | false |
cretingame/Yarr-fw
|
syn/spec/top_yarr_spec.vhd
| 1 | 47,236 |
--------------------------------------------
-- Project: YARR
-- Author: Timon Heim ([email protected])
-- Description: Top module for YARR on SPEC
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity yarr is
generic (
g_TX_CHANNELS : integer := 4;
g_RX_CHANNELS : integer := 16
);
port
(
-- On board 20MHz oscillator
clk20_vcxo_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n : out std_logic; -- 25MHz VCXO
pll20dac_sync_n : out std_logic; -- 20MHz VCXO
plldac_din : out std_logic;
plldac_sclk : out std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
clk_125m_pllref_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- DDR3
DDR3_CAS_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_RZQ : inout std_logic;
DDR3_ZIO : inout std_logic;
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_DQ : inout std_logic_vector(15 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
-- Trigger input
ext_trig : out std_logic;
-- LVDS buffer
pwdn_l : out std_logic_vector(2 downto 0);
-- FE-I4
fe_clk_p : out std_logic_vector(g_TX_CHANNELS-1 downto 0);
fe_clk_n : out std_logic_vector(g_TX_CHANNELS-1 downto 0);
fe_cmd_p : out std_logic_vector(g_TX_CHANNELS-1 downto 0);
fe_cmd_n : out std_logic_vector(g_TX_CHANNELS-1 downto 0);
fe_data_p : in std_logic_vector(g_RX_CHANNELS-1 downto 0);
fe_data_n : in std_logic_vector(g_RX_CHANNELS-1 downto 0);
-- I2c
sda : inout std_logic;
scl : inout std_logic
);
end yarr;
architecture rtl of yarr is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component gn4124_core
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic;
csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
dma_err_i : in std_logic;
dma_rty_i : in std_logic;
dma_int_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := g_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := g_RX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_dat_i : in std_logic_vector(31 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(31 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component ddr3_ctrl
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock, control and status
----------------------------------------------------------------------------
--! Clock input
clk_i : in std_logic;
--! Reset input (active low)
rst_n_i : in std_logic;
--! Status output
status_o : out std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 0
----------------------------------------------------------------------------
--! Command FIFO empty
p0_cmd_empty_o : out std_logic;
--! Command FIFO full
p0_cmd_full_o : out std_logic;
--! Read FIFO full
p0_rd_full_o : out std_logic;
--! Read FIFO empty
p0_rd_empty_o : out std_logic;
--! Read FIFO count
p0_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p0_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p0_rd_error_o : out std_logic;
--! Write FIFO full
p0_wr_full_o : out std_logic;
--! Write FIFO empty
p0_wr_empty_o : out std_logic;
--! Write FIFO count
p0_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p0_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p0_wr_error_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 1
----------------------------------------------------------------------------
--! Command FIFO empty
p1_cmd_empty_o : out std_logic;
--! Command FIFO full
p1_cmd_full_o : out std_logic;
--! Read FIFO full
p1_rd_full_o : out std_logic;
--! Read FIFO empty
p1_rd_empty_o : out std_logic;
--! Read FIFO count
p1_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p1_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p1_rd_error_o : out std_logic;
--! Write FIFO full
p1_wr_full_o : out std_logic;
--! Write FIFO empty
p1_wr_empty_o : out std_logic;
--! Write FIFO count
p1_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p1_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p1_wr_error_o : out std_logic
);
end component ddr3_ctrl;
component clk_gen
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component ila_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave
constant c_TX_CHANNELS : integer := g_TX_CHANNELS;
constant c_RX_CHANNELS : integer := g_RX_CHANNELS;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk : std_logic;
-- IO clocks
signal CLK_40 : std_logic;
signal CLK_80 : std_logic;
signal CLK_125 : std_logic;
signal CLK_160 : std_logic;
signal CLK_640 : std_logic;
signal CLK_40_buf : std_logic;
signal CLK_80_buf : std_logic;
signal CLK_160_buf : std_logic;
signal CLK_640_buf : std_logic;
signal ioclk_fb : std_logic;
-- System clock generation
signal sys_clk_in : std_logic;
signal sys_clk_40_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_40 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
signal locked : std_logic;
signal locked_v : std_logic_vector(1 downto 0);
signal rst_n : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0');
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal ram_we : std_logic;
-- DMAbus RX bridge
signal rx_dma_adr : std_logic_vector(31 downto 0);
signal rx_dma_dat_o : std_logic_vector(31 downto 0);
signal rx_dma_dat_i : std_logic_vector(31 downto 0);
signal rx_dma_cyc : std_logic;
signal rx_dma_stb : std_logic;
signal rx_dma_we : std_logic;
signal rx_dma_ack : std_logic;
signal rx_dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_out : std_logic;
-- CSR whisbone slaves for test
signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-- I2C
signal scl_t : std_logic;
signal sda_t : std_logic;
-- FOR TESTS
signal debug : std_logic_vector(31 downto 0);
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_k2000 : unsigned(2 downto 0);
signal led_pps : std_logic;
signal leds : std_logic_vector(3 downto 0);
-- ILA
signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal debug_dma : std_logic_vector(31 downto 0);
signal ddr_status : std_logic_vector(31 downto 0);
signal gn4124_core_Status : std_logic_vector(31 downto 0);
signal tx_data_o : std_logic_vector(0 downto 0);
signal trig_pulse : std_logic;
signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0);
signal rx_data : std_logic_vector(31 downto 0);
signal rx_valid : std_logic;
signal rx_busy : std_logic;
begin
-- Activate LVDS buffer
pwdn_l <= (others => '1');
-- Differential buffers
tx_loop: for I in 0 to c_TX_CHANNELS-1 generate
begin
tx_buf : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => fe_cmd_p(I), -- Diff_p output (connect directly to top-level port)
OB => fe_cmd_n(I), -- Diff_n output (connect directly to top-level port)
I => fe_cmd_o(I) -- Buffer input
);
clk_buf : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => fe_clk_p(I), -- Diff_p output (connect directly to top-level port)
OB => fe_clk_n(I), -- Diff_n output (connect directly to top-level port)
I => fe_clk_o(I) -- Buffer input
);
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => fe_clk_o(I), -- 1-bit output data
C0 => clk_40, -- 1-bit clock input
C1 => not clk_40, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => not rst_n, -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
rx_loop: for I in 0 to c_RX_CHANNELS-1 generate
begin
rx_buf : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => fe_data_i(I), -- Buffer output
I => fe_data_p(I), -- Diff_p buffer input (connect directly to top-level port)
IB => fe_data_n(I) -- Diff_n buffer input (connect directly to top-level port)
);
end generate;
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
IBUFGDS_gn_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DIFF_SSTL18_I"
)
port map (
O => l_clk, -- Clock buffer output
I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS_pll_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25"
)
port map (
O => CLK_125, -- Clock buffer output
I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => rst_n,
status_o => gn4124_core_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_out,
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall,
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0'
);
GPIO(0) <= irq_out;
GPIO(1) <= '0';
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk,
rst_n_i => rst_n,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
------------------------------------------------------------------------------
-- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-- port map(
-- rst_n_i => rst_n,
-- wb_clk_i => sys_clk,
-- wb_addr_i => wb_adr(1 downto 0),
-- wb_data_i => wb_dat_o,
-- wb_data_o => wb_dat_i(63 downto 32),
-- wb_cyc_i => wb_cyc(1),
-- wb_sel_i => wb_sel,
-- wb_stb_i => wb_stb,
-- wb_we_i => wb_we,
-- wb_ack_o => wb_ack(1),
-- dummy_stat_reg_1_i => dummy_stat_reg_1,
-- dummy_stat_reg_2_i => dummy_stat_reg_2,
-- dummy_stat_reg_3_i => dummy_stat_reg_3,
-- dummy_stat_reg_switch_i => dummy_stat_reg_switch
-- );
OBUF_tx : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "FAST")
port map (
O => ext_trig, -- Buffer output (connect directly to top-level port)
I => fe_data_i(0) -- Buffer input
);
cmp_wb_tx_core : wb_tx_core port map
(
-- Sys connect
wb_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
wb_stall_o => wb_stall(1),
-- TX
tx_clk_i => CLK_40,
tx_data_o => fe_cmd_o,
trig_pulse_o => trig_pulse
);
cmp_wb_rx_core: wb_rx_core PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(95 downto 64),
wb_cyc_i => wb_cyc(2),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(2),
wb_stall_o => wb_stall(2),
rx_clk_i => CLK_40,
rx_serdes_clk_i => CLK_160,
rx_data_i => fe_data_i,
rx_valid_o => rx_valid,
rx_data_o => rx_data,
busy_o => open,
debug_o => debug
);
cmp_wb_rx_bridge : wb_rx_bridge port map (
-- Sys Connect
sys_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(127 downto 96),
wb_cyc_i => wb_cyc(3),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(3),
wb_stall_o => wb_stall(3),
-- Wishbone DMA Master Interface
dma_clk_i => sys_clk,
dma_adr_o => rx_dma_adr,
dma_dat_o => rx_dma_dat_o,
dma_dat_i => rx_dma_dat_i,
dma_cyc_o => rx_dma_cyc,
dma_stb_o => rx_dma_stb,
dma_we_o => rx_dma_we,
dma_ack_i => rx_dma_ack,
dma_stall_i => rx_dma_stall,
-- Rx Interface (sync to sys_clk)
rx_data_i => rx_data,
rx_valid_i => rx_valid,
-- Status in
trig_pulse_i => trig_pulse,
-- Status out
irq_o => open,
busy_o => rx_busy
);
wb_dat_i(159 downto 136) <= (others => '0');
cmp_i2c_master : i2c_master_wb_top
port map (
wb_clk_i => sys_clk,
wb_rst_i => not rst_n,
arst_i => rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
wb_dat_o => wb_dat_i(135 downto 128),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(4),
wb_ack_o => wb_ack(4),
wb_inta_o => open,
scl => scl,
sda => sda
);
--wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1));
-- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2));
-- dummy_stat_reg_1 <= X"DEADBABE";
-- dummy_stat_reg_2 <= X"BEEFFACE";
-- dummy_stat_reg_3 <= X"12345678";
-- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked;
led_red_o <= dummy_ctrl_reg_led(0);
led_green_o <= dummy_ctrl_reg_led(1);
-- TRIG0(31 downto 0) <= (others => '0');
-- TRIG1(31 downto 0) <= (others => '0');
-- TRIG2(31 downto 0) <= (others => '0');
-- TRIG0(12 downto 0) <= (others => '0');
--TRIG1(31 downto 0) <= rx_dma_dat_o;
--TRIG1(31 downto 0) <= dma_dat_i;
-- TRIG1(31 downto 0) <= gn4124_core_status;
-- TRIG2(31 downto 0) <= ddr_status;
-- TRIG0(13) <= rx_dma_cyc;
-- TRIG0(14) <= rx_dma_stb;
-- TRIG0(15) <= rx_dma_we;
-- TRIG0(16) <= rx_dma_ack;
-- TRIG0(17) <= rx_dma_stall;
-- TRIG0(18) <= dma_cyc;
-- TRIG0(19) <= dma_stb;
-- TRIG0(20) <= dma_we;
-- TRIG0(21) <= dma_ack;
-- TRIG0(22) <= dma_stall;
-- TRIG0(23) <= irq_out;
-- TRIG0(24) <= rx_busy;
-- TRIG0(31 downto 25) <= (others => '0');
TRIG0(0) <= rx_valid;
TRIG0(1) <= fe_cmd_o(0);
TRIG0(2) <= trig_pulse;
TRIG0(3) <= fe_cmd_o(0);
TRIG0(31 downto 4) <= (others => '0');
TRIG1 <= rx_data;
TRIG2 <= debug;
-- TRIG0(0) <= scl;
-- TRIG0(1) <= sda;
-- TRIG0(2) <= wb_stb;
-- TRIG0(3) <= wb_ack(4);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= wb_adr;
-- TRIG2 <= wb_dat_o;
ila_i : ila
port map (
CONTROL => CONTROL,
CLK => CLK_40,
-- CLK => sys_clk,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2);
ila_icon_i : ila_icon
port map (
CONTROL0 => CONTROL);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- FOR TEST
------------------------------------------------------------------------------
p_led_cnt : process (L_RST_N, sys_clk)
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
elsif rising_edge(sys_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(23);
end if;
end process p_led_cnt;
led_pps <= led_cnt(23) and not(led_en);
p_led_k2000 : process (sys_clk, L_RST_N)
begin
if L_RST_N = '0' then
led_k2000 <= (others => '0');
leds <= "0001";
elsif rising_edge(sys_clk) then
if led_pps = '1' then
if led_k2000(2) = '0' then
if leds /= "1000" then
leds <= leds(2 downto 0) & '0';
end if;
else
if leds /= "0001" then
leds <= '0' & leds(3 downto 1);
end if;
end if;
led_k2000 <= led_k2000 + 1;
end if;
end if;
end process p_led_k2000;
AUX_LEDS_O <= not(leds);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
rst_n <= (L_RST_N and sys_clk_pll_locked and locked);
cmp_clk_gen : clk_gen
port map (
-- Clock in ports
CLK_40_IN => sys_clk_40,
CLKFB_IN => ioclk_fb,
-- Clock out ports
CLK_640 => CLK_640_buf,
CLK_160 => CLK_160_buf,
CLK_80 => CLK_80_buf,
CLK_40 => CLK_40_buf,
CLKFB_OUT => ioclk_fb,
-- Status and control signals
RESET => not L_RST_N,
LOCKED => locked
);
BUFPLL_640 : BUFPLL
generic map (
DIVIDE => 4, -- DIVCLK divider (1-8)
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
port map (
IOCLK => CLK_640, -- 1-bit output: Output I/O clock
LOCK => open, -- 1-bit output: Synchronized LOCK output
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
GCLK => CLK_160, -- 1-bit input: BUFG clock input
LOCKED => locked, -- 1-bit input: LOCKED input from PLL
PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL
);
cmp_ioclk_160_buf : BUFG
port map (
O => CLK_160,
I => CLK_160_buf);
cmp_ioclk_80_buf : BUFG
port map (
O => CLK_80,
I => CLK_80_buf);
cmp_ioclk_40_buf : BUFG
port map (
O => CLK_40,
I => CLK_40_buf);
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 40.000 MHz IO driver clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
sys_clk <= l_clk;
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n <= '1';
pll20dac_sync_n <= '1';
plldac_din <= '0';
plldac_sclk <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_40_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_40,
I => sys_clk_40_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
cmp_ddr3_ctrl: ddr3_ctrl PORT MAP(
clk_i => ddr_clk,
rst_n_i => rst_n,
status_o => ddr_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk,
wb0_sel_i => dma_sel,
wb0_cyc_i => dma_cyc,
wb0_stb_i => dma_stb,
wb0_we_i => dma_we,
wb0_addr_i => dma_adr,
wb0_data_i => dma_dat_o,
wb0_data_o => dma_dat_i,
wb0_ack_o => dma_ack,
wb0_stall_o => dma_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => open,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk,
wb1_sel_i => "1111",
wb1_cyc_i => rx_dma_cyc,
wb1_stb_i => rx_dma_stb,
wb1_we_i => rx_dma_we,
wb1_addr_i => rx_dma_adr,
wb1_data_i => rx_dma_dat_o,
wb1_data_o => rx_dma_dat_i,
wb1_ack_o => rx_dma_ack,
wb1_stall_o => rx_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
end rtl;
|
gpl-3.0
|
d8e938360413d9c526f4857cd0a8e23d
| 0.517169 | 3.078066 | false | false | false | false |
makestuff/umdkv2
|
vhdl/trace-fifo/trace_fifo_wrapper_xilinx.vhdl
| 1 | 2,016 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trace_fifo_wrapper is
port(
-- Clock
clk_in : in std_logic;
depth_out : out std_logic_vector(12 downto 0);
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(55 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(55 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of trace_fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.xilinx_trace_fifo
port map(
clk => clk_in,
data_count => depth_out,
-- Production end
din => inputData_in,
wr_en => inputValid_in,
full => inputFull,
-- Consumption end
dout => outputData_out,
empty => outputEmpty,
rd_en => outputReady_in
);
end architecture;
|
gpl-3.0
|
09fa5f6b55d567ad0f6cda18564f3413
| 0.688988 | 3.587189 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/minimips.vhd
| 1 | 28,647 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : miniMIPS processor --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2004 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pack_mips.all;
entity minimips is
port (
clock : in std_logic;
reset : in std_logic;
-- Ram connexion
ram_req : out std_logic;
ram_adr : out bus32;
ram_r_w : out std_logic;
ram_data : inout bus32;
ram_ack : in std_logic;
-- Hardware interruption
it_mat : in std_logic
);
end minimips;
architecture rtl of minimips is
-- General signals
signal stop_all : std_logic; -- Lock the pipeline evolution
signal it_mat_clk : std_logic; -- Synchronised hardware interruption
-- interface PF - EI
signal PF_pc : bus32; -- PC value
-- interface Controler - EI
signal CTE_instr : bus32; -- Instruction from the memory
signal ETC_adr : bus32; -- Address to read in memory
-- interface EI - DI
signal EI_instr : bus32; -- Read interface
signal EI_adr : bus32; -- Address from the read instruction
signal EI_it_ok : std_logic; -- Allow hardware interruptions
-- Asynchronous connexion with the bypass unit
signal adr_reg1 : adr_reg_type; -- Operand 1 address
signal adr_reg2 : adr_reg_type; -- Operand 2 address
signal use1 : std_logic; -- Operand 1 utilisation
signal use2 : std_logic; -- Operand 2 utilisation
signal data1 : bus32; -- First register value
signal data2 : bus32; -- Second register value
signal alea : std_logic; -- Unresolved hazards detected
-- interface DI - EX
signal DI_bra : std_logic; -- Branch decoded
signal DI_link : std_logic; -- A link for that instruction
signal DI_op1 : bus32; -- operand 1 for alu
signal DI_op2 : bus32; -- operand 2 for alu
signal DI_code_ual : alu_ctrl_type; -- Alu operation
signal DI_offset : bus32; -- Offset for the address calculation
signal DI_adr_reg_dest : adr_reg_type; -- Address of the destination register of the result
signal DI_ecr_reg : std_logic; -- Effective writing of the result
signal DI_mode : std_logic; -- Address mode (relative to pc or indexed to a register)
signal DI_op_mem : std_logic; -- Memory operation request
signal DI_r_w : std_logic; -- Type of memory operation (reading or writing)
signal DI_adr : bus32; -- Address of the decoded instruction
signal DI_exc_cause : bus32; -- Potential exception detected
signal DI_level : level_type; -- Availability of the result for the data bypass
signal DI_it_ok : std_logic; -- Allow hardware interruptions
-- interface EX - MEM
signal EX_adr : bus32; -- Instruction address
signal EX_bra_confirm : std_logic; -- Branch execution confirmation
signal EX_data_ual : bus32; -- Ual result
signal EX_adresse : bus32; -- Address calculation result
signal EX_adr_reg_dest : adr_reg_type; -- Destination register for the result
signal EX_ecr_reg : std_logic; -- Effective writing of the result
signal EX_op_mem : std_logic; -- Memory operation needed
signal EX_r_w : std_logic; -- Type of memory operation (read or write)
signal EX_exc_cause : bus32; -- Potential cause exception
signal EX_level : level_type; -- Availability stage of result for bypassing
signal EX_it_ok : std_logic; -- Allow hardware interruptions
-- interface Controler - MEM
signal MTC_data : bus32; -- Data to write in memory
signal MTC_adr : bus32; -- Address for memory
signal MTC_r_w : std_logic; -- Read/Write in memory
signal MTC_req : std_logic; -- Request access to memory
signal CTM_data : bus32; -- Data from memory
-- interface MEM - REG
signal MEM_adr : bus32; -- Instruction address
signal MEM_adr_reg_dest : adr_reg_type; -- Destination register address
signal MEM_ecr_reg : std_logic; -- Writing of the destination register
signal MEM_data_ecr : bus32; -- Data to write (from alu or memory)
signal MEM_exc_cause : bus32; -- Potential exception cause
signal MEM_level : level_type; -- Availability stage for the result for bypassing
signal MEM_it_ok : std_logic; -- Allow hardware interruptions
-- connexion to the register banks
-- Writing commands in the register banks
signal write_data : bus32; -- Data to write
signal write_adr : bus5; -- Address of the register to write
signal write_GPR : std_logic; -- Selection in the internal registers
signal write_SCP : std_logic; -- Selection in the coprocessor system registers
-- Reading commands for Reading in the registers
signal read_adr1 : bus5; -- Address of the first register to read
signal read_adr2 : bus5; -- Address of the second register to read
signal read_data1_GPR : bus32; -- Value of operand 1 from the internal registers
signal read_data1_SCP : bus32; -- Value of operand 2 from the internal registers
signal read_data2_GPR : bus32; -- Value of operand 1 from the coprocessor system registers
signal read_data2_SCP : bus32; -- Value of operand 2 from the coprocessor system registers
-- Interruption controls
signal interrupt : std_logic; -- Interruption to take into account
signal vecteur_it : bus32; -- Interruption vector
-- Connexion with predict
signal PR_bra_cmd : std_logic; -- Defined a branch
signal PR_bra_bad : std_logic; -- Defined a branch to restore from a bad prediction
signal PR_bra_adr : std_logic_vector(31 downto 0); -- New PC
signal PR_clear : std_logic; -- Clear the three pipeline stage : EI, DI, EX
-- Clear asserted when interrupt or PR_clear are asserted
signal clear : std_logic;
begin
clear <= interrupt or PR_clear;
-- Take into account the hardware interruption on rising edge
process (clock)
begin
if clock='1' and clock'event then
it_mat_clk <= it_mat;
end if;
end process;
U1_pf : pps_pf port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of the pipeline stage
-- entrees asynchrones
bra_adr => PR_bra_adr, -- Branch
bra_cmd => PR_bra_cmd, -- Address to load when an effective branch
bra_cmd_pr => PR_bra_bad, -- Branch which have a priority on stop_pf (bad prediction branch)
exch_adr => vecteur_it, -- Exception branch
exch_cmd => interrupt, -- Exception vector
-- Lock the stage
stop_pf => alea,
-- Synchronous output to EI stage
PF_pc => PF_pc -- PC value
);
U2_ei : pps_ei port map (
clock => clock,
reset => reset,
clear => clear, -- Clear the pipeline stage
stop_all => stop_all, -- Evolution locking signal
-- Asynchronous inputs
stop_ei => alea, -- Lock the EI_adr and Ei_instr registers
-- interface Controler - EI
CTE_instr => CTE_instr, -- Instruction from the memory
ETC_adr => ETC_adr, -- Address to read in memory
-- Synchronous inputs from PF stage
PF_pc => PF_pc, -- Current value of the pc
-- Synchronous outputs to DI stage
EI_instr => EI_instr, -- Read interface
EI_adr => EI_adr, -- Address from the read instruction
EI_it_ok => EI_it_ok -- Allow hardware interruptions
);
U3_di : pps_di port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of the outputs
clear => clear, -- Clear the pipeline stage (nop in the outputs)
-- Asynchronous connexion with the register management and data bypass unit
adr_reg1 => adr_reg1, -- Address of the first register operand
adr_reg2 => adr_reg2, -- Address of the second register operand
use1 => use1, -- Effective use of operand 1
use2 => use2, -- Effective use of operand 2
stop_di => alea, -- Unresolved detected : send nop in the pipeline
data1 => data1, -- Operand register 1
data2 => data2, -- Operand register 2
-- Datas from EI stage
EI_adr => EI_adr, -- Address of the instruction
EI_instr => EI_instr, -- The instruction to decode
EI_it_ok => EI_it_ok, -- Allow hardware interruptions
-- Synchronous output to EX stage
DI_bra => DI_bra, -- Branch decoded
DI_link => DI_link, -- A link for that instruction
DI_op1 => DI_op1, -- operand 1 for alu
DI_op2 => DI_op2, -- operand 2 for alu
DI_code_ual => DI_code_ual, -- Alu operation
DI_offset => DI_offset, -- Offset for the address calculation
DI_adr_reg_dest => DI_adr_reg_dest, -- Address of the destination register of the result
DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
DI_mode => DI_mode, -- Address mode (relative to pc or indexed to a register)
DI_op_mem => DI_op_mem, -- Memory operation request
DI_r_w => DI_r_w, -- Type of memory operation (reading or writing)
DI_adr => DI_adr, -- Address of the decoded instruction
DI_exc_cause => DI_exc_cause, -- Potential exception detected
DI_level => DI_level, -- Availability of the result for the data bypass
DI_it_ok => DI_it_ok -- Allow hardware interruptions
);
U4_ex : pps_ex port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of outputs
clear => clear, -- Clear the pipeline stage
-- Datas from DI stage
DI_bra => DI_bra, -- Branch instruction
DI_link => DI_link, -- Branch with link
DI_op1 => DI_op1, -- Operand 1 for alu
DI_op2 => DI_op2, -- Operand 2 for alu
DI_code_ual => DI_code_ual, -- Alu operation
DI_offset => DI_offset, -- Offset for address calculation
DI_adr_reg_dest => DI_adr_reg_dest, -- Destination register address for the result
DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
DI_mode => DI_mode, -- Address mode (relative to pc ou index by a register)
DI_op_mem => DI_op_mem, -- Memory operation
DI_r_w => DI_r_w, -- Type of memory operation (read or write)
DI_adr => DI_adr, -- Instruction address
DI_exc_cause => DI_exc_cause, -- Potential cause exception
DI_level => DI_level, -- Availability stage of the result for bypassing
DI_it_ok => DI_it_ok, -- Allow hardware interruptions
-- Synchronous outputs to MEM stage
EX_adr => EX_adr, -- Instruction address
EX_bra_confirm => EX_bra_confirm, -- Branch execution confirmation
EX_data_ual => EX_data_ual, -- Ual result
EX_adresse => EX_adresse, -- Address calculation result
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register for the result
EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
EX_op_mem => EX_op_mem, -- Memory operation needed
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
EX_exc_cause => EX_exc_cause, -- Potential cause exception
EX_level => EX_level, -- Availability stage of result for bypassing
EX_it_ok => EX_it_ok -- Allow hardware interruptions
);
U5_mem : pps_mem port map (
clock => clock,
reset => reset,
stop_all => stop_all, -- Unconditionnal locking of the outputs
clear => interrupt, -- Clear the pipeline stage
-- Interface with the control bus
MTC_data => MTC_data, -- Data to write in memory
MTC_adr => MTC_adr, -- Address for memory
MTC_r_w => MTC_r_w, -- Read/Write in memory
MTC_req => MTC_req, -- Request access to memory
CTM_data => CTM_data, -- Data from memory
-- Datas from Execution stage
EX_adr => EX_adr, -- Instruction address
EX_data_ual => EX_data_ual, -- Result of alu operation
EX_adresse => EX_adresse, -- Result of the calculation of the address
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register address for the result
EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
EX_op_mem => EX_op_mem, -- Memory operation needed
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
EX_exc_cause => EX_exc_cause, -- Potential exception cause
EX_level => EX_level, -- Availability stage for the result for bypassing
EX_it_ok => EX_it_ok, -- Allow hardware interruptions
-- Synchronous outputs for bypass unit
MEM_adr => MEM_adr, -- Instruction address
MEM_adr_reg_dest=>MEM_adr_reg_dest, -- Destination register address
MEM_ecr_reg => MEM_ecr_reg, -- Writing of the destination register
MEM_data_ecr => MEM_data_ecr, -- Data to write (from alu or memory)
MEM_exc_cause => MEM_exc_cause, -- Potential exception cause
MEM_level => MEM_level, -- Availability stage for the result for bypassing
MEM_it_ok => MEM_it_ok -- Allow hardware interruptions
);
U6_renvoi : renvoi port map (
-- Register access signals
adr1 => adr_reg1, -- Operand 1 address
adr2 => adr_reg2, -- Operand 2 address
use1 => use1, -- Operand 1 utilisation
use2 => use2, -- Operand 2 utilisation
data1 => data1, -- First register value
data2 => data2, -- Second register value
alea => alea, -- Unresolved hazards detected
-- Bypass signals of the intermediary datas
DI_level => DI_level, -- Availability level of the data
DI_adr => DI_adr_reg_dest, -- Register destination of the result
DI_ecr => DI_ecr_reg, -- Writing register request
DI_data => DI_op2, -- Data to used
EX_level => EX_level, -- Availability level of the data
EX_adr => EX_adr_reg_dest, -- Register destination of the result
EX_ecr => EX_ecr_reg, -- Writing register request
EX_data => EX_data_ual, -- Data to used
MEM_level => MEM_level, -- Availability level of the data
MEM_adr => MEM_adr_reg_dest, -- Register destination of the result
MEM_ecr => MEM_ecr_reg, -- Writing register request
MEM_data => MEM_data_ecr, -- Data to used
interrupt => interrupt, -- Exceptions or interruptions
-- Connexion to the differents bank of register
-- Writing commands for writing in the registers
write_data => write_data, -- Data to write
write_adr => write_adr, -- Address of the register to write
write_GPR => write_GPR, -- Selection in the internal registers
write_SCP => write_SCP, -- Selection in the coprocessor system registers
-- Reading commands for Reading in the registers
read_adr1 => read_adr1, -- Address of the first register to read
read_adr2 => read_adr2, -- Address of the second register to read
read_data1_GPR => read_data1_GPR, -- Value of operand 1 from the internal registers
read_data1_SCP => read_data1_SCP, -- Value of operand 2 from the internal registers
read_data2_GPR => read_data2_GPR, -- Value of operand 1 from the coprocessor system registers
read_data2_SCP => read_data2_SCP -- Value of operand 2 from the coprocessor system registers
);
U7_banc : banc port map(
clock => clock,
reset => reset,
-- Register addresses to read
reg_src1 => read_adr1,
reg_src2 => read_adr2,
-- Register address to write and its data
reg_dest => write_adr,
donnee => write_data,
-- Write signal
cmd_ecr => write_GPR,
-- Bank outputs
data_src1 => read_data1_GPR,
data_src2 => read_data2_GPR
);
U8_syscop : syscop port map (
clock => clock,
reset => reset,
-- Datas from the pipeline
MEM_adr => MEM_adr, -- Address of the current instruction in the pipeline end -> responsible of the exception
MEM_exc_cause => MEM_exc_cause, -- Potential cause exception of that instruction
MEM_it_ok => MEM_it_ok, -- Allow hardware interruptions
-- Hardware interruption
it_mat => it_mat_clk, -- Hardware interruption detected
-- Interruption controls
interrupt => interrupt, -- Interruption to take into account
vecteur_it => vecteur_it, -- Interruption vector
-- Writing request in register bank
write_data => write_data, -- Data to write
write_adr => write_adr, -- Address of the register to write
write_SCP => write_SCP, -- Writing request
-- Reading request in register bank
read_adr1 => read_adr1, -- Address of the first register
read_adr2 => read_adr2, -- Address of the second register
read_data1 => read_data1_SCP, -- Value of register 1
read_data2 => read_data2_SCP -- Value of register 2
);
U9_bus_ctrl : bus_ctrl port map (
clock => clock,
reset => reset,
-- Interruption in the pipeline
interrupt => interrupt,
-- Interface for the Instruction Extraction Stage
adr_from_ei => ETC_adr, -- The address of the data to read
instr_to_ei => CTE_instr, -- Instruction from the memory
-- Interface with the MEMory Stage
req_from_mem => MTC_req, -- Request to access the ram
r_w_from_mem => MTC_r_w, -- Read/Write request
adr_from_mem => MTC_adr, -- Address in ram
data_from_mem => MTC_data, -- Data to write in ram
data_to_mem => CTM_data, -- Data from the ram to the MEMory stage
-- RAM interface signals
req_to_ram => ram_req, -- Request to ram
adr_to_ram => ram_adr, -- Address of the data to read or write
r_w_to_ram => ram_r_w, -- Read/Write request
ack_from_ram => ram_ack, -- Acknowledge from the memory
data_inout_ram => ram_data, -- Data from/to the memory
-- Pipeline progress control signal
stop_all => stop_all
);
U10_predict : predict port map (
clock => clock,
reset => reset,
-- Datas from PF pipeline stage
PF_pc => PF_pc, -- PC of the current instruction extracted
-- Datas from DI pipeline stage
DI_bra => DI_bra, -- Branch detected
DI_adr => DI_adr, -- Address of the branch
-- Datas from EX pipeline stage
EX_bra_confirm => EX_bra_confirm, -- Confirm if the branch test is ok
EX_adr => EX_adr, -- Address of the branch
EX_adresse => EX_adresse, -- Result of the branch
EX_uncleared => EX_it_ok, -- Define if the EX stage is cleared
-- Outputs to PF pipeline stage
PR_bra_cmd => PR_bra_cmd, -- Defined a branch
PR_bra_bad => PR_bra_bad, -- Defined a branch to restore from a bad prediction
PR_bra_adr => PR_bra_adr, -- New PC
-- Clear the three pipeline stage : EI, DI, EX
PR_clear => PR_clear
);
end rtl;
|
gpl-2.0
|
ba6c3dca35ad9d9b07c06c096d8356ff
| 0.441757 | 5.334637 | false | false | false | false |
makestuff/umdkv2
|
templates/fx2min/vhdl/lx9r3.vhdl
| 2 | 6,552 |
-- file: clk_gen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.001______0.000______50.0______200.000____150.000
-- CLK_OUT2____48.001____180.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________48____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_gen is
port
(-- Clock in ports
clk_in : in std_logic;
-- Clock out ports
clk000_out : out std_logic;
clk180_out : out std_logic;
-- Status and control signals
locked_out : out std_logic
);
end clk_gen;
architecture xilinx of clk_gen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_gen,clk_wiz_v4_1,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.833,clkin2_period=20.833,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk180 : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clk_in);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.833,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => clk180,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
locked_out <= locked_internal;
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
clk000_out <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => clk180_out,
I => clk180);
end xilinx;
|
gpl-3.0
|
d1a228b7e490a4d1f3b59e516bb71a20
| 0.57265 | 4.235294 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Equalizer.vhd
| 1 | 16,697 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- This file describes the implementation of a generic equalizer. This --
-- equaliser is made up out of three second order, direct IIR-filters with --
-- multipliers between. --
-- --
-- --
-- Generic: --
-- DATA_WIDTH - The width of the input data, output data as well --
-- as the data signals between the IIR-filters and --
-- multipliers --
-- DATA_FRACT - The factrional width of above data --
-- --
-- SCALE_WIDTH_1 - Data width of the first scaling factor --
-- SCALE_FRACT_1 - Fractional width of the first scaling factor --
-- SCALE_WIDTH_2 - Data width of the second scaling factor --
-- SCALE_FRACT_2 - Fractional width of the second scaling factor --
-- SCALE_WIDTH_3 - Data width of the third scaling factor --
-- SCALE_FRACT_3 - Fractional width of the third scaling factor --
-- SCALE_WIDTH_4 - Data width of the fourth scaling factor --
-- SCALE_FRACT_4 - Fractional width of the fourth scaling factor --
-- --
-- INTERNAL_IIR_WIDTH_1 - Width of the internal calculations within the --
-- first IIR-filter --
-- INTERNAL_IIR_FRACT_1 - Fractional width of the internal calculations --
-- within the first IIR-filter --
-- INTERNAL_IIR_WIDTH_2 - Width of the internal calculations within the --
-- second IIR-filter --
-- INTERNAL_IIR_FRACT_2 - Fractional width of the internal calculations --
-- within the second IIR-filter --
-- INTERNAL_IIR_WIDTH_3 - Width of the internal calculations within the --
-- third IIR-filter --
-- INTERNAL_IIR_FRACT_3 - Fractional width of the internal calculations --
-- within the third IIR-filter --
-- --
-- COEFF_WIDTH_1 - Width of the coefficients used in the first --
-- IIR-filter --
-- COEFF_FRACT_1 - Fractional width of the coefficients used in the --
-- first IIR-filter --
-- COEFF_WIDTH_2 - Width of the coefficients used in the second --
-- IIR-filter --
-- COEFF_FRACT_2 - Fractional width of the coefficients used in the --
-- second IIR-filter --
-- COEFF_WIDTH_3 - Width of the coefficients used in the third --
-- IIR-filter --
-- COEFF_FRACT_3 - Fractional width of the coefficients used in the --
-- third IIR-filter --
-- --
-- --
-- Input/Output: --
-- clk - System clock --
-- reset - Resets component when high --
-- write_mode - Write new coefficients when high --
-- x - Input --
-- --
-- scale_1 - First scaling factor --
-- scale_2 - Second scaling factor --
-- scale_3 - Third scaling factor --
-- scale_4 - Fourth scaling factor --
-- --
-- b0_1 - B coefficient of the first IIR filter --
-- b1_1 - B coefficient of the first IIR filter --
-- b2_1 - B coefficient of the first IIR filter --
-- a1_1 - A coefficient of the first IIR filter --
-- a2_1 - A coefficient of the first IIR filter --
-- --
-- b0_2 - B coefficient of the second IIR filter --
-- b1_2 - B coefficient of the second IIR filter --
-- b2_2 - B coefficient of the second IIR filter --
-- a1_2 - A coefficient of the second IIR filter --
-- a2_2 - A coefficient of the second IIR filter --
-- --
-- b0_3 - B coefficient of the third IIR filter --
-- b1_3 - B coefficient of the third IIR filter --
-- b2_3 - B coefficient of the third IIR filter --
-- a1_3 - A coefficient of the third IIR filter --
-- a2_3 - A coefficient of the third IIR filter --
-- --
-- y - Output --
-- --
-- --
-- Internal Constants: --
-- N - Number of coefficients, this number is three for a --
-- second order filter and should not be changed. The --
-- constant is mearly there to simplify creation of --
-- higher order filters. Note that for this to be done --
-- successfully, you have to increase the number of --
-- coefficients as well. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Equalizer is
generic (DATA_WIDTH : natural := 8;
DATA_FRACT : natural := 6;
SCALE_WIDTH_1 : natural := 8;
SCALE_FRACT_1 : natural := 6;
SCALE_WIDTH_2 : natural := 8;
SCALE_FRACT_2 : natural := 6;
SCALE_WIDTH_3 : natural := 8;
SCALE_FRACT_3 : natural := 6;
SCALE_WIDTH_4 : natural := 8;
SCALE_FRACT_4 : natural := 6;
INTERNAL_IIR_WIDTH_1 : natural := 12;
INTERNAL_IIR_FRACT_1 : natural := 8;
INTERNAL_IIR_WIDTH_2 : natural := 12;
INTERNAL_IIR_FRACT_2 : natural := 8;
INTERNAL_IIR_WIDTH_3 : natural := 12;
INTERNAL_IIR_FRACT_3 : natural := 8;
COEFF_WIDTH_1 : natural := 8;
COEFF_FRACT_1 : natural := 6;
COEFF_WIDTH_2 : natural := 8;
COEFF_FRACT_2 : natural := 6;
COEFF_WIDTH_3 : natural := 8;
COEFF_FRACT_3 : natural := 6);
port(clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(DATA_WIDTH-1 downto 0);
scale_1 : in std_logic_vector(SCALE_WIDTH_1-1 downto 0);
scale_2 : in std_logic_vector(SCALE_WIDTH_2-1 downto 0);
scale_3 : in std_logic_vector(SCALE_WIDTH_3-1 downto 0);
scale_4 : in std_logic_vector(SCALE_WIDTH_4-1 downto 0);
b0_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b1_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b2_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
a1_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
a2_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b0_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b1_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b2_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
a1_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
a2_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b0_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
b1_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
b2_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
a1_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
a2_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
y : out std_logic_vector(DATA_WIDTH-1 downto 0));
end Equalizer;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Equalizer is
-- Signals ---------------------------------------------------------------------
signal s_scale_1 : std_logic_vector(SCALE_WIDTH_1-1 downto 0);
signal s_scale_2 : std_logic_vector(SCALE_WIDTH_2-1 downto 0);
signal s_scale_3 : std_logic_vector(SCALE_WIDTH_3-1 downto 0);
signal s_scale_4 : std_logic_vector(SCALE_WIDTH_4-1 downto 0);
signal s_b0_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b1_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b2_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_a1_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_a2_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b0_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b1_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b2_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_a1_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_a2_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b0_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_b1_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_b2_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_a1_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_a2_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal iir_input_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_input_2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_input_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Set coefficients
s_scale_1 <= scale_1;
s_scale_2 <= scale_2;
s_scale_3 <= scale_3;
s_scale_4 <= scale_4;
s_b0_1 <= b0_1;
s_b1_1 <= b1_1;
s_b2_1 <= b2_1;
s_a1_1 <= a1_1;
s_a2_1 <= a2_1;
s_b0_2 <= b0_2;
s_b1_2 <= b1_2;
s_b2_2 <= b2_2;
s_a1_2 <= a1_2;
s_a2_2 <= a2_2;
s_b0_3 <= b0_3;
s_b1_3 <= b1_3;
s_b2_3 <= b2_3;
s_a1_3 <= a1_3;
s_a2_3 <= a2_3;
-- Stage 1 -------------------------------------------------------------------
Multiplier_1 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_1,
Y_FRACTION => SCALE_FRACT_1,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => x,
y => s_scale_1,
s => iir_input_1);
Generic_IIR_SO_1 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_1,
COEFFICIENT_FRACT => COEFF_FRACT_1,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_1,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_1,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_1,
B0 => s_b0_1,
B1 => s_b1_1,
B2 => s_b2_1,
A1 => s_a1_1,
A2 => s_a2_1,
y => iir_output_1);
-- Stage 2 -------------------------------------------------------------------
Multiplier_2 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_2,
Y_FRACTION => SCALE_FRACT_2,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_1,
y => s_scale_2,
s => iir_input_2);
Generic_IIR_SO_2 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_2,
COEFFICIENT_FRACT => COEFF_FRACT_2,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_2,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_2,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_2,
B0 => s_b0_2,
B1 => s_b1_2,
B2 => s_b2_2,
A1 => s_a1_2,
A2 => s_a2_2,
y => iir_output_2);
-- Stage 3 -------------------------------------------------------------------
Multiplier_3 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_3,
Y_FRACTION => SCALE_FRACT_3,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_2,
y => s_scale_3,
s => iir_input_3);
Generic_IIR_SO_3 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_3,
COEFFICIENT_FRACT => COEFF_FRACT_3,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_3,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_3,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_3,
B0 => s_b0_3,
B1 => s_b1_3,
B2 => s_b2_3,
A1 => s_a1_3,
A2 => s_a2_3,
y => iir_output_3);
-- Stage 4 -------------------------------------------------------------------
Multiplier_4 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_4,
Y_FRACTION => SCALE_FRACT_4,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_3,
y => s_scale_4,
s => y);
end architecture;
|
mit
|
11e973cc429e980afde03e34cc383591
| 0.405821 | 4.281282 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/arbiter_in.vhd
| 12 | 3,876 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L:in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L:out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_in is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N <= '0';
X_E <= '0';
X_W <= '0';
X_S <= '0';
X_L <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
|
gpl-3.0
|
c5b5d74295f4969f5b0ab123a477e0f6
| 0.453302 | 2.871111 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/delay_line.vhd
| 2 | 3,699 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity delay_line is
generic (
width : positive := 8
);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0)
);
end delay_line;
architecture Behavioral of delay_line is
signal chain : std_logic_vector(((2**width)-1) downto 0);
signal chain_t : std_logic_vector(((2**width)-1) downto 0);
signal select_t : std_logic_vector(((2**width)-1) downto 0);
signal input_t : std_logic_vector(((2**width)/4)-1 downto 0);
signal output_t : std_logic;
attribute KEEP : string;
attribute KEEP of chain_t : signal is "true";
attribute KEEP of input_t : signal is "true";
attribute RLOC : string;
attribute RLOC of first_mux : label is "X" & INTEGER'image(0) & "Y" & INTEGER'image(0);
constant delay_time: time := 300 ps;
begin
output <= input when (unsigned(setting) = 0) else output_t;
reg: process(clk, rst, input, setting)
begin
if (rst = '1') then
select_t <= (others => '0');
elsif rising_edge(clk) then
select_t <= (others => '0');
select_t <= std_logic_vector(to_unsigned(1, 2**width) sll 2**width-1-to_integer(unsigned(setting)));
end if;
end process reg;
first_mux: muxf6 port map (s => '0', i0 => input_t(0), i1 => '0', o => chain_t(0));
chain(0) <= chain_t(0) after delay_time;
delay_loop: for j in 1 to ((2**WIDTH)-1) generate
begin
even_cols: if ((j/32) rem 2) = 0 generate
-- four mux go into one slice
constant row : integer := (j/4) rem 8;
constant column : integer := j/32;
attribute RLOC of mux : label is "X" & INTEGER'image(column) & "Y" & INTEGER'image(row);
begin
mux: muxf6 port map (s => select_t(j), i0 => chain(j - 1), i1 => input_t(j/4), o => chain_t(j));
chain(j) <= chain_t(j) after delay_time;
end generate;
odd_cols: if ((j/32) rem 2) = 1 generate
-- four mux go into one slice
constant row : integer := 7-((j/4) rem 8);
constant column : integer := j/32;
attribute RLOC of mux : label is "X" & INTEGER'image(column) & "Y" & INTEGER'image(row);
begin
mux: muxf6 port map (s => select_t(j+(3-((j rem 4)*2))), i0 => chain(j+(3-((j rem 4)*2)) - 1), i1 => input_t(j/4), o => chain_t(j+(3-((j rem 4)*2))));
chain(j) <= chain_t(j) after delay_time;
end generate;
end generate;
reg_loop: for j in 0 to ((2**width)/4)-1 generate
begin
even_cols: if ((j/8) rem 2) = 0 generate
constant row : integer := (j) rem 8;
constant column : integer := j/8;
attribute RLOC of input_reg : label is "X" & INTEGER'image(column-1) & "Y" & INTEGER'image(row);
begin
input_reg : FDCE generic map (INIT => '0')port map (Q => input_t(j), C => clk,CE => '1', CLR => rst, D => input);
end generate;
odd_cols: if ((j/8) rem 2) = 1 generate
constant row : integer := 7-((j) rem 8);
constant column : integer := j/8;
attribute RLOC of input_reg : label is "X" & INTEGER'image(column-1) & "Y" & INTEGER'image(row);
begin
input_reg : FDCE generic map (INIT => '0')port map (Q => input_t(j), C => clk,CE => '1', CLR => rst, D => input);
end generate;
end generate;
output_t <= chain(2**width-1);
end Behavioral;
|
gpl-3.0
|
8ec105e6359c642617458e13306226e5
| 0.545283 | 3.338448 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/xbar.vhd
| 1 | 1,701 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
North_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (9 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in, North_vc_in, East_vc_in, West_vc_in, South_vc_in, Local_vc_in) begin
case(sel) is
when "0000000001" =>
Data_out <= Local_in;
when "0000000010" =>
Data_out <= South_in;
when "0000000100" =>
Data_out <= West_in;
when "0000001000" =>
Data_out <= East_in;
when "0000010000" =>
Data_out <= North_in;
when "0000100000" =>
Data_out <= Local_vc_in;
when "0001000000" =>
Data_out <= South_vc_in;
when "0010000000" =>
Data_out <= West_vc_in;
when "0100000000" =>
Data_out <= East_vc_in;
when others =>
Data_out <= North_vc_in;
end case;
end process;
end;
|
gpl-3.0
|
befcdc76cbc65fb5783e66ab3b47cc09
| 0.599059 | 3.081522 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/pps_pf.vhd
| 1 | 5,383 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Address calculation stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity pps_pf is
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1; -- Unconditionnal locking of the pipeline stage
-- Asynchronous inputs
bra_cmd : in bus1; -- Branch
bra_cmd_pr : in bus1; -- Branch which have a priority on stop_pf (bad prediction branch)
bra_adr : in bus32; -- Address to load when an effective branch
exch_cmd : in bus1; -- Exception branch
exch_adr : in bus32; -- Exception vector
stop_pf : in bus1; -- Lock the stage
-- Synchronous output to EI stage
PF_pc : out bus32 -- PC value
);
end pps_pf;
architecture rtl of pps_pf is
signal suivant : bus32; -- Preparation of the future pc
signal pc_interne : bus32; -- Value of the pc output, needed for an internal reading
signal lock : bus1; -- Specify the authorization of the pc evolution
begin
-- Connexion the pc to the internal pc
PF_pc <= pc_interne;
-- Elaboration of an potential future pc
suivant <= exch_adr when exch_cmd='1' else
bra_adr when bra_cmd_pr='1' else
bra_adr when bra_cmd='1' else
bus32(unsigned(pc_interne) + 4);
lock <= '1' when stop_all='1' else -- Lock this stage when all the pipeline is locked
'0' when exch_cmd='1' else -- Exception
'0' when bra_cmd_pr='1' else -- Bad prediction restoration
'1' when stop_pf='1' else -- Wait for the data hazard
'0' when bra_cmd='1' else -- Branch
'0'; -- Normal evolution
-- Synchronous evolution of the pc
process(clock)
begin
if clock='1' and clock'event then
if reset='1' then
-- PC reinitialisation with the boot address
pc_interne <= ADR_INIT;
elsif lock='0' then
-- PC not locked
pc_interne <= suivant;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
e68e3f57d92d6686d2be8f9232fc139a
| 0.385659 | 5.56095 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/ADSampler_tb.vhd
| 1 | 3,283 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:41:06 02/07/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/ISEProject/Soundbox/Source/AudioIO/ADSampler_tb.vhd
-- Project Name: Soundbox
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ADSampler
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ADSampler_tb IS
END ADSampler_tb;
ARCHITECTURE behavior OF ADSampler_tb IS
-- Component Declaration for the Unit Under Test (UUT)
--Inputs
signal DRP_output : std_logic_vector(15 downto 0) := (others => '0');
signal DRP_dataReady : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal DRP_input : std_logic_vector(15 downto 0);
signal DRP_address : std_logic_vector(6 downto 0);
signal DRP_enable : std_logic;
signal DRP_writeEnable : std_logic;
signal DRP_clk : std_logic;
signal XADC_reset : std_logic;
signal XADC_EOC : std_logic := '0';
signal XADC_busy : std_logic := '0';
signal output : std_logic_vector(11 downto 0);
-- Clock period definitions
constant DRP_clk_period : time := 10 ns;
constant XADC_convstclk_period : time := 10 ns;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.ADSampler
port map(
DRP_output => DRP_output,
DRP_dataReady => DRP_dataReady,
DRP_input => DRP_input,
DRP_address => DRP_address,
DRP_enable => DRP_enable,
DRP_writeEnable => DRP_writeEnable,
DRP_clk => DRP_clk,
XADC_reset => XADC_reset,
XADC_EOC => XADC_EOC,
XADC_busy => XADC_busy,
output => output,
clk => clk,
reset => reset
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
XADC_busy <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*5;
XADC_busy <= '0';
wait for clk_period*10;
XADC_EOC <= '1';
wait for clk_period;
XADC_EOC <= '0';
wait for clk_period*5;
DRP_dataReady <= '1';
DRP_output <= (others => '1');
wait for clk_period;
DRP_dataReady <= '0';
-- insert stimulus here
wait;
end process;
END;
|
mit
|
a476595551a801a041a0475cb5724a32
| 0.586049 | 3.821886 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/sampler.vhd
| 4 | 3,390 |
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sampler is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0); -- 32 input channels
clock : in STD_LOGIC; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in STD_LOGIC_VECTOR (23 downto 0); -- configuration data
wrDivider : in STD_LOGIC; -- write divider register
sample : out STD_LOGIC_VECTOR (31 downto 0); -- sampled data
ready : out STD_LOGIC; -- new sample ready
ready50 : out std_logic); -- low rate sample signal with 50% duty cycle
end sampler;
architecture Behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
begin
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
-- sample <= input(31 downto 10) & exClock & lastExClock & input(7 downto 0);
ready <= '1';
else
sample <= input;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= input;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
-- generate ready50 50% duty cycle sample signal
process(clock)
begin
if rising_edge(clock) then
if counter = divider then
ready50 <= '1';
elsif counter(22 downto 0) = divider(23 downto 1) then
ready50 <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
ee877c04604691ac45abdf9096b0484c
| 0.607965 | 3.887615 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/sp6_data_gen.vhd
| 20 | 37,259 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
gpl-3.0
|
1abbb18dda151198494a24f11d07c72a
| 0.455299 | 4.511321 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
uart_tx.vhd
| 2 | 2,928 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- UART transmission module
entity uart_tx is
port (Clk : in std_logic;
Rst : in std_logic;
FreqEn : in std_logic;
Byte : in std_logic_vector(7 downto 0);
Kick : in std_logic;
RsTx : out std_logic;
Busy : out std_logic);
end uart_tx;
-- Operation:
-- Wait for @Kick, save values of @Kick and @Byte when it's high.
-- Transition between states when @FreqEn is high.
architecture Behavioral of uart_tx is
type state_t is (IDLE, START, XMIT, STOP);
signal state, NEXT_state : state_t;
signal cnt, NEXT_cnt : integer range 0 to 7;
signal saveByte : std_logic_vector(7 downto 0);
signal saveKick : std_logic;
begin
Busy <= saveKick;
NEXT_fsm : process (state, cnt, saveByte, saveKick)
begin
NEXT_state <= state;
NEXT_cnt <= cnt + 1;
RsTx <= '1'; -- high is idle
case state is
when IDLE =>
if saveKick = '1' then
NEXT_state <= START;
end if;
when START =>
NEXT_state <= XMIT;
NEXT_cnt <= 0;
RsTx <= '0';
when XMIT =>
RsTx <= saveByte(cnt);
if cnt = 7 then
NEXT_state <= STOP;
end if;
when STOP => -- UART wants at least two stop bits - STOP, IDLE
NEXT_state <= IDLE;
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
if FreqEn = '1' then
state <= NEXT_state;
cnt <= NEXT_cnt;
if state = STOP then
saveKick <= '0';
end if;
end if;
if saveKick = '0' and Kick = '1' then
saveKick <= Kick;
saveByte <= Byte;
end if;
if Rst = '1' then
state <= IDLE;
saveKick <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
62873aa37ae0060515b1c93ba5d0fe59
| 0.537227 | 4.095105 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/mcb_traffic_gen.vhd
| 20 | 37,533 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
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-- special, incidental, or consequential loss or damage
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_traffic_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level module of memory traffic generator which can
-- generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
-- hard memory controller core.
-- Reference:
-- Revision History: 2009 Brought out internal signals cmp_data and cmp_error as outputs.
-- 2010/01/09 Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
-- 2010/05/03 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG.
-- 2010/05/20 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_traffic_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
SIMULATION : STRING := "FALSE";
MEM_BURST_LEN : INTEGER := 8;
PORT_MODE : STRING := "BI_MODE";
DATA_PATTERN : STRING := "DGEN_ADDR";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
CMP_DATA_PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
NUM_DQ_PINS : INTEGER := 16;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : INTEGER := 3;
DWIDTH : INTEGER := 32;
EYE_TEST : STRING := "FALSE";
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
run_traffic_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
bram_cmd_i : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
mcb_cmd_en_o : OUT STD_LOGIC;
mcb_cmd_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_cmd_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
mcb_cmd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_en_o : OUT STD_LOGIC;
mcb_wr_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_wr_data_end_o : OUT STD_LOGIC;
mcb_wr_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
mcb_wr_full_i : IN STD_LOGIC;
mcb_wr_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
mcb_rd_en_o : OUT STD_LOGIC;
mcb_rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_rd_empty_i : IN STD_LOGIC;
mcb_rd_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
counts_rst : IN STD_LOGIC;
wr_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
rd_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
error : OUT STD_LOGIC;
cmp_data_valid : OUT STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
cmp_error : out std_logic;
cmp_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
mem_rd_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END mcb_traffic_gen;
ARCHITECTURE trans OF mcb_traffic_gen IS
COMPONENT mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_gen IS
GENERIC (
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_PRBS";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END COMPONENT;
component afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component read_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
CMP_DATA_PIPE_STAGES : INTEGER := 3;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
DQ_ERROR_WIDTH : INTEGER := 1;
SEL_VICTIM_LINE : integer := 3;
MEM_COL_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
manual_clear_error : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_o : OUT STD_LOGIC;
data_valid_i : IN STD_LOGIC;
data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
last_word_rd_o : OUT STD_LOGIC;
data_error_o : OUT STD_LOGIC;
cmp_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_mdata_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_data_valid : OUT STD_LOGIC;
cmp_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error_r :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END component;
component write_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_ALL";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
MEM_COL_WIDTH : INTEGER := 10;
EYE_TEST : string := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
last_word_wr_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
data_wr_end_o : out std_logic
);
END component;
component tg_status IS
GENERIC (
TCQ : TIME := 100 ps;
DWIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
data_error_i : IN STD_LOGIC;
cmp_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_full_i : IN STD_LOGIC;
mcb_rd_empty_i : IN STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
error : OUT STD_LOGIC
);
END component;
attribute KEEP : STRING;
attribute MAX_FANOUT : STRING;
function MEM_BLENGTH return integer is
begin
if (MEM_BURST_LEN = 4) then
return 4;
elsif (MEM_BURST_LEN = 8) then
return 8;
else
return 8;
end if;
end function MEM_BLENGTH;
constant MEM_BLEN : INTEGER := MEM_BLENGTH;
SIGNAL mcb_wr_en : STD_LOGIC;
SIGNAL cmd2flow_valid : STD_LOGIC;
SIGNAL cmd2flow_cmd : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL cmd2flow_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmd2flow_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL last_word_rd : STD_LOGIC;
SIGNAL last_word_wr : STD_LOGIC;
SIGNAL flow2cmd_rdy : STD_LOGIC;
SIGNAL wr_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rd_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL run_traffic_reg : STD_LOGIC;
SIGNAL wr_validB : STD_LOGIC;
SIGNAL wr_valid : STD_LOGIC;
SIGNAL wr_validC : STD_LOGIC;
SIGNAL bram_addr_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bram_instr_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bram_bl_i : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL addr_o : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- SIGNAL m_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL dcount_rst : STD_LOGIC;
SIGNAL rd_addr_error : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_rdy : STD_LOGIC;
SIGNAL cmp_error_int : STD_LOGIC;
SIGNAL cmd_full : STD_LOGIC;
SIGNAL cmp_data_int : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mem_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL cmp_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmp_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rst_ra : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rst_rb : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL mcb_wr_full_r1 : STD_LOGIC;
SIGNAL mcb_wr_full_r2 : STD_LOGIC;
SIGNAL mcb_rd_empty_r : STD_LOGIC;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL rd_buff_avail : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL data_mode_r_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_c : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tmp_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL error_access_range : STD_LOGIC ;
SIGNAL mcb_rd_empty : STD_LOGIC;
SIGNAL mcb_wr_full : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_rdy : STD_LOGIC;
SIGNAL rd_valid : STD_LOGIC;
SIGNAL cmd_rd_en : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL xhdl17 : STD_LOGIC;
SIGNAL xhdl19 : STD_LOGIC;
SIGNAL ZEROS : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bram_rdy_o_xhdl0 : STD_LOGIC;
SIGNAL mcb_cmd_en_o_xhdl5 : STD_LOGIC;
SIGNAL mcb_cmd_instr_o_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL mcb_cmd_addr_o_xhdl3 : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL mcb_cmd_bl_o_xhdl4 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mcb_wr_data_o_xhdl9 : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
SIGNAL mcb_wr_mask_o_xhdl10 : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
SIGNAL mcb_rd_en : STD_LOGIC;
SIGNAL wr_data_counts_xhdl12 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL rd_data_counts_xhdl11 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL error_xhdl1 : STD_LOGIC;
SIGNAL error_status_xhdl2 : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
SIGNAL cmd_fifo_wr : STD_LOGIC;
SIGNAL xfer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fifo_error : STD_LOGIC;
SIGNAL cmd_fifo_rd : STD_LOGIC;
SIGNAL cmd_fifo_empty : STD_LOGIC;
SIGNAL xfer_cmd_bl : STD_LOGIC;
SIGNAL cmd_fifo_full : STD_LOGIC;
SIGNAL rd_mdata_afull_set : STD_LOGIC;
SIGNAL rd_mdata_fifo_afull : STD_LOGIC;
SIGNAL rdpath_data_valid_i : STD_LOGIC;
SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
SIGNAL rd_v6_mdata : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mdata_wren : STD_LOGIC;
attribute KEEP of rst_ra : signal is "TRUE";
attribute KEEP of rst_rb : signal is "TRUE";
attribute KEEP of mcb_wr_full_r1 : signal is "TRUE";
attribute KEEP of mcb_wr_full_r2 : signal is "TRUE";
attribute MAX_FANOUT of rst_ra : signal is "20";
attribute MAX_FANOUT of rst_rb : signal is "20";
BEGIN
mem_rd_data <= mem_rd_data_i;
ZEROS <= (others => '0');
cmp_data <= cmp_data_int;
cmp_error <= cmp_error_int;
-- Drive referenced outputs
bram_rdy_o <= bram_rdy_o_xhdl0;
mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
mcb_rd_en_o <= mcb_rd_en;
wr_data_counts <= wr_data_counts_xhdl12;
rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
error <= error_xhdl1;
error_status <= error_status_xhdl2;
tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
-- tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
--synthesis translate_off
PROCESS
BEGIN
IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
END IF;
WAIT;
END PROCESS;
PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
BEGIN
IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
report "Error ! Data access beyond address range"; -- severity ERROR;
error_access_range <= '1';
-- $stop();
END IF;
END PROCESS;
--synthesis translate_on
mcb_rd_empty <= mcb_rd_empty_i;
mcb_wr_full <= mcb_wr_full_i;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_r_a <= data_mode_i;
data_mode_r_b <= data_mode_i;
data_mode_r_c <= data_mode_i;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_wr_full_r1 <= '0';
ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
mcb_wr_full_r1 <= '1';
mcb_wr_full_r2 <= '1';
ELSE
mcb_wr_full_r1 <= '0';
mcb_wr_full_r2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_rd_empty_r <= '1';
ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
mcb_rd_empty_r <= '1';
ELSE
mcb_rd_empty_r <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_reg <= run_traffic_i;
END IF;
END PROCESS;
bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
dcount_rst <= counts_rst OR rst_ra(0);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
wr_data_counts_xhdl12 <= (OTHERS => '0');
ELSIF (mcb_wr_en = '1') THEN
wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
rd_data_counts_xhdl11 <= (others => '0');
ELSIF (mcb_rd_en = '1') THEN
rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
xhdl13 : IF (SIMULATION = "TRUE") GENERATE
cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_o_xhdl5 = '1') THEN
if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
fifo_error <= '1';
ELSE
fifo_error <= '0';
END IF;
END IF;
END IF;
END PROCESS;
cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
xfer_cmd_bl <= xhdl15(32);
xfer_addr <= xhdl15(31 downto 0);
cmd_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => 38,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_ra(0),
wr_en => cmd_fifo_wr,
wr_data => xhdl14,
rd_en => cmd_fifo_rd,
rd_clk => clk_i,
rd_data => xhdl15,
full => cmd_fifo_full,
almost_full => open,
empty => cmd_fifo_empty
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i;
END IF;
END PROCESS;
u_c_gen : cmd_gen
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
PORT_MODE => PORT_MODE,
MEM_BURST_LEN => MEM_BLEN,
NUM_DQ_PINS => NUM_DQ_PINS,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => ADDR_WIDTH,
DWIDTH => DWIDTH,
MEM_COL_WIDTH => MEM_COL_WIDTH,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
PRBS_SADDR_MASK_POS => PRBS_SADDR_MASK_POS,
PRBS_EADDR => PRBS_EADDR,
PRBS_SADDR => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
rd_buff_avail_i => rd_buff_avail,
reading_rd_data_i => mcb_rd_en,
force_wrcmd_gen_i => force_wrcmd_gen,
run_traffic_i => run_traffic_reg,
start_addr_i => start_addr_i,
end_addr_i => end_addr_r,
cmd_seed_i => cmd_seed_i,
data_seed_i => data_seed_i,
load_seed_i => load_seed_i,
addr_mode_i => addr_mode_i,
data_mode_i => data_mode_r_a,
instr_mode_i => instr_mode_i,
bl_mode_i => bl_mode_i,
mode_load_i => mode_load_i,
fixed_bl_i => fixed_bl_i,
fixed_addr_i => fixed_addr_i,
fixed_instr_i => fixed_instr_i,
bram_addr_i => bram_addr_i,
bram_instr_i => bram_instr_i,
bram_bl_i => bram_bl_i,
bram_valid_i => bram_valid_i,
bram_rdy_o => bram_rdy_o_xhdl0,
rdy_i => flow2cmd_rdy,
instr_o => cmd2flow_cmd,
addr_o => cmd2flow_addr,
bl_o => cmd2flow_bl,
-- m_addr_o => m_addr,
cmd_o_vld => cmd2flow_valid
);
mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
cmd_full <= mcb_cmd_full_i;
mcb_control : mcb_flow_control
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
cmd_rdy_o => flow2cmd_rdy,
cmd_valid_i => cmd2flow_valid,
cmd_i => cmd2flow_cmd,
addr_i => cmd2flow_addr,
bl_i => cmd2flow_bl,
mcb_cmd_full => cmd_full,
cmd_o => mcb_cmd_instr_o_xhdl6,
addr_o => addr_o,
bl_o => mcb_cmd_bl_o_xhdl4,
cmd_en_o => mcb_cmd_en_o_xhdl5,
last_word_wr_i => last_word_wr,
wdp_rdy_i => wr_rdy,
wdp_valid_o => wr_valid,
wdp_validB_o => wr_validB,
wdp_validC_o => wr_validC,
wr_addr_o => wr_addr,
wr_bl_o => wr_bl,
last_word_rd_i => last_word_rd,
rdp_rdy_i => rd_rdy,
rdp_valid_o => rd_valid,
rd_addr_o => rd_addr,
rd_bl_o => rd_bl
);
mdata_wren <= not mcb_rd_empty;
rd_mdata_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_rb(0),
wr_en => mdata_wren,
wr_data => mcb_rd_data_i,
rd_en => mcb_rd_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
almost_full => open,
empty => rd_mdata_fifo_empty
);
cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_rb(0) = '1') THEN
rd_mdata_afull_set <= '0';
ELSIF (rd_mdata_fifo_afull = '1') THEN
rd_mdata_afull_set <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
ELSE
rdpath_data_valid_i <= not(mcb_rd_empty);
END IF;
END PROCESS;
PROCESS(rd_v6_mdata,mcb_rd_data_i)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_rd_data_i <= rd_v6_mdata;
ELSE
rdpath_rd_data_i <= mcb_rd_data_i;
END IF;
END PROCESS;
RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl17 <= NOT(mcb_rd_empty);
read_data_path_inst : read_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
cmp_data_pipe_stages => CMP_DATA_PIPE_STAGES,
addr_width => ADDR_WIDTH,
sel_victim_line => SEL_VICTIM_LINE,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
mem_col_width => MEM_COL_WIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
manual_clear_error => manual_clear_error,
cmd_rdy_o => rd_rdy,
cmd_valid_i => rd_valid,
prbs_fseed_i => data_seed_i,
cmd_sent => mcb_cmd_instr_o_xhdl6,
bl_sent => mcb_cmd_bl_o_xhdl4,
cmd_en_i => cmd_rd_en,
data_mode_i => data_mode_r_b,
last_word_rd_o => last_word_rd,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => rd_addr,
bl_i => rd_bl,
data_rdy_o => mcb_rd_en,
data_valid_i => rdpath_data_valid_i,
data_i => rdpath_rd_data_i,
data_error_o => cmp_error_int,
cmp_data_o => cmp_data_int,
rd_mdata_o => mem_rd_data_i,
cmp_data_valid => cmp_data_valid,
cmp_addr_o => cmp_addr,
cmp_bl_o => cmp_bl,
force_wrcmd_gen_o => force_wrcmd_gen,
rd_buff_avail_o => rd_buff_avail,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
cumlative_dq_lane_error_r => cumlative_dq_lane_error
);
END GENERATE;
write_only_path_inst: IF ( NOT(PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE")) GENERATE
cmp_error_int <= '0';
END GENERATE;
xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl19 <= NOT(mcb_wr_full);
write_data_path_inst : write_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
addr_width => ADDR_WIDTH,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
mem_col_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
cmd_rdy_o => wr_rdy,
cmd_valid_i => wr_valid,
cmd_validb_i => wr_validB,
cmd_validc_i => wr_validC,
prbs_fseed_i => data_seed_i,
data_mode_i => data_mode_r_c,
last_word_wr_o => last_word_wr,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => wr_addr,
bl_i => wr_bl,
data_rdy_i => xhdl19,
data_valid_o => mcb_wr_en,
data_o => mcb_wr_data_o_xhdl9,
data_mask_o => mcb_wr_mask_o_xhdl10,
data_wr_end_o => mcb_wr_data_end_o_xhdl8
-- tpt_hdata =>
);
END GENERATE;
mcb_wr_en_o <= mcb_wr_en;
tg_status_inst : tg_status
GENERIC MAP (
dwidth => DWIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra(2),
manual_clear_error => manual_clear_error,
data_error_i => cmp_error_int,
cmp_data_i => cmp_data_int,
rd_data_i => mem_rd_data_i,
cmp_addr_i => cmp_addr,
cmp_bl_i => cmp_bl,
mcb_cmd_full_i => mcb_cmd_full_i,
mcb_wr_full_i => mcb_wr_full,
mcb_rd_empty_i => mcb_rd_empty,
error_status => error_status_xhdl2,
error => error_xhdl1
);
END trans;
|
gpl-3.0
|
8937cd52aedbc5e52a6e4522f1781230
| 0.499587 | 3.473027 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Filters/FIR.vhd
| 1 | 2,307 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
use work.filter_pkg.all;
entity FIR is
generic (
wordLength : natural := 32;
fractionalBits : natural := 31;
coeffWordLength : natural := 12;
coeffFractionalBits : natural := 11;
sumWordLength : natural := 32;
sumFractionalBits : natural := 31;
outputWordLength : natural := 32;
outputFractionalBits : natural := 31;
order : natural := 6;
coefficients : coefficient_array := (
-0.0390625,
0.0,
0.28759765625,
0.5,
0.28759765625,
0.0,
-0.0390625
)
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(outputWordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
);
end entity ; -- FIR
architecture arch of FIR is
type signalArray is array(0 to order) of std_logic_vector(wordLength-1 downto 0);
type sumArray is array(0 to order) of std_logic_vector(sumWordLength-1 downto 0);
signal inputs : signalArray := (others => (others => '0'));
signal gainedInputs : sumArray := (others => (others => '0'));
signal sums : sumArray := (others => (others => '0'));
begin
inputs(0) <= input;
output <= sums(0)(sumFractionalBits-outputFractionalBits+outputWordLength-1 downto sumFractionalBits-outputFractionalBits);
sums(order) <= gainedInputs(order);
delays : for i in 0 to order-1 generate
-- Delay stages
delay : entity work.VectorRegister
generic map (
wordLength => wordLength
)
port map (
input => inputs(i),
output => inputs(i+1),
clk => clk,
reset => reset
);
-- Output summation
adder : entity work.AdderSat
generic map (
wordLength => sumWordLength
)
port map (
a => gainedInputs(i),
b => sums(i+1),
s => sums(i)
);
end generate ; -- delays
multiplication : for i in 0 to order generate
mult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => fractionalBits,
Y_WIDTH => coeffWordLength,
Y_FRACTION => coeffFractionalBits,
S_WIDTH => sumWordLength,
S_FRACTION => sumFractionalBits
)
port map (
x => inputs(i),
y => real_to_fixed(coefficients(i), coeffWordLength, coeffFractionalBits),
s => gainedInputs(i)
);
end generate;
end architecture ; -- arch
|
mit
|
2235521039ee35c1e8f7a3f220e79a35
| 0.658864 | 3.231092 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/clockman.vhd
| 3 | 2,890 |
----------------------------------------------------------------------------------
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
|
gpl-2.0
|
8c2711d95630d83ccd98383bbd3e74ff
| 0.579585 | 3.695652 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Multiplier_Saturate.vhd
| 1 | 5,130 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- This components takes two inputs ,x and y, and outputs their signed --
-- product on the output s. This component also allows width-scaling of the --
-- output in any direction and size. This sclaling may leed to overflow in --
-- the output. In that case, the output is saturated. --
-- --
-- Generics: --
-- X_WIDTH - Bitwidth of the input x --
-- X_FRACTION - Fractional width of the input x --
-- Y_WIDTH - Bitwidth of the input y --
-- Y_FRACTION - Fractional width of the input y --
-- S_WIDTH - Bitwidth of the output s --
-- S_FRACTION - Fractional width of the output s --
-- --
-- Input/Output: --
-- x - First term. --
-- y - Second term --
-- overflow - Overflow indicator --
-- s - Product --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier_Saturate is
generic (X_WIDTH : natural := 16;
X_FRACTION : natural := 15;
Y_WIDTH : natural := 16;
Y_FRACTION : natural := 15;
S_WIDTH : natural := 16;
S_FRACTION : natural := 15);
port(x : in std_logic_vector(X_WIDTH-1 downto 0);
y : in std_logic_vector(Y_WIDTH-1 downto 0);
overflow : out std_logic;
s : out std_logic_vector(S_WIDTH-1 downto 0));
end Multiplier_Saturate;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Multiplier_Saturate is
-- Constants
constant RESULT_WIDTH : integer := X_WIDTH+Y_WIDTH;
constant LSB : integer := X_FRACTION+Y_FRACTION-S_FRACTION;
constant MSB : integer := X_FRACTION+Y_FRACTION-S_FRACTION+S_WIDTH;
-- Signal Declarations
signal overflow_copy : std_logic;
signal s_product : std_logic_vector(RESULT_WIDTH-1 downto 0);
signal s_output : std_logic_vector(S_WIDTH-1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Calculate product
s_product <= std_logic_vector(signed(x) * signed(y));
-- Map to output
gen_mapping :
for i in 0 to S_WIDTH-1 generate
if_inside :
if(((LSB+i) <= (RESULT_WIDTH-1)) and ((LSB+i) >= (0))) generate
s_output(i) <= s_product(LSB+i);
end generate;
if_above:
if((LSB+i) > (RESULT_WIDTH-1)) generate
s_output(i) <= s_product(RESULT_WIDTH-1);
end generate;
if_under:
if((LSB+i) < (0)) generate
s_output(i) <= '0';
end generate;
end generate;
-- Check for overflow
gen_overflow:
if(MSB < RESULT_WIDTH) generate
process(s_product)
constant ones : std_logic_vector(RESULT_WIDTH downto MSB) := (others => '1');
constant zeroes : std_logic_vector(RESULT_WIDTH downto MSB) := (others => '0');
begin
if((s_product(RESULT_WIDTH-1 downto MSB-1) = zeroes) or (s_product(RESULT_WIDTH-1 downto MSB-1) = ones)) then
overflow_copy <= '0';
else
overflow_copy <= '1';
end if;
end process;
end generate;
gen_no_overflow:
if(MSB >= RESULT_WIDTH) generate
overflow_copy <= '0';
end generate;
overflow <= overflow_copy;
-- Saturate output
process(s_product, overflow_copy, s_output)
begin
if(overflow_copy = '1') then
if(s_product(RESULT_WIDTH-1) = '1') then
s <= (others => '0');
s(S_WIDTH-1) <= '1';
else
s <= (others => '1');
s(S_WIDTH-1) <= '0';
end if;
else
s <= s_output;
end if;
end process;
end behaviour;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
|
mit
|
c3bc3701c7f81cf68129e022054c9984
| 0.388304 | 4.966118 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/stage.vhd
| 4 | 6,303 |
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the input channels
-- can be used as input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be software compensated. (By adjusting the before/after ratio.)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stage is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0);
inputReady : in std_logic;
data : in STD_LOGIC_VECTOR (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in STD_LOGIC;
wrValue : in STD_LOGIC;
wrConfig : in STD_LOGIC;
arm : in std_logic;
level : in STD_LOGIC_VECTOR (1 downto 0);
demuxed : in std_logic;
run : out STD_LOGIC;
match : out STD_LOGIC
);
end stage;
architecture Behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister, configRegister : STD_LOGIC_VECTOR (31 downto 0);
signal intermediateRegister, shiftRegister : STD_LOGIC_VECTOR (31 downto 0);
signal testValue: STD_LOGIC_VECTOR (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : STD_LOGIC;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- assign configuration bits to more meaningful signal names
cfgStart <= configRegister(27);
cfgSerial <= configRegister(26);
cfgChannel <= configRegister(24 downto 20);
cfgLevel <= configRegister(17 downto 16);
cfgDelay <= configRegister(15 downto 0);
-- use shift register or input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= input(i);
serialChannelH16 <= input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever input is ready
process(clock)
begin
if rising_edge(clock) then
if inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if reset = '1' then
state <= OFF;
elsif rising_edge(clock) then
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
configRegister <= data;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
6be9a48f272a5cbdf7aeb64ca1dbd6d9
| 0.667619 | 3.751786 | false | true | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/allocator.vhd
| 1 | 26,855 |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- vc signals
credit_in_vc_N, credit_in_vc_E, credit_in_vc_W, credit_in_vc_S, credit_in_vc_L: in std_logic;
req_N_N_vc, req_N_E_vc, req_N_W_vc, req_N_S_vc, req_N_L_vc: in std_logic;
req_E_N_vc, req_E_E_vc, req_E_W_vc, req_E_S_vc, req_E_L_vc: in std_logic;
req_W_N_vc, req_W_E_vc, req_W_W_vc, req_W_S_vc, req_W_L_vc: in std_logic;
req_S_N_vc, req_S_E_vc, req_S_W_vc, req_S_S_vc, req_S_L_vc: in std_logic;
req_L_N_vc, req_L_E_vc, req_L_W_vc, req_L_S_vc, req_L_L_vc: in std_logic;
empty_vc_N, empty_vc_E, empty_vc_W, empty_vc_S, empty_vc_L: in std_logic;
valid_vc_N, valid_vc_E, valid_vc_W, valid_vc_S, valid_vc_L : out std_logic;
grant_N_N_vc, grant_N_E_vc, grant_N_W_vc, grant_N_S_vc, grant_N_L_vc: out std_logic;
grant_E_N_vc, grant_E_E_vc, grant_E_W_vc, grant_E_S_vc, grant_E_L_vc: out std_logic;
grant_W_N_vc, grant_W_E_vc, grant_W_W_vc, grant_W_S_vc, grant_W_L_vc: out std_logic;
grant_S_N_vc, grant_S_E_vc, grant_S_W_vc, grant_S_S_vc, grant_S_L_vc: out std_logic;
grant_L_N_vc, grant_L_E_vc, grant_L_W_vc, grant_L_S_vc, grant_L_L_vc: out std_logic
);
end allocator;
architecture behavior of allocator is
-- so the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal grant_vc_N, grant_vc_E, grant_vc_W, grant_vc_S, grant_vc_L: std_logic;
signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic;
signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic;
signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic;
signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic;
signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic;
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
signal credit_counter_N_in_vc, credit_counter_N_out_vc: std_logic_vector(1 downto 0);
signal credit_counter_E_in_vc, credit_counter_E_out_vc: std_logic_vector(1 downto 0);
signal credit_counter_W_in_vc, credit_counter_W_out_vc: std_logic_vector(1 downto 0);
signal credit_counter_S_in_vc, credit_counter_S_out_vc: std_logic_vector(1 downto 0);
signal credit_counter_L_in_vc, credit_counter_L_out_vc: std_logic_vector(1 downto 0);
signal X_N_N_vc, X_N_E_vc, X_N_W_vc, X_N_S_vc, X_N_L_vc: std_logic;
signal X_E_N_vc, X_E_E_vc, X_E_W_vc, X_E_S_vc, X_E_L_vc: std_logic;
signal X_W_N_vc, X_W_E_vc, X_W_W_vc, X_W_S_vc, X_W_L_vc: std_logic;
signal X_S_N_vc, X_S_E_vc, X_S_W_vc, X_S_S_vc, X_S_L_vc: std_logic;
signal X_L_N_vc, X_L_E_vc, X_L_W_vc, X_L_S_vc, X_L_L_vc: std_logic;
signal grant_N_N_sig_vc, grant_N_E_sig_vc, grant_N_W_sig_vc, grant_N_S_sig_vc, grant_N_L_sig_vc: std_logic;
signal grant_E_N_sig_vc, grant_E_E_sig_vc, grant_E_W_sig_vc, grant_E_S_sig_vc, grant_E_L_sig_vc: std_logic;
signal grant_W_N_sig_vc, grant_W_E_sig_vc, grant_W_W_sig_vc, grant_W_S_sig_vc, grant_W_L_sig_vc: std_logic;
signal grant_S_N_sig_vc, grant_S_E_sig_vc, grant_S_W_sig_vc, grant_S_S_sig_vc, grant_S_L_sig_vc: std_logic;
signal grant_L_N_sig_vc, grant_L_E_sig_vc, grant_L_W_sig_vc, grant_L_S_sig_vc, grant_L_L_sig_vc: std_logic;
signal req_N_N_tmp, req_N_E_tmp, req_N_W_tmp, req_N_S_tmp, req_N_L_tmp: std_logic;
signal req_E_N_tmp, req_E_E_tmp, req_E_W_tmp, req_E_S_tmp, req_E_L_tmp: std_logic;
signal req_W_N_tmp, req_W_E_tmp, req_W_W_tmp, req_W_S_tmp, req_W_L_tmp: std_logic;
signal req_S_N_tmp, req_S_E_tmp, req_S_W_tmp, req_S_S_tmp, req_S_L_tmp: std_logic;
signal req_L_N_tmp, req_L_E_tmp, req_L_W_tmp, req_L_S_tmp, req_L_L_tmp: std_logic;
component arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L:in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L:out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
component arbiter_out is
port ( reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y:in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L :out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
begin
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= (others=>'1');
credit_counter_E_out <= (others=>'1');
credit_counter_W_out <= (others=>'1');
credit_counter_S_out <= (others=>'1');
credit_counter_L_out <= (others=>'1');
credit_counter_N_out_vc <= (others=>'1');
credit_counter_E_out_vc <= (others=>'1');
credit_counter_W_out_vc <= (others=>'1');
credit_counter_S_out_vc <= (others=>'1');
credit_counter_L_out_vc <= (others=>'1');
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
credit_counter_N_out_vc <= credit_counter_N_in_vc;
credit_counter_E_out_vc <= credit_counter_E_in_vc;
credit_counter_W_out_vc <= credit_counter_W_in_vc;
credit_counter_S_out_vc <= credit_counter_S_in_vc;
credit_counter_L_out_vc <= credit_counter_L_in_vc;
end if;
end process;
-- The combionational part
req_N_N_tmp <= req_N_N;
req_N_E_tmp <= req_N_E;
req_N_W_tmp <= req_N_W;
req_N_S_tmp <= req_N_S;
req_N_L_tmp <= req_N_L;
req_E_N_tmp <= req_E_N;
req_E_E_tmp <= req_E_E;
req_E_W_tmp <= req_E_W;
req_E_S_tmp <= req_E_S;
req_E_L_tmp <= req_E_L;
req_W_N_tmp <= req_W_N;
req_W_E_tmp <= req_W_E;
req_W_W_tmp <= req_W_W;
req_W_S_tmp <= req_W_S;
req_W_L_tmp <= req_W_L;
req_S_N_tmp <= req_S_N;
req_S_E_tmp <= req_S_E;
req_S_W_tmp <= req_S_W;
req_S_S_tmp <= req_S_S;
req_S_L_tmp <= req_S_L;
req_L_N_tmp <= req_L_N;
req_L_E_tmp <= req_L_E;
req_L_W_tmp <= req_L_W;
req_L_S_tmp <= req_L_S;
req_L_L_tmp <= req_L_L;
grant_N_N <= grant_N_N_sig and not empty_N and not grant_vc_N;
grant_N_E <= grant_N_E_sig and not empty_E and not grant_vc_N;
grant_N_W <= grant_N_W_sig and not empty_W and not grant_vc_N;
grant_N_S <= grant_N_S_sig and not empty_S and not grant_vc_N;
grant_N_L <= grant_N_L_sig and not empty_L and not grant_vc_N;
grant_E_N <= grant_E_N_sig and not empty_N and not grant_vc_E;
grant_E_E <= grant_E_E_sig and not empty_E and not grant_vc_E;
grant_E_W <= grant_E_W_sig and not empty_W and not grant_vc_E;
grant_E_S <= grant_E_S_sig and not empty_S and not grant_vc_E;
grant_E_L <= grant_E_L_sig and not empty_L and not grant_vc_E;
grant_W_N <= grant_W_N_sig and not empty_N and not grant_vc_W;
grant_W_E <= grant_W_E_sig and not empty_E and not grant_vc_W;
grant_W_W <= grant_W_W_sig and not empty_W and not grant_vc_W;
grant_W_S <= grant_W_S_sig and not empty_S and not grant_vc_W;
grant_W_L <= grant_W_L_sig and not empty_L and not grant_vc_W;
grant_S_N <= grant_S_N_sig and not empty_N and not grant_vc_S;
grant_S_E <= grant_S_E_sig and not empty_E and not grant_vc_S;
grant_S_W <= grant_S_W_sig and not empty_W and not grant_vc_S;
grant_S_S <= grant_S_S_sig and not empty_S and not grant_vc_S;
grant_S_L <= grant_S_L_sig and not empty_L and not grant_vc_S;
grant_L_N <= grant_L_N_sig and not empty_N and not grant_vc_L;
grant_L_E <= grant_L_E_sig and not empty_E and not grant_vc_L;
grant_L_W <= grant_L_W_sig and not empty_W and not grant_vc_L;
grant_L_S <= grant_L_S_sig and not empty_S and not grant_vc_L;
grant_L_L <= grant_L_L_sig and not empty_L and not grant_vc_L;
grant_N <= ((grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L))and not grant_vc_N;
grant_E <= ((grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L))and not grant_vc_E;
grant_W <= ((grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L))and not grant_vc_W;
grant_S <= ((grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L))and not grant_vc_S;
grant_L <= ((grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L))and not grant_vc_L;
-- this process handels the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
arb_N_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N_tmp, Req_X_E=> req_N_E_tmp, Req_X_W=>req_N_W_tmp, Req_X_S=>req_N_S_tmp, Req_X_L=>req_N_L_tmp,
X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L);
arb_E_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N_tmp, Req_X_E=> req_E_E_tmp, Req_X_W=>req_E_W_tmp, Req_X_S=>req_E_S_tmp, Req_X_L=>req_E_L_tmp,
X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L);
arb_W_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N_tmp, Req_X_E=> req_W_E_tmp, Req_X_W=>req_W_W_tmp, Req_X_S=>req_W_S_tmp, Req_X_L=>req_W_L_tmp,
X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L);
arb_S_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N_tmp, Req_X_E=> req_S_E_tmp, Req_X_W=>req_S_W_tmp, Req_X_S=>req_S_S_tmp, Req_X_L=>req_S_L_tmp,
X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L);
arb_L_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N_tmp, Req_X_E=> req_L_E_tmp, Req_X_W=>req_L_W_tmp, Req_X_S=>req_L_S_tmp, Req_X_L=>req_L_L_tmp,
X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L);
-- Y is N now
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig,
grant_Y_E => grant_N_E_sig,
grant_Y_W => grant_N_W_sig,
grant_Y_S => grant_N_S_sig,
grant_Y_L => grant_N_L_sig);
-- Y is E now
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig,
grant_Y_E => grant_E_E_sig,
grant_Y_W => grant_E_W_sig,
grant_Y_S => grant_E_S_sig,
grant_Y_L => grant_E_L_sig);
-- Y is W now
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig,
grant_Y_E => grant_W_E_sig,
grant_Y_W => grant_W_W_sig,
grant_Y_S => grant_W_S_sig,
grant_Y_L => grant_W_L_sig);
-- Y is S now
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig,
grant_Y_E => grant_S_E_sig,
grant_Y_W => grant_S_W_sig,
grant_Y_S => grant_S_S_sig,
grant_Y_L => grant_S_L_sig);
-- Y is L now
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig,
grant_Y_E => grant_L_E_sig,
grant_Y_W => grant_L_W_sig,
grant_Y_S => grant_L_S_sig,
grant_Y_L => grant_L_L_sig);
valid_N <= grant_N and not grant_vc_N;
valid_E <= grant_E and not grant_vc_E;
valid_W <= grant_W and not grant_vc_W;
valid_S <= grant_S and not grant_vc_S;
valid_L <= grant_L and not grant_vc_L;
-- VC part
grant_N_N_vc <= grant_N_N_sig_vc and not empty_vc_N;
grant_N_E_vc <= grant_N_E_sig_vc and not empty_vc_E;
grant_N_W_vc <= grant_N_W_sig_vc and not empty_vc_W;
grant_N_S_vc <= grant_N_S_sig_vc and not empty_vc_S;
grant_N_L_vc <= grant_N_L_sig_vc and not empty_vc_L;
grant_E_N_vc <= grant_E_N_sig_vc and not empty_vc_N;
grant_E_E_vc <= grant_E_E_sig_vc and not empty_vc_E;
grant_E_W_vc <= grant_E_W_sig_vc and not empty_vc_W;
grant_E_S_vc <= grant_E_S_sig_vc and not empty_vc_S;
grant_E_L_vc <= grant_E_L_sig_vc and not empty_vc_L;
grant_W_N_vc <= grant_W_N_sig_vc and not empty_vc_N;
grant_W_E_vc <= grant_W_E_sig_vc and not empty_vc_E;
grant_W_W_vc <= grant_W_W_sig_vc and not empty_vc_W;
grant_W_S_vc <= grant_W_S_sig_vc and not empty_vc_S;
grant_W_L_vc <= grant_W_L_sig_vc and not empty_vc_L;
grant_S_N_vc <= grant_S_N_sig_vc and not empty_vc_N;
grant_S_E_vc <= grant_S_E_sig_vc and not empty_vc_E;
grant_S_W_vc <= grant_S_W_sig_vc and not empty_vc_W;
grant_S_S_vc <= grant_S_S_sig_vc and not empty_vc_S;
grant_S_L_vc <= grant_S_L_sig_vc and not empty_vc_L;
grant_L_N_Vc <= grant_L_N_sig_vc and not empty_vc_N;
grant_L_E_Vc <= grant_L_E_sig_vc and not empty_vc_E;
grant_L_W_Vc <= grant_L_W_sig_vc and not empty_vc_W;
grant_L_S_Vc <= grant_L_S_sig_vc and not empty_vc_S;
grant_L_L_Vc <= grant_L_L_sig_vc and not empty_vc_L;
grant_vc_N <= (grant_N_N_sig_vc and not empty_vc_N )or (grant_N_E_sig_vc and not empty_vc_E) or (grant_N_W_sig_vc and not empty_vc_W) or (grant_N_S_sig_vc and not empty_vc_S) or (grant_N_L_sig_vc and not empty_vc_L);
grant_vc_E <= (grant_E_N_sig_vc and not empty_vc_N )or (grant_E_E_sig_vc and not empty_vc_E) or (grant_E_W_sig_vc and not empty_vc_W) or (grant_E_S_sig_vc and not empty_vc_S) or (grant_E_L_sig_vc and not empty_vc_L);
grant_vc_W <= (grant_W_N_sig_vc and not empty_vc_N )or (grant_W_E_sig_vc and not empty_vc_E) or (grant_W_W_sig_vc and not empty_vc_W) or (grant_W_S_sig_vc and not empty_vc_S) or (grant_W_L_sig_vc and not empty_vc_L);
grant_vc_S <= (grant_S_N_sig_vc and not empty_vc_N )or (grant_S_E_sig_vc and not empty_vc_E) or (grant_S_W_sig_vc and not empty_vc_W) or (grant_S_S_sig_vc and not empty_vc_S) or (grant_S_L_sig_vc and not empty_vc_L);
grant_vc_L <= (grant_L_N_sig_vc and not empty_vc_N )or (grant_L_E_sig_vc and not empty_vc_E) or (grant_L_W_sig_vc and not empty_vc_W) or (grant_L_S_sig_vc and not empty_vc_S) or (grant_L_L_sig_vc and not empty_vc_L);
-- this process handels the credit counters!
process(credit_in_vc_N, credit_in_vc_E, credit_in_vc_W, credit_in_vc_S, credit_in_vc_L, grant_vc_N, grant_vc_E, grant_vc_W, grant_vc_S, grant_vc_L,
credit_counter_N_out_vc, credit_counter_E_out_vc, credit_counter_W_out_vc, credit_counter_S_out_vc, credit_counter_L_out_vc
)
begin
credit_counter_N_in_vc <= credit_counter_N_out_vc;
credit_counter_E_in_vc <= credit_counter_E_out_vc;
credit_counter_W_in_vc <= credit_counter_W_out_vc;
credit_counter_S_in_vc <= credit_counter_S_out_vc;
credit_counter_L_in_vc <= credit_counter_L_out_vc;
if credit_in_vc_N = '1' and grant_vc_N = '1' then
credit_counter_N_in_vc <= credit_counter_N_out_vc;
elsif credit_in_vc_N = '1' and credit_counter_N_out_vc < 3 then
credit_counter_N_in_vc <= credit_counter_N_out_vc + 1;
elsif grant_vc_N = '1' and credit_counter_N_out_vc > 0 then
credit_counter_N_in_vc <= credit_counter_N_out_vc - 1;
end if;
if credit_in_vc_E = '1' and grant_vc_E = '1' then
credit_counter_E_in_vc <= credit_counter_E_out_vc;
elsif credit_in_vc_E = '1' and credit_counter_E_out_vc < 3 then
credit_counter_E_in_vc <= credit_counter_E_out_vc + 1;
elsif grant_vc_E = '1' and credit_counter_E_out_vc > 0 then
credit_counter_E_in_vc <= credit_counter_E_out_vc - 1;
end if;
if credit_in_vc_W = '1' and grant_vc_W = '1' then
credit_counter_W_in_vc <= credit_counter_W_out_vc;
elsif credit_in_vc_W = '1' and credit_counter_W_out_vc < 3 then
credit_counter_W_in_vc <= credit_counter_W_out_vc + 1;
elsif grant_vc_W = '1' and credit_counter_W_out_vc > 0 then
credit_counter_W_in_vc <= credit_counter_W_out_vc - 1;
end if;
if credit_in_vc_S = '1' and grant_vc_S = '1' then
credit_counter_S_in_vc <= credit_counter_S_out_vc;
elsif credit_in_vc_S = '1' and credit_counter_S_out_vc < 3 then
credit_counter_S_in_vc <= credit_counter_S_out_vc + 1;
elsif grant_vc_S = '1' and credit_counter_S_out_vc > 0 then
credit_counter_S_in_vc <= credit_counter_S_out_vc - 1;
end if;
if credit_in_vc_L = '1' and grant_vc_L = '1' then
credit_counter_L_in_vc <= credit_counter_L_out_vc;
elsif credit_in_vc_L = '1' and credit_counter_L_out_vc < 3 then
credit_counter_L_in_vc <= credit_counter_L_out_vc + 1;
elsif grant_vc_L = '1' and credit_counter_L_out_vc > 0 then
credit_counter_L_in_vc <= credit_counter_L_out_vc - 1;
end if;
end process;
arb_N_X_vc: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N_vc, Req_X_E=> req_N_E_vc, Req_X_W=>req_N_W_vc, Req_X_S=>req_N_S_vc, Req_X_L=>req_N_L_vc,
X_N=>X_N_N_vc, X_E=>X_N_E_vc, X_W=>X_N_W_vc, X_S=>X_N_S_vc, X_L=>X_N_L_vc);
arb_E_X_vc: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N_vc, Req_X_E=> req_E_E_vc, Req_X_W=>req_E_W_vc, Req_X_S=>req_E_S_vc, Req_X_L=>req_E_L_vc,
X_N=>X_E_N_vc, X_E=>X_E_E_vc, X_W=>X_E_W_vc, X_S=>X_E_S_vc, X_L=>X_E_L_vc);
arb_W_X_vc: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N_vc, Req_X_E=> req_W_E_vc, Req_X_W=>req_W_W_vc, Req_X_S=>req_W_S_vc, Req_X_L=>req_W_L_vc,
X_N=>X_W_N_vc, X_E=>X_W_E_vc, X_W=>X_W_W_vc, X_S=>X_W_S_vc, X_L=>X_W_L_vc);
arb_S_X_vc: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N_vc, Req_X_E=> req_S_E_vc, Req_X_W=>req_S_W_vc, Req_X_S=>req_S_S_vc, Req_X_L=>req_S_L_vc,
X_N=>X_S_N_vc, X_E=>X_S_E_vc, X_W=>X_S_W_vc, X_S=>X_S_S_vc, X_L=>X_S_L_vc);
arb_L_X_vc: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N_vc, Req_X_E=> req_L_E_vc, Req_X_W=>req_L_W_vc, Req_X_S=>req_L_S_vc, Req_X_L=>req_L_L_vc,
X_N=>X_L_N_vc, X_E=>X_L_E_vc, X_W=>X_L_W_vc, X_S=>X_L_S_vc, X_L=>X_L_L_vc);
-- Y is N now
arb_X_N_vc: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N_vc, X_E_Y => X_E_N_vc, X_W_Y => X_W_N_vc, X_S_Y => X_S_N_vc, X_L_Y => X_L_N_vc,
credit => credit_counter_N_out_vc,
grant_Y_N => grant_N_N_sig_vc,
grant_Y_E => grant_N_E_sig_vc,
grant_Y_W => grant_N_W_sig_vc,
grant_Y_S => grant_N_S_sig_vc,
grant_Y_L => grant_N_L_sig_vc);
-- Y is E now
arb_X_E_vc: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E_vc, X_E_Y => X_E_E_vc, X_W_Y => X_W_E_vc, X_S_Y => X_S_E_vc, X_L_Y => X_L_E_vc,
credit => credit_counter_E_out_vc,
grant_Y_N => grant_E_N_sig_vc,
grant_Y_E => grant_E_E_sig_vc,
grant_Y_W => grant_E_W_sig_vc,
grant_Y_S => grant_E_S_sig_vc,
grant_Y_L => grant_E_L_sig_vc);
-- Y is W now
arb_X_W_vc: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W_vc, X_E_Y => X_E_W_vc, X_W_Y => X_W_W_vc, X_S_Y => X_S_W_vc, X_L_Y => X_L_W_vc,
credit => credit_counter_W_out_vc,
grant_Y_N => grant_W_N_sig_vc,
grant_Y_E => grant_W_E_sig_vc,
grant_Y_W => grant_W_W_sig_vc,
grant_Y_S => grant_W_S_sig_vc,
grant_Y_L => grant_W_L_sig_vc);
-- Y is S now
arb_X_S_vc: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S_vc, X_E_Y => X_E_S_vc, X_W_Y => X_W_S_vc, X_S_Y => X_S_S_vc, X_L_Y => X_L_S_vc,
credit => credit_counter_S_out_vc,
grant_Y_N => grant_S_N_sig_vc,
grant_Y_E => grant_S_E_sig_vc,
grant_Y_W => grant_S_W_sig_vc,
grant_Y_S => grant_S_S_sig_vc,
grant_Y_L => grant_S_L_sig_vc);
-- Y is L now
arb_X_L_vc: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L_vc, X_E_Y => X_E_L_vc, X_W_Y => X_W_L_vc, X_S_Y => X_S_L_vc, X_L_Y => X_L_L_vc,
credit => credit_counter_L_out_vc,
grant_Y_N => grant_L_N_sig_vc,
grant_Y_E => grant_L_E_sig_vc,
grant_Y_W => grant_L_W_sig_vc,
grant_Y_S => grant_L_S_sig_vc,
grant_Y_L => grant_L_L_sig_vc);
valid_vc_N <= grant_vc_N;
valid_vc_E <= grant_vc_E;
valid_vc_W <= grant_vc_W;
valid_vc_S <= grant_vc_S;
valid_vc_L <= grant_vc_L;
END;
|
gpl-3.0
|
17648da2c2a4235152c7cd002669f675
| 0.557066 | 2.355495 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
eth_add_crc.vhd
| 1 | 6,267 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
--------------------------------------------------------------------------------
-- Csum calculations (the big XOR mapping) copied from:
-- CRC GENERATOR
--
-- @author Peter A Bennett
-- @copyright (c) 2012 Peter A Bennett
-- @version $Rev: 2 $
-- @lastrevision $Date: 2012-03-11 15:19:25 +0000 (Sun, 11 Mar 2012) $
-- @license LGPL
-- @email [email protected]
-- @contact www.bytebash.com
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Ethernet CRC module
-- Calculate and append CRC of data flowing through Bus
-- Data must begin with 802.3 Preamble + SFD, CRC calc start on first byte after SFD
-- CRC is glued after data, Pkt signal is continuous
--
-- WARNING: Pkt signal must be (and is kept) continuous
entity eth_add_crc is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
InPkt : in STD_LOGIC;
InData : in STD_LOGIC_VECTOR (7 downto 0);
OutPkt : out STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (7 downto 0));
end eth_add_crc;
architecture Behavioral of eth_add_crc is
type state_t is (IDLE, CALC, APPEND);
signal state : state_t;
signal NEXT_state : state_t;
signal c, csum, NEXT_csum : STD_LOGIC_VECTOR (0 to 31);
signal SHIFT_csum : STD_LOGIC_VECTOR (0 to 31);
signal d : STD_LOGIC_VECTOR (0 to 7);
signal cnt, NEXT_cnt : integer range 0 to 3;
begin
c <= csum;
d <= InData;
fsm: process (state, cnt, InData, InPkt, d, c, csum, SHIFT_csum)
begin
SHIFT_csum(0) <= d(6) xor d(0) xor c(24) xor c(30);
SHIFT_csum(1) <= d(7) xor d(6) xor d(1) xor d(0) xor c(24) xor c(25) xor c(30) xor c(31);
SHIFT_csum(2) <= d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31);
SHIFT_csum(3) <= d(7) xor d(3) xor d(2) xor d(1) xor c(25) xor c(26) xor c(27) xor c(31);
SHIFT_csum(4) <= d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30);
SHIFT_csum(5) <= d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31);
SHIFT_csum(6) <= d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31);
SHIFT_csum(7) <= d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31);
SHIFT_csum(8) <= d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(24) xor c(25) xor c(27) xor c(28);
SHIFT_csum(9) <= d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(25) xor c(26) xor c(28) xor c(29);
SHIFT_csum(10) <= d(5) xor d(3) xor d(2) xor d(0) xor c(2) xor c(24) xor c(26) xor c(27) xor c(29);
SHIFT_csum(11) <= d(4) xor d(3) xor d(1) xor d(0) xor c(3) xor c(24) xor c(25) xor c(27) xor c(28);
SHIFT_csum(12) <= d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30);
SHIFT_csum(13) <= d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31);
SHIFT_csum(14) <= d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31);
SHIFT_csum(15) <= d(7) xor d(5) xor d(4) xor d(3) xor c(7) xor c(27) xor c(28) xor c(29) xor c(31);
SHIFT_csum(16) <= d(5) xor d(4) xor d(0) xor c(8) xor c(24) xor c(28) xor c(29);
SHIFT_csum(17) <= d(6) xor d(5) xor d(1) xor c(9) xor c(25) xor c(29) xor c(30);
SHIFT_csum(18) <= d(7) xor d(6) xor d(2) xor c(10) xor c(26) xor c(30) xor c(31);
SHIFT_csum(19) <= d(7) xor d(3) xor c(11) xor c(27) xor c(31);
SHIFT_csum(20) <= d(4) xor c(12) xor c(28);
SHIFT_csum(21) <= d(5) xor c(13) xor c(29);
SHIFT_csum(22) <= d(0) xor c(14) xor c(24);
SHIFT_csum(23) <= d(6) xor d(1) xor d(0) xor c(15) xor c(24) xor c(25) xor c(30);
SHIFT_csum(24) <= d(7) xor d(2) xor d(1) xor c(16) xor c(25) xor c(26) xor c(31);
SHIFT_csum(25) <= d(3) xor d(2) xor c(17) xor c(26) xor c(27);
SHIFT_csum(26) <= d(6) xor d(4) xor d(3) xor d(0) xor c(18) xor c(24) xor c(27) xor c(28) xor c(30);
SHIFT_csum(27) <= d(7) xor d(5) xor d(4) xor d(1) xor c(19) xor c(25) xor c(28) xor c(29) xor c(31);
SHIFT_csum(28) <= d(6) xor d(5) xor d(2) xor c(20) xor c(26) xor c(29) xor c(30);
SHIFT_csum(29) <= d(7) xor d(6) xor d(3) xor c(21) xor c(27) xor c(30) xor c(31);
SHIFT_csum(30) <= d(7) xor d(4) xor c(22) xor c(28) xor c(31);
SHIFT_csum(31) <= d(5) xor c(23) xor c(29);
NEXT_state <= state;
NEXT_cnt <= cnt + 1;
NEXT_csum <= SHIFT_csum;
OutData <= InData;
OutPkt <= InPkt;
case state is
when IDLE =>
NEXT_csum <= X"FFffFFff";
if InPkt = '1' and InData(7 downto 4) = X"d" then
NEXT_state <= CALC;
end if;
when CALC =>
NEXT_cnt <= 0;
if InPkt = '0' then
NEXT_state <= APPEND;
NEXT_cnt <= 1;
OutPkt <= '1';
NEXT_csum <= csum;
OutData <= not csum(24 to 31);
end if;
when APPEND =>
NEXT_csum <= csum;
OutData <= not csum(24 - cnt*8 to 31 - cnt*8);
OutPkt <= '1';
if cnt = 3 then
NEXT_state <= IDLE;
end if;
when others =>
NEXT_state <= IDLE;
end case;
end process;
fsm_next: process (Clk)
begin
if RISING_EDGE(Clk) then
state <= NEXT_state;
cnt <= NEXT_cnt;
csum <= NEXT_csum;
if rst = '1' then
state <= IDLE;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
d10a1c01bf0c0f9b9daa6a5b3d5233a2
| 0.575395 | 2.446136 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/arbiter_out.vhd
| 12 | 4,006 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
gpl-3.0
|
893ebb71d66e4f8831b49ecdef27033c
| 0.421118 | 3.338333 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
bus_get_last_nbits.vhd
| 1 | 1,963 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity bus_get_last_nbits is
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
Value : out std_logic_vector(N_BITS - 1 downto 0);
ValueEn : out std_logic);
end bus_get_last_nbits;
architecture Behavioral of bus_get_last_nbits is
constant N_BYTES : integer := (N_BITS - 1)/8 + 1;
type byte_vec is array (0 to N_BYTES) of std_logic_vector(7 downto 0);
signal delayByte : byte_vec;
signal delayPkt : std_logic_vector(0 to N_BYTES);
begin
delayByte(0) <= DataIn when rising_edge(Clk);
delayPkt(0) <= PktIn when rising_edge(Clk);
delay_path : for i in 0 to N_BYTES - 1
generate
delayByte(i + 1) <= delayByte(i) when rising_edge(Clk);
delayPkt(i + 1) <= delayPkt(i) when rising_edge(Clk);
end generate delay_path;
output_path : for i in 0 to N_BITS - 1
generate
Value(i) <= delayByte(1 + i/8)(i mod 8);
end generate output_path;
ValueEn <= (not delayPkt(0)) and delayPkt(1) and (not Rst);
end Behavioral;
|
gpl-3.0
|
7e7793c6abb14ec327582d00cc5219a6
| 0.662761 | 3.505357 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
reg.vhd
| 1 | 2,921 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- register on a register bus
entity reg is
generic (REG_BYTES : integer;
DEFAULT_VALUE : integer := 0;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : out std_logic_vector(REG_BYTES*8 - 1 downto 0));
end reg;
-- Operation:
-- Hold the @Value. Access it when address on the bus matches @REG_ADDR_BASE.
-- Writes are atomic - @Value is changed only when address on the bus is out of
-- the range of addresses of this register.
-- Writes to register must be 'clock-in-clock' to ensure atomicity of the value.
architecture Behavioral of reg is
constant OFFSET_LEN : integer := integer(ceil(log2(real(REG_BYTES))));
constant REG_BITS : integer := REG_BYTES*8;
subtype OffsetRange is natural range OFFSET_LEN - 1 downto 0;
subtype AddrRange is natural range REG_ADDR_W - 1 downto OFFSET_LEN;
signal offset : integer;
signal bus_addr, reg_addr : std_logic_vector(AddrRange);
signal v_atomic, v_new : std_logic_vector(REG_BITS - 1 downto 0) := CONV_std_logic_vector(DEFAULT_VALUE, REG_BITS);
begin
offset <= CONV_integer(RegBusI.addr(OffsetRange));
bus_addr <= RegBusI.addr(AddrRange);
reg_addr <= REG_ADDR_BASE(AddrRange);
Value <= v_atomic;
update : process (Clk)
begin
if rising_edge(Clk) then
RegBusO <= RegBusI;
if bus_addr = reg_addr then
if RegBusI.wr = '1' then
v_new(7 + offset*8 downto offset*8) <= RegBusI.data;
else
RegBusO.data <= v_atomic(7 + offset*8 downto offset*8);
end if;
else
v_atomic <= v_new;
end if;
if Rst = '1' then
v_new <= CONV_std_logic_vector(DEFAULT_VALUE, REG_BITS);
RegBusO.addr <= reg_addr_invl;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
7f822a7760f7152ce60b5e55251584a5
| 0.627182 | 3.749679 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/generic_async_fifo_wrapper.vhd
| 1 | 6,159 |
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Generic asynchronous FIFO wrapper
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: generic_async_fifo (generic_async_fifo_wrapper.vhd)
--
-- author: Matthieu Cattin ([email protected])
--
-- date: 05-12-2011
--
-- version: 1.0
--
-- description: Wrapper to use Xilinx Coregen FIFOs instead of generic FIFOs
-- from Generics RAMs and FIFOs collection.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library work;
use work.gn4124_core_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component fifo_32x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_32x512;
component fifo_64x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_64x512;
signal rst : std_logic;
begin
-- Active high reset for FIFOs
rst <= not(rst_n_i);
-- Assign unused outputs
wr_empty_o <= '0';
wr_almost_empty_o <= '0';
wr_count_o <= (others => '0');
rd_full_o <= '0';
rd_almost_full_o <= '0';
rd_almost_empty_o <= '0';
rd_count_o <= (others => '0');
gen_fifo_32bit : if g_data_width = 32 generate
cmp_fifo_32x512 : fifo_32x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 10)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_32bit;
gen_fifo_64bit : if g_data_width = 64 generate
cmp_fifo_64x512 : fifo_64x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_64bit;
end syn;
|
gpl-3.0
|
54dce8cb7e53cde432073a0b8a03740d
| 0.468095 | 3.683612 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Utilities/ClockDivider.vhd
| 2 | 1,143 |
-- We might change this to a special implementation in the FPGA later, but you
-- can still use this block for simulation and implementation since we'll only
-- change the architecture of this block.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity ClockDivider is
generic (
divider : natural := 2
);
port (
reset : in std_logic;
clk : in std_logic;
clkOut : out std_logic
);
end entity ; -- ClockDivider
architecture arch of ClockDivider is
type reg_type is record
value : natural range 0 to divider-1;
output : std_logic;
end record;
signal r, rin : reg_type;
begin
clkOut <= r.output;
clk_proc : process( clk, reset )
begin
if(reset = '1') then
r.value <= 0;
r.output <= '0';
elsif(rising_edge(clk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin )
variable v : reg_type;
begin
v := r;
if(r.value = 0) then
v.output := '1';
else
v.output := '0';
end if;
if(v.value = divider-1) then
v.value := 0;
else
v.value := r.value + 1;
end if;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
e6ebbe8f442f3ec29be031cc77d2b125
| 0.63867 | 2.923274 | false | false | false | false |
makestuff/umdkv2
|
vhdl/mem-arbiter/tb_unit/mem_arbiter_tb.vhdl
| 1 | 9,287 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
use work.mem_ctrl_pkg.all;
entity mem_arbiter_tb is
end entity;
architecture behavioural of mem_arbiter_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
-- I/O pipes
signal cmdData : std_logic_vector(15 downto 0);
signal cmdValid : std_logic;
signal cmdReady : std_logic;
signal rspData : std_logic_vector(15 downto 0);
signal rspValid : std_logic;
signal rspReady : std_logic;
-- Pipe interface
signal ppReady : std_logic;
signal ppCmd : MCCmdType;
signal ppAddr : std_logic_vector(22 downto 0);
signal ppDataWr : std_logic_vector(15 downto 0);
signal ppDataRd : std_logic_vector(15 downto 0);
signal ppRDV : std_logic;
-- Memory controller interface
signal mcAutoMode : std_logic;
signal mcReady : std_logic;
signal mcCmd : MCCmdType;
signal mcAddr : std_logic_vector(22 downto 0);
signal mcDataWr : std_logic_vector(15 downto 0);
signal mcDataRd : std_logic_vector(15 downto 0);
signal mcRDV : std_logic;
-- SDRAM signals
signal ramCmd : std_logic_vector(2 downto 0);
signal ramBank : std_logic_vector(1 downto 0);
signal ramAddr : std_logic_vector(11 downto 0);
signal ramDataIO : std_logic_vector(15 downto 0);
signal ramLDQM : std_logic;
signal ramUDQM : std_logic;
-- MegaDrive external interface
signal mdDriveBus : std_logic;
signal mdReset : std_logic;
signal mdDTACK : std_logic;
signal mdAddr : std_logic_vector(22 downto 0);
signal mdData : std_logic_vector(15 downto 0);
signal mdOE : std_logic;
signal mdAS : std_logic;
signal mdLDSW : std_logic;
signal mdUDSW : std_logic;
-- Trace pipe
signal traceEnable : std_logic;
signal traceData : std_logic_vector(71 downto 0);
signal traceValid : std_logic;
-- MegaDrive registers
signal regAddr : std_logic_vector(2 downto 0);
signal regWrData : std_logic_vector(15 downto 0);
signal regWrValid : std_logic;
signal regRdData : std_logic_vector(15 downto 0);
signal regRdStrobe : std_logic;
begin
-- Instantiate the memory pipe
mem_pipe: entity work.mem_pipe
port map(
clk_in => sysClk,
reset_in => reset,
-- I/O pipes
cmdData_in => cmdData,
cmdValid_in => cmdValid,
cmdReady_out => cmdReady,
rspData_out => rspData,
rspValid_out => rspValid,
rspReady_in => rspReady,
-- Connection to mem_arbiter
mcReady_in => ppReady,
mcCmd_out => ppCmd,
mcAddr_out => ppAddr,
mcData_out => ppDataWr,
mcData_in => ppDataRd,
mcRDV_in => ppRDV
);
-- Instantiate the memory arbiter for testing
uut: entity work.mem_arbiter
port map(
clk_in => sysClk,
reset_in => reset,
-- Connetion to mem_pipe
ppReady_out => ppReady,
ppCmd_in => ppCmd,
ppAddr_in => ppAddr,
ppData_in => ppDataWr,
ppData_out => ppDataRd,
ppRDV_out => ppRDV,
-- Connection to mem_ctrl
mcAutoMode_out => mcAutoMode,
mcReady_in => mcReady,
mcCmd_out => mcCmd,
mcAddr_out => mcAddr,
mcData_out => mcDataWr,
mcData_in => mcDataRd,
mcRDV_in => mcRDV,
-- Connection to MegaDrive
mdDriveBus_out => mdDriveBus,
mdReset_in => mdReset,
mdDTACK_out => mdDTACK,
mdAddr_in => mdAddr,
mdData_io => mdData,
mdOE_in => mdOE,
mdAS_in => mdAS,
mdLDSW_in => mdLDSW,
mdUDSW_in => mdUDSW,
-- Trace pipe
traceEnable_in => traceEnable,
traceData_out => traceData,
traceValid_out => traceValid,
-- MegaDrive registers
regAddr_out => regAddr,
regWrData_out => regWrData,
regWrValid_out => regWrValid,
regRdData_in => regRdData,
regRdStrobe_out => regRdStrobe
);
-- Instantiate the memory controller
mem_ctrl: entity work.mem_ctrl
generic map(
INIT_COUNT => "0" & x"004", --\
REFRESH_DELAY => "0" & x"010", -- Much longer in real hardware!
REFRESH_LENGTH => "0" & x"002" --/
)
port map(
clk_in => sysClk,
reset_in => reset,
-- Connection to mem_arbiter
mcAutoMode_in => mcAutoMode,
mcReady_out => mcReady,
mcCmd_in => mcCmd,
mcAddr_in => mcAddr,
mcData_in => mcDataWr,
mcData_out => mcDataRd,
mcRDV_out => mcRDV,
-- Connection to sdram_model
ramCmd_out => ramCmd,
ramBank_out => ramBank,
ramAddr_out => ramAddr,
ramData_io => ramDataIO,
ramLDQM_out => ramLDQM,
ramUDQM_out => ramUDQM
);
-- Instantiate the SDRAM model for testing
sdram_model: entity work.sdram_model
port map(
ramClk_in => sysClk,
ramCmd_in => ramCmd,
ramBank_in => ramBank,
ramAddr_in => ramAddr,
ramData_io => ramDataIO
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset one cycle after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
procedure cmdWord(constant w : in std_logic_vector(15 downto 0)) is
begin
cmdData <= w;
cmdValid <= '1';
if ( cmdReady = '0' ) then
wait until rising_edge(cmdReady);
end if;
wait until rising_edge(sysClk);
cmdData <= (others => 'X');
cmdValid <= '0';
wait until rising_edge(sysClk);
end procedure;
begin
-- Simulate MD on power-on
mdReset <= '1';
mdAddr <= (others => 'Z');
mdOE <= '1';
mdAS <= '1';
mdLDSW <= '1';
mdUDSW <= '1';
traceEnable <= '1';
-- Simulate load of initial program
cmdData <= (others => 'X');
cmdValid <= '0';
rspReady <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cmdWord(x"0012"); -- set pointer = 0x123456
cmdWord(x"3456");
cmdWord(x"8000"); -- write 0x10 words
cmdWord(x"0010");
cmdWord(x"CAFE");
cmdWord(x"BABE");
cmdWord(x"DEAD");
cmdWord(x"F00D");
cmdWord(x"0123");
cmdWord(x"4567");
cmdWord(x"89AB");
cmdWord(x"CDEF");
cmdWord(x"BABA");
cmdWord(x"B0B0");
cmdWord(x"BFBF");
cmdWord(x"1122");
cmdWord(x"3344");
cmdWord(x"5566");
cmdWord(x"7788");
cmdWord(x"99AA");
cmdWord(x"0012"); -- set pointer = 0x123456
cmdWord(x"3456");
cmdWord(x"4000"); -- read 0x10 words
cmdWord(x"0010");
-- Wait for read of 0x10 words to complete
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
wait until rising_edge(mcRDV);
-- Wait a bit longer
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
-- Bring the MD out of reset and simulate a read of 0x123456.
mdReset <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
mdAddr <= "001" & x"23456";
wait until rising_edge(sysClk);
mdOE <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
mdOE <= '1';
mdAddr <= (others => 'Z');
wait;
end process;
end architecture;
|
gpl-3.0
|
a502d14ec639c05e658476eed66a2aec
| 0.645418 | 3.216834 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd
| 2 | 35,790 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : ddr3_ctrl_spec_bank3_32b_32b.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr3_ctrl_spec_bank3_32b_32b is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end ddr3_ctrl_spec_bank3_32b_32b;
architecture arc of ddr3_ctrl_spec_bank3_32b_32b is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"10";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 1;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_p1_cmd_clk,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_p1_wr_clk,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_p1_rd_clk,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
|
gpl-3.0
|
64dc0db37dfc00960723bd26f39edc69
| 0.454037 | 3.434741 | false | false | false | false |
freecores/minimips
|
miniMIPS/bench/ram.vhd
| 1 | 3,774 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pack_mips.all;
entity ram is
generic (mem_size : natural := 256; -- Size of the memory in words
latency : time := 0 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic
);
end;
architecture bench of ram is
type storage_array is array(natural range 1024 to 1024+4*mem_size - 1) of bus8;
signal storage : storage_array; -- The memory
begin
process(adr, data_inout, r_w)
variable inadr : integer;
variable i : natural;
begin
inadr := to_integer(unsigned(adr));
if (inadr>=storage'low) and (inadr<=storage'high) then
ready <= '0', '1' after latency;
if req = '1' then
if r_w /= '1' then -- Reading in memory
for i in 0 to 3 loop
data_inout(8*(i+1)-1 downto 8*i) <= storage(inadr+(3-i)) after latency;
end loop;
else
for i in 0 to 3 loop
storage(inadr+(3-i)) <= data_inout(8*(i+1)-1 downto 8*i) after latency;
end loop;
data_inout <= (others => 'Z');
end if;
else
data_inout <= (others => 'Z');
end if;
else
data_inout <= (others => 'Z');
ready <= 'L';
end if;
end process;
end bench;
|
gpl-2.0
|
500d794c7d7f3bce38c03bf92839f7c2
| 0.401431 | 5.134694 | false | false | false | false |
mammenx/synesthesia_moksha
|
wxp/dgn/syn/limbus/limbus_inst.vhd
| 1 | 6,320 |
component limbus is
port (
clk_100_clk : in std_logic := 'X'; -- clk
reset_100_reset_n : in std_logic := 'X'; -- reset_n
tristate_conduit_bridge_sram_out_sram_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X'); -- sram_tcm_data_out
tristate_conduit_bridge_sram_out_sram_tcm_address_out : out std_logic_vector(18 downto 0); -- sram_tcm_address_out
tristate_conduit_bridge_sram_out_sram_tcm_outputenable_n_out : out std_logic_vector(0 downto 0); -- sram_tcm_outputenable_n_out
tristate_conduit_bridge_sram_out_sram_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- sram_tcm_chipselect_n_out
tristate_conduit_bridge_sram_out_sram_tcm_byteenable_n_out : out std_logic_vector(1 downto 0); -- sram_tcm_byteenable_n_out
tristate_conduit_bridge_sram_out_sram_tcm_write_n_out : out std_logic_vector(0 downto 0); -- sram_tcm_write_n_out
cortex_s_address : out std_logic_vector(17 downto 0); -- address
cortex_s_read : out std_logic; -- read
cortex_s_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
cortex_s_write : out std_logic; -- write
cortex_s_writedata : out std_logic_vector(31 downto 0); -- writedata
cortex_s_readdatavalid : in std_logic := 'X'; -- readdatavalid
cortex_reset_reset_n : out std_logic; -- reset_n
cortex_irq_irq : in std_logic := 'X'; -- irq
uart_rxd : in std_logic := 'X'; -- rxd
uart_txd : out std_logic; -- txd
hdmi_tx_int_n_export : in std_logic := 'X' -- export
);
end component limbus;
u0 : component limbus
port map (
clk_100_clk => CONNECTED_TO_clk_100_clk, -- clk_100.clk
reset_100_reset_n => CONNECTED_TO_reset_100_reset_n, -- reset_100.reset_n
tristate_conduit_bridge_sram_out_sram_tcm_data_out => CONNECTED_TO_tristate_conduit_bridge_sram_out_sram_tcm_data_out, -- tristate_conduit_bridge_sram_out.sram_tcm_data_out
tristate_conduit_bridge_sram_out_sram_tcm_address_out => CONNECTED_TO_tristate_conduit_bridge_sram_out_sram_tcm_address_out, -- .sram_tcm_address_out
tristate_conduit_bridge_sram_out_sram_tcm_outputenable_n_out => CONNECTED_TO_tristate_conduit_bridge_sram_out_sram_tcm_outputenable_n_out, -- .sram_tcm_outputenable_n_out
tristate_conduit_bridge_sram_out_sram_tcm_chipselect_n_out => CONNECTED_TO_tristate_conduit_bridge_sram_out_sram_tcm_chipselect_n_out, -- .sram_tcm_chipselect_n_out
tristate_conduit_bridge_sram_out_sram_tcm_byteenable_n_out => CONNECTED_TO_tristate_conduit_bridge_sram_out_sram_tcm_byteenable_n_out, -- .sram_tcm_byteenable_n_out
tristate_conduit_bridge_sram_out_sram_tcm_write_n_out => CONNECTED_TO_tristate_conduit_bridge_sram_out_sram_tcm_write_n_out, -- .sram_tcm_write_n_out
cortex_s_address => CONNECTED_TO_cortex_s_address, -- cortex_s.address
cortex_s_read => CONNECTED_TO_cortex_s_read, -- .read
cortex_s_readdata => CONNECTED_TO_cortex_s_readdata, -- .readdata
cortex_s_write => CONNECTED_TO_cortex_s_write, -- .write
cortex_s_writedata => CONNECTED_TO_cortex_s_writedata, -- .writedata
cortex_s_readdatavalid => CONNECTED_TO_cortex_s_readdatavalid, -- .readdatavalid
cortex_reset_reset_n => CONNECTED_TO_cortex_reset_reset_n, -- cortex_reset.reset_n
cortex_irq_irq => CONNECTED_TO_cortex_irq_irq, -- cortex_irq.irq
uart_rxd => CONNECTED_TO_uart_rxd, -- uart.rxd
uart_txd => CONNECTED_TO_uart_txd, -- .txd
hdmi_tx_int_n_export => CONNECTED_TO_hdmi_tx_int_n_export -- hdmi_tx_int_n.export
);
|
gpl-3.0
|
d3f6c45d5499bbaf00d78f1b15da1a1a
| 0.385443 | 4.828113 | false | false | false | false |
freecores/minimips
|
miniMIPS/bench/rom.vhd
| 1 | 6,850 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.pack_mips.all;
entity rom is
generic (mem_size : natural := 256; -- Size of the memory in words
start : natural := 32768;
latency : time := 0 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
load : in std_logic;
fname : in string
);
end;
architecture bench of rom is
type storage_array is array(natural range start to start+4*mem_size - 1) of bus8;
signal storage : storage_array := (others => (others => '0')); -- The memory
signal adresse : bus16;
signal taille : bus16;
begin
process (load)
-- Variables for loading the memory
-- The reading is done by blocks
type bin is file of integer; -- Binary type file
file load_file : bin;
variable c : integer ; -- Integer (32 bits) read in the file
variable index : integer range storage'range; -- Index for loading
variable word : bus32; -- Word read in the file
variable taille_bloc : integer; -- Current size of the block to load
variable tmp : bus16;
variable status : file_open_status;
variable s : line;
variable big_endian : boolean := true; -- Define if the processor (on which we work) is little or big endian
begin
if load='1' then
-- Reading of the file de fill the memory at the defined address
file_open(status, load_file, fname, read_mode);
if status=open_ok then
while not endfile(load_file) loop
-- Read the header of the block
read(load_file, c); -- Read a 32 bit long word
word := bus32(to_unsigned(c, 32)); -- Conversion to a bit vector
if big_endian then
tmp := word(7 downto 0) & word(15 downto 8);
else
tmp := word(31 downto 16);
end if;
index := to_integer(unsigned(tmp));
adresse <= tmp;
if big_endian then
tmp := word(23 downto 16) & word(31 downto 24);
else
tmp := word(15 downto 0);
end if;
taille_bloc := to_integer(unsigned(tmp)) / 4;
taille <= tmp;
-- Load the block in the ROM
for n in 1 to taille_bloc loop
-- The header file is not correct (block too small, ROM to small ...)
-- The simulation is stopped
assert (not endfile(load_file) and (index<=storage'high))
report "L'image n'a pas le bon format ou ne rentre pas dans la rom."
severity error;
if not endfile(load_file) and (index<=storage'high) then
read(load_file, c);
word := bus32(to_unsigned(c, 32));
if (c < 0) then
word := not(word);
word := std_logic_vector(unsigned(word)+1);
end if;
for i in 0 to 3 loop
if big_endian then
storage(index+i) <= word(8*(i+1)-1 downto 8*i);
else
storage(index+(3-i)) <= word(8*(i+1)-1 downto 8*i);
end if;
end loop;
index := index + 4;
end if;
end loop;
end loop;
file_close(load_file);
else
assert false
report "Impossible d'ouvrir le fichier specifie."
severity error;
end if;
end if;
end process;
process(adr) -- Request for reading the ROM
variable inadr : integer;
variable i : natural;
begin
inadr := to_integer(unsigned(adr));
if (inadr>=storage'low) and (inadr<=storage'high) then
for i in 0 to 3 loop
donnee(8*(i+1)-1 downto 8*i) <= storage(inadr+3-i) after latency;
end loop;
ack <= '0', '1' after latency;
else
donnee <= (others => 'Z');
ack <= 'L';
end if;
end process;
end bench;
|
gpl-2.0
|
31ca30a913aa97ba501881c3485d69ae
| 0.430219 | 5.134933 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/trigger-logic/eudet_tlu.vhd
| 1 | 5,563 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: EUDET TLU interface
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eudet_tlu is
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end eudet_tlu;
architecture rtl of eudet_tlu is
-- Components
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
-- constants
signal C_DEADTIME : integer := 300; -- clk_i cycles
signal C_CLKDIVIDER : integer := 4; -- 40 MHz -> 10Mhz
-- State machine
type state_type is (IDLE, TRIGGER, RECEIVE, DEAD);
signal state : state_type;
-- Sync inputs
signal sync_eudet_trig_i : std_logic;
signal sync_eudet_rst_i : std_logic;
signal trig_tag_t : std_logic_vector(15 downto 0); -- only 15:1 good
signal eudet_busy_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_bust_t : std_logic;
signal clk_counter : unsigned (3 downto 0);
signal bit_counter : unsigned (4 downto 0);
signal dead_counter : unsigned (9 downto 0);
begin
-- Sync async inputs
trig_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_trig_i, sync_out => sync_eudet_trig_i);
rst_sync: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => eudet_rst_i, sync_out => sync_eudet_rst_i);
eudet_busy_o <= eudet_busy_t;
eudet_clk_o <= eudet_clk_t;
rst_o <= '0';
state_machine: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
state <= IDLE;
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
dead_counter <= (others => '0');
trig_tag_t <= (others => '0');
trig_tag_o <= (others => '0');
trig_o <= '0';
elsif rising_edge(clk_i) then
case state is
when IDLE =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_o <= '0';
if (sync_eudet_trig_i = '1') then
state <= TRIGGER;
end if;
when TRIGGER =>
-- Raise busy and wit until trigger is negated
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
trig_tag_t <= (others => '0');
dead_counter <= (others => '0');
if (sync_eudet_trig_i = '0' and simple_mode_i = '0') then
state <= RECEIVE;
elsif (sync_eudet_trig_i = '0' and simple_mode_i = '1') then
state <= DEAD;
end if;
when RECEIVE =>
eudet_busy_t <= '1';
trig_o <= '0';
clk_counter <= clk_counter + 1;
dead_counter <= (others => '0');
if (clk_counter = (C_CLKDIVIDER-1)) then
clk_counter <= (others => '0');
eudet_clk_t <= not eudet_clk_t;
if (eudet_clk_t = '1') then --sampling on negative edge
bit_counter <= bit_counter + 1;
trig_tag_t <= eudet_trig_i & trig_tag_t(15 downto 1); -- do not need synced vers here
end if;
end if;
if (bit_counter = "10000") then
state <= DEAD;
trig_tag_o <= '0' & trig_tag_t(14 downto 0);
end if;
when DEAD =>
eudet_busy_t <= '1';
eudet_clk_t <= '0';
trig_o <= '0';
if (dead_counter = 0) then
trig_o <= '1'; -- Trigger now (16 clock cycles after the inital trigger?)
end if;
dead_counter <= dead_counter + 1;
if (dead_counter = C_DEADTIME) then
state <= IDLE;
end if;
when others =>
eudet_busy_t <= '0';
eudet_clk_t <= '0';
trig_o <= '0';
clk_counter <= (others => '0');
bit_counter <= (others => '0');
state <= IDLE;
end case;
end if;
end process state_machine;
end rtl;
|
gpl-3.0
|
b617c8c9223443438350e65245eff4d0
| 0.433759 | 3.967903 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_bram.vhd
| 1 | 13,028 |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_bram.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder for decoding 8b/10b encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE STD.textio.ALL; -- required to initialize bram from .mif
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
-----------------------------------------------------------------------------
-- Entity Declaration
-----------------------------------------------------------------------------
ENTITY decode_8b10b_bram IS
GENERIC (
C_ELABORATION_DIR : STRING := "./../../src/";
C_HAS_BPORTS : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_IN_B : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_ERR_B : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_RUN_DISP_B : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_SYM_DISP_B : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_ND_B : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_DOUT_B : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_KOUT_B : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0;
C_SINIT_RUN_DISP_B : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000";
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_bram;
-----------------------------------------------------------------------------
-- Architecture
-----------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_bram IS
-----------------------------------------------------------------------------
-- .MIF file support
-----------------------------------------------------------------------------
-- Specify relative path for .mif file
CONSTANT mif_file_name : STRING := "dec.mif";
-- Initialize inferred ROM from mif file
TYPE RomType IS ARRAY(0 TO 1023) OF BIT_VECTOR(13 DOWNTO 0);
IMPURE FUNCTION InitRomFromFile (RomFileName : IN STRING) RETURN RomType IS
FILE RomFile : TEXT OPEN READ_MODE IS RomFileName;
VARIABLE RomFileLine : LINE;
VARIABLE ROM : RomType;
BEGIN
FOR I IN RomType'range LOOP
READLINE (RomFile, RomFileLine);
READ (RomFileLine, ROM(I));
END LOOP;
RETURN ROM;
END FUNCTION;
SIGNAL ROM : RomType := InitRomFromFile(mif_file_name);
-----------------------------------------------------------------------------
-- Constant initialization values for internal signals ROM_data(_b)
-----------------------------------------------------------------------------
CONSTANT INIT_DATA : STRING :=
concat_sinit(C_SINIT_RUN_DISP,C_SINIT_KOUT, C_SINIT_DOUT);
CONSTANT INIT_DATA_B : STRING :=
concat_sinit(C_SINIT_RUN_DISP_B,C_SINIT_KOUT_B, C_SINIT_DOUT_B);
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT_B,8);
SIGNAL kout_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT_B);
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
SIGNAL run_disp_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP_B);
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP_B,2);
--Internal signals tied to the 14x1k block memory----------------------------
SIGNAL ROM_address : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ROM_data : STD_LOGIC_VECTOR(13 DOWNTO 0) :=
str_to_slv(INIT_DATA, 14);
-----------------------------------------------------------------------------
-- BEGIN ARCHITECTURE
-----------------------------------------------------------------------------
BEGIN
-- Map internal signals to outputs
DOUT <= dout_i;
KOUT <= kout_i;
DOUT_B <= dout_b_i;
KOUT_B <= kout_b_i;
RUN_DISP <= run_disp_i;
RUN_DISP_B <= run_disp_b_i;
SYM_DISP <= sym_disp_i;
SYM_DISP_B <= sym_disp_b_i;
-----------------------------------------------------------------------------
-- Decoder A
-----------------------------------------------------------------------------
ROM_address <= DIN;
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
ROM_data <= str_to_slv(INIT_DATA, 14) AFTER TFF;
ELSE
ROM_data <= to_stdlogicvector(ROM(conv_integer(ROM_address))) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Map ROM data into dout, kout, and code_err outputs
dout_i <= ROM_data(7 DOWNTO 0);
kout_i <= ROM_data(8);
CODE_ERR <= ROM_data(9);
-----------------------------------------------------------------------------
-- Instantiate disparity logic block for Decoder A
-----------------------------------------------------------------------------
dla : ENTITY decode_8b10b.decode_8b10b_disp
GENERIC MAP(
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_SYM_DISP => C_HAS_SYM_DISP
)
PORT MAP(
SINIT => SINIT,
CE => CE,
CLK => CLK,
SYM_DISP => ROM_data(13 DOWNTO 10),
DISP_IN => DISP_IN,
RUN_DISP => run_disp_i,
DISP_ERR => DISP_ERR,
USER_SYM_DISP => sym_disp_i
);
-- create ND output
gndr : IF (C_HAS_ND = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF ((SINIT = '1') AND (CE = '1')) THEN
ND <= '0' AFTER TFF;
ELSE
ND <= CE AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gndr;
-------------------------------------------------------------------------------
-- Generate Decoder B
-------------------------------------------------------------------------------
gdp : IF (C_HAS_BPORTS=1) GENERATE
--Internal signals tied to the 14x1k block memory (B)----------------------
SIGNAL ROM_address_b : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ROM_data_b : STD_LOGIC_VECTOR(13 DOWNTO 0) :=
str_to_slv(INIT_DATA_B, 14);
BEGIN
ROM_address_b <= DIN_B;
PROCESS (CLK_B)
BEGIN
IF (CLK_B'event AND CLK_B = '1') THEN
IF (CE_B = '1') THEN
IF (SINIT_B = '1') THEN
ROM_data_b <= str_to_slv(INIT_DATA_B, 14) AFTER TFF;
ELSE
ROM_data_b <= to_stdlogicvector(ROM(conv_integer(ROM_address_b)))
AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Map ROM_data_b into dout_b, kout_b, and code_err_b outputs
dout_b_i <= ROM_data_b(7 DOWNTO 0);
kout_b_i <= ROM_data_b(8);
CODE_ERR_B <= ROM_data_b(9);
-----------------------------------------------------------------------------
-- Instantiate disparity logic block for Decoder B
-----------------------------------------------------------------------------
dlb : ENTITY decode_8b10b.decode_8b10b_disp
GENERIC MAP(
C_SINIT_DOUT => C_SINIT_DOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP_B,
C_HAS_DISP_IN => C_HAS_DISP_IN_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP_B
)
PORT MAP(
SINIT => SINIT_B,
CE => CE_B,
CLK => CLK_B,
SYM_DISP => ROM_data_b(13 DOWNTO 10),
DISP_IN => DISP_IN_B,
RUN_DISP => run_disp_b_i,
DISP_ERR => DISP_ERR_B,
USER_SYM_DISP => sym_disp_b_i
);
-- create ND_B output
gndbr : IF (C_HAS_ND_B = 1) GENERATE
PROCESS (CLK_B)
BEGIN
IF (CLK_B'event AND CLK_B = '1') THEN
IF ((SINIT_B = '1') AND (CE_B = '1')) THEN
ND_B <= '0' AFTER TFF;
ELSE
ND_B <= CE_B AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gndbr;
END GENERATE gdp;
END xilinx;
|
gpl-3.0
|
37b951c0cfe60960f8adec69e6fcac12
| 0.454943 | 4.029694 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
mem_reader.vhd
| 1 | 2,015 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mem_reader is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Enable : in STD_LOGIC;
FrameLen : in STD_LOGIC_VECTOR(10 downto 0);
FrameIval : in STD_LOGIC_VECTOR(27 downto 0);
MemAddr : out STD_LOGIC_VECTOR (10 downto 0);
MemData : in STD_LOGIC_VECTOR (7 downto 0);
BusPkt : out STD_LOGIC;
BusData : out STD_LOGIC_VECTOR (7 downto 0));
end mem_reader;
architecture Behavioral of mem_reader is
signal time_cnt, NEXT_time_cnt : STD_LOGIC_VECTOR(27 downto 0) := ( others => '0' );
begin
NEXT_time_cnt <= time_cnt + 1;
MemAddr <= time_cnt(10 downto 0);
BusData <= MemData;
counter : process (Clk)
variable frameSent : STD_LOGIC := '0';
variable saveEna : STD_LOGIC := '0';
begin
if RISING_EDGE(Clk) then
time_cnt <= NEXT_time_cnt;
BusPkt <= '0';
if time_cnt(10 downto 0) < FrameLen and frameSent = '0' then
BusPkt <= saveEna;
else
frameSent := '1';
end if;
if rst = '1' or NEXT_time_cnt >= FrameIval then
time_cnt <= ( others => '0' );
frameSent := '0';
saveEna := Enable;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
01016bb0f3011f9621d87a3ce0750ed4
| 0.647643 | 3.158307 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
counter_en.vhd
| 1 | 1,640 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter with enable
entity counter_en is
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
Cnt : out std_logic_vector (N_BITS - 1 downto 0));
end counter_en;
-- Operation:
-- Count number of cycles @Enable is up.
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again.
architecture Behavioral of counter_en is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
if Enable = '1' then
count <= count + 1;
end if;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
3cdc844be97352c893bcefeaff45b780
| 0.646951 | 3.796296 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sim_1/imports/BMP/sim_tb_bmpread.vhd
| 1 | 5,719 |
-------------------------------------------------------------------------------
-- Title : Testbench BMP Read
-- Project :
-------------------------------------------------------------------------------
-- File : sim_tb_bmpread.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2007-12-26
-- Platform : ModelSIM
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use work.sim_bmppack.all;
entity sim_tb_bmpread is
port(
resetn : in std_logic;
pclk : in std_logic;
pixel_data : out std_logic_vector(7 downto 0 );
pixel_out_hsync, pixel_out_vsync, pixel_out_href : out std_logic );
end sim_tb_bmpread;
-------------------------------------------------------------------------------
architecture BMP_to_OV7670 of sim_tb_bmpread is
signal clk : std_logic := '0';
signal ImageWidth, ImageHeight : integer := 0;
signal bit_number : integer := 0;
signal temp_hsync, temp_vsync, temp_href, temp_pixel_clock : std_logic ;
signal pixel_data_temp : std_logic_vector(23 downto 0);
signal data: std_logic_vector(7 downto 0);
signal npixel, nline : integer;
constant VSYNC_Width : integer := 3; --sehe Datenblatt OV 7670
constant VSYNC_for : integer := 17;
constant VSYNC_after : integer := 10;
constant HSYNC_Width : integer := 80;
constant HSYNC_for : integer := 45;
constant HSYNC_after : integer := 19;
constant byte_per_pixel : integer := 3;
begin
assert byte_per_pixel < 4
report " byte_per_pixel to big "
severity failure;
read_file: process
variable px_count, x_count, y_count, line_count, byte_count, bit_number : integer := 0 ;
begin
report "read File...";
ReadFile("test.bmp");
GetWidth(ImageWidth);
GetHeigth(ImageHeight);
if resetn = '1' then
loop EXIT WHEN line_count = (ImageHeight + VSYNC_for + VSYNC_Width + VSYNC_after);
wait until pclk'event and clk = '0'; -- bei negative flanke
temp_pixel_clock <= '0';
-- HSYNC
if (px_count >= 0 and px_count < HSYNC_Width - 1) then
temp_hsync <= '0';
else
temp_hsync <= '1' ;
end if ;
-- HREF
if (px_count >= (HSYNC_for + HSYNC_Width)
and px_count < (HSYNC_for + HSYNC_Width + ImageWidth)
and line_count >= (VSYNC_for + VSYNC_Width)
and line_count < (VSYNC_for + VSYNC_Width + ImageHeight)) then
if (bit_number = 0) then
GetPixel( px_count - (HSYNC_for + HSYNC_Width), line_count - (VSYNC_for + VSYNC_Width), pixel_data_temp);
npixel <= px_count - (HSYNC_for + HSYNC_Width);
nline <= line_count - (VSYNC_for + VSYNC_Width);
end if;
temp_href <= '1';
else
pixel_data_temp <= (others => '0');
temp_href <= '0';
end if ;
-- vsync control
if line_count < VSYNC_Width then -- nach 510 lines line_count soll auf 0
temp_vsync <= '1' ;
else
temp_vsync <= '0' ;
end if ;
if (px_count = (HSYNC_for + HSYNC_Width + ImageWidth - 1 + HSYNC_after) ) then -- neue line
px_count := 0 ; -- abnullen
bit_number := 0;
if (line_count > ( VSYNC_for + VSYNC_Width + ImageHeight - 1 + VSYNC_after)) then -- neues Frame
line_count := 0; -- abnullen
else
line_count := line_count + 1 ;
end if;
end if ;
if line_count >= (VSYNC_for + VSYNC_Width + ImageHeight - 1 + VSYNC_after) then -- volle frame
line_count := 0;
px_count := 0;
bit_number := 0;
end if;
wait until pclk'event and pclk = '1'; -- bei positive flanke
temp_pixel_clock <= '1';
case bit_number is
when 0 =>
data <= pixel_data_temp(23 downto 16);
when 1 =>
data <= pixel_data_temp(15 downto 8);
when 2 =>
data <= pixel_data_temp(7 downto 0);
end case;
if ( bit_number = byte_per_pixel - 1) then -- pixel ausgabe
px_count := px_count + 1;
bit_number := 0;
else
bit_number := bit_number + 1;
end if;
end loop;
wait; -- one shot at time zero,
end if; -- reset
end process read_file;
clk_domain_latch : process(pclk, resetn)
begin
if resetn = '0' then
pixel_out_hsync <= '0' ;
pixel_out_vsync <= '1' ;
pixel_out_href <= '0';
pixel_data <= (others => '0');
elsif falling_edge(pclk) then
-- pixel_out_clk <= temp_pixel_clock ;
pixel_out_href <= temp_href;
pixel_out_hsync <= temp_hsync ;
pixel_out_vsync <= temp_vsync ;
pixel_data <= data ;
end if ;
end process ;
end BMP_to_OV7670;
|
gpl-3.0
|
798e8691a8eff30d7747bd5952880ab7
| 0.462144 | 4.035992 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/prescaler.vhd
| 3 | 2,076 |
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prescaler is
generic (
SCALE : integer
);
Port ( clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
5cd9603d12d6131bd29184a0ae5b7c8a
| 0.592967 | 3.924386 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Arithmetic/Mult.vhd
| 1 | 912 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity Mult is
generic (
wordLengthA : natural := 8;
wordLengthB : natural := 8;
fractionalBitsA : natural := 7;
fractionalBitsB : natural := 7;
wordLengthP : natural := 16;
fractionalBitsP : natural := 7
);
port (
a : in std_logic_vector(wordLengthA-1 downto 0);
b : in std_logic_vector(wordLengthB-1 downto 0);
p : out std_logic_vector(wordLengthP-1 downto 0)
);
end entity ; -- Mult
architecture arch of Mult is
signal product : signed(wordLengthA+wordLengthB-1 downto 0);
signal pEntire : std_logic_vector(wordLengthA+wordLengthB-1 downto 0);
constant LSB : natural := fractionalBitsA+fractionalBitsB-fractionalBitsP;
constant MSB : natural := LSB + wordLengthP-1;
begin
product <= (signed(a)*signed(b));
pEntire <= std_logic_vector(product);
p <= pEntire(MSB downto LSB);
end architecture ; -- arch
|
mit
|
8613d5ee22e64daf0da04aa6c68bb078
| 0.70614 | 3.304348 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sim_1/imports/BMP/sim_tb_bmprotate_simple.vhd
| 1 | 3,385 |
-------------------------------------------------------------------------------
-- Title : Testbench BMP Rotate
-- Project :
-------------------------------------------------------------------------------
-- File : sim_tb_bmprotate.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2007-10-29
-- Platform : ModelSIM
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use work.sim_bmppack.all;
-------------------------------------------------------------------------------
entity sim_tb_bmprotate_simple is
end sim_tb_bmprotate_simple;
-------------------------------------------------------------------------------
architecture testbench of sim_tb_bmprotate_simple is
constant cMathOne : integer := 1024;
signal clk : std_logic := '0';
signal data : std_logic_vector(23 downto 0) := x"ffffff";
signal adr, ImageWidth, ImageHeight, centerX, centerY : integer := 0;
signal x, y, x_mitte, y_mitte : integer;
signal angle, zoom : real := 0.0;
signal co, si, rotX, rotY, xf, yf : real := 0.0;
begin
process(clk) is
begin
clk <= not clk after 5 ns;
end process;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
process is
begin
ReadFile("lena.bmp");
angle <= 45.0 * 3.14 / 180.0;
zoom <= 1.0;
GetWidth(ImageWidth);
GetHeigth(ImageHeight);
wait until clk'event and clk = '1';
co <= cos(angle);
si <= sin(angle);
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
-- innere Schleife
---------------------------------------------------------------------------
centerX <= integer(ImageWidth/2);
centerY <= integer(ImageHeight/2);
for y1 in 0 to integer(real(ImageHeight)/zoom) loop
wait until clk'event and clk = '1';
for x1 in 0 to integer(real(ImageWidth)/zoom) loop
rotX <= real(x1);
rotY <= real(y1);
xf <= rotX * co + rotY * si;
yf <= rotY * co - rotX * si;
wait until clk'event and clk = '1';
x <= integer(xf);
y <= integer(yf);
wait until clk'event and clk = '1';
if x >= 0 and x < ImageWidth and y >= 0 and y < ImageHeight then
GetPixel(x, y, data);
wait until clk'event and clk = '1';
SetPixel(x1, y1, data);
wait until clk'event and clk = '1';
end if;
end loop;
end loop;
wait until clk'event and clk = '1';
report "Jetzt ist das Bild fertig...";
WriteFile("lena_rotated.bmp");
wait until clk'event and clk = '1';
wait;
end process;
end testbench;
|
gpl-3.0
|
57e4fced3d3a90d7403f869078f030ce
| 0.397637 | 4.513333 | false | false | false | false |
cretingame/Yarr-fw
|
ip-cores/spartan6/clk_gen.vhd
| 1 | 6,696 |
-- file: clk_gen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
-- CLK_OUT3____80.000______0.000______50.0______263.295____213.982
-- CLK_OUT4____40.000______0.000______50.0______306.416____213.982
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________40____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_gen is
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clk_gen;
architecture xilinx of clk_gen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_gen,clk_wiz_v3_6,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_40_IN;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 16,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 25.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => RESET,
-- Input clock control
CLKFBIN => CLKFB_IN,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLKFB_OUT <= clkfbout;
CLK_640 <= clkout0;
CLK_160 <= clkout1;
CLK_80 <= clkout2;
CLK_40 <= clkout3;
end xilinx;
|
gpl-3.0
|
243c7a35462f9bef22b4b3904f05a670
| 0.584677 | 4.090409 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Utilities/Decimator.vhd
| 1 | 1,149 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity ClockDecimator is
generic (
wordLength : natural := 8;
divider : natural := 2
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
reset : in std_logic;
clk : in std_logic
);
end entity ; -- ClockDecimator
architecture arch of ClockDecimator is
type reg_type is record
vector : std_logic_vector(wordLength-1 downto 0);
end record;
signal r, rin : reg_type;
signal decimatedClk : std_logic;
begin
output <= r.vector;
-- Create a decimated (slow) clock via ClockDivider:
decimator : entity work.ClockDivider
generic map(
divider => divider
)
port map(
reset => reset,
clk => clk,
clkOut => decimatedClk
);
-- Let the clocked process trigger on the slow clock.
clk_proc : process( decimatedClk )
begin
if(rising_edge(decimatedClk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin, input )
variable v : reg_type;
begin
v := r;
v.vector := input;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
cd04ae84bd877ece3032d96c97d71dec
| 0.672759 | 3.113821 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/FIFO_one_hot_credit_based.vhd
| 1 | 9,864 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
valid_in_vc: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_en_vc_N : in std_logic;
read_en_vc_E : in std_logic;
read_en_vc_W : in std_logic;
read_en_vc_S : in std_logic;
read_en_vc_L : in std_logic;
credit_out: out std_logic;
credit_out_vc: out std_logic;
empty_out: out std_logic;
empty_out_vc: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
Data_out_vc: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal read_pointer_vc, read_pointer_in_vc, write_pointer_vc, write_pointer_in_vc: std_logic_vector(3 downto 0);
signal full_vc, empty_vc: std_logic;
signal read_en_vc, write_en_vc: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_1, FIFO_MEM_vc_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_2, FIFO_MEM_vc_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_3, FIFO_MEM_vc_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_vc_4, FIFO_MEM_vc_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
credit_out <= '0';
read_pointer_vc <= "0001";
write_pointer_vc <= "0001";
FIFO_MEM_vc_1 <= (others=>'0');
FIFO_MEM_vc_2 <= (others=>'0');
FIFO_MEM_vc_3 <= (others=>'0');
FIFO_MEM_vc_4 <= (others=>'0');
credit_out_vc <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
credit_out <= '0';
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
if read_en = '1' then
credit_out <= '1';
end if;
write_pointer_vc <= write_pointer_in_vc;
read_pointer_vc <= read_pointer_in_vc;
credit_out_vc <= '0';
if write_en_vc = '1' then
--write into the memory
FIFO_MEM_vc_1 <= FIFO_MEM_vc_1_in;
FIFO_MEM_vc_2 <= FIFO_MEM_vc_2_in;
FIFO_MEM_vc_3 <= FIFO_MEM_vc_3_in;
FIFO_MEM_vc_4 <= FIFO_MEM_vc_4_in;
end if;
if read_en_vc = '1' then
credit_out_vc <= '1';
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
-------------------------------------------------------------------------------
--- VC stuff
---
-------------------------------------------------------------------------------
process(RX, write_pointer_vc, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer_vc ) is
when "0001" => FIFO_MEM_vc_1_in <= RX; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
when "0010" => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= RX; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
when "0100" => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= RX; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
when "1000" => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= RX;
when others => FIFO_MEM_vc_1_in <= FIFO_MEM_vc_1; FIFO_MEM_vc_2_in <= FIFO_MEM_vc_2; FIFO_MEM_vc_3_in <= FIFO_MEM_vc_3; FIFO_MEM_vc_4_in <= FIFO_MEM_vc_4;
end case ;
end process;
process(read_pointer_vc, FIFO_MEM_vc_1, FIFO_MEM_vc_2, FIFO_MEM_vc_3, FIFO_MEM_vc_4)begin
case( read_pointer_vc ) is
when "0001" => Data_out_vc <= FIFO_MEM_vc_1;
when "0010" => Data_out_vc <= FIFO_MEM_vc_2;
when "0100" => Data_out_vc <= FIFO_MEM_vc_3;
when "1000" => Data_out_vc <= FIFO_MEM_vc_4;
when others => Data_out_vc <= FIFO_MEM_vc_1;
end case ;
end process;
read_en_vc <= (read_en_vc_N or read_en_vc_E or read_en_vc_W or read_en_vc_S or read_en_vc_L) and not empty_vc;
empty_out_vc <= empty_vc;
process(write_en_vc, write_pointer_vc)begin
if write_en_vc = '1'then
write_pointer_in_vc <= write_pointer_vc(2 downto 0)&write_pointer_vc(3);
else
write_pointer_in_vc <= write_pointer_vc;
end if;
end process;
process(read_en_vc, empty_vc, read_pointer_vc)begin
if (read_en_vc = '1' and empty_vc = '0') then
read_pointer_in_vc <= read_pointer_vc(2 downto 0)&read_pointer_vc(3);
else
read_pointer_in_vc <= read_pointer_vc;
end if;
end process;
process(full_vc, valid_in_vc) begin
if valid_in_vc = '1' and full_vc ='0' then
write_en_vc <= '1';
else
write_en_vc <= '0';
end if;
end process;
process(write_pointer_vc, read_pointer_vc) begin
if read_pointer_vc = write_pointer_vc then
empty_vc <= '1';
else
empty_vc <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer_vc = read_pointer_vc(0)&read_pointer_vc(3 downto 1) then
full_vc <= '1';
else
full_vc <= '0';
end if;
end process;
end;
|
gpl-3.0
|
999d4b3c635bdcd2d77b148e1e3e41ec
| 0.510949 | 3.133418 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/wshexp_core_pkg.vhd
| 1 | 6,663 |
--==============================================================================
--! @file gn4124_core_pkg_s6.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Package for gn4124 core
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! Package for components declaration and core wide constants.
--! Spartan6 FPGAs version.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 01.09.2010 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Package declaration
--==============================================================================
package wshexp_core_pkg is
--==============================================================================
--! Constants declaration
--==============================================================================
constant c_RST_ACTIVE : std_logic := '0'; -- Active low reset
--==============================================================================
--! Functions declaration
--==============================================================================
function f_byte_swap_64 (
constant enable : boolean;
signal din : std_logic_vector(63 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector;
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
-----------------------------------------------------------------------------
end wshexp_core_pkg;
package body wshexp_core_pkg is
-----------------------------------------------------------------------------
-- Byte swap function
--
-- enable | byte_swap | din | dout
-- false | XX | ABCD | ABCD
-- true | 00 | ABCD | ABCD
-- true | 01 | ABCD | BADC
-- true | 10 | ABCD | CDAB
-- true | 11 | ABCD | DCBA
-----------------------------------------------------------------------------
function f_byte_swap (
constant enable : boolean;
signal din : std_logic_vector(31 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(31 downto 0) := din;
begin
if (enable = true) then
case byte_swap is
when "00" =>
dout := din;
when "01" =>
dout := din(23 downto 16)
& din(31 downto 24)
& din(7 downto 0)
& din(15 downto 8);
when "10" =>
dout := din(15 downto 0)
& din(31 downto 16);
when "11" =>
dout := din(7 downto 0)
& din(15 downto 8)
& din(23 downto 16)
& din(31 downto 24);
when others =>
dout := din;
end case;
else
dout := din;
end if;
return dout;
end function f_byte_swap;
-----------------------------------------------------------------------------
-- Byte swap function
--
-- enable | byte_swap | din | dout
-- false | XXX | ABCDEFGH | ABCDEFGH
-- true | 000 | ABCDEFGH | ABCDEFGH
-- true | 001 | ABCDEFGH | BADCFEHG
-- true | 010 | ABCDEFGH | CDABGHEF
-- true | 011 | ABCDEFGH | DCBAHGFE
-- true | 100 | ABCDEFGH | EFGHABCD
-- true | 101 | ABCDEFGH | FEHGBADC
-- true | 110 | ABCDEFGH | GHEFCDAB
-- true | 111 | ABCDEFGH | HGFEDCBA
-----------------------------------------------------------------------------
function f_byte_swap_64 (
constant enable : boolean;
signal din : std_logic_vector(63 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(63 downto 0) := din;
begin
if (enable = true) then
if byte_swap(2) = '0' then
dout := f_byte_swap(true, din(63 downto 32), byte_swap(1 downto 0)) & f_byte_swap(true, din(31 downto 0), byte_swap(1 downto 0));
else
dout := f_byte_swap(true, din(31 downto 0), byte_swap(1 downto 0)) & f_byte_swap(true, din(63 downto 32), byte_swap(1 downto 0));
end if;
else
dout := din;
end if;
return dout;
end function f_byte_swap_64;
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end wshexp_core_pkg;
|
gpl-3.0
|
6050b0dda37690ff849ff51350849917
| 0.406424 | 5.078506 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/flags.vhd
| 4 | 1,796 |
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity flags is
Port ( data : in STD_LOGIC_VECTOR(8 downto 0);
clock : in STD_LOGIC;
write : in STD_LOGIC;
demux : out STD_LOGIC;
filter : out STD_LOGIC;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
end flags;
architecture Behavioral of flags is
begin
-- write flags
process (clock)
begin
if rising_edge(clock) and write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
rle <= data(8);
end if;
end process;
end Behavioral;
|
gpl-2.0
|
e0a9f3dcce5175c49c53b990924ff118
| 0.582962 | 4.138249 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_eth_add_ts.vhd
| 1 | 2,750 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_eth_add_ts IS
END tb_eth_add_ts;
ARCHITECTURE behavior OF tb_eth_add_ts IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bus_append
GENERIC ( N_BYTES : integer );
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Value : in STD_LOGIC_VECTOR (N_BYTES*8 - 1 downto 0);
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal Cnt64 : std_logic_vector(63 downto 0) := (others => '0');
signal InPkt : std_logic := '0';
signal InData : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OutPkt : std_logic;
signal OutData : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bus_append
GENERIC MAP ( N_BYTES <= 8 )
PORT MAP (
Clk => Clk,
Rst => Rst,
Value => Cnt64,
InPkt => InPkt,
InData => InData,
OutPkt => OutPkt,
OutData => OutData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
Cnt64 <= Cnt64 + 1;
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
InPkt <= '1';
for i in 0 to 6 loop
InData <= X"55";
wait for Clk_period;
end loop;
InData <= X"d5";
wait for Clk_period;
for i in 0 to 63 loop
InData <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
-- InData <= x"00";
-- wait for Clk_period;
InPkt <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
000685ab8cc8e196ecf562b5af52e220
| 0.625455 | 3.374233 | false | false | false | false |
starsheriff/papilio-one250
|
pong/vga_switch_input.vhd
| 1 | 3,082 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:31:09 10/18/2015
-- Design Name:
-- Module Name: vga_switch_input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_switch_input is
Port(
clk : in STD_LOGIC;
switches: in STD_LOGIC_VECTOR(7 downto 0);
leds : out STD_LOGIC_VECTOR(7 downto 0);
JOY_LEFT: in STD_LOGIC;
JOY_RIGHT: in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
red : out STD_LOGIC_VECTOR(2 downto 0);
green : out STD_LOGIC_VECTOR(2 downto 0);
blue : out STD_LOGIC_VECTOR(1 downto 0)
);
end vga_switch_input;
architecture Behavioral of vga_switch_input is
--signal hcount: STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
--signal vcount: STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal x_pos, y_pos: STD_LOGIC_VECTOR(9 downto 0);
signal rgb: STD_LOGIC_VECTOR(7 downto 0);
--signal x_pos: integer range 0 to 799;
signal video_on: STD_LOGIC;
COMPONENT sync_module
Port ( start : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
x_pos : out STD_LOGIC_VECTOR(9 downto 0);
y_pos : out STD_LOGIC_VECTOR(9 downto 0);
video_on : out STD_LOGIC);
END COMPONENT;
COMPONENT img_gen
Port ( x_pos : in STD_LOGIC_VECTOR (9 downto 0);
y_pos : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
JOY_LEFT: in STD_LOGIC;
JOY_RIGHT: in STD_LOGIC;
video_on : in STD_LOGIC;
rgb : out STD_LOGIC_VECTOR (7 downto 0));
END COMPONENT;
begin
Isync_module : sync_module
PORT MAP (
clk => clk, start => '0', reset => '0',
hsync => hsync, vsync => vsync,
x_pos => x_pos, y_pos => y_pos,
video_on => video_on);
Iimg_gen : img_gen
PORT MAP (
x_pos => x_pos, y_pos => y_pos, clk => clk,
video_on => video_on, rgb => rgb,
JOY_LEFT => JOY_LEFT, JOY_RIGHT => JOY_RIGHT);
leds <= switches;
red <= rgb(7 downto 5);
green <= rgb(4 downto 2);
blue <= rgb(1 downto 0);
--red <= "000" when (video_on = '0') else
-- switches(7 downto 5);
--green <= "000" when video_on = '0' else
-- switches(4 downto 2);
--blue <= "00" when video_on = '0' else
-- switches(1 downto 0);
end Behavioral;
|
gpl-2.0
|
125128b614fa7f0b99e4b7d0a99887a5
| 0.562297 | 3.462921 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/ADSampler.vhdl
| 1 | 4,578 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity ADSampler is
port (
--http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
vauxp : in std_logic;
vauxn : in std_logic;
output : out std_logic_vector(11 downto 0);
sampleClk : in std_logic;
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- ADSampler
architecture arch of ADSampler is
constant address_input : std_logic_vector(6 downto 0) := "001" & x"3";
type state_type is (res, busy, busy_conversion, read);
type reg_type is record
state : state_type;
output : std_logic_vector(11 downto 0);
DRP_enable : std_logic;
end record;
signal r, rin : reg_type;
signal DRP_output : std_logic_vector(15 downto 0);
signal DRP_dataReady : std_logic;
signal DRP_input : std_logic_vector(15 downto 0);
signal DRP_address : std_logic_vector(6 downto 0);
signal DRP_enable : std_logic;
signal DRP_writeEnable : std_logic;
signal DRP_clk : std_logic;
signal XADC_EOC : std_logic;
signal XADC_busy : std_logic;
signal XADC_reset : std_logic;
signal CONVST_IN : std_logic;
component xadc_wiz_0
port (
DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
VAUXP3 : in STD_LOGIC; -- Auxiliary Channel 2
VAUXN3 : in STD_LOGIC;
BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
ALARM_OUT : out STD_LOGIC; -- OR'ed output of all the Alarms
VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
VN_IN : in STD_LOGIC;
CONVST_IN : in STD_LOGIC
);
end component;
begin
DRP_clk <= clk;
XADC_reset <= reset;
DRP_address <= address_input;
DRP_enable <= r.DRP_enable;
DRP_writeEnable <= '0';
DRP_input <= (others => '0');
CONVST_IN <= sampleClk;
theCore : xadc_wiz_0
port map (
DADDR_IN => DRP_address,
DCLK_IN => DRP_clk,
DEN_IN => DRP_enable,
DI_IN => DRP_input,
DWE_IN => DRP_writeEnable,
RESET_IN => XADC_reset,
VAUXP3 => vauxp,
VAUXN3 => vauxn,
BUSY_OUT => XADC_busy,
DO_OUT => DRP_output,
DRDY_OUT => DRP_dataReady,
EOC_OUT => XADC_EOC,
CONVST_IN => CONVST_IN,
--ALARM_OUT
VP_IN => '0',
VN_IN => '0'
);
output <= r.output;
clk_proc : process( clk, reset )
begin
if(reset = '1') then
r.state <= res;
r.output <= (others => '0');
elsif(rising_edge(clk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin, DRP_output, DRP_dataReady, XADC_busy, XADC_EOC )
variable v : reg_type;
begin
v := r;
v.DRP_enable := '0';
case r.state is
when res =>
-- Reset the XADC (done strucutrally, just go to next state)
v.state := busy;
when busy =>
-- Wait for the XADC to become ready
-- (This state might not be necessary)
if(XADC_busy = '0') then
v.state := busy_conversion;
end if;
when busy_conversion =>
-- Wait for the DRP to acquire the data
if(XADC_EOC = '1') then
-- Data is available in the DRP, read it.
v.DRP_enable := '1';
v.state := read;
end if;
when read =>
-- Wait for the DRP data to become ready
if(DRP_dataReady = '1') then
v.state := busy_conversion;
-- Read the DRP output
v.output := DRP_output(15 downto 4);
end if;
when others =>
-- Don't care
end case;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
56d0af499bff6760a020e0ba771b6faf
| 0.569244 | 3.376106 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_Equalizer_No_Change_Test.vhd
| 1 | 3,222 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer_No_Change_Test is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_Equalizer_No_Change_Test;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer_No_Change_Test is
begin
Generic_Equalizer : entity work.Generic_Equalizer
generic map(NO_SECTIONS => 9,
INPUT_WIDTH => 16,
INPUT_FRACT => 14,
OUTPUT_WIDTH => 16,
OUTPUT_FRACT => 14,
SCALE_WIDTH => 16,
SCALE_FRACT => (14,14,14,14,14,14,14,14,14,14),
INTERNAL_WIDTH => 30,
INTERNAL_FRACT => 24,
COEFF_WIDTH_B => 16,
COEFF_FRACT_B => (14,14,14,14,14,14,14,14,14),
COEFF_WIDTH_A => 16,
COEFF_FRACT_A => (14,14,14,14,14,14,14,14,14))
port map(clk => clk,
reset => reset,
x => input,
scale => (x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b0 => (x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b1 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
b2 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a1 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a2 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
y => output);
end architecture;
|
mit
|
1f7b64d160f737f13761e06214087ce0
| 0.277157 | 4.493724 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/common_pkg.vhd
| 1 | 1,881 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
package common_pkg is
component generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
);
end component generic_async_fifo;
end common_pkg;
package body common_pkg is
end common_pkg;
|
gpl-3.0
|
60e61e8634422d653f1fb4f4b4963063
| 0.591707 | 3.07856 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/BRAM8k32bit.vhd
| 4 | 2,519 |
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM8k32bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (31 downto 0);
DIN : in STD_LOGIC_VECTOR (31 downto 0));
end BRAM8k32bit;
architecture Behavioral of BRAM8k32bit is
begin
BlockRAMS: for i in 0 to 15 generate
RAMB16_S2_inst : RAMB16_S2
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
ADDR => ADDR, -- 13-bit Address Input
CLK => CLK, -- Clock
DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input
);
end generate;
end Behavioral;
|
gpl-2.0
|
d29628f980585cd1bb8ca470a1177c3c
| 0.592696 | 3.979463 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Multiplier_tb.vhd
| 1 | 5,918 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier_tb is
end Multiplier_tb;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture Behaviour of Multiplier_tb is
component Multiplier is
generic (X_WIDTH : integer;
X_FRACTION : integer;
Y_WIDTH : integer;
Y_FRACTION : integer;
S_WIDTH : integer;
S_FRACTION : integer);
port(x : in std_logic_vector;
y : in std_logic_vector;
s : out std_logic_vector);
end component;
constant NO_OF_SAMPLES : integer := 10;
constant X_1_WIDTH : integer := 16;
constant X_1_FRACTION : integer := 14;
constant Y_1_WIDTH : integer := 16;
constant Y_1_FRACTION : integer := 14;
constant S_1_WIDTH : integer := 16;
constant S_1_FRACTION : integer := 13;
constant X_2_WIDTH : integer := 14;
constant X_2_FRACTION : integer := 10;
constant Y_2_WIDTH : integer := 8;
constant Y_2_FRACTION : integer := 6;
constant S_2_WIDTH : integer := 10;
constant S_2_FRACTION : integer := 6;
type x_1_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(X_1_WIDTH-1 downto 0);
type y_1_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(Y_1_WIDTH-1 downto 0);
type s_1_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(S_1_WIDTH-1 downto 0);
type x_2_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(X_2_WIDTH-1 downto 0);
type y_2_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(Y_2_WIDTH-1 downto 0);
type s_2_array is array(0 to NO_OF_SAMPLES-1) of std_logic_vector(S_2_WIDTH-1 downto 0);
signal x_1 : x_1_array := ("1111100001010010",
"0001001001011001",
"0101011101011110",
"0011011100001000",
"0101011001110111",
"1111100011010000",
"0110100111011001",
"0111111011100010",
"0011100001010111",
"1000111111101101");
signal y_1 : y_1_array := ("0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000",
"0100000000000000");
signal s_1 : s_1_array := ("1111110000101001",
"0000100100101100",
"0010101110101111",
"0001101110000100",
"0010101100111011",
"1111110001101000",
"0011010011101100",
"0011111101110001",
"0001110000101011",
"1100011111110110");
signal x_2 : x_2_array := ("01010111100101",
"10000001101101",
"00010100011110",
"01101101011010",
"11011111110111",
"01011101111111",
"00101101011011",
"00100100110000",
"11011010111001",
"01010000000101");
signal y_2 : y_2_array := ("01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000");
signal s_2 : s_2_array := ("0101011110",
"1000000110",
"0001010001",
"0110110101",
"1101111111",
"0101110111",
"0010110101",
"0010010011",
"1101101011",
"0101000000");
signal s1 : std_logic_vector(S_1_WIDTH-1 downto 0);
signal s2 : std_logic_vector(S_2_WIDTH-1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- End process
ending : process
begin
wait for 1050 ns;
assert false
report "Simulation Done!"
severity failure;
end process;
-- Test process
test : process
begin
wait for 100 ns;
assert (s1 = s_1(0))
report "Error: Multiplier 1 output wrong!"
severity Error;
assert (s2 = s_2(0))
report "Error: Multiplier 2 output wrong!"
severity Error;
x_1(0 to NO_OF_SAMPLES-2) <= x_1(1 to NO_OF_SAMPLES-1);
y_1(0 to NO_OF_SAMPLES-2) <= y_1(1 to NO_OF_SAMPLES-1);
s_1(0 to NO_OF_SAMPLES-2) <= s_1(1 to NO_OF_SAMPLES-1);
x_2(0 to NO_OF_SAMPLES-2) <= x_2(1 to NO_OF_SAMPLES-1);
y_2(0 to NO_OF_SAMPLES-2) <= y_2(1 to NO_OF_SAMPLES-1);
s_2(0 to NO_OF_SAMPLES-2) <= s_2(1 to NO_OF_SAMPLES-1);
end process;
Multiplier_1 : Multiplier
generic map(X_WIDTH => X_1_WIDTH,
X_FRACTION => X_1_FRACTION,
Y_WIDTH => Y_1_WIDTH,
Y_FRACTION => Y_1_FRACTION,
S_WIDTH => S_1_WIDTH,
S_FRACTION => S_1_FRACTION)
port map(x => x_1(0),
y => y_1(0),
s => s1);
Multiplier_2 : Multiplier
generic map(X_WIDTH => X_2_WIDTH,
X_FRACTION => X_2_FRACTION,
Y_WIDTH => Y_2_WIDTH,
Y_FRACTION => Y_2_FRACTION,
S_WIDTH => S_2_WIDTH,
S_FRACTION => S_2_FRACTION)
port map(x => x_2(0),
y => y_2(0),
s => s2);
end Behaviour;
|
mit
|
8a8dd2a7b05a3295efd2bbf149a119b3
| 0.466036 | 4.104022 | false | false | false | false |
eda-ricercatore/eda-ricercatore.github.io
|
vecchi-progetti/vlsi-design-projects/mult32.vhd
| 1 | 2,426 |
----------------------------------------------------------------------------------
-- Engineer: Zhiyang Ong
--
-- Create Date: 13:32:34 04/13/2010
-- Module Name: multiplier - Behavioral
-- Tool versions: Xilinx ISE 11.1
-- Description: Behavioral model of an unsigned
-- 32-bit multiplier.
-- Input: multiplicand, a[31:0]
-- Input: multiplier, b[31:0]
-- Output: product, out[63:0]
-- out[63:0] = a[31:0] * b[31:0]
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- This is written by Zhiyang Ong to refresh his
-- memory on digital VLSI design using VHDL.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Describe the I/O ports of the unsigned 32-bit
-- multiplier
entity mult32 is
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
b : in STD_LOGIC_VECTOR (31 downto 0);
op : out STD_LOGIC_VECTOR (63 downto 0));
end mult32;
-- Describe the behavior of the unsigned 32-bit
-- multiplier
architecture behaviorial of mult32 is
begin
process(a, b)
-- Temporary variables to store the operands
-- and the product
variable a_reg: std_logic_vector(31 downto 0);
variable b_reg: std_logic_vector(31 downto 0);
variable res_reg: std_logic_vector(63 downto 0);
begin
-- Store¡¡operands temporarily in these variables
a_reg := "11111111111111111111111111111111" and a;
b_reg := "11111111111111111111111111111111" and b;
-- Perform the following operations for each
-- bit of the multiplicand/multiplier reg,
-- which are assumed to have the same
-- bit-vector size.
-- Since the multiplicand/multiplier reg is
-- 32-bit wide, perform this loop 32 times.
for num_rep in 0 to 32 loop
-- If bit multiplier[0] == 0,
if b(0) = '1' then
-- pdt reg = pdt reg + multiplier reg
res_reg := res_reg + a;
end if;
-- Shift multiplicand reg left 1 bit
-- a_reg := a_reg sll 1;
a_reg := a_reg(30 downto 0) & '0';
-- Shift multiplier reg right 1 bit
-- b_reg := b_reg srl 1;
b_reg := '0' & b_reg(31 downto 1);
end loop;
-- Place the contents of the temporary output
-- register in "op"
op <= res_reg;
end process;
end behaviorial;
|
mit
|
1119362fa2010e7780f67a661830611a
| 0.589448 | 3.332418 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/example_design/sim/functional/sim_tb_top.vhd
| 2 | 16,400 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 8;
constant C3_P0_DATA_PORT_SIZE : integer := 64;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_reset_n : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
gpl-3.0
|
96bee01838a36058220417bd886dd51b
| 0.472683 | 3.689539 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
main.vhd
| 1 | 18,741 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.globals.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity main is
Port ( clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(6 downto 0);
an : out STD_LOGIC_VECTOR(3 downto 0);
Led : out STD_LOGIC_VECTOR(7 downto 0);
sw : in STD_LOGIC_VECTOR(7 downto 0);
btn : in STD_LOGIC_VECTOR(0 downto 0);
PhyMdc : out STD_LOGIC;
PhyMdio : inout STD_LOGIC;
PhyRstn : out STD_LOGIC;
PhyRxd : in STD_LOGIC_VECTOR(3 downto 0);
PhyRxDv : in STD_LOGIC;
PhyRxClk : in STD_LOGIC;
PhyTxd : out STD_LOGIC_VECTOR(3 downto 0);
PhyTxEn : out STD_LOGIC;
PhyTxClk : in STD_LOGIC;
PhyTxEr : out STD_LOGIC;
RsRx : in STD_LOGIC;
RsTx : out STD_LOGIC);
end main;
architecture Behavioral of main is
-- Turn button into reset - active '1'
signal rst : STD_LOGIC;
component debouncer is
PORT( clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end component;
COMPONENT enable_to_kick
PORT( Clk : IN std_logic;
Enable : IN std_logic;
Kick : OUT std_logic);
END COMPONENT;
-- General purpose counters
COMPONENT counter
GENERIC (N_BITS : integer);
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Cnt : OUT std_logic_vector(63 downto 0));
END COMPONENT;
signal cnt64 : std_logic_vector(63 downto 0);
COMPONENT counter_en
GENERIC (N_BITS : integer);
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Enable : in std_logic;
Cnt : OUT std_logic_vector(N_BITS - 1 downto 0));
END COMPONENT;
signal cnt_underflow_en, cnt_tx_pkt_en : std_logic;
signal cnt_underflow, cnt_rx_pkt, cnt_tx_pkt : std_logic_vector(35 downto 0);
COMPONENT disp
PORT( clk_i : IN std_logic;
rst_i : IN std_logic;
data_i : IN std_logic_vector(15 downto 0);
led_an_o : OUT std_logic_vector(3 downto 0);
led_seg_o : OUT std_logic_vector(6 downto 0));
END COMPONENT;
signal digit, d_tx : std_logic_vector(15 downto 0);
-- Ethernet control module
COMPONENT ethernet_control
PORT(
clk : IN std_logic;
rst : IN std_logic;
cnt_23 : IN std_logic;
cnt_22 : IN std_logic;
PhyRstn : OUT std_logic
);
END COMPONENT;
-- MDIO programming
COMPONENT mdio_ctrl
PORT( clk : IN std_logic;
rst : IN std_logic;
cnt_5 : IN std_logic;
cnt_23 : IN std_logic;
mdio_i : IN std_logic;
op : IN std_logic;
addr : IN std_logic_vector(4 downto 0);
data_i : IN std_logic_vector(15 downto 0);
kick : IN std_logic;
mdc : OUT std_logic;
mdio_o : OUT std_logic;
mdio_t : OUT std_logic;
data_o : OUT std_logic_vector(15 downto 0);
busy : OUT std_logic);
END COMPONENT;
signal mdio_trgr : STD_LOGIC;
signal mdio_i, mdio_o, mdio_t : STD_LOGIC;
signal mdio_op, mdio_kick, mdio_busy : STD_LOGIC;
signal mdio_addr : STD_LOGIC_VECTOR(4 downto 0);
signal mdio_in, mdio_out : STD_LOGIC_VECTOR(15 downto 0);
COMPONENT mdio_set_100Full
PORT( clk : in STD_LOGIC;
rst : in STD_LOGIC;
mdio_op : out STD_LOGIC;
mdio_addr : out STD_LOGIC_VECTOR (4 downto 0);
data_i : in STD_LOGIC_VECTOR (15 downto 0);
data_o : out STD_LOGIC_VECTOR (15 downto 0);
mdio_busy : in STD_LOGIC;
mdio_kick : out STD_LOGIC;
mnl_addr : in STD_LOGIC_VECTOR (4 downto 0);
mnl_trgr : in STD_LOGIC;
cfg_busy : out STD_LOGIC);
END COMPONENT;
signal mdio_cfg_busy : STD_LOGIC;
-- RX: Ethernet receive path
COMPONENT ethernet_receive
PORT( clk : IN std_logic;
rst : IN std_logic;
PhyRxd : IN std_logic_vector(3 downto 0);
PhyRxDv : IN std_logic;
PhyRxClk : IN std_logic;
Led : out std_logic_vector(4 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0);
busPkt : out STD_LOGIC;
busDesc : out STD_LOGIC);
END COMPONENT;
signal phyPkt, phyDesc : STD_LOGIC;
signal phyData : std_logic_vector(7 downto 0);
COMPONENT bus_tail_strip
GENERIC (N_BYTES : integer);
PORT( Clk : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector(7 downto 0));
END COMPONENT;
signal rxCrcPkt : STD_LOGIC;
signal rxCrcData : std_logic_vector(7 downto 0);
COMPONENT bus_get_last_nbits
GENERIC (N_BITS : integer);
PORT( Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
Value : out std_logic_vector(N_BITS - 1 downto 0);
ValueEn : out std_logic);
END COMPONENT;
signal rxPktTs : std_logic_vector(63 downto 0);
signal rxPktTsKick: std_logic;
-- TX: Ethernet tramsmit path
COMPONENT packet_mem
PORT( clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
signal pkt_mem_addr : std_logic_vector(10 downto 0);
signal pkt_mem_dout : std_logic_vector(7 downto 0);
COMPONENT mem_reader
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Enable : IN std_logic;
FrameLen : IN std_logic_vector(10 downto 0);
FrameIval : IN std_logic_vector(27 downto 0);
MemAddr : out STD_LOGIC_VECTOR (10 downto 0);
MemData : IN STD_LOGIC_VECTOR (7 downto 0);
BusPkt : OUT std_logic;
BusData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
signal memPkt : STD_LOGIC;
signal memData : std_logic_vector(7 downto 0);
signal TX_en : std_logic;
COMPONENT bus_append
GENERIC ( N_BYTES : integer );
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Value : in STD_LOGIC_VECTOR (N_BYTES*8 - 1 downto 0);
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
signal tsPkt : STD_LOGIC;
signal tsData : std_logic_vector(7 downto 0);
COMPONENT eth_add_crc
PORT( Clk : IN std_logic;
Rst : IN std_logic;
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
signal crcPkt : STD_LOGIC;
signal crcData : std_logic_vector(7 downto 0);
COMPONENT phy_tx is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
PhyTxd : out STD_LOGIC_VECTOR (3 downto 0);
PhyTxEn : out STD_LOGIC;
PhyTxClk : in STD_LOGIC;
PhyTxEr : out STD_LOGIC;
Led : out std_logic_vector(1 downto 0);
value : out std_logic_vector(15 downto 0);
sw : in std_logic_vector(7 downto 0);
data : in STD_LOGIC_VECTOR (7 downto 0);
busPkt : in STD_LOGIC;
busDesc : in STD_LOGIC);
end COMPONENT;
-- Statistics path
COMPONENT stat_calc
PORT( Time64 : IN std_logic_vector(63 downto 0);
Delay : IN std_logic_vector(31 downto 0);
Value : IN std_logic_vector(63 downto 0);
KickIn : IN std_logic;
Output : OUT std_logic_vector(63 downto 0);
KickOut : OUT std_logic;
Underflow : out std_logic);
END COMPONENT;
COMPONENT stat_compress
PORT( Clk : IN std_logic;
Value : IN std_logic_vector(63 downto 0);
KickIn : IN std_logic;
Statistic : OUT std_logic_vector(8 downto 0);
KickOut : OUT std_logic);
END COMPONENT;
signal stat_cprs_val : std_logic_vector(63 downto 0);
signal stat_cprs_kick : std_logic;
COMPONENT stat_writer
PORT( Clk : in std_logic;
Rst : in std_logic;
MemWe : out std_logic_vector(0 downto 0);
MemAddr : out std_logic_vector(8 downto 0);
MemDin : out std_logic_vector(35 downto 0);
MemDout : in std_logic_vector(35 downto 0);
Value : in std_logic_vector(8 downto 0);
Kick : in std_logic);
END COMPONENT;
signal stat_wr_kick : std_logic;
signal stat_wr_we : std_logic_vector(0 downto 0);
signal stat_wr_dout, stat_wr_din : std_logic_vector(35 downto 0);
signal stat_wr_addr, stat_wr_value : std_logic_vector(8 downto 0);
COMPONENT stat_mem
PORT( clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(35 DOWNTO 0));
END COMPONENT;
signal stat_read_addr : STD_LOGIC_VECTOR(8 DOWNTO 0);
signal stat_read_dout : STD_LOGIC_VECTOR(35 DOWNTO 0);
COMPONENT mod_uart_regs is
generic (UART_RATE : integer;
REQ_SIZE : integer);
port (Clk : in std_logic;
Rst : in std_logic;
RsRx : in std_logic;
RsTx : out std_logic;
RegBusStart : out reg_bus_t;
RegBusEnd : in reg_bus_t);
end COMPONENT;
type reg_chain is array (0 to 11) of reg_bus_t;
signal RegBus : reg_chain;
COMPONENT reg_ro is
generic (REG_BYTES : integer;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : in std_logic_vector(REG_BYTES*8 - 1 downto 0));
end COMPONENT;
COMPONENT reg is
generic (REG_BYTES : integer;
DEFAULT_VALUE : integer := 0;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : out std_logic_vector(REG_BYTES*8 - 1 downto 0));
end COMPONENT;
COMPONENT reg_byte is
generic (DEFAULT_VALUE : integer := 0;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : out byte_t);
end COMPONENT;
signal val_delay : std_logic_vector(31 downto 0);
signal val_pkt_ival : std_logic_vector(31 downto 0);
signal val_pkt_len : std_logic_vector(15 downto 0);
signal val_pmem_addr : std_logic_vector(15 downto 0);
signal val_pmem_dout : std_logic_vector(7 downto 0);
signal val_csr : std_logic_vector(7 downto 0);
COMPONENT reg_stat_reader is
generic (REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
MemAddr : out std_logic_vector (8 downto 0);
MemData : in std_logic_vector (35 downto 0));
end COMPONENT;
signal RstBtn : STD_LOGIC;
signal RstStats : STD_LOGIC;
signal LinkUp : STD_LOGIC;
signal stat_read_addr2 : std_logic_vector(15 downto 0);
BEGIN
stat_read_addr <= stat_read_addr2(stat_read_addr'range);
LinkUp <= not mdio_cfg_busy;
btnC_db : debouncer port map (clk, btn(0), RstBtn);
rst <= RstBtn or val_csr(0) when RISING_EDGE(clk);
RstStats <= rst or val_csr(1) when RISING_EDGE(clk);
TX_en <= LinkUp and val_csr(2) when RISING_EDGE(clk);
counter64: counter
GENERIC MAP( N_BITS => 64 )
PORT MAP(
Clk => clk,
Rst => rst,
Cnt => cnt64
);
Inst_ethernet_control: ethernet_control PORT MAP(
clk => clk,
rst => rst,
cnt_23 => cnt64(23),
cnt_22 => cnt64(22),
PhyRstn => PhyRstn
);
Inst_disp: disp PORT MAP(
clk_i => clk,
rst_i => rst,
data_i => digit,
led_an_o => an,
led_seg_o=> seg
);
mdio_iobuf : IOBUF
generic map (IOSTANDARD => "LVCMOS33")
port map (
O => mdio_i,
IO => PhyMdio,
I => mdio_o,
T => mdio_t
);
Inst_mdio_ctrl: mdio_ctrl PORT MAP(
clk => clk,
rst => rst,
cnt_5 => cnt64(5),
cnt_23 => cnt64(23),
mdc => PhyMdc,
mdio_i => mdio_i,
mdio_o => mdio_o,
mdio_t => mdio_t,
op => mdio_op,
addr => mdio_addr,
data_i => mdio_in,
data_o => mdio_out,
busy => mdio_busy,
kick => mdio_kick
);
Inst_mdio_set_100Full: mdio_set_100Full PORT MAP(
clk => clk,
rst => rst,
mdio_op => mdio_op,
mdio_addr => mdio_addr,
data_i => mdio_out,
data_o => mdio_in,
mdio_busy => mdio_busy,
mdio_kick => mdio_kick,
mnl_addr => sw(4 downto 0),
mnl_trgr => mdio_trgr,
cfg_busy => mdio_cfg_busy
);
Led(7) <= mdio_cfg_busy;
-- RX path
eth_rx : ethernet_receive PORT MAP(
clk => clk,
rst => rst,
Led => Led(4 downto 0),
PhyRxd => PhyRxd,
PhyRxDv => PhyRxDv,
PhyRxClk => PhyRxClk,
busPkt => phyPkt,
busDesc => phyDesc,
data => phyData
);
strip_crc: bus_tail_strip GENERIC MAP (N_BYTES => 4)
PORT MAP(
Clk => clk,
PktIn => phyPkt,
DataIn => phyData,
PktOut => rxCrcPkt,
DataOut => rxCrcData
);
get_tail : bus_get_last_nbits GENERIC MAP (N_BITS => 64)
PORT MAP(
Clk => clk,
Rst => rst,
PktIn => rxCrcPkt,
DataIn => rxCrcData,
Value => rxPktTs,
ValueEn => rxPktTsKick
);
-- TX path
pkt_mem : packet_mem port map (
clka => clk,
wea(0) => val_csr(7),
addra => val_pmem_addr(10 downto 0),
dina => val_pmem_dout,
clkb => clk,
addrb => pkt_mem_addr,
doutb => pkt_mem_dout
);
TX_mem_reader: mem_reader PORT MAP(
Clk => clk,
Rst => rst,
Enable => TX_en,
FrameLen => val_pkt_len(10 downto 0), -- b"001" & X"22",
FrameIval=> val_pkt_ival(27 downto 0), -- ( 14 => '1', others => '0' ),
MemAddr => pkt_mem_addr,
MemData => pkt_mem_dout,
BusPkt => memPkt,
BusData => memData
);
TX_eth_add_ts: bus_append
GENERIC MAP ( N_BYTES => 8 )
PORT MAP(
Clk => Clk,
Rst => Rst,
Value => cnt64,
InPkt => memPkt,
InData => memData,
OutPkt => tsPkt,
OutData => tsData
);
TX_eth_add_crc: eth_add_crc PORT MAP(
Clk => clk,
Rst => rst,
InPkt => tsPkt,
InData => tsData,
OutPkt => crcPkt,
OutData => crcData
);
TX_eth_tx : phy_tx PORT MAP (
clk => clk,
rst => rst,
Led => Led(6 downto 5),
PhyTxd => PhyTxd,
PhyTxEn => PhyTxEn,
PhyTxClk => PhyTxClk,
PhyTxEr => PhyTxEr,
value => d_tx,
sw => sw,
busPkt => crcPkt,
busDesc => '0',
data => crcData
);
digit <= mdio_out when mdio_trgr = '1' else
d_tx;
-- Statistics path
STAT_stat_calc: stat_calc PORT MAP(
Time64 => cnt64,
Delay => val_delay, -- X"0007A120", -- 5ms
Value => rxPktTs,
KickIn => rxPktTsKick,
Output => stat_cprs_val,
KickOut => stat_cprs_kick,
Underflow => cnt_underflow_en
);
STAT_stat_compress: stat_compress PORT MAP(
Clk => clk,
Value => stat_cprs_val,
KickIn => stat_cprs_kick,
Statistic => stat_wr_value,
KickOut => stat_wr_kick
);
STAT_stat_writer: stat_writer PORT MAP(
Clk => clk,
Rst => RstStats,
MemWe => stat_wr_we,
MemAddr => stat_wr_addr,
MemDin => stat_wr_din,
MemDout => stat_wr_dout,
Value => stat_wr_value,
Kick => stat_wr_kick
);
statistics_memory : stat_mem PORT MAP (
clka => clk,
wea => stat_wr_we,
addra => stat_wr_addr,
dina => stat_wr_din,
douta => stat_wr_dout,
clkb => clk,
web => "0",
addrb => stat_read_addr,
dinb => ( others => '0' ),
doutb => stat_read_dout
);
CNT_udrfl : counter_en GENERIC MAP (N_BITS => 36)
PORT MAP(clk, RstStats, cnt_underflow_en, cnt_underflow);
CNT_rxpkt : counter_en GENERIC MAP (N_BITS => 36)
PORT MAP(clk, RstStats, rxPktTsKick, cnt_rx_pkt);
E2K_tx_pkt : enable_to_kick PORT MAP(clk, memPkt, cnt_tx_pkt_en);
CNT_txpkt : counter_en GENERIC MAP (N_BITS => 36)
PORT MAP(clk, RstStats, cnt_tx_pkt_en, cnt_tx_pkt);
reg_master : mod_uart_regs
GENERIC MAP (UART_RATE => 115200,
REQ_SIZE => 4)
PORT MAP (Clk => clk,
Rst => rst,
RsRx => RsRx,
RsTx => RsTx,
RegBusStart => RegBus(0),
RegBusEnd => RegBus(11)
);
REG_csr : reg_byte
GENERIC MAP (REG_ADDR_BASE => b"000000")
PORT MAP (clk, rst, RegBus(0), RegBus(1), val_csr);
REG_pmem_data : reg_byte
GENERIC MAP (REG_ADDR_BASE => b"000001")
PORT MAP (clk, rst, RegBus(1), RegBus(2), val_pmem_dout);
REG_pmem_addr : reg
GENERIC MAP (REG_BYTES => 2, REG_ADDR_BASE => b"000010")
PORT MAP (clk, rst, RegBus(2), RegBus(3), val_pmem_addr);
REG_pkt_len : reg
GENERIC MAP (REG_BYTES => 2, REG_ADDR_BASE => b"000100")
PORT MAP (clk, rst, RegBus(3), RegBus(4), val_pkt_len);
REG_pkt_ival : reg
GENERIC MAP (REG_BYTES => 4, REG_ADDR_BASE => b"001000")
PORT MAP (clk, rst, RegBus(4), RegBus(5), val_pkt_ival);
REG_delay : reg
GENERIC MAP (REG_BYTES => 4, REG_ADDR_BASE => b"001100")
PORT MAP (clk, rst, RegBus(5), RegBus(6), val_delay);
REG_uflow : reg_ro
GENERIC MAP (REG_BYTES => 8, REG_ADDR_BASE => b"010000")
PORT MAP (clk, rst, RegBus(6), RegBus(7), X"0000000" & cnt_underflow);
REG_tx_cnt : reg_ro
GENERIC MAP (REG_BYTES => 8, REG_ADDR_BASE => b"011000")
PORT MAP (clk, rst, RegBus(7), RegBus(8), X"0000000" & cnt_tx_pkt);
REG_rx_cnt : reg_ro
GENERIC MAP (REG_BYTES => 8, REG_ADDR_BASE => b"100000")
PORT MAP (clk, rst, RegBus(8), RegBus(9), X"0000000" & cnt_rx_pkt);
REG_saddr : reg
GENERIC MAP (REG_BYTES => 2, REG_ADDR_BASE => b"101000")
PORT MAP (clk, rst, RegBus(9), RegBus(10), stat_read_addr2);
REG_sdout : reg_ro
GENERIC MAP (REG_BYTES => 8, REG_ADDR_BASE => b"110000")
PORT MAP (clk, rst, RegBus(10), RegBus(11), X"0000000" & stat_read_dout);
end Behavioral;
|
gpl-3.0
|
8b9de8d4cfdaa8c4d72e967df6b24b34
| 0.599168 | 2.724379 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/DAPwm_tb.vhd
| 1 | 2,826 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:17 02/10/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/Source/AudioIO/DAPwm_tb.vhd
-- Project Name: SoundboxProject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DAPwm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DAPwm_tb IS
END DAPwm_tb;
ARCHITECTURE behavior OF DAPwm_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DAPwm
PORT(
input : IN std_logic_vector(11 downto 0);
output : OUT std_logic;
clk : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(11 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal inputNumber : natural := 0;
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant sample_period : time := 40960 ns;
BEGIN
input <= std_logic_vector(to_unsigned(inputNumber, input'high+1));
-- Instantiate the Unit Under Test (UUT)
uut: DAPwm PORT MAP (
input => input,
output => output,
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait for 20000 ns;
inputNumber <= 5;
wait for sample_period;
inputNumber <= 4095;
wait for sample_period;
inputNumber <= 4094;
wait for sample_period;
inputNumber <= 4095;
wait for sample_period;
inputNumber <= 5;
wait for sample_period;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
8727d1e283b5e6536f18c7702af7e97e
| 0.591649 | 4.019915 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_Equalizer_Low_Pass.vhd
| 1 | 3,371 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer_Low_Pass is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_Equalizer_Low_Pass;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer_Low_Pass is
begin
Generic_Equalizer : entity work.Generic_Equalizer
generic map(NO_SECTIONS => 9,
INPUT_WIDTH => 16,
INPUT_FRACT => 14,
OUTPUT_WIDTH => 16,
OUTPUT_FRACT => 14,
SCALE_WIDTH => 16,
SCALE_FRACT => (14,14,14,14,14,14,14,14,14,14),
INTERNAL_WIDTH => 30,
INTERNAL_FRACT => 24,
COEFF_WIDTH_B => 16,
COEFF_FRACT_B => (16,14,14,14,14,14,14,14,14),
COEFF_WIDTH_A => 16,
COEFF_FRACT_A => (14,14,14,14,14,14,14,14,14))
port map(clk => clk,
reset => reset,
x => input,
scale => (x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b0 => (x"3e74"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b1 => (x"8a7f"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
b2 => (x"3777"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a1 => (x"754C"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a2 => (x"C9E0"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
y => output);
end architecture;
|
mit
|
13899dfa95a7bad7dd6f01333ac5ad50
| 0.260457 | 4.694986 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_IIR.vhd
| 1 | 9,573 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- Implementation of a discrete-time, direct-form I IIR filter. --
-- This filter uses fixed point arithmetic to do it's calculations and can be --
-- described by the following mathematical formula: --
-- Y[k] = B0*X[k] + B1*X[k-1] + Bn*X[k-n] + A1*Y[k-1] + An*Y[k-n] --
-- --
-- --
-- Generic: --
-- ORDER - The order of the filter --
-- IN_WIDTH - The width of the input signal --
-- IN_FRACT - The width of the fractional part of the input signal --
-- B_WIDTH - The width of the B coefficients --
-- B_FRACT - The width of the fractional part of the B --
-- coefficients --
-- A_WIDTH - The width of the A coefficients --
-- A_FRACT - The width of the fractional part of the A --
-- coefficients --
-- INTERNAL_WIDTH - The width of internal states of the filter --
-- INTERNAL_FRACT - The width of the fractional part of internal states in --
-- the filter --
-- OUT_WIDTH - The width of the output signal --
-- OUT_FRACT - The width of the fractional part of the output signal --
-- --
-- --
-- Input/Output: --
-- clk - System clock --
-- reset - Asynchronous reset that resets when high --
-- x - Input signal to be filtered --
-- B - An array containing all the B-coefficients starting --
-- with B0 --
-- A - An array containing all the A-coefficients starting --
-- with A1 --
-- y - Output signal --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_IIR is
generic (ORDER : natural := 2;
IN_WIDTH : natural := 8;
IN_FRACT : natural := 6;
B_WIDTH : natural := 8;
B_FRACT : natural := 6;
A_WIDTH : natural := 8;
A_FRACT : natural := 6;
INTERNAL_WIDTH : natural := 12;
INTERNAL_FRACT : natural := 8;
OUT_WIDTH : natural := 8;
OUT_FRACT : natural := 6);
port(clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(IN_WIDTH-1 downto 0);
B : in std_logic_vector((B_WIDTH*(ORDER+1))-1 downto 0);
A : in std_logic_vector((A_WIDTH*ORDER)-1 downto 0);
y : out std_logic_vector(OUT_WIDTH-1 downto 0));
end Generic_IIR;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_IIR is
-- Constants
constant N : natural := ORDER + 1;
constant IN_INT : natural := IN_WIDTH - IN_FRACT;
constant B_INT : natural := B_WIDTH - B_FRACT;
constant A_INT : natural := A_WIDTH - A_FRACT;
constant INTERNAL_INT : natural := INTERNAL_WIDTH - INTERNAL_FRACT;
constant OUT_INT : natural := OUT_WIDTH - OUT_FRACT;
-- Type declarations
type array_b_coeffecient is array(0 to N-1) of std_logic_vector(B_WIDTH-1 downto 0);
type array_a_coeffecient is array(1 to N-1) of std_logic_vector(A_WIDTH-1 downto 0);
type array_internal is array(0 to N-1) of std_logic_vector(INTERNAL_WIDTH-1 downto 0);
type array_internal_a is array(1 to N-1) of std_logic_vector(INTERNAL_WIDTH-1 downto 0);
-- Coefficients
signal coefficients_b : array_b_coeffecient;
signal coefficients_a : array_a_coeffecient;
-- Signal Declarations
signal input_copy : std_logic_vector(INTERNAL_WIDTH-1 downto 0);
signal my_inputs : array_internal := (others => (others => '0'));
signal my_outputs : array_internal := (others => (others => '0'));
signal my_mults_in : array_internal := (others => (others => '0'));
signal my_mults_out : array_internal_a := (others => (others => '0'));
signal my_sum_in : array_internal := (others => (others => '0'));
signal my_sum_out : array_internal := (others => (others => '0'));
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Assign coefficients
assign_coefficients:
for i in 1 to N-1 generate
coefficients_b(i) <= B(B_WIDTH*(N-i)-1 downto B_WIDTH*(N-i-1));
coefficients_a(i) <= A(A_WIDTH*(N-i)-1 downto A_WIDTH*(N-i-1));
end generate assign_coefficients;
coefficients_b(0) <= B(B_WIDTH*N-1 downto B_WIDTH*(N-1));
-- Prepare input to fit into internal bit width
input_copy(INTERNAL_WIDTH-1 downto INTERNAL_FRACT + IN_INT) <= (others => x(IN_WIDTH-1));
input_copy(INTERNAL_FRACT + IN_INT-1 downto INTERNAL_FRACT - IN_FRACT) <= x;
input_copy(INTERNAL_FRACT - IN_FRACT-1 downto 0) <= (others => x(IN_WIDTH-1));
-- Shift input and ouput
VectorRegisterIn0 : entity work.VectorRegister
generic map (
wordLength => INTERNAL_WIDTH)
port map (
input => input_copy,
output => my_inputs(0),
clk => clk,
reset => reset);
my_outputs(0) <= my_sum_out(0);
gen_shifts:
for i in 0 to N-2 generate
VectorRegisterIn : entity work.VectorRegister
generic map (
wordLength => INTERNAL_WIDTH)
port map (
input => my_inputs(i),
output => my_inputs(i+1),
clk => clk,
reset => reset);
VectorRegisterOut : entity work.VectorRegister
generic map (
wordLength => INTERNAL_WIDTH)
port map (
input => my_outputs(i),
output => my_outputs(i+1),
clk => clk,
reset => reset);
end generate gen_shifts;
-- Multiply the input with coefficients
gen_mults_in:
for i in 0 to N-1 generate
Multiplier_in : entity work.Multiplier_Saturate
generic map(X_WIDTH => INTERNAL_WIDTH,
X_FRACTION => INTERNAL_FRACT,
Y_WIDTH => B_WIDTH,
Y_FRACTION => B_FRACT,
S_WIDTH => INTERNAL_WIDTH,
S_FRACTION => INTERNAL_FRACT)
port map(x => my_inputs(i),
y => coefficients_b(i),
s => my_mults_in(i));
end generate gen_mults_in;
-- Add the input multiplications together
my_sum_in(N-1) <= my_mults_in(N-1);
gen_adds_in:
for i in 0 to N-2 generate
AdderSat_in : entity work.AdderSat
generic map(wordLength => INTERNAL_WIDTH)
port map(a => my_mults_in(i),
b => my_sum_in(i+1),
s => my_sum_in(i));
end generate gen_adds_in;
-- Add the output multiplications together
my_sum_out(N-1) <= my_mults_out(N-1);
AdderSat_Out_0 : entity work.AdderSat
generic map(wordLength => INTERNAL_WIDTH)
port map(a => my_sum_in(0),
b => my_sum_out(1),
s => my_sum_out(0));
gen_adds_out:
for i in 1 to N-2 generate
AdderSat_out : entity work.AdderSat
generic map(wordLength => INTERNAL_WIDTH)
port map(a => my_mults_out(i),
b => my_sum_out(i+1),
s => my_sum_out(i));
end generate gen_adds_out;
-- Multiply the output with coefficients
gen_mults_out:
for i in 1 to N-1 generate
Multiplier_out : entity work.Multiplier_Saturate
generic map(X_WIDTH => INTERNAL_WIDTH,
X_FRACTION => INTERNAL_FRACT,
Y_WIDTH => A_WIDTH,
Y_FRACTION => A_FRACT,
S_WIDTH => INTERNAL_WIDTH,
S_FRACTION => INTERNAL_FRACT)
port map(x => my_outputs(i),
y => coefficients_a(i),
s => my_mults_out(i));
end generate gen_mults_out;
-- Output the result
y <= my_outputs(0)(INTERNAL_FRACT + OUT_INT-1 downto INTERNAL_FRACT - OUT_FRACT);
end behaviour;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
|
mit
|
4a32f78fdbc553b3b79a85cb35f7b5f7
| 0.448135 | 4.40543 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/Router_32_bit_credit_based.vhd
| 1 | 21,473 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.router_pack.all;
entity router_credit_based is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
NoC_size_x: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
credit_in_vc_N, credit_in_vc_E, credit_in_vc_W, credit_in_vc_S, credit_in_vc_L: in std_logic;
valid_in_vc_N, valid_in_vc_E, valid_in_vc_W, valid_in_vc_S, valid_in_vc_L : in std_logic;
valid_out_vc_N, valid_out_vc_E, valid_out_vc_W, valid_out_vc_S, valid_out_vc_L : out std_logic;
credit_out_vc_N, credit_out_vc_E, credit_out_vc_W, credit_out_vc_S, credit_out_vc_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_credit_based;
architecture behavior of router_credit_based is
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_D_out_vc_N, FIFO_D_out_vc_E, FIFO_D_out_vc_W, FIFO_D_out_vc_S, FIFO_D_out_vc_L: std_logic_vector(DATA_WIDTH-1 downto 0);
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Grant_NN_vc, Grant_NE_vc, Grant_NW_vc, Grant_NS_vc, Grant_NL_vc: std_logic;
signal Grant_EN_vc, Grant_EE_vc, Grant_EW_vc, Grant_ES_vc, Grant_EL_vc: std_logic;
signal Grant_WN_vc, Grant_WE_vc, Grant_WW_vc, Grant_WS_vc, Grant_WL_vc: std_logic;
signal Grant_SN_vc, Grant_SE_vc, Grant_SW_vc, Grant_SS_vc, Grant_SL_vc: std_logic;
signal Grant_LN_vc, Grant_LE_vc, Grant_LW_vc, Grant_LS_vc, Grant_LL_vc: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal Req_NN_vc, Req_EN_vc, Req_WN_vc, Req_SN_vc, Req_LN_vc: std_logic;
signal Req_NE_vc, Req_EE_vc, Req_WE_vc, Req_SE_vc, Req_LE_vc: std_logic;
signal Req_NW_vc, Req_EW_vc, Req_WW_vc, Req_SW_vc, Req_LW_vc: std_logic;
signal Req_NS_vc, Req_ES_vc, Req_WS_vc, Req_SS_vc, Req_LS_vc: std_logic;
signal Req_NL_vc, Req_EL_vc, Req_WL_vc, Req_SL_vc, Req_LL_vc: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal empty_vc_N, empty_vc_E, empty_vc_W, empty_vc_S, empty_vc_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(9 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N, valid_in_vc => valid_in_vc_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
read_en_vc_N => '0', read_en_vc_E =>Grant_EN_vc, read_en_vc_W =>Grant_WN_vc, read_en_vc_S =>Grant_SN_vc, read_en_vc_L =>Grant_LN_vc,
credit_out => credit_out_N, credit_out_vc => credit_out_vc_N, empty_out => empty_N, empty_out_vc => empty_vc_N, Data_out => FIFO_D_out_N, Data_out_vc => FIFO_D_out_vc_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E, valid_in_vc => valid_in_vc_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
read_en_vc_N => Grant_NE_vc, read_en_vc_E =>'0', read_en_vc_W =>Grant_WE_vc, read_en_vc_S =>Grant_SE_vc, read_en_vc_L =>Grant_LE_vc,
credit_out => credit_out_E, credit_out_vc => credit_out_vc_E, empty_out => empty_E, empty_out_vc => empty_vc_E, Data_out => FIFO_D_out_E, Data_out_vc => FIFO_D_out_vc_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W, valid_in_vc => valid_in_vc_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
read_en_vc_N => Grant_NW_vc, read_en_vc_E =>Grant_EW_vc, read_en_vc_W =>'0', read_en_vc_S =>Grant_SW_vc, read_en_vc_L =>Grant_LW_vc,
credit_out => credit_out_W, credit_out_vc => credit_out_vc_W, empty_out => empty_W, empty_out_vc => empty_vc_W, Data_out => FIFO_D_out_W, Data_out_vc => FIFO_D_out_vc_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S, valid_in_vc => valid_in_vc_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
read_en_vc_N => Grant_NS_vc, read_en_vc_E =>Grant_ES_vc, read_en_vc_W =>Grant_WS_vc, read_en_vc_S =>'0', read_en_vc_L =>Grant_LS_vc,
credit_out => credit_out_S, credit_out_vc => credit_out_vc_S, empty_out => empty_S, empty_out_vc => empty_vc_S, Data_out => FIFO_D_out_S, Data_out_vc => FIFO_D_out_vc_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L, valid_in_vc => valid_in_vc_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
read_en_vc_N => Grant_NL_vc, read_en_vc_E =>Grant_EL_vc, read_en_vc_W =>Grant_WL_vc, read_en_vc_S =>Grant_SL_vc, read_en_vc_L =>'0',
credit_out => credit_out_L, credit_out_vc => credit_out_vc_L, empty_out => empty_L, empty_out_vc => empty_vc_L, Data_out => FIFO_D_out_L, Data_out_vc => FIFO_D_out_vc_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_N(14 downto 8),
dst_addr_x => FIFO_D_out_N(7 downto 1),
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_E(14 downto 8),
dst_addr_x => FIFO_D_out_E(7 downto 1),
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_W(14 downto 8),
dst_addr_x => FIFO_D_out_W(7 downto 1),
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_S(14 downto 8),
dst_addr_x => FIFO_D_out_S(7 downto 1),
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_L(14 downto 8),
dst_addr_x => FIFO_D_out_L(7 downto 1),
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
--VC LBDRs
LBDR_vc_N: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_vc_N,
flit_type => FIFO_D_out_vc_N(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_vc_N(14 downto 8),
dst_addr_x => FIFO_D_out_vc_N(7 downto 1),
grant_N => '0', grant_E =>Grant_EN_vc, grant_W => Grant_WN_vc, grant_S=>Grant_SN_vc, grant_L =>Grant_LN_vc,
Req_N=> Req_NN_vc, Req_E=>Req_NE_vc, Req_W=>Req_NW_vc, Req_S=>Req_NS_vc, Req_L=>Req_NL_vc);
LBDR_vc_E: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_vc_E,
flit_type => FIFO_D_out_vc_E(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_vc_E(14 downto 8),
dst_addr_x => FIFO_D_out_vc_E(7 downto 1),
grant_N => Grant_NE_vc, grant_E =>'0', grant_W => Grant_WE_vc, grant_S=>Grant_SE_vc, grant_L =>Grant_LE_vc,
Req_N=> Req_EN_vc, Req_E=>Req_EE_vc, Req_W=>Req_EW_vc, Req_S=>Req_ES_vc, Req_L=>Req_EL_vc);
LBDR_vc_W: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_vc_W,
flit_type => FIFO_D_out_vc_W(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_vc_W(14 downto 8),
dst_addr_x => FIFO_D_out_vc_W(7 downto 1),
grant_N => Grant_NW_vc, grant_E =>Grant_EW_vc, grant_W =>'0' ,grant_S=>Grant_SW_vc, grant_L =>Grant_LW_vc,
Req_N=> Req_WN_vc, Req_E=>Req_WE_vc, Req_W=>Req_WW_vc, Req_S=>Req_WS_vc, Req_L=>Req_WL_vc);
LBDR_vc_S: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_vc_S,
flit_type => FIFO_D_out_vc_S(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_vc_S(14 downto 8),
dst_addr_x => FIFO_D_out_vc_S(7 downto 1),
grant_N => Grant_NS_vc, grant_E =>Grant_ES_vc, grant_W =>Grant_WS_vc ,grant_S=>'0', grant_L =>Grant_LS_vc,
Req_N=> Req_SN_vc, Req_E=>Req_SE_vc, Req_W=>Req_SW_vc, Req_S=>Req_SS_vc, Req_L=>Req_SL_vc);
LBDR_vc_L: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_vc_L,
flit_type => FIFO_D_out_vc_L(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_vc_L(14 downto 8),
dst_addr_x => FIFO_D_out_vc_L(7 downto 1),
grant_N => Grant_NL_vc, grant_E =>Grant_EL_vc, grant_W => Grant_WL_vc,grant_S=>Grant_SL_vc, grant_L =>'0',
Req_N=> Req_LN_vc, Req_E=>Req_LE_vc, Req_W=>Req_LW_vc, Req_S=>Req_LS_vc, Req_L=>Req_LL_vc);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL,
-- vc signals
credit_in_vc_N => credit_in_vc_N, credit_in_vc_E => credit_in_vc_E, credit_in_vc_W => credit_in_vc_W, credit_in_vc_S => credit_in_vc_S, credit_in_vc_L => credit_in_vc_L,
req_N_N_vc => '0', req_N_E_vc => Req_NE_vc, req_N_W_vc => Req_NW_vc, req_N_S_vc => Req_NS_vc, req_N_L_vc => Req_NL_vc,
req_E_N_vc => Req_EN_vc, req_E_E_vc => '0', req_E_W_vc => Req_EW_vc, req_E_S_vc => Req_ES_vc, req_E_L_vc => Req_EL_vc,
req_W_N_vc => Req_WN_vc, req_W_E_vc => Req_WE_vc, req_W_W_vc => '0', req_W_S_vc => Req_WS_vc, req_W_L_vc => Req_WL_vc,
req_S_N_vc => Req_SN_vc, req_S_E_vc => Req_SE_vc, req_S_W_vc => Req_SW_vc, req_S_S_vc => '0', req_S_L_vc => Req_SL_vc,
req_L_N_vc => Req_LN_vc, req_L_E_vc => Req_LE_vc, req_L_W_vc => Req_LW_vc, req_L_S_vc => Req_LS_vc, req_L_L_vc => '0',
empty_vc_N => empty_vc_N, empty_vc_E => empty_vc_E, empty_vc_w => empty_vc_W, empty_vc_S => empty_vc_S, empty_vc_L => empty_vc_L,
valid_vc_N => valid_out_vc_N, valid_vc_E => valid_out_vc_E, valid_vc_W => valid_out_vc_W, valid_vc_S => valid_out_vc_S, valid_vc_L => valid_out_vc_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N_vc => Grant_NN_vc, grant_N_E_vc => Grant_NE_vc, grant_N_W_vc => Grant_NW_vc, grant_N_S_vc => Grant_NS_vc, grant_N_L_vc => Grant_NL_vc,
grant_E_N_vc => Grant_EN_vc, grant_E_E_vc => Grant_EE_vc, grant_E_W_vc => Grant_EW_vc, grant_E_S_vc => Grant_ES_vc, grant_E_L_vc => Grant_EL_vc,
grant_W_N_vc => Grant_WN_vc, grant_W_E_vc => Grant_WE_vc, grant_W_W_vc => Grant_WW_vc, grant_W_S_vc => Grant_WS_vc, grant_W_L_vc => Grant_WL_vc,
grant_S_N_vc => Grant_SN_vc, grant_S_E_vc => Grant_SE_vc, grant_S_W_vc => Grant_SW_vc, grant_S_S_vc => Grant_SS_vc, grant_S_L_vc => Grant_SL_vc,
grant_L_N_vc => Grant_LN_vc, grant_L_E_vc => Grant_LE_vc, grant_L_W_vc => Grant_LW_vc, grant_L_S_vc => Grant_LS_vc, grant_L_L_vc => Grant_LL_vc
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE_vc & Grant_NW_vc & Grant_NS_vc & Grant_NL_vc & '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN_vc & '0' & Grant_EW_vc & Grant_ES_vc & Grant_EL_vc & Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN_vc & Grant_WE_vc & '0' & Grant_WS_vc & Grant_WL_vc & Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN_vc & Grant_SE_vc & Grant_SW_vc & '0' & Grant_SL_vc & Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN_vc & Grant_LE_vc & Grant_LW_vc & Grant_LS_vc & '0' & Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
North_vc_in => FIFO_D_out_vc_N, East_vc_in => FIFO_D_out_vc_E, West_vc_in => FIFO_D_out_vc_W, South_vc_in => FIFO_D_out_vc_S, Local_vc_in => FIFO_D_out_vc_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
North_vc_in => FIFO_D_out_vc_N, East_vc_in => FIFO_D_out_vc_E, West_vc_in => FIFO_D_out_vc_W, South_vc_in => FIFO_D_out_vc_S, Local_vc_in => FIFO_D_out_vc_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
North_vc_in => FIFO_D_out_vc_N, East_vc_in => FIFO_D_out_vc_E, West_vc_in => FIFO_D_out_vc_W, South_vc_in => FIFO_D_out_vc_S, Local_vc_in => FIFO_D_out_vc_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
North_vc_in => FIFO_D_out_vc_N, East_vc_in => FIFO_D_out_vc_E, West_vc_in => FIFO_D_out_vc_W, South_vc_in => FIFO_D_out_vc_S, Local_vc_in => FIFO_D_out_vc_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
North_vc_in => FIFO_D_out_vc_N, East_vc_in => FIFO_D_out_vc_E, West_vc_in => FIFO_D_out_vc_W, South_vc_in => FIFO_D_out_vc_S, Local_vc_in => FIFO_D_out_vc_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
gpl-3.0
|
6cc76761cc7c3c581e21b19e893708ca
| 0.553486 | 2.589917 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/display.vhd
| 3 | 2,909 |
----------------------------------------------------------------------------------
-- display.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Provides 7 segment display multiplexing.
-- No encoding is performed. Input will be displayed in raw format.
-- This allows to display 32bit on the on-board 4 digit display.
-- (The dot serves as 8th bit.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity display is
Port ( data : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
an : inout std_logic_vector (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0));
end display;
architecture Behavioral of display is
signal counter : STD_LOGIC_VECTOR (17 downto 0);
begin
an(0) <= counter(17) or counter(16);
an(1) <= counter(17) or not counter(16);
an(2) <= not counter(17) or counter(16);
an(3) <= not counter(17) or not counter(16);
segment(0) <= not ((an(0) or data(0)) and (an(1) or data( 8)) and (an(2) or data(16)) and (an(3) or data(24)));
segment(1) <= not ((an(0) or data(1)) and (an(1) or data( 9)) and (an(2) or data(17)) and (an(3) or data(25)));
segment(2) <= not ((an(0) or data(2)) and (an(1) or data(10)) and (an(2) or data(18)) and (an(3) or data(26)));
segment(3) <= not ((an(0) or data(3)) and (an(1) or data(11)) and (an(2) or data(19)) and (an(3) or data(27)));
segment(4) <= not ((an(0) or data(4)) and (an(1) or data(12)) and (an(2) or data(20)) and (an(3) or data(28)));
segment(5) <= not ((an(0) or data(5)) and (an(1) or data(13)) and (an(2) or data(21)) and (an(3) or data(29)));
segment(6) <= not ((an(0) or data(6)) and (an(1) or data(14)) and (an(2) or data(22)) and (an(3) or data(30)));
segment(7) <= not ((an(0) or data(7)) and (an(1) or data(15)) and (an(2) or data(23)) and (an(3) or data(31)));
process(clock)
begin
if rising_edge(clock) then
counter <= counter + 1;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
074626b48ce8d7afdd0fd84831c8cac5
| 0.599175 | 3.214365 | false | false | false | false |
metaspace/ghdl_extra
|
int_bool/sha-1.vhdl
| 1 | 2,657 |
-- sha-1.vhdl : microbenchmark pour simulation comportementale
-- création : 2011/02/01 par [email protected]
-- code dérivé du pseudo-code disponible à http://en.wikipedia.org/wiki/SHA-1
library work;
-- Décommenter l'une de ces 4 possibilités :
-- version integer simple :
--use work.int_ops.all;
--use work.int_integer.all;
-- version integer avec détection des dépassements :
--use work.int_ops.all;
--use work.int_integer_range.all;
-- version à base de bit_vector :
use work.int_bitvector.all;
library IEEE; use IEEE.numeric_bit.all;
-- version à base de std_ulogic_vector :
--use work.int_sulv.all;
--library IEEE; use IEEE.numeric_std.all;
entity sha1 is end sha1;
architecture comportement of sha1 is
begin
process
constant k1 : int_32 := from_int( 1518500249,32); -- sqrt( 2)*2^30
constant k2 : int_32 := from_int( 1859775393,32); -- sqrt( 3)*2^30
constant k3 : int_32 := from_int( -253476060,32); -- sqrt( 5)*2^30
constant k4 : int_32 := from_int(-1247986134,32); -- sqrt(10)*2^30
variable i, j: integer; -- compteurs de boucles
variable h0 : int_32 := from_int( 19088743,32); -- 0x01234567
variable h1 : int_32 := from_int(-1985229329,32); -- 0x89ABCDEF
variable h2 : int_32 := from_int( -19088744,32); -- 0xFEDCBA98
variable h3 : int_32 := from_int( 1985229328,32); -- 0x76543210
variable h4 : int_32 := from_int( -253635901,32); -- 0xF0E1D2C3
variable A, B, C, D, E, F, k, t : int_32;
type type_array80 is array(0 to 79) of int_32;
variable w : type_array80;
begin
-- boucle principale (à faire varier pour prendre plus de temps) :
for j in 0 to 200 loop
-- expansion des 16 premiers mots :
for i in 16 to 79 loop
w(i) := (w(i-3) xor w(i-8) xor w(i-14) xor w(i-16)) rol 1;
end loop;
-- initialisation des variables :
A:=h0; B:=h1; C:=h2; D:=h3; E:=h4;
for i in 0 to 79 loop
if i < 40 then
if i < 20 then
F := (B and C) or ((not B) and D);
k := k1;
else
F := B xor C xor D;
k := k2;
end if;
else
if i < 60 then
F := (B and C) or (B and D) or (C and D);
k := k3;
else
F := B xor C xor D;
k := k4;
end if;
end if;
t := (A rol 5) + F + E + k + w(i);
E := D; D := C;
C := B rol 30;
B := A; A := t;
end loop;
-- recombinaison des résultats :
h0 := h0 + A; h1 := h1 + B;
h2 := h2 + C; h3 := h3 + D;
h4 := h4 + E;
end loop;
wait;
end process;
end comportement;
|
gpl-3.0
|
91ce2b1913382108f6e34e7445f2e2e2
| 0.559546 | 2.897043 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/ddr3k7-core/ddr3_ctrl_wb.vhd
| 1 | 28,994 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.ddr3_ctrl_pkg.all;
entity ddr3_ctrl_wb is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64
);
port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_sr_req_o : out std_logic;
ddr_ref_req_o : out std_logic;
ddr_zq_req_o : out std_logic;
ddr_sr_active_i : in std_logic;
ddr_ref_ack_i : in std_logic;
ddr_zq_ack_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_ui_clk_sync_rst_i : in std_logic;
ddr_init_calib_complete_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(32 - 1 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Debug ports
----------------------------------------------------------------------------
ddr_wb_rd_mask_dout_do : out std_logic_vector(7 downto 0);
ddr_wb_rd_mask_addr_dout_do : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_rd_mask_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_data_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_fifo_full_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_empty_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_rd_do : out std_logic_vector(1 downto 0)
);
end entity ddr3_ctrl_wb;
architecture behavioral of ddr3_ctrl_wb is
--------------------------------------
-- Constants
--------------------------------------
constant c_write_wait_time : unsigned(9 downto 0) := TO_UNSIGNED(15, 10);
constant c_read_wait_time : unsigned(9 downto 0) := TO_UNSIGNED(15, 10);
constant c_register_shift_size : integer := 8;
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal wb_wr_data_shift_a : data_array;
signal wb_wr_data_shift_next_a : data_array;
signal wb_wr_data_shift_s : std_logic_vector(511 downto 0);
signal wb_wr_mask_shift_a : mask_array;
signal wb_wr_mask_shift_next_a : mask_array;
signal wb_wr_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_addr_shift_a : addr_array;
signal wb_wr_addr_shift_next_a : addr_array;
signal wb_wr_shifting_s : std_logic;
signal wb_wr_match_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_row_a : row_array;
signal wb_wr_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_several_row_s : std_logic;
signal wb_wr_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_wr_shift_flush_s : std_logic;
signal wb_wr_shift_flush_1_s : std_logic;
signal fifo_wb_wr_mask_s : std_logic_vector(63 downto 0);
signal fifo_wb_wr_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_wr_din_s : std_logic_vector(604 downto 0);
signal fifo_wb_wr_wr_s : std_logic;
signal fifo_wb_wr_rd_s : std_logic;
signal fifo_wb_wr_rd_d : std_logic;
signal fifo_wb_wr_dout_s : std_logic_vector(604 downto 0);
signal fifo_wb_wr_full_s : std_logic;
signal fifo_wb_wr_empty_s : std_logic;
signal wb_rd_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_data_shift_a : data_array;
signal wb_rd_ack_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_addr_shift_a : addr_array;
signal wb_rd_addr_shift_next_a : addr_array;
signal wb_rd_addr_ref_a : addr_array;
signal wb_rd_shifting_s : std_logic;
signal wb_rd_match_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_row_a : row_array;
signal wb_rd_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_several_row_s : std_logic;
signal wb_rd_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_shift_flush_s : std_logic;
signal wb_rd_shift_flush_1_s : std_logic;
signal fifo_wb_rd_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_wr_s : std_logic;
signal fifo_wb_rd_addr_rd_s : std_logic;
signal fifo_wb_rd_addr_dout_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_full_s : std_logic;
signal fifo_wb_rd_addr_almost_full_s : std_logic;
signal fifo_wb_rd_addr_empty_s : std_logic;
signal fifo_wb_rd_mask_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_wr_s : std_logic;
signal fifo_wb_rd_mask_rd_s : std_logic;
signal fifo_wb_rd_mask_dout_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_full_s : std_logic;
signal fifo_wb_rd_mask_almost_full_s : std_logic;
signal fifo_wb_rd_mask_empty_s : std_logic;
signal fifo_wb_rd_mask_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal fifo_wb_rd_data_din_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_wr_s : std_logic;
signal fifo_wb_rd_data_rd_s : std_logic;
signal fifo_wb_rd_data_dout_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_dout_a : data_array;
signal fifo_wb_rd_data_full_s : std_logic;
signal fifo_wb_rd_data_almost_full_s : std_logic;
signal fifo_wb_rd_data_empty_s : std_logic;
signal fifo_wb_rd_data_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal ddr_cmd_s : std_logic; -- '1' = read, '0' = write
signal ddr_rd_data_end_s : std_logic;
signal wb_stall_s : std_logic;
signal wb_stall_d : std_logic;
signal wb_stall_dd : std_logic;
signal wb_wr_ack_s : std_logic;
signal wb_rd_ack_s : std_logic;
--------------------------------------
-- debug
--------------------------------------
--------------------------------------
-- Counter
--------------------------------------
signal wb_write_wait_cnt : unsigned(9 downto 0);
signal wb_read_wait_cnt : unsigned(9 downto 0);
begin
rst_s <= not rst_n_i;
ddr_sr_req_o <= '0';
ddr_ref_req_o <= '0';
ddr_zq_req_o <= '0';
--------------------------------------
-- Read FIFOs debug
--------------------------------------
ddr_wb_rd_mask_dout_do <= fifo_wb_rd_mask_dout_s;
ddr_rd_fifo_full_do <= fifo_wb_rd_data_full_s & fifo_wb_rd_mask_full_s;
ddr_rd_fifo_empty_do <= fifo_wb_rd_data_empty_s & fifo_wb_rd_mask_empty_s;
ddr_rd_fifo_rd_do <= fifo_wb_rd_data_rd_s & fifo_wb_rd_mask_rd_s;
ddr_rd_mask_rd_data_count_do <= fifo_wb_rd_mask_rd_data_count_s(3 downto 0);
ddr_rd_data_rd_data_count_do <= fifo_wb_rd_data_rd_data_count_s(3 downto 0);
--------------------------------------
-- QWORD swap debug
--------------------------------------
--------------------------------------
-- Wishbone ack
--------------------------------------
wb_ack_o <= wb_wr_ack_s or wb_rd_ack_s;
--------------------------------------
-- Wishbone write
--------------------------------------
p_wb_write : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_write_wait_cnt <= c_write_wait_time;
wb_wr_shift_flush_1_s <= '0';
wb_wr_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_wr_addr_shift_a(i) <= (others => '1');
wb_wr_data_shift_a(i) <= (others => '0');
wb_wr_mask_shift_a(i) <= (others => '0');
end loop;
wb_wr_ack_s <= '0';
elsif rising_edge(wb_clk_i) then
wb_wr_shift_flush_1_s <= wb_wr_shift_flush_s;
if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
wb_wr_ack_s <= '1';
wb_write_wait_cnt <= c_write_wait_time;
else
wb_wr_ack_s <= '0';
if(wb_wr_valid_shift_s /= (wb_wr_valid_shift_s'range => '0')) then
if (wb_write_wait_cnt /= 0) then
wb_write_wait_cnt <= wb_write_wait_cnt - 1;
end if;
end if;
end if;
-- Erase the data sent to the FIFO
--if(wb_wr_shift_flush_1_s = '1') then
if(wb_wr_shift_flush_s = '1') then
wb_write_wait_cnt <= c_write_wait_time;
end if;
wb_wr_addr_shift_a <= wb_wr_addr_shift_next_a;
wb_wr_data_shift_a <= wb_wr_data_shift_next_a;
wb_wr_mask_shift_a <= wb_wr_mask_shift_next_a;
wb_wr_valid_shift_s <= wb_wr_valid_shift_next_s;
end if;
end process p_wb_write;
p_wb_write_rtl : process (wb_write_wait_cnt,wb_wr_addr_shift_a,wb_wr_valid_shift_s,wb_wr_shift_flush_s,wb_wr_first_row_s,wb_wr_row_a,wb_wr_match_s,wb_wr_global_row_s)
begin
fifo_wb_wr_addr_s <= (others => '0');
wb_wr_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_wr_global_row_s(i) = '1' then
fifo_wb_wr_addr_s <= wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_wr_first_row_s <= wb_wr_row_a(i);
end if;
end loop;
if((wb_wr_global_row_s /= wb_wr_first_row_s) and (wb_wr_global_row_s /= (wb_wr_global_row_s'range => '0'))) then
wb_wr_several_row_s <= '1';
else
wb_wr_several_row_s <= '0';
end if;
end process p_wb_write_rtl;
p_wb_write_shift: process (wb_wr_shifting_s,wb_wr_addr_shift_a,wb_wr_data_shift_a,wb_wr_mask_shift_a,wb_wr_valid_shift_s,wb_addr_i,wb_data_i,wb_sel_i,wb_wr_flush_v_s)
begin
if(wb_wr_shifting_s = '1') then
wb_wr_addr_shift_next_a(c_register_shift_size-1) <= wb_addr_i(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_wr_data_shift_next_a(c_register_shift_size-1) <= wb_data_i;
wb_wr_mask_shift_next_a(c_register_shift_size-1) <= wb_sel_i;
wb_wr_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_i and wb_stb_i and wb_we_i;
for i in 1 to c_register_shift_size-1 loop
wb_wr_addr_shift_next_a(i-1) <= wb_wr_addr_shift_a(i);
wb_wr_data_shift_next_a(i-1) <= wb_wr_data_shift_a(i);
wb_wr_mask_shift_next_a(i-1) <= wb_wr_mask_shift_a(i);
if wb_wr_flush_v_s(i) = '0' then
wb_wr_valid_shift_next_s(i-1) <= wb_wr_valid_shift_s(i);
else
wb_wr_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_wr_addr_shift_next_a(i) <= wb_wr_addr_shift_a(i);
wb_wr_data_shift_next_a(i) <= wb_wr_data_shift_a(i);
wb_wr_mask_shift_next_a(i) <= wb_wr_mask_shift_a(i);
if wb_wr_flush_v_s(i) = '0' then
wb_wr_valid_shift_next_s(i) <= wb_wr_valid_shift_s(i);
else
wb_wr_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_write_shift;
wb_wr_shifting_s <= --'0' when wb_wr_several_row_s = '1' else
'1' when wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1' else
'1' when wb_write_wait_cnt = 0 else
'0';
wb_wr_global_row_s <= wb_wr_match_s and wb_wr_valid_shift_s;
wb_wr_flush_v_s <= wb_wr_first_row_s;
wb_wr_shift_flush_s <= '1' when wb_wr_flush_v_s /= (wb_wr_flush_v_s'range => '0') else
'0';
wr_mask_match_g:for i in 0 to c_register_shift_size-1 generate
wb_wr_match_s(i) <= '1' when wb_wr_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
wr_row_g:for j in 0 to c_register_shift_size-1 generate
wb_wr_row_a(i)(j) <= '1' when wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_wr_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_wr_match_s(i) = '1' and wb_wr_match_s(j) = '1' and wb_wr_valid_shift_s(i) = '1' and wb_wr_valid_shift_s(j) = '1' else
'0';
end generate;
fifo_wb_wr_mask_s((i)*8+7 downto (i)*8) <= wb_wr_mask_shift_a(i) when wb_wr_flush_v_s(i) = '1' else (others=>'0');
end generate;
-- No Little endian conversion
wb_wr_data_shift_s <= wb_wr_data_shift_a(7) &
wb_wr_data_shift_a(6) &
wb_wr_data_shift_a(5) &
wb_wr_data_shift_a(4) &
wb_wr_data_shift_a(3) &
wb_wr_data_shift_a(2) &
wb_wr_data_shift_a(1) &
wb_wr_data_shift_a(0);
fifo_wr_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_wr_din_s <= (others => '0');
fifo_wb_wr_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_wr_din_s <= fifo_wb_wr_addr_s &
fifo_wb_wr_mask_s &
wb_wr_data_shift_s;
fifo_wb_wr_wr_s <= wb_wr_shift_flush_s;
end if;
end process;
--fifo_wb_wr_din_s <= fifo_wb_wr_addr_s &
-- fifo_wb_wr_mask_s &
-- wb_wr_data_shift_s;
--fifo_wb_wr_wr_s <= wb_wr_shift_flush_s;
fifo_wb_write : fifo_315x16
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_wr_din_s,
wr_en => fifo_wb_wr_wr_s,
rd_en => fifo_wb_wr_rd_s,
dout => fifo_wb_wr_dout_s,
full => fifo_wb_wr_full_s,
empty => fifo_wb_wr_empty_s
);
--------------------------------------
-- Wishbone read
--------------------------------------
p_wb_read : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
wb_read_wait_cnt <= c_read_wait_time;
wb_rd_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_a(i) <= (others => '0');
end loop;
elsif rising_edge(wb_clk_i) then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
-- Register Shift
if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0') then
wb_read_wait_cnt <= c_read_wait_time;
else
if(wb_rd_valid_shift_s /= (wb_rd_valid_shift_s'range => '0')) then
if (wb_read_wait_cnt /= 0) then
wb_read_wait_cnt <= wb_read_wait_cnt - 1;
end if;
end if;
end if;
-- Erase the data sent to the FIFO
--if(wb_rd_shift_flush_1_s = '1') then
if(wb_rd_shift_flush_s = '1') then
wb_read_wait_cnt <= c_read_wait_time;
end if;
wb_rd_addr_shift_a <= wb_rd_addr_shift_next_a;
wb_rd_valid_shift_s <= wb_rd_valid_shift_next_s;
end if;
end process p_wb_read;
p_wb_read_rtl : process (wb_read_wait_cnt,wb_rd_addr_shift_a,wb_rd_addr_ref_a,wb_rd_valid_shift_s,wb_rd_shift_flush_s,wb_rd_global_row_s,wb_rd_addr_shift_a,wb_rd_row_a,wb_rd_first_row_s)
begin
fifo_wb_rd_addr_s <= (others => 'X');
wb_rd_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_rd_global_row_s(i) = '1' then
fifo_wb_rd_addr_s <= wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_rd_first_row_s <= wb_rd_row_a(i);
end if;
end loop;
if((wb_rd_global_row_s /= wb_rd_first_row_s) and (wb_rd_global_row_s /= (wb_rd_global_row_s'range => '0'))) then
wb_rd_several_row_s <= '1';
else
wb_rd_several_row_s <= '0';
end if;
end process p_wb_read_rtl;
wb_rd_shifting_s <= --'0' when wb_rd_several_row_s = '1' else
'1' when wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0' else
'1' when wb_read_wait_cnt = 0 else
'0';
wb_rd_global_row_s <= wb_rd_match_s and wb_rd_valid_shift_s;
wb_rd_flush_v_s <= wb_rd_first_row_s;
rd_match_g:for i in 0 to c_register_shift_size-1 generate
wb_rd_match_s(i) <= '1' when wb_rd_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
rd_row_g:for j in 0 to c_register_shift_size-1 generate
wb_rd_row_a(i)(j) <= '1' when wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_rd_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_rd_match_s(i) = '1' and wb_rd_match_s(j) = '1' and wb_rd_valid_shift_s(i) = '1' and wb_rd_valid_shift_s(j) = '1' else
'0';
end generate;
end generate;
p_wb_read_shift: process (wb_rd_shifting_s,wb_rd_addr_shift_a,wb_rd_valid_shift_s,wb_addr_i,wb_data_i,wb_sel_i,wb_rd_flush_v_s)
begin
if(wb_rd_shifting_s = '1') then
wb_rd_addr_shift_next_a(c_register_shift_size-1) <= wb_addr_i(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_rd_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_i and wb_stb_i and not wb_we_i;
for i in 1 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i-1) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i-1) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_read_shift;
p_wb_read_data : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= (others => '0');
wb_rd_ack_shift_s(i) <= '0';
end loop;
elsif rising_edge(wb_clk_i) then
if(fifo_wb_rd_data_rd_s = '1') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= fifo_wb_rd_data_dout_s(63+(i*64) downto 0+(i*64));
wb_rd_ack_shift_s(i) <= fifo_wb_rd_mask_dout_s(i); -- The data are reversed
end loop;
else
wb_rd_data_shift_a(c_register_shift_size-1) <= (others => '0');
wb_rd_ack_shift_s(c_register_shift_size-1) <= '0';
for i in 0 to c_register_shift_size-2 loop
wb_rd_data_shift_a(i) <= wb_rd_data_shift_a(i+1);
wb_rd_ack_shift_s(i) <= wb_rd_ack_shift_s(i+1);
end loop;
end if;
end if;
end process p_wb_read_data;
fifo_rd_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_rd_addr_din_s <= (others => '0');
fifo_wb_rd_mask_din_s <= (others => '0');
fifo_wb_rd_addr_wr_s <= '0';
fifo_wb_rd_mask_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_addr_din_s <= fifo_wb_rd_addr_s;
fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
end if;
end process;
--fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
--fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
--fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
fifo_wb_rd_data_rd_s <= '1' when wb_rd_ack_shift_s(c_register_shift_size-1 downto 1) = "0000000" and fifo_wb_rd_mask_empty_s = '0' and fifo_wb_rd_data_empty_s = '0' else
'0';
fifo_wb_rd_mask_rd_s <= fifo_wb_rd_data_rd_s;
wb_data_o <= wb_rd_data_shift_a(0);
wb_rd_ack_s <= wb_rd_ack_shift_s(0);
wb_rd_shift_flush_s <= '1' when wb_rd_flush_v_s /= (wb_rd_flush_v_s'range => '0') else
'0';
fifo_wb_read_addr : fifo_27x16
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_rd_addr_din_s,
wr_en => fifo_wb_rd_addr_wr_s,
rd_en => fifo_wb_rd_addr_rd_s,
dout => fifo_wb_rd_addr_dout_s,
full => fifo_wb_rd_addr_full_s,
almost_full => fifo_wb_rd_addr_almost_full_s,
empty => fifo_wb_rd_addr_empty_s
);
fifo_wb_read_mask : fifo_4x16
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_mask_din_s,
wr_en => fifo_wb_rd_mask_wr_s,
rd_en => fifo_wb_rd_mask_rd_s,
dout(7 downto 0) => fifo_wb_rd_mask_dout_s,
dout(36 downto 8) => ddr_wb_rd_mask_addr_dout_do,
full => fifo_wb_rd_mask_full_s,
almost_full => fifo_wb_rd_mask_almost_full_s,
empty => fifo_wb_rd_mask_empty_s,
rd_data_count => fifo_wb_rd_mask_rd_data_count_s
);
fifo_wb_read_data : fifo_256x16
PORT MAP (
rst => rst_s,
wr_clk => ddr_ui_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_data_din_s,
wr_en => fifo_wb_rd_data_wr_s,
rd_en => fifo_wb_rd_data_rd_s,
dout => fifo_wb_rd_data_dout_s,
full => fifo_wb_rd_data_full_s,
almost_full => fifo_wb_rd_data_almost_full_s,
empty => fifo_wb_rd_data_empty_s,
rd_data_count => fifo_wb_rd_data_rd_data_count_s
);
--------------------------------------
-- DDR CMD
--------------------------------------
p_ddr_cmd : process (ddr_ui_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ddr_cmd_en_o <= '0';
ddr_cmd_o <= "000";
elsif rising_edge(ddr_ui_clk_i) then
if(fifo_wb_wr_rd_s = '1') then
ddr_cmd_en_o <= '1';
ddr_cmd_o <= "000";
ddr_cmd_s <= '0';
elsif (fifo_wb_rd_addr_rd_s = '1') then
ddr_cmd_en_o <= '1';
ddr_cmd_o <= "001";
ddr_cmd_s <= '1';
elsif (ddr_rdy_i = '1') then
ddr_cmd_en_o <= '0';
end if;
end if;
end process p_ddr_cmd;
ddr_addr_o <= fifo_wb_wr_dout_s(604 downto 576) when ddr_cmd_s = '0' else
fifo_wb_rd_addr_dout_s;
--------------------------------------
-- DDR Data out
--------------------------------------
p_ddr_data_out : process (ddr_ui_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ddr_wdf_wren_o <= '0';
ddr_wdf_end_o <= '0';
elsif rising_edge(ddr_ui_clk_i) then
if (fifo_wb_wr_rd_s = '1') then
ddr_wdf_wren_o <= '1';
ddr_wdf_end_o <= '1';
elsif (ddr_wdf_rdy_i = '1') then
ddr_wdf_wren_o <= '0';
ddr_wdf_end_o <= '0';
end if;
end if;
end process p_ddr_data_out;
ddr_wdf_data_o <= fifo_wb_wr_dout_s(511 downto 0);
ddr_wdf_mask_o <= not fifo_wb_wr_dout_s(575 downto 512);
--------------------------------------
-- DDR Data in
--------------------------------------
fifo_wb_wr_rd_s <= ddr_wdf_rdy_i and ddr_rdy_i and not fifo_wb_wr_empty_s;
fifo_wb_rd_addr_rd_s <= ddr_rdy_i and (not fifo_wb_rd_addr_empty_s) and (not fifo_wb_rd_data_almost_full_s); -- and (not fifo_wb_rd_mask_full_s);
fifo_wb_rd_data_wr_s <= ddr_rd_data_valid_i and ddr_rd_data_end_i;
fifo_wb_rd_data_din_s <= ddr_rd_data_i;
--------------------------------------
-- Stall proc
--------------------------------------
wb_stall_s <= fifo_wb_wr_full_s or fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s or wb_wr_several_row_s; --or (not ddr_wdf_rdy_i) or (not ddr_rdy_i);
wb_stall_o <= wb_stall_s;
end architecture behavioral;
|
gpl-3.0
|
29a4b2a2eb6c6a1b8a535e862c854b1a
| 0.472891 | 3.086767 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_lut.vhd
| 1 | 7,934 |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Decoder for decoding 8b/10b encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY decode_8b10b;
-----------------------------------------------------------------------------
-- Entity Declaration
-----------------------------------------------------------------------------
ENTITY decode_8b10b_lut IS
GENERIC (
C_HAS_BPORTS : INTEGER := 0;
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_CODE_ERR_B : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_ERR_B : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_IN_B : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_ND_B : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_SYM_DISP_B : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_RUN_DISP_B : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_DOUT_B : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_KOUT_B : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0;
C_SINIT_RUN_DISP_B : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_lut;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_lut IS
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
----Instantiate the first decoder (A decoder)--------------------------------
deca : ENTITY decode_8b10b.decode_8b10b_lut_base
GENERIC MAP (
C_HAS_CODE_ERR => C_HAS_CODE_ERR,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_ND => C_HAS_ND,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_KOUT => C_SINIT_KOUT,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP
)
PORT MAP (
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
KOUT => KOUT,
CE => CE,
DISP_IN => DISP_IN,
SINIT => SINIT,
CODE_ERR => CODE_ERR,
DISP_ERR => DISP_ERR,
ND => ND,
RUN_DISP => RUN_DISP,
SYM_DISP => SYM_DISP
);
gdecb : IF (C_HAS_BPORTS=1) GENERATE
----Instantiate second decoder (B decoder, only if bports are present)------
decb : ENTITY decode_8b10b.decode_8b10b_lut_base
GENERIC MAP (
C_HAS_CODE_ERR => C_HAS_CODE_ERR_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR_B,
C_HAS_DISP_IN => C_HAS_DISP_IN_B,
C_HAS_ND => C_HAS_ND_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP_B,
C_SINIT_DOUT => C_SINIT_DOUT_B,
C_SINIT_KOUT => C_SINIT_KOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP_B
)
PORT MAP (
CLK => CLK_B,
DIN => DIN_B,
DOUT => DOUT_B,
KOUT => KOUT_B,
CE => CE_B,
DISP_IN => DISP_IN_B,
SINIT => SINIT_B,
CODE_ERR => CODE_ERR_B,
DISP_ERR => DISP_ERR_B,
ND => ND_B,
RUN_DISP => RUN_DISP_B,
SYM_DISP => SYM_DISP_B
);
END GENERATE gdecb;
END xilinx ;
|
gpl-3.0
|
001d9b8673602ce2f93ce3ba24bd0796
| 0.451349 | 4.041773 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Test Files/testbench.vhd
| 1 | 3,562 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- USE ieee.numeric_std.ALL;
use std.textio.all;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
entity testbench is
generic(
width : natural :=16
);
port(
output : out std_logic_vector(width-1 downto 0)
);
end testbench;
architecture arch_testbench of testbench is
signal clock : std_logic := '0';
signal reset_signal : std_logic;
signal endoffile : std_logic := '0';
signal dataread : real ;
signal datawrite : real ;
signal linenumber : natural;
signal input_signal : std_logic_vector(width-1 downto 0);
signal output_signal: std_logic_vector(width-1 downto 0);
signal output_signal1: SIGNED(width-1 downto 0);
-- COMPONENT StructuralDecimator is
-- Port ( input: in std_logic_vector(11 downto 0);
-- output: out std_logic_vector(15 downto 0);
-- clk :in std_logic;
-- reset:in std_logic
-- );
-- END COMPONENT StructuralDecimator;
-- COMPONENT EffectEcho is
-- generic (
-- wordLength : natural := 16;
-- constantsWordLength : natural := 16
-- );
-- port (
-- input : in std_logic_vector(wordLength-1 downto 0);
-- output : out std_logic_vector(wordLength-1 downto 0);
--
-- clk : in std_logic;
-- reset : in std_logic
-- );
--end COMPONENT ;
begin
-- decimator_comp: COMPONENT StructuralDecimator
-- PORT MAP(clk=>clock,
-- reset=>reset_signal,
-- input=>input_signal,
-- output=>output_signal
-- );
-- EffectEcho_comp: COMPONENT EffectEcho
-- PORT MAP(clk=>clock,
-- reset=>reset_signal,
-- input=>input_signal,
-- output=>output_signal
-- );
test_comp: entity work.Generic_Equalizer_Low_Pass
port map (input => input_signal,
output => output_signal,
clk=> clock,
reset => reset_signal
);
reset_signal<='0',
'1' AFTER 15 ns,
'0' AFTER 25 ns;
clk_proc:process
begin
wait for 25 us;
clock<=NOT(clock);
end process clk_proc;
reading:process
file infile : text is in "Input.txt"; --declare input file
variable inline : line; --line number declaration
variable dataread1 : real;
begin
wait until clock = '1' and clock'event;
if (not endfile(infile)) then --checking the "END OF FILE" is not reached.
readline(infile, inline);
read(inline, dataread1);
dataread <=dataread1; --put the value available in variable in a signal.
else
endoffile <='1'; --set signal to tell end of file read file is reached.
end if;
end process reading;
input_signal <= STD_LOGIC_VECTOR(CONV_SIGNED(INTEGER(dataread*65536.0),width));-- 12 =width
output_signal1 <= SIGNED(output_signal(15 downto 0));
--output_signal1 <= SIGNED(input_signal(15 downto 0));
datawrite <= REAL(CONV_INTEGER(output_signal1))/65536.0 ;
writing:process
file outfile : text is out "Output_Low.txt"; --declare output file
variable outline : line; --line number declaration
begin
wait until clock = '0' and clock'event;
if(endoffile='0') then write(outline, datawrite, left, 16, 12);--write(linenumber,value(real type),justified(side),field(width),digits(natural));
writeline(outfile, outline);
linenumber <= linenumber + 1;
else
null;
end if;
end process writing;
end arch_testbench;
|
mit
|
31b8415edeba932c6cccde6a857ed016
| 0.604716 | 3.558442 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
ethernet_receive.vhd
| 1 | 5,661 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ethernet_receive is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
PhyRxd : in STD_LOGIC_VECTOR(3 downto 0);
PhyRxDv : in STD_LOGIC;
PhyRxClk : in STD_LOGIC;
Led : OUT std_logic_vector(4 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0);
busPkt : out STD_LOGIC;
busDesc : out STD_LOGIC
);
end ethernet_receive;
architecture Behavioral of ethernet_receive is
signal len_fifo_din, len_fifo_dout : STD_LOGIC_VECTOR(10 DOWNTO 0);
signal len_fifo_we, len_fifo_re, len_fifo_full, len_fifo_empty : STD_LOGIC;
COMPONENT packet_len_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal fifo_re, fifo_full, fifo_empty, fifo_underflow, fifo_valid : STD_LOGIC;
signal fifo_dout : STD_LOGIC_VECTOR(7 downto 0);
COMPONENT async_fifo_rx
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC
);
END COMPONENT;
-- Fifo has nibbles swapped
signal pktData, pktDataX : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal oldValid : STD_LOGIC;
type ro_state_t is (RO_IDLE,
RO_READ_LEN, RO_WRITE_DESC_0, RO_WRITE_DESC_1,
RO_READ_PKT);
signal ro_state : ro_state_t := RO_IDLE;
signal NEXT_ro_state : ro_state_t;
signal ro_len : STD_LOGIC_VECTOR(10 DOWNTO 0);
signal ro_cnt, NEXT_ro_cnt : STD_LOGIC_VECTOR(10 DOWNTO 0);
begin
underflowTest : process (clk)
variable prev : STD_LOGIC := '0';
begin
if RISING_EDGE(clk) then
prev := prev or fifo_underflow;
led(4) <= prev;
if rst = '1' then
prev := '0';
end if;
end if;
end process;
packet_lens : packet_len_fifo
PORT MAP (
rst => rst,
rd_clk => clk,
rd_en => len_fifo_re,
dout => len_fifo_dout,
empty => len_fifo_empty,
wr_clk => PhyRxClk,
wr_en => len_fifo_we,
din => len_fifo_din,
full => len_fifo_full
);
Led(2) <= len_fifo_full;
Led(3) <= not len_fifo_empty;
-- Processes in Phy clock domain that count frame lengths
oldValid <= PhyRxDv when RISING_EDGE(PhyRxClk);
eth_count_len: process (PhyRxClk)
variable counter : STD_LOGIC_VECTOR(11 downto 0);
begin
if RISING_EDGE(PhyRxClk) then
-- No need for reset here
-- Phy reset will cause Dv to drop low
-- FIFO will be in reset so it will not take the length in
len_fifo_we <= '0';
-- Add to fifo
if oldValid = '1' and PhyRxDv = '0' then
len_fifo_we <= '1';
end if;
-- Count Dv = '1' cycles
if PhyRxDv = '1' then
counter := counter + 1;
end if;
len_fifo_din <= counter(11 downto 1);
if PhyRxDv = '0' then
counter := (others => '0');
end if;
end if;
end process;
xclk_fifo : async_fifo_rx
PORT MAP (
rst => rst,
rd_clk => clk,
rd_en => fifo_re,
dout => fifo_dout,
empty => fifo_empty,
valid => fifo_valid,
underflow => fifo_underflow,
wr_clk => PhyRxClk,
din => PhyRxd,
wr_en => PhyRxDv,
full => fifo_full
);
busPkt <= fifo_valid;
pktDataX <= fifo_dout;
pktData <= pktDataX(3 downto 0) & pktDataX(7 downto 4);
Led(0) <= fifo_full;
Led(1) <= not fifo_empty;
fsm : process (ro_state, ro_cnt, ro_len, pktData, len_fifo_empty, NEXT_ro_cnt)
begin
NEXT_ro_state <= ro_state;
NEXT_ro_cnt <= ro_cnt + 1;
len_fifo_re <= '0';
fifo_re <= '0';
busDesc <= '0';
data <= pktData;
case ro_state is
when RO_IDLE =>
if len_fifo_empty = '0' then
NEXT_ro_state <= RO_READ_LEN;
len_fifo_re <= '1';
end if;
when RO_READ_LEN =>
NEXT_ro_state <= RO_WRITE_DESC_0;
when RO_WRITE_DESC_0 =>
NEXT_ro_state <= RO_WRITE_DESC_1;
busDesc <= '1';
data <= "00000" & ro_len(10 downto 8);
when RO_WRITE_DESC_1 =>
NEXT_ro_state <= RO_READ_PKT;
NEXT_ro_cnt <= ( others => '0' );
busDesc <= '1';
data <= ro_len(7 downto 0);
when RO_READ_PKT =>
fifo_re <= '1';
if NEXT_ro_cnt = ro_len then
NEXT_ro_state <= RO_IDLE;
end if;
end case;
end process;
NEXT_fsm : process (clk)
begin
if RISING_EDGE(clk) then
ro_state <= NEXT_ro_state;
ro_cnt <= NEXT_ro_cnt;
if ro_state = RO_READ_LEN then
ro_len <= len_fifo_dout;
end if;
if rst = '1' then
ro_state <= RO_IDLE;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
498f2dad8b94dc96e31bd51bac0013ac
| 0.60749 | 2.90755 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/tx-core/wb_tx_core.vhd
| 1 | 12,400 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Serial Port
-- # Outputs are synchronous to clk_i
-- ####################################
-- # Adress Map:
-- # Adr[8:4]: channel number 0 to 31
-- # Adr[3:0]:
-- # 0x0 - FiFo (WO) (Write to enabled channels)
-- # 0x1 - CMD Enable (RW)
-- # 0x2 - CMD Empty (RO)
-- # 0x3 - Trigger Enable (RW)
-- # 0x4 - Trigger Done (RO)
-- # 0x5 - Trigger Conf (RW) :
-- # 0 = External
-- # 1 = Internal Time
-- # 2 = Internal Count
-- # 0x6 - Trigger Frequency (RW)
-- # 0x7 - Trigger Time_L (RW)
-- # 0x8 - Trigger Time_H (RW)
-- # 0x9 - Trigger Count (RW)
-- # 0xA - Trigger Word Length (RW)
-- # 0xB - Trigger Word [31:0] (RW)
-- # 0xC - Trigger Word [63:32] (RW)
-- # 0xD - Trigger Word [95:64] (RW)
-- # 0xE - Trigger Word [127:96] (RW)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_tx_core is
generic (
g_NUM_TX : integer range 1 to 32 := 1
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- Sync
ext_trig_i : in std_logic
);
end wb_tx_core;
architecture behavioral of wb_tx_core is
component tx_channel
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data In
wb_dat_i : in std_logic_vector(31 downto 0);
wb_wr_en_i : in std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic;
tx_enable_i : in std_logic;
-- Status
tx_underrun_o : out std_logic;
tx_overrun_o : out std_logic;
tx_almost_full_o : out std_logic;
tx_empty_o : out std_logic
);
end component;
component trigger_unit
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Serial Trigger Out
trig_o : out std_logic;
trig_pulse_o : out std_logic;
-- Trigger In (async)
ext_trig_i : in std_logic;
-- Config
trig_word_i : in std_logic_vector(127 downto 0); -- Trigger command
trig_word_length_i : in std_logic_vector(31 downto 0); -- Trigger command length
trig_freq_i : in std_logic_vector(31 downto 0); -- Number of clock cycles between triggers
trig_time_i : in std_logic_vector(63 downto 0); -- Clock cycles
trig_count_i : in std_logic_vector(31 downto 0); -- Fixed number of triggers
trig_conf_i : in std_logic_vector(3 downto 0); -- Internal, external, pseudo random,
trig_en_i : in std_logic;
trig_abort_i : in std_logic;
trig_done_o : out std_logic
);
end component;
-- Signals
signal tx_data_cmd : std_logic_vector(g_NUM_TX-1 downto 0);
signal tx_data_trig : std_logic;
signal tx_trig_pulse : std_logic;
-- Registers
signal tx_enable : std_logic_vector(31 downto 0) := (others => '0');
signal tx_underrun : std_logic_vector(31 downto 0) := (others => '0');
signal tx_overrun : std_logic_vector(31 downto 0) := (others => '0');
signal tx_almost_full : std_logic_vector(31 downto 0) := (others => '0');
signal tx_empty : std_logic_vector(31 downto 0) := (others => '0');
-- Trigger command
signal trig_freq : std_logic_vector(31 downto 0); -- Number of clock cycles between triggers
signal trig_time : std_logic_vector(63 downto 0); -- Clock cycles
signal trig_time_l : std_logic_vector(31 downto 0);
signal trig_time_l_d : std_logic_vector(31 downto 0);
signal trig_time_h : std_logic_vector(31 downto 0);
signal trig_time_h_d : std_logic_vector(31 downto 0);
signal trig_count : std_logic_vector(31 downto 0); -- Fixed number of triggers
signal trig_conf : std_logic_vector(3 downto 0); -- Internal, external, pseudo random,
signal trig_en : std_logic;
signal trig_done : std_logic;
signal trig_word_length : std_logic_vector(31 downto 0);
signal trig_word : std_logic_vector(127 downto 0);
-- Trig input freq counter
signal ext_trig_t1 : std_logic;
signal ext_trig_t2 : std_logic;
signal ext_trig_t3 : std_logic;
signal trig_in_freq_cnt : unsigned(31 downto 0);
signal trig_in_freq : std_logic_vector(31 downto 0);
signal per_second : std_logic;
signal per_second_cnt : unsigned(31 downto 0);
constant ticks_per_second : integer := 40000000; -- 40 MHz clock rate
signal trig_abort : std_logic;
signal wb_wr_en : std_logic_vector(31 downto 0) := (others => '0');
signal wb_dat_t : std_logic_vector(31 downto 0);
signal channel : integer range 0 to 31;
begin
channel <= TO_INTEGER(unsigned(wb_adr_i(8 downto 4)));
wb_stall_o <= '1' when (tx_almost_full /= x"00000000") else '0';
wb_proc: process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_wr_en <= (others => '0');
tx_enable <= (others => '0');
wb_dat_t <= (others => '0');
trig_en <= '0';
trig_abort <= '0';
tx_enable <= (others => '0');
trig_conf <= (others => '0');
trig_time_h <= (others => '0');
trig_time_h_d <= (others => '0');
trig_time_h <= (others => '0');
trig_time_l_d <= (others => '0');
trig_count <= (others => '0');
trig_word <= (others => '0');
trig_abort <= '0';
elsif rising_edge(wb_clk_i) then
wb_wr_en <= (others => '0');
wb_ack_o <= '0';
trig_time_h_d <= trig_time_h;
trig_time_l_d <= trig_time_l;
trig_time <= trig_time_h_d & trig_time_l_d; -- delay for more flexible routing
trig_abort <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '1') then
case (wb_adr_i(3 downto 0)) is
when x"0" => -- Write to fifo
wb_wr_en <= tx_enable;
wb_ack_o <= '1';
wb_dat_t <= wb_dat_i;
when x"1" => -- Set enable mask
tx_enable <= wb_dat_i;
wb_ack_o <= '1';
when x"3" => -- Set trigger enable
trig_en <= wb_dat_i(0);
wb_ack_o <= '1';
when x"5" => -- Set trigger conf
trig_conf <= wb_dat_i(3 downto 0);
wb_ack_o <= '1';
when x"6" => -- Set trigger frequency
trig_freq <= wb_dat_i;
wb_ack_o <= '1';
when x"7" => -- Set trigger time low
trig_time_l(31 downto 0) <= wb_dat_i;
wb_ack_o <= '1';
when x"8" => -- Set trigger time high
trig_time_h(31 downto 0) <= wb_dat_i;
wb_ack_o <= '1';
when x"9" => -- Set trigger count
trig_count <= wb_dat_i;
wb_ack_o <= '1';
when x"A" => -- Set trigger word length (bits)
trig_word_length <= wb_dat_i;
wb_ack_o <= '1';
when x"B" => -- Set trigger word [31:0]
trig_word(31 downto 0) <= wb_dat_i;
wb_ack_o <= '1';
when x"C" => -- Set trigger word [63:32]
trig_word(63 downto 32) <= wb_dat_i;
wb_ack_o <= '1';
when x"D" => -- Set trigger word [95:64]
trig_word(95 downto 64) <= wb_dat_i;
wb_ack_o <= '1';
when x"E" => -- Set trigger word [127:96]
trig_word(127 downto 96) <= wb_dat_i;
wb_ack_o <= '1';
when x"F" => -- Toggle trigger abort
trig_abort <= wb_dat_i(0);
wb_ack_o <= '1';
when others =>
wb_ack_o <= '1';
end case;
else
case (wb_adr_i(3 downto 0)) is
when x"0" => -- Read enable mask
wb_dat_o <= tx_enable;
wb_ack_o <= '1';
when x"2" => -- Read empty stat
wb_dat_o <= tx_empty;
wb_ack_o <= '1';
when x"3" => -- Read trigger enable
wb_dat_o(0) <= trig_en;
wb_dat_o(31 downto 1) <= (others => '0');
wb_ack_o <= '1';
when x"4" => -- Read trigger done
wb_dat_o(0) <= trig_done;
wb_dat_o(31 downto 1) <= (others => '0');
wb_ack_o <= '1';
when x"5" => -- Read trigger conf
wb_dat_o(3 downto 0) <= trig_conf;
wb_dat_o(31 downto 4) <= (others => '0');
wb_ack_o <= '1';
when x"6" => -- Read trigger freq
wb_dat_o <= trig_freq;
wb_ack_o <= '1';
when x"7" => -- Read trigger time low
wb_dat_o <= trig_time(31 downto 0);
wb_ack_o <= '1';
when x"8" => -- Read trigger time high
wb_dat_o <= trig_time(63 downto 32);
wb_ack_o <= '1';
when x"9" => -- Read trigger count
wb_dat_o <= trig_count;
wb_ack_o <= '1';
when x"A" => -- Set trigger word length (bits)
wb_dat_o <= trig_word_length;
wb_ack_o <= '1';
when x"B" => -- Set trigger word [31:0]
wb_dat_o <= trig_word(31 downto 0);
wb_ack_o <= '1';
when x"C" => -- Set trigger word [63:32]
wb_dat_o <= trig_word(63 downto 32);
wb_ack_o <= '1';
when x"D" => -- Set trigger word [95:64]
wb_dat_o <= trig_word(95 downto 64);
wb_ack_o <= '1';
when x"E" => -- Set trigger word [127:96]
wb_dat_o <= trig_word(127 downto 96);
wb_ack_o <= '1';
when x"F" => -- Trigger in frequency
wb_dat_o <= trig_in_freq;
wb_ack_o <= '1';
when others =>
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end case;
end if;
end if;
end if;
end process wb_proc;
tx_channels: for I in 0 to g_NUM_TX-1 generate
begin
cmp_tx_channel: tx_channel PORT MAP (
-- Sys connect
wb_clk_i => wb_clk_i,
rst_n_i => rst_n_i,
-- Data In
wb_dat_i => wb_dat_t,
wb_wr_en_i => wb_wr_en(I),
-- TX
tx_clk_i => tx_clk_i,
tx_data_o => tx_data_cmd(I),
tx_enable_i => tx_enable(I),
-- Status
tx_underrun_o => tx_underrun(I),
tx_overrun_o => tx_overrun(I),
tx_almost_full_o => tx_almost_full(I),
tx_empty_o => tx_empty(I)
);
tx_mux : process(tx_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
tx_data_o(I) <= '0';
elsif rising_edge(tx_clk_i) then
if (tx_enable(I) = '1' and trig_en = '1') then
tx_data_o(I) <= tx_data_trig;
else
tx_data_o(I) <= tx_data_cmd(I);
end if;
end if;
end process;
end generate tx_channels;
trig_pulse_o <= tx_trig_pulse;
cmp_trig_unit : trigger_unit PORT MAP (
clk_i => tx_clk_i,
rst_n_i => rst_n_i,
-- Serial Trigger Out
trig_o => tx_data_trig,
trig_pulse_o=> tx_trig_pulse,
-- Trigger In (async)
ext_trig_i => ext_trig_i,
-- Config
trig_word_i => trig_word,
trig_word_length_i => trig_word_length,
trig_freq_i => trig_freq,
trig_time_i => trig_time,
trig_count_i => trig_count,
trig_conf_i => trig_conf,
trig_en_i => trig_en,
trig_abort_i => trig_abort,
trig_done_o => trig_done
);
-- Create 1 tick per second for counter
per_sec_proc : process(tx_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
per_second <= '0';
per_second_cnt <= (others => '0');
elsif rising_edge(tx_clk_i) then
if (per_second_cnt = ticks_per_second) then
per_second <= '1';
per_second_cnt <= (others => '0');
else
per_second <= '0';
per_second_cnt <= per_second_cnt + 1;
end if;
end if;
end process per_sec_proc;
-- Count incoming trig frequency
trig_in_freq_proc : process(tx_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_in_freq_cnt <= (others => '0');
ext_trig_t1 <= '0';
ext_trig_t2 <= '0';
ext_trig_t3 <= '0';
elsif rising_edge(tx_clk_i) then
ext_trig_t1 <= ext_trig_i;
ext_trig_t2 <= ext_trig_t1;
ext_trig_t3 <= ext_trig_t2;
if (trig_done = '1') then -- reset when trigger module is done
trig_in_freq_cnt <= (others => '0');
else
if (ext_trig_t2 = '1' and ext_trig_t3 = '0') then -- positive edge
trig_in_freq_cnt <= trig_in_freq_cnt + 1;
end if;
trig_in_freq <= std_logic_vector(trig_in_freq_cnt);
end if;
end if;
end process trig_in_freq_proc;
end behavioral;
|
gpl-3.0
|
fa0524ef723d628ef14bd51bf5d30ffa
| 0.536935 | 2.726473 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Utilities/Decimator_tb.vhd
| 1 | 2,798 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:40:27 02/07/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/Source/Utilities/Decimator_tb.vhd
-- Project Name: SoundboxProject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Decimator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Decimator_tb IS
END Decimator_tb;
ARCHITECTURE behavior OF Decimator_tb IS
-- Component Declaration for the Unit Under Test (UUT)
--Inputs
signal input : std_logic_vector(7 downto 0) := (others => '0');
signal reset : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.Decimator
generic map(
divider => 4
)
port map(
input => input,
output => output,
reset => reset,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
input <= (others => '0');
wait for clk_period*10;
input <= (others => '1');
wait for clk_period*10;
input <= (others => '0');
wait for clk_period;
input <= x"F1";
wait for clk_period;
input <= x"F2";
wait for clk_period;
input <= x"F3";
wait for clk_period;
input <= x"F4";
wait for clk_period;
input <= x"F5";
wait for clk_period;
input <= x"F6";
wait for clk_period;
input <= x"F7";
wait for clk_period;
input <= x"F8";
wait for clk_period;
input <= x"F9";
-- insert stimulus here
wait;
end process;
END;
|
mit
|
f9ab711ebeb268969decaca5b6ce424e
| 0.571837 | 3.902371 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/app_package.vhd
| 1 | 36,560 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/11/2017 10:26:23 AM
-- Design Name:
-- Module Name: app_package - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package app_pkg is
component simple_counter is
Port (
enable_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0);
gray_count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
component m_clk_sync is
Generic (
data_width_g : integer := 29
);
Port ( rst0_i : in STD_LOGIC;
rst1_i : in STD_LOGIC;
clk0_i : in STD_LOGIC;
clk1_i : in STD_LOGIC;
data0_i : in STD_LOGIC_VECTOR (data_width_g-1 downto 0);
data1_o : out STD_LOGIC_VECTOR (data_width_g-1 downto 0));
end component;
Component p2l_decoder is
Port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
-- From Slave AXI-Stream
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR (64 - 1 downto 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR (64/8 - 1 downto 0);
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR (21 downto 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
-- To the wishbone master
pd_wbm_address_o : out STD_LOGIC_VECTOR(63 downto 0);
pd_wbm_data_o : out STD_LOGIC_VECTOR(31 downto 0);
pd_wbm_valid_o : out std_logic;
pd_wbm_hdr_rid_o : out std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_tag_o : out std_logic_vector(7 downto 0);
pd_wbm_target_mrd_o : out std_logic; -- Target memory read
pd_wbm_target_mwr_o : out std_logic; -- Target memory write
wbm_pd_ready_i : in std_logic;
-- to L2P DMA
pd_pdm_data_valid_o : out std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_o : out std_logic_vector(1 downto 0);
pd_pdm_data_last_o : out std_logic; -- Indicates end of the packet
pd_pdm_keep_o : out std_logic_vector(7 downto 0);
pd_pdm_data_o : out std_logic_vector(63 downto 0); -- Data
--debug outputs
states_do : out STD_LOGIC_VECTOR(3 downto 0);
pd_op_o : out STD_LOGIC_VECTOR(2 downto 0);
pd_header_type_o : out STD_LOGIC;
pd_payload_length_o : out STD_LOGIC_VECTOR(9 downto 0)
);
end component;
component wbmaster32 is
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i : in std_logic; -- Header strobe
--pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_rid_i : in std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_cid_i : in std_logic_vector(15 downto 0); -- Completer ID
pd_wbm_hdr_tag_i : in std_logic_vector(7 downto 0); -- Completion ID
pd_wbm_target_mrd_i : in std_logic; -- Target memory read
pd_wbm_target_mwr_i : in std_logic; -- Target memory write
--
-- Address
pd_wbm_addr_start_i : in std_logic; -- Address strobe
pd_wbm_addr_i : in std_logic_vector(31 downto 0); -- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i : in std_logic; -- Indicates Data is valid
--pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i : in std_logic_vector(31 downto 0); -- Data
--pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
wbm_arb_tdata_o : out STD_LOGIC_VECTOR (64 - 1 downto 0);
wbm_arb_tkeep_o : out STD_LOGIC_VECTOR (64/8 - 1 downto 0);
--wbm_arb_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
wbm_arb_tlast_o : out STD_LOGIC;
wbm_arb_tvalid_o : out STD_LOGIC;
wbm_arb_tready_i : in STD_LOGIC;
wbm_arb_req_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic; -- Stall
wb_err_i : in std_logic; -- Error
wb_rty_i : in std_logic; -- Retry
wb_int_i : in std_logic -- Interrupt
);
end component;
component dma_controller is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_o : out std_logic_vector(31 downto 0);
dma_ctrl_len_o : out std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_o : out std_logic; -- To the L2P DMA master
dma_ctrl_start_p2l_o : out std_logic; -- To the P2L DMA master
dma_ctrl_start_next_o : out std_logic; -- To the P2L DMA master
dma_ctrl_byte_swap_o : out std_logic_vector(1 downto 0);
dma_ctrl_abort_o : out std_logic;
dma_ctrl_done_i : in std_logic;
dma_ctrl_error_i : in std_logic;
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i : in std_logic_vector(31 downto 0);
next_item_host_addr_h_i : in std_logic_vector(31 downto 0);
next_item_host_addr_l_i : in std_logic_vector(31 downto 0);
next_item_len_i : in std_logic_vector(31 downto 0);
next_item_next_l_i : in std_logic_vector(31 downto 0);
next_item_next_h_i : in std_logic_vector(31 downto 0);
next_item_attrib_i : in std_logic_vector(31 downto 0);
next_item_valid_i : in std_logic;
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i : in std_logic; -- Bus clock
wb_adr_i : in std_logic_vector(3 downto 0); -- Adress
wb_dat_o : out std_logic_vector(31 downto 0); -- Data in
wb_dat_i : in std_logic_vector(31 downto 0); -- Data out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wb_cyc_i : in std_logic; -- Read or write cycle
wb_stb_i : in std_logic; -- Read or write strobe
wb_we_i : in std_logic; -- Write
wb_ack_o : out std_logic; -- Acknowledge
---------------------------------------------------------
-- debug outputs
dma_ctrl_current_state_do : out std_logic_vector (2 downto 0);
dma_ctrl_do : out std_logic_vector(31 downto 0);
dma_stat_do : out std_logic_vector(31 downto 0);
dma_attrib_do : out std_logic_vector(31 downto 0)
);
end component;
component bram_wbs32 is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 32
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(5-1 downto 0);
wb_dat_i : in std_logic_vector(32-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(32-1 downto 0);
wb_ack_o : out std_logic
);
end component;
component k_bram is
generic (
constant ADDR_WIDTH : integer := 9+4;
constant DATA_WIDTH : integer := 64
);
Port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(9+4-1 downto 0);
wb_dat_i : in std_logic_vector(64-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(64-1 downto 0);
wb_ack_o : out std_logic
);
end component;
component l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end component;
component p2l_dma_master is
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_p2l_i : in std_logic;
dma_ctrl_start_next_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_master_cpld_i : in std_logic; -- Master read completion with data
pd_pdm_master_cpln_i : in std_logic; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_i: in std_logic_vector(1 downto 0);
pd_pdm_data_last_i : in std_logic; -- Indicates end of the packet
pd_pdm_data_i : in std_logic_vector(63 downto 0); -- Data
pd_pdm_be_i : in std_logic_vector(7 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o : out std_logic; -- Read completion signals
pdm_arb_tlast_o : out std_logic; -- Toward the arbiter
pdm_arb_tdata_o : out std_logic_vector(63 downto 0);
pdm_arb_tkeep_o : out std_logic_vector(7 downto 0);
pdm_arb_req_o : out std_logic;
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(63 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(63 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(7 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o : out std_logic_vector(31 downto 0);
next_item_host_addr_h_o : out std_logic_vector(31 downto 0);
next_item_host_addr_l_o : out std_logic_vector(31 downto 0);
next_item_len_o : out std_logic_vector(31 downto 0);
next_item_next_l_o : out std_logic_vector(31 downto 0);
next_item_next_h_o : out std_logic_vector(31 downto 0);
next_item_attrib_o : out std_logic_vector(31 downto 0);
next_item_valid_o : out std_logic
);
end component;
component l2p_dma_master is
generic (
g_BYTE_SWAP : boolean := false;
axis_data_width_c : integer := 64;
wb_address_width_c : integer := 64;
wb_data_width_c : integer := 64
);
port (
-- GN4124 core clk and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
-- From the DMA controller
dma_ctrl_target_addr_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_len_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_start_l2p_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
-- To the arbiter (L2P data)
ldm_arb_tvalid_o : out std_logic;
--ldm_arb_dframe_o : out std_logic;
ldm_arb_tlast_o : out std_logic;
ldm_arb_tdata_o : out std_logic_vector(axis_data_width_c-1 downto 0);
ldm_arb_tkeep_o : out std_logic_vector(axis_data_width_c/8-1 downto 0);
ldm_arb_tready_i : in std_logic;
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l2p_rdy_i : in std_logic; -- De-asserted to pause transdert already in progress
tx_error_i : in std_logic; -- Asserted when unexpected or malformed paket received
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic;
l2p_dma_adr_o : out std_logic_vector(wb_address_width_c-1 downto 0);
l2p_dma_dat_i : in std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_dat_o : out std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_sel_o : out std_logic_vector(3 downto 0);
l2p_dma_cyc_o : out std_logic;
l2p_dma_stb_o : out std_logic;
l2p_dma_we_o : out std_logic;
l2p_dma_ack_i : in std_logic;
l2p_dma_stall_i : in std_logic;
p2l_dma_cyc_i : in std_logic; -- P2L dma WB cycle for bus arbitration
--DMA Debug
l2p_current_state_do : out std_logic_vector (2 downto 0);
l2p_data_cnt_do : out unsigned(12 downto 0);
l2p_len_cnt_do : out unsigned(12 downto 0);
l2p_timeout_cnt_do : out unsigned(12 downto 0);
wb_timeout_cnt_do : out unsigned(12 downto 0);
-- Data FIFO
data_fifo_rd_do : out std_logic;
data_fifo_wr_do : out std_logic;
data_fifo_empty_do : out std_logic;
data_fifo_full_do : out std_logic;
data_fifo_dout_do : out std_logic_vector(axis_data_width_c-1 downto 0);
data_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
addr_fifo_rd_do : out std_logic;
addr_fifo_wr_do : out std_logic;
addr_fifo_empty_do : out std_logic;
addr_fifo_full_do : out std_logic;
addr_fifo_dout_do : out std_logic_vector(axis_data_width_c-1 downto 0);
addr_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0)
);
end component;
component mig_7series_0
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(28 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic
);
end component mig_7series_0;
component ddr3_ctrl_wb
generic(
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64
);
port(
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_addr_o : out std_logic_vector(28 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_sr_req_o : out std_logic;
ddr_ref_req_o : out std_logic;
ddr_zq_req_o : out std_logic;
ddr_sr_active_i : in std_logic;
ddr_ref_ack_i : in std_logic;
ddr_zq_ack_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_ui_clk_sync_rst_i : in std_logic;
ddr_init_calib_complete_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Debug ports
----------------------------------------------------------------------------
ddr_wb_rd_mask_dout_do : out std_logic_vector(7 downto 0);
ddr_wb_rd_mask_addr_dout_do : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_rd_mask_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_data_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_fifo_full_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_empty_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_rd_do : out std_logic_vector(1 downto 0)
);
end component ddr3_ctrl_wb;
component debugregisters is
generic (
constant ADDR_WIDTH : integer := 4;
constant DATA_WIDTH : integer := 32
);
Port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic ;
-- input/ouput
dummyram_sel_o : out std_logic;
ddr3ram_sel_o : out std_logic;
dummyaddress_sel_o : out std_logic;
dummydeadbeef_sel_o : out std_logic;
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0)--;
--ddr_init_calib_complete_i : in std_logic
);
end component;
COMPONENT ila_axis
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_dma_ctrl_reg
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_wsh_pipe
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(36 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_pd_pdm
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(1 DOWNTO 1)
);
END COMPONENT ;
COMPONENT ila_l2p_dma
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe26 : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
probe27 : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe32 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe33 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe34 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe38 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe39 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe40 : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
probe41 : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
probe42 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
COMPONENT ila_ddr
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(28 DOWNTO 0)
);
END COMPONENT ;
end app_pkg;
package body app_pkg is
end app_pkg;
|
gpl-3.0
|
8bfd72447789516987eb9861296c759a
| 0.491111 | 3.624108 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_IIR_Debugger.vhd
| 1 | 1,886 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_IIR_Debugger is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_IIR_Debugger;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_IIR_Debugger is
begin
Generic_IIR : entity work.Generic_IIR
generic map(ORDER => 2,
IN_WIDTH => 16,
IN_FRACT => 11,
B_WIDTH => 16,
B_FRACT => 13,
A_WIDTH => 16,
A_FRACT => 14,
INTERNAL_WIDTH => 24,
INTERNAL_FRACT => 12,
OUT_WIDTH => 16,
OUT_FRACT => 9)
port map(clk => clk,
reset => reset,
x => input,
B => x"2000" &
x"0000" &
x"0000",
A => x"4000" &
x"4000",
y => output);
end architecture;
|
mit
|
ed802d5fef377f91b7d01acb44ea7102
| 0.252386 | 6.163399 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/k_bram.vhd
| 2 | 19,120 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/07/2017 03:04:27 PM
-- Design Name:
-- Module Name: k_bram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity k_bram is
generic (
constant ADDR_WIDTH : integer := 9+4;--9+4
constant DATA_WIDTH : integer := 64
);
Port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic
);
end k_bram;
architecture Behavioral of k_bram is
constant bram_col_exp_c : integer := 4; --4
constant bram_col_c : integer := 2**bram_col_exp_c;
--constant bram_row_c : integer := 4;
type ram_data_bus is array (bram_col_c-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal di : std_logic_vector(DATA_WIDTH-1 downto 0);
signal do : ram_data_bus;
signal we : std_logic_vector(DATA_WIDTH/8-1 downto 0);
signal en : std_logic_vector(bram_col_c-1 downto 0);
signal regce : std_logic;
signal select_s : std_logic_vector (bram_col_exp_c-1 downto 0);
--signal select_1_s : integer;
begin
ADDR <= wb_adr_i(ADDR_WIDTH-1 downto 0);
bram: process (clk, rst)
begin
if (rst ='1') then
wb_ack_o <= '0';
elsif (clk'event and clk = '1') then
if (wb_stb_i = '1' and wb_cyc_i = '1') then
wb_ack_o <= '1';
else
wb_ack_o <= '0';
end if;
end if;
end process bram;
process(clk)
begin
if (clk'event and clk = '1') then
select_s <= ADDR(9+bram_col_exp_c-1 downto 9);
end if;
end process;
wb_dat_o <= DO(conv_integer(select_s));
gen_bram:for i in 0 to bram_col_c-1 generate
en(i) <= wb_cyc_i when ADDR(8+bram_col_exp_c downto 9) = std_logic_vector(to_unsigned(i,bram_col_exp_c))
else '0';
gen_we:for i in 0 to DATA_WIDTH/8-1 generate
we(i) <= wb_we_i;
end generate gen_we;
-- BRAM_SINGLE_MACRO: Single Port RAM
-- Kintex-7
-- Xilinx HDL Language Template, version 2016.2
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
---------------------------------------------------------------------
-- READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | --
-- WRITE_WIDTH | | WRITE Depth | | WE Width --
-- ============|===========|=============|============|============--
-- 37-72 | "36Kb" | 512 | 9-bit | 8-bit --
-- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit --
-- 19-36 | "18Kb" | 512 | 9-bit | 4-bit --
-- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit --
-- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit --
-- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit --
-- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit --
-- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit --
-- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit --
-- 2 | "36Kb" | 16384 | 14-bit | 1-bit --
-- 2 | "18Kb" | 8192 | 13-bit | 1-bit --
-- 1 | "36Kb" | 32768 | 15-bit | 1-bit --
-- 1 | "18Kb" | 16384 | 14-bit | 1-bit --
---------------------------------------------------------------------
BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACRO
generic map (
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6"
DO_REG => 0, -- Optional output register (0 or 1)
INIT => X"000000000000000000", -- Initial values on output port
INIT_FILE => "NONE",
WRITE_WIDTH => 64, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
READ_WIDTH => 64, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
SRVAL => X"000000000000000000", -- Set/Reset value for port output
WRITE_MODE => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
-- The following INIT_xx declarations specify the initial contents of the RAM
INIT_00 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_01 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_02 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_03 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_04 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_05 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_06 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_07 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_08 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_09 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_0A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_0B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_0C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_0D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_0E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_0F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_10 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_11 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_12 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_13 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_14 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_15 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_16 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_17 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_18 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_19 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_1A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_1B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_1C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_1D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_1E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_1F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_20 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_21 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_22 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_23 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_24 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_25 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_26 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_27 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_28 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_29 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_2A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_2B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_2C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_2D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_2E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_2F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_30 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_31 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_32 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_33 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_34 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_35 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_36 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_37 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_38 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_39 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_3A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_3B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_3C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_3D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_3E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_3F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
-- The next set of INIT_xx are valid when configured as 36Kb
INIT_40 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_41 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_42 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_43 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_44 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_45 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_46 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_47 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_48 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_49 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_4A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_4B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_4C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_4D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_4E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_4F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_50 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_51 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_52 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_53 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_54 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_55 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_56 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_57 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_58 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_59 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_5A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_5B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_5C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_5D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_5E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_5F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_60 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_61 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_62 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_63 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_64 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_65 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_66 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_67 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_68 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_69 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_6A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_6B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_6C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_6D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_6E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_6F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_70 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_71 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_72 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_73 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_74 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_75 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_76 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_77 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_78 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_79 => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_7A => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_7B => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_7C => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_7D => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_7E => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
INIT_7F => X"DEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF",
-- The next set of INITP_xx are for the parity bits
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INIT_xx are valid when configured as 36Kb
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => DO(i), -- 64-bit Output data, width defined by READ_WIDTH parameter
ADDR => ADDR(9-1 downto 0), -- 9-bit Input address, width defined by read/write port depth
CLK => CLK, -- 1-bit input clock
DI => wb_dat_i, -- 64-bit Input data port, width defined by WRITE_WIDTH parameter
EN => en(i), -- 1-bit input RAM enable
REGCE => wb_stb_i, -- 1-bit input output register enable
RST => RST, -- 1-bit input reset
WE => WE -- 8-bit Input write enable, width defined by write port depth
);
-- End of BRAM_SINGLE_MACRO_inst instantiation
end generate gen_bram;
end Behavioral;
|
gpl-3.0
|
0aa52c73135e6a36b63c4f6f20608399
| 0.712134 | 5.760771 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/rtl/example_top.vhd
| 2 | 45,380 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p1_DATA_MODE : std_logic_vector(3 downto 0);
C_p1_END_ADDRESS : std_logic_vector(31 downto 0);
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"10";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"01";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"10";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 1;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000004ff", x"04ffffff");
constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p1_cmd_en : std_logic;
signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p1_cmd_empty : std_logic;
signal c3_p1_cmd_full : std_logic;
signal c3_p1_wr_en : std_logic;
signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_wr_full : std_logic;
signal c3_p1_wr_empty : std_logic;
signal c3_p1_wr_count : std_logic_vector(6 downto 0);
signal c3_p1_wr_underrun : std_logic;
signal c3_p1_wr_error : std_logic;
signal c3_p1_rd_en : std_logic;
signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_rd_full : std_logic;
signal c3_p1_rd_empty : std_logic;
signal c3_p1_rd_count : std_logic_vector(6 downto 0);
signal c3_p1_rd_overflow : std_logic;
signal c3_p1_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c3_error;
calib_done <= c3_calib_done;
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_clk0,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_clk0,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_clk0,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_clk0,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_clk0,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_clk0,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C3_p1_DATA_MODE,
C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p1_mcb_cmd_en_o => c3_p1_cmd_en,
p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c3_p1_cmd_full,
p1_mcb_wr_en_o => c3_p1_wr_en,
p1_mcb_wr_mask_o => c3_p1_wr_mask,
p1_mcb_wr_data_o => c3_p1_wr_data,
p1_mcb_wr_full_i => c3_p1_wr_full,
p1_mcb_wr_fifo_counts => c3_p1_wr_count,
p1_mcb_rd_en_o => c3_p1_rd_en,
p1_mcb_rd_data_i => c3_p1_rd_data,
p1_mcb_rd_empty_i => c3_p1_rd_empty,
p1_mcb_rd_fifo_counts => c3_p1_rd_count
);
end arc;
|
gpl-3.0
|
c80d9c42a154c0e4c85ee86fa3d2abf6
| 0.452821 | 3.401289 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/base_line/LBDR.vhd
| 1 | 3,035 |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
cur_addr_y, cur_addr_x: in std_logic_vector(6 downto 0);
dst_addr_y, dst_addr_x: in std_logic_vector(6 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
N1 <= '1' when dst_addr_y < cur_addr_y else '0';
E1 <= '1' when cur_addr_x < dst_addr_x else '0';
W1 <= '1' when dst_addr_x < cur_addr_x else '0';
S1 <= '1' when cur_addr_y < dst_addr_y else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END;
|
gpl-3.0
|
0ea3913e162879a4d9fa362950f118a3
| 0.562438 | 2.483633 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
reg_byte.vhd
| 1 | 2,091 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use work.globals.all;
-- single byte register on a register bus
entity reg_byte is
generic (DEFAULT_VALUE : integer := 0;
REG_ADDR_BASE : reg_addr_t);
port (Clk : in std_logic;
Rst : in std_logic;
RegBusI : in reg_bus_t;
RegBusO : out reg_bus_t;
Value : out byte_t);
end reg_byte;
-- Operation:
-- Hold the @Value. Access it when address on the bus matches @REG_ADDR_BASE.
--
-- This version of register is slightly optimised, because there is no need for
-- atomicity and stuff.
architecture Behavioral of reg_byte is
signal byte : byte_t := CONV_std_logic_vector(DEFAULT_VALUE, 8);
begin
Value <= byte;
update : process (Clk)
begin
if rising_edge(Clk) then
RegBusO <= RegBusI;
if RegBusI.addr = REG_ADDR_BASE then
if RegBusI.wr = '1' then
byte <= RegBusI.data;
else
RegBusO.data <= byte;
end if;
end if;
if Rst = '1' then
RegBusO.addr <= reg_addr_invl;
byte <= CONV_std_logic_vector(DEFAULT_VALUE, 8);
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
6d5f2c4ed69b9296a0e073825b09757c
| 0.622669 | 3.872222 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/p2l_dma_master.vhd
| 2 | 29,337 |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: 32 bit P2L DMA master (p2l_dma_master.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 0.1
--
-- description: Provides a pipelined Wishbone interface to performs DMA
-- transfers from PCI express host to local application.
-- This entity is also used to catch the next item in chained DMA.
--
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
use work.common_pkg.all;
entity p2l_dma_master is
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_p2l_i : in std_logic;
dma_ctrl_start_next_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
--pd_pdm_hdr_start_i : in std_logic; -- Header strobe
--pd_pdm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
--pd_pdm_hdr_cid_i : in std_logic_vector(1 downto 0); -- Completion ID
pd_pdm_master_cpld_i : in std_logic; -- Master read completion with data
pd_pdm_master_cpln_i : in std_logic; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i : in std_logic;
pd_pdm_data_valid_w_i: in std_logic_vector(1 downto 0); -- Indicates Data is valid
pd_pdm_data_last_i : in std_logic; -- Indicates end of the packet
pd_pdm_data_i : in std_logic_vector(63 downto 0); -- Data
pd_pdm_be_i : in std_logic_vector(7 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o : out std_logic; -- Read completion signals
pdm_arb_tlast_o : out std_logic; -- Toward the arbiter
pdm_arb_tdata_o : out std_logic_vector(63 downto 0);
pdm_arb_tkeep_o : out std_logic_vector(7 downto 0);
pdm_arb_req_o : out std_logic;
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(63 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(63 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(7 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o : out std_logic_vector(31 downto 0);
next_item_host_addr_h_o : out std_logic_vector(31 downto 0);
next_item_host_addr_l_o : out std_logic_vector(31 downto 0);
next_item_len_o : out std_logic_vector(31 downto 0);
next_item_next_l_o : out std_logic_vector(31 downto 0);
next_item_next_h_o : out std_logic_vector(31 downto 0);
next_item_attrib_o : out std_logic_vector(31 downto 0);
next_item_valid_o : out std_logic
);
end p2l_dma_master;
architecture behaviour of p2l_dma_master is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
-- c_MAX_READ_REQ_SIZE is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_MAX_READ_REQ_SIZE values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- control signals
signal is_next_item : std_logic;
signal completion_error : std_logic;
signal dma_busy_error : std_logic;
signal dma_length_error : std_logic;
signal dma_ctrl_done_t : std_logic;
signal rx_error_t : std_logic;
-- L2P packet generator
signal l2p_address_h : std_logic_vector(31 downto 0);
signal l2p_address_l : std_logic_vector(31 downto 0);
signal l2p_len_cnt : unsigned(28 downto 0);
signal l2p_len_header : unsigned(9 downto 0);
signal l2p_64b_address : std_logic;
signal s_l2p_header : std_logic_vector(63 downto 0);
signal l2p_last_packet : std_logic;
signal l2p_lbe_header : std_logic_vector(3 downto 0);
-- Target address counter
signal target_addr_cnt : unsigned(28 downto 0);
-- sync fifo
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
signal to_wb_fifo_rd : std_logic;
signal to_wb_fifo_wr : std_logic;
signal to_wb_fifo_din : std_logic_vector(95 downto 0);
signal to_wb_fifo_dout : std_logic_vector(95 downto 0);
signal to_wb_fifo_valid : std_logic;
signal to_wb_fifo_byte_swap : std_logic_vector(2 downto 0);
-- wishbone
signal wb_write_cnt : unsigned(31 downto 0);
signal wb_ack_cnt : unsigned(31 downto 0);
signal p2l_dma_cyc_t : std_logic;
signal p2l_dma_stb_t : std_logic;
signal p2l_dma_stall_d : std_logic_vector(1 downto 0);
-- P2L DMA read request FSM
type p2l_dma_state_type is (P2L_IDLE, P2L_HEADER, P2L_HEADER_1, P2L_HEADER_2, P2L_WAIT_READ_COMPLETION);
signal p2l_dma_current_state : p2l_dma_state_type;
signal p2l_data_cnt : unsigned(10 downto 0);
--signal p2l_data_cnt_1 : unsigned(10 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for fifo
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst_n <= not(rst_n_i);
end generate;
-- Errors to DMA controller
dma_ctrl_error_o <= dma_busy_error or completion_error;
------------------------------------------------------------------------------
-- PCIe read request
------------------------------------------------------------------------------
-- Stores infofmation for read request packet
-- Can be a P2L DMA transfer or catching the next item of a chained DMA
p_read_req : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
l2p_address_h <= (others => '0');
l2p_address_l <= (others => '0');
l2p_len_cnt <= (others => '0');
l2p_len_header <= (others => '0');
l2p_64b_address <= '0';
is_next_item <= '0';
l2p_last_packet <= '0';
elsif rising_edge(clk_i) then
if (p2l_dma_current_state = P2L_IDLE) then
if (dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1') then
-- Stores DMA info locally
l2p_address_h <= dma_ctrl_host_addr_h_i;
l2p_address_l <= dma_ctrl_host_addr_l_i;
l2p_len_cnt <= unsigned(dma_ctrl_len_i(30 downto 2)); -- dma_ctrl_len_i is in byte
if (dma_ctrl_start_next_i = '1') then
-- Catching next DMA item
is_next_item <= '1'; -- flag for data retrieve block
else
-- P2L DMA transfer
is_next_item <= '0';
end if;
if (dma_ctrl_host_addr_h_i = X"00000000") then
l2p_64b_address <= '0';
else
l2p_64b_address <= '1';
end if;
end if;
elsif (p2l_dma_current_state = P2L_HEADER) then
-- if DMA length is bigger than the max PCIe payload size,
-- we have to generate several read request
if (l2p_len_cnt > c_MAX_READ_REQ_SIZE) then
-- when max payload length is 1024, the header length field = 0
l2p_len_header <= c_MAX_READ_REQ_SIZE(9 downto 0);
l2p_last_packet <= '0';
elsif (l2p_len_cnt = c_MAX_READ_REQ_SIZE) then
-- when max payload length is 1024, the header length field = 0
l2p_len_header <= c_MAX_READ_REQ_SIZE(9 downto 0);
l2p_last_packet <= '1';
else
l2p_len_header <= l2p_len_cnt(9 downto 0);
l2p_last_packet <= '1';
end if;
elsif (p2l_dma_current_state = P2L_HEADER_2) then
-- Subtract the number of word requested to generate a new read request if needed
if (l2p_last_packet = '0') then
l2p_len_cnt <= l2p_len_cnt - c_MAX_READ_REQ_SIZE;
else
l2p_len_cnt <= (others => '0');
end if;
end if;
end if;
end process p_read_req;
-- Last Byte Enable must be "0000" when length = 1
l2p_lbe_header <= "0000" when l2p_len_header = 1 else "1111";
s_l2p_header(63 downto 48) <= l2p_rid_i; --X"0100"; --> H1 Requester ID
s_l2p_header(47 downto 40) <= X"00"; --> H1 Tag
s_l2p_header(39 downto 36) <= l2p_lbe_header; --> LBE (Last Byte Enable)
s_l2p_header(35 downto 32) <= X"f"; --> FBE (First Byte Enable)
s_l2p_header(31 downto 29) <= "00" & l2p_64b_address; --> FMT without data (read request)
s_l2p_header(28 downto 24) <= "00000"; --> type Memory request
s_l2p_header(23 downto 16) <= X"00"; --> some unused bits
s_l2p_header(15 downto 10) <= "000000"; --> unused bits
s_l2p_header(9 downto 0) <= std_logic_vector(l2p_len_header); --> length H & length L
-- s_l2p_header <= "000" --> Traffic Class
-- & '0' --> Snoop
-- & "000" & l2p_64b_address --> Packet type = read request (32 or 64 bits)
-- & l2p_lbe_header --> LBE (Last Byte Enable)
-- & "1111" --> FBE (First Byte Enable)
-- & "000" --> Reserved
-- & '0' --> VC (Virtual Channel)
-- & "01" --> CID
-- & std_logic_vector(l2p_len_header); --> Length (in 32-bit words)
--0x000 => 1024 words (4096 bytes)
-----------------------------------------------------------------------------
-- PCIe read request FSM
-----------------------------------------------------------------------------
p_read_req_fsm : process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
p2l_dma_current_state <= P2L_IDLE;
pdm_arb_req_o <= '0';
pdm_arb_tdata_o <= (others => '0');
pdm_arb_tvalid_o <= '0';
pdm_arb_tlast_o <= '0';
pdm_arb_tkeep_o <= X"FF";
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
elsif rising_edge(clk_i) then
case p2l_dma_current_state is
when P2L_IDLE =>
-- Clear status bits
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
-- Start a read request when a P2L DMA is initated or when the DMA
-- controller asks for the next DMA info (in a chained DMA).
if (dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1') then
-- request access to PCIe bus
pdm_arb_req_o <= '1';
-- prepare a packet, first the header
p2l_dma_current_state <= P2L_HEADER;
end if;
when P2L_HEADER =>
if(arb_pdm_gnt_i = '1') then
-- clear access request to the arbiter
-- access is granted until dframe is cleared
--if(l2p_64b_address = '1') then
-- if host address is 64-bit, we have to send an additionnal
-- 32-word containing highest bits of the host address
--p2l_dma_current_state <= P2L_ADDR_H;
--else
-- for 32-bit host address, we only have to send lowest bits
p2l_dma_current_state <= P2L_HEADER_1;
--end if;
end if;
when P2L_HEADER_1 =>
-- send host address 32 highest bits
pdm_arb_req_o <= '0';
-- send header
pdm_arb_tdata_o <= s_l2p_header;
pdm_arb_tvalid_o <= '1';
pdm_arb_tkeep_o <= X"FF";
--pdm_arb_tdata_o <= l2p_address_h;
p2l_dma_current_state <= P2L_HEADER_2;
when P2L_HEADER_2 =>
-- send host address 32 lowest bits
if(l2p_64b_address = '1') then
pdm_arb_tdata_o <= l2p_address_l & l2p_address_h;
pdm_arb_tkeep_o <= X"FF";
else
pdm_arb_tdata_o <= X"00000000" & l2p_address_l;
pdm_arb_tkeep_o <= X"0F";
end if;
-- clear dframe signal to indicate the end of packet
pdm_arb_tlast_o <= '1';
p2l_dma_current_state <= P2L_WAIT_READ_COMPLETION;
when P2L_WAIT_READ_COMPLETION =>
-- End of the read request packet
pdm_arb_tlast_o <= '0';
pdm_arb_tvalid_o <= '0';
if (dma_ctrl_abort_i = '1') then
rx_error_t <= '1';
p2l_dma_current_state <= P2L_IDLE;
elsif (pd_pdm_master_cpld_i = '1' and pd_pdm_data_last_i = '1'
and p2l_data_cnt <= 2) then
-- last word of read completion has been received
if (l2p_last_packet = '0') then
-- A new read request is needed, DMA size > max payload
p2l_dma_current_state <= P2L_HEADER;
-- As the end of packet is used to delimit arbitration phases
-- we have to ask again for permission
pdm_arb_req_o <= '1';
else
-- indicate end of DMA transfer
if (is_next_item = '1') then
next_item_valid_o <= '1';
else
dma_ctrl_done_t <= '1';
end if;
p2l_dma_current_state <= P2L_IDLE;
end if;
elsif (pd_pdm_master_cpln_i = '1') then
-- should not return a read completion without data
completion_error <= '1';
p2l_dma_current_state <= P2L_IDLE;
end if;
when others =>
p2l_dma_current_state <= P2L_IDLE;
pdm_arb_req_o <= '0';
pdm_arb_tdata_o <= (others => '0');
pdm_arb_tvalid_o <= '0';
pdm_arb_tlast_o <= '0';
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
end case;
end if;
end process p_read_req_fsm;
------------------------------------------------------------------------------
-- Pipeline control signals
------------------------------------------------------------------------------
p_ctrl_pipe : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
rx_error_o <= '0';
dma_ctrl_done_o <= '0';
elsif rising_edge(clk_i) then
rx_error_o <= rx_error_t;
dma_ctrl_done_o <= dma_ctrl_done_t;
end if;
end process p_ctrl_pipe;
------------------------------------------------------------------------------
-- Received data counter
------------------------------------------------------------------------------
p_recv_data_cnt : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
p2l_data_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (p2l_dma_current_state = P2L_HEADER_2) then
-- Store number of 32-bit data words to be received for the current read request
if l2p_len_header = 0 then
p2l_data_cnt <= to_unsigned(1024, p2l_data_cnt'length);
else
p2l_data_cnt <= "0" & l2p_len_header(9 downto 0);
end if;
elsif (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and pd_pdm_data_valid_w_i = "11"
and pd_pdm_master_cpld_i = '1') then
-- decrement number of data to be received
p2l_data_cnt <= p2l_data_cnt - 2;
elsif (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and (pd_pdm_data_valid_w_i = "01" or pd_pdm_data_valid_w_i = "10")
and pd_pdm_master_cpld_i = '1') then
p2l_data_cnt <= p2l_data_cnt - 1;
end if;
end if;
end process p_recv_data_cnt;
------------------------------------------------------------------------------
-- Next DMA item retrieve
------------------------------------------------------------------------------
p_next_item : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
next_item_carrier_addr_o <= (others => '0');
next_item_host_addr_h_o <= (others => '0');
next_item_host_addr_l_o <= (others => '0');
next_item_len_o <= (others => '0');
next_item_next_l_o <= (others => '0');
next_item_next_h_o <= (others => '0');
next_item_attrib_o <= (others => '0');
elsif rising_edge(clk_i) then
--p2l_data_cnt_1 <= p2l_data_cnt;
if (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and is_next_item = '1' and (pd_pdm_data_valid_w_i(0) = '1' or pd_pdm_data_valid_w_i(1) = '1')) then
-- next item data are supposed to be received in the rigth order !!
case p2l_data_cnt(3 downto 0) is
when "0111" =>
if pd_pdm_data_valid_w_i(1) = '1' then next_item_host_addr_l_o <= pd_pdm_data_i(63 downto 32); end if; -- 1
if pd_pdm_data_valid_w_i(0) = '1' then next_item_carrier_addr_o <= pd_pdm_data_i(31 downto 0); end if; -- 0
when "0110" =>
if pd_pdm_data_valid_w_i(1) = '1' then next_item_host_addr_h_o <= pd_pdm_data_i(63 downto 32); end if; -- 2
if pd_pdm_data_valid_w_i(0) = '1' then next_item_host_addr_l_o <= pd_pdm_data_i(31 downto 0); end if; -- 1
when "0101" =>
if pd_pdm_data_valid_w_i(1) = '1' then next_item_len_o <= pd_pdm_data_i(63 downto 32); end if; -- 3
if pd_pdm_data_valid_w_i(0) = '1' then next_item_host_addr_h_o <= pd_pdm_data_i(31 downto 0); end if; -- 2
when "0100" =>
if pd_pdm_data_valid_w_i(1) = '1' then next_item_next_l_o <= pd_pdm_data_i(63 downto 32); end if; -- 4
if pd_pdm_data_valid_w_i(0) = '1' then next_item_len_o <= pd_pdm_data_i(31 downto 0); end if; -- 3
when "0011" =>
if pd_pdm_data_valid_w_i(1) = '1' then next_item_next_h_o <= pd_pdm_data_i(63 downto 32); end if; -- 5
if pd_pdm_data_valid_w_i(0) = '1' then next_item_next_l_o <= pd_pdm_data_i(31 downto 0); end if; -- 4
when "0010" =>
if pd_pdm_data_valid_w_i(1) = '1' then next_item_attrib_o <= pd_pdm_data_i(63 downto 32); end if; -- 6
if pd_pdm_data_valid_w_i(0) = '1' then next_item_next_h_o <= pd_pdm_data_i(31 downto 0); end if; -- 5
when "0001" =>
if pd_pdm_data_valid_w_i(0) = '1' then next_item_attrib_o <= pd_pdm_data_i(31 downto 0); end if; -- 6
when others =>
null;
end case;
end if;
end if;
end process p_next_item;
------------------------------------------------------------------------------
-- Target address counter
------------------------------------------------------------------------------
p_addr_cnt : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
target_addr_cnt <= (others => '0');
dma_busy_error <= '0';
to_wb_fifo_din <= (others => '0');
to_wb_fifo_wr <= '0';
to_wb_fifo_byte_swap <= (others => '0');
elsif rising_edge(clk_i) then
if (dma_ctrl_start_p2l_i = '1') then
if (p2l_dma_current_state = P2L_IDLE) then
-- dma_ctrl_target_addr_i is a byte address and target_addr_cnt is a
-- 64-bit word address
target_addr_cnt <= unsigned(dma_ctrl_carrier_addr_i(31 downto 3));
-- stores byte swap info for the current DMA transfer
to_wb_fifo_byte_swap <= dma_ctrl_byte_swap_i;
else
dma_busy_error <= '1';
end if;
elsif (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and is_next_item = '0' and (pd_pdm_data_valid_w_i(0) = '1' or pd_pdm_data_valid_w_i(1) = '1')) then
-- increment target address counter
target_addr_cnt <= target_addr_cnt + 1;
-- write target address and data to the sync fifo
to_wb_fifo_wr <= '1';
to_wb_fifo_din(63 downto 0) <= pd_pdm_data_i; --f_byte_swap(g_BYTE_SWAP, pd_pdm_data_i, to_wb_fifo_byte_swap);
to_wb_fifo_din(92 downto 64) <= std_logic_vector(target_addr_cnt);
else
dma_busy_error <= '0';
to_wb_fifo_wr <= '0';
end if;
end if;
end process p_addr_cnt;
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
cmp_to_wb_fifo : generic_async_fifo
generic map (
g_data_width => 96,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => p2l_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
--p_gen_fifo_valid : process(p2l_dma_clk_i)
--begin
--if rising_edge(p2l_dma_clk_i) then
to_wb_fifo_valid <= to_wb_fifo_rd and (not to_wb_fifo_empty);
--end if;
--end process;
-- pause transfer from GN4124 if fifo is (almost) full
p2l_rdy_o <= not(to_wb_fifo_full);
------------------------------------------------------------------------------
-- Wishbone master (write only)
------------------------------------------------------------------------------
-- fifo read
to_wb_fifo_rd <= not(to_wb_fifo_empty)
and not(p2l_dma_stall_i)
and not(l2p_dma_cyc_i);
-- write only
p2l_dma_we_o <= '1';
-- Wishbone master process
p_wb_master : process (rst_n_i, p2l_dma_clk_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
p2l_dma_cyc_t <= '0';
p2l_dma_stb_t <= '0';
p2l_dma_sel_o <= (others => '0');
p2l_dma_adr_o <= (others => '0');
p2l_dma_dat_o <= (others => '0');
p2l_dma_stall_d <= (others => '0');
elsif rising_edge(p2l_dma_clk_i) then
p2l_dma_stall_d(0) <= p2l_dma_stall_i;
p2l_dma_stall_d(1) <= p2l_dma_stall_d(0);
-- data and address
if (to_wb_fifo_valid = '1') then
--p2l_dma_adr_o(31 downto 30) <= "00";
p2l_dma_adr_o(31 downto 0) <= to_wb_fifo_dout(95 downto 64);
p2l_dma_dat_o <= to_wb_fifo_dout(63 downto 0);
end if;
-- stb and sel signals management
if (to_wb_fifo_valid = '1') then --or (p2l_dma_stall_i = '1' and p2l_dma_stb_t = '1') then
p2l_dma_stb_t <= '1';
p2l_dma_sel_o <= (others => '1');
else
p2l_dma_stb_t <= '0';
p2l_dma_sel_o <= (others => '0');
end if;
-- cyc signal management
if (to_wb_fifo_valid = '1') then
p2l_dma_cyc_t <= '1';
elsif (wb_ack_cnt >= wb_write_cnt and p2l_dma_stall_d(1) = '0') then
-- last ack received -> end of the transaction
p2l_dma_cyc_t <= '0';
end if;
end if;
end process p_wb_master;
-- for read back
p2l_dma_cyc_o <= p2l_dma_cyc_t;
p2l_dma_stb_o <= p2l_dma_stb_t;
-- Wishbone write cycle counter
p_wb_write_cnt : process (p2l_dma_clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_write_cnt <= (others => '0');
elsif rising_edge(p2l_dma_clk_i) then
if (to_wb_fifo_valid = '1') then
wb_write_cnt <= wb_write_cnt + 1;
end if;
end if;
end process p_wb_write_cnt;
-- Wishbone ack counter
p_wb_ack_cnt : process (p2l_dma_clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_ack_cnt <= (others => '0');
elsif rising_edge(p2l_dma_clk_i) then
if (p2l_dma_ack_i = '1' and p2l_dma_cyc_t = '1') then
wb_ack_cnt <= wb_ack_cnt + 1;
end if;
end if;
end process p_wb_ack_cnt;
end behaviour;
|
gpl-3.0
|
cbaaeb75966dc36511a986ace14c1d9b
| 0.491155 | 3.389601 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/sram_bram.vhd
| 4 | 2,555 |
----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
|
gpl-2.0
|
aaad0ddee35405f24bcf23a0f15da107
| 0.621135 | 3.719068 | false | false | false | false |
metaspace/ghdl_extra
|
fb/fb_ghdl.vhdl
| 1 | 3,482 |
-- fichier fb_ghdl.vhdl
-- version ven. juil. 9 10:05:20 CEST 2010 : added get_color_depth()
-- fb_ghdl.vhdl : Framebuffer wrapper for graphic display on the host computer
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
package fb_ghdl is
-- déclaration de la fonction en C
function get_fb(f : integer) return integer;
attribute foreign of get_fb :
function is "VHPIDIRECT get_fb";
function get_color_depth(expected_depth : integer) return integer;
-- initialise les constantes
constant fbx : integer := get_fb(1);
constant fbx1 : integer := fbx-1;
constant fby : integer := get_fb(2);
constant fby1 : integer := fby-1;
constant fbxv : integer := get_fb(3);
constant fbxv1 : integer := fbxv-1;
constant fbyv : integer := get_fb(4);
constant fbdepth : integer := get_color_depth(32);
constant fbsize : integer := get_fb(6);
-- crée un tableau de pixels
type screen_type is
array(integer range 0 to fby1,
integer range 0 to fbxv1) of integer;
-- Définit un pointeur vers ce type :
type screen_p is access screen_type;
-- alias permettant de retourner ce type :
function get_fbp(f : integer) return screen_p;
attribute foreign of get_fbp :
function is "VHPIDIRECT get_fb";
-- initialise l'adresse de l'écran
shared variable pixel : screen_p := get_fbp(0);
procedure save_pixels(n: string);
-- Active le clignotement du curseur
constant esc_cursor_on : string := ESC & "[?c";
-- Eteint le curseur
constant esc_cursor_off : string := ESC & "[?17c";
end fb_ghdl;
package body fb_ghdl is
function get_fb(f : integer) return integer is
begin
assert false report "VHPI" severity failure;
end get_fb;
function get_fbp(f : integer) return screen_p is
begin
assert false report "VHPI" severity failure;
end get_fbp;
function get_color_depth(expected_depth : integer) return integer is
variable t : integer;
begin
t := get_fb(5);
assert t = expected_depth
report "framebuffer pixel depth is not " & integer'image(expected_depth)
severity failure;
return t;
end get_color_depth;
procedure save_pixels(n: string) is
type screen_line is array(0 to (3*fbx)-1) of character;
variable buff : screen_line;
type screen_file is file of screen_line;
file pixout : screen_file open write_mode is n;
variable i,j,k,l: integer;
begin
for j in 0 to fby1 loop
l:=0;
-- collecte les composantes
for i in 0 to fbx1 loop
k:=pixel(j,i);
buff(l ):= character'val((k/65536) mod 256);
buff(l+1):= character'val((k/256) mod 256);
buff(l+2):= character'val( k mod 256);
l:=l+3;
end loop;
-- écriture du tampon
write(pixout,buff);
end loop;
end save_pixels;
end fb_ghdl;
|
gpl-3.0
|
f2e6448d7f7f6400da88be9cf1244448
| 0.667242 | 3.57716 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_reg_dumper.vhd
| 1 | 3,414 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_reg_dumper IS
END tb_reg_dumper;
ARCHITECTURE behavior OF tb_reg_dumper IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_dumper
GENERIC (N_BYTES : integer);
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
Trgr : IN std_logic;
Regs : IN std_logic_vector(N_BYTES*8-1 downto 0);
Request : OUT std_logic;
Grant : IN std_logic;
Byte : OUT std_logic_vector(7 downto 0);
ByteEna : OUT std_logic;
ReaderBusy : IN std_logic
);
END COMPONENT;
COMPONENT uart_tx
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FreqEn : IN std_logic;
Byte : IN std_logic_vector(7 downto 0);
Kick : IN std_logic;
RsTx : OUT std_logic;
Busy : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '1';
signal Trgr : std_logic := '0';
signal Regs : std_logic_vector(31 downto 0) := X"11223344";
signal Grant : std_logic := '1';
signal ReaderBusy : std_logic := '0';
signal FreqEn : std_logic := '0';
signal Byte : std_logic_vector(7 downto 0) := X"AA";
--Outputs
signal Request : std_logic;
signal ByteEna : std_logic;
signal RsTx : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_dumper
GENERIC MAP ( N_BYTES => 4 )
PORT MAP (
Clk => Clk,
Rst => Rst,
Trgr => Trgr,
Regs => Regs,
Request => Request,
Grant => Grant,
Byte => Byte,
ByteEna => ByteEna,
ReaderBusy => ReaderBusy
);
uut2: uart_tx PORT MAP (
Clk => Clk,
Rst => Rst,
FreqEn => FreqEn,
Byte => Byte,
Kick => ByteEna,
RsTx => RsTx,
Busy => ReaderBusy
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Frequenct enable process
Freq_process :process
begin
FreqEn <= '0';
wait for Clk_period * 2;
FreqEn <= '1';
wait for Clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 20 ns;
Rst <= '0';
Trgr <= '1';
wait for 100 ns;
Trgr <= '0';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
9142efc97e4bce5d06c7ab4575062bee
| 0.579965 | 3.563674 | false | false | false | false |
starsheriff/papilio-one250
|
pong/sync_module.vhd
| 1 | 2,450 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:34:23 10/24/2015
-- Design Name:
-- Module Name: sync_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sync_module is
Port ( start : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
x_pos : out STD_LOGIC_VECTOR(9 downto 0);
y_pos : out STD_LOGIC_VECTOR(9 downto 0);
video_on : out STD_LOGIC);
end sync_module;
architecture Behavioral of sync_module is
signal hcount, vcount: integer range 0 to 799;
--signal hsync, vsync: std_logic;
signal video : std_logic;
signal x_ct : integer range 0 to 640;
begin
process(clk)
begin
if rising_edge(clk) then
-- resetting counters when end is reached
if hcount = 799 then
hcount <= 0;
if vcount = 524 then
vcount <= 0;
else
vcount <= vcount+1;
end if;
else
hcount <= hcount+1;
end if;
-- vsync
if (vcount >= 490) and (vcount <= 492) then
vsync <= '0';
else
vsync <= '1';
end if;
-- hsync
if (hcount >= 656) and (hcount <= 752) then
hsync <= '0';
else
hsync <= '1';
end if;
-- video signal and position
if (hcount <= 640) and (vcount <= 480) then
video_on <= '1';
x_pos <= std_logic_vector(to_unsigned(hcount, x_pos'length));
y_pos <= std_logic_vector(to_unsigned(vcount, y_pos'length));
else
video_on <= '0';
x_pos <= std_logic_vector(to_unsigned(0, x_pos'length));
y_pos <= std_logic_vector(to_unsigned(0, x_pos'length));
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
391e0df15e681f389cecf9399b1b5d3d
| 0.535102 | 3.882726 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/wbmaster32.vhd
| 2 | 22,794 |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: 32-bit Wishbone master (wbmaster32.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.2
--
-- description: Provides a Wishbone interface for single read and write
-- control and status registers
--
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 27-09-2010 (mcattin) Split wishbone and gn4124 clock domains
-- All signals crossing the clock domains are now going through fifos.
-- Dead times optimisation in packet generator.
-- 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
use work.common_pkg.all;
entity wbmaster32 is
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i : in std_logic; -- Header strobe
--pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_rid_i : in std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_cid_i : in std_logic_vector(15 downto 0); -- Completer ID
pd_wbm_hdr_tag_i : in std_logic_vector(7 downto 0);
pd_wbm_target_mrd_i : in std_logic; -- Target memory read
pd_wbm_target_mwr_i : in std_logic; -- Target memory write
--
-- Address
pd_wbm_addr_start_i : in std_logic; -- Address strobe
pd_wbm_addr_i : in std_logic_vector(31 downto 0); -- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i : in std_logic; -- Indicates Data is valid
--pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i : in std_logic_vector(31 downto 0); -- Data
--pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
--wbm_arb_valid_o : out std_logic; -- Read completion signals
--wbm_arb_dframe_o : out std_logic; -- Toward the arbiter
--wbm_arb_data_o : out std_logic_vector(31 downto 0);
--wbm_arb_req_o : out std_logic;
--arb_wbm_gnt_i : in std_logic;
wbm_arb_tdata_o : out STD_LOGIC_VECTOR (64 - 1 downto 0);
wbm_arb_tkeep_o : out STD_LOGIC_VECTOR (64/8 - 1 downto 0);
--wbm_arb_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
wbm_arb_tlast_o : out STD_LOGIC;
wbm_arb_tvalid_o : out STD_LOGIC;
wbm_arb_tready_i : in STD_LOGIC;
wbm_arb_req_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic; -- Stall
wb_err_i : in std_logic; -- Error
wb_rty_i : in std_logic; -- Retry
wb_int_i : in std_logic -- Interrupt
);
end wbmaster32;
architecture behaviour of wbmaster32 is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
constant c_FROM_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Sync fifos
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
signal to_wb_fifo_rd : std_logic;
signal to_wb_fifo_wr : std_logic;
signal to_wb_fifo_din : std_logic_vector(63 downto 0);
signal to_wb_fifo_dout : std_logic_vector(63 downto 0);
signal to_wb_fifo_rw : std_logic;
signal to_wb_fifo_data : std_logic_vector(31 downto 0);
signal to_wb_fifo_addr : std_logic_vector(30 downto 0);
signal from_wb_fifo_empty : std_logic;
signal from_wb_fifo_full : std_logic;
signal from_wb_fifo_rd : std_logic;
signal from_wb_fifo_wr : std_logic;
signal from_wb_fifo_din : std_logic_vector(63 downto 0);
signal from_wb_fifo_dout : std_logic_vector(63 downto 0);
-- Wishbone
type wishbone_state_type is (WB_IDLE, WB_READ_FIFO, WB_CYCLE, WB_WAIT_ACK);
signal wishbone_current_state : wishbone_state_type;
signal wb_ack_t : std_logic;
signal wb_err_t : std_logic;
signal wb_dat_i_t : std_logic_vector(31 downto 0);
signal wb_cyc_t : std_logic;
signal wb_dat_o_t : std_logic_vector(31 downto 0);
signal wb_stb_t : std_logic;
signal wb_adr_t : std_logic_vector(30 downto 0);
signal wb_we_t : std_logic;
signal wb_sel_t : std_logic_vector(3 downto 0);
signal wb_stall_t : std_logic;
signal wb_ack_timeout_cnt : unsigned(log2_ceil(g_ACK_TIMEOUT)-1 downto 0);
signal wb_ack_timeout : std_logic;
-- L2P packet generator
type l2p_read_cpl_state_type is (L2P_IDLE, L2P_HEADER, L2P_DATA);
signal l2p_read_cpl_current_state : l2p_read_cpl_state_type;
signal p2l_cid : std_logic_vector(15 downto 0);
signal p2l_rid : std_logic_vector(15 downto 0);
signal p2l_tag : std_logic_vector(7 downto 0);
signal s_l2p_header0 : std_logic_vector(63 downto 0);
signal s_l2p_header1 : std_logic_vector(63 downto 0);
constant payload_length_c : STD_LOGIC_VECTOR(9 downto 0) := "0000000001";
signal byte_swap_c : STD_LOGIC_VECTOR (1 downto 0);
begin
byte_swap_c <= "11";
------------------------------------------------------------------------------
-- Active high reset for fifo
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst_n <= not(rst_n_i);
end generate;
------------------------------------------------------------------------------
-- Write frame from P2L decoder to fifo
------------------------------------------------------------------------------
-- ready to receive new target write if fifo not full
p_wr_rdy_o <= "00" when to_wb_fifo_full = '1' else "11";
-- pause transfer from GN4124 when fifo is full
p2l_rdy_o <= not(to_wb_fifo_full);
p_from_decoder : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
to_wb_fifo_din <= (others => '0');
to_wb_fifo_wr <= '0';
elsif rising_edge(clk_i) then
if (pd_wbm_target_mwr_i = '1' and pd_wbm_data_valid_i = '1') then
-- Target write
-- wishbone address is in 32-bit words and address from PCIe in byte
-- pd_wbm_addr_i(0) represent the BAR (0 = BAR0, 1 = BAR 2)
to_wb_fifo_din(62 downto 32) <= pd_wbm_addr_i(0) & pd_wbm_addr_i(31 downto 2);
to_wb_fifo_din(31 downto 0) <= pd_wbm_data_i;
to_wb_fifo_din(63) <= '1';
to_wb_fifo_wr <= '1';
elsif (pd_wbm_target_mrd_i = '1' and pd_wbm_addr_start_i = '1') then
-- Target read request
-- wishbone address is in 32-bit words and address from PCIe in byte
-- pd_wbm_addr_i(0) represent the BAR (0 = BAR0, 1 = BAR 2)
to_wb_fifo_din(62 downto 32) <= pd_wbm_addr_i(0) & pd_wbm_addr_i(31 downto 2);
to_wb_fifo_din(63) <= '0';
to_wb_fifo_wr <= '1';
else
to_wb_fifo_wr <= '0';
end if;
end if;
end process p_from_decoder;
------------------------------------------------------------------------------
-- Packet generator
------------------------------------------------------------------------------
-- Generates read completion with requested data
-- Single 32-bit word read only
-- Store CID and tag for read completion packet
p_pkt_gen : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
p2l_cid <= (others => '0');
p2l_rid <= (others => '0');
p2l_tag <= (others => '0');
elsif rising_edge(clk_i) then
if (pd_wbm_hdr_start_i = '1') then
p2l_cid <= pd_wbm_hdr_cid_i;
p2l_rid <= pd_wbm_hdr_rid_i;
p2l_tag <= pd_wbm_hdr_tag_i;
end if;
end if;
end process p_pkt_gen;
--read completion header
s_l2p_header0 <= p2l_cid & -- H1: Completer ID
X"0" & -- Status and BCM
X"004" & -- Byte count
"010" & -- H0: FMT
"01010" & -- Type
X"00" & -- some bits
"000000" & -- some bits
payload_length_c; -- length
s_l2p_header1 <= wb_dat_i_t & p2l_rid & p2l_tag & "0" & wb_adr_t(4 downto 0) & "00";
-- s_l2p_header <= "000" --> Traffic Class
-- & '0' --> Reserved
-- & "0101" --> Read completion (Master read competition with data)
-- & "000000" --> Reserved
-- & "00" --> Completion Status
-- & '1' --> Last completion packet
-- & "00" --> Reserved
-- & '0' --> VC (Vitrual Channel)
-- & p2l_cid --> CID (Completion Identifer)
-- & "0000000001"; --> Length (Single 32-bit word read only)
------------------------------------------------------------------------------
-- L2P packet write FSM
------------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_req_o <= '0';
wbm_arb_tdata_o <= (others => '0');
wbm_arb_tvalid_o <= '0';
wbm_arb_tlast_o <= '0';
from_wb_fifo_rd <= '0';
elsif rising_edge(clk_i) then
case l2p_read_cpl_current_state is
when L2P_IDLE =>
wbm_arb_req_o <= '0';
wbm_arb_tdata_o <= (others => '0');
wbm_arb_tvalid_o <= '0';
wbm_arb_tlast_o <= '0';
if(from_wb_fifo_empty = '0' and p_rd_d_rdy_i = "11") then
-- generate a packet when read data in fifo and GN4124 ready to receive the packet
wbm_arb_req_o <= '1';
from_wb_fifo_rd <= '1';
l2p_read_cpl_current_state <= L2P_HEADER;
end if;
when L2P_HEADER =>
from_wb_fifo_rd <= '0';
if(wbm_arb_tready_i = '1') then
wbm_arb_req_o <= '0';
wbm_arb_tdata_o <= s_l2p_header0;
wbm_arb_tvalid_o <= '1';
wbm_arb_tlast_o <= '0';
l2p_read_cpl_current_state <= L2P_DATA;
end if;
when L2P_DATA =>
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_tdata_o <= f_byte_swap(true, from_wb_fifo_dout(63 downto 32), byte_swap_c) & from_wb_fifo_dout(31 downto 0); -- DATA and ADDRESS
wbm_arb_tlast_o <= '1';
when others =>
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_req_o <= '0';
wbm_arb_tdata_o <= (others => '0');
wbm_arb_tvalid_o <= '0';
wbm_arb_tlast_o <= '0';
from_wb_fifo_rd <= '0';
end case;
end if;
end process;
wbm_arb_tkeep_o <= X"FF";
-----------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
-----------------------------------------------------------------------------
-- fifo for PCIe to WB transfer
cmp_fifo_to_wb : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => wb_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
to_wb_fifo_rw <= to_wb_fifo_dout(63);
to_wb_fifo_addr <= to_wb_fifo_dout(62 downto 32); -- 31-bit
to_wb_fifo_data <= to_wb_fifo_dout(31 downto 0); -- 32-bit
-- fifo for WB to PCIe transfer
cmp_from_wb_fifo : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_FROM_WB_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => wb_clk_i,
d_i => from_wb_fifo_din,
we_i => from_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => from_wb_fifo_full,
wr_count_o => open,
clk_rd_i => clk_i,
q_o => from_wb_fifo_dout,
rd_i => from_wb_fifo_rd,
rd_empty_o => from_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
-----------------------------------------------------------------------------
-- Wishbone master FSM
-----------------------------------------------------------------------------
p_wb_fsm : process (wb_clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
wishbone_current_state <= WB_IDLE;
to_wb_fifo_rd <= '0';
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_we_t <= '0';
wb_sel_t <= "0000";
wb_dat_o_t <= (others => '0');
wb_adr_t <= (others => '0');
from_wb_fifo_din <= (others => '0');
from_wb_fifo_wr <= '0';
elsif rising_edge(wb_clk_i) then
case wishbone_current_state is
when WB_IDLE =>
-- stop writing to fifo
from_wb_fifo_wr <= '0';
-- clear bus
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_sel_t <= "0000";
-- Wait for a Wishbone cycle
if (to_wb_fifo_empty = '0') then
-- read requset in fifo (address, data and transfer type)
to_wb_fifo_rd <= '1';
wishbone_current_state <= WB_READ_FIFO;
end if;
when WB_READ_FIFO =>
-- read only one request in fifo (no block transfer)
to_wb_fifo_rd <= '0';
wishbone_current_state <= WB_CYCLE;
when WB_CYCLE =>
-- initate a bus cycle
wb_cyc_t <= '1';
wb_stb_t <= '1';
wb_we_t <= to_wb_fifo_rw;
wb_sel_t <= "1111";
wb_adr_t <= to_wb_fifo_addr;
--if (to_wb_fifo_rw = '1') then
wb_dat_o_t <= to_wb_fifo_data;
--end if;
-- wait for slave to ack
wishbone_current_state <= WB_WAIT_ACK;
when WB_WAIT_ACK =>
if wb_stall_t = '0' then
wb_stb_t <= '0';
end if;
if (wb_ack_t = '1') then
-- for read cycles write read data to fifo
if (wb_we_t = '0') then
from_wb_fifo_din <= s_l2p_header1;
from_wb_fifo_wr <= '1';
end if;
-- end of the bus cycle
wb_cyc_t <= '0';
wishbone_current_state <= WB_IDLE;
elsif (wb_err_t = '1') or (wb_ack_timeout = '1') then
-- e.g. When trying to access unmapped wishbone addresses,
-- the wb crossbar asserts ERR. If ERR is not asserted when
-- accessing un-mapped addresses, a timeout makes sure the
-- transaction terminates.
if (wb_we_t = '0') then
from_wb_fifo_din <= (others => '1'); -- dummy data as the transaction failed
from_wb_fifo_wr <= '1';
end if;
-- end of the bus cycle
wb_cyc_t <= '0';
wishbone_current_state <= WB_IDLE;
end if;
when others =>
-- should not get here!
wishbone_current_state <= WB_IDLE;
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_we_t <= '0';
wb_sel_t <= "0000";
wb_dat_o_t <= (others => '0');
wb_adr_t <= (others => '0');
to_wb_fifo_rd <= '0';
from_wb_fifo_din <= (others => '0');
from_wb_fifo_wr <= '0';
end case;
end if;
end process p_wb_fsm;
wb_adr_o <= wb_adr_t;
wb_cyc_o <= wb_cyc_t;
wb_stb_o <= wb_stb_t;
wb_we_o <= wb_we_t;
wb_sel_o <= wb_sel_t;
wb_dat_i_t <= wb_dat_i;
wb_dat_o <= wb_dat_o_t;
wb_ack_t <= wb_ack_i;
wb_stall_t <= wb_stall_i;
wb_err_t <= wb_err_i;
-- ACK timeout
p_wb_ack_timeout_cnt : process (wb_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
wb_ack_timeout_cnt <= (others => '1');
elsif rising_edge(wb_clk_i) then
if wishbone_current_state = WB_WAIT_ACK then
if wb_ack_timeout_cnt /= 0 then
wb_ack_timeout_cnt <= wb_ack_timeout_cnt - 1;
end if;
else
wb_ack_timeout_cnt <= (others => '1');
end if;
end if;
end process p_wb_ack_timeout_cnt;
p_ack_timeout : process (wb_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
wb_ack_timeout <= '0';
elsif rising_edge(wb_clk_i) then
if wb_ack_timeout_cnt = 0 then
wb_ack_timeout <= '1';
else
wb_ack_timeout <= '0';
end if;
end if;
end process p_ack_timeout;
end behaviour;
|
gpl-3.0
|
7e05f14283ebc9dd2dde814988053c77
| 0.460823 | 3.586782 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/DAPwm.vhd
| 1 | 1,649 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity DAPwm is
generic (
wordLength : natural := 12
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic;
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- DAPwm
architecture arch of DAPwm is
signal sampleClk : std_logic;
type reg_type is record
countdown : natural range 0 to (2**wordLength)-1;
bit : std_logic;
end record;
signal r, rin : reg_type;
signal inputUnsigned : std_logic_vector(wordLength-1 downto 0);
begin
output <= r.bit;
-- Flip the MSB to map from signed fixed input to output duty cycle
--1000 -> 0000
--1111 -> 0111
--0000 -> 1000
--0111 -> 1111
inputUnsigned <= not(input(wordLength-1)) & input(wordLength-2 downto 0);
sampleClkGenerator : entity work.ClockDivider
generic map (
divider => 2**wordLength -- 4096 for 12 bits
)
port map (
clk => clk,
clkOut => sampleClk,
reset => reset
);
clk_proc : process( clk, reset )
begin
if(reset = '1') then
r.countdown <= 0;
r.bit <= '0';
elsif(rising_edge(clk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin, inputUnsigned, sampleClk )
variable v : reg_type;
begin
v := r;
if(sampleClk = '1') then
v.countdown := to_integer(unsigned(inputUnsigned));
-- If statement may be removed for optimization
if(v.countdown >= 0) then
v.bit := '1';
else
v.bit := '0';
end if;
elsif(r.countdown <= 0) then
v.bit := '0';
else
v.countdown := r.countdown-1;
end if;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
a7d874afcf4c4e98b1a7319613f72e73
| 0.637356 | 2.965827 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
bus_append.vhd
| 1 | 2,521 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Generic bus append module
-- Appends Value (N_BYTES long) after packet on the bus
-- Value is latched with InPkt, what is seen on the last cycle
-- with InPkt high will be transmitted byte by byte onto the wire
-- Transmission is big endian
--
-- WARNING: Pkt signal must be (and is kept) continuous
entity bus_append is
Generic ( N_BYTES : integer );
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Value : in STD_LOGIC_VECTOR (N_BYTES*8 - 1 downto 0);
InPkt : in STD_LOGIC;
InData : in STD_LOGIC_VECTOR (7 downto 0);
OutPkt : out STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (7 downto 0));
end bus_append;
architecture Behavioral of bus_append is
constant UBIT : integer := N_BYTES * 8 - 1;
begin
main: process (Clk)
variable delayPkt : STD_LOGIC;
variable delayData : STD_LOGIC_VECTOR(7 downto 0);
variable saveValue : STD_LOGIC_VECTOR (UBIT downto 0);
variable write_out : STD_LOGIC := '0';
variable write_cnt : integer range 0 to N_BYTES - 1;
begin
if RISING_EDGE(Clk) then
OutPkt <= delayPkt;
OutData <= delayData;
if write_out = '1' then
OutPkt <= '1';
OutData <= saveValue(UBIT - write_cnt*8 downto UBIT - 7 - write_cnt*8);
if write_cnt = N_BYTES - 1 then
write_out := '0';
end if;
write_cnt := write_cnt + 1;
end if;
if InPkt = '1' then
saveValue := Value;
end if;
if delayPkt = '1' and InPkt = '0' then
write_out := '1';
write_cnt := 0;
end if;
delayPkt := InPkt;
delayData := InData;
if rst = '1' then
write_out := '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
bc7acdba8eb9d7c4c71bcbd1181f115d
| 0.646569 | 3.252903 | false | false | false | false |
Project-Bonfire/Bonfire
|
Packages/TB_Package_32_bit_credit_based_vc_NI.vhd
| 1 | 15,606 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function CX_GEN(current_address, network_x, network_y : integer) return integer;
procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0); -- reserved address for sending data to VC 0
signal reserved_address_vc : in std_logic_vector(29 downto 0); -- reserved address for sending data to VC 1
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0));
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function CX_GEN(current_address, network_x, network_y: integer) return integer is
variable X, Y : integer := 0;
variable CN, CE, CW, CS : std_logic := '0';
variable CX : std_logic_vector(3 downto 0);
begin
X := current_address mod network_x;
Y := current_address / network_x;
if X /= 0 then
CW := '1';
end if;
if X /= network_x-1 then
CE := '1';
end if;
if Y /= 0 then
CN := '1';
end if;
if Y /= network_y-1 then
CS := '1';
end if;
CX := CS&CW&CE&CN;
return to_integer(unsigned(CX));
end CX_GEN;
procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal reserved_address_vc : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0)) is
-- variables for random functions
constant DATA_WIDTH : integer := 32;
variable seed1 :positive := current_address+1;
variable seed2 :positive := current_address+1;
variable rand : real ;
--file handling variables
variable SEND_LINEVARIABLE : line;
file SEND_FILE : text;
variable RECEIVED_LINEVARIABLE : line;
file RECEIVED_FILE : text;
-- receiving variables
variable receive_source_node, receive_destination_node, receive_packet_id, receive_counter, receive_packet_length: integer;
variable receive_source_node_vc, receive_destination_node_vc, receive_packet_id_vc, receive_counter_vc, receive_packet_length_vc: integer;
-- sending variables
variable send_destination_node, send_counter, send_id_counter: integer:= 0;
variable send_packet_length: integer:= 8;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit);
variable state : state_type;
variable frame_starting_delay : integer:= 0;
variable frame_counter: integer:= 0;
variable first_packet : boolean := True;
variable vc: integer := 0; -- virtual channel selector
variable read_vc: integer := 0; -- virtual channel selector
begin
file_open(RECEIVED_FILE,"received.txt",WRITE_MODE);
file_open(SEND_FILE,"sent.txt",WRITE_MODE);
enable <= '1';
state := Idle;
send_packet_length := min_packet_size;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size-1)))/100);
wait until clk'event and clk ='0';
address <= reconfiguration_address;
wait until clk'event and clk ='0';
write_byte_enable <= "1111";
data_write <= "00000000000000000000" & std_logic_vector(to_unsigned(CX_GEN(current_address, network_x, network_y), 4)) & std_logic_vector(to_unsigned(60, 8));
wait until clk'event and clk ='0';
write_byte_enable <= "0000";
data_write <= (others =>'0');
while true loop
-- read the flag status
address <= flag_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
--flag register is organized like this:
-- .-------------------------------------------------.
-- | N2P_empty | P2N_full | ...|
-- '-------------------------------------------------'
-- Note that VC 1 has higher priority to VC 0
if data_read(29) = '0' then -- N2P VC1 is not empty, can receive flit
-- set the address for VC1
address <= reserved_address_vc;
read_vc := 1;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node_vc := to_integer(unsigned(data_read(14 downto 8)))* network_x+to_integer(unsigned(data_read(7 downto 1)));
receive_source_node_vc :=to_integer(unsigned(data_read(21 downto 15)))* network_x+to_integer(unsigned(data_read(21 downto 15)));
receive_counter_vc := 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter_vc = 1 then
receive_packet_length_vc := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id_vc := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter_vc := receive_counter_vc + 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter_vc := receive_counter_vc +1;
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node_vc) & " to: " & integer'image(receive_destination_node_vc) & " length: "& integer'image(receive_packet_length_vc) & " actual length: "& integer'image(receive_counter_vc) & " id: "& integer'image(receive_packet_id_vc)& " VC: "& integer'image(read_vc));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
end if;
elsif data_read(31) = '0' then -- N2P VC0 is not empty, can receive flit
-- set the address for VC0
address <= reserved_address;
read_vc := 0;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node := to_integer(unsigned(data_read(14 downto 8)))* network_x+to_integer(unsigned(data_read(7 downto 1)));
receive_source_node :=to_integer(unsigned(data_read(21 downto 15)))* network_x+to_integer(unsigned(data_read(21 downto 15)));
receive_counter := 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter = 1 then
receive_packet_length := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter := receive_counter+1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter := receive_counter+1;
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id)& " VC: "& integer'image(read_vc));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
end if;
elsif data_read(30) = '0' then -- P2N is not full, can send flit
if frame_counter >= frame_starting_delay then
if state = Idle and now < finish_time then
if frame_counter < frame_starting_delay+1 then
state := Header_flit;
send_counter := send_counter+1;
-- generating the destination address
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_x*network_y)-1));
while (send_destination_node = current_address) loop
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_x*network_y)-1));
end loop;
uniform(seed1, seed2, rand);
vc := integer(rand*real(1));
-- this is the header flit
if vc = 1 then
address <= reserved_address_vc;
write_byte_enable <= "1111";
-- if you want to write into VC1 you should write "00000000000001" into the sender part! (since the NI sets the source address automatically, the source address field can be used for selecting VC)
data_write <= "0000" & "00000000000001" & std_logic_vector(to_unsigned(send_destination_node/network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node mod network_x, 7));
else
address <= reserved_address;
write_byte_enable <= "1111";
data_write <= "0000" & "00000000000000" & std_logic_vector(to_unsigned(send_destination_node/network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node mod network_x, 7));
end if;
write(SEND_LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(current_address) & " to " & integer'image(send_destination_node) & " with length: "& integer'image(send_packet_length) & " id: " & integer'image(send_id_counter) & " VC: " & integer'image(vc));
writeline(SEND_FILE, SEND_LINEVARIABLE);
else
state := Idle;
end if;
elsif state = Header_flit then
--generating the packet length
uniform(seed1, seed2, rand);
send_packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (send_packet_length < min_packet_size) then
send_packet_length:=min_packet_size;
end if;
if (send_packet_length > max_packet_size) then
send_packet_length:=max_packet_size;
end if;
if vc = 1 then
address <= reserved_address_vc;
else
address <= reserved_address;
end if;
write_byte_enable <= "1111";
-- first body flit
if first_packet = True then
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
else
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
end if;
send_counter := send_counter+1;
state := Body_flit;
elsif state = Body_flit then
-- rest of body flits
if vc = 1 then
address <= reserved_address_vc;
else
address <= reserved_address;
end if;
write_byte_enable <= "1111";
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
send_counter := send_counter+1;
if send_counter = send_packet_length-1 then
state := Tail_flit;
else
state := Body_flit;
end if;
elsif state = Tail_flit then
-- tail flit
if vc = 1 then
address <= reserved_address_vc;
else
address <= reserved_address;
end if;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & "0000000000000000000000000000";
first_packet := False;
else
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
end if;
send_counter := 0;
state := Idle;
-- updating the id counter!
send_id_counter := send_id_counter + 1;
if send_id_counter = 16384 then
send_id_counter := 0;
end if;
end if;
end if;
frame_counter := frame_counter + 1;
if frame_counter = frame_length then
frame_counter := 0;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size)))/100);
end if;
wait until clk'event and clk ='0';
end if;
end loop;
file_close(SEND_FILE);
file_close(RECEIVED_FILE);
end NI_control;
end TB_Package;
|
gpl-3.0
|
9027cbbf32c98badf77d7eda534d3b57
| 0.543509 | 4.191781 | false | false | false | false |
cretingame/Yarr-fw
|
syn/spec/top_yarr_spec_fe65p2.vhd
| 1 | 63,118 |
--------------------------------------------
-- Project: YARR
-- Author: Timon Heim ([email protected])
-- Description: Top module for YARR on SPEC
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity yarr is
generic (
g_TX_CHANNELS : integer := 1;
g_RX_CHANNELS : integer := 1
);
port
(
-- On board 20MHz oscillator
clk20_vcxo_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n : out std_logic; -- 25MHz VCXO
pll20dac_sync_n : out std_logic; -- 20MHz VCXO
plldac_din : out std_logic;
plldac_sclk : out std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
clk_125m_pllref_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- DDR3
DDR3_CAS_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_RZQ : inout std_logic;
DDR3_ZIO : inout std_logic;
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_DQ : inout std_logic_vector(15 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
DAC_LD : out std_logic;
INJ_SW : out std_logic;
DAC_DIN : out std_logic;
DAC_CLK : out std_logic;
DAC_CS : out std_logic;
TRIGGER_P : out std_logic;
TRIGGER_N : out std_logic;
CLK_DATA_P : out std_logic;
CLK_DATA_N : out std_logic;
RST_0_P : out std_logic;
RST_0_N : out std_logic;
CLK_CNFG_P : out std_logic;
CLK_CNFG_N : out std_logic;
PIX_D_CNFG_P : out std_logic;
PIX_D_CNFG_N : out std_logic;
LD_CNFG_P : out std_logic;
LD_CNFG_N : out std_logic;
CLK_BX_P : out std_logic;
CLK_BX_N : out std_logic;
RST_1_P : out std_logic;
RST_1_N : out std_logic;
EN_PIX_SR_CNFG_P : out std_logic;
EN_PIX_SR_CNFG_N : out std_logic;
SI_CNFG_P : out std_logic;
SI_CNFG_N : out std_logic;
SO_CNFG_P : in std_logic;
SO_CNFG_N : in std_logic;
HIT_OR_P : in std_logic;
HIT_OR_N : in std_logic;
OUT_DATA_P : in std_logic;
OUT_DATA_N : in std_logic;
EXT_4_P : out std_logic;
EXT_4_N : out std_logic;
EXT_3_P : in std_logic;
EXT_3_N : in std_logic;
EXT_2_P : out std_logic;
EXT_2_N : out std_logic;
EXT_1_P : in std_logic;
EXT_1_N : in std_logic;
IO_0 : out std_logic;
IO_1 : in std_logic
);
end yarr;
architecture rtl of yarr is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
COMPONENT fe65p2_addon
PORT(
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
clk_bx_o : OUT std_logic;
trig_o : OUT std_logic;
clk_cnfg_o : OUT std_logic;
en_pix_sr_cnfg_o : OUT std_logic;
ld_cnfg_o : OUT std_logic;
si_cnfg_o : OUT std_logic;
pix_d_cnfg_o : OUT std_logic;
clk_data_o : OUT std_logic;
rst_0_o : OUT std_logic;
rst_1_o : OUT std_logic;
dac_sclk_o : OUT std_logic;
dac_sdi_o : OUT std_logic;
dac_ld_o : OUT std_logic;
dac_cs_o : OUT std_logic;
inj_sw_o : OUT std_logic
);
END COMPONENT;
component gn4124_core
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic;
csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
dma_err_i : in std_logic;
dma_rty_i : in std_logic;
dma_int_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := g_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- Async
ext_trig_i : in std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := g_RX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_dat_i : in std_logic_vector(31 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(31 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component wb_trigger_logic
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
int_trig_i : in std_logic_vector(3 downto 0);
int_trig_o : out std_logic;
int_busy_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0)
);
end component;
component ddr3_ctrl
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock, control and status
----------------------------------------------------------------------------
--! Clock input
clk_i : in std_logic;
--! Reset input (active low)
rst_n_i : in std_logic;
--! Status output
status_o : out std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 0
----------------------------------------------------------------------------
--! Command FIFO empty
p0_cmd_empty_o : out std_logic;
--! Command FIFO full
p0_cmd_full_o : out std_logic;
--! Read FIFO full
p0_rd_full_o : out std_logic;
--! Read FIFO empty
p0_rd_empty_o : out std_logic;
--! Read FIFO count
p0_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p0_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p0_rd_error_o : out std_logic;
--! Write FIFO full
p0_wr_full_o : out std_logic;
--! Write FIFO empty
p0_wr_empty_o : out std_logic;
--! Write FIFO count
p0_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p0_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p0_wr_error_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 1
----------------------------------------------------------------------------
--! Command FIFO empty
p1_cmd_empty_o : out std_logic;
--! Command FIFO full
p1_cmd_full_o : out std_logic;
--! Read FIFO full
p1_rd_full_o : out std_logic;
--! Read FIFO empty
p1_rd_empty_o : out std_logic;
--! Read FIFO count
p1_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p1_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p1_rd_error_o : out std_logic;
--! Write FIFO full
p1_wr_full_o : out std_logic;
--! Write FIFO empty
p1_wr_empty_o : out std_logic;
--! Write FIFO count
p1_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p1_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p1_wr_error_o : out std_logic
);
end component ddr3_ctrl;
component clk_gen
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component ila_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave
constant c_TX_CHANNELS : integer := g_TX_CHANNELS;
constant c_RX_CHANNELS : integer := g_RX_CHANNELS;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk : std_logic;
-- IO clocks
signal CLK_40 : std_logic;
signal CLK_80 : std_logic;
signal CLK_125 : std_logic;
signal CLK_160 : std_logic;
signal CLK_640 : std_logic;
signal CLK_40_buf : std_logic;
signal CLK_80_buf : std_logic;
signal CLK_160_buf : std_logic;
signal CLK_640_buf : std_logic;
signal ioclk_fb : std_logic;
-- System clock generation
signal sys_clk_in : std_logic;
signal sys_clk_40_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_40 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
signal locked : std_logic;
signal locked_v : std_logic_vector(1 downto 0);
signal rst_n : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0');
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal ram_we : std_logic;
-- DMAbus RX bridge
signal rx_dma_adr : std_logic_vector(31 downto 0);
signal rx_dma_dat_o : std_logic_vector(31 downto 0);
signal rx_dma_dat_i : std_logic_vector(31 downto 0);
signal rx_dma_cyc : std_logic;
signal rx_dma_stb : std_logic;
signal rx_dma_we : std_logic;
signal rx_dma_ack : std_logic;
signal rx_dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_out : std_logic;
-- CSR whisbone slaves for test
signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-- I2C
signal scl_t : std_logic;
signal sda_t : std_logic;
-- Trigger logic
signal int_busy_t : std_logic;
signal trig_tag_t : std_logic_vector(31 downto 0);
signal int_trig_t : std_logic;
signal eudet_trig_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_rst_t : std_logic;
signal eudet_busy_t : std_logic;
-- FOR TESTS
signal debug : std_logic_vector(31 downto 0);
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_k2000 : unsigned(2 downto 0);
signal led_pps : std_logic;
signal leds : std_logic_vector(3 downto 0);
-- ILA
signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal debug_dma : std_logic_vector(31 downto 0);
signal ddr_status : std_logic_vector(31 downto 0);
signal gn4124_core_Status : std_logic_vector(31 downto 0);
signal tx_data_o : std_logic_vector(0 downto 0);
signal trig_pulse : std_logic;
signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0);
signal rx_data : std_logic_vector(31 downto 0);
signal rx_valid : std_logic;
signal rx_busy : std_logic;
-- FMC
signal dac_ld_t : std_logic;
signal inj_sw_t : std_logic;
signal dac_din_t : std_logic;
signal dac_clk_t : std_logic;
signal dac_cs_t : std_logic;
signal trigger_t : std_logic;
signal clk_data_t : std_logic;
signal rst_0_t : std_logic;
signal clk_cnfg_t : std_logic;
signal pix_d_cnfg_t : std_logic;
signal ld_cnfg_t : std_logic;
signal clk_bx_t : std_logic;
signal rst_1_t : std_logic;
signal en_pix_sr_cnfg_t : std_logic;
signal si_cnfg_t : std_logic;
signal so_cnfg_t : std_logic;
signal hit_or_t : std_logic;
signal out_data_t : std_logic;
begin
-- Buffers
dac_ld <= dac_ld_t;
inj_sw <= inj_sw_t;
dac_din <= dac_din_t;
dac_clk <= dac_clk_t;
dac_cs <= dac_cs_t;
trigger_buf : OBUFDS port map (O => trigger_n, OB => trigger_p, I => not trigger_t); -- inv
clk_datar_buf : OBUFDS port map (O => clk_data_p, OB => clk_data_n, I => clk_data_t);
rst_0_buf : OBUFDS port map (O => rst_0_n, OB => rst_0_p, I => not rst_0_t); -- inv
clk_cnfg_buf : OBUFDS port map (O => clk_cnfg_n, OB => clk_cnfg_p, I => clk_cnfg_t); --inv
pix_d_cnfg_buf : OBUFDS port map (O => pix_d_cnfg_p, OB => pix_d_cnfg_n, I => pix_d_cnfg_t);
ld_cnfg_buf : OBUFDS port map (O => ld_cnfg_p, OB => ld_cnfg_n, I => ld_cnfg_t);
clk_bx_buf : OBUFDS port map (O => clk_bx_p, OB => clk_bx_n, I => clk_bx_t);
en_pix_sr_cnfg_buf : OBUFDS port map (O => en_pix_sr_cnfg_n, OB => en_pix_sr_cnfg_p, I => not en_pix_sr_cnfg_t); -- inv
rst_1_buf : OBUFDS port map (O => rst_1_n, OB => rst_1_p, I => not rst_1_t); --inv
si_cnfg_buf : OBUFDS port map (O => si_cnfg_p, OB => si_cnfg_n, I => si_cnfg_t);
eudet_clk_buf : OBUFDS port map (O => EXT_4_P, OB => EXT_4_N, I => not eudet_clk_t);
eudet_busy_buf : OBUFDS port map (O => EXT_2_P, OB => EXT_2_N, I => eudet_busy_t);
so_cnfg_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => so_cnfg_t, I => so_cnfg_p, IB => so_cnfg_n);
hit_or_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => hit_or_t, I => hit_or_p, IB => hit_or_n);
out_data_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => out_data_t, I => out_data_p, IB => out_data_n);
eudet_rst_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_rst_t, I => EXT_3_P, IB => EXT_3_N);
eudet_trig_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_trig_t, I => EXT_1_P, IB => EXT_1_N);
fe_data_i(0) <= not out_data_t;
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
IBUFGDS_gn_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DIFF_SSTL18_I"
)
port map (
O => l_clk, -- Clock buffer output
I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS_pll_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25"
)
port map (
O => CLK_125, -- Clock buffer output
I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
cmp_fe65p2_addon: fe65p2_addon PORT MAP(
clk_i => CLK_40,
rst_n => rst_n,
serial_in => fe_cmd_o(0),
clk_rx_i => CLK_40,
clk_bx_o => clk_bx_t,
trig_o => trigger_t,
clk_cnfg_o => clk_cnfg_t,
en_pix_sr_cnfg_o => en_pix_sr_cnfg_t,
ld_cnfg_o => ld_cnfg_t,
si_cnfg_o => si_cnfg_t,
pix_d_cnfg_o => pix_d_cnfg_t,
clk_data_o => clk_data_t,
rst_0_o => rst_0_t,
rst_1_o => rst_1_t,
dac_sclk_o => dac_clk_t,
dac_sdi_o => dac_din_t,
dac_ld_o => dac_ld_t,
dac_cs_o => dac_cs_t,
inj_sw_o => inj_sw_t
);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => rst_n,
status_o => gn4124_core_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_out,
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall,
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0'
);
GPIO(0) <= irq_out;
GPIO(1) <= '0';
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk,
rst_n_i => rst_n,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
------------------------------------------------------------------------------
-- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-- port map(
-- rst_n_i => rst_n,
-- wb_clk_i => sys_clk,
-- wb_addr_i => wb_adr(1 downto 0),
-- wb_data_i => wb_dat_o,
-- wb_data_o => wb_dat_i(63 downto 32),
-- wb_cyc_i => wb_cyc(1),
-- wb_sel_i => wb_sel,
-- wb_stb_i => wb_stb,
-- wb_we_i => wb_we,
-- wb_ack_o => wb_ack(1),
-- dummy_stat_reg_1_i => dummy_stat_reg_1,
-- dummy_stat_reg_2_i => dummy_stat_reg_2,
-- dummy_stat_reg_3_i => dummy_stat_reg_3,
-- dummy_stat_reg_switch_i => dummy_stat_reg_switch
-- );
cmp_wb_tx_core : wb_tx_core port map
(
-- Sys connect
wb_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
wb_stall_o => wb_stall(1),
-- TX
tx_clk_i => CLK_40,
tx_data_o => fe_cmd_o,
trig_pulse_o => trig_pulse,
ext_trig_i => int_trig_t
);
cmp_wb_rx_core: wb_rx_core PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(95 downto 64),
wb_cyc_i => wb_cyc(2),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(2),
wb_stall_o => wb_stall(2),
rx_clk_i => CLK_40,
rx_serdes_clk_i => CLK_160,
rx_data_i => fe_data_i,
rx_valid_o => rx_valid,
rx_data_o => rx_data,
trig_tag_i => trig_tag_t,
busy_o => open,
debug_o => debug
);
cmp_wb_rx_bridge : wb_rx_bridge port map (
-- Sys Connect
sys_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(127 downto 96),
wb_cyc_i => wb_cyc(3),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(3),
wb_stall_o => wb_stall(3),
-- Wishbone DMA Master Interface
dma_clk_i => sys_clk,
dma_adr_o => rx_dma_adr,
dma_dat_o => rx_dma_dat_o,
dma_dat_i => rx_dma_dat_i,
dma_cyc_o => rx_dma_cyc,
dma_stb_o => rx_dma_stb,
dma_we_o => rx_dma_we,
dma_ack_i => rx_dma_ack,
dma_stall_i => rx_dma_stall,
-- Rx Interface (sync to sys_clk)
rx_data_i => rx_data,
rx_valid_i => rx_valid,
-- Status in
trig_pulse_i => trig_pulse,
-- Status out
irq_o => open,
busy_o => rx_busy
);
wb_dat_i(159 downto 136) <= (others => '0');
cmp_i2c_master : i2c_master_wb_top
port map (
wb_clk_i => sys_clk,
wb_rst_i => not rst_n,
arst_i => rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
wb_dat_o => wb_dat_i(135 downto 128),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(4),
wb_ack_o => wb_ack(4),
wb_inta_o => open,
scl => open,
sda => open
);
cmp_wb_trigger_logic: wb_trigger_logic PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr(31 downto 0),
wb_dat_i => wb_dat_o(31 downto 0),
wb_dat_o => wb_dat_i(191 downto 160),
wb_cyc_i => wb_cyc(5),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(5),
ext_trig_i => "00" & IO_1 & not hit_or_t,
ext_trig_o => open,
ext_busy_i => '0',
ext_busy_o => IO_0,
eudet_clk_o => eudet_clk_t,
eudet_busy_o => eudet_busy_t,
eudet_trig_i => eudet_trig_t,
eudet_rst_i => eudet_rst_t,
clk_i => CLK_40,
int_trig_i => "000" & trig_pulse,
int_trig_o => int_trig_t,
int_busy_i => '0',
trig_tag => trig_tag_t
);
--wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1));
-- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2));
-- dummy_stat_reg_1 <= X"DEADBABE";
-- dummy_stat_reg_2 <= X"BEEFFACE";
-- dummy_stat_reg_3 <= X"12345678";
-- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked;
led_red_o <= dummy_ctrl_reg_led(0);
led_green_o <= dummy_ctrl_reg_led(1);
-- TRIG0(31 downto 0) <= (others => '0');
TRIG1(31 downto 0) <= (others => '0');
TRIG2(31 downto 0) <= (others => '0');
-- TRIG0(12 downto 0) <= (others => '0');
--TRIG1(31 downto 0) <= rx_dma_dat_o;
--TRIG1(31 downto 0) <= dma_dat_i;
-- TRIG1(31 downto 0) <= gn4124_core_status;
-- TRIG2(31 downto 0) <= ddr_status;
-- TRIG0(13) <= rx_dma_cyc;
-- TRIG0(14) <= rx_dma_stb;
-- TRIG0(15) <= rx_dma_we;
-- TRIG0(16) <= rx_dma_ack;
-- TRIG0(17) <= rx_dma_stall;
-- TRIG0(18) <= dma_cyc;
-- TRIG0(19) <= dma_stb;
-- TRIG0(20) <= dma_we;
-- TRIG0(21) <= dma_ack;
-- TRIG0(22) <= dma_stall;
-- TRIG0(23) <= irq_out;
-- TRIG0(24) <= rx_busy;
-- TRIG0(31 downto 25) <= (others => '0');
-- TRIG0(0) <= rx_valid;
-- TRIG0(1) <= fe_cmd_o(0);
-- TRIG0(2) <= trig_pulse;
-- TRIG0(3) <= fe_cmd_o(0);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= rx_data;
-- TRIG2 <= debug;
-- TRIG0(0) <= scl;
-- TRIG0(1) <= sda;
-- TRIG0(2) <= wb_stb;
-- TRIG0(3) <= wb_ack(4);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= wb_adr;
-- TRIG2 <= wb_dat_o;
TRIG0(14 downto 0) <= trig_tag_t(14 downto 0);
TRIG0(15) <= int_trig_t;
TRIG0(16) <= eudet_trig_t;
TRIG0(17) <= eudet_clk_t;
TRIG0(18) <= eudet_busy_t;
TRIG0(19) <= trigger_t;
TRIG0(20) <= hit_or_t;
ila_i : ila
port map (
CONTROL => CONTROL,
CLK => CLK_40,
-- CLK => sys_clk,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2);
ila_icon_i : ila_icon
port map (
CONTROL0 => CONTROL);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- FOR TEST
------------------------------------------------------------------------------
p_led_cnt : process (L_RST_N, sys_clk)
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
elsif rising_edge(sys_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(23);
end if;
end process p_led_cnt;
led_pps <= led_cnt(23) and not(led_en);
p_led_k2000 : process (sys_clk, L_RST_N)
begin
if L_RST_N = '0' then
led_k2000 <= (others => '0');
leds <= "0001";
elsif rising_edge(sys_clk) then
if led_pps = '1' then
if led_k2000(2) = '0' then
if leds /= "1000" then
leds <= leds(2 downto 0) & '0';
end if;
else
if leds /= "0001" then
leds <= '0' & leds(3 downto 1);
end if;
end if;
led_k2000 <= led_k2000 + 1;
end if;
end if;
end process p_led_k2000;
AUX_LEDS_O <= not(leds);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
rst_n <= (L_RST_N and sys_clk_pll_locked and locked);
cmp_clk_gen : clk_gen
port map (
-- Clock in ports
CLK_40_IN => sys_clk_40,
CLKFB_IN => ioclk_fb,
-- Clock out ports
CLK_640 => CLK_640_buf,
CLK_160 => CLK_160_buf,
CLK_80 => CLK_80_buf,
CLK_40 => CLK_40_buf,
CLKFB_OUT => ioclk_fb,
-- Status and control signals
RESET => not L_RST_N,
LOCKED => locked
);
BUFPLL_640 : BUFPLL
generic map (
DIVIDE => 4, -- DIVCLK divider (1-8)
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
port map (
IOCLK => CLK_640, -- 1-bit output: Output I/O clock
LOCK => open, -- 1-bit output: Synchronized LOCK output
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
GCLK => CLK_160, -- 1-bit input: BUFG clock input
LOCKED => locked, -- 1-bit input: LOCKED input from PLL
PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL
);
cmp_ioclk_160_buf : BUFG
port map (
O => CLK_160,
I => CLK_160_buf);
cmp_ioclk_80_buf : BUFG
port map (
O => CLK_80,
I => CLK_80_buf);
cmp_ioclk_40_buf : BUFG
port map (
O => CLK_40,
I => CLK_40_buf);
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 40.000 MHz IO driver clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
sys_clk <= l_clk;
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n <= '1';
pll20dac_sync_n <= '1';
plldac_din <= '0';
plldac_sclk <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_40_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_40,
I => sys_clk_40_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
cmp_ddr3_ctrl: ddr3_ctrl PORT MAP(
clk_i => ddr_clk,
rst_n_i => rst_n,
status_o => ddr_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk,
wb0_sel_i => dma_sel,
wb0_cyc_i => dma_cyc,
wb0_stb_i => dma_stb,
wb0_we_i => dma_we,
wb0_addr_i => dma_adr,
wb0_data_i => dma_dat_o,
wb0_data_o => dma_dat_i,
wb0_ack_o => dma_ack,
wb0_stall_o => dma_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => open,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk,
wb1_sel_i => "1111",
wb1_cyc_i => rx_dma_cyc,
wb1_stb_i => rx_dma_stb,
wb1_we_i => rx_dma_we,
wb1_addr_i => rx_dma_adr,
wb1_data_i => rx_dma_dat_o,
wb1_data_o => rx_dma_dat_i,
wb1_ack_o => rx_dma_ack,
wb1_stall_o => rx_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
end rtl;
|
gpl-3.0
|
7a396703e2e2eb075c8738d6b5350126
| 0.428737 | 3.70955 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/bus_ctrl.vhd
| 1 | 8,087 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : bus controler --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pack_mips.all;
entity bus_ctrl is
port
(
clock : std_logic;
reset : std_logic;
-- Interruption in the pipeline
interrupt : in std_logic;
-- Interface for the Instruction Extraction Stage
adr_from_ei : in bus32; -- The address of the data to read
instr_to_ei : out bus32; -- Instruction from the memory
-- Interface with the MEMory Stage
req_from_mem : in std_logic; -- Request to access the ram
r_w_from_mem : in std_logic; -- Read/Write request
adr_from_mem : in bus32; -- Address in ram
data_from_mem : in bus32; -- Data to write in ram
data_to_mem : out bus32; -- Data from the ram to the MEMory stage
-- RAM interface signals
req_to_ram : out std_logic; -- Request to ram
adr_to_ram : out bus32; -- Address of the data to read or write
r_w_to_ram : out std_logic; -- Read/Write request
ack_from_ram : in std_logic; -- Acknowledge from the memory
data_inout_ram : inout bus32; -- Data from/to the memory
-- Pipeline progress control signal
stop_all : out std_logic
);
end bus_ctrl;
architecture rtl of bus_ctrl is
type ctrl_state is ( ST1, ST2 );
signal cs, ns : ctrl_state;
signal ei_buffer : bus32; -- Buffer storing the data for EI
signal r_w : std_logic; -- Current utilisation of the tristate bus
signal data_in : bus32; -- Data read on the tristate bus
signal req_allowed : std_logic;
begin
-- Read/write on the tristate bus
process (r_w, data_from_mem, data_inout_ram)
begin
r_w_to_ram <= r_w;
if r_w='0' then -- Reads bus
data_inout_ram <= (others => 'Z');
data_in <= data_inout_ram;
else -- Writing of the data from the MEM stage
data_inout_ram <= data_from_mem;
data_in <= (others => '0');
end if;
end process;
process (clock)
begin
if clock='1' and clock'event then
if reset='1' then
cs <= ST1;
ei_buffer <= (others => '0');
else
if cs=ST1 then
-- Storing of the data to send to EI stage
ei_buffer <= data_in;
end if;
cs <= ns;
end if;
end if;
end process;
process (clock, ack_from_ram)
begin
if ack_from_ram = '0' then
req_allowed <= '0';
elsif clock='1' and clock'event then
if ack_from_ram = '1' then
req_allowed <= '1';
end if;
end if;
end process;
process (req_allowed, ack_from_ram)
begin
if req_allowed = '1' then
req_to_ram <= '1';
elsif ack_from_ram = '0' then
req_to_ram <= '1';
else
req_to_ram <= '0';
end if;
end process;
process (cs, interrupt, adr_from_ei, req_from_mem, r_w_from_mem, adr_from_mem, ack_from_ram)
begin
if interrupt = '1' then -- An interruption is detected
ns <= ST1; -- Get back to the reading request
stop_all <= '0'; -- The pipeline is unlock for taking in account the interruption
adr_to_ram <= adr_from_ei;
r_w <= '0';
else
case cs is
when ST1 => -- First step the reading for EI
adr_to_ram <= adr_from_ei;
r_w <= '0';
if ack_from_ram='1' then
if req_from_mem='1' then
-- If request from MEM, then step 2
ns <= ST2;
stop_all <= '1';
else
-- else next reading for EI
ns <= ST1;
stop_all <= '0';
end if;
else
-- Wait the end of the reading
ns <= ST1;
stop_all <= '1';
end if;
when ST2 => -- Treat the request from the MEM stage
adr_to_ram <= adr_from_mem;
r_w <= r_w_from_mem;
-- Wait the acknowledge from the RAM
if ack_from_ram='1' then
ns <= ST1;
stop_all <= '0';
else
ns <= ST2;
stop_all <= '1';
end if;
end case;
end if;
end process;
data_to_mem <= data_in;
instr_to_ei <= ei_buffer when cs=ST2 else data_in;
end rtl;
|
gpl-2.0
|
d80abf98e2912f7acdd06b1e11915f1b
| 0.388896 | 5.00743 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Effects/EffectFlanger.vhd
| 1 | 6,440 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.fixed_pkg.all;
-- use ieee.std_logic_arith.all;
entity EffectFlanger is
generic (
wordLength : natural := 16;
constantsWordLength : natural := 16
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
);
end entity ; -- EffectFlanger
architecture arch of EffectFlanger is
COMPONENT blk_mem_gen_Flanger
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
constant delayDuration : natural := 2;
constant decayGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.5, constantsWordLength);
constant directGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(1.0, constantsWordLength);
constant echoGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.7, constantsWordLength);
-- 2 second max delay
constant addressWidth : natural := 11;
constant addressMax : natural := 440;
signal addressOffset : natural := 0;
signal feedback : std_logic_vector(wordLength-1 downto 0);
signal directGained : std_logic_vector(wordLength-1 downto 0);
signal delayedGained : std_logic_vector(wordLength-1 downto 0);
signal delayed : std_logic_vector(wordLength-1 downto 0);
signal feedbackDirectSum : std_logic_vector(wordLength-1 downto 0);
signal writeBus : std_logic_vector(wordLength-1 downto 0);
signal readBus : std_logic_vector(wordLength-1 downto 0);
signal writeEnable : std_logic_vector(0 downto 0);
signal memoryReadAddress : std_logic_vector(addressWidth-1 downto 0);
signal memoryWriteAddress : std_logic_vector(addressWidth-1 downto 0);
type state_type is (readStart, readWait, read, writeDone);
constant waitTime : natural := 4;
type reg_type is record
state : state_type;
waitCounter : natural range 0 to waitTime;
writeAddress : unsigned(addressWidth-1 downto 0);
readAddress : unsigned(addressWidth-1 downto 0);
writeEnable : std_logic;
delayedOutput : std_logic_vector(wordLength-1 downto 0);
end record;
signal r, rin : reg_type;
begin
-- Summation
feedbackSum : entity work.AdderSat
generic map (
wordLength => wordLength
)
port map (
a => input,
b => feedback,
s => feedbackDirectSum
);
outputSum : entity work.AdderSat
generic map (
wordLength => wordLength
)
port map (
a => directGained,
b => delayedGained,
s => output
);
-- Gains
directMult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => wordLength-1,
Y_WIDTH => constantsWordLength,
Y_FRACTION => constantsWordLength-1,
S_WIDTH => wordLength,
S_FRACTION => wordLength-1
)
port map (
x => input,
y => directGain, --x"0000" ,
s => directGained
);
feedbackMult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => wordLength-1,
Y_WIDTH => constantsWordLength,
Y_FRACTION => constantsWordLength-1,
S_WIDTH => wordLength,
S_FRACTION => wordLength-1
)
port map (
x => delayed,
y => decayGain,
s => feedback
);
echoMult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => wordLength-1,
Y_WIDTH => constantsWordLength,
Y_FRACTION => constantsWordLength-1,
S_WIDTH => wordLength,
S_FRACTION => wordLength-1
)
port map (
x => delayed,
y => echoGain,
s => delayedGained
);
-- Delay
writeBus <= feedbackDirectSum;
writeEnable <= (others => r.writeEnable);
delayed <= r.delayedOutput;
memoryReadAddress <= std_logic_vector(r.readAddress);
memoryWriteAddress <= std_logic_vector(r.writeAddress);
memory: blk_mem_gen_Flanger
port map (
dina => writeBus,
wea => writeEnable,
doutb => readBus,
clka => clk,
clkb => clk,
addra => memoryWriteAddress,
addrb => memoryReadAddress
);
triangle_proc:process(clk)
variable intialValue: integer := 0;
constant minValue : integer := 0;
constant sweepLength : natural := 1000;
variable temp : integer := 0;
variable counter : integer := 0;
begin
if rising_edge(clk) then
if intialValue <= addressMax and temp = 0 then
counter := counter + 1 ;
if counter = sweepLength then -- to get a low frequency
intialValue := intialValue + 1;
counter := 0;
end if;
if intialValue = addressMax then
temp := 1;
end if;
elsif intialValue >= minValue and temp = 1 then
counter := counter + 1 ;
if counter = sweepLength then
intialValue := intialValue - 1;
counter := 0;
end if ;
if intialValue = minValue then
temp := 0;
end if;
end if;
end if;
addressOffset <= intialValue;
end process;
clk_proc : process( clk, reset )
begin
if(reset = '1') then
r.state <= readStart;
r.writeAddress <= (others => '0');
r.readAddress <= (others => '0');
r.writeEnable <= '0';
r.delayedOutput <= (others => '0');
elsif(rising_edge(clk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin, readBus, addressOffset )
variable v : reg_type;
variable readAddressInteger : integer;
begin
v := r;
v.writeEnable := '0';
readAddressInteger := to_integer(v.writeAddress)-addressOffset;
if(readAddressInteger > 0) then
v.readAddress := to_unsigned(readAddressInteger, addressWidth);
else
v.readAddress := to_unsigned(addressMax+readAddressInteger, addressWidth);
end if;
case r.state is
when readStart =>
v.state := readWait;
v.waitCounter := 0;
when readWait =>
-- Wait some cycles before reading
if(r.waitCounter >= waitTime) then
v.state := read;
else
v.waitCounter := r.waitCounter + 1;
end if;
when read =>
v.state := writeDone;
-- Write the new value
v.writeEnable := '1';
-- Result is ready, read it.
v.delayedOutput := readBus;
when writeDone =>
v.state := readStart;
if(r.writeAddress = addressMax) then
v.writeAddress := (others => '0');
else
v.writeAddress := v.writeAddress + 1;
end if;
when others =>
-- Don't care
end case;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
0ce413448f4aaee91a6f98fb4d6909fc
| 0.665062 | 3.292434 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd
| 4 | 47,995 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb3_dram_reset_n,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
gpl-3.0
|
1eddaa6ad2eb008d77a0992ac7ae17f9
| 0.425919 | 3.495121 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
stat_calc.vhd
| 1 | 1,653 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity stat_calc is
port (Time64 : in std_logic_vector (63 downto 0);
Delay : in std_logic_vector (31 downto 0);
Value : in std_logic_vector (63 downto 0);
KickIn : in std_logic;
Output : out std_logic_vector (63 downto 0);
KickOut : out std_logic;
Underflow : out std_logic);
end stat_calc;
architecture Behavioral of stat_calc is
signal valuePlusDelay : std_logic_vector (63 downto 0);
signal subResult : std_logic_vector(64 downto 0);
signal noUnderflow : std_logic;
begin
valuePlusDelay <= Value + Delay;
subResult <= ('1' & Time64) - ('0' & valuePlusDelay);
noUnderflow <= subResult(64);
Output <= subResult(63 downto 0);
KickOut <= KickIn and noUnderflow;
Underflow <= KickIn and not noUnderflow;
end Behavioral;
|
gpl-3.0
|
8a410aa6278c91584107e3734070d669
| 0.68542 | 3.731377 | false | false | false | false |
starsheriff/papilio-one250
|
uart_3/main.vhd
| 1 | 1,595 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
switches : in STD_LOGIC_VECTOR(7 downto 0);
leds : out STD_LOGIC_VECTOR(7 downto 0);
JOY_PUSH : in STD_LOGIC
);
end serial_transmitter;
architecture Behavioral of serial_transmitter is
signal data_shiftreg : std_logic_vector(9 downto 0) := (others => '1');
signal busy_shiftreg : std_logic_vector(9 downto 0) := (others => '0');
signal counter : std_logic_vector(12 downto 0) := (others => '0');
signal data_byte : std_logic_vector(7 downto 0) := (others => '1');
signal send : std_logic := '0';
begin
data_out <= data_shiftreg(0);
--debug_out <= shiftreg(0);
leds <= switches;
data_byte <= switches;
send <= not JOY_PUSH;
process(clk)
begin
if rising_edge(clk) then
if (busy_shiftreg(0) = '0') and (send='1') then
-- least significant bit is 0 indicating that the line is free
-- now set the whole shiftregister to 1, indicating that the line is busy
busy_shiftreg <= (others => '1');
data_shiftreg <= '1' & data_byte & '0';
counter <= (others => '0');
else
if counter=3332 then
data_shiftreg <= '1' & data_shiftreg(9 downto 1);
busy_shiftreg <= '0' & busy_shiftreg(9 downto 1);
counter <= (others => '0');
else
counter <= counter + 1;
end if; -- counter
end if; -- rising_edge
end if;
end process;
end Behavioral;
|
gpl-2.0
|
4f226b0fbf3d58c5c9a9f41dea088b8e
| 0.602508 | 3.520971 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/syscop.vhd
| 1 | 9,460 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Coprocessor system (cop0) --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
-- By convention in the commentary, the term interruption means hardware interruptions and software exceptions
entity syscop is
port
(
clock : in std_logic;
reset : in std_logic;
-- Datas from the pipeline
MEM_adr : in bus32; -- Address of the current instruction in the pipeline end -> responsible of the exception
MEM_exc_cause : in bus32; -- Potential cause exception of that instruction
MEM_it_ok : in std_logic; -- Allow hardware interruptions
-- Hardware interruption
it_mat : in std_logic; -- Hardware interruption detected
-- Interruption controls
interrupt : out std_logic; -- Interruption to take into account
vecteur_it : out bus32; -- Interruption vector
-- Writing request in register bank
write_data : in bus32; -- Data to write
write_adr : in bus5; -- Address of the register to write
write_SCP : in std_logic; -- Writing request
-- Reading request in register bank
read_adr1 : in bus5; -- Address of the first register
read_adr2 : in bus5; -- Address of the second register
read_data1 : out bus32; -- Value of register 1
read_data2 : out bus32 -- Value of register 2
);
end syscop;
architecture rtl of syscop is
subtype adr_scp_reg is integer range 12 to 15;
type scp_reg_type is array (integer range adr_scp_reg'low to adr_scp_reg'high) of bus32;
-- Constants to define the coprocessor registers
constant COMMAND : integer := 0; -- False register to command the coprocessor system
constant STATUS : adr_scp_reg := 12; -- Registre 12 of the coprocessor system
constant CAUSE : adr_scp_reg := 13; -- Registre 13 of the coprocessor system
constant ADRESSE : adr_scp_reg := 14; -- Registre 14 of the coprocessor system
constant VECTIT : adr_scp_reg := 15; -- Registre 15 of the coprocessor system
signal scp_reg : scp_reg_type; -- Internal register bank
signal pre_reg : scp_reg_type; -- Register bank preparation
signal adr_src1 : integer range 0 to 31;
signal adr_src2 : integer range 0 to 31;
signal adr_dest : integer range 0 to 31;
signal exception : std_logic; -- Set to '1' when exception detected
signal interruption : std_logic; -- Set to '1' when interruption detected
signal cmd_itret : std_logic; -- Set to '1' when interruption return command is detected
signal save_msk : std_logic; -- Save the mask state when an interruption occurs
begin
-- Detection of the interruptions
exception <= '1' when MEM_exc_cause/=IT_NOEXC else '0';
interruption <= '1' when it_mat='1' and scp_reg(STATUS)(0)='1' and MEM_it_ok='1' else '0';
-- Update asynchronous outputs
interrupt <= exception or interruption; -- Detection of interruptions
vecteur_it <= scp_reg(ADRESSE) when cmd_itret = '1' else -- Send the return adress when a return instruction appears
scp_reg(VECTIT); -- Send the interruption vector in other cases
-- Decode the address of the registers
adr_src1 <= to_integer(unsigned(read_adr1));
adr_src2 <= to_integer(unsigned(read_adr2));
adr_dest <= to_integer(unsigned(write_adr));
-- Read the two registers
read_data1 <= (others => '0') when (adr_src1<scp_reg'low or adr_src1>scp_reg'high) else
scp_reg(adr_src1);
read_data2 <= (others => '0') when adr_src2<scp_reg'low or adr_src2>scp_reg'high else
scp_reg(adr_src2);
-- Define the pre_reg signal, next value for the registers
process (scp_reg, adr_dest, write_SCP, write_data, interruption,
exception, MEM_exc_cause, MEM_adr, reset)
begin
pre_reg <= scp_reg;
cmd_itret <= '0'; -- No IT return in most cases
-- Potential writing in a register
if (write_SCP='1' and adr_dest>=pre_reg'low and adr_dest<=pre_reg'high) then
pre_reg(adr_dest) <= write_data;
end if;
-- Command from the core
if write_SCP='1' and adr_dest=COMMAND then
case write_data is -- Different operations
when SYS_UNMASK => pre_reg(STATUS)(0) <= '1'; -- Unamsk command
when SYS_MASK => pre_reg(STATUS)(0) <= '0'; -- Mask command
when SYS_ITRET => -- Interruption return command
pre_reg(STATUS)(0) <= save_msk; -- Restore the mask before the interruption
cmd_itret <= '1'; -- False interruption request (to clear the pipeline)
when others => null;
end case;
end if;
-- Modifications from the interruptions
if interruption='1' then
pre_reg(STATUS)(0) <= '0'; -- Mask the interruptions
pre_reg(CAUSE) <= IT_ITMAT; -- Save the interruption cause
pre_reg(ADRESSE) <= MEM_adr; -- Save the return address
end if;
-- Modifications from the exceptions
if exception='1' then
pre_reg(STATUS)(0) <= '0'; -- Mask the interruptions
pre_reg(CAUSE) <= MEM_exc_cause; -- Save the exception cause
pre_reg(ADRESSE) <= MEM_adr; -- Save the return address
end if;
-- The reset has the priority on the other cuases
if reset='1' then
pre_reg <= (others => (others => '0'));
-- NB : The processor is masked after a reset
-- The exception handler is set at address 0
end if;
end process;
-- Memorisation of the modifications in the register bank
process(clock)
begin
if clock='1' and clock'event then
-- Save the mask when an interruption appears
if (exception='1') or (interruption='1') then
save_msk <= scp_reg(STATUS)(0);
end if;
scp_reg <= pre_reg;
end if;
end process;
end rtl;
|
gpl-2.0
|
dd5ce3366e6c00c13dec94c2f56c52ed
| 0.484038 | 4.881321 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/transmitter.vhd
| 3 | 4,675 |
----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
constant BITLENGTH : integer := FREQ / RATE;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
574aef3404ace095acee8dd8c6dc00ef
| 0.590374 | 3.50976 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Utilities/VectorRegister.vhd
| 2 | 706 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity VectorRegister is
generic (
wordLength : natural := 8
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- VectorRegister
architecture arch of VectorRegister is
signal delayedSignal : std_logic_vector(wordLength-1 downto 0);
begin
output <= delayedSignal;
clk_proc : process( clk, reset )
begin
if(reset = '1') then
delayedSignal <= (others => '0');
elsif(rising_edge(clk)) then
delayedSignal <= input;
end if;
end process ; -- clk_proc
end architecture ; -- arch
|
mit
|
4a86563621736358160a61b09595e629
| 0.685552 | 3.209091 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_bus_append.vhd
| 1 | 2,823 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_bus_append IS
END tb_bus_append;
ARCHITECTURE behavior OF tb_bus_append IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bus_append
GENERIC ( N_BYTES : integer );
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Value : in STD_LOGIC_VECTOR (N_BYTES*8 - 1 downto 0);
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal Cnt64 : std_logic_vector(63 downto 0) := (others => '0');
signal InPkt : std_logic := '0';
signal InData : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OutPkt : std_logic;
signal OutData : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bus_append
GENERIC MAP ( N_BYTES => 8 )
PORT MAP (
Clk => Clk,
Rst => Rst,
Value => Cnt64,
InPkt => InPkt,
InData => InData,
OutPkt => OutPkt,
OutData => OutData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
Cnt64_process :process
begin
wait for Clk_period;
Cnt64 <= Cnt64 + 1;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
InPkt <= '1';
for i in 0 to 6 loop
InData <= X"55";
wait for Clk_period;
end loop;
InData <= X"d5";
wait for Clk_period;
for i in 0 to 63 loop
InData <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
-- InData <= x"00";
-- wait for Clk_period;
InPkt <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
fc9b45d348c3718085967e58663e5876
| 0.628055 | 3.388956 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Arithmetic/AdderSat.vhd
| 1 | 1,253 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AdderSat is
generic (
wordLength : natural := 12
);
port (
a : in std_logic_vector(wordLength-1 downto 0);
b : in std_logic_vector(wordLength-1 downto 0);
s : out std_logic_vector(wordLength-1 downto 0)
);
end entity ; -- AdderSat
architecture arch of AdderSat is
constant MAX : std_logic_vector(wordLength-1 downto 0) := '0' & (wordLength-2 downto 0 => '1');
constant MIN : std_logic_vector(wordLength-1 downto 0) := '1' & (wordLength-2 downto 0 => '0');
signal sum : std_logic_vector(wordLength-1 downto 0);
signal overflow : std_logic;
signal s_a : std_logic;
signal s_b : std_logic;
signal s_s : std_logic;
begin
sum <= std_logic_vector(signed(a) + signed(b));
s_a <= a(wordLength-1);
s_b <= b(wordLength-1);
s_s <= sum(wordLength-1);
-- Signs of a and b are the same, but not equal to sign of s means overflow.
overflow <= ((s_a and s_b) and not(s_s)) or ((not(s_a) and not(s_b)) and s_s);
s <= sum when overflow = '0' else -- No overflow
MAX when s_a = '0' else -- Overflow positive
MIN when s_a = '1' else -- Overflow negative
(others => '-'); -- Don't care (Required to remove latch).
end architecture ; -- arch
|
mit
|
2b7ec6123dab792be4283066e06a4239
| 0.646449 | 2.873853 | false | false | false | false |
cretingame/Yarr-fw
|
syn/xpressk7/bram_revA/top_level.vhd
| 1 | 18,986 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/27/2016 04:46:45 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_level is
Port ( ---------------------------------------------------------------------------
-- Xilinx Hard IP Interface
-- . Clock and Resets
pcie_clk_p : in std_logic;
pcie_clk_n : in std_logic;
clk200_n : in STD_LOGIC;
clk200_p : in STD_LOGIC;
rst_n_i : in STD_LOGIC;
sys_rst_n_i : in STD_LOGIC;
-- . Serial I/F
pci_exp_txn : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txn ,
pci_exp_txp : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txp ,
pci_exp_rxn : in std_logic_vector(4-1 downto 0);--input wire [4 -1:0] pci_exp_rxn ,
pci_exp_rxp : in std_logic_vector(4-1 downto 0);
-- . IO
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (2 downto 0);
--front_led_o : out STD_LOGIC_VECTOR (3 downto 0);
-- . DDR3
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
--init_calib_complete : out std_logic;
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end top_level;
architecture Behavioral of top_level is
constant AXI_BUS_WIDTH : integer := 64;
component simple_counter is
Port (
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
COMPONENT pcie_7x_0
PORT (
pci_exp_txp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_txn : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
user_clk_out : OUT STD_LOGIC;
user_reset_out : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
user_app_rdy : OUT STD_LOGIC;
tx_buf_av : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_cfg_req : OUT STD_LOGIC;
tx_err_drop : OUT STD_LOGIC;
s_axis_tx_tready : OUT STD_LOGIC;
s_axis_tx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tx_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tx_tlast : IN STD_LOGIC;
s_axis_tx_tvalid : IN STD_LOGIC;
s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rx_tlast : OUT STD_LOGIC;
m_axis_rx_tvalid : OUT STD_LOGIC;
m_axis_rx_tready : IN STD_LOGIC;
m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
cfg_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_command : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_pcie_link_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_pmcsr_pme_en : OUT STD_LOGIC;
cfg_pmcsr_powerstate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pmcsr_pme_status : OUT STD_LOGIC;
cfg_received_func_lvl_rst : OUT STD_LOGIC;
cfg_interrupt : IN STD_LOGIC;
cfg_interrupt_rdy : OUT STD_LOGIC;
cfg_interrupt_assert : IN STD_LOGIC;
cfg_interrupt_di : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable : OUT STD_LOGIC;
cfg_interrupt_msixenable : OUT STD_LOGIC;
cfg_interrupt_msixfm : OUT STD_LOGIC;
cfg_interrupt_stat : IN STD_LOGIC;
cfg_pciecap_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_to_turnoff : OUT STD_LOGIC;
cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_bridge_serr_en : OUT STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : OUT STD_LOGIC;
cfg_root_control_syserr_corr_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_pme_int_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : OUT STD_LOGIC;
cfg_msg_received_err_cor : OUT STD_LOGIC;
cfg_msg_received_err_non_fatal : OUT STD_LOGIC;
cfg_msg_received_err_fatal : OUT STD_LOGIC;
cfg_msg_received_pm_as_nak : OUT STD_LOGIC;
cfg_msg_received_pm_pme : OUT STD_LOGIC;
cfg_msg_received_pme_to_ack : OUT STD_LOGIC;
cfg_msg_received_assert_int_a : OUT STD_LOGIC;
cfg_msg_received_assert_int_b : OUT STD_LOGIC;
cfg_msg_received_assert_int_c : OUT STD_LOGIC;
cfg_msg_received_assert_int_d : OUT STD_LOGIC;
cfg_msg_received_deassert_int_a : OUT STD_LOGIC;
cfg_msg_received_deassert_int_b : OUT STD_LOGIC;
cfg_msg_received_deassert_int_c : OUT STD_LOGIC;
cfg_msg_received_deassert_int_d : OUT STD_LOGIC;
cfg_msg_received_setslotpowerlimit : OUT STD_LOGIC;
cfg_vc_tcvc_map : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_rst_n : IN STD_LOGIC
);
END COMPONENT;
component app is
Generic(
AXI_BUS_WIDTH : integer := 64;
DMA_MEMORY_SELECTED : string := "DDR3"
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i : in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
--Clocks
signal sys_clk : STD_LOGIC;
--signal clk200 : STD_LOGIC;
signal aclk : STD_LOGIC;
signal arstn_s : STD_LOGIC;
signal rst_s : STD_LOGIC;
--Wishbone bus
signal usr_led_s : std_logic_vector(3 downto 0);
--signal count_s : STD_LOGIC_VECTOR (28 downto 0);
-- AXI-stream bus to PCIE
signal s_axis_tx_tready_s : STD_LOGIC;
signal s_axis_tx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal s_axis_tx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal s_axis_tx_tlast_s : STD_LOGIC;
signal s_axis_tx_tvalid_s : STD_LOGIC;
signal s_axis_tx_tuser_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal m_axis_rx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal m_axis_rx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal m_axis_rx_tlast_s : STD_LOGIC;
signal m_axis_rx_tvalid_s : STD_LOGIC;
signal m_axis_rx_tready_s : STD_LOGIC;
signal m_axis_rx_tuser_s : STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIE signals
signal user_lnk_up_s : STD_LOGIC;
signal user_app_rdy_s : STD_LOGIC;
signal tx_err_drop_s : STD_LOGIC;
signal cfg_interrupt_s : STD_LOGIC;
signal cfg_interrupt_rdy_s : STD_LOGIC;
signal cfg_interrupt_assert_s : STD_LOGIC;
signal cfg_interrupt_di_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_do_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_mmenable_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal cfg_interrupt_msienable_s : STD_LOGIC;
signal cfg_interrupt_msixenable_s : STD_LOGIC;
signal cfg_interrupt_msixfm_s : STD_LOGIC;
signal cfg_interrupt_stat_s : STD_LOGIC;
signal cfg_pciecap_interrupt_msgnum_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIE ID
signal cfg_bus_number_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_device_number_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal cfg_function_number_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
--PCIE debug
signal cfg_dstatus_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
-- LVDS input to internal single
-- CLK_IBUFDS : IBUFDS
-- generic map(
-- IOSTANDARD => "DEFAULT"
-- )
-- port map(
-- I => clk200_p,
-- IB => clk200_n,
-- O => clk200
-- );
-- design_1_0: component design_1
-- port map (
-- CLK_IN_D_clk_n(0) => pcie_clk_n,
-- CLK_IN_D_clk_p(0) => pcie_clk_p,
-- IBUF_OUT(0) => sys_clk
-- );
refclk_ibuf : IBUFDS_GTE2
port map(
O => sys_clk,
ODIV2 => open,
I => pcie_clk_p,
IB => pcie_clk_n,
CEB => '0');
rst_s <= not rst_n_i;
arstn_s <= sys_rst_n_i or rst_n_i;
pcie_0 : pcie_7x_0
PORT MAP (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
user_clk_out => aclk,
user_reset_out => open, -- TODO
user_lnk_up => user_lnk_up_s,
user_app_rdy => user_app_rdy_s,
tx_err_drop => tx_err_drop_s,
s_axis_tx_tready => s_axis_tx_tready_s,
s_axis_tx_tdata => s_axis_tx_tdata_s,
s_axis_tx_tkeep => s_axis_tx_tkeep_s,
s_axis_tx_tlast => s_axis_tx_tlast_s,
s_axis_tx_tvalid => s_axis_tx_tvalid_s,
s_axis_tx_tuser => s_axis_tx_tuser_s,
m_axis_rx_tdata => m_axis_rx_tdata_s,
m_axis_rx_tkeep => m_axis_rx_tkeep_s,
m_axis_rx_tlast => m_axis_rx_tlast_s,
m_axis_rx_tvalid => m_axis_rx_tvalid_s,
m_axis_rx_tready => m_axis_rx_tready_s,
m_axis_rx_tuser => m_axis_rx_tuser_s,
cfg_interrupt => cfg_interrupt_s,
cfg_interrupt_rdy => cfg_interrupt_rdy_s,
cfg_interrupt_assert => cfg_interrupt_assert_s,
cfg_interrupt_di => cfg_interrupt_di_s,
cfg_interrupt_do => cfg_interrupt_do_s,
cfg_interrupt_mmenable => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm => cfg_interrupt_msixfm_s,
cfg_interrupt_stat => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum_s,
cfg_dstatus => cfg_dstatus_s,
cfg_bus_number => cfg_bus_number_s,
cfg_device_number => cfg_device_number_s,
cfg_function_number => cfg_function_number_s,
sys_clk => sys_clk,
sys_rst_n => sys_rst_n_i
);
app_0:app
generic map(
AXI_BUS_WIDTH => 64,
DMA_MEMORY_SELECTED => "BRAM"
)
port map(
clk_i => aclk,
sys_clk_n_i => clk200_n,
sys_clk_p_i => clk200_p,
rst_i => rst_s,
user_lnk_up_i => user_lnk_up_s,
user_app_rdy_i => user_app_rdy_s,
-- AXI-Stream bus
m_axis_tx_tready_i => s_axis_tx_tready_s,
m_axis_tx_tdata_o => s_axis_tx_tdata_s,
m_axis_tx_tkeep_o => s_axis_tx_tkeep_s,
m_axis_tx_tlast_o => s_axis_tx_tlast_s,
m_axis_tx_tvalid_o => s_axis_tx_tvalid_s,
m_axis_tx_tuser_o => s_axis_tx_tuser_s,
s_axis_rx_tdata_i => m_axis_rx_tdata_s,
s_axis_rx_tkeep_i => m_axis_rx_tkeep_s,
s_axis_rx_tlast_i => m_axis_rx_tlast_s,
s_axis_rx_tvalid_i => m_axis_rx_tvalid_s,
s_axis_rx_tready_o => m_axis_rx_tready_s,
s_axis_rx_tuser_i => m_axis_rx_tuser_s,
-- PCIe interrupt config
cfg_interrupt_o => cfg_interrupt_s,
cfg_interrupt_rdy_i => cfg_interrupt_rdy_s,
cfg_interrupt_assert_o => cfg_interrupt_assert_s,
cfg_interrupt_di_o => cfg_interrupt_di_s,
cfg_interrupt_do_i => cfg_interrupt_do_s,
cfg_interrupt_mmenable_i => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable_i => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable_i => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm_i => cfg_interrupt_msixfm_s,
cfg_interrupt_stat_o => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum_o => cfg_pciecap_interrupt_msgnum_s,
-- PCIe ID
cfg_bus_number_i => cfg_bus_number_s,
cfg_device_number_i => cfg_device_number_s,
cfg_function_number_i => cfg_function_number_s,
-- PCIe debug
tx_err_drop_i => tx_err_drop_s,
cfg_dstatus_i => cfg_dstatus_s,
--DDR3
ddr3_dq_io => ddr3_dq,
ddr3_dqs_p_io => ddr3_dqs_p,
ddr3_dqs_n_io => ddr3_dqs_n,
--init_calib_complete_o => init_calib_complete,
ddr3_addr_o => ddr3_addr,
ddr3_ba_o => ddr3_ba,
ddr3_ras_n_o => ddr3_ras_n,
ddr3_cas_n_o => ddr3_cas_n,
ddr3_we_n_o => ddr3_we_n,
ddr3_reset_n_o => ddr3_reset_n,
ddr3_ck_p_o => ddr3_ck_p,
ddr3_ck_n_o => ddr3_ck_n,
ddr3_cke_o => ddr3_cke,
ddr3_cs_n_o => ddr3_cs_n,
ddr3_dm_o => ddr3_dm,
ddr3_odt_o => ddr3_odt,
--I/O
usr_sw_i => usr_sw_i,
usr_led_o => usr_led_s,
front_led_o => open--front_led_o
);
usr_led_o <= usr_led_s(2 downto 0);
--m_axis_rx_tready_s <= '1';
end Behavioral;
|
gpl-3.0
|
0d294345f2ec0a9aaf4a31a05686ed2b
| 0.539187 | 3.270065 | false | false | false | false |
openttp/openttp
|
software/system/src/fpga/vhdl/Triggers.vhd
| 1 | 1,964 |
----------------------------------------------------------------------------------
--
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Michael J. Wouters
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OneShot is
Port ( trigger : in STD_LOGIC;
clk : in STD_LOGIC;
pulse : out STD_LOGIC);
end OneShot;
architecture Behavioral of OneShot is
signal QA: std_logic := '0';
signal QB: std_logic := '0';
begin
pulse <= QB;
process (trigger, QB)
begin
if QB='1' then
QA <= '0';
elsif (rising_edge(trigger)) then
QA <= '1';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
QB <= QA;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package TRIGGERS is
component OneShot is port (
trigger : in STD_LOGIC;
clk : in STD_LOGIC;
pulse : out STD_LOGIC);
end component;
end TRIGGERS;
|
mit
|
bc76e35c11b3061928e787dc092dd1e1
| 0.683299 | 3.798839 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/uart/uart.vhd
| 1 | 18,734 |
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART is
Generic (
BAUD_RATE : integer := 115200; -- baud rate value
DATA_BITS : integer := 8; -- legal values: 5,6,7,8
PARITY_BIT : string := "none"; -- legal values: "none", "even", "odd", "mark", "space"
--STOP_BITS : integer; -- TODO, now must be 1 stop bit
CLK_FREQ : integer := 50e6; -- set system clock frequency in Hz
INPUT_FIFO : boolean := False; -- enable input data FIFO
FIFO_DEPTH : integer := 256 -- set depth of input data FIFO
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART RS232 INTERFACE
TX_UART : out std_logic;
RX_UART : in std_logic;
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(DATA_BITS-1 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic; -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(DATA_BITS-1 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
);
end UART;
architecture FULL of UART is
constant divider_value : integer := CLK_FREQ/(16*BAUD_RATE);
signal tx_clk_en : std_logic;
signal tx_ticks : integer range 0 to 15;
signal tx_data : std_logic_vector(DATA_BITS-1 downto 0);
signal tx_bit_count : integer range 0 to DATA_BITS-1;
signal tx_bit_count_en : std_logic;
signal tx_bit_count_rst : std_logic;
signal tx_busy : std_logic;
signal tx_data_in : std_logic_vector(DATA_BITS-1 downto 0);
signal tx_data_send : std_logic;
signal tx_parity_bit : std_logic;
signal uart_ticks : integer range 0 to divider_value-1;
signal uart_clk_en : std_logic;
signal fifo_in_rd : std_logic;
signal fifo_in_empty : std_logic;
signal rx_clk_en : std_logic;
signal rx_ticks : integer range 0 to 15;
signal rx_clk_divider_en : std_logic;
signal rx_data : std_logic_vector(DATA_BITS-1 downto 0);
signal rx_bit_count : integer range 0 to DATA_BITS-1;
signal rx_bit_count_en : std_logic;
signal rx_bit_count_rst : std_logic;
signal rx_data_shreg_en : std_logic;
signal rx_parity_bit : std_logic;
signal rx_parity_error : std_logic := '0';
signal rx_parity_check_en : std_logic;
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
signal rx_pstate : state;
signal rx_nstate : state;
begin
-- -------------------------------------------------------------------------
-- UART INPUT DATA FIFO
-- -------------------------------------------------------------------------
data_in_fifo_g : if (INPUT_FIFO = True) generate
data_in_fifo_i: entity work.UART_FIFO
generic map (
DATA_WIDTH => DATA_BITS,
FIFO_DEPTH => FIFO_DEPTH
)
port map (
CLK => CLK,
RST => RST,
-- FIFO WRITE INTERFACE
DATA_IN => DATA_IN,
WR_EN => DATA_SEND,
FULL => BUSY,
-- FIFO READ INTERFACE
DATA_OUT => tx_data_in,
DATA_VLD => tx_data_send,
RD_EN => fifo_in_rd,
EMPTY => fifo_in_empty
);
fifo_in_rd <= fifo_in_empty NOR tx_busy;
end generate;
no_data_in_fifo_g : if (INPUT_FIFO = False) generate
tx_data_in <= DATA_IN;
tx_data_send <= DATA_SEND;
BUSY <= tx_busy;
end generate;
-- -------------------------------------------------------------------------
-- UART CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_ticks <= 0;
uart_clk_en <= '0';
elsif (uart_ticks = divider_value-1) then
uart_ticks <= 0;
uart_clk_en <= '1';
else
uart_ticks <= uart_ticks + 1;
uart_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER
-- -------------------------------------------------------------------------
tx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_ticks <= 0;
tx_clk_en <= '0';
elsif (uart_clk_en = '1') then
if (tx_ticks = 15) then
tx_ticks <= 0;
tx_clk_en <= '1';
else
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '0';
end if;
else
tx_ticks <= tx_ticks;
tx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
input_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_data <= (others => '0');
elsif (tx_data_send = '1' AND tx_busy = '0') then
tx_data <= tx_data_in;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
tx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (tx_bit_count_rst = '1') then
tx_bit_count <= 0;
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = DATA_BITS-1) then
tx_bit_count <= 0;
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
tx_parity_g : if (PARITY_BIT /= "none") generate
tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => DATA_BITS,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
tx_pstate_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, tx_data_send, tx_clk_en, tx_data, tx_bit_count, tx_parity_bit)
begin
case tx_pstate is
when idle =>
tx_busy <= '0';
TX_UART <= '1';
tx_bit_count_rst <= '1';
tx_bit_count_en <= '0';
if (tx_data_send = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_busy <= '1';
TX_UART <= '1';
tx_bit_count_rst <= '1';
tx_bit_count_en <= '0';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_busy <= '1';
TX_UART <= '0';
tx_bit_count_rst <= '0';
tx_bit_count_en <= '0';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_busy <= '1';
TX_UART <= tx_data(tx_bit_count);
tx_bit_count_rst <= '0';
tx_bit_count_en <= '1';
if ((tx_clk_en = '1') AND (tx_bit_count = DATA_BITS-1)) then
if (PARITY_BIT = "none") then
tx_nstate <= idle;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_busy <= '1';
TX_UART <= tx_parity_bit;
tx_bit_count_rst <= '1';
tx_bit_count_en <= '0';
if (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= paritybit;
end if;
when others =>
tx_busy <= '1';
TX_UART <= '1';
tx_bit_count_rst <= '1';
tx_bit_count_en <= '0';
tx_nstate <= idle;
end case;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER CLOCK DIVIDER
-- -------------------------------------------------------------------------
rx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (rx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (rx_ticks = 15) then
rx_ticks <= 0;
rx_clk_en <= '0';
elsif (rx_ticks = 7) then
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '1';
else
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '0';
end if;
else
rx_ticks <= rx_ticks;
rx_clk_en <= '0';
end if;
else
rx_ticks <= 0;
rx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER BIT COUNTER
-- -------------------------------------------------------------------------
rx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (rx_bit_count_rst = '1') then
rx_bit_count <= 0;
elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
if (rx_bit_count = DATA_BITS-1) then
rx_bit_count <= 0;
else
rx_bit_count <= rx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER DATA SHIFT REGISTER
-- -------------------------------------------------------------------------
rx_data_shift_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_data <= (others => '0');
elsif (rx_clk_en = '1' AND rx_data_shreg_en = '1') then
rx_data <= RX_UART & rx_data(7 downto 1);
end if;
end if;
end process;
DATA_OUT <= rx_data;
-- -------------------------------------------------------------------------
-- UART RECEIVER PARITY GENERATOR AND CHECK
-- -------------------------------------------------------------------------
rx_parity_g : if (PARITY_BIT /= "none") generate
rx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => DATA_BITS,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => rx_data,
PARITY_OUT => rx_parity_bit
);
rx_parity_check_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_parity_error <= '0';
elsif (rx_parity_check_en = '1') then
rx_parity_error <= rx_parity_bit XOR RX_UART;
end if;
end if;
end process;
end generate;
-- -------------------------------------------------------------------------
-- UART RECEIVER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_pstate <= idle;
else
rx_pstate <= rx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (rx_pstate, RX_UART, rx_clk_en, rx_bit_count, rx_parity_error)
begin
case rx_pstate is
when idle =>
DATA_VLD <= '0';
FRAME_ERROR <= '0';
rx_bit_count_rst <= '1';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
if (RX_UART = '0') then
rx_nstate <= startbit;
else
rx_nstate <= idle;
end if;
when startbit =>
DATA_VLD <= '0';
FRAME_ERROR <= '0';
rx_bit_count_rst <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= databits;
else
rx_nstate <= startbit;
end if;
when databits =>
DATA_VLD <= '0';
FRAME_ERROR <= '0';
rx_bit_count_rst <= '0';
rx_bit_count_en <= '1';
rx_data_shreg_en <= '1';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if ((rx_clk_en = '1') AND (rx_bit_count = DATA_BITS-1)) then
if (PARITY_BIT = "none") then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if ;
else
rx_nstate <= databits;
end if;
when paritybit =>
DATA_VLD <= '0';
FRAME_ERROR <= '0';
rx_bit_count_rst <= '1';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
if (rx_clk_en = '1') then
rx_nstate <= stopbit;
rx_parity_check_en <= '1';
else
rx_nstate <= paritybit;
rx_parity_check_en <= '0';
end if;
when stopbit =>
rx_bit_count_rst <= '1';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= idle;
DATA_VLD <= NOT rx_parity_error;
FRAME_ERROR <= NOT RX_UART;
else
rx_nstate <= stopbit;
DATA_VLD <= '0';
FRAME_ERROR <= '0';
end if;
when others =>
DATA_VLD <= '0';
FRAME_ERROR <= '0';
rx_bit_count_rst <= '1';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
rx_nstate <= idle;
end case;
end process;
end FULL;
|
mit
|
2dbeb48f40294fc6a3a9f3f79983d5b9
| 0.393296 | 4.503365 | false | false | false | false |
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