repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
blutsvente/MIX
|
test/results/sigport/verilog/ent_t-rtl-a.vhd
| 1 | 5,101 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
-- Generated Generics for Entity ent_b
-- End of Generated Generics for Entity ent_b
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic;
port_b_5_2 : in std_ulogic;
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
6f6da79924d61a7e648a00e883c59ce3
| 0.61537 | 2.796601 | false | false | false | false |
mitchsm/nvc
|
test/regress/jcore3.vhd
| 3 | 437 |
entity jcore3 is
end entity;
architecture test of jcore3 is
signal x, y : integer;
begin
a: process (x, y) is
variable count : integer := 0;
begin
report "wakeup";
count := count + 1;
assert count <= 2;
end process;
b: process is
begin
x <= 1;
wait;
end process;
c: process is
begin
y <= 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
14c432d83cdaeb29a388c71de260be09
| 0.524027 | 3.901786 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare0.vhd
| 1 | 4,464 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (16 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (16 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(16 DOWNTO 0) <= "01000110010100000";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 17
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "36000"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "17"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 17 0 INPUT NODEFVAL "dataa[16..0]"
-- Retrieval info: CONNECT: @dataa 0 0 17 0 dataa 0 0 17 0
-- Retrieval info: CONNECT: @datab 0 0 17 0 36000 0 0 17 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
b7459bb3e6891d19bb5674eaccaeba1e
| 0.657482 | 3.710723 | false | false | false | false |
blutsvente/MIX
|
test/results/constant/inst_ae_e-rtl-a.vhd
| 1 | 2,474 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ae_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ae_e-rtl-a.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_ae_e-rtl-a.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ae_e
--
architecture rtl of inst_ae_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aea_e
bus20040728_altop_i : in std_ulogic_vector(7 downto 0);
bus20040728_top_i : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_aea_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal bus20040728_altop : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal bus20040728_top : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
bus20040728_altop <= bus20040728_altop_i; -- __I_I_BUS_PORT
--!wig: ERROR: bus20040728_top(7 downto 4) <= p_mix_bus20040728_top_7_4_gi(3 downto 0); -- __I_I_SLICE_PORT
bus20040728_top <= p_mix_bus20040728_top_7_0_gi; -- __I_I_SLICE_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aea
inst_aea: inst_aea_e
port map (
bus20040728_altop_i => bus20040728_altop,
bus20040728_top_i => bus20040728_top
);
-- End of Generated Instance Port Map for inst_aea
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
01a5ee846a9f9096f622780ae442af7e
| 0.607114 | 3.151592 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab1.vhd
| 5 | 656 |
entity elab1_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab1_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab1 is
end entity;
architecture test of elab1 is
signal x, y : integer;
begin
uut: entity work.elab1_bot
port map ( x, y );
process is
begin
x <= 0;
wait for 1 ns;
assert y = 1;
x <= 2;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
158af91455a172f255f7fabee91db448
| 0.466463 | 4.049383 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_mux2.vhd
| 1 | 3,885 |
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux2.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux2 IS
PORT
(
data0 : IN STD_LOGIC ;
data1 : IN STD_LOGIC ;
sel : IN STD_LOGIC ;
result : OUT STD_LOGIC
);
END lpm_mux2;
ARCHITECTURE SYN OF lpm_mux2 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
sub_wire4 <= data0;
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
sub_wire2 <= data1;
sub_wire3(1, 0) <= sub_wire2;
sub_wire3(0, 0) <= sub_wire4;
sub_wire5 <= sel;
sub_wire6(0) <= sub_wire5;
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_MUX",
lpm_width => 1,
lpm_widths => 1
)
PORT MAP (
data => sub_wire3,
sel => sub_wire6,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
fe3647d1125d2e248742399120d03c06
| 0.632175 | 3.438053 | false | false | false | false |
blutsvente/MIX
|
test/results/io/inst_t_e-rtl-a.vhd
| 1 | 2,299 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:39:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.3 2006/06/26 07:42:19 wig Exp $
-- $Date: 2006/06/26 07:42:19 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.3 2006/06/26 07:42:19 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_sig_in_01_gi : in std_ulogic;
p_mix_sig_in_03_gi : in std_ulogic_vector(7 downto 0);
p_mix_sig_io_05_gc : inout std_ulogic_vector(5 downto 0);
p_mix_sig_io_06_gc : inout std_ulogic_vector(6 downto 0);
p_mix_sig_out_02_go : out std_ulogic;
p_mix_sig_out_04_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_sig_in_01_gi => sig_in_01,
p_mix_sig_in_03_gi => sig_in_03,
p_mix_sig_io_05_gc => sig_io_05,
p_mix_sig_io_06_gc => sig_io_06,
p_mix_sig_out_02_go => sig_out_02,
p_mix_sig_out_04_go => sig_out_04
);
-- End of Generated Instance Port Map for inst_a
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3d6c35ce93e76eb5bcc03b9f67a85371
| 0.582862 | 2.845297 | false | false | false | false |
blutsvente/MIX
|
test/results/sigport/verilog/ent_a-rtl-a.vhd
| 1 | 6,931 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa --
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic;
port_ab_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
c0ef54d1727481546dfde05a72f21c22
| 0.619247 | 2.82092 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/inst_e_e-rtl-a.vhd
| 1 | 17,255 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.4 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.4 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_ea_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_cp_lcmd_2_6_6_gi : in std_ulogic;
p_mix_cp_lcmd_3_6_6_gi : in std_ulogic;
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic;
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_widesig_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
video_i : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eb_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end component;
-- ---------
component inst_ec_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ec_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ec_e
);
end component;
-- ---------
component inst_ed_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ed_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ed_e
);
end component;
-- ---------
component inst_ee_e
-- No Generated Generics
-- Generated Generics for Entity inst_ee_e
-- End of Generated Generics for Entity inst_ee_e
port (
-- Generated Port for Entity inst_ee_e
tmi_sbist_fail : in std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ee_e
);
end component;
-- ---------
component inst_ef_e
-- No Generated Generics
-- Generated Generics for Entity inst_ef_e
-- End of Generated Generics for Entity inst_ef_e
port (
-- Generated Port for Entity inst_ef_e
c_addr : out std_ulogic_vector(12 downto 0);
c_bus_in : out std_ulogic_vector(31 downto 0); -- CBUSinterface
cp_lcmd : out std_ulogic_vector(6 downto 0); -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2 : out std_ulogic_vector(6 downto 0); -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p : out std_ulogic_vector(6 downto 0) -- Signal name != port name
-- End of Generated Port for Entity inst_ef_e
);
end component;
-- ---------
component inst_eg_e
-- No Generated Generics
-- Generated Generics for Entity inst_eg_e
-- End of Generated Generics for Entity inst_eg_e
port (
-- Generated Port for Entity inst_eg_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- cpui/finputs
-- End of Generated Port for Entity inst_eg_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0);
signal c_bus_in : std_ulogic_vector(31 downto 0);
signal cp_lcmd : std_ulogic_vector(6 downto 0);
signal cp_lcmd_2 : std_ulogic_vector(6 downto 0);
signal cp_lcmd_3 : std_ulogic_vector(6 downto 0);
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0);
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0);
signal widemerge_a1 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_19 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_20 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_21 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_22 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_23 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_24 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_25 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_26 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_28 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_29 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_30 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
unsplice_a1_no3(125 downto 0) <= p_mix_unsplice_a1_no3_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a1_no3(127) <= p_mix_unsplice_a1_no3_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
widemerge_a1 <= p_mix_widemerge_a1_31_0_gi; -- __I_I_BUS_PORT
widesig <= widesig_i; -- __I_I_BUS_PORT
widesig_r_0 <= p_mix_widesig_r_0_gi; -- __I_I_BIT_PORT
widesig_r_1 <= p_mix_widesig_r_1_gi; -- __I_I_BIT_PORT
widesig_r_10 <= p_mix_widesig_r_10_gi; -- __I_I_BIT_PORT
widesig_r_11 <= p_mix_widesig_r_11_gi; -- __I_I_BIT_PORT
widesig_r_12 <= p_mix_widesig_r_12_gi; -- __I_I_BIT_PORT
widesig_r_13 <= p_mix_widesig_r_13_gi; -- __I_I_BIT_PORT
widesig_r_14 <= p_mix_widesig_r_14_gi; -- __I_I_BIT_PORT
widesig_r_15 <= p_mix_widesig_r_15_gi; -- __I_I_BIT_PORT
widesig_r_16 <= p_mix_widesig_r_16_gi; -- __I_I_BIT_PORT
widesig_r_17 <= p_mix_widesig_r_17_gi; -- __I_I_BIT_PORT
widesig_r_18 <= p_mix_widesig_r_18_gi; -- __I_I_BIT_PORT
widesig_r_19 <= p_mix_widesig_r_19_gi; -- __I_I_BIT_PORT
widesig_r_2 <= p_mix_widesig_r_2_gi; -- __I_I_BIT_PORT
widesig_r_20 <= p_mix_widesig_r_20_gi; -- __I_I_BIT_PORT
widesig_r_21 <= p_mix_widesig_r_21_gi; -- __I_I_BIT_PORT
widesig_r_22 <= p_mix_widesig_r_22_gi; -- __I_I_BIT_PORT
widesig_r_23 <= p_mix_widesig_r_23_gi; -- __I_I_BIT_PORT
widesig_r_24 <= p_mix_widesig_r_24_gi; -- __I_I_BIT_PORT
widesig_r_25 <= p_mix_widesig_r_25_gi; -- __I_I_BIT_PORT
widesig_r_26 <= p_mix_widesig_r_26_gi; -- __I_I_BIT_PORT
widesig_r_27 <= p_mix_widesig_r_27_gi; -- __I_I_BIT_PORT
widesig_r_28 <= p_mix_widesig_r_28_gi; -- __I_I_BIT_PORT
widesig_r_29 <= p_mix_widesig_r_29_gi; -- __I_I_BIT_PORT
widesig_r_3 <= p_mix_widesig_r_3_gi; -- __I_I_BIT_PORT
widesig_r_30 <= p_mix_widesig_r_30_gi; -- __I_I_BIT_PORT
widesig_r_4 <= p_mix_widesig_r_4_gi; -- __I_I_BIT_PORT
widesig_r_5 <= p_mix_widesig_r_5_gi; -- __I_I_BIT_PORT
widesig_r_6 <= p_mix_widesig_r_6_gi; -- __I_I_BIT_PORT
widesig_r_7 <= p_mix_widesig_r_7_gi; -- __I_I_BIT_PORT
widesig_r_8 <= p_mix_widesig_r_8_gi; -- __I_I_BIT_PORT
widesig_r_9 <= p_mix_widesig_r_9_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
p_mix_cp_lcmd_2_6_6_gi => cp_lcmd_2(6), -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
p_mix_cp_lcmd_3_6_6_gi => cp_lcmd_3(6), -- Signal name != port name
p_mix_cp_lcmd_6_6_gi => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
p_mix_tmi_sbist_fail_11_10_gi => tmi_sbist_fail(11 downto 10),
p_mix_tmi_sbist_fail_9_0_go => tmi_sbist_fail(9 downto 0),
p_mix_unsplice_a1_no3_125_0_gi => unsplice_a1_no3(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_no3_127_127_gi => unsplice_a1_no3(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0), -- # conflict
p_mix_v_select_2_2_gi => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
p_mix_v_select_5_5_gi => v_select(5), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
p_mix_widemerge_a1_31_0_gi => widemerge_a1,
p_mix_widesig_31_0_gi => widesig,
p_mix_widesig_r_0_gi => widesig_r_0,
p_mix_widesig_r_10_gi => widesig_r_10,
p_mix_widesig_r_11_gi => widesig_r_11,
p_mix_widesig_r_12_gi => widesig_r_12,
p_mix_widesig_r_13_gi => widesig_r_13,
p_mix_widesig_r_14_gi => widesig_r_14,
p_mix_widesig_r_15_gi => widesig_r_15,
p_mix_widesig_r_16_gi => widesig_r_16,
p_mix_widesig_r_17_gi => widesig_r_17,
p_mix_widesig_r_18_gi => widesig_r_18,
p_mix_widesig_r_19_gi => widesig_r_19,
p_mix_widesig_r_1_gi => widesig_r_1,
p_mix_widesig_r_20_gi => widesig_r_20,
p_mix_widesig_r_21_gi => widesig_r_21,
p_mix_widesig_r_22_gi => widesig_r_22,
p_mix_widesig_r_23_gi => widesig_r_23,
p_mix_widesig_r_24_gi => widesig_r_24,
p_mix_widesig_r_25_gi => widesig_r_25,
p_mix_widesig_r_26_gi => widesig_r_26,
p_mix_widesig_r_27_gi => widesig_r_27,
p_mix_widesig_r_28_gi => widesig_r_28,
p_mix_widesig_r_29_gi => widesig_r_29,
p_mix_widesig_r_2_gi => widesig_r_2,
p_mix_widesig_r_30_gi => widesig_r_30,
p_mix_widesig_r_3_gi => widesig_r_3,
p_mix_widesig_r_4_gi => widesig_r_4,
p_mix_widesig_r_5_gi => widesig_r_5,
p_mix_widesig_r_6_gi => widesig_r_6,
p_mix_widesig_r_7_gi => widesig_r_7,
p_mix_widesig_r_8_gi => widesig_r_8,
p_mix_widesig_r_9_gi => widesig_r_9,
video_i => video_i
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
p_mix_tmi_sbist_fail_12_10_go => tmi_sbist_fail(12 downto 10)
);
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
p_mix_v_select_2_2_gi => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
p_mix_v_select_5_5_gi => v_select(5) -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
port map (
tmi_sbist_fail => tmi_sbist_fail
);
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
cp_lcmd => cp_lcmd, -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2 => cp_lcmd_2, -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p => cp_lcmd_3 -- Signal name != port name
);
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
21d4383ec0ba2db5171683ff220a4953
| 0.649145 | 2.398193 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/ioblock1_e-rtl-a.vhd
| 1 | 16,203 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:23 wig Exp $
-- $Date: 2006/07/05 10:01:23 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:23 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc_r_io
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- out to in
nand_out : out std_ulogic; -- Last is open
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_out_12 : std_ulogic;
signal nand_out_13 : std_ulogic;
signal nand_out_14 : std_ulogic;
signal nand_out_15 : std_ulogic;
signal nand_out_16 : std_ulogic;
signal nand_out_17 : std_ulogic;
signal nand_out_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
nand_out_2 <= p_mix_nand_out_2_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_r_io_12
ioc_r_io_12: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_2, -- Links ...
nand_out => nand_out_12, -- out to in
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_12
-- Generated Instance Port Map for ioc_r_io_13
ioc_r_io_13: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_12, -- out to in
nand_out => nand_out_13, -- out to in
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_13
-- Generated Instance Port Map for ioc_r_io_14
ioc_r_io_14: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_13, -- out to in
nand_out => nand_out_14, -- out to in
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_14
-- Generated Instance Port Map for ioc_r_io_15
ioc_r_io_15: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_14, -- out to in
nand_out => nand_out_15, -- out to in
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_15
-- Generated Instance Port Map for ioc_r_io_16
ioc_r_io_16: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_15, -- out to in
nand_out => nand_out_16, -- out to in
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_16
-- Generated Instance Port Map for ioc_r_io_17
ioc_r_io_17: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_16, -- out to in
nand_out => nand_out_17, -- out to in
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_17
-- Generated Instance Port Map for ioc_r_io_18
ioc_r_io_18: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_17, -- out to in
nand_out => open, -- Last is open
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_18
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
91f5da39d091a4a81b67a0432d9c33ca
| 0.589274 | 2.361265 | false | false | false | false |
mitchsm/nvc
|
test/regress/const4.vhd
| 5 | 529 |
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
assert c(0, 0) = 0;
assert c(0, 1) = 3;
assert c(0, 3) = 5;
assert c(1, 0) = 6;
assert c(1, 1) = 7;
assert c(1, 2) = 8;
wait;
end process;
end architecture;
|
gpl-3.0
|
023292d5bc063621f2934e57581c5dda
| 0.487713 | 3.075581 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_ec_e-rtl-a.vhd
| 1 | 4,139 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ec_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_ec_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ec_e
--
architecture rtl of inst_ec_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eca_e
-- No Generated Generics
-- Generated Generics for Entity inst_eca_e
-- End of Generated Generics for Entity inst_eca_e
port (
-- Generated Port for Entity inst_eca_e
v_select : in std_ulogic_vector(5 downto 0); -- RequestBusinterface:RequestBus#6(VPU)
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- CPUinterface
-- End of Generated Port for Entity inst_eca_e
);
end component;
-- ---------
component inst_ecb_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecb_e
-- End of Generated Generics for Entity inst_ecb_e
port (
-- Generated Port for Entity inst_ecb_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ecb_e
);
end component;
-- ---------
component inst_ecc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecc_e
-- End of Generated Generics for Entity inst_ecc_e
port (
-- Generated Port for Entity inst_ecc_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- CPUInterface
-- End of Generated Port for Entity inst_ecc_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eca
inst_eca: inst_eca_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select => v_select -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
-- End of Generated Instance Port Map for inst_eca
-- Generated Instance Port Map for inst_ecb
inst_ecb: inst_ecb_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecb
-- Generated Instance Port Map for inst_ecc
inst_ecc: inst_ecc_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
51350aa434238436f65a8ece35eb71c7
| 0.633003 | 3.050111 | false | false | false | false |
mitchsm/nvc
|
test/regress/case4.vhd
| 5 | 972 |
entity case4 is
end entity;
architecture test of case4 is
constant c1 : bit_vector(7 downto 0) := X"ab";
constant c2 : bit_vector(7 downto 0) := X"62";
signal s : bit_vector(7 downto 0);
signal x, y : natural;
begin
process (s) is
begin
case s is
when c1 =>
x <= x + 1;
when c2 | X"50" =>
y <= y + 1;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(1 to 6);
begin
s <= c1;
wait for 1 ns;
s <= c2;
wait for 1 ns;
s <= X"63";
wait for 1 ns;
s <= X"50";
wait for 1 ns;
assert x = 1;
assert y = 2;
v := "000100";
case v is
when "000100" =>
null;
when others =>
assert false;
end case;
wait;
end process;
end architecture;
|
gpl-3.0
|
6bc8ddd9149e8851532f1ace41455698
| 0.427984 | 3.826772 | false | false | false | false |
blutsvente/MIX
|
test/results/highlow/lownobus/ent_a-rtl-a.vhd
| 1 | 7,096 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jun 9 19:08:01 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.7 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.7 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
partzero_2 : out std_ulogic_vector(7 downto 0); -- map partzero to inst_aa, 2
partzero_22 : out std_ulogic_vector(7 downto 0) -- map partzero to inst_aa, 2, 2
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
partzero : in std_ulogic_vector(15 downto 0); -- map parts to high and low
partzero2 : in std_ulogic_vector(15 downto 0); -- map parts to high and low, 2
port_low2bus : in std_ulogic_vector(5 downto 0); -- Map mix_logic0 to a bus, use std_ulogic_vectorMap mix_logic0 to a bus, use std_ulogic_vector
port_low3bus : in std_ulogic_vector(4 downto 0); -- Map mix_logic0 to a bus no vector
port_lowbus : in std_ulogic_vector(5 downto 0); -- Correct mix_logic0_bus
port_lowbus2 : in std_ulogic_vector(4 downto 0) -- Correct mix_logic0_bus, second try
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
partzero_1 : out std_ulogic -- map parts to high and low inst_aa, single bitmap parts to high and low, 2 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_ae
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_bus_0 : std_ulogic_vector(5 downto 0);
signal mix_logic0_bus_1 : std_ulogic_vector(4 downto 0);
signal mix_logic0_bus_2 : std_ulogic_vector(5 downto 0);
signal mix_logic0_bus_3 : std_ulogic_vector(4 downto 0);
signal mix_logic0_bus_4 : std_ulogic_vector(5 downto 0);
constant partzero_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
constant partzero_1c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant partzero_2c : std_ulogic_vector(3 downto 0) := ( others => '0' );
signal partzero : std_ulogic_vector(15 downto 0);
constant partzero2_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
constant partzero2_1c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant partzero2_2c : std_ulogic_vector(3 downto 0) := ( others => '0' );
signal partzero2 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_bus_0 <= ( others => '0' );
mix_logic0_bus_1 <= ( others => '0' );
mix_logic0_bus_2 <= ( others => '0' );
mix_logic0_bus_3 <= ( others => '0' );
mix_logic0_bus_4 <= ( others => '0' );
partzero(10 downto 9) <= partzero_c;
partzero(6) <= partzero_1c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
partzero(15 downto 12) <= partzero_2c;
partzero2(10 downto 9) <= partzero2_c;
partzero2(6) <= partzero2_1c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
partzero2(15 downto 12) <= partzero2_2c;
partzero2(10 downto 9) <= p_mix_partzero2_10_9_gi(1 downto 0); -- __I_I_SLICE_PORT
partzero2(6) <= p_mix_partzero2_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
partzero2(15 downto 12) <= p_mix_partzero2_15_12_gi(3 downto 0); -- __I_I_SLICE_PORT
p_mix_partzero2_5_0_go(5 downto 0) <= partzero2(5 downto 0); -- __I_O_SLICE_PORT
p_mix_partzero2_11_11_go <= partzero2(11); -- __I_O_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_partzero2_8_7_go(1 downto 0) <= partzero2(8 downto 7); -- __I_O_SLICE_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
partzero_2(5 downto 0) => partzero(5 downto 0), -- map parts to high and lowmap parts to high and low inst_aa, single bitmap partzero to inst_aam...
partzero_2(7 downto 6) => partzero(8 downto 7), -- map parts to high and lowmap parts to high and low inst_aa, single bitmap partzero to inst_aam...
partzero_22(5 downto 0) => partzero2(5 downto 0), -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
partzero_22(7 downto 6) => partzero2(8 downto 7) -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
partzero => partzero, -- map parts to high and lowmap parts to high and low inst_aa, single bitmap partzero to inst_aam...
partzero2 => partzero2, -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
port_low2bus => mix_logic0_bus_0, -- Map mix_logic0 to a bus, use std_ulogic_vector
port_low2bus => mix_logic0_bus_4, -- Map mix_logic0 to a bus, use std_ulogic_vector
port_low3bus => mix_logic0_bus_1, -- Map mix_logic0 to a bus no vector
port_lowbus => mix_logic0_bus_2, -- Correct mix_logic0_bus
port_lowbus2 => mix_logic0_bus_3 -- Correct mix_logic0_bus, second try
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
partzero_1 => partzero(11), -- map parts to high and lowmap parts to high and low inst_aa, single bitmap partzero to inst_aam...
partzero_1 => partzero2(11) -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
;
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
cd1e208e48fce98956c9ebdb1038cb0c
| 0.641065 | 2.941957 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/pkg/dma_package.vhd
| 1 | 35,598 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psl.all;
use work.functions.all;
package dma_package is
----------------------------------------------------------------------------------------------------------------------- dma parameters
constant DMA_SIZE_WIDTH : natural := 32; -- number of bits for dma size port - should be log2 of largest request
constant DMA_ID_WIDTH : natural := 32; -- number of bits for unique id field - should be log2 of total requests
constant DMA_READ_QUEUE_DEPTH : natural := 8; -- number of address bits for read queues
constant DMA_WRITE_QUEUE_DEPTH : natural := 8; -- number of address bits for write queues
constant DMA_WRITE_BUFFER_DEPTH : natural := 8; -- number of address bits for write buffers - should be larger than write queue depth if requests are mostly more than one cacheline
constant DMA_DATA_WIDTH : natural := 1024; -- number of bits for dma data port - don't change
constant DMA_READ_ENGINES : natural := 1; -- number of stream engines for reading
constant DMA_WRITE_ENGINES : natural := 1; -- number of stream engines for writing
constant DMA_READ_CREDITS : natural := 32; -- number of credits used for reading - recommended to be (31 or 32) - sum of credits can't exceed 64
constant DMA_WRITE_CREDITS : natural := 32; -- number of credits used for writing - recommended to be (32 or 33) - sum of credits can't exceed 64
constant DMA_TOUCH_COUNT : natural := 1; -- should be smaller than number of cachelines in page (512 by default on POWER8)
constant DMA_READ_TOUCH : std_logic := '0'; -- '1' enables pre-touching pages for large read requests
constant DMA_WRITE_TOUCH : std_logic := '0'; -- '1' enables pre-touching pages for large write requests
constant DMA_WRITE_PRIORITY : std_logic := '1'; -- '1' enables write priority - '0' enables read priority
constant DMA_TAG_WIDTH : natural := PSL_TAG_WIDTH - 1;
constant DMA_READ_CREDITS_WIDTH : natural := log2(DMA_READ_CREDITS) + 1;
constant DMA_WRITE_CREDITS_WIDTH : natural := log2(DMA_WRITE_CREDITS) + 1;
constant DMA_READ_ENGINES_WIDTH : natural := log2(DMA_READ_ENGINES) + 1;
constant DMA_WRITE_ENGINES_WIDTH : natural := log2(DMA_WRITE_ENGINES) + 1;
----------------------------------------------------------------------------------------------------------------------- io
type dma_read_request is record
valid : std_logic;
stream : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
size : unsigned(DMA_SIZE_WIDTH - 1 downto 0);
end record;
type dma_read_response is record
valid : std_logic;
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
data : std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
full : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
end record;
type dma_write_request_item is record
valid : std_logic;
stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
size : unsigned(DMA_SIZE_WIDTH - 1 downto 0);
end record;
type dma_write_data_item is record
valid : std_logic;
stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
data : std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
end record;
type dma_write_request is record
request : dma_write_request_item;
data : dma_write_data_item;
end record;
type dma_write_response is record
valid : std_logic;
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
full : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
end record;
type dma_cd_in is record
read : dma_read_request;
write : dma_write_request;
end record;
type dma_dc_out is record
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
read : dma_read_response;
write : dma_write_response;
end record;
type dma_in is record
cr : cr_in;
-- c : psl_command_in;
b : psl_buffer_in;
r : psl_response_in;
cd : dma_cd_in;
end record;
type dma_out is record
c : psl_command_out;
b : psl_buffer_out;
dc : dma_dc_out;
end record;
----------------------------------------------------------------------------------------------------------------------- stream engines
type request_item is record
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
size : unsigned(DMA_SIZE_WIDTH - 1 downto 0);
end record;
type touch_control is record
touch : std_logic;
count : unsigned(PSL_ERAT_WIDTH - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
end record;
type read_stream_engine is record
request : request_item;
hold : unsigned(DMA_READ_ENGINES_WIDTH - 1 downto 0);
touch : touch_control;
end record;
type write_stream_engine is record
request : request_item;
hold : unsigned(DMA_WRITE_ENGINES_WIDTH - 1 downto 0);
touch : touch_control;
end record;
type read_stream_engines is array (0 to DMA_READ_ENGINES - 1) of read_stream_engine;
type write_stream_engines is array (0 to DMA_WRITE_ENGINES - 1) of write_stream_engine;
type read_stream_engines_control is record
free : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
active_count : unsigned(DMA_READ_ENGINES_WIDTH - 1 downto 0);
ready : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
pull_engine : natural;
pull_stream : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
engine : read_stream_engines;
end record;
type write_stream_engines_control is record
free : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
active_count : unsigned(DMA_WRITE_ENGINES_WIDTH - 1 downto 0);
ready : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
pull_engine : natural;
pull_stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
engine : write_stream_engines;
end record;
----------------------------------------------------------------------------------------------------------------------- queues
type queue_item is record
data : unsigned(DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto 0);
request : request_item;
empty : std_logic;
full : std_logic;
end record;
type read_queues is array (0 to DMA_READ_ENGINES - 1) of queue_item;
type write_queues is array (0 to DMA_WRITE_ENGINES - 1) of queue_item;
type write_buffer_item is record
data : std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
full : std_logic;
empty : std_logic;
end record;
type write_buffers is array (0 to DMA_WRITE_ENGINES - 1) of write_buffer_item;
type write_buffer_control is array (0 to DMA_WRITE_ENGINES - 1) of unsigned(DMA_WRITE_BUFFER_DEPTH - 1 downto 0);
----------------------------------------------------------------------------------------------------------------------- tag control
type tag_control is record
available : std_logic;
tag : unsigned(DMA_TAG_WIDTH downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- response buffer
type response_buffer_control is record
put_flip : std_logic;
pull_flip : std_logic;
pull_address : unsigned(DMA_TAG_WIDTH downto 0);
status : std_logic_vector(2 ** DMA_TAG_WIDTH - 1 downto 0);
end record;
type read_buffer_item is record
data0 : std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
data1 : std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- command history
type read_history_item is record
data : unsigned(DMA_ID_WIDTH + DMA_READ_ENGINES downto 0);
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : unsigned(DMA_READ_ENGINES - 1 downto 0);
touch : std_logic;
end record;
type write_history_item is record
data : unsigned(DMA_ID_WIDTH + DMA_WRITE_ENGINES downto 0);
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : unsigned(DMA_WRITE_ENGINES - 1 downto 0);
touch : std_logic;
end record;
----------------------------------------------------------------------------------------------------------------------- internals
type dma_int is record
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
read : std_logic;
read_touch : std_logic;
write : std_logic;
write_touch : std_logic;
read_credits : unsigned(DMA_READ_CREDITS_WIDTH - 1 downto 0);
write_credits : unsigned(DMA_WRITE_CREDITS_WIDTH - 1 downto 0);
wqb : write_buffer_control;
rt : tag_control;
wt : tag_control;
rse : read_stream_engines_control;
wse : write_stream_engines_control;
rb : response_buffer_control;
wb : response_buffer_control;
o : dma_out;
end record;
----------------------------------------------------------------------------------------------------------------------- externals
type dma_ext is record
rq : read_queues;
wq : write_queues;
wqb : write_buffers;
rb : read_buffer_item;
wb : write_buffer_item;
rh : read_history_item;
wh : write_history_item;
end record;
procedure dma_reset (signal r : inout dma_int);
----------------------------------------------------------------------------------------------------------------------- read procedures
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
);
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
);
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
----------------------------------------------------------------------------------------------------------------------- write procedures
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0)
);
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0)
);
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0);
stream : in natural
);
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0);
stream : in natural
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0)
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0)
);
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector
);
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned
);
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector;
stream : in natural
);
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned;
stream : in natural
);
end package dma_package;
package body dma_package is
----------------------------------------------------------------------------------------------------------------------- reset procedure
procedure dma_reset (signal r : inout dma_int) is
begin
r.id <= (others => '0');
r.read <= '0';
r.read_touch <= '0';
r.write <= '0';
r.write_touch <= '0';
r.read_credits <= u(DMA_READ_CREDITS, DMA_READ_CREDITS_WIDTH);
r.write_credits <= u(DMA_WRITE_CREDITS, DMA_WRITE_CREDITS_WIDTH);
r.wqb <= (others => (others => '0'));
r.rt.available <= '1';
r.rt.tag <= (others => '0');
r.wt.available <= '1';
r.wt.tag <= (others => '0');
r.rse.free <= (others => '1');
r.rse.ready <= (others => '0');
r.rse.active_count <= (others => '0');
r.rse.pull_engine <= 0;
r.rse.pull_stream <= (others => '0');
for stream in 0 to DMA_READ_ENGINES - 1 loop
r.rse.engine(stream).hold <= (others => '0');
end loop;
r.wse.free <= (others => '1');
r.wse.ready <= (others => '0');
r.wse.active_count <= (others => '0');
r.wse.pull_engine <= 0;
r.wse.pull_stream <= (others => '0');
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
r.wse.engine(stream).hold <= (others => '0');
end loop;
r.rb.put_flip <= '1';
r.rb.pull_flip <= '1';
r.rb.pull_address <= (others => '0');
r.rb.status <= (others => '0');
r.wb.put_flip <= '1';
r.wb.pull_flip <= '1';
r.wb.pull_address <= (others => '0');
r.wb.status <= (others => '0');
end procedure dma_reset;
----------------------------------------------------------------------------------------------------------------------- read procedures
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read.valid := '1';
read.address := address;
read.size := n;
read.stream := (others => '0');
read.stream(stream) := '1';
end procedure read_bytes;
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
read_bytes (read, address, u(n, DMA_SIZE_WIDTH), stream);
end procedure read_bytes;
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
read_bytes (read, address, n, 0);
end procedure read_bytes;
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
read_bytes (read, address, u(n, DMA_SIZE_WIDTH), 0);
end procedure read_bytes;
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read_bytes (read, address, u(1, DMA_SIZE_WIDTH), stream);
end procedure read_byte;
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
) is
begin
read_bytes (read, address, u(1, DMA_SIZE_WIDTH), 0);
end procedure read_byte;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
read_bytes (read, address, u(n*PSL_CACHELINE_SIZE, DMA_SIZE_WIDTH), stream);
end procedure read_cachelines;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read_cachelines (read, address, idx(n), stream);
end procedure read_cachelines;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
read_cachelines (read, address, n, 0);
end procedure read_cachelines;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
read_cachelines (read, address, n, 0);
end procedure read_cachelines;
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read_cachelines (read, address, 1, stream);
end procedure read_cacheline;
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
) is
begin
read_cachelines (read, address, 1, 0);
end procedure read_cacheline;
----------------------------------------------------------------------------------------------------------------------- write procedures
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector;
stream : in natural
) is
begin
write.valid := '1';
write.stream := (others => '0');
write.stream(stream) := '1';
write.data(data'range) := data;
end procedure write_data;
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned;
stream : in natural
) is
begin
write_data (write, slv(data), stream);
end procedure write_data;
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector
) is
begin
write_data (write, data, 0);
end procedure write_data;
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned
) is
begin
write_data (write, slv(data), 0);
end procedure write_data;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write.valid := '1';
write.address := address;
write.size := n;
write.stream := (others => '0');
write.stream(stream) := '1';
end procedure write_bytes;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
write_bytes (write, address, u(n, DMA_SIZE_WIDTH), stream);
end procedure write_bytes;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
write_bytes (write, address, n, 0);
end procedure write_bytes;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
write_bytes (write, address, n, 0);
end procedure write_bytes;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0);
stream : in natural
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), stream);
write_data (write.data, data, stream);
end procedure write_byte;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0);
stream : in natural
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), stream);
write_data (write.data, data, stream);
end procedure write_byte;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0)
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), 0);
write_data (write.data, data, 0);
end procedure write_byte;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0)
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), 0);
write_data (write.data, data, 0);
end procedure write_byte;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
write_bytes (write, address, u(n*PSL_CACHELINE_SIZE, DMA_SIZE_WIDTH), stream);
end procedure write_cachelines;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write_cachelines (write, address, idx(n), stream);
end procedure write_cachelines;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
write_cachelines (write, address, n, 0);
end procedure write_cachelines;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
write_cachelines (write, address, n, 0);
end procedure write_cachelines;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write_cachelines (write.request, address, 1, stream);
write_data (write.data, data, stream);
end procedure write_cacheline;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write_cachelines (write.request, address, 1, stream);
write_data (write.data, data, stream);
end procedure write_cacheline;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0)
) is
begin
write_cachelines (write.request, address, 1, 0);
write_data (write.data, data, 0);
end procedure write_cacheline;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0)
) is
begin
write_cachelines (write.request, address, 1, 0);
write_data (write.data, data, 0);
end procedure write_cacheline;
end package body dma_package;
|
bsd-2-clause
|
bc990933a52957fbe91192647bd98be6
| 0.45452 | 4.811841 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/oarg_columnized_mem_bank.vhd
| 1 | 8,266 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : oarg_columnized_mem_bank.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
entity oarg_columnized_mem_bank is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_FACTOR : integer;
C_BUFFER_WIDTH : integer;
C_CONV_AWIDTH : integer;
C_CONV_DWIDTH : integer;
C_ARG_WIDTH : integer;
C_ARG_AWIDTH : integer);
port (
ap_rst : in std_logic;
ap_clk : in std_logic;
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_buffer : in std_logic_vector(C_BUFFER_WIDTH-1 downto 0);
ap_arg_addr : in std_logic_vector(C_ARG_AWIDTH-1 downto 0);
ap_arg_din : in std_logic_vector(C_ARG_WIDTH*C_FACTOR-1 downto 0);
ap_arg_dout : out std_logic_vector(C_ARG_WIDTH*C_FACTOR-1 downto 0);
clk : in std_logic;
conv_ce : in std_logic;
conv_we : in std_logic;
conv_buffer : in std_logic_vector(C_BUFFER_WIDTH-1 downto 0);
conv_addr : in std_logic_vector(C_CONV_AWIDTH-1 downto 0);
conv_data : out std_logic_vector(C_CONV_DWIDTH-1 downto 0));
end oarg_columnized_mem_bank;
architecture rtl of oarg_columnized_mem_bank is
constant BANK_AWIDTH : integer := log2(C_FACTOR);
constant IPORT_AWIDTH : integer := C_BUFFER_WIDTH+C_ARG_AWIDTH;
constant OPORT_AWIDTH : integer := C_BUFFER_WIDTH+(C_CONV_AWIDTH-BANK_AWIDTH);
signal oport_addr : std_logic_vector(OPORT_AWIDTH-1 downto 0);
signal iport_addr : std_logic_vector(IPORT_AWIDTH-1 downto 0);
signal oport_ce : std_logic_vector(C_FACTOR-1 downto 0);
signal oport_din : std_logic_vector(C_CONV_DWIDTH*C_FACTOR-1 downto 0);
signal oport_dout : std_logic_vector(C_CONV_DWIDTH*C_FACTOR-1 downto 0);
begin
ONLY_ONE_BANK : if (C_FACTOR = 1) generate
begin
oport_ce(0) <= conv_ce;
iport_addr <= ap_arg_buffer & ap_arg_addr;
oport_addr <= conv_buffer & conv_addr;
conv_data <= oport_dout;
end generate ONLY_ONE_BANK;
SEVERAL_BANKS : if (C_FACTOR > 1) generate
constant OFFSET_WIDTH : integer := C_CONV_AWIDTH-BANK_AWIDTH;
constant BANK_MSB : integer := C_CONV_AWIDTH-1;
constant BANK_LSB : integer := BANK_MSB-BANK_AWIDTH+1;
constant OFFSET_MSB : integer := BANK_LSB-1;
constant OFFSET_LSB : integer := 0;
signal conv_bank : std_logic_vector(BANK_AWIDTH-1 downto 0);
signal conv_offset : std_logic_vector(OFFSET_WIDTH-1 downto 0);
signal conv_bank_r : std_logic_vector(BANK_AWIDTH-1 downto 0);
begin
iport_addr <= ap_arg_buffer & ap_arg_addr;
conv_bank <= conv_addr(BANK_MSB downto BANK_LSB);
conv_offset <= conv_addr(OFFSET_MSB downto OFFSET_LSB);
process(conv_ce, conv_bank)
begin
oport_ce <= (others => '0');
for i in 0 to C_FACTOR-1 loop
if(unsigned(conv_bank) = i) then
oport_ce(i) <= conv_ce;
end if;
end loop;
end process;
oport_addr <= conv_buffer & conv_offset;
-- Register part of address used to select the bank
process(clk)
begin
if(clk'event and clk = '1') then
if(conv_ce = '1') then
conv_bank_r <= conv_bank;
end if;
end if;
end process;
-- use conv_bank_r to select the mux at the output
process(conv_bank_r, oport_dout)
begin
conv_data <= (others => '0');
for i in 0 to C_FACTOR-1 loop
if(unsigned(conv_bank_r) = i) then
conv_data <= oport_dout(C_CONV_DWIDTH*(i+1)-1 downto C_CONV_DWIDTH*i);
end if;
end loop;
end process;
end generate SEVERAL_BANKS;
BANK_GEN : for i in 0 to C_FACTOR-1 generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 0,
C_IPORT_DWIDTH => C_ARG_WIDTH,
C_IPORT_AWIDTH => IPORT_AWIDTH,
C_OPORT_DWIDTH => C_CONV_DWIDTH,
C_OPORT_AWIDTH => OPORT_AWIDTH)
port map (
rst => ap_rst,
iport_clk => ap_clk,
iport_ce => ap_arg_ce,
iport_we => ap_arg_we,
iport_addr => iport_addr,
iport_din => ap_arg_din(C_ARG_WIDTH*(i+1)-1 downto C_ARG_WIDTH*i),
iport_dout => ap_arg_dout(C_ARG_WIDTH*(i+1)-1 downto C_ARG_WIDTH*i),
oport_clk => clk,
oport_ce => oport_ce(i),
oport_we => conv_we,
oport_addr => oport_addr,
oport_din => oport_din(C_CONV_DWIDTH*(i+1)-1 downto C_CONV_DWIDTH*i),
oport_dout => oport_dout(C_CONV_DWIDTH*(i+1)-1 downto C_CONV_DWIDTH*i));
end generate BANK_GEN;
end rtl;
|
mit
|
73afc9cee34a793007b267fa9d0ecf24
| 0.595572 | 3.698434 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/20051004c/test_e-struct-a.vhd
| 1 | 2,677 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of test_e
--
-- Generated
-- by: wig
-- on: Thu Oct 6 12:55:50 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: test_e-struct-a.vhd,v 1.1 2005/10/06 13:36:57 wig Exp $
-- $Date: 2005/10/06 13:36:57 $
-- $Log: test_e-struct-a.vhd,v $
-- Revision 1.1 2005/10/06 13:36:57 wig
-- New testcase or generics
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of test_e
--
architecture struct of test_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_bug_e
generic (
-- Generated Generics for Entity inst_bug_e
CHROMA_GROUP_DELAY2_G : integer := 1;
CHROMA_GROUP_DELAY_G : integer := 12;
CHROMA_LINE_DELAY2_G : integer := 3;
CHROMA_LINE_DELAY_G : integer := 0;
CHROMA_PIPE_DELAY2_G : integer := 2;
CHROMA_PIPE_DELAY_G : integer := 1
-- End of Generated Generics for Entity inst_bug_e
);
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_7_ar_chroma_delay
inst_7_ar_chroma_delay: inst_bug_e
generic map (
CHROMA_GROUP_DELAY2_G => 4,
CHROMA_GROUP_DELAY_G => 12,
CHROMA_LINE_DELAY2_G => 6,
CHROMA_LINE_DELAY_G => 0,
CHROMA_PIPE_DELAY2_G => 5,
CHROMA_PIPE_DELAY_G => 1
)
;
-- End of Generated Instance Port Map for inst_7_ar_chroma_delay
-- Generated Instance Port Map for inst_9_ar_chroma_delay
inst_9_ar_chroma_delay: inst_bug_e
generic map (
CHROMA_GROUP_DELAY2_G => 7,
CHROMA_GROUP_DELAY_G => 8,
CHROMA_LINE_DELAY2_G => 9,
CHROMA_LINE_DELAY_G => 3,
CHROMA_PIPE_DELAY2_G => 8,
CHROMA_PIPE_DELAY_G => 3
)
;
-- End of Generated Instance Port Map for inst_9_ar_chroma_delay
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
86569555a3e74e3d18962312b91a3155
| 0.599178 | 3.087659 | false | false | false | false |
mitchsm/nvc
|
test/group/issue250.vhd
| 3 | 713 |
entity field is
end entity;
architecture fum of field is
constant cols: natural := 2;
constant rows: natural := 2;
type inter_cell is record
alive_in: bit_vector (0 to 1);
alive_out: bit;
end record;
type field_cell_signals is array
(integer range <>, integer range <>) of inter_cell;
signal cellio : field_cell_signals(0 to rows - 1, 0 to cols - 1); -- 0..11
signal row: integer range 0 to rows - 1 := 1; -- 12
signal col: integer range 0 to rows - 1 := 1; -- 13
begin
cellio(col, row).alive_in <= cellio(col - 1, row - 1).alive_out & '0'
when (col > 0 and row > 0) else "00";
end architecture;
|
gpl-3.0
|
5d0b529441dcb4242e9f2290b8e0fde5
| 0.565217 | 3.495098 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/a_clk-rtl-a.vhd
| 1 | 31,095 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:55:26 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.2 2005/10/06 11:16:05 wig Exp $
-- $Date: 2005/10/06 11:16:05 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.2 2005/10/06 11:16:05 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component a_fsm --
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0);
d9_core_en : in std_ulogic_vector(1 downto 0);
d9_core_pu : in std_ulogic_vector(1 downto 0);
data_core_do : out std_ulogic_vector(1 downto 0);
data_core_i33 : in std_ulogic_vector(7 downto 0);
data_core_i34 : in std_ulogic_vector(7 downto 0);
data_core_o35 : out std_ulogic_vector(7 downto 0);
data_core_o36 : out std_ulogic_vector(7 downto 0);
data_i1 : in std_ulogic_vector(7 downto 0);
data_o1 : out std_ulogic_vector(7 downto 0);
di : in std_ulogic_vector(7 downto 0);
di2 : in std_ulogic_vector(8 downto 0);
disp2_en : in std_ulogic_vector(7 downto 0);
disp_ls_port : out std_ulogic;
disp_ms_port : out std_ulogic;
iosel_bus : out std_ulogic_vector(7 downto 0);
iosel_bus_disp : out std_ulogic_vector(3 downto 0);
iosel_bus_ls_hr : out std_ulogic;
iosel_bus_ls_min : out std_ulogic;
iosel_bus_ms_hr : out std_ulogic;
iosel_bus_ms_min : out std_ulogic;
iosel_bus_nosel : out std_ulogic;
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e --
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_0_0_gi : in std_ulogic; -- __W_SINGLEBITBUS
p_mix_iosel_disp_gi : in std_ulogic_vector(3 downto 0);
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e --
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component alreg --
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4 --
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4 --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad --
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan --
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen --
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic(3 downto 0);
-- __I_OUT_OPEN signal iosel_1 : std_ulogic;
-- __I_OUT_OPEN signal iosel_2 : std_ulogic;
-- __I_OUT_OPEN signal iosel_3 : std_ulogic;
-- __I_OUT_OPEN signal iosel_4 : std_ulogic;
-- __I_OUT_OPEN signal iosel_5 : std_ulogic;
-- __I_OUT_OPEN signal iosel_6 : std_ulogic;
-- __I_OUT_OPEN signal iosel_7 : std_ulogic;
signal iosel_disp : std_ulogic(3 downto 0);
-- __I_OUT_OPEN signal iosel_ls_hr : std_ulogic;
-- __I_OUT_OPEN signal iosel_ls_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_ms_hr : std_ulogic;
-- __I_OUT_OPEN signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0(0), -- IO_Select
iosel_bus(1) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(2) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(3) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(4) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(5) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(6) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(7) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_ls_min => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_ms_hr => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_ms_min => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_0_0_gi => iosel_0(0), -- IO_Select
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
;
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3bc49f16c76a72d4cf431abd1f6b114a
| 0.62949 | 2.447269 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/ios_e-rtl-a.vhd
| 1 | 17,994 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:55:26 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-rtl-a.vhd,v 1.2 2005/10/06 11:16:05 wig Exp $
-- $Date: 2005/10/06 11:16:05 $
-- $Log: ios_e-rtl-a.vhd,v $
-- Revision 1.2 2005/10/06 11:16:05 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ios_e
--
architecture rtl of ios_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioblock0_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_0_0_gi : in std_ulogic; -- __W_SINGLEBITBUS
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end component;
-- ---------
component ioblock1_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock1_e
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_disp_gi : in std_ulogic_vector(3 downto 0);
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic
-- End of Generated Port for Entity ioblock1_e
);
end component;
-- ---------
component ioblock2_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ioblock3_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock3_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ioblock3_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_0(0) <= p_mix_iosel_0_0_0_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BUS_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioblock_0
ioblock_0: ioblock0_e
port map (
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_iosel_0_0_0_gi => iosel_0(0), -- IO_Select
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_en_2_go => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_0
-- Generated Instance Port Map for ioblock_1
ioblock_1: ioblock1_e
port map (
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_1
-- Generated Instance Port Map for ioblock_2
ioblock_2: ioblock2_e
;
-- End of Generated Instance Port Map for ioblock_2
-- Generated Instance Port Map for ioblock_3
ioblock_3: ioblock3_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ioblock_3
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
55f14af695d5d80c563724a1ac2a0f9b
| 0.605924 | 2.260269 | false | false | false | false |
DacHt/CU_Droptest
|
hdl/UART_reset_monitor.vhd
| 1 | 4,585 |
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: UART_reset_monitor.vhd
-- File history:
-- <v0.1>: <2017-06-18>: Initital verison
--
-- Description:
--
-- Monitors the UART rx channels for a reset command ('r') from RMU. If commands is recevied it set the
-- reset signal high for 1 sec to reset the whole system.
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity UART_reset_monitor is
port (
---------------------------------------------------
-- Inputs --
---------------------------------------------------
mclk : IN std_logic; -- Master clock
reset_in : IN std_logic; -- Reset
txrdy : IN std_logic; -- Set to high when command is recevied
data_in : IN std_logic_vector(7 downto 0); -- Data_in from UART
---------------------------------------------------
-- Inputs --
---------------------------------------------------
reset_out : OUT std_logic := '0' -- Reset signal out
);
end UART_reset_monitor;
architecture architecture_UART_reset_monitor of UART_reset_monitor is
--####################### Constants #####################################
constant reset_clk_cyc_duration : integer := 10; -- Amount of clock cycles the reset should last
constant reset_command : integer := 82; -- Reset ascii character to monitor for 82 = 'R'
--####################### Signals #####################################
----------------------------------------------------------------------------------------------------------------------
-- Control signals |Comments --
----------------------------------------------------------------------------------------------------------------------
signal reset_counter : unsigned(4 downto 0) := (others => '0'); -- Variable to keep track of clock cycles
-----------------------------------------------------------------------------------------------------------------------
-- State Machine Signals |Comments --
-----------------------------------------------------------------------------------------------------------------------
type reset_state is (START, IDLE, RECEIVE, RESET);
signal reset_current_state : reset_state;
signal reset_next_state : reset_state := START;
begin
-----------------------------------------------------------------
-- Reset State Machine --
-- Description: --
-- Reset state machine --
-----------------------------------------------------------------
uart_state_machine : process(mclk, reset_in)
begin
if(reset_in = '1') then
reset_out <= '0';
reset_counter <= (others => '0');
else
if(rising_edge(mclk)) then
reset_current_state <= reset_next_state;
case reset_current_state is
when START =>
reset_out <= '0';
reset_counter <= (others => '0');
reset_next_state <= IDLE;
when IDLE => -- Wait for receving command
if(txrdy ='1') then
reset_next_state <= RECEIVE;
end if;
when RECEIVE => -- Recevie the byte
if(data_in = std_logic_vector(to_unsigned(reset_command, data_in'length))) then
reset_next_state <= RESET;
else
reset_next_state <= START;
end if;
when RESET =>
reset_out <= '1';
if (reset_counter >= To_unsigned(reset_clk_cyc_duration, reset_counter'length)) then
reset_next_state <= START;
else
reset_counter <= reset_counter + 1;
end if;
end case;
end if;
end if;
end process uart_state_machine;
-- architecture body
end architecture_UART_reset_monitor;
|
mit
|
22d660b38f0b0240656266f9ebe18a75
| 0.367067 | 5.625767 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue18.vhd
| 5 | 900 |
entity sub is
port (
x, y : in bit_vector(3 downto 0);
z : out bit_vector(3 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y;
end architecture;
-------------------------------------------------------------------------------
entity issue18 is
end entity;
architecture test of issue18 is
signal s : bit_vector(7 downto 0);
constant c : bit_vector(7 downto 0) := X"AA";
begin
sub_i: entity work.sub
port map (
x => c(3 downto 0),
y => s(3 downto 0),
z => s(7 downto 4) );
process is
begin
s(3 downto 0) <= X"A";
wait for 1 ns;
assert s = X"AA";
s(3 downto 0) <= X"0";
wait for 1 ns;
assert s = X"00";
s(3 downto 0) <= X"F";
wait for 1 ns;
assert s = X"AF";
wait;
end process;
end architecture;
|
gpl-3.0
|
98745e6bcf4d5538b61aced6eeee1bc3
| 0.46 | 3.614458 | false | false | false | false |
mitchsm/nvc
|
test/regress/record5.vhd
| 5 | 762 |
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
f1bfc40170ded8e9ddf9faa75b42551f
| 0.515748 | 3.59434 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/lib/functions.vhd
| 1 | 5,408 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package functions is
function endian_swap (a : in std_logic_vector) return std_logic_vector;
function is_full (a : in std_logic_vector; b : in std_logic_vector) return std_logic;
function is_full (a : in unsigned; b : in unsigned) return std_logic;
function is_empty (a : in std_logic_vector; b : in std_logic_vector) return std_logic;
function is_empty (a : in unsigned; b : in unsigned) return std_logic;
function idx (a : in std_logic_vector) return integer;
function idx (a : in unsigned) return integer;
function slv (a : in integer; b : in natural) return std_logic_vector;
function slv (a : in unsigned) return std_logic_vector;
function u (a : in integer; b : in natural) return unsigned;
function u (a : in std_logic_vector) return unsigned;
function u (a : in std_logic) return unsigned;
function l (a : in boolean) return std_logic;
function log2 (a : in natural) return natural;
function ones (a : in std_logic_vector) return natural;
end package functions;
package body functions is
function endian_swap (a : in std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(a'range);
constant bytes : natural := a'length / 8;
begin
for i in 0 to bytes - 1 loop
result(8 * i + 7 downto 8 * i) := a((bytes - 1 - i) * 8 + 7 downto (bytes - 1 - i) * 8);
end loop;
return result;
end function endian_swap;
function is_full (a : in std_logic_vector; b : in std_logic_vector) return std_logic is
variable result : std_logic;
begin
if a(a'high) /= b(b'high) and a(a'high - 1 downto a'low) = b(b'high - 1 downto b'low) then
result := '1';
else
result := '0';
end if;
return result;
end function is_full;
function is_full (a : in unsigned; b : in unsigned) return std_logic is
variable result : std_logic;
begin
if a(a'high) /= b(b'high) and a(a'high - 1 downto a'low) = b(b'high - 1 downto b'low) then
result := '1';
else
result := '0';
end if;
return result;
end function is_full;
function is_empty (a : in std_logic_vector; b : in std_logic_vector) return std_logic is
variable result : std_logic;
begin
if a = b then
result := '1';
else
result := '0';
end if;
return result;
end function is_empty;
function is_empty (a : in unsigned; b : in unsigned) return std_logic is
variable result : std_logic;
begin
if a = b then
result := '1';
else
result := '0';
end if;
return result;
end function is_empty;
function idx (a : in std_logic_vector) return integer is
begin
return to_integer(unsigned(a));
end function idx;
function idx (a : in unsigned) return integer is
begin
return to_integer(a);
end function idx;
function slv (a : in integer; b : in natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(a, b));
end function slv;
function slv (a : in unsigned) return std_logic_vector is
begin
return std_logic_vector(a);
end function slv;
function u (a : in integer; b : in natural) return unsigned is
begin
return to_unsigned(a, b);
end function u;
function u (a : in std_logic_vector) return unsigned is
begin
return unsigned(a);
end function u;
function u (a : in std_logic) return unsigned is
variable result : unsigned(0 downto 0);
begin
if a then
result := u("1");
else
result := u("0");
end if;
return result;
end function u;
function l (a: boolean) return std_logic is
variable result : std_logic;
begin
if a then
result := '1';
else
result := '0';
end if;
return result;
end function l;
function log2 (a : in natural) return natural is
variable b : natural := a;
variable result : natural := 0;
begin
while b > 1 loop
result := result + 1;
b := b / 2;
end loop;
return result;
end function log2;
function ones (a : in std_logic_vector) return natural is
variable result : natural := 0;
begin
for i in a'range loop
if a(i) then
result := result + 1;
end if;
end loop;
return result;
end function ones;
end package body functions;
|
bsd-2-clause
|
d64c640d1d5808314620da0c39d119a6
| 0.507396 | 4.144061 | false | false | false | false |
mitchsm/nvc
|
test/regress/proc5.vhd
| 5 | 941 |
entity proc5 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of proc5 is
procedure next_cycle(signal clk : in std_logic; n : in integer := 1) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
wait for 1 ns;
end loop;
end procedure;
procedure create_clock
( signal clk : inout std_logic;
period : in delay_length;
signal running : in boolean ) is
begin
if running then
clk <= not clk after period / 2;
end if;
end procedure;
signal running : boolean := true;
signal clk : std_logic := '1';
begin
process (clk, running) is
begin
create_clock(clk, 20 ns, running);
end process;
process is
begin
next_cycle(clk, 50);
assert now = 1001 ns;
running <= false;
wait;
end process;
end architecture;
|
gpl-3.0
|
e813d1824a88c4cb03c866ca206630ad
| 0.564293 | 4.056034 | false | false | false | false |
blutsvente/MIX
|
test/results/padio2/padframe-struct-a.vhd
| 1 | 10,095 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of padframe
--
-- Generated
-- by: wig
-- on: Wed Jul 5 17:16:56 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: padframe-struct-a.vhd,v 1.5 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: padframe-struct-a.vhd,v $
-- Revision 1.5 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of padframe
--
architecture struct of padframe is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component pads_eastnord
-- No Generated Generics
port (
-- Generated Port for Entity pads_eastnord
clkf81_gi : in std_ulogic;
clockdr_i_gi : in std_ulogic;
db2o_10 : inout std_ulogic; -- Flat Panel
db2o_11 : inout std_ulogic; -- Flat Panel
db2o_12 : inout std_ulogic; -- Flat Panel
db2o_13 : inout std_ulogic; -- Flat Panel
db2o_14 : inout std_ulogic; -- Flat Panel
db2o_15 : inout std_ulogic; -- Flat Panel
db2o_i : in std_ulogic_vector(15 downto 10); -- padin
db2o_o : out std_ulogic_vector(15 downto 10); -- padout
dbo_10 : inout std_ulogic; -- Flat Panel
dbo_11 : inout std_ulogic; -- Flat Panel
dbo_12 : inout std_ulogic; -- Flat Panel
dbo_13 : inout std_ulogic; -- Flat Panel
dbo_14 : inout std_ulogic; -- Flat Panel
dbo_15 : inout std_ulogic; -- Flat Panel
dbo_i : in std_ulogic_vector(15 downto 10); -- padin
dbo_o_15_10_go : out std_ulogic_vector(5 downto 0);
default_gi : in std_ulogic;
mode_1_i_gi : in std_ulogic;
mode_2_i_gi : in std_ulogic;
mode_3_i_gi : in std_ulogic;
pmux_sel_por_gi : in std_ulogic;
res_f81_n_gi : in std_ulogic;
rgbout_byp_i_gi : in std_ulogic;
rgbout_iddq_i_gi : in std_ulogic;
rgbout_sio_i_gi : in std_ulogic;
scan_en_i_gi : in std_ulogic;
shiftdr_i_gi : in std_ulogic;
tck_i_gi : in std_ulogic;
updatedr_i_gi : in std_ulogic;
varclk_i_gi : in std_ulogic
-- End of Generated Port for Entity pads_eastnord
);
end component;
-- ---------
component pads_eastsouth
-- No Generated Generics
port (
-- Generated Port for Entity pads_eastsouth
clkf81_gi : in std_ulogic;
clockdr_i_gi : in std_ulogic;
default_gi : in std_ulogic;
mode_1_i_gi : in std_ulogic;
mode_2_i_gi : in std_ulogic;
mode_3_i_gi : in std_ulogic;
pmux_sel_por_gi : in std_ulogic;
res_f81_n_gi : in std_ulogic;
scan_en_i_gi : in std_ulogic;
shiftdr_i_gi : in std_ulogic;
tck_i_gi : in std_ulogic;
updatedr_i_gi : in std_ulogic
-- End of Generated Port for Entity pads_eastsouth
);
end component;
-- ---------
component pads_nordeast
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_nordwest
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_southeast
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_southwest
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_westsouth
-- No Generated Generics
port (
-- Generated Port for Entity pads_westsouth
clkf81_gi : in std_ulogic;
clockdr_i_gi : in std_ulogic;
db2o_0 : inout std_ulogic; -- Flat Panel
db2o_1 : inout std_ulogic; -- Flat Panel
db2o_2 : inout std_ulogic; -- Flat Panel
db2o_3 : inout std_ulogic; -- Flat Panel
db2o_4 : inout std_ulogic; -- Flat Panel
db2o_5 : inout std_ulogic; -- Flat Panel
db2o_6 : inout std_ulogic; -- Flat Panel
db2o_7 : inout std_ulogic; -- Flat Panel
db2o_8 : inout std_ulogic; -- Flat Panel
db2o_9 : inout std_ulogic; -- Flat Panel
db2o_i : in std_ulogic_vector(9 downto 0); -- padin
db2o_o : out std_ulogic_vector(9 downto 0); -- padout
dbo_0 : inout std_ulogic; -- Flat Panel
dbo_1 : inout std_ulogic; -- Flat Panel
dbo_2 : inout std_ulogic; -- Flat Panel
dbo_3 : inout std_ulogic; -- Flat Panel
dbo_4 : inout std_ulogic; -- Flat Panel
dbo_5 : inout std_ulogic; -- Flat Panel
dbo_6 : inout std_ulogic; -- Flat Panel
dbo_7 : inout std_ulogic; -- Flat Panel
dbo_8 : inout std_ulogic; -- Flat Panel
dbo_9 : inout std_ulogic; -- Flat Panel
dbo_i : in std_ulogic_vector(9 downto 0); -- padin
dbo_o_9_0_go : out std_ulogic_vector(9 downto 0);
default_gi : in std_ulogic;
mode_1_i_gi : in std_ulogic;
mode_2_i_gi : in std_ulogic;
mode_3_i_gi : in std_ulogic;
pmux_sel_por_gi : in std_ulogic;
res_f81_n_gi : in std_ulogic;
rgbout_byp_i_gi : in std_ulogic;
rgbout_iddq_i_gi : in std_ulogic;
rgbout_sio_i_gi : in std_ulogic;
scan_en_i_gi : in std_ulogic;
shiftdr_i_gi : in std_ulogic;
tck_i_gi : in std_ulogic;
updatedr_i_gi : in std_ulogic;
varclk_i_gi : in std_ulogic
-- End of Generated Port for Entity pads_westsouth
);
end component;
-- ---------
--
-- Generated Signal List
--
signal clkf81 : std_ulogic;
signal clockdr_i : std_ulogic;
signal default : std_ulogic;
signal mode_1_i : std_ulogic;
signal mode_2_i : std_ulogic;
signal mode_3_i : std_ulogic;
signal pmux_sel_por : std_ulogic;
signal res_f81_n : std_ulogic;
signal rgbout_byp_i : std_ulogic;
signal rgbout_iddq_i : std_ulogic;
signal rgbout_sio_i : std_ulogic;
signal scan_en_i : std_ulogic;
signal shiftdr_i : std_ulogic;
signal tck_i : std_ulogic;
signal updatedr_i : std_ulogic;
signal varclk_i : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for i_pads_en
i_pads_en: pads_eastnord
port map (
clkf81_gi => clkf81,
clockdr_i_gi => clockdr_i,
db2o_10 => db2o_10, -- Flat Panel
db2o_11 => db2o_11, -- Flat Panel
db2o_12 => db2o_12, -- Flat Panel
db2o_13 => db2o_13, -- Flat Panel
db2o_14 => db2o_14, -- Flat Panel
db2o_15 => db2o_15, -- Flat Panel
db2o_i => db2o_i(15 downto 10), -- padin (X2)
db2o_o => db2o_o(15 downto 10), -- padout (X2)
dbo_10 => dbo_10, -- Flat Panel
dbo_11 => dbo_11, -- Flat Panel
dbo_12 => dbo_12, -- Flat Panel
dbo_13 => dbo_13, -- Flat Panel
dbo_14 => dbo_14, -- Flat Panel
dbo_15 => dbo_15, -- Flat Panel
dbo_i => dbo_i(15 downto 10), -- padin (X2)
dbo_o_15_10_go => dbo_o(15 downto 10), -- padout
default_gi => default,
mode_1_i_gi => mode_1_i,
mode_2_i_gi => mode_2_i,
mode_3_i_gi => mode_3_i,
pmux_sel_por_gi => pmux_sel_por,
res_f81_n_gi => res_f81_n,
rgbout_byp_i_gi => rgbout_byp_i,
rgbout_iddq_i_gi => rgbout_iddq_i,
rgbout_sio_i_gi => rgbout_sio_i,
scan_en_i_gi => scan_en_i,
shiftdr_i_gi => shiftdr_i,
tck_i_gi => tck_i,
updatedr_i_gi => updatedr_i,
varclk_i_gi => varclk_i
);
-- End of Generated Instance Port Map for i_pads_en
-- Generated Instance Port Map for i_pads_es
i_pads_es: pads_eastsouth
port map (
clkf81_gi => clkf81,
clockdr_i_gi => clockdr_i,
default_gi => default,
mode_1_i_gi => mode_1_i,
mode_2_i_gi => mode_2_i,
mode_3_i_gi => mode_3_i,
pmux_sel_por_gi => pmux_sel_por,
res_f81_n_gi => res_f81_n,
scan_en_i_gi => scan_en_i,
shiftdr_i_gi => shiftdr_i,
tck_i_gi => tck_i,
updatedr_i_gi => updatedr_i
);
-- End of Generated Instance Port Map for i_pads_es
-- Generated Instance Port Map for i_pads_ne
i_pads_ne: pads_nordeast
;
-- End of Generated Instance Port Map for i_pads_ne
-- Generated Instance Port Map for i_pads_nw
i_pads_nw: pads_nordwest
;
-- End of Generated Instance Port Map for i_pads_nw
-- Generated Instance Port Map for i_pads_se
i_pads_se: pads_southeast
;
-- End of Generated Instance Port Map for i_pads_se
-- Generated Instance Port Map for i_pads_sw
i_pads_sw: pads_southwest
;
-- End of Generated Instance Port Map for i_pads_sw
-- Generated Instance Port Map for i_pads_ws
i_pads_ws: pads_westsouth
port map (
clkf81_gi => clkf81,
clockdr_i_gi => clockdr_i,
db2o_0 => db2o_0, -- Flat Panel
db2o_1 => db2o_1, -- Flat Panel
db2o_2 => db2o_2, -- Flat Panel
db2o_3 => db2o_3, -- Flat Panel
db2o_4 => db2o_4, -- Flat Panel
db2o_5 => db2o_5, -- Flat Panel
db2o_6 => db2o_6, -- Flat Panel
db2o_7 => db2o_7, -- Flat Panel
db2o_8 => db2o_8, -- Flat Panel
db2o_9 => db2o_9, -- Flat Panel
db2o_i => db2o_i(9 downto 0), -- padin (X2)
db2o_o => db2o_o(9 downto 0), -- padout (X2)
dbo_0 => dbo_0, -- Flat Panel
dbo_1 => dbo_1, -- Flat Panel
dbo_2 => dbo_2, -- Flat Panel
dbo_3 => dbo_3, -- Flat Panel
dbo_4 => dbo_4, -- Flat Panel
dbo_5 => dbo_5, -- Flat Panel
dbo_6 => dbo_6, -- Flat Panel
dbo_7 => dbo_7, -- Flat Panel
dbo_8 => dbo_8, -- Flat Panel
dbo_9 => dbo_9, -- Flat Panel
dbo_i => dbo_i(9 downto 0), -- padin (X2)
dbo_o_9_0_go => dbo_o(9 downto 0), -- padout
default_gi => default,
mode_1_i_gi => mode_1_i,
mode_2_i_gi => mode_2_i,
mode_3_i_gi => mode_3_i,
pmux_sel_por_gi => pmux_sel_por,
res_f81_n_gi => res_f81_n,
rgbout_byp_i_gi => rgbout_byp_i,
rgbout_iddq_i_gi => rgbout_iddq_i,
rgbout_sio_i_gi => rgbout_sio_i,
scan_en_i_gi => scan_en_i,
shiftdr_i_gi => shiftdr_i,
tck_i_gi => tck_i,
updatedr_i_gi => updatedr_i,
varclk_i_gi => varclk_i
);
-- End of Generated Instance Port Map for i_pads_ws
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
ecfffd4982aaea22a5ce1dda9af0d000
| 0.609411 | 2.531344 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/EXE_MEM_Register.vhd
| 2 | 2,639 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:52 11/22/2013
-- Design Name:
-- Module Name: EXE_MEM_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EXE_MEM_Register is
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_REG_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
DATA_MEM_READ_WRITE_IN : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
REGS_READ_WRITE_IN : in STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0) := HIGH_RESIST;
WRITE_REG_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
DATA_MEM_READ_WRITE_OUT : out STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
REGS_READ_WRITE_OUT : out STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT
);
end EXE_MEM_Register;
architecture Behavioral of EXE_MEM_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
NEW_PC_OUT <= NEW_PC_IN;
WRITE_DM_DATA_OUT <= WRITE_DM_DATA_IN;
WRITE_REG_NUM_OUT <= WRITE_REG_NUM_IN;
ALU_RESULT_OUT <= ALU_RESULT_IN;
IH_REG_OUT <= IH_REG_IN;
DATA_MEM_READ_WRITE_OUT <= DATA_MEM_READ_WRITE_IN;
REGS_READ_WRITE_OUT <= REGS_READ_WRITE_IN;
REGS_WRITE_DATA_SRC_OUT <= REGS_WRITE_DATA_SRC_IN;
end if;
end process;
end Behavioral;
|
apache-2.0
|
45cbaac4695976ebfd5ae923da5df8f2
| 0.595301 | 3.210462 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/CLK_MODULE.vhd
| 2 | 1,465 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:32:35 11/22/2013
-- Design Name:
-- Module Name: MUX_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLK_MODULE is
Port ( CLK_IN : in STD_LOGIC;
CLK : inout STD_LOGIC := '1'
);
end CLK_MODULE;
architecture Behavioral of CLK_MODULE is
signal count : std_logic_vector(29 downto 0) := "000000000000000000000000000000";
begin
process (CLK_IN)
begin
if (CLK_IN'event and CLK_IN = '0') then
count <= count + 1;
--if (count = "000001010110001001011010000000") then
if (count = "000000000000000000000000000011") then
CLK <= not CLK;
count <= "000000000000000000000000000000";
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
df4c2f67e561411ecca3e3809ca89f79
| 0.614334 | 3.815104 | false | false | false | false |
mitchsm/nvc
|
test/regress/bounds6.vhd
| 5 | 378 |
entity bounds6 is
end entity;
architecture test of bounds6 is
begin
process is
variable i : integer;
variable c : character;
begin
i := 32;
wait for 1 ns;
c := character'val(i);
assert c = ' ';
i := 1517262;
wait for 1 ns;
c := character'val(i);
wait;
end process;
end architecture;
|
gpl-3.0
|
3b6c7fde3315e8f4de3d215e25775262
| 0.526455 | 3.9375 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/iarg_columnized_mem_bank.vhd
| 1 | 7,331 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : iarg_columnized_mem_bank.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
entity iarg_columnized_mem_bank is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_FACTOR : integer;
C_BUFFER_WIDTH : integer;
C_CONV_AWIDTH : integer;
C_CONV_DWIDTH : integer;
C_ARG_WIDTH : integer;
C_ARG_AWIDTH : integer);
port (
ap_rst : in std_logic;
clk : in std_logic;
conv_ce : in std_logic;
conv_we : in std_logic;
conv_buffer : in std_logic_vector(C_BUFFER_WIDTH-1 downto 0);
conv_addr : in std_logic_vector(C_CONV_AWIDTH-1 downto 0);
conv_data : in std_logic_vector(C_CONV_DWIDTH-1 downto 0);
ap_clk : in std_logic;
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_buffer : in std_logic_vector(C_BUFFER_WIDTH-1 downto 0);
ap_arg_addr : in std_logic_vector(C_ARG_AWIDTH-1 downto 0);
ap_arg_din : in std_logic_vector(C_ARG_WIDTH*C_FACTOR-1 downto 0);
ap_arg_dout : out std_logic_vector(C_ARG_WIDTH*C_FACTOR-1 downto 0));
end iarg_columnized_mem_bank;
architecture rtl of iarg_columnized_mem_bank is
constant BANK_AWIDTH : integer := log2(C_FACTOR);
constant IPORT_AWIDTH : integer := C_BUFFER_WIDTH+(C_CONV_AWIDTH-BANK_AWIDTH);
constant OPORT_AWIDTH : integer := C_BUFFER_WIDTH+C_ARG_AWIDTH;
signal iport_addr : std_logic_vector(IPORT_AWIDTH-1 downto 0);
signal oport_addr : std_logic_vector(OPORT_AWIDTH-1 downto 0);
signal iport_ce : std_logic_vector(C_FACTOR-1 downto 0);
begin
ONLY_ONE_BANK : if (C_FACTOR = 1) generate
begin
iport_ce(0) <= conv_ce;
iport_addr <= conv_buffer & conv_addr;
oport_addr <= ap_arg_buffer & ap_arg_addr;
end generate ONLY_ONE_BANK;
SEVERAL_BANKS : if (C_FACTOR > 1) generate
constant OFFSET_WIDTH : integer := C_CONV_AWIDTH-BANK_AWIDTH;
constant BANK_MSB : integer := C_CONV_AWIDTH-1;
constant BANK_LSB : integer := BANK_MSB-BANK_AWIDTH+1;
constant OFFSET_MSB : integer := BANK_LSB-1;
constant OFFSET_LSB : integer := 0;
signal conv_bank : std_logic_vector(BANK_AWIDTH-1 downto 0);
signal conv_offset : std_logic_vector(OFFSET_WIDTH-1 downto 0);
begin
conv_bank <= conv_addr(BANK_MSB downto BANK_LSB);
conv_offset <= conv_addr(OFFSET_MSB downto OFFSET_LSB);
process(conv_ce, conv_bank)
begin
iport_ce <= (others => '0');
for i in 0 to C_FACTOR-1 loop
if(unsigned(conv_bank) = i) then
iport_ce(i) <= conv_ce;
end if;
end loop;
end process;
iport_addr <= conv_buffer & conv_offset;
oport_addr <= ap_arg_buffer & ap_arg_addr;
end generate SEVERAL_BANKS;
BANK_GEN : for i in 0 to C_FACTOR-1 generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 1,
C_IPORT_DWIDTH => C_CONV_DWIDTH,
C_IPORT_AWIDTH => IPORT_AWIDTH,
C_OPORT_DWIDTH => C_ARG_WIDTH,
C_OPORT_AWIDTH => OPORT_AWIDTH)
port map (
rst => ap_rst,
iport_clk => clk,
iport_ce => iport_ce(i),
iport_we => '1',
iport_addr => iport_addr,
iport_din => conv_data,
iport_dout => open,
oport_clk => ap_clk,
oport_ce => ap_arg_ce,
oport_we => ap_arg_we,
oport_addr => oport_addr,
oport_din => ap_arg_din(C_ARG_WIDTH*(i+1)-1 downto C_ARG_WIDTH*i),
oport_dout => ap_arg_dout(C_ARG_WIDTH*(i+1)-1 downto C_ARG_WIDTH*i));
end generate BANK_GEN;
end rtl;
|
mit
|
3db7bf7e33b1cc0e56fa29eca05c903d
| 0.593507 | 3.790589 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/components.vhd
| 1 | 2,651 |
library ieee;
use ieee.std_logic_1164.all;
package CU_TOP_FPGA_UART_components is
component CU_TOP_FPGA_UART_CoreUARTapb
GENERIC (
RX_LEGACY_MODE : integer := 0;
-- DEVICE FAMILY
FAMILY : integer := 15;
-- UART configuration parameters
TX_FIFO : integer := 0; -- 1 = with tx fifo, 0 = without tx fifo
RX_FIFO : integer := 0; -- 1 = with rx fifo, 0 = without rx fifo
BAUD_VALUE : integer := 0; -- Baud value is set only when fixed buad rate is selected
FIXEDMODE : integer := 0; -- fixed or programmable mode, 0: programmable; 1:fixed
PRG_BIT8 : integer := 0; -- This bit value is selected only when FIXEDMODE is set to 1
PRG_PARITY : integer := 0; -- This bit value is selected only when FIXEDMODE is set to 1
BAUD_VAL_FRCTN : integer := 0; -- 0 = +0.0, 1 = +0.125, 2 = +0.25, 3 = +0.375, 4 = +0.5, 5 = +0.625, 6 = +0.75, 7 = +0.875,
BAUD_VAL_FRCTN_EN : integer := 0 -- 1 = enable baud fraction, 0 = disable baud fraction
);
PORT (
-- Inputs and Outputs
-- APB signals
PCLK : IN std_logic; -- APB system clock
PRESETN : IN std_logic; -- APB system reset
PADDR : IN std_logic_vector(4 DOWNTO 0); -- Address
PSEL : IN std_logic; -- Peripheral select signal
PENABLE : IN std_logic; -- Enable (data valid strobe)
PWRITE : IN std_logic; -- Write/nRead signal
PWDATA : IN std_logic_vector(7 DOWNTO 0); -- 8 bit write data
PRDATA : OUT std_logic_vector(7 DOWNTO 0); -- 8 bit read data
-- AS: Added PREADY and PSLVERR
PREADY : OUT std_logic; -- APB READY signal (tied to 1)
PSLVERR : OUT std_logic; -- APB slave error signal (tied to 0)
-- transmit ready and receive full indicators
TXRDY : OUT std_logic;
RXRDY : OUT std_logic;
-- FLAGS
FRAMING_ERR : OUT std_logic;
PARITY_ERR : OUT std_logic;
OVERFLOW : OUT std_logic;
-- Serial receive and transmit data
RX : IN std_logic;
TX : OUT std_logic
);
end component;
end CU_TOP_FPGA_UART_components;
|
mit
|
3e612a4356e6a3c537059b136576cc37
| 0.477556 | 4.135725 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_t_e-rtl-a.vhd
| 1 | 3,185 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:33 wig Exp $
-- $Date: 2004/04/06 10:50:33 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:33 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_b_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_c_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_d_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_e_e
cgs_ramclk : out std_ulogic;
p_mix_nreset_go : out std_ulogic;
si_vclkx2 : in std_ulogic;
tmu_dac_reset : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
;
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
;
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: inst_c_e
;
-- End of Generated Instance Port Map for inst_c
-- Generated Instance Port Map for inst_d
inst_d: inst_d_e
;
-- End of Generated Instance Port Map for inst_d
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
cgs_ramclk => cgs_ramclk, -- ClockSignalsESDRAMInterface
p_mix_nreset_go => nreset, -- GlobalRESET(Verilogmacro)
si_vclkx2 => si_vclkx2, -- DigitalVideoPort
tmu_dac_reset => tmu_dac_reset, -- CADCTestModeRGBADAC
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
634267c3f1dd7eb5402428cbcd472857
| 0.609419 | 3.266667 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/Rx_async.vhd
| 1 | 21,038 |
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY CU_TOP_FPGA_UART_Rx_async IS
GENERIC ( SYNC_RESET : integer := 0;
-- RX Parameters
RX_FIFO : integer := 0); -- 0=without rx fifo, 1=with rx fifo
PORT (
clk : IN std_logic; -- system clock
baud_clock : IN std_logic; -- 8x baud clock pulse
reset_n : IN std_logic; -- active low async reset
bit8 : IN std_logic; -- if set to one 8 data bits otherwise 7 data bits
parity_en : IN std_logic; -- if set to one parity is enabled otherwise disabled
odd_n_even : IN std_logic; -- if set to one odd parity otherwise even parity
read_rx_byte : IN std_logic; -- read rx byte register
clear_parity : IN std_logic; -- clear parity error
clear_framing_error : IN std_logic; -- clear framing error
rx : IN std_logic;
overflow : OUT std_logic; -- receiver overflow
parity_err : OUT std_logic; -- parity error indicator on recieved data
framing_error : OUT std_logic; -- framing error indicator (AS)
rx_idle_out : OUT std_logic; -- used for framing error assignment (AS)
stop_strobe : OUT std_logic; -- stop sync signal for RXRDY
clear_framing_error_en : OUT std_logic; -- clear framing error enable
clear_parity_en : OUT std_logic; -- clear parity error enable
receive_full : OUT std_logic; -- receiver has a byte ready
rx_byte : OUT std_logic_vector(7 DOWNTO 0);
fifo_write : OUT std_logic);
END ENTITY CU_TOP_FPGA_UART_Rx_async;
ARCHITECTURE translated OF CU_TOP_FPGA_UART_Rx_async IS
-- TYPE receive_states:
type receive_states is (rx_idle, rx_data_bits, rx_stop_bit, rx_wait_state);
-- receive byte register
SIGNAL rx_state : receive_states; -- receive state machine
SIGNAL receive_count : std_logic_vector(3 DOWNTO 0); -- counts bits received
SIGNAL rx_filtered : std_logic; -- filtered rx data
SIGNAL rx_shift : std_logic_vector(8 DOWNTO 0); -- receive shift register
SIGNAL rx_parity_calc : std_logic; -- received parity, calculated
SIGNAL rx_bit_cnt : std_logic_vector(3 DOWNTO 0); -- count of received bits
SIGNAL receive_full_int : std_logic; -- receiver has a byte ready
SIGNAL samples : std_logic_vector(2 DOWNTO 0);
SIGNAL overflow_int : std_logic;
SIGNAL shift_choice : std_logic_vector(1 DOWNTO 0);
SIGNAL parity_choice : std_logic_vector(1 DOWNTO 0);
-- ----------------------------------------------------------------------------
SIGNAL last_bit : std_logic_vector(3 DOWNTO 0);
-- ----------------------------------------------------------------------------
-- receive state machine & byte register
-- ----------------------------------------------------------------------------
SIGNAL overflow_xhdl1 : std_logic;
SIGNAL parity_err_xhdl2 : std_logic;
SIGNAL framing_error_i : std_logic;
SIGNAL framing_error_int : std_logic;
SIGNAL stop_strobe_i : std_logic;
SIGNAL clear_parity_en_xhdl3 : std_logic;
SIGNAL clear_framing_error_en_i : std_logic; -- AS: Added 07-29-09
SIGNAL receive_full_xhdl4 : std_logic;
SIGNAL rx_byte_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL last_bit_case : std_logic_vector(1 DOWNTO 0);
SIGNAL fifo_write_xhdl6 : std_logic;
SIGNAL aresetn : std_logic;
SIGNAL sresetn : std_logic;
BEGIN
aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;
sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';
stop_strobe <= stop_strobe_i;
framing_error <= framing_error_i;
overflow <= overflow_xhdl1;
parity_err <= parity_err_xhdl2;
clear_parity_en <= clear_parity_en_xhdl3;
receive_full <= receive_full_xhdl4;
rx_byte <= rx_byte_xhdl5;
fifo_write <= fifo_write_xhdl6;
rx_idle_out <= '1' when (rx_state = rx_idle) else '0';
clear_framing_error_en <= clear_framing_error_en_i;
last_bit_case <= bit8 & parity_en;
-- filter the receive data
-- ----------------------------------------------------------------------------
-- The receive data filter is a simple majority voter that accepts three
-- samples of the "raw" data and reports the most populus result. This
-- provides a simple single-cycle glitch filter.
-- This input needs to go to both the state machine start bit detector as
-- well as the data shift register as this filter introduces a three-clock
-- delay and we need to keep the phases lined up.
--
majority : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
samples <= "111";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
samples <= "111";
ELSE
IF (baud_clock = '1') THEN
samples(1 DOWNTO 0) <= samples(2 DOWNTO 1);
samples(2) <= rx;
END IF;
END IF;
END IF;
END PROCESS majority;
-- our voter
PROCESS (samples)
BEGIN
CASE samples IS
WHEN "000" =>
rx_filtered <= '0';
WHEN "001" =>
rx_filtered <= '0';
WHEN "010" =>
rx_filtered <= '0';
WHEN "011" =>
rx_filtered <= '1';
WHEN "100" =>
rx_filtered <= '0';
WHEN "101" =>
rx_filtered <= '1';
WHEN "110" =>
rx_filtered <= '1';
WHEN OTHERS =>
rx_filtered <= '1';
END CASE;
END PROCESS;
-- ----------------------------------------------------------------------------
-- receive bit counter
-- ----------------------------------------------------------------------------
rcv_cnt : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
receive_count <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
receive_count <= "0000";
ELSE
IF (baud_clock = '1') THEN
-- no start bit yet or begin sample period for data
IF ((baud_clock = '1' AND rx_state = rx_idle AND (rx_filtered = '1' OR receive_count = "1000")) OR (rx_state = rx_wait_state AND (receive_count = "0110"))) THEN
receive_count <= "0000";
ELSE
receive_count <= receive_count + "0001";
END IF;
END IF;
END IF;
END IF;
END PROCESS rcv_cnt;
-- ----------------------------------------------------------------------------
-- registering of the overflow signal
-- ----------------------------------------------------------------------------
make_overflow : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
overflow_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
overflow_xhdl1 <= '0';
ELSE
IF (baud_clock = '1') THEN
IF (overflow_int = '1') THEN
overflow_xhdl1 <= '1';
END IF;
END IF;
IF (read_rx_byte = '1') THEN
overflow_xhdl1 <= '0';
END IF;
END IF;
END IF;
END PROCESS make_overflow;
-- ----------------------------------------------------------------------------
-- registering of the framing_error signal
-- ----------------------------------------------------------------------------
make_framing_error : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
framing_error_i <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
framing_error_i <= '0';
ELSE
IF (baud_clock = '1') THEN
IF (framing_error_int = '1') THEN
framing_error_i <= '1';
ELSIF (clear_framing_error = '1') THEN
framing_error_i <= '0';
END IF;
ELSIF (clear_framing_error = '1') THEN
framing_error_i <= '0';
ELSE
framing_error_i <= framing_error_i;
END IF;
END IF;
END IF;
END PROCESS make_framing_error;
make_last_bit : PROCESS (clk, aresetn)
BEGIN
IF(aresetn = '0') THEN
last_bit <= "1001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF(sresetn = '0') THEN
last_bit <= "1001";
ELSE
IF((baud_clock = '1') AND (rx_state = rx_idle) AND (receive_count = "1000")) THEN
CASE(last_bit_case) IS
WHEN "00" => last_bit <= "0111";
WHEN "01" => last_bit <= "1000";
WHEN "10" => last_bit <= "1000";
WHEN "11" => last_bit <= "1001";
WHEN OTHERS => last_bit <= "1001";
END CASE;
ELSE
last_bit <= last_bit;
END IF;
END IF;
END IF;
END PROCESS;
rcv_sm : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
rx_state <= rx_idle;
rx_byte_xhdl5 <= "00000000";
overflow_int <= '0';
framing_error_int <= '0';
stop_strobe_i <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
rx_state <= rx_idle;
rx_byte_xhdl5 <= "00000000";
overflow_int <= '0';
framing_error_int <= '0';
stop_strobe_i <= '0';
ELSE
IF (baud_clock = '1') THEN
overflow_int <= '0';
framing_error_int <= '0';
stop_strobe_i <= '0';
CASE rx_state IS
WHEN rx_idle =>
IF (receive_count = "1000") THEN
rx_state <= rx_data_bits;
ELSE
rx_state <= rx_idle;
END IF;
WHEN rx_data_bits =>
IF (rx_bit_cnt = last_bit) THEN
-- last bit has been received
-- if receive_full is still active at this point, then overflow
rx_state <= rx_stop_bit ;
overflow_int <= receive_full_int;
IF (receive_full_int = '0') THEN
rx_byte_xhdl5 <= (bit8 AND rx_shift(7)) & rx_shift(6 DOWNTO 0);
END IF;
ELSE
rx_state <= rx_data_bits; -- still clocking in bits
END IF;
WHEN rx_stop_bit =>
IF (receive_count = "1110") THEN
IF (rx_filtered = '0') THEN
framing_error_int <= '1';
END IF;
ELSIF (receive_count = "1111") THEN
stop_strobe_i <= '1';
rx_state <= rx_wait_state;
ELSE
rx_state <= rx_stop_bit;
END IF;
WHEN rx_wait_state =>
IF ((rx_filtered = '1') OR (receive_count = "0110")) THEN
rx_state <= rx_idle;
ELSE
rx_state <= rx_wait_state;
END IF;
WHEN OTHERS =>
rx_state <= rx_idle;
END CASE;
END IF;
END IF;
END IF;
END PROCESS rcv_sm;
-- ----------------------------------------------------------------------------
-- receive shift register and parity calculation
-- ----------------------------------------------------------------------------
shift_choice <= bit8 & parity_en ;
receive_shift : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
rx_shift(8 DOWNTO 0) <= "000000000";
rx_bit_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
rx_shift(8 DOWNTO 0) <= "000000000";
rx_bit_cnt <= "0000";
ELSE
IF (baud_clock = '1') THEN
IF (rx_state = rx_idle) THEN
rx_shift(8 DOWNTO 0) <= "000000000";
rx_bit_cnt <= "0000";
ELSE
IF (receive_count = "1111") THEN
-- sample new data bit
rx_bit_cnt <= rx_bit_cnt + "0001";
CASE shift_choice IS
WHEN "00" =>
rx_shift(5 DOWNTO 0) <= rx_shift(6 DOWNTO 1);
rx_shift(6) <= rx_filtered;
WHEN "11" =>
rx_shift(7 DOWNTO 0) <= rx_shift(8 DOWNTO 1);
rx_shift(8) <= rx_filtered;
WHEN OTHERS =>
rx_shift(6 DOWNTO 0) <= rx_shift(7 DOWNTO 1);
rx_shift(7) <= rx_filtered;
END CASE;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS receive_shift;
-- ----------------------------------------------------------------------------
-- receiver parity calculation
-- ----------------------------------------------------------------------------
rx_par_calc : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
rx_parity_calc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
rx_parity_calc <= '0';
ELSE
IF (baud_clock = '1') THEN
IF (receive_count = "1111" AND parity_en = '1') THEN
rx_parity_calc <= rx_parity_calc XOR rx_filtered;
END IF;
IF ((rx_state = rx_stop_bit)) THEN
rx_parity_calc <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS rx_par_calc;
-- ----------------------------------------------------------------------------
-- latch parity error for even or odd parity
-- ----------------------------------------------------------------------------
parity_choice <= bit8 & odd_n_even ;
make_parity_err : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
parity_err_xhdl2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
parity_err_xhdl2 <= '0';
ELSE
IF ((baud_clock = '1' AND parity_en = '1') AND receive_count = "1111") THEN
CASE parity_choice IS
WHEN "00" =>
IF (rx_bit_cnt = "0111") THEN
parity_err_xhdl2 <= rx_parity_calc XOR rx_filtered;
END IF;
WHEN "01" =>
IF (rx_bit_cnt = "0111") THEN
parity_err_xhdl2 <= NOT (rx_parity_calc XOR rx_filtered);
END IF;
WHEN "10" =>
IF (rx_bit_cnt = "1000") THEN
parity_err_xhdl2 <= rx_parity_calc XOR rx_filtered;
END IF;
WHEN "11" =>
IF (rx_bit_cnt = "1000") THEN
parity_err_xhdl2 <= NOT (rx_parity_calc XOR rx_filtered);
END IF;
WHEN OTHERS =>
parity_err_xhdl2 <= '0';
END CASE;
END IF;
-- if (read_rx_byte == 1'b1)
IF (clear_parity = '1') THEN
parity_err_xhdl2 <= '0';
END IF;
END IF;
END IF;
END PROCESS make_parity_err;
-- ----------------------------------------------------------------------------
-- receive full indicator process
-- ----------------------------------------------------------------------------
receive_full_indicator : PROCESS (clk, aresetn)
BEGIN
IF (aresetn = '0') THEN
receive_full_int <= '0';
fifo_write_xhdl6 <= '1';
clear_parity_en_xhdl3 <= '0';
clear_framing_error_en_i <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
receive_full_int <= '0';
fifo_write_xhdl6 <= '1';
clear_parity_en_xhdl3 <= '0';
clear_framing_error_en_i <= '0';
ELSE
fifo_write_xhdl6 <= '1';
clear_parity_en_xhdl3 <= '0';
clear_framing_error_en_i <= '0';
IF (baud_clock = '1') THEN
-- last bit has been received
IF (bit8 = '1') THEN
IF (parity_en = '1') THEN
IF (rx_bit_cnt = "1001" AND rx_state = rx_data_bits) THEN
fifo_write_xhdl6 <= '0';
clear_parity_en_xhdl3 <= '1';
clear_framing_error_en_i <= '1';
IF (RX_FIFO = 2#0#) THEN
receive_full_int <= '1';
END IF;
END IF;
ELSE
IF (rx_bit_cnt = "1000" AND rx_state = rx_data_bits) THEN
fifo_write_xhdl6 <= '0';
clear_parity_en_xhdl3 <= '1';
clear_framing_error_en_i <= '1';
IF (RX_FIFO = 2#0#) THEN
receive_full_int <= '1';
END IF;
END IF;
END IF;
ELSE
IF (parity_en = '1') THEN
IF (rx_bit_cnt = "1000" AND rx_state = rx_data_bits) THEN
fifo_write_xhdl6 <= '0';
clear_parity_en_xhdl3 <= '1';
clear_framing_error_en_i <= '1';
IF (RX_FIFO = 2#0#) THEN
receive_full_int <= '1';
END IF;
END IF;
ELSE
IF (rx_bit_cnt = "0111" AND rx_state = rx_data_bits) THEN
fifo_write_xhdl6 <= '0';
clear_parity_en_xhdl3 <= '1';
clear_framing_error_en_i <= '1';
IF (RX_FIFO = 2#0#) THEN
receive_full_int <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
IF (read_rx_byte = '1') THEN
receive_full_int <= '0';
END IF;
END IF;
END IF;
END PROCESS receive_full_indicator;
receive_full_xhdl4 <= receive_full_int ;
END ARCHITECTURE translated;
|
mit
|
11c2ee30c6e46de9218b454e21b40443
| 0.409972 | 4.468564 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_constant2.vhd
| 3 | 3,483 |
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(8 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 102,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 9
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "102"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "102"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
6437ccf37f513853dee8c1fc91b081ce
| 0.645995 | 3.831683 | false | false | false | false |
blutsvente/MIX
|
test/results/io/inst_a_e-rtl-a.vhd
| 1 | 3,458 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:39:03 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.3 2006/06/26 07:42:19 wig Exp $
-- $Date: 2006/06/26 07:42:19 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.3 2006/06/26 07:42:19 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_aa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
sig_in_01_p : in std_ulogic;
sig_in_03_p : in std_ulogic_vector(7 downto 0);
sig_io_out_05_p : inout std_ulogic_vector(5 downto 0);
sig_io_out_06_p : inout std_ulogic_vector(6 downto 0);
sig_out_02_p : out std_ulogic;
sig_out_04_p : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ac_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_in_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_in_03 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_io_05 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_io_06 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_out_02 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_out_04 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
sig_in_01 <= p_mix_sig_in_01_gi; -- __I_I_BIT_PORT
sig_in_03 <= p_mix_sig_in_03_gi; -- __I_I_BUS_PORT
sig_io_05 <= p_mix_sig_io_05_gc; -- __I_I_BUS_PORT
sig_io_06 <= p_mix_sig_io_06_gc; -- __I_I_BUS_PORT
p_mix_sig_out_02_go <= sig_out_02; -- __I_O_BIT_PORT
p_mix_sig_out_04_go <= sig_out_04; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
sig_in_01_p => sig_in_01,
sig_in_03_p => sig_in_03,
sig_io_out_05_p => sig_io_05,
sig_io_out_06_p => sig_io_06,
sig_out_02_p => sig_out_02,
sig_out_04_p => sig_out_04
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
;
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
;
-- End of Generated Instance Port Map for inst_ac
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
fb4fde479cdded14b372235e1872c4ae
| 0.596009 | 2.714286 | false | false | false | false |
blutsvente/MIX
|
test/results/sigport/ent_t-rtl-a.vhd
| 1 | 5,623 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/11/30 14:04:00 wig Exp $
-- $Date: 2005/11/30 14:04:00 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:00 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
e3156606b8a61177486fd02ce0627c47
| 0.628846 | 2.801694 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/vhls/set/solution/syn/vhdl/set_assign_val.vhd
| 4 | 17,258 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set_assign_val is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set_assign_val is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal dest_addr_reg_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_cast_fu_76_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_reg_ioackin_m_axi_dest_AWREADY : STD_LOGIC := '0';
signal ap_sig_ioackin_m_axi_dest_AWREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_103 : BOOLEAN;
signal ap_reg_ioackin_m_axi_dest_WREADY : STD_LOGIC := '0';
signal ap_sig_ioackin_m_axi_dest_WREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_120 : BOOLEAN;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_136 : BOOLEAN;
signal tmp_cast_cast_fu_62_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal sext_cast_fu_66_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal sum_fu_70_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_m_axi_dest_AWREADY assign process. --
ap_reg_ioackin_m_axi_dest_AWREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_m_axi_dest_AWREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_AWREADY))) then
ap_reg_ioackin_m_axi_dest_AWREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = m_axi_dest_AWREADY)) then
ap_reg_ioackin_m_axi_dest_AWREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_m_axi_dest_WREADY assign process. --
ap_reg_ioackin_m_axi_dest_WREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_m_axi_dest_WREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_WREADY))) then
ap_reg_ioackin_m_axi_dest_WREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = m_axi_dest_WREADY)) then
ap_reg_ioackin_m_axi_dest_WREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
dest_addr_reg_86 <= sum_cast_fu_76_p1(32 - 1 downto 0);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, m_axi_dest_BVALID, ap_sig_ioackin_m_axi_dest_AWREADY, ap_sig_ioackin_m_axi_dest_WREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_AWREADY))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_WREADY))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if (not((m_axi_dest_BVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, m_axi_dest_BVALID, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((m_axi_dest_BVALID = ap_const_logic_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(m_axi_dest_BVALID, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((m_axi_dest_BVALID = ap_const_logic_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_103 assign process. --
ap_sig_bdd_103_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_103 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_120 assign process. --
ap_sig_bdd_120_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_120 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_136 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_103)
begin
if (ap_sig_bdd_103) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_120)
begin
if (ap_sig_bdd_120) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_136)
begin
if (ap_sig_bdd_136) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_m_axi_dest_AWREADY assign process. --
ap_sig_ioackin_m_axi_dest_AWREADY_assign_proc : process(m_axi_dest_AWREADY, ap_reg_ioackin_m_axi_dest_AWREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_AWREADY)) then
ap_sig_ioackin_m_axi_dest_AWREADY <= m_axi_dest_AWREADY;
else
ap_sig_ioackin_m_axi_dest_AWREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_m_axi_dest_WREADY assign process. --
ap_sig_ioackin_m_axi_dest_WREADY_assign_proc : process(m_axi_dest_WREADY, ap_reg_ioackin_m_axi_dest_WREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_WREADY)) then
ap_sig_ioackin_m_axi_dest_WREADY <= m_axi_dest_WREADY;
else
ap_sig_ioackin_m_axi_dest_WREADY <= ap_const_logic_1;
end if;
end process;
m_axi_dest_ARADDR <= ap_const_lv32_0;
m_axi_dest_ARBURST <= ap_const_lv2_0;
m_axi_dest_ARCACHE <= ap_const_lv4_0;
m_axi_dest_ARID <= ap_const_lv1_0;
m_axi_dest_ARLEN <= ap_const_lv32_0;
m_axi_dest_ARLOCK <= ap_const_lv2_0;
m_axi_dest_ARPROT <= ap_const_lv3_0;
m_axi_dest_ARQOS <= ap_const_lv4_0;
m_axi_dest_ARREGION <= ap_const_lv4_0;
m_axi_dest_ARSIZE <= ap_const_lv3_0;
m_axi_dest_ARUSER <= ap_const_lv1_0;
m_axi_dest_ARVALID <= ap_const_logic_0;
m_axi_dest_AWADDR <= dest_addr_reg_86;
m_axi_dest_AWBURST <= ap_const_lv2_0;
m_axi_dest_AWCACHE <= ap_const_lv4_0;
m_axi_dest_AWID <= ap_const_lv1_0;
m_axi_dest_AWLEN <= ap_const_lv32_1;
m_axi_dest_AWLOCK <= ap_const_lv2_0;
m_axi_dest_AWPROT <= ap_const_lv3_0;
m_axi_dest_AWQOS <= ap_const_lv4_0;
m_axi_dest_AWREGION <= ap_const_lv4_0;
m_axi_dest_AWSIZE <= ap_const_lv3_0;
m_axi_dest_AWUSER <= ap_const_lv1_0;
-- m_axi_dest_AWVALID assign process. --
m_axi_dest_AWVALID_assign_proc : process(ap_reg_ioackin_m_axi_dest_AWREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_AWREADY))) then
m_axi_dest_AWVALID <= ap_const_logic_1;
else
m_axi_dest_AWVALID <= ap_const_logic_0;
end if;
end process;
-- m_axi_dest_BREADY assign process. --
m_axi_dest_BREADY_assign_proc : process(m_axi_dest_BVALID, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((m_axi_dest_BVALID = ap_const_logic_0)))) then
m_axi_dest_BREADY <= ap_const_logic_1;
else
m_axi_dest_BREADY <= ap_const_logic_0;
end if;
end process;
m_axi_dest_RREADY <= ap_const_logic_0;
m_axi_dest_WDATA <= src;
m_axi_dest_WID <= ap_const_lv1_0;
m_axi_dest_WLAST <= ap_const_logic_0;
m_axi_dest_WSTRB <= ap_const_lv4_F;
m_axi_dest_WUSER <= ap_const_lv1_0;
-- m_axi_dest_WVALID assign process. --
m_axi_dest_WVALID_assign_proc : process(ap_reg_ioackin_m_axi_dest_WREADY, ap_sig_cseq_ST_st3_fsm_2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_WREADY))) then
m_axi_dest_WVALID <= ap_const_logic_1;
else
m_axi_dest_WVALID <= ap_const_logic_0;
end if;
end process;
sext_cast_fu_66_p1 <= std_logic_vector(resize(unsigned(data1),33));
sum_cast_fu_76_p1 <= std_logic_vector(resize(unsigned(sum_fu_70_p2),64));
sum_fu_70_p2 <= std_logic_vector(unsigned(tmp_cast_cast_fu_62_p1) + unsigned(sext_cast_fu_66_p1));
tmp_cast_cast_fu_62_p1 <= std_logic_vector(resize(unsigned(tmp),33));
end behav;
|
mit
|
1f0f38faeff9f1997a40c7f1dd58db5a
| 0.563854 | 2.981171 | false | false | false | false |
mitchsm/nvc
|
test/misc/kcuart.vhd
| 5 | 724 |
entity kcuart is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of kcuart is
signal clk : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0);
signal tx_full : std_logic;
signal tx_wr : std_logic := '0';
signal uart_tx : std_logic;
signal en_16_x_baud : std_logic;
begin
clk <= not clk after 5 ns;
tx_i: entity work.uart_tx6
port map (
data_in => tx_data,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => tx_wr,
buffer_full => tx_full,
buffer_reset => '0',
clk => clk );
end architecture;
|
gpl-3.0
|
e0e2bd981534dfa07dc0aeb3ebd46e87
| 0.516575 | 3.399061 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/ddrv4-rtl-a.vhd
| 1 | 5,642 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ddrv4
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-a.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ddrv4-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ddrv --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_time : in std_ulogic_vector(3 downto 0);
current_time : in std_ulogic_vector(3 downto 0);
display : out std_ulogic_vector(6 downto 0);
key_buffer : in std_ulogic_vector(3 downto 0);
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f --
-- No Generated Generics
port (
-- Generated Port for Entity and_f
out_p : out std_ulogic;
y : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_display_ls_hr_go <= display_ls_hr; -- __I_O_BUS_PORT
p_mix_display_ls_min_go <= display_ls_min; -- __I_O_BUS_PORT
p_mix_display_ms_hr_go <= display_ms_hr; -- __I_O_BUS_PORT
p_mix_display_ms_min_go <= display_ms_min; -- __I_O_BUS_PORT
p_mix_sound_alarm_go <= sound_alarm; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
out_p => sound_alarm,
y => alarm -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
153af74a7d6f0f3d13f58c356bddfdc2
| 0.638603 | 3.120575 | false | false | false | false |
mitchsm/nvc
|
test/regress/null1.vhd
| 4 | 778 |
entity null1 is
end entity;
architecture test of null1 is
type int_array is array (integer range <>) of integer;
function get_null return int_array is
variable b : int_array(7 to -999999) := (others => 0);
begin
return b;
end function;
begin
process is
variable a : int_array(0 to -1) := (others => 0);
variable b : int_array(7 to -999999) := (others => 0);
variable c : int_array(0 downto 1) := (others => 0);
begin
report integer'image(a'length);
assert a'length = 0;
report integer'image(b'length);
assert b'length = 0;
report integer'image(c'length);
assert c'length = 0;
a := get_null;
wait;
end process;
end architecture;
|
gpl-3.0
|
11cee09b60336991d2c5f387de152b29
| 0.565553 | 3.758454 | false | false | false | false |
blutsvente/MIX
|
template/mix_template-rtl-a.vhd
| 1 | 1,689 |
-- -------------------------------------------------------------
-- MIX Architecture Template
--
-- (C) 2002 Micronas GmbH
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: lutscher $
-- $Id: mix_template-rtl-a.vhd,v 1.1 2009/12/15 12:02:53 lutscher Exp $
-- $Date: 2009/12/15 12:02:53 $
-- $Log: mix_template-rtl-a.vhd,v $
-- Revision 1.1 2009/12/15 12:02:53 lutscher
-- initial release
--
-- Revision 1.1 2003/03/25 13:49:00 wig
-- VHDL Templates
--
--
-- Generator: %0%%VERSION%, [email protected]
--
-- --------------------------------------------------------------
--weg: Library IEEE;
--weg: Use IEEE.std_logic_1164.all;
--weg: Use IEEE.std_logic_arith.all;
architecture %ARCH% of %ENTY% is
-- components
component %ENTY%
port( -- SET_TIME,HRS,MINS,CLK: in std_ulogic;
-- RESET : in std_ulogic;
-- CONNECT6:buffer INTEGER range 1 to 12;
-- CONNECT7:buffer INTEGER range 0 to 59;
-- CONNECT8: buffer std_ulogic
);
end component;
-- top level nets
-- signal KONNECT7,KONNECT10 : INTEGER range 0 to 59;
-- signal KONNECT8,KONNECT11,KONNECT12 : std_ulogic;
-- signal KONNECT6,KONNECT9 : INTEGER range 1 to 12;
-- signal KONNECT13 : unsigned(10 downto 0);
begin
-- AM_PM_DISPLAY <= KONNECT13(0);
%INST%: %ENTY%
PORT MAP(
-- SET_TIME => SET_TIME, pin/port to signal
-- HRS => HRS,
-- MINS => MINS,
-- CLK => CLK,
-- RESET => RESET,
-- CONNECT6 => KONNECT6,
-- CONNECT7 => KONNECT7,
-- CONNECT8 => KONNECT8
);
end;
--!End
|
gpl-3.0
|
9604a227d84f6b64de568cb4bf374ead
| 0.523979 | 3.405242 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_constant1.vhd
| 3 | 3,477 |
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant1 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_constant1;
ARCHITECTURE SYN OF lpm_constant1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(8 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 341,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 9
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "341"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "341"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
1d1411243fce00f547914df78233a6c1
| 0.645672 | 3.829295 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/MUX_6.vhd
| 2 | 1,809 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:32:35 11/22/2013
-- Design Name:
-- Module Name: MUX_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_6 is
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_5 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_6 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (2 downto 0) := "111";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
end MUX_6;
architecture Behavioral of MUX_6 is
begin
process (SRC_1, SRC_2, SRC_3, SRC_4, SRC_5, SRC_6, SELEC)
begin
case SELEC is
when "000" =>
OUTPUT <= SRC_1;
when "001" =>
OUTPUT <= SRC_2;
when "010" =>
OUTPUT <= SRC_3;
when "011" =>
OUTPUT <= SRC_4;
when "100" =>
OUTPUT <= SRC_5;
when "101" =>
OUTPUT <= SRC_6;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
|
apache-2.0
|
6aec2eb31965e650876a7408e36cb7c8
| 0.555003 | 3.362454 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/Special_Register.vhd
| 2 | 2,319 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:41:35 11/23/2013
-- Design Name:
-- Module Name: Special_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Special_Register is
port(
clk : in STD_LOGIC;
T_cmd_write : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
RA_cmd_write : in STD_LOGIC;
RA_src : in STD_LOGIC_VECTOR(15 downto 0);
IH_cmd_write : in STD_LOGIC;
IH_src : in STD_LOGIC_VECTOR(15 downto 0);
SP_cmd_write : in STD_LOGIC;
SP_src : in STD_LOGIC_VECTOR(15 downto 0);
T_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
RA_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
IH_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
SP_value : out STD_LOGIC_VECTOR(15 downto 0) := ZERO
);
end Special_Register;
architecture Behavioral of Special_Register is
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (T_cmd_write = WRITE_T_YES) then
if (T_cmd_src = T_SRC_IS_SF) then
if (T_src_SF = '1') then
T_value <= FFFF;
else
T_value <= ZERO;
end if;
elsif (T_cmd_src = T_SRC_IS_NOT_ZF) then
if (T_src_ZF = '0') then
T_value <= FFFF;
else
T_Value <= ZERO;
end if;
else
NULL;
end if;
end if;
if (RA_cmd_write = WRITE_RA_YES) then
RA_value <= RA_src;
end if;
if (IH_cmd_write = WRITE_IH_YES) then
IH_value <= IH_src;
end if;
if (SP_cmd_write = WRITE_SP_YES) then
SP_value <= SP_src;
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
8ecb8d2e473bd58c7707f2d749768b8c
| 0.589047 | 3.027415 | false | false | false | false |
mitchsm/nvc
|
test/regress/ieee1.vhd
| 5 | 688 |
library ieee;
use ieee.std_logic_1164.all;
entity ieee1 is
end entity;
architecture test of ieee1 is
begin
process is
variable a, b, c : std_logic_vector(3 downto 0);
variable d : std_logic_vector(5 downto 0);
begin
a := ( '0', '1', '0', '0' );
b := ( '1', '0', '1', '0' );
assert_a: assert ((a(3) or b(3)) = '1') report "a";
c := (a or b);
assert c(3) = '1' report "c(3)";
assert c(0) = '0' report "c(0)";
assert_b: assert c = ( '1', '1', '1', '0' ) report "b";
d(4 downto 1) := (a or b);
assert d = ( 'U', '1', '1', '1', '0', 'U' );
wait;
end process;
end architecture;
|
gpl-3.0
|
274950058807e87b5bdcd29017a0f503
| 0.463663 | 2.796748 | false | false | false | false |
mitchsm/nvc
|
test/regress/func3.vhd
| 5 | 1,866 |
entity func3 is
end entity;
architecture test of func3 is
type int_array is array (integer range <>) of integer;
function copy_and_sum_1(x : int_array) return integer is
variable tmp : int_array(1 to x'length);
variable sum : integer := 0;
begin
for i in x'range loop
tmp(i) := x(i);
end loop;
for i in tmp'range loop
sum := sum + tmp(i);
end loop;
return sum;
end function;
function copy_and_sum_2(x : int_array) return integer is
variable tmp : int_array(x'range);
variable sum : integer := 0;
begin
for i in x'range loop
tmp(i) := x(i);
end loop;
for i in tmp'range loop
sum := sum + tmp(i);
end loop;
return sum;
end function;
function copy_and_add_1(x : int_array; y : integer) return int_array is
variable tmp : int_array(1 to 5);
begin
for i in 1 to 5 loop
tmp(i) := x(i) + y;
end loop;
return tmp;
end function;
function copy_and_add_2(x : int_array; y : integer) return int_array is
variable tmp : int_array(x'range);
begin
for i in tmp'range loop
tmp(i) := x(i) + y;
report integer'image(tmp(i));
end loop;
return tmp;
end function;
begin
process is
variable a : int_array(1 to 5) := (1, 2, 3, 4, 5);
variable b : int_array(6 downto 2) := (1, 2, 3, 4, 5);
variable c : int_array(1 to 5);
begin
assert copy_and_sum_1(a) = 15;
assert copy_and_sum_2(a) = 15;
assert copy_and_sum_2(b) = 15;
c := copy_and_add_1(a, 1);
assert c = (2, 3, 4, 5, 6);
c := copy_and_add_2(a, 5);
assert c = (6, 7, 8, 9, 10);
wait;
end process;
end architecture;
|
gpl-3.0
|
562b59ecb6105a1ce61ed0e826d3b6da
| 0.517149 | 3.356115 | false | false | false | false |
mitchsm/nvc
|
test/parse/literal.vhd
| 3 | 522 |
architecture a of e is
signal pos : integer := 64;
signal neg : integer := -265;
constant c : integer := 523;
constant a : string := "hel""lo";
constant b : string := """quote""";
constant d : integer := 1E3; -- Integer not real
constant e : real := 1.234;
constant f : real := 0.21712;
constant g : real := 1.4e6;
constant h : real := 235.1e-2;
constant i : integer := 1_2_3_4;
constant j : real := 5_6_7.12_3;
constant k : ptr := null;
begin
end architecture;
|
gpl-3.0
|
d92371fd73fb6d32fa512c10247f77e1
| 0.563218 | 3.324841 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_ed_e-rtl-a.vhd
| 1 | 4,676 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:29 wig Exp $
-- $Date: 2004/04/06 10:50:29 $
-- $Log: inst_ed_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:29 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ed_e
--
architecture rtl of inst_ed_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eda_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eda_e
-- End of Generated Generics for Entity inst_eda_e
port (
-- Generated Port for Entity inst_eda_e
cgs_ramclk : out std_ulogic;
nreset : out std_ulogic;
nreset_s : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_eda_e
);
end component;
-- ---------
component inst_edb_e --
-- No Generated Generics
-- Generated Generics for Entity inst_edb_e
-- End of Generated Generics for Entity inst_edb_e
port (
-- Generated Port for Entity inst_edb_e
acg_systime_init : in std_ulogic_vector(30 downto 0);
cgu_scani : in std_ulogic;
cgu_scano : out std_ulogic;
ifu_gpio0_wkup : in std_ulogic;
ifu_gpio1_wkup : in std_ulogic;
ifu_gpio2_wkup : in std_ulogic;
nreset : in std_ulogic;
nreset_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_edb_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal gpio_int : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal itm_scani : std_ulogic_vector(70 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_scano : std_ulogic_vector(70 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
acg_systime_init <= p_mix_acg_systime_init_30_0_gi; -- __I_I_BUS_PORT
p_mix_cgs_ramclk_go <= cgs_ramclk; -- __I_O_BIT_PORT
gpio_int(2 downto 0) <= p_mix_gpio_int_2_0_gi(2 downto 0); -- __I_I_SLICE_PORT
itm_scani(0) <= p_mix_itm_scani_0_0_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
p_mix_nreset_s_go <= nreset_s; -- __I_O_BIT_PORT
p_mix_tmi_scano_0_0_go <= tmi_scano(0); -- __I_O_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_vclkl27_go <= vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eda
inst_eda: inst_eda_e
port map (
cgs_ramclk => cgs_ramclk, -- ClockSignalsESDRAMInterface
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eda
-- Generated Instance Port Map for inst_edb
inst_edb: inst_edb_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
cgu_scani => itm_scani(0),
cgu_scano => tmi_scano(0),
ifu_gpio0_wkup => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
ifu_gpio1_wkup => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
ifu_gpio2_wkup => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_edb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
d3b01e832492e0379b7178edc61d85fe
| 0.634731 | 3.04229 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_set_0_if_0/synth/zc702_set_0_if_0.vhd
| 1 | 55,377 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_set_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt : OUT STD_LOGIC
);
END zc702_set_0_if_0;
ARCHITECTURE zc702_set_0_if_0_arch OF zc702_set_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_set_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_set_0_if_0_arch: ARCHITECTURE IS "axis_accelerator_adapter,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_set_0_if_0_arch : ARCHITECTURE IS "zc702_set_0_if_0,axis_accelerator_adapter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_set_0_if_0_arch: ARCHITECTURE IS "zc702_set_0_if_0,axis_accelerator_adapter,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_accelerator_adapter,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_AP_ADAPTER_ID=1,C_N_INPUT_ARGS=0,C_N_OUTPUT_ARGS=0,C_S_AXIS_TDATA_WIDTH=64,C_S_AXIS_TUSER_WIDTH=8,C_S_AXIS_TID_WIDTH=4,C_S_AXIS_TDEST_WIDTH=4,C_AP_IARG_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_IARG_MB_DEPTH=0x0000000400000004000000040000000400000004000000040000000400000004,C_AP_IARG_WIDTH=0x0000002000000020000000200000002000000020000000200000002000000020,C_AP_IARG_N_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_DIM_1=0x0000040000000400000004000000040000000400000004000000040000000400,C_AP_IARG_DIM_2=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_FORMAT_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_IARG_FORMAT_FACTOR=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_FORMAT_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_0_DWIDTH=32,C_AP_IARG_1_DWIDTH=32,C_AP_IARG_2_DWIDTH=32,C_AP_IARG_3_DWIDTH=32,C_AP_IARG_4_DWIDTH=32,C_AP_IARG_5_DWIDTH=32,C_AP_IARG_6_DWIDTH=32,C_AP_IARG_7_DWIDTH=32,C_M_AXIS_TDATA_WIDTH=64,C_M_AXIS_TUSER_WIDTH=8,C_M_AXIS_TID_WIDTH=4,C_M_AXIS_TDEST_WIDTH=4,C_AP_OARG_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_OARG_MB_DEPTH=0x0000000400000004000000040000000400000004000000040000000400000004,C_AP_OARG_WIDTH=0x0000002000000020000000200000002000000020000000200000002000000020,C_AP_OARG_N_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_DIM=0x0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008,C_AP_OARG_DIM_1=0x0000040000000400000004000000040000000400000004000000040000000400,C_AP_OARG_DIM_2=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_FORMAT_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_OARG_FORMAT_FACTOR=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_FORMAT_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_0_DWIDTH=32,C_AP_OARG_1_DWIDTH=32,C_AP_OARG_2_DWIDTH=32,C_AP_OARG_3_DWIDTH=32,C_AP_OARG_4_DWIDTH=32,C_AP_OARG_5_DWIDTH=32,C_AP_OARG_6_DWIDTH=32,C_AP_OARG_7_DWIDTH=32,C_N_INOUT_SCALARS=0,C_N_INPUT_SCALARS=3,C_INPUT_SCALAR_DWIDTH=0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020,C_INPUT_SCALAR_MODE=0x0000000000000000,C_OUTPUT_SCALAR_MODE=0x0000000000000000,C_AP_ISCALAR_DOUT_WIDTH=96,C_AP_ISCALAR_IO_DOUT_WIDTH=32,C_INPUT_SCALAR_0_WIDTH=32,C_INPUT_SCALAR_1_WIDTH=32,C_INPUT_SCALAR_2_WIDTH=32,C_INPUT_SCALAR_3_WIDTH=32,C_INPUT_SCALAR_4_WIDTH=32,C_INPUT_SCALAR_5_WIDTH=32,C_INPUT_SCALAR_6_WIDTH=32,C_INPUT_SCALAR_7_WIDTH=32,C_INPUT_SCALAR_8_WIDTH=32,C_INPUT_SCALAR_9_WIDTH=32,C_INPUT_SCALAR_10_WIDTH=32,C_INPUT_SCALAR_11_WIDTH=32,C_INPUT_SCALAR_12_WIDTH=32,C_INPUT_SCALAR_13_WIDTH=32,C_INPUT_SCALAR_14_WIDTH=32,C_INPUT_SCALAR_15_WIDTH=32,C_OUTPUT_SCALAR_0_WIDTH=32,C_OUTPUT_SCALAR_1_WIDTH=32,C_OUTPUT_SCALAR_2_WIDTH=32,C_OUTPUT_SCALAR_3_WIDTH=32,C_OUTPUT_SCALAR_4_WIDTH=32,C_OUTPUT_SCALAR_5_WIDTH=32,C_OUTPUT_SCALAR_6_WIDTH=32,C_OUTPUT_SCALAR_7_WIDTH=32,C_OUTPUT_SCALAR_8_WIDTH=32,C_OUTPUT_SCALAR_9_WIDTH=32,C_OUTPUT_SCALAR_10_WIDTH=32,C_OUTPUT_SCALAR_11_WIDTH=32,C_OUTPUT_SCALAR_12_WIDTH=32,C_OUTPUT_SCALAR_13_WIDTH=32,C_OUTPUT_SCALAR_14_WIDTH=32,C_OUTPUT_SCALAR_15_WIDTH=32,C_N_OUTPUT_SCALARS=1,C_OUTPUT_SCALAR_DWIDTH=0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020,C_AP_OSCALAR_DIN_WIDTH=32,C_AP_OSCALAR_IO_DIN_WIDTH=32,C_ENABLE_STREAM_CLK=0,C_PRMRY_IS_ACLK_ASYNC=0,C_S_AXIS_HAS_TSTRB=0,C_S_AXIS_HAS_TKEEP=0,C_NONE=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 3,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000000",
C_AP_ISCALAR_DOUT_WIDTH => 96,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 1,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 32,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_iscalar_2_dout => ap_iscalar_2_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => '0',
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_set_0_if_0_arch;
|
mit
|
8bb4b0cf00a9179b72c8d574ab8b8770
| 0.635968 | 2.93746 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/ioblock3_e-rtl-a.vhd
| 1 | 11,515 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock3_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:23 wig Exp $
-- $Date: 2006/07/05 10:01:23 $
-- $Log: ioblock3_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:23 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock3_e
--
architecture rtl of ioblock3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc_g_i
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- Links ...
nand_out : out std_ulogic; -- Links ...
p_di : in std_ulogic; -- data in from pad
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- Links ...
nand_out : out std_ulogic; -- Links ...
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
component ioc_r_io3
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io3
do : in std_ulogic_vector(3 downto 0);
en : in std_ulogic_vector(3 downto 0);
nand_dir : in std_ulogic; -- Direction
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io3
);
end component;
-- ---------
component ioc_r_iou
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_iou
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nand_dir : in std_ulogic; -- Direction
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
p_pu : out std_ulogic; -- pull-up control
pu : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ioc_r_iou
);
end component;
-- ---------
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal ioseldi_0 : std_ulogic;
-- __I_NODRV_I signal ioseldi_1 : std_ulogic;
signal ioseldi_2 : std_ulogic;
signal ioseldi_3 : std_ulogic;
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_g_i_33
ioc_g_i_33: ioc_g_i
port map (
di => data_i33, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_33, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_i_33
-- Generated Instance Port Map for ioc_g_i_34
ioc_g_i_34: ioc_g_i
port map (
di => data_i34, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_34, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_i_34
-- Generated Instance Port Map for ioc_g_o_35
ioc_g_o_35: ioc_g_o
port map (
do => data_o35, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_do => pad_do_35, -- data out to pad
p_en => pad_en_35, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_o_35
-- Generated Instance Port Map for ioc_g_o_36
ioc_g_o_36: ioc_g_o
port map (
do => data_o36, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_do => pad_do_36, -- data out to pad
p_en => pad_en_36, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_o_36
-- Generated Instance Port Map for ioc_r_io3_39
ioc_r_io3_39: ioc_r_io3
port map (
do(0) => display_ls(0),
do(1) => display_ls(2),
do(2) => display_ls(4),
do(3) => display_ls(6),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_39, -- data in from pad
p_do => pad_do_39, -- data out to pad
p_en => pad_en_39, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
-- __I_NODRV_I sel(1) => __nodrv__/ioseldi_1, -- __I_BIT_TO_BUSPORT
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_r_io3_39
-- Generated Instance Port Map for ioc_r_io3_40
ioc_r_io3_40: ioc_r_io3
port map (
do(0) => display_ls(1),
do(1) => display_ls(3),
do(2) => display_ls(5),
do(3) => display_ls(7),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_40, -- data in from pad
p_do => pad_do_40, -- data out to pad
p_en => pad_en_40, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
sel(1) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_r_io3_40
-- Generated Instance Port Map for ioc_r_iou_31
ioc_r_iou_31: ioc_r_iou
port map (
di => d9_di(0), -- d9io
do => d9_do(0), -- d9io
en => d9_en(0), -- d9io
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_31, -- data in from pad
p_do => pad_do_31, -- data out to pad
p_en => pad_en_31, -- pad output enable
p_pu => pad_pu_31, -- pull-up control
pu => d9_pu(0) -- d9io
);
-- End of Generated Instance Port Map for ioc_r_iou_31
-- Generated Instance Port Map for ioc_r_iou_32
ioc_r_iou_32: ioc_r_iou
port map (
di => d9_di(1), -- d9io
do => d9_do(1), -- d9io
en => d9_en(1), -- d9io
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_32, -- data in from pad
p_do => pad_do_32, -- data out to pad
p_en => pad_en_32, -- pad output enable
p_pu => pad_pu_32, -- pull-up control
pu => d9_pu(1) -- d9io
);
-- End of Generated Instance Port Map for ioc_r_iou_32
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
4f1e679e69cada28ed5507fd3d8705ff
| 0.592445 | 2.377658 | false | false | false | false |
blutsvente/MIX
|
test/results/verilog/useconfname/ent_t-rtl-a.vhd
| 1 | 5,183 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:08:19 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/07/19 07:13:17 wig Exp $
-- $Date: 2005/07/19 07:13:17 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:17 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
-- Generated Generics for Entity ent_a
-- End of Generated Generics for Entity ent_a
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
02a4c39622b45dde7a7f3bb82b6af2ad
| 0.61721 | 2.797086 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_sync_module.vhd
| 1 | 40,635 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_sync_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-07-12 2.0 pankajk Added new ports iscalar_rqt_enable &
-- iscalar_rqt_enable to qualify with
-- iscalar_start & oscalar_start
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.async_fifo_dist_wt;
use axis_accelerator_adapter_v2_1_6.sync_ap_status;
use axis_accelerator_adapter_v2_1_6.cdc_sync;
entity xd_sync_module is
generic (
-- System generics:
C_FAMILY : string; -- Xilinx FPGA family
C_MAX_N_IARGS : integer;
C_MAX_N_OARGS : integer;
C_N_INPUT_ARGS : integer;
C_N_OUTPUT_ARGS : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MTBF_STAGES : integer;
C_MAX_N_ISCALARS : integer;
C_N_INPUT_SCALARS : integer;
C_MAX_N_OSCALARS : integer;
C_N_INOUT_SCALARS : integer;
C_MAX_N_IOSCALARS : integer;
C_N_OUTPUT_SCALARS : integer;
C_NONE : integer := 2);
port (
-- SLAVE AXI LITE:
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- Host command input port
host_cmd_data : in std_logic_vector(31 downto 0);
host_cmd_we : in std_logic;
host_cmd_rdy : out std_logic;
host_complete_re : in std_logic;
host_cmd_error : out std_logic;
---
iarg_rqt_enable : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
oarg_rqt_enable : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
---
status_ap_start : out std_logic;
status_ap_done : out std_logic;
status_ap_idle : out std_logic;
status_ap_ready : out std_logic;
status_ap_start_clr : in std_logic;
status_ap_done_clr : in std_logic;
status_ap_idle_clr : in std_logic;
status_ap_ready_clr : in std_logic;
---
status_iarg_rqt : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_ack : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_oarg_rqt : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_ack : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
---
ap_clk : in std_logic;
soft_rst : in std_logic;
ap_rst : in std_logic;
--- Control and status signals for multibuffers
mb_iarg_rdy : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
mb_iarg_done : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
mb_oarg_rdy : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
mb_oarg_done : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-- AP control handshaking
ap_start : out std_logic;
ap_ready : in std_logic;
ap_done : in std_logic;
ap_continue : out std_logic;
ap_idle : in std_logic;
ap_start_one_shot : out std_logic;
---
iscalar_rqt_enable : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
oscalar_rqt_enable : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
---
ap_iscalar_rdy : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
ap_iscalar_done : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
---
ap_oscalar_vld : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_oscalar_rdy : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0));
end entity;
architecture rtl of xd_sync_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
type state_type is (
idle,
apply_input_mask,
wait_start,
wait_done,
stop);
signal state : state_type;
signal ap_start_i : std_logic;
---------------------------------------
constant OPCODE_WIDTH : integer := 4;
constant ARG_MASK_LSB : integer := 0;
constant ARG_MASK_MSB : integer := 7;
constant SCALAR_MASK_LSB : integer := 8;
constant SCALAR_MASK_MSB : integer := 15;
constant OPCODE_LSB : integer := 16;
constant OPCODE_MSB : integer := OPCODE_LSB+OPCODE_WIDTH-1;
constant ISCALAR_MASK_LSB: integer := OPCODE_MSB+1;
constant ISCALAR_MASK_MSB: integer := ISCALAR_MASK_LSB+7;
-- input commands
constant UPDATE_INPUT : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0000";
constant UPDATE_OUTPUT : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0001";
constant EXECUTE_STEP : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0010";
constant EXECUTE_RESUME : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0100";
constant EXECUTE_STOP : std_logic_vector(OPCODE_WIDTH-1 downto 0) := "0101";
--
constant EXECUTE : std_logic_vector(1 downto 0) := "10";
constant IARG_UM_LSB : integer := 0;
constant OARG_UM_LSB : integer := 8;
constant ISCALAR_UM_LSB : integer := 16;
constant OSCALAR_UM_LSB : integer := 24;
-- pragma translate_off
type dbg_opcode_type is (
op_update_input,
op_update_output,
op_exec_step,
op_exec_resume,
op_exec_stop,
op_invalid);
signal dbg_opcode : dbg_opcode_type;
-- pragma translate_on
signal command_full : std_logic;
signal command : std_logic_vector(31 downto 0);
signal command_vld : std_logic;
signal command_rdy : std_logic;
--
signal arg_mask : std_logic_vector(7 downto 0);
signal scalar_mask : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal opcode : std_logic_vector(OPCODE_WIDTH-1 downto 0);
--
signal input_mask_we : std_logic;
signal input_mask_clr : std_logic;
signal output_mask_we : std_logic;
signal output_mask_clr : std_logic;
--
signal iarg_mask : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal oarg_mask : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal iscalar_mask : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal oscalar_mask : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
--
signal iarg_start : std_logic;
signal iarg_start_sync : std_logic;
signal oarg_start : std_logic;
signal oarg_start_sync : std_logic;
signal iscalar_start : std_logic;
signal iscalar_start_sync: std_logic;
signal oscalar_start : std_logic;
signal oscalar_start_sync : std_logic;
signal global_start : std_logic;
--
signal mb_iarg_done_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal mb_oarg_done_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
--
-- Core ap_start delayed version.
signal core_ap_start : std_logic;
signal set_ap_start : std_logic;
signal set_ap_start_r : std_logic;
signal clr_ap_start : std_logic;
signal run_continous : std_logic;
signal ap_cmd_error : std_logic;
signal host_cmd_error_i : std_logic;
signal axi_rst : std_logic;
--- Syncrhonizer signals
signal iarg_rqt_enable_sync : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal oarg_rqt_enable_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_start_i_sync : std_logic;
signal ap_done_sync : std_logic;
signal ap_idle_sync : std_logic;
signal ap_ready_sync : std_logic;
signal ap_cmd_error_sync : std_logic;
signal ap_rstn : std_logic;
signal ap_rst_vec : std_logic_vector(0 downto 0);
signal ap_rst_axi_sync : std_logic;
signal ap_rst_sync : std_logic_vector(0 downto 0);
signal axin_rst : std_logic;
constant C_EXTRA_SYNCS : integer := 1;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true";
begin
-- Active low ap_rst
ap_rstn <= not ap_rst;
----------------------
--- Reset Synchronizer
----------------------
-- EN_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
-- begin
--
--
-- XD_IARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 0,
-- C_FLOP_INPUT => 1,
-- C_VECTOR_WIDTH => C_MAX_N_IARGS,
-- C_MTBF_STAGES => C_MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => S_AXI_ACLK,
-- prmry_resetn => S_AXI_ARESETN,
-- prmry_in => '0',
-- prmry_vect_in => iarg_rqt_enable,
--
-- scndry_aclk => ap_clk,
-- scndry_resetn => ap_rstn,
-- scndry_out => open,
-- scndry_vect_out => iarg_rqt_enable_sync
-- );
--
--
-- XD_OARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 0,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => C_MAX_N_OARGS,
-- C_MTBF_STAGES => C_MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => S_AXI_ACLK,
-- prmry_resetn => S_AXI_ARESETN,
-- prmry_in => '0',
-- prmry_vect_in => oarg_rqt_enable,
--
-- scndry_aclk => ap_clk,
-- scndry_resetn => ap_rstn,
-- scndry_out => open,
-- scndry_vect_out => oarg_rqt_enable_sync
-- );
--
-- end generate EN_SYNC_GEN;
--
-- NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
-- begin
iarg_rqt_enable_sync <= iarg_rqt_enable;
oarg_rqt_enable_sync <= oarg_rqt_enable;
-- end generate NO_SYNC_GEN;
----------------------
--- Reset Synchronizer
----------------------
EN_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
AP_START_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_start_i,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_start_i_sync,
scndry_vect_out => open
);
AP_DONE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_done,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_done_sync,
scndry_vect_out => open
);
AP_IDLE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_idle,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_idle_sync,
scndry_vect_out => open
);
AP_READY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_ready,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_ready_sync,
scndry_vect_out => open
);
AP_CMDERR_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_cmd_error,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_cmd_error_sync,
scndry_vect_out => open
);
end generate EN_APCLK_LITE_SYNC_GEN;
NO_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
--
-- ap_start_i_sync <= ap_start_i;
-- ap_done_sync <= ap_done;
-- ap_idle_sync <= ap_idle;
-- ap_ready_sync <= ap_ready;
-- ap_cmd_error_sync <= ap_cmd_error;
--
AP_START_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2--C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_start_i,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_start_i_sync,
scndry_vect_out => open
);
AP_DONE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2--C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_done,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_done_sync,
scndry_vect_out => open
);
AP_IDLE_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2--C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_idle,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_idle_sync,
scndry_vect_out => open
);
AP_READY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2--C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_ready,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_ready_sync,
scndry_vect_out => open
);
AP_CMDERR_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2--C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rstn,
prmry_in => ap_cmd_error,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => ap_cmd_error_sync,
scndry_vect_out => open
);
end generate NO_APCLK_LITE_SYNC_GEN;
----------------------
--- Reset Synchronizer
----------------------
mb_iarg_done <= mb_iarg_done_i;
mb_oarg_done <= mb_oarg_done_i;
axin_rst <= not(S_AXI_ARESETN);
-- axi_rst <= not(S_AXI_ARESETN) or ap_rst;
-- ap_rst_vec(0) <= ap_rst;
--
-- rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => 1,
-- C_WIDTH => 1
-- )
-- PORT MAP (
-- RST => S_AXI_ARESETN,
-- CLK => S_AXI_ACLK,
-- D => ap_rst_vec,
-- Q => ap_rst_sync
-- );
-- process(S_AXI_ACLK)
-- begin
-- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- ap_rst_vec(0) <= ap_rst;
-- ap_rst_sync(0) <= ap_rst_vec(0);
-- end if;
-- end process;
-- process(S_AXI_ACLK, S_AXI_ARESETN)
-- begin
-- if(S_AXI_ARESETN='0') then
-- axi_rst <= '1';
-- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- axi_rst <= ap_rst_axi_sync;
-- end if;
-- end process;
ap_rst_axi_sync1 : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ap_rst,
prmry_vect_in => (others=>'0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => axi_rst,
scndry_vect_out => open
);
---------------------------------------
COMMAND_FIFO_NEW : entity axis_accelerator_adapter_v2_1_6.async_fifo_dist_inst
generic map (
C_FAMILY => C_FAMILY,
DEPTH => 32,
WIDTH => 32)
port map (
din => host_cmd_data,
din_vld => host_cmd_we,
din_rdy => host_cmd_rdy,
wr_clk => S_AXI_ACLK,
wr_rst => axi_rst,
dout => command,
dout_vld => command_vld,
dout_rdy => command_rdy,
rd_clk => ap_clk,
rd_rst => ap_rst);
arg_mask <= command(ARG_MASK_MSB downto ARG_MASK_LSB);
scalar_mask <= command(ISCALAR_MASK_MSB downto ISCALAR_MASK_LSB) & command(SCALAR_MASK_MSB downto SCALAR_MASK_LSB);
--scalar_mask <= command(SCALAR_MASK_MSB downto SCALAR_MASK_LSB);
opcode <= command(OPCODE_MSB downto OPCODE_LSB);
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(ap_rst = '1' or input_mask_clr = '1') then
iarg_mask <= (others => '0');
iscalar_mask <= (others => '0');
elsif(input_mask_we = '1') then
iarg_mask <= iarg_mask or arg_mask;
iscalar_mask <= iscalar_mask or scalar_mask;
end if;
end if;
end process;
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(ap_rst = '1' or output_mask_clr = '1') then
oarg_mask <= (others => '0');
oscalar_mask <= (others => '0');
elsif(output_mask_we = '1') then
oarg_mask <= oarg_mask or arg_mask;
oscalar_mask <= oscalar_mask or scalar_mask(15 downto 0);
end if;
end if;
end process;
----------------------------------------
USE_INPUT_ARGS_GEN : if (C_N_INPUT_ARGS > 0) generate
begin
iarg_start <= and_reduce(mb_iarg_rdy(C_N_INPUT_ARGS-1 downto 0) or not(iarg_rqt_enable_sync(C_N_INPUT_ARGS-1 downto 0)));
end generate USE_INPUT_ARGS_GEN;
NO_INPUT_ARGS_GEN : if (C_N_INPUT_ARGS = 0) generate
begin
iarg_start <= '1';
end generate NO_INPUT_ARGS_GEN;
USE_OUTPUT_ARGS_GEN : if (C_N_OUTPUT_ARGS > 0) generate
begin
oarg_start <= and_reduce(mb_oarg_rdy(C_N_OUTPUT_ARGS-1 downto 0) or not(oarg_rqt_enable_sync(C_N_OUTPUT_ARGS-1 downto 0)));
end generate USE_OUTPUT_ARGS_GEN;
NO_OUTPUT_ARGS_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
oarg_start <= '1';
end generate NO_OUTPUT_ARGS_GEN;
USE_INPUT_SCALAR_GEN1 : if (C_N_INPUT_SCALARS+C_N_INOUT_SCALARS > 0 ) generate
begin
iscalar_start <= and_reduce((ap_iscalar_rdy(C_MAX_N_ISCALARS-1 downto 0)) or not(iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0)));
--iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0) or not(iscalar_rqt_enable(C_N_INPUT_SCALARS-1 downto 0))) and and_reduce(ap_iscalar_rdy(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) or not(iscalar_rqt_enable(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS)));
end generate USE_INPUT_SCALAR_GEN1;
-- USE_INPUT_SCALAR_GEN2 : if (C_N_INPUT_SCALARS > 0 and C_N_INOUT_SCALARS = 0) generate
-- begin
-- --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0));
-- iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0) or not(iscalar_rqt_enable(C_N_INPUT_SCALARS-1 downto 0)));
-- end generate USE_INPUT_SCALAR_GEN2;
--
-- USE_INPUT_SCALAR_GEN3 : if (C_N_INPUT_SCALARS = 0 and C_N_INOUT_SCALARS > 0) generate
-- begin
-- --iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INPUT_SCALARS-1 downto 0));
-- iscalar_start <= and_reduce(ap_iscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) or not(iscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS)));
-- end generate USE_INPUT_SCALAR_GEN3;
NO_INPUT_SCALAR_GEN : if (C_N_INPUT_SCALARS = 0 and C_N_INOUT_SCALARS = 0) generate
begin
iscalar_start <= '1';
end generate NO_INPUT_SCALAR_GEN;
USE_OUTPUT_SCALAR_GEN1 : if (C_N_OUTPUT_SCALARS+C_N_INOUT_SCALARS > 0 ) generate
begin
oscalar_start <= and_reduce((ap_oscalar_rdy(C_MAX_N_OSCALARS-1 downto 0)) or not(oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0)));
--oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0) or not(oscalar_rqt_enable(C_N_OUTPUT_SCALARS-1 downto 0)));
end generate USE_OUTPUT_SCALAR_GEN1;
-- USE_OUTPUT_SCALAR_GEN2 : if (C_N_OUTPUT_SCALARS > 0 and C_N_INOUT_SCALARS > 0) generate
-- begin
-- --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0));
-- oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) or not(oscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS))) and and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0) or not(oscalar_rqt_enable(C_N_OUTPUT_SCALARS-1 downto 0)));
-- end generate USE_OUTPUT_SCALAR_GEN2;
--
-- USE_OUTPUT_SCALAR_GEN3 : if (C_N_OUTPUT_SCALARS = 0 and C_N_INOUT_SCALARS > 0) generate
-- begin
-- --oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_OUTPUT_SCALARS-1 downto 0));
-- oscalar_start <= and_reduce(ap_oscalar_rdy(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) or not(oscalar_rqt_enable(C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS)));
-- end generate USE_OUTPUT_SCALAR_GEN3;
NO_OUTPUT_SCALAR_GEN : if (C_N_OUTPUT_SCALARS = 0 and C_N_INOUT_SCALARS = 0) generate
begin
oscalar_start <= '1';
end generate NO_OUTPUT_SCALAR_GEN;
-- pragma translate_off
process(opcode)
begin
dbg_opcode <= op_invalid;
case opcode is
when UPDATE_INPUT => dbg_opcode <= op_update_input;
when UPDATE_OUTPUT => dbg_opcode <= op_update_output;
when EXECUTE_STEP => dbg_opcode <= op_exec_step;
when EXECUTE_RESUME => dbg_opcode <= op_exec_resume;
when EXECUTE_STOP => dbg_opcode <= op_exec_stop;
when others => null;
end case;
end process;
-- pragma translate_on
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
global_start <= iarg_start and oarg_start and iscalar_start and oscalar_start;
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate
begin
AP_IARGSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rst,
prmry_in => iarg_start,
prmry_vect_in => (others=>'0'),
scndry_aclk => ap_clk,
scndry_resetn => ap_rst,
scndry_out => iarg_start_sync,
scndry_vect_out => open
);
AP_OARGSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => S_AXI_ARESETN,
prmry_in => oarg_start,
prmry_vect_in => (others=>'0'),
scndry_aclk => ap_clk,
scndry_resetn => ap_rst,
scndry_out => oarg_start_sync,
scndry_vect_out => open
);
AP_ISCALARSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => S_AXI_ARESETN,
prmry_in => iscalar_start,
prmry_vect_in => (others=>'0'),
scndry_aclk => ap_clk,
scndry_resetn => ap_rst,
scndry_out => iscalar_start_sync,
scndry_vect_out => open
);
AP_OSCALARSTART_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => S_AXI_ARESETN,
prmry_in => oscalar_start,
prmry_vect_in => (others=>'0'),
scndry_aclk => ap_clk,
scndry_resetn => ap_rst,
scndry_out => oscalar_start_sync,
scndry_vect_out => open
);
global_start <= iarg_start_sync and oarg_start_sync and iscalar_start_sync and oscalar_start_sync;
end generate NEW_INTRO;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
state <= idle;
ap_start_i <= '0';
ap_start_one_shot <= '0';
run_continous <= '0';
elsif(ap_clk'event and ap_clk = '1') then
ap_start_i <= '0';
ap_start_one_shot <= '0';
case state is
when idle =>
-- Wait until there is a command available
if (command_vld = '1') then
case opcode is
when EXECUTE_STEP =>
state <= wait_start;
when EXECUTE_RESUME =>
run_continous <= '1';
state <= wait_start;
when others =>
end case;
end if;
when apply_input_mask =>
-- In this state we apply the command. For input arguments and
-- scalars we give a "done" of the elements.
state <= wait_start;
when wait_start =>
if (run_continous = '0') then
-- accelerator start is given when:
-- 1.- all input arguments have data valid to process.
-- 2.- all ouput arguments have free memory where to wite the
-- processed data.
if (global_start = '1') then
state <= wait_done;
ap_start_i <= '1';
ap_start_one_shot <= '1';
end if;
else
if (command_vld = '1') then
case opcode is
when EXECUTE_STOP =>
run_continous <= '0';
state <= idle;
when others =>
state <= stop;
end case;
elsif (global_start = '1') then
state <= wait_done;
ap_start_i <= '1';
ap_start_one_shot <= '1';
end if;
end if;
when wait_done =>
if(ap_done = '1') then
if (run_continous = '0') then
state <= idle;
else
state <= apply_input_mask;
end if;
end if;
when others =>
end case;
end if;
end process;
ap_start <= core_ap_start;
process(state, global_start, run_continous, command_vld, opcode, iarg_mask, iscalar_mask,
arg_mask, scalar_mask,
ap_done, oarg_mask, oscalar_mask)
begin
command_rdy <= '0';
input_mask_we <= '0';
output_mask_we <= '0';
input_mask_clr <= '0';
output_mask_clr <= '0';
mb_iarg_done_i <= (others => '0');
ap_iscalar_done <= (others => '0');
mb_oarg_done_i <= (others => '0');
ap_oscalar_vld <= (others => '0');
set_ap_start <= '0';
ap_cmd_error <= '0';
case state is
when idle =>
command_rdy <= command_vld;
if(command_vld = '1') then
case opcode is
when UPDATE_INPUT =>
input_mask_we <= '1';
mb_iarg_done_i <= arg_mask;
ap_iscalar_done <= scalar_mask;
when UPDATE_OUTPUT =>
output_mask_we <= '1';
when EXECUTE_STEP =>
when EXECUTE_RESUME =>
when EXECUTE_STOP =>
when others =>
end case;
end if;
when apply_input_mask =>
mb_iarg_done_i <= iarg_mask;
ap_iscalar_done <= iscalar_mask;
when wait_start =>
if (run_continous = '0') then
set_ap_start <= global_start;
else
if (command_vld = '1') then
command_rdy <= '1';
if (opcode = EXECUTE_STOP) then
input_mask_clr <= '1';
output_mask_clr <= '1';
else
ap_cmd_error <= '1';
end if;
else
set_ap_start <= global_start;
end if;
end if;
when wait_done =>
if(ap_done = '1') then
-- Toggle the output argument multibuffer (if enabled)
if (C_N_OUTPUT_ARGS > 0) then
mb_oarg_done_i(C_N_OUTPUT_ARGS-1 downto 0) <= oarg_mask(C_N_OUTPUT_ARGS-1 downto 0);
end if;
-- Write values in output FIFOs (if enabled)
if (C_N_OUTPUT_SCALARS+C_N_INOUT_SCALARS > 0) then
ap_oscalar_vld(C_MAX_N_OSCALARS-1 downto 0) <= oscalar_mask(C_MAX_N_OSCALARS-1 downto 0);
end if;
-- if (C_N_INOUT_SCALARS > 0) then
-- ap_oscalar_vld(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= oscalar_mask(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS);
-- end if;
-- clear input/output masks before we start a new iteration
input_mask_clr <= not(run_continous);
output_mask_clr <= not(run_continous);
end if;
when others =>
end case;
end process;
clr_ap_start <= ap_ready;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
set_ap_start_r <= '0';
elsif(ap_clk'event and ap_clk = '1') then
set_ap_start_r <= set_ap_start;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
core_ap_start <= '0';
elsif(ap_clk'event and ap_clk = '1') then
-- Core ap_start delayed version.
if(core_ap_start = '0') then
core_ap_start <= set_ap_start_r;
else
core_ap_start <= not(clr_ap_start);
end if;
end if;
end process;
---------------------------
SYNC_AP_START_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status
port map (
rst => soft_rst,
ap_clk => S_AXI_ACLK,
ap_flag => ap_start_i_sync,
axi_clk => S_AXI_ACLK,
flag => status_ap_start,
flag_clr => status_ap_start_clr);
SYNC_AP_DONE_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status
port map (
rst => soft_rst,
ap_clk => S_AXI_ACLK,
ap_flag => ap_done_sync,
axi_clk => S_AXI_ACLK,
flag => status_ap_done,
flag_clr => status_ap_done_clr);
STATUS_AP_IDLE_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status
port map (
rst => soft_rst,
ap_clk => S_AXI_ACLK,
ap_flag => ap_idle_sync,
axi_clk => S_AXI_ACLK,
flag => status_ap_idle,
flag_clr => status_ap_idle_clr);
STATUS_AP_READY_I : entity axis_accelerator_adapter_v2_1_6.sync_ap_status
port map (
rst => soft_rst,
ap_clk => S_AXI_ACLK,
ap_flag => ap_ready_sync,
axi_clk => S_AXI_ACLK,
flag => status_ap_ready,
flag_clr => status_ap_ready_clr);
SYNC_AP_CMD_ERROR_I : entity work.sync_ap_status
port map (
rst => soft_rst,
ap_clk => S_AXI_ACLK,
ap_flag => ap_cmd_error_sync,
axi_clk => S_AXI_ACLK,
flag => host_cmd_error_i,
flag_clr => host_cmd_error_i);
host_cmd_error <= host_cmd_error_i;
-- TODO:
status_iarg_rqt <= (others => '0');
status_iarg_ack <= (others => '0');
status_oarg_rqt <= (others => '0');
status_oarg_ack <= (others => '0');
ap_continue <= ap_done;
end rtl;
|
mit
|
84ae004810311120a9d08fb95e4d9d03
| 0.498339 | 3.566977 | false | false | false | false |
blutsvente/MIX
|
test/results/open/inst_t_e-rtl-a.vhd
| 1 | 3,949 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 16:43:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../open.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
open_bit : out std_ulogic;
open_bus : out std_ulogic_vector(3 downto 0);
open_bus_9 : out std_ulogic_vector(5 downto 0);
open_in_bit_11 : in std_ulogic;
open_in_bus_10 : in std_ulogic_vector(7 downto 0);
open_part12 : out std_ulogic_vector(6 downto 0); -- from 5 to 3
open_part13 : out std_ulogic_vector(6 downto 0);
openport14 : out std_ulogic_vector(2 downto 0); -- check width and type
wire_open : out std_ulogic_vector(5 downto 0);
wire_open_in : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
mix_key_open : out std_ulogic; -- replace name
non_open : in std_ulogic_vector(2 downto 0);
non_open_bit : in std_ulogic;
open_bit_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
open_bit_3 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
open_bit_4 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal non_open : std_ulogic_vector(2 downto 0);
signal non_open_bit : std_ulogic;
signal wire_open : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
open_bit => open,
open_bus => open,
open_bus_9 => open,
open_in_bit_11 => open,
open_in_bus_10 => open,
open_part12(2 downto 0) => non_open, -- __W_PORT
open_part12(5 downto 3) => open, -- __W_PORT -- from 5 to 3
open_part12(6) => non_open_bit, -- __I_BIT_TO_BUSPORT
open_part13(2 downto 0) => non_open, -- __W_PORT
open_part13(3) => open, -- __I_BIT_TO_BUSPORT
open_part13(4) => open, -- __I_BIT_TO_BUSPORT
open_part13(5) => non_open_bit, -- __I_BIT_TO_BUSPORT
open_part13(6) => open, -- __I_BIT_TO_BUSPORT
openport14 => open, -- check width and type
wire_open(3 downto 0) => wire_open, -- __W_PORT
wire_open(5 downto 4) => open, -- __W_PORT
wire_open_in => wire_open
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
mix_key_open => open, -- replace name
non_open => non_open,
non_open_bit => non_open_bit,
open_bit_2 => open,
open_bit_3 => open,
open_bit_4 => open
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
947aa0802a360a219030acf681537c23
| 0.601925 | 2.843053 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_ec_e-rtl-a.vhd
| 1 | 3,480 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:03 wig Exp $
-- $Date: 2004/04/06 10:50:03 $
-- $Log: inst_ec_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:03 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ec_e
--
architecture rtl of inst_ec_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eca_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eca_e
nreset : in std_ulogic;
nreset_s : in std_ulogic;
v_select : in std_ulogic_vector(5 downto 0)
-- End of Generated Port for Entity inst_eca_e
);
end component;
-- ---------
component inst_ecb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ecb_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecb_e
);
end component;
-- ---------
component inst_ecc_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ecc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecc_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
v_select <= p_mix_v_select_5_0_gi; -- __I_I_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eca
inst_eca: inst_eca_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
v_select => v_select -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_eca
-- Generated Instance Port Map for inst_ecb
inst_ecb: inst_ecb_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ecb
-- Generated Instance Port Map for inst_ecc
inst_ecc: inst_ecc_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ecc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3e4b31832debc2041b77309b98b05bb2
| 0.616092 | 3.198529 | false | false | false | false |
blutsvente/MIX
|
test/results/sigport/use/ent_t-rtl-a.vhd
| 1 | 5,101 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/07/15 16:20:07 wig Exp $
-- $Date: 2005/07/15 16:20:07 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:07 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
-- Generated Generics for Entity ent_b
-- End of Generated Generics for Entity ent_b
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic;
port_b_5_2 : in std_ulogic;
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
507aeca03668160a9c521ca08357f72d
| 0.61537 | 2.796601 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter7.vhd
| 1 | 4,443 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter7.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter7 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_counter7;
ARCHITECTURE SYN OF lpm_counter7 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(8 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 286,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 9
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "286"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "286"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter7.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter7.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter7.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter7.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter7_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
d931626a3285a9ce29f530526cebf45e
| 0.651812 | 3.687137 | false | false | false | false |
DacHt/CU_Droptest
|
component/Actel/DirectCore/COREUART/5.6.102/rtl/vhdl/test/common/misc.vhd
| 1 | 13,133 |
-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: PRINTF SUPPORT for cores using std_logic_arith or std_logic_unsigned
--
-- Revision Information:
-- Date Description
-- 01Sep07 Initial Release
-- 14Sep07 Updated for 1.2 functionality
-- 25Sep07 Updated for 1.3 functionality
-- 09Nov07 Updated for 1.4 functionality
-- 08May08 2.0 for Soft IP Usage
-- 22Oct08 3.0 Moved into SVN Properly (TEXTIO Project)
--
--
-- SVN Revision Information:
-- SVN $Revision: 3758 $
-- SVN $Date: 2008-10-22 01:56:45 -0700 (Wed, 22 Oct 2008) $
--
--
-- Resolved SARs
-- SAR Date Who Description
--
--
-- Notes:
--
-- *********************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package misc is
-- synthesis translate_off
type INTEGER_ARRAY is array ( INTEGER range <>) of INTEGER;
subtype NIBBLE is std_logic_vector ( 3 downto 0);
subtype BYTE is std_logic_vector ( 7 downto 0);
subtype WORD is std_logic_vector (15 downto 0);
subtype DWORD is std_logic_vector (31 downto 0);
subtype QWORD is std_logic_vector (63 downto 0);
type BYTE_ARRAY is array ( INTEGER range <>) of BYTE;
type WORD_ARRAY is array ( INTEGER range <>) of WORD;
type DWORD_ARRAY is array ( INTEGER range <>) of DWORD;
type TIME_ARRAY is array ( INTEGER range <>) of TIME;
type BOOLEAN_VECTOR is array ( INTEGER range <>) of BOOLEAN;
constant ZERO : DWORD := (others => '0');
constant ZERO16 : WORD := (others => '0');
constant ALLONES : std_logic_vector (31 downto 0) := (others => '0');
constant UNKNOWN : std_logic_vector (31 downto 0) := (others => 'U');
procedure waitclocks(signal clock : std_logic; N : INTEGER);
function to_std_logic( x: UNSIGNED ) return std_logic_vector;
function to_unsigned( x: std_logic_vector ) return UNSIGNED;
function to_std_logic( tmp : INTEGER ) return std_logic;
function to_std_logic_invert( tmp : INTEGER ) return std_logic;
function to_std_logic( tmp : BOOLEAN ) return std_logic;
function to_std_logic_invert( tmp : BOOLEAN ) return std_logic;
function to_boolean( tmp : integer ) return BOOLEAN;
function to_boolean( tmp : std_logic ) return BOOLEAN;
function to_boolean_invert( tmp : std_logic ) return BOOLEAN;
function to_integer( tmp : boolean ) return INTEGER;
function to_byte ( x : INTEGER ) return BYTE;
function to_word ( x : INTEGER ) return WORD;
function to_dword ( x : INTEGER ) return DWORD;
function to_byte ( str : STRING ) return BYTE;
function to_word ( str : STRING ) return WORD;
function to_dword ( str : STRING ) return DWORD;
function to_integer ( din : std_logic_vector ) return integer;
function init_data( seed : INTEGER; size : INTEGER) return DWORD_ARRAY;
function init_data( seed : STRING; size : INTEGER) return DWORD_ARRAY;
function maxval (a,b : integer) return integer;
function minval (a,b : integer) return integer;
function absval (a : integer) return integer;
function muxop ( s: boolean; a,b : integer) return integer;
function is_hex( str : STRING ) return BOOLEAN;
function to_uppercase( c : character) return character;
function onoff( x : boolean) return string;
function notonoff( x : boolean) return string;
function decode_params( str : string ) return INTEGER_ARRAY;
procedure getstring( para : out string; str : string; pos : inout integer);
function debug_level ( x ,y : integer) return boolean;
function to_01( tmp : std_logic ) return std_logic;
function to_01( tmp : std_logic_vector ) return std_logic_vector;
-- synthesis translate_on
end misc;
-- synthesis translate_off
package body misc is
---------------------------------------------------------------------
-- Handle UNSIGNED to std_logic_vector conversions
--
function to_std_logic( x: UNSIGNED ) return std_logic_vector is
variable y: std_logic_vector(x'range);
begin
for i in x'range loop
y(i) := x(i);
end loop;
return(y);
end to_std_logic;
function to_unsigned( x: std_logic_vector ) return UNSIGNED is
variable y: UNSIGNED(x'range);
begin
for i in x'range loop
y(i) := x(i);
end loop;
return(y);
end to_unsigned;
---------------------------------------------------------------------
-- Miscellanous Conversions
--
function to_integer( tmp : boolean ) return INTEGER is
begin
if tmp then return (1);
else return (0);
end if;
end to_integer;
function to_std_logic_invert( tmp : INTEGER ) return std_logic is
begin
if tmp=1 then return ('0');
else return ('1');
end if;
end to_std_logic_invert;
function to_std_logic( tmp : INTEGER ) return std_logic is
begin
if tmp=1 then return ('1');
else return ('0');
end if;
end to_std_logic;
function to_std_logic_invert( tmp : BOOLEAN ) return std_logic is
begin
if tmp then return ('0');
else return ('1');
end if;
end to_std_logic_invert;
function to_std_logic( tmp : BOOLEAN ) return std_logic is
begin
if tmp then return ('1');
else return ('0');
end if;
end to_std_logic;
function to_boolean_invert( tmp : std_logic ) return BOOLEAN is
begin
if to_X01(tmp)='0' then return (TRUE);
else return (FALSE);
end if;
end to_boolean_invert;
function to_boolean( tmp : std_logic ) return BOOLEAN is
begin
if to_X01(tmp)='1' then return (TRUE);
else return (FALSE);
end if;
end to_boolean;
function to_boolean( tmp : integer ) return BOOLEAN is
begin
if tmp/=0 then return (TRUE);
else return (FALSE);
end if;
end to_boolean;
function to_integer ( din : std_logic_vector ) return integer is
variable xv : std_logic_vector(31 downto 0);
variable x : integer;
begin
x := 0;
if din'length/=32 then
x := conv_integer( din);
elsif din(31) = '0' then
x := conv_integer( din (30 downto 0));
else
for i in 0 to 30 loop
xv(i) := not din(i);
end loop;
x := conv_integer( xv (30 downto 0));
x := x + 1;
x := -1 * x;
end if;
return(x);
end to_integer;
procedure waitclocks(signal clock : std_logic;
N : INTEGER) is
begin
if N>0 then
for i in 1 to N loop
wait until clock'event and clock='0';
end loop;
end if;
end waitclocks;
function to_byte ( x : INTEGER ) return BYTE is
variable x1 : BYTE;
begin
x1 := conv_std_logic_vector( x,8);
return(x1);
end to_byte;
function to_word ( x : INTEGER ) return WORD is
variable x1 : WORD;
begin
x1 := conv_std_logic_vector( x,16);
return(x1);
end to_word;
function to_dword ( x : INTEGER ) return DWORD is
variable x1 : DWORD;
begin
x1 := conv_std_logic_vector( x,32);
return(x1);
return(x1);
end to_dword;
function to_byte( str : STRING ) return BYTE is
variable str1 : string ( 1 to 2);
variable x : INTEGER;
variable dw : byte;
begin
str1 := str;
for i in 1 to 2 loop
case str1(i) is
when '0' to '9' => x:= CHARACTER'POS(str1(i)) - CHARACTER'POS('0');
when 'A' to 'F' => x:= 10 + CHARACTER'POS(str1(i)) - CHARACTER'POS('A');
when 'a' to 'z' => x:= 10 + CHARACTER'POS(str1(i)) - CHARACTER'POS('a');
when others => assert FALSE
report "Illegal Character in the Hex String"
severity failure;
end case;
dw(11- (i*4) downto 8 - (i*4) ) := conv_std_logic_vector(x,4);
end loop;
return(dw);
end to_byte;
function to_word( str : STRING ) return WORD is
variable str1 : string (1 to 4);
variable dw : word;
begin
str1 := str;
dw(15 downto 8) := to_byte( str1(1 to 2));
dw( 7 downto 0) := to_byte( str1(3 to 4));
return(dw);
end to_word;
function to_dword( str : STRING ) return DWORD is
variable str1 : string (1 to 8);
variable dw : dword;
begin
str1 := str;
dw(31 downto 16) := to_word( str1(1 to 4));
dw(15 downto 0) := to_word( str1(5 to 8));
return(dw);
end to_dword;
function init_data( seed : INTEGER; size : INTEGER) return DWORD_ARRAY is
variable xdata : DWORD_ARRAY (0 to 4095);
begin
-- In case there are any 16#FFFFFFFF# type constants Causes VSS to complain
assert seed>=0
report "INIT_DATA with integer Seed cannot be negative"
severity failure;
for i in 0 to size-1 loop
xdata(i) := to_dword(seed+i);
end loop;
return(xdata(0 to size-1));
end init_data;
function init_data( seed : STRING; size : INTEGER) return DWORD_ARRAY is
variable xdata : DWORD_ARRAY (0 to 4095);
variable seedxx : DWORD;
begin
seedxx := to_dword(seed);
for i in 0 to size-1 loop
xdata(i) := seedxx +i ;
end loop;
return(xdata(0 to size-1));
end init_data;
function maxval( a,b : integer) return integer is
begin
if (a>b) then return(a);
else return(b);
end if;
end maxval;
function minval( a,b : integer) return integer is
begin
if (a<b) then return(a);
else return(b);
end if;
end minval;
function absval( a : integer) return integer is
begin
if (a>0) then return(a);
else return(-a);
end if;
end absval;
function muxop ( s: boolean; a,b : integer) return integer is
begin
if s then return(a);
else return(b);
end if;
end muxop;
function is_hex( str : STRING ) return BOOLEAN is
variable ok : boolean;
variable str1 : string ( 1 to 2);
begin
ok := TRUE;
str1 := str;
for i in 1 to 2 loop
case str1(i) is
when '0' to '9' =>
when 'A' to 'F' =>
when 'a' to 'z' =>
when others => OK := FALSE;
end case;
end loop;
return(ok);
end is_hex;
function to_uppercase( c : character) return character is
variable ok : boolean;
variable cuc : character;
begin
case c is
when 'a' to 'z' => cuc := character'val(character'pos(c)-32);
when others => cuc := c;
end case;
return(cuc);
end to_uppercase;
function onoff( x : boolean) return string is
begin
if X then return("On");
else return("Off");
end if;
end onoff;
function notonoff( x : boolean) return string is
begin
if not X then return("On");
else return("Off");
end if;
end notonoff;
--------------------------------------------------------------------
-- returns no of params, para1, para2 etc
function decode_params( str : string) return INTEGER_ARRAY is
variable pos : INTEGER;
variable PARAMS : INTEGER_ARRAY(0 to 9);
variable i,x : INTEGER;
variable ERR : BOOLEAN;
variable BASE : INTEGER;
variable c : Character;
begin
pos := 2;
i := 0;
ERR := FALSE;
PARAMS := ( others => 0 );
while str(pos)/=NUL and not ERR loop
while str(pos)=' ' loop
pos := pos+1;
end loop;
x := 0;
BASE := 10;
c := str(pos);
while c/=' ' and c/=NUL and c/=',' and not ERR loop
case str(pos) is
when '0' to '9' => x :=x * BASE + character'pos(c) - character'pos('0');
when 'A' to 'F' => BASE := 16;
x :=x * BASE + 10 + character'pos(c) - character'pos('A');
when 'a' to 'f' => BASE := 16;
x :=x * BASE + 10 + character'pos(c) - character'pos('a');
when '#' => BASE := 16;
when others => ERR := TRUE;
--printf("Illegal character POS %d:",fmt(pos)&fmt(str));
end case;
pos := pos +1;
c := str(pos);
end loop;
i := i + 1;
PARAMS(i) := x;
end loop;
if ERR then
PARAMS(0) := 0;
else
PARAMS(0) := i;
end if;
-- for i in 0 to PARAMS(0) loop
-- printf("Got %d",fmt(params(i)));
-- end loop;
return(PARAMS);
end decode_params;
procedure getstring( para : out string; str : string; pos : inout integer) is
variable i,x : INTEGER;
variable ERR : BOOLEAN;
variable BASE : INTEGER;
variable c : Character;
begin
i := 1;
ERR := FALSE;
for i in para'range loop
para(i) := NUL;
end loop;
while str(pos)=' ' loop
pos := pos+1;
end loop;
while str(pos) /= ' ' and str(pos)/=',' and str(pos)/=NUL and str(pos)/=';' loop
para(i) := str(pos);
i := i + 1;
pos := pos + 1;
end loop;
end getstring;
function to_01( tmp : std_logic ) return std_logic is
begin
if tmp='1' then return ('1');
else return ('0');
end if;
end to_01;
function to_01( tmp : std_logic_vector ) return std_logic_vector is
variable ret : std_logic_vector(tmp'range);
begin
ret := ( others => '0');
for i in tmp'range loop
if tmp(i)='1' then
ret(i) := '1';
end if;
end loop;
return(ret);
end to_01;
function debug_level ( x ,y : integer) return boolean is
begin
if x>=y then return(TRUE);
else return(FALSE);
end if;
end debug_level;
end misc;
-- synthesis translate_on
|
mit
|
57d7380fcdb8da7250f0494e6296c1fb
| 0.608239 | 3.379568 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/inst/inst_t_e-rtl-a.vhd
| 1 | 3,072 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- Change parent to verilog
-- No Generated Generics
-- Generated Generics for Entity inst_b_e
-- End of Generated Generics for Entity inst_b_e
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- Change parent to verilog
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
dee74b419dbf5acb06f468e2a2a21b03
| 0.608073 | 2.991237 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/20051121a/ent_b-struct-a.vhd
| 1 | 3,485 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of ent_b
--
-- Generated
-- by: wig
-- on: Fri Jul 7 06:37:54 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-struct-a.vhd,v 1.4 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: ent_b-struct-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of ent_b
--
architecture struct of ent_b is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba -- is i_padframe / hier inst_ba inst_ba inst_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_ba
sc_p_1 : in std_ulogic; -- bad conection bits detected
sc_p_2 : in std_ulogic_vector(31 downto 0) -- reverse order
-- End of Generated Port for Entity ent_ba
);
end component;
-- ---------
component ent_bb -- is i_padframe / hier inst_bb inst_bb inst_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_bb
sc_p_3 : in std_ulogic_vector(31 downto 0); -- reverse order
-- multiline comments
sc_p_4 : in std_ulogic_vector(31 downto 0) -- reverse order
-- multiline comments
-- line 3
-- line 4
-- line 5
-- line 6
-- line 7
-- line 8
-- line 9
-- line 10
-- ...[cut]...
-- End of Generated Port for Entity ent_bb
);
end component;
-- ---------
--
-- Generated Signal List
--
signal sc_sig_1 : std_ulogic_vector; -- __W_PORT_SIGNAL_MAP_REQ
signal sc_sig_2 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sc_sig_4 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
sc_sig_1 <= p_mix_sc_sig_1_gi; -- __I_I_BIT_PORT
sc_sig_2 <= p_mix_sc_sig_2_gi; -- __I_I_BUS_PORT
sc_sig_4 <= p_mix_sc_sig_4_gi; -- __I_I_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba -- is i_padframe / hier inst_ba inst_ba inst_b
port map (
sc_p_1 => sc_sig_1, -- bad conection bits detected
sc_p_2 => sc_sig_2 -- reverse orderreverse order
-- multiline comments
);
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb -- is i_padframe / hier inst_bb inst_bb inst_b
port map (
sc_p_3 => sc_sig_2, -- reverse orderreverse order
-- multiline comments
sc_p_4 => sc_sig_4 -- reverse order
-- multiline comments
-- line 3
-- line 4
-- line 5
-- line 6
-- line 7
-- line 8
-- line 9
-- line 10
-- ...[cut]...
);
-- End of Generated Instance Port Map for inst_bb
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
b041336bb7624f6e2e05fa6a74803fd9
| 0.57934 | 3.0121 | false | false | false | false |
mitchsm/nvc
|
test/regress/jcore2.vhd
| 3 | 2,384 |
package data_bus_pkg is
type data_bus_device_t is (
DEV_NONE
,DEV_PIO
,DEV_SPI
,DEV_AIC
,DEV_UART0
,DEV_UART1
,DEV_UARTGPS
,DEV_SRAM
,DEV_DDR
,DEV_BL0
,DEV_EMAC
,DEV_I2C
);
type ext_bus_device_t is (
DEV_BL0,
DEV_EMAC,
DEV_I2C,
DEV_DDR
);
type ext_to_int_data_bus_t is array(ext_bus_device_t'left to ext_bus_device_t'right) of data_bus_device_t;
-- arrays for mapping mcu_lib's data bus and irq ports to the internal versions
constant ext_to_int_data : ext_to_int_data_bus_t := (
DEV_BL0 => DEV_BL0,
DEV_EMAC => DEV_EMAC,
DEV_I2C => DEV_I2C,
DEV_DDR => DEV_NONE
);
end data_bus_pkg;
-------------------------------------------------------------------------------
package monitor_pkg is
type timeout_t is record
cnt : integer range 0 to 10;
end record;
type cnt_reg_t is record
a : bit;
cnt : integer range 0 to 10;
end record;
constant CNT_REG_RESET : cnt_reg_t := ('0',0);
end package;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
entity timeout_cnt is
port(
clk : in bit;
rst : in bit;
timeout : out timeout_t
);
end timeout_cnt;
architecture structure of timeout_cnt is
signal this_c : cnt_reg_t;
signal this_r : cnt_reg_t := CNT_REG_RESET;
begin
counter_r0 : process(clk, rst)
begin
if rst = '1' then
this_r <= CNT_REG_RESET;
elsif clk = '1' and clk'event then
report integer'image(this_c.cnt);
this_c.cnt <= this_c.cnt + 1;
this_r <= this_c;
end if;
end process;
timeout.cnt <= this_r.cnt;
end structure;
-------------------------------------------------------------------------------
use work.monitor_pkg.all;
use work.data_bus_pkg.all;
entity jcore2 is
end;
architecture behaviour of jcore2 is
signal clk : bit := '1';
signal rst : bit := '1';
signal timeout : timeout_t;
begin
timeout_cnt_i: entity work.timeout_cnt
port map(clk => clk, rst => rst,
timeout => timeout);
process is
begin
wait for 1 ns;
assert timeout.cnt = 0;
rst <= '0';
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert timeout.cnt = 1;
wait;
end process;
end;
|
gpl-3.0
|
10a2e9cdfda1a5412f89d594484ad1d1
| 0.526846 | 3.252387 | false | false | false | false |
mitchsm/nvc
|
test/elab/toplevel2.vhd
| 5 | 492 |
entity toplevel2 is
generic (
I : integer;
S : string;
B : bit;
V : bit_vector );
end entity;
architecture test of toplevel2 is
signal x, y : integer;
signal z : bit;
begin
g1: if I = 4 generate
x <= 2;
end generate;
g2: if I > 10 generate
x <= 6;
end generate;
g3: if S = "hello" generate
y <= 1;
end generate;
g4: if V = "101" generate
z <= B;
end generate;
end architecture;
|
gpl-3.0
|
e4b1d2dc1aeb8381b81f741876e599cd
| 0.510163 | 3.539568 | false | false | false | false |
blutsvente/MIX
|
test/results/verilog/uamn/ent_t-rtl-a.vhd
| 1 | 5,687 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Jun 27 15:34:40 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_UAMN ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
-- Generated Generics for Entity ent_a
-- End of Generated Generics for Entity ent_a
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
dd97183bb7bfbd77e87094ce48592cff
| 0.63144 | 2.800098 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/verilog/inst_b_e-rtl-a.vhd
| 1 | 3,844 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.2 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_bb_e -- bb instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end component;
-- ---------
component inst_vb_e -- verilog udc
-- No Generated Generics
-- Generated Generics for Entity inst_vb_e
-- End of Generated Generics for Entity inst_vb_e
-- No Generated Port
end component;
-- ---------
component inst_be_i -- no verilog udc here
-- No Generated Generics
-- Generated Generics for Entity inst_be_i
-- End of Generated Generics for Entity inst_be_i
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
udc: THIS GOES TO DECL of inst_b_i
begin
udc: THIS ARE TWO LINES in BODY of inst_b_i
SECOND LINE
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_aa_ba <= p_mix_signal_aa_ba_gi; -- __I_I_BIT_PORT
p_mix_signal_bb_ab_go <= signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba_i
inst_ba_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => signal_aa_ba, -- signal test aa to ba
port_xa_o => open -- open signal to create port
);
-- End of Generated Instance Port Map for inst_ba_i
-- Generated Instance Port Map for inst_bb_i
inst_bb_i: inst_bb_e -- bb instance
port map (
port_bb_o => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_bb_i
-- Generated Instance Port Map for inst_bc_i
inst_bc_i: inst_vb_e -- verilog udc
;
-- End of Generated Instance Port Map for inst_bc_i
-- Generated Instance Port Map for inst_bd_i
inst_bd_i: inst_vb_e -- no verilog udc here, but multiple instantiations
;
-- End of Generated Instance Port Map for inst_bd_i
-- Generated Instance Port Map for inst_be_i
inst_be_i: inst_be_i -- no verilog udc here
;
-- End of Generated Instance Port Map for inst_be_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3fcb0fb1e4494b003254b15e7b04f422
| 0.622268 | 3.117599 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare14.vhd
| 1 | 4,219 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare14.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare14 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare14;
ARCHITECTURE SYN OF lpm_compare14 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "SIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare14.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare14.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare14.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare14.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare14_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
c5ec116e4a6f7ee7c91d150d0443e4d0
| 0.652998 | 3.783857 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab11.vhd
| 5 | 753 |
entity sub is
port (
x, y : in bit_vector(3 downto 0);
z : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
z <= x & y;
end architecture;
-------------------------------------------------------------------------------
entity elab11 is
end entity;
architecture test of elab11 is
signal a, b : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
port map (
x => a(7 downto 4),
y => a(5 downto 2),
z => b );
process is
begin
a <= "11110000";
wait for 1 ns;
assert b = "11111100";
a <= "10110011";
wait for 1 ns;
assert b = "10111100";
wait;
end process;
end architecture;
|
gpl-3.0
|
6d64d5bb0bf365c7c70f1a956e20440c
| 0.462151 | 4.005319 | false | false | false | false |
mitchsm/nvc
|
test/sem/ambiguous.vhd
| 4 | 4,603 |
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;
process is
type baz is (a, b, c, d);
variable z : baz := b;
begin
z := d;
z := a;
x <= a;
end process;
process is
begin
x <= bar'(c); -- Error!
end process;
process is
type small is range 10 downto -5;
variable z : small := -5;
variable a : boolean;
begin
a := z = -5;
a := -5 = z;
end process;
process is
variable a : bit_vector(3 downto 0);
variable x : character;
variable b : boolean;
begin
b := x = '1'; -- OK
b := '1' = x; -- OK
b := a = ('0', '1', '0', '1'); -- OK
b := ('0', '1', '0', '1') = a; -- OK
b := ('0', '1') = ('0', '1'); -- Error
end process;
process is
subtype some_foo is foo range a to b;
subtype less_foo is some_foo range a to a;
subtype all_foo is foo;
variable f : some_foo;
variable g : all_foo;
variable h : less_foo;
begin
f := a; -- OK
f := c; -- OK at semantic check
g := f; -- OK
g := h; -- OK
end process;
process is
type weird is ( '¢', '¦' );
variable x : weird;
variable y : character;
begin
x := '¢';
y := '¢';
report "foo¥bar";
end process;
process is
type t is (false, true);
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function now return integer;
begin
for i in now to now loop -- Error
end loop;
end process;
process is
function false return integer is
begin
return 1;
end function;
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function "="(a, b : foo) return boolean is
begin
return false;
end function;
variable x, y : foo;
begin
assert x = y; -- OK
end process;
end architecture;
package pack is
type my_int is range 1 to 10;
end package;
use work.pack.all;
package pack2 is
function "<"(a, b: my_int) return boolean;
end package;
use work.pack2.all;
use work.pack.all;
architecture a2 of e is
function ">"(a, b: my_int) return boolean;
begin
process is
variable x, y : my_int;
begin
assert x > y; -- OK
assert x < y; -- Error
end process;
end architecture;
architecture a3 of e is
type unsigned is array (natural range <>) of bit;
function "*"(a, b : unsigned) return bit_vector;
function "*"(a, b : bit_vector) return bit_vector;
function "*"(a, b : unsigned) return unsigned;
function "+"(a, b : unsigned) return bit_vector;
function "+"(a, b : bit_vector) return bit_vector;
function "+"(a, b : unsigned) return unsigned;
signal x, y, z : bit_vector(7 downto 0);
begin
x <= unsigned(y) * unsigned(z) + unsigned(z);
end architecture;
-- Test case reduced from Altera model
architecture a4 of e is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
type rbit_vector is array (natural range <>) of rbit;
function "and" (x, y : rbit_vector) return rbit_vector;
signal mdio_wr : rbit;
signal reg_addr : rbit_vector(15 downto 0);
begin
process is
begin
assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000";
end process;
end architecture;
architecture issue61 of e is
type ubit_vector is array (natural range <>) of bit;
begin
process is
variable x: bit_vector(4 downto 0);
variable y: ubit_vector(6 downto 0);
begin
y := ubit_vector(x & ('0' & '1'));
y := ubit_vector((x & '0') & '1');
y := ubit_vector(x & '0' & '1');
wait;
end process;
end architecture;
architecture cassign of e is
function "="(x, y : bit) return bit;
signal x, y, z : bit;
begin
x <= '1' when y = z else '0'; -- OK
end architecture;
-- -*- coding: latin-1; -*-
|
gpl-3.0
|
5704dc4f108f3b50aa0475dd2d9e7ee5
| 0.499457 | 3.757551 | false | false | false | false |
mitchsm/nvc
|
test/regress/driver5.vhd
| 5 | 513 |
entity driver5 is
end entity;
architecture test of driver5 is
type int_vec is array (integer range <>) of integer;
function resolved(x : int_vec) return integer is
begin
return x'length;
end function;
subtype rint is resolved integer;
signal s : rint;
begin
s <= 5;
process is
begin
assert s = 2;
wait for 0 ns;
assert s = 2;
s <= 4;
wait for 1 ns;
assert s = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
2f21c873f55e4f08620dc03f7efa5b53
| 0.567251 | 3.976744 | false | false | false | false |
mitchsm/nvc
|
test/elab/genagg.vhd
| 5 | 1,071 |
entity genagg_sub_sub is
generic (
DEVA : bit_vector(6 downto 0) );
port (
clk : in bit;
reset : in bit );
end entity;
architecture rtl of genagg_sub_sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity genagg_sub is
generic (
DEVA : bit_vector(6 downto 0) );
port (
clk : in bit;
reset : in bit );
end entity;
architecture rtl of genagg_sub is
begin
slave_i: entity work.genagg_sub_sub
generic map (
DEVA => DEVA )
port map (
clk => clk,
reset => reset );
end architecture;
-------------------------------------------------------------------------------
entity genagg is
end entity;
architecture test of genagg is
signal clk : bit := '0';
signal reset : bit := '1';
begin
uut: entity work.genagg_sub
generic map (
DEVA => "0000101" )
port map (
clk => clk,
reset => reset );
end architecture;
|
gpl-3.0
|
662e638e6ddb8845c094a37baab25221
| 0.453782 | 4.183594 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/axis_accelerator_adapter_core.vhd
| 1 | 57,629 |
-------------------------------------------------------------------------------
-- axis_accelerator_adapter_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2013] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : axis_accelerator_adapter_core.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axis_accelerator_adapter.vhd
-- xd_adapter_pkg.vhd
-- axis_accelerator_adapter_core.vhd
-- |-- axi_lite_adapter
-- |-- cdc_sync.vhd
-- |-- xd_input_args_module.vhd
-- |-- xd_s2m_adapter.vhd
-- |-- xd_s2m_converter.vhd
-- |-- xd_s2m_memory_dc.vhd
-- |-- xd_iarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_output_args_module.vhd
-- |-- cdc_sync.vhd
-- |-- xd_m2s_adapter.vhd
-- |-- xd_m2s_converter.vhd
-- |-- xd_m2s_memory_dc.vhd
-- |-- arg_mem_bank.vhd
-- |-- asymmetric_dp_bank_v6.vhd
-- |-- symmetric_dp_bank_v6.vhd
-- |-- dp_bank_sdp_v6.vhd
-- |-- oarg_columnized_mem_bank.vhd
-- |-- srl_fifo_32_wt.vhd
-- |-- xd_oarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_sync_module.vhd
-- |-- cdc_sync.vhd
-- |-- sync_ap_status.vhd
-- |-- async_fifo_dist_wt.vhd
-- |-- xd_input_scalars_module.vhd
-- |-- xd_input_scalars_fifo.vhd
-- |-- xd_output_scalars_module.vhd
-- |-- xd_output_scalars_fifo.vhd
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-07-19 2.0 pvk New ports added for scalar valid and ack
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.axi_lite_adapter;
use axis_accelerator_adapter_v2_1_6.xd_input_args_module;
use axis_accelerator_adapter_v2_1_6.xd_output_args_module;
use axis_accelerator_adapter_v2_1_6.xd_sync_module;
use axis_accelerator_adapter_v2_1_6.cdc_sync;
use axis_accelerator_adapter_v2_1_6.xd_input_scalars_module;
use axis_accelerator_adapter_v2_1_6.xd_output_scalars_module;
entity axis_accelerator_adapter_core is
generic (
-- System generics:
C_FAMILY : string := "virtex7"; -- Xilinx FPGA family
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
---
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_PRMRY_IS_ACLK_ASYNC : integer := 0;
C_MTBF_STAGES : integer := 2;
---
C_AP_ADAPTER_ID : integer range 0 to 15;
C_MAX_SCALAR_DWIDTH : integer;
C_MAX_ARG_DWIDTH : integer;
C_MAX_ARG_AWIDTH : integer;
C_MAX_ARG_N_DIM : integer;
C_MAX_MB_DEPTH : integer;
C_MAX_N_IARGS : integer;
C_MAX_N_OARGS : integer;
C_MAX_N_ISCALARS : integer;
C_MAX_N_OSCALARS : integer;
C_MAX_N_IOSCALARS : integer;
---
C_N_INPUT_ARGS : integer;
C_N_OUTPUT_ARGS : integer;
---
C_S_AXIS_TDATA_WIDTH : integer;
C_S_AXIS_TUSER_WIDTH : integer;
C_S_AXIS_TID_WIDTH : integer;
C_S_AXIS_TDEST_WIDTH : integer;
---
C_AP_IARG_TYPE : std_logic_vector;
C_AP_IARG_DWIDTH : std_logic_vector;
C_AP_IARG_MB_DEPTH : std_logic_vector;
C_AP_IARG_WIDTH : std_logic_vector;
C_AP_IARG_N_DIM : std_logic_vector;
C_AP_IARG_DIM_1 : std_logic_vector;
C_AP_IARG_DIM_2 : std_logic_vector;
C_AP_IARG_FORMAT_TYPE : std_logic_vector;
C_AP_IARG_FORMAT_FACTOR : std_logic_vector;
C_AP_IARG_FORMAT_DIM : std_logic_vector;
---
C_M_AXIS_TDATA_WIDTH : integer;
C_M_AXIS_TUSER_WIDTH : integer;
C_M_AXIS_TID_WIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer;
---
C_AP_OARG_TYPE : std_logic_vector;
C_AP_OARG_DWIDTH : std_logic_vector;
C_AP_OARG_MB_DEPTH : std_logic_vector;
C_AP_OARG_WIDTH : std_logic_vector;
C_AP_OARG_N_DIM : std_logic_vector;
C_AP_OARG_DIM : std_logic_vector;
C_AP_OARG_DIM_1 : std_logic_vector;
C_AP_OARG_DIM_2 : std_logic_vector;
C_AP_OARG_FORMAT_TYPE : std_logic_vector;
C_AP_OARG_FORMAT_FACTOR : std_logic_vector;
C_AP_OARG_FORMAT_DIM : std_logic_vector;
---
C_N_INOUT_SCALARS : integer;
C_N_INPUT_SCALARS : integer;
C_INPUT_SCALAR_MODE : std_logic_vector(63 downto 0);
C_OUTPUT_SCALAR_MODE : std_logic_vector(63 downto 0);
C_INPUT_SCALAR_DWIDTH : std_logic_vector;
C_AP_ISCALAR_DOUT_WIDTH : integer;
C_N_OUTPUT_SCALARS : integer;
C_OUTPUT_SCALAR_DWIDTH : std_logic_vector;
C_AP_OSCALAR_DIN_WIDTH : integer;
C_AP_ISCALAR_IO_DOUT_WIDTH : integer;
C_AP_OSCALAR_IO_DIN_WIDTH : integer;
---
C_EXTRA_SYNCS : integer := 1;
C_NONE : integer := 2);
port (
-- SLAVE AXI LITE:
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
--- Slave AXI streams (input arguments)
S_AXIS_ACLK : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_ARESETN : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TVALID : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TREADY : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TDATA : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector(C_MAX_N_IARGS*(C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TKEEP : in std_logic_vector(C_MAX_N_IARGS*(C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TID : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TUSER_WIDTH-1 downto 0);
--- AP input arguments, memory map interface
ap_iarg_addr : in std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_AWIDTH-1 downto 0);
ap_iarg_ce : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_iarg_we : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_iarg_din : in std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_iarg_dout : out std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
--- AP input arguments, fifo interface
ap_fifo_iarg_dout : out std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_fifo_iarg_read : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_fifo_iarg_empty_n : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
--- Master AXI streams (output arguments)
M_AXIS_ACLK : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_ARESETN : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TVALID : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TREADY : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TDATA : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(C_MAX_N_OARGS*(C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(C_MAX_N_OARGS*(C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TLAST : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TUSER_WIDTH-1 downto 0);
--- AP output arguments, memory map interface
ap_oarg_addr : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_AWIDTH-1 downto 0);
ap_oarg_ce : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_we : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_din : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_oarg_dout : out std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
--- AP output arguments, fifo interface
ap_fifo_oarg_din : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_fifo_oarg_write : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_fifo_oarg_full_n : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-- AP system signals
ap_clk : in std_logic;
ap_rst : out std_logic;
-- AP control handshaking
ap_start : out std_logic;
ap_ready : in std_logic;
ap_done : in std_logic;
ap_continue : out std_logic;
ap_idle : in std_logic;
-- AP scalar interface
ap_iscalar_dout : out std_logic_vector(511 downto 0);
ap_oscalar_din : in std_logic_vector(511 downto 0);
ap_oscalar_vld : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_oscalar_ack : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_iscalar_vld : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
ap_iscalar_ack : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
interrupt : out std_logic);
end entity;
architecture rtl of axis_accelerator_adapter_core is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
signal s_aclk : std_logic;
signal m_aclk : std_logic;
signal S_AXI_ARESET : std_logic;
signal axi_ap_rst : std_logic;
signal ap_rst_i : std_logic;
signal ap_rst_s_axi_aclk : std_logic;
signal ap_rst_saclk : std_logic;
signal ap_rst_maclk : std_logic;
signal ap_rst_i_n : std_logic;
signal ap_start_i : std_logic;
signal ap_start_one_shot : std_logic;
--- COMMAND INPUT PORT:
signal host_cmd_data : std_logic_vector(31 downto 0);
signal host_cmd_we : std_logic;
signal host_cmd_rdy : std_logic;
signal host_complete_re : std_logic;
signal host_cmd_error : std_logic;
--- AP CORE STATUS MANAGEMENT:
signal status_ap_start : std_logic;
signal status_ap_done : std_logic;
signal status_ap_idle : std_logic;
signal status_ap_ready : std_logic;
signal status_ap_start_clr : std_logic;
signal status_ap_done_clr : std_logic;
signal status_ap_idle_clr : std_logic;
signal status_ap_ready_clr : std_logic;
-- INPUT ARGUMENTS MANAGEMENT:
signal host_iarg_rst : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal iarg_rqt_enable : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal iarg_rqt_enable_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_empty : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_empty_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_empty_int : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_full : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_full_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_full_int : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_used : std_logic_vector(C_MAX_N_IARGS*4-1 downto 0);
signal status_iarg_used_i : std_logic_vector(C_MAX_N_IARGS*4-1 downto 0);
signal status_iarg_n_words : std_logic_vector(C_MAX_N_IARGS*(C_MAX_ARG_AWIDTH+1)-1 downto 0);
-- TODO:
signal status_iarg_rqt : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal status_iarg_ack : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
-- Input args, multibuffer management:
signal mb_iarg_rdy : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal mb_iarg_rdy_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal mb_iarg_done : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
-- OUTPUT ARGUMENTS MANAGEMENT:
signal host_oarg_rst : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_rqt_enable : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_rqt_enable_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_sw_length : std_logic_vector(31 downto 0);
signal oarg_sw_length_m2s : std_logic_vector(31 downto 0);
signal oarg_sw_length_we : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_use_sw_length : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal host_oarg_tdest : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
signal status_oarg_empty : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_empty_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_empty_int : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_full : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_full_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_full_int : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_used : std_logic_vector(C_MAX_N_OARGS*4-1 downto 0);
signal status_oarg_used_i : std_logic_vector(C_MAX_N_OARGS*4-1 downto 0);
-- TODO:
signal status_oarg_rqt : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal status_oarg_ack : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-- Output args, multibuffer management:
signal mb_oarg_rdy : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal mb_oarg_rdy_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal mb_oarg_done : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-- Debugging signals:
signal dbg_iarg_stream_nwords : std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
signal dbg_iarg_buffer_nwords : std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
signal dbg_ap_start : std_logic;
signal dbg_oarg_stream_nwords : std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
signal dbg_oarg_buffer_nwords : std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
signal dbg_ap_done : std_logic;
-----------------------
-- INPUT SCALARS MANAGEMENT:
signal host_iscalar_rst : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal host_iscalar_dout : std_logic_vector(31 downto 0);
signal host_iscalar_we : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal host_iscalar_rdy : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal status_iscalar_empty : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal status_iscalar_full : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal status_iscalar_used : std_logic_vector((C_MAX_N_ISCALARS)*4-1 downto 0);
---
signal ap_iscalar_rdy : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal ap_iscalar_done : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
-- TODO:
signal iscalar_rqt_enable : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
-- OUTPUT SCALARS MANAGEMENT:
signal host_oscalar_rst : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
-- signal host_oscalar_din : std_logic_vector((C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS)*C_MAX_SCALAR_DWIDTH-1 downto 0);
signal host_oscalar_din : std_logic_vector(C_MAX_N_OSCALARS*C_MAX_SCALAR_DWIDTH-1 downto 0);
signal host_oscalar_re : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal host_oscalar_rdy : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal status_oscalar_empty : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal status_oscalar_full : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal status_oscalar_used : std_logic_vector((C_MAX_N_OSCALARS)*4-1 downto 0);
---
signal ap_oscalar_vld_sync : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0); -- Generated with ap_done
signal ap_iscalar_done_sync : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal ap_oscalar_vld_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal ap_oscalar_rdy : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
-- TODO:
signal oscalar_rqt_enable : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
begin
-- Reset for AXI clk domain
S_AXI_ARESET <= not(S_AXI_ARESETN);
s_aclk <= S_AXIS_ACLK(0);
m_aclk <= M_AXIS_ACLK(0);
-- Reset for Accelerator clock domain (assign to output port)
-- Changed to active low reset for accelerator
ap_rst <= not(ap_rst_i);
ap_rst_i_n <= not(ap_rst_i);
-----------------------------------------------------------------------------------------
-- AXI_LITE_IF_I : AXI4-Lite register interface module
-----------------------------------------------------------------------------------------
AXI_LITE_IF_I : entity axis_accelerator_adapter_v2_1_6.axi_lite_adapter
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_MAX_N_IARGS => C_MAX_N_IARGS,
C_MAX_N_OARGS => C_MAX_N_OARGS,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MTBF_STAGES => C_MTBF_STAGES,
C_MAX_MB_DEPTH => C_MAX_MB_DEPTH,
C_N_INPUT_ARGS => C_N_INPUT_ARGS,
C_N_OUTPUT_ARGS => C_N_OUTPUT_ARGS,
C_MAX_ARG_AWIDTH => C_MAX_ARG_AWIDTH,
---
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS-C_MAX_N_IOSCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS-C_MAX_N_IOSCALARS,
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS,
C_MAX_N_IOSCALARS => C_MAX_N_IOSCALARS,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS,
C_MAX_SCALAR_DWIDTH => C_MAX_SCALAR_DWIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
--- App. ports
ap_rst => axi_ap_rst,
--- Command input port:
host_cmd_data => host_cmd_data,
host_cmd_we => host_cmd_we,
host_cmd_rdy => host_cmd_rdy,
host_complete_re => host_complete_re,
host_cmd_error => host_cmd_error,
--- AP core status signals:
status_ap_start => status_ap_start,
status_ap_done => status_ap_done,
status_ap_idle => status_ap_idle,
status_ap_ready => status_ap_ready,
status_ap_start_clr => status_ap_start_clr,
status_ap_done_clr => status_ap_done_clr,
status_ap_idle_clr => status_ap_idle_clr,
status_ap_ready_clr => status_ap_ready_clr,
-- Input arguments management:
host_iarg_rst => host_iarg_rst,
iarg_rqt_enable => iarg_rqt_enable_i,
status_iarg_empty => status_iarg_empty,
status_iarg_full => status_iarg_full,
status_iarg_used => status_iarg_used,
status_iarg_n_words => status_iarg_n_words,
-- Output arguments management:
host_oarg_rst => host_oarg_rst,
oarg_rqt_enable => oarg_rqt_enable_i,
oarg_sw_length => oarg_sw_length,
oarg_sw_length_m2s => oarg_sw_length_m2s,
oarg_sw_length_we => oarg_sw_length_we,
oarg_use_sw_length => oarg_use_sw_length,
host_oarg_tdest => host_oarg_tdest,
status_oarg_empty => status_oarg_empty,
status_oarg_full => status_oarg_full,
status_oarg_used => status_oarg_used,
--- Input scalars management:
host_iscalar_rst => host_iscalar_rst,
host_iscalar_dout => host_iscalar_dout,
host_iscalar_we => host_iscalar_we,
host_iscalar_rdy => host_iscalar_rdy,
status_iscalar_empty => status_iscalar_empty,
status_iscalar_full => status_iscalar_full,
status_iscalar_used => status_iscalar_used,
-- Output scalars management:
host_oscalar_rst => host_oscalar_rst,
host_oscalar_din => host_oscalar_din,
host_oscalar_re => host_oscalar_re,
host_oscalar_rdy => host_oscalar_rdy,
status_oscalar_empty => status_oscalar_empty,
status_oscalar_full => status_oscalar_full,
status_oscalar_used => status_oscalar_used,
---
dbg_iarg_stream_nwords => dbg_iarg_stream_nwords,
dbg_iarg_buffer_nwords => dbg_iarg_buffer_nwords,
dbg_oarg_stream_nwords => dbg_oarg_stream_nwords,
dbg_oarg_buffer_nwords => dbg_oarg_buffer_nwords,
---
iscalar_rqt_enable => iscalar_rqt_enable,
oscalar_rqt_enable => oscalar_rqt_enable,
---
interrupt => interrupt);
-----------------------------------------------------------------------------------------
-- XD_RESET_SYNC : Reset Synchronizer
-----------------------------------------------------------------------------------------
XD_RESET_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => '0',
prmry_in => axi_ap_rst,
prmry_vect_in => (others => '0'),
scndry_aclk => ap_clk,
scndry_resetn => '0',
scndry_out => ap_rst_i,
scndry_vect_out => open
);
XD_RESET_SYNC_s_axi_aclk : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => '0',
prmry_in => axi_ap_rst,
prmry_vect_in => (others => '0'),
scndry_aclk => S_AXI_ACLK,
scndry_resetn => '0',
scndry_out => ap_rst_s_axi_aclk,
scndry_vect_out => open
);
XD_RESET_SYNC_saclk : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => '0',
prmry_in => axi_ap_rst,
prmry_vect_in => (others => '0'),
scndry_aclk => s_aclk,
scndry_resetn => '0',
scndry_out => ap_rst_saclk,
scndry_vect_out => open
);
XD_RESET_SYNC_maclk : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => '0',
prmry_in => axi_ap_rst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_aclk,
scndry_resetn => '0',
scndry_out => ap_rst_maclk,
scndry_vect_out => open
);
-----------------------------------------------------------------------------------------
-- XD_INPUT_ARGS_I : Input argument generation module
-----------------------------------------------------------------------------------------
XD_INPUT_ARGS_I : entity axis_accelerator_adapter_v2_1_6.xd_input_args_module
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_MAX_ARG_DWIDTH => C_MAX_ARG_DWIDTH,
C_MAX_ARG_AWIDTH => C_MAX_ARG_AWIDTH,
C_MAX_ARG_N_DIM => C_MAX_ARG_N_DIM,
C_MAX_MB_DEPTH => C_MAX_MB_DEPTH,
C_MAX_N_IARGS => C_MAX_N_IARGS,
C_N_INPUT_ARGS => C_N_INPUT_ARGS,
---
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_TUSER_WIDTH,
C_S_AXIS_TID_WIDTH => C_S_AXIS_TID_WIDTH,
C_S_AXIS_TDEST_WIDTH => C_S_AXIS_TDEST_WIDTH,
---
C_AP_IARG_TYPE => C_AP_IARG_TYPE,
C_AP_IARG_DWIDTH => C_AP_IARG_DWIDTH,
C_AP_IARG_MB_DEPTH => C_AP_IARG_MB_DEPTH,
C_AP_IARG_WIDTH => C_AP_IARG_WIDTH,
C_AP_IARG_N_DIM => C_AP_IARG_N_DIM,
C_AP_IARG_DIM_1 => C_AP_IARG_DIM_1,
C_AP_IARG_DIM_2 => C_AP_IARG_DIM_2,
C_AP_IARG_FORMAT_TYPE => C_AP_IARG_FORMAT_TYPE,
C_AP_IARG_FORMAT_FACTOR => C_AP_IARG_FORMAT_FACTOR,
C_AP_IARG_FORMAT_DIM => C_AP_IARG_FORMAT_DIM,
C_MTBF_STAGES => C_MTBF_STAGES,
C_EXTRA_SYNCS => C_EXTRA_SYNCS)
port map (
--- Slave AXI streams (input arguments)
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TKEEP => S_AXIS_TKEEP,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TID => S_AXIS_TID,
S_AXIS_TDEST => S_AXIS_TDEST,
S_AXIS_TUSER => S_AXIS_TUSER,
dbg_stream_nwords => dbg_iarg_stream_nwords,
dbg_buffer_nwords => dbg_iarg_buffer_nwords,
dbg_ap_start => dbg_ap_start,
--- AP input arguments
ap_clk => ap_clk,
ap_rst => ap_rst_i,
ap_rst_saclk => ap_rst_saclk,
ap_iarg_rst => host_iarg_rst,
ap_iarg_addr => ap_iarg_addr,
ap_iarg_ce => ap_iarg_ce,
ap_iarg_we => ap_iarg_we,
ap_iarg_din => ap_iarg_din,
ap_iarg_dout => ap_iarg_dout,
mb_iarg_rdy => mb_iarg_rdy_i,
mb_iarg_done => mb_iarg_done,
status_iarg_empty => status_iarg_empty_i,
status_iarg_full => status_iarg_full_i,
status_iarg_used => status_iarg_used_i,
status_iarg_n_words => status_iarg_n_words,
---
ap_fifo_iarg_dout => ap_fifo_iarg_dout,
ap_fifo_iarg_read => ap_fifo_iarg_read,
ap_fifo_iarg_empty_n => ap_fifo_iarg_empty_n);
-----------------------------------------------------------------------------------------
-- XD_OUTPUT_ARGS_I : Output argument generation module
-----------------------------------------------------------------------------------------
XD_OUTPUT_ARGS_I : entity axis_accelerator_adapter_v2_1_6.xd_output_args_module
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_MAX_ARG_DWIDTH => C_MAX_ARG_DWIDTH,
C_MAX_ARG_AWIDTH => C_MAX_ARG_AWIDTH,
C_MAX_ARG_N_DIM => C_MAX_ARG_N_DIM,
C_MAX_MB_DEPTH => C_MAX_MB_DEPTH,
C_MAX_N_OARGS => C_MAX_N_OARGS,
C_N_OUTPUT_ARGS => C_N_OUTPUT_ARGS,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MTBF_STAGES => C_MTBF_STAGES,
---
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
---
C_AP_OARG_TYPE => C_AP_OARG_TYPE,
C_AP_OARG_DWIDTH => C_AP_OARG_DWIDTH,
C_AP_OARG_MB_DEPTH => C_AP_OARG_MB_DEPTH,
---
C_AP_OARG_WIDTH => C_AP_OARG_WIDTH,
C_AP_OARG_N_DIM => C_AP_OARG_N_DIM,
C_AP_OARG_DIM => C_AP_OARG_DIM,
C_AP_OARG_DIM_1 => C_AP_OARG_DIM_1,
C_AP_OARG_DIM_2 => C_AP_OARG_DIM_2,
C_AP_OARG_FORMAT_TYPE => C_AP_OARG_FORMAT_TYPE,
C_AP_OARG_FORMAT_FACTOR => C_AP_OARG_FORMAT_FACTOR,
C_AP_OARG_FORMAT_DIM => C_AP_OARG_FORMAT_DIM)
port map (
--- Master AXI streams (output arguments)
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_ARESETN => M_AXIS_ARESETN,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TSTRB => M_AXIS_TSTRB,
M_AXIS_TKEEP => M_AXIS_TKEEP,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TID => M_AXIS_TID,
M_AXIS_TDEST => M_AXIS_TDEST,
M_AXIS_TUSER => M_AXIS_TUSER,
---
oarg_sw_length => oarg_sw_length,
oarg_sw_length_m2s => oarg_sw_length_m2s,
oarg_sw_length_we => oarg_sw_length_we,
oarg_use_sw_length => oarg_use_sw_length,
host_oarg_tdest => host_oarg_tdest,
---
dbg_stream_nwords => dbg_oarg_stream_nwords,
dbg_buffer_nwords => dbg_oarg_buffer_nwords,
dbg_ap_done => dbg_ap_done,
--- AP output arguments
ap_clk => ap_clk,
ap_rst => ap_rst_i,
ap_rst_maclk => ap_rst_maclk,
ap_oarg_rst => host_oarg_rst,
ap_oarg_addr => ap_oarg_addr,
ap_oarg_ce => ap_oarg_ce,
ap_oarg_we => ap_oarg_we,
ap_oarg_din => ap_oarg_din,
ap_oarg_dout => ap_oarg_dout,
ap_oarg_rdy => mb_oarg_rdy_i,
ap_oarg_done => mb_oarg_done,
status_oarg_empty => status_oarg_empty_i,
status_oarg_full => status_oarg_full_i,
status_oarg_used => status_oarg_used_i,
---
ap_fifo_oarg_din => ap_fifo_oarg_din,
ap_fifo_oarg_write => ap_fifo_oarg_write,
ap_fifo_oarg_full_n => ap_fifo_oarg_full_n,
ap_start => ap_start_one_shot,
ap_done => ap_done);
EN_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
AP_OARGFULL_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => M_AXIS_ACLK(0),
prmry_resetn => M_AXIS_ARESETN(0),
prmry_in => '0',
prmry_vect_in => status_oarg_full_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_oarg_full_int
);
AP_OARGEMPTY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => M_AXIS_ACLK(0),
prmry_resetn => M_AXIS_ARESETN(0),
prmry_in => '0',
prmry_vect_in => status_oarg_empty_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_oarg_empty_int
);
-- status_oarg_empty <= status_oarg_empty_i;
AP_OARGUSED_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OARGS*4,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => M_AXIS_ACLK(0),
prmry_resetn => M_AXIS_ARESETN(0),
prmry_in => '0',
prmry_vect_in => status_oarg_used_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_oarg_used
);
AP_ORGRDY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => ap_rst_i_n,
prmry_in => '0',
prmry_vect_in => mb_oarg_rdy_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => mb_oarg_rdy
);
AP_IARGFULL_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXIS_ACLK(0),
prmry_resetn => S_AXIS_ARESETN(0),
prmry_in => '0',
prmry_vect_in => status_iarg_full_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_iarg_full_int
);
AP_IARGEMPTY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXIS_ACLK(0),
prmry_resetn => S_AXIS_ARESETN(0),
prmry_in => '0',
prmry_vect_in => status_iarg_empty_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_iarg_empty_int
);
AP_IARGUSED_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS*4,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXIS_ACLK(0),
prmry_resetn => S_AXIS_ARESETN(0),
prmry_in => '0',
prmry_vect_in => status_iarg_used_i,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_iarg_used
);
AP_IRGRQT_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => S_AXI_ACLK,
prmry_resetn => S_AXI_ARESETN,
prmry_in => '0',
prmry_vect_in => iarg_rqt_enable_i,
scndry_aclk => ap_clk,
scndry_resetn => ap_rst_i_n,
scndry_out => open,
scndry_vect_out => iarg_rqt_enable
);
mb_iarg_rdy <= mb_iarg_rdy_i;
oarg_rqt_enable <= oarg_rqt_enable_i;
OARGS_GEN_INT : if (C_N_OUTPUT_ARGS > 0) generate
begin
OUTPUT_ARGS_GEN_INT : for i in 0 to C_N_OUTPUT_ARGS-1 generate
constant OARG_TYPE : integer := get_int_element(C_AP_OARG_TYPE, i);
begin
M2S_gen_INT: if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) generate
begin
status_oarg_full(i) <= status_oarg_full_int(i);
status_oarg_empty(i) <= status_oarg_empty_int(i);
end generate M2S_gen_INT;
S2S_gen_INT: if (OARG_TYPE = AP_ARG_STREAM_TYPE) generate
begin
status_oarg_full(i) <= '0';
status_oarg_empty(i) <= '0';
end generate S2S_gen_INT;
end generate OUTPUT_ARGS_GEN_INT;
end generate OARGS_GEN_INT;
IARGS_GEN_INT : if (C_N_INPUT_ARGS > 0) generate
begin
INPUT_ARGS_GEN_INT : for i in 0 to C_N_INPUT_ARGS-1 generate
constant IARG_TYPE : integer := get_int_element(C_AP_IARG_TYPE, i);
begin
M2S_gen_INT: if (IARG_TYPE = AP_ARG_MEM_MAP_TYPE) generate
begin
status_iarg_full(i) <= status_iarg_full_int(i);
status_iarg_empty(i) <= status_iarg_empty_int(i);
end generate M2S_gen_INT;
S2S_gen_INT: if (IARG_TYPE = AP_ARG_STREAM_TYPE) generate
begin
status_iarg_full(i) <= '0';
status_iarg_empty(i) <= '0';
end generate S2S_gen_INT;
end generate INPUT_ARGS_GEN_INT;
end generate IARGS_GEN_INT;
end generate EN_APCLK_LITE_SYNC_GEN;
NO_APCLK_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_oarg_full <= status_oarg_full_i;
status_oarg_empty <= status_oarg_empty_i;
status_oarg_used <= status_oarg_used_i;
status_iarg_full <= status_iarg_full_i;
status_iarg_empty <= status_iarg_empty_i;
status_iarg_used <= status_iarg_used_i;
mb_iarg_rdy <= mb_iarg_rdy_i;
iarg_rqt_enable <= iarg_rqt_enable_i;
oarg_rqt_enable <= oarg_rqt_enable_i;
mb_oarg_rdy <= mb_oarg_rdy_i;
end generate NO_APCLK_LITE_SYNC_GEN;
-----------------------------------------------------------------------------------------
-- XD_SYNC_I : Accelerator Synchronizer module
-----------------------------------------------------------------------------------------
XD_SYNC_I : entity axis_accelerator_adapter_v2_1_6.xd_sync_module
generic map (
C_FAMILY => C_FAMILY,
C_MAX_N_IARGS => C_MAX_N_IARGS,
C_MAX_N_OARGS => C_MAX_N_OARGS,
C_N_INPUT_ARGS => C_N_INPUT_ARGS,
C_N_OUTPUT_ARGS => C_N_OUTPUT_ARGS,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MTBF_STAGES => C_MTBF_STAGES,
---
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS,
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS,
C_MAX_N_IOSCALARS => C_MAX_N_IOSCALARS,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS)
port map (
---
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
host_cmd_data => host_cmd_data,
host_cmd_we => host_cmd_we,
host_cmd_rdy => host_cmd_rdy,
host_complete_re => host_complete_re,
host_cmd_error => host_cmd_error,
---
iarg_rqt_enable => iarg_rqt_enable,
oarg_rqt_enable => oarg_rqt_enable,
---
status_ap_start => status_ap_start,
status_ap_done => status_ap_done,
status_ap_idle => status_ap_idle,
status_ap_ready => status_ap_ready,
status_ap_start_clr => status_ap_start_clr,
status_ap_done_clr => status_ap_done_clr,
status_ap_idle_clr => status_ap_idle_clr,
status_ap_ready_clr => status_ap_ready_clr,
---
status_iarg_rqt => status_iarg_rqt,
status_iarg_ack => status_iarg_ack,
status_oarg_rqt => status_oarg_rqt,
status_oarg_ack => status_oarg_ack,
---
ap_clk => ap_clk,
soft_rst => ap_rst_s_axi_aclk,
ap_rst => ap_rst_i,
---
mb_iarg_rdy => mb_iarg_rdy,
mb_iarg_done => mb_iarg_done,
mb_oarg_rdy => mb_oarg_rdy,
mb_oarg_done => mb_oarg_done,
-- AP control handshaking:
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_start_one_shot => ap_start_one_shot,
---
iscalar_rqt_enable => iscalar_rqt_enable,
oscalar_rqt_enable => oscalar_rqt_enable,
---
ap_iscalar_rdy => ap_iscalar_rdy,
ap_iscalar_done => ap_iscalar_done_sync,
ap_oscalar_vld => ap_oscalar_vld_sync,
ap_oscalar_rdy => ap_oscalar_rdy);
-----------------------------------------------------------------------------------------
-- XD_INPUT_SCALARS_I : Input scalar generation module
-----------------------------------------------------------------------------------------
IN_ACTIVE_GEN1 : if (C_N_INOUT_SCALARS > 0) generate
XD_INPUT_SCALARS_I : entity axis_accelerator_adapter_v2_1_6.xd_input_scalars_module
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-C_MAX_N_IOSCALARS,
C_INPUT_SCALAR_DWIDTH => C_INPUT_SCALAR_DWIDTH,
C_AP_ISCALAR_DOUT_WIDTH => 32*(C_MAX_N_ISCALARS-C_MAX_N_IOSCALARS)+ C_AP_ISCALAR_IO_DOUT_WIDTH)
port map (
clk => S_AXI_ACLK,
rst => S_AXI_ARESET,
iscalar_rst => host_iscalar_rst,
iscalar_din => host_iscalar_dout,
iscalar_we => host_iscalar_we,
status_iscalar_empty => status_iscalar_empty,
status_iscalar_full => status_iscalar_full,
status_iscalar_used => status_iscalar_used,
--- AP input scalars
ap_clk => ap_clk,
ap_rst => ap_rst_i,
ap_rst_s_axi_aclk => ap_rst_s_axi_aclk,
ap_iscalar_rdy => ap_iscalar_rdy,
ap_iscalar_done => ap_iscalar_done,
ap_iscalar_dout => ap_iscalar_dout(32*(C_MAX_N_ISCALARS-C_MAX_N_IOSCALARS) + C_AP_ISCALAR_IO_DOUT_WIDTH-1 downto 0));
end generate IN_ACTIVE_GEN1;
IN_ACTIVE_GEN2 : if (C_N_INOUT_SCALARS = 0) generate
XD_INPUT_SCALARS_I : entity axis_accelerator_adapter_v2_1_6.xd_input_scalars_module
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS,--+C_MAX_N_IOSCALARS,
--C_N_INPUT_SCALARS => C_N_INPUT_SCALARS+C_N_INOUT_SCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS+C_MAX_N_ISCALARS-C_MAX_N_IOSCALARS,
C_INPUT_SCALAR_DWIDTH => C_INPUT_SCALAR_DWIDTH,
C_AP_ISCALAR_DOUT_WIDTH => C_AP_ISCALAR_DOUT_WIDTH)
port map (
clk => S_AXI_ACLK,
rst => S_AXI_ARESET,
iscalar_rst => host_iscalar_rst,
iscalar_din => host_iscalar_dout,
iscalar_we => host_iscalar_we,
status_iscalar_empty => status_iscalar_empty,
status_iscalar_full => status_iscalar_full,
status_iscalar_used => status_iscalar_used,
--- AP input scalars
ap_clk => ap_clk,
ap_rst_s_axi_aclk => ap_rst_s_axi_aclk,
ap_rst => ap_rst_i,
ap_iscalar_rdy => ap_iscalar_rdy,
ap_iscalar_done => ap_iscalar_done,
ap_iscalar_dout => ap_iscalar_dout(C_AP_ISCALAR_DOUT_WIDTH-1 downto 0));
end generate IN_ACTIVE_GEN2;
-----------------------------------------------------------------------------------------
-- XD_OUTPUT_SCALARS_I : Output scalar generation module
-----------------------------------------------------------------------------------------
ACTIVE_GEN1 : if (C_N_INOUT_SCALARS > 0) generate
XD_OUTPUT_SCALARS_I : entity axis_accelerator_adapter_v2_1_6.xd_output_scalars_module
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MAX_SCALAR_DWIDTH => C_MAX_SCALAR_DWIDTH,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS,
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-C_MAX_N_IOSCALARS,
C_OUTPUT_SCALAR_DWIDTH => C_OUTPUT_SCALAR_DWIDTH,
C_AP_OSCALAR_DIN_WIDTH => 32*(C_MAX_N_OSCALARS-C_MAX_N_IOSCALARS) + C_AP_OSCALAR_IO_DIN_WIDTH)
port map (
--- AP output scalars
ap_clk => ap_clk,
ap_rst => ap_rst_i,
ap_rst_s_axi_aclk => ap_rst_s_axi_aclk,
ap_oscalar_vld => ap_oscalar_vld_i,
ap_oscalar_rdy => ap_oscalar_rdy,
ap_oscalar_din => ap_oscalar_din(32*(C_MAX_N_OSCALARS-C_MAX_N_IOSCALARS) + C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0),
---
clk => S_AXI_ACLK,
rst => S_AXI_ARESET,
oscalar_rst => host_oscalar_rst,
oscalar_data => host_oscalar_din,
oscalar_re => host_oscalar_re,
status_oscalar_empty => status_oscalar_empty,
status_oscalar_full => status_oscalar_full,
status_oscalar_used => status_oscalar_used);
end generate ACTIVE_GEN1;
ACTIVE_GEN2 : if (C_N_INOUT_SCALARS = 0) generate
XD_OUTPUT_SCALARS_I : entity axis_accelerator_adapter_v2_1_6.xd_output_scalars_module
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MAX_SCALAR_DWIDTH => C_MAX_SCALAR_DWIDTH,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS,
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS+C_MAX_N_OSCALARS-C_MAX_N_IOSCALARS,
C_OUTPUT_SCALAR_DWIDTH => C_OUTPUT_SCALAR_DWIDTH,
C_AP_OSCALAR_DIN_WIDTH => C_AP_OSCALAR_DIN_WIDTH)
port map (
--- AP output scalars
ap_clk => ap_clk,
ap_rst => ap_rst_i,
ap_rst_s_axi_aclk => ap_rst_s_axi_aclk,
ap_oscalar_vld => ap_oscalar_vld_i,
ap_oscalar_rdy => ap_oscalar_rdy,
ap_oscalar_din => ap_oscalar_din(C_AP_OSCALAR_DIN_WIDTH-1 downto 0),
---
clk => S_AXI_ACLK,
rst => S_AXI_ARESET,
oscalar_rst => host_oscalar_rst,
oscalar_data => host_oscalar_din,
oscalar_re => host_oscalar_re,
status_oscalar_empty => status_oscalar_empty,
status_oscalar_full => status_oscalar_full,
status_oscalar_used => status_oscalar_used);
end generate ACTIVE_GEN2;
-----------------------------------------------------------------------------------------
-- OUTPUT_SCALARS_MODE_GEN : Output Scalar IO mode logic
-----------------------------------------------------------------------------------------
OUTPUT_SCALARS_MODE_GEN : for i in 0 to C_MAX_N_OSCALARS-1 generate
-- AP_HS mode
OSCALAR_HS_MODE : if (C_OUTPUT_SCALAR_MODE(4*(i+1)-1 downto 4*i) = "0010") generate
ap_oscalar_ack(i) <= ap_oscalar_rdy(i);
ap_oscalar_vld_i(i) <= ap_oscalar_vld(i);
end generate OSCALAR_HS_MODE;
-- AP_VLD mode
OSCALAR_VLD_MODE : if (C_OUTPUT_SCALAR_MODE(4*(i+1)-1 downto 4*i) = "0001") generate
ap_oscalar_ack(i) <= '0';
ap_oscalar_vld_i(i) <= ap_oscalar_vld(i);
end generate OSCALAR_VLD_MODE;
-- AP_NONE mode
OSCALAR_NONE_MODE : if (C_OUTPUT_SCALAR_MODE(4*(i+1)-1 downto 4*i) = "0000") generate
ap_oscalar_ack(i) <= '0';
ap_oscalar_vld_i(i) <= ap_oscalar_vld_sync(i);
end generate OSCALAR_NONE_MODE;
end generate OUTPUT_SCALARS_MODE_GEN;
-----------------------------------------------------------------------------------------
-- INPUT_SCALARS_MODE_GEN : Input Scalar IO mode logic
-----------------------------------------------------------------------------------------
INPUT_SCALARS_MODE_GEN : for i in 0 to C_MAX_N_ISCALARS-1 generate
-- AP_HS mode
ISCALAR_HS_MODE : if (C_INPUT_SCALAR_MODE(4*(i+1)-1 downto 4*i) = "0010") generate
ap_iscalar_vld(i) <= ap_iscalar_rdy(i);
ap_iscalar_done(i) <= ap_iscalar_ack(i);
end generate ISCALAR_HS_MODE;
-- AP_VLD mode
ISCALAR_VLD_MODE : if (C_INPUT_SCALAR_MODE(4*(i+1)-1 downto 4*i) = "0001") generate
ap_iscalar_vld(i) <= ap_iscalar_rdy(i);
ap_iscalar_done(i) <= ap_iscalar_done_sync(i);
end generate ISCALAR_VLD_MODE;
-- AP_NONE mode
ISCALAR_NONE_MODE : if (C_INPUT_SCALAR_MODE(4*(i+1)-1 downto 4*i) = "0000") generate
ap_iscalar_vld(i) <= '0';
ap_iscalar_done(i) <= ap_iscalar_done_sync(i);
end generate ISCALAR_NONE_MODE;
end generate INPUT_SCALARS_MODE_GEN;
-- Unused nets
host_iscalar_rdy <= (others => '0');
host_oscalar_rdy <= (others => '0');
dbg_ap_start <= '0';
dbg_ap_done <= '0';
end rtl;
|
mit
|
20adac64c762d6d19923bd69f2e47a22
| 0.508268 | 3.387948 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/ioblock0_e-rtl-a.vhd
| 1 | 3,429 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:55:26 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-rtl-a.vhd,v 1.2 2005/10/06 11:16:05 wig Exp $
-- $Date: 2005/10/06 11:16:05 $
-- $Log: ioblock0_e-rtl-a.vhd,v $
-- Revision 1.2 2005/10/06 11:16:05 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock0_e
--
architecture rtl of ioblock0_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_g_i --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
p_di : in std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
iosel_0(0) <= p_mix_iosel_0_0_0_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_data_i1
ioc_data_i1: ioc_g_i
port map (
di => data_i1, -- io data
p_di => pad_di_1, -- data in from pad
sel => iosel_0 -- IO_Select
);
-- End of Generated Instance Port Map for ioc_data_i1
-- Generated Instance Port Map for ioc_data_o1
ioc_data_o1: ioc_g_o
port map (
do => data_o1, -- io data
p_do => pad_do_2, -- data out to pad
p_en => pad_en_2, -- pad output enable
sel => iosel_0 -- IO_Select
);
-- End of Generated Instance Port Map for ioc_data_o1
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
9cbc2c1b9b4ea70b1f4a98212e03c9ff
| 0.587343 | 2.808354 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/20051004c/inst_bug_e-e.vhd
| 1 | 1,594 |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_bug_e
--
-- Generated
-- by: wig
-- on: Thu Oct 6 12:55:50 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bug_e-e.vhd,v 1.1 2005/10/06 13:36:57 wig Exp $
-- $Date: 2005/10/06 13:36:57 $
-- $Log: inst_bug_e-e.vhd,v $
-- Revision 1.1 2005/10/06 13:36:57 wig
-- New testcase or generics
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_bug_e
--
entity inst_bug_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_bug_e
CHROMA_GROUP_DELAY2_G : integer := 1;
CHROMA_GROUP_DELAY_G : integer := 12;
CHROMA_LINE_DELAY2_G : integer := 3;
CHROMA_LINE_DELAY_G : integer := 0;
CHROMA_PIPE_DELAY2_G : integer := 2;
CHROMA_PIPE_DELAY_G : integer := 1
-- End of Generated Generics for Entity inst_bug_e
);
-- Generated Port Declaration:
-- No Generated Port for Entity inst_bug_e
end inst_bug_e;
--
-- End of Generated Entity inst_bug_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
9df66f2100783f2a390662fff021d09c
| 0.570891 | 3.07722 | false | false | false | false |
mitchsm/nvc
|
test/regress/operator2.vhd
| 5 | 859 |
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"(x, y : tv) return tv is
variable tmp : tv(x'range);
begin
for i in x'range loop
tmp(i) := x(i) and y(i);
end loop;
return tmp;
end function;
begin
process is
variable x, y : t;
variable xv, yv : tv(1 to 2);
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
xv := (A, B);
yv := (B, B);
assert (xv and yv) = (B, A);
wait;
end process;
end architecture;
|
gpl-3.0
|
9da5a7e48fd31f6f07541b480c145587
| 0.459837 | 3.534979 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/blk_mem_gen_paramReg_ste/example_design/bmg_wrapper.vhd
| 1 | 10,478 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 255
-- C_READ_DEPTH_A : 255
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 255
-- C_READ_DEPTH_B : 255
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_paramReg_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_paramReg_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
gpl-2.0
|
286ed60309b7e2a3ee6253fdec051b52
| 0.490838 | 3.842318 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/blk_mem_gen_paramReg_ste/example_design/blk_mem_gen_paramReg_top.vhd
| 1 | 5,436 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_paramReg_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_paramReg_top;
ARCHITECTURE xilinx OF blk_mem_gen_paramReg_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_paramReg IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_paramReg
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-2.0
|
d6f6360e9124c867ab61e4ac2336405b
| 0.5539 | 4.518703 | false | false | false | false |
DacHt/CU_Droptest
|
hdl/System_clock.vhd
| 1 | 2,397 |
-- System_clock.vhd
--------------------------------
-- Generates all timing for the system
--------------------------------
-- Authors:
-- Åke Forslund
-- Terry Edberg
-- Göran Olsson
--------------------------------
-- Reused for WOLF experiment.
-- Time vector:
--M_TIME 0 32768 KHz
--M_TIME 1 16384 KHz
--M_TIME 2 8192 KHz
--M_TIME 3 4096 KHz
--M_TIME 4 2048 KHz
--M_TIME 5 1024 KHz
--M_TIME 6 512 KHz
--M_TIME 7 256 KHz
--M_TIME 8 128 KHz
--M_TIME 9 64 KHz
--M_TIME 10 32 KHz
--M_TIME 11 16 KHz
--M_TIME 12 8 KHz
--M_TIME 13 4 KHz
--M_TIME 14 2 KHz
--M_TIME 15 1 KHz
--M_TIME 16 500 Hz
--M_TIME 17 250 Hz
--M_TIME 18 128 Hz
--M_TIME 19 64 Hz
--M_TIME 20 32 Hz
--M_TIME 21 16 Hz
--M_TIME 22 8 Hz
--M_TIME 23 4 Hz
--M_TIME 24 2 Hz
--M_TIME 25 1 Hz
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY system_clock is
PORT(mclk, reset : in std_logic; -- mclk is 32.768 MHz
m_time : out std_logic_vector(25 downto 0) );
END system_clock;
ARCHITECTURE behaviour of system_clock is
signal s_time : std_logic_vector(7 downto 0) := (others => '0');
signal l_time : std_logic_vector(17 downto 1) := (others => '0');
signal flag : std_logic;
begin
m_time(25 downto 0) <= s_time & l_time & mclk;
-- Intermediate counter, 18 bit
process(mclk, reset)
begin
if reset /= '0' then
l_time <= (others => '0');
elsif falling_edge(mclk) then
l_time <= l_time + 1;
end if;
end process;
process(mclk, reset)
begin
if reset /= '0' then
flag <= '0';
elsif rising_edge(mclk) then
if l_time = '1' & x"FFFF" then
flag <= '1';
else
flag <= '0';
end if;
end if;
end process;
-- Slow counter, 8 bit, counts 0...249; MSB at 1 Hz
process(mclk, reset)
begin
if reset /= '0' then
s_time <= (others => '0');
elsif falling_edge(mclk) then
if flag = '1' then
if (s_time(7 downto 3) = x"1F") and(s_time(0) = '1') then -- 249; Don't check the zero bits
s_time <= (others => '0');
else
s_time <= s_time + 1;
end if;
end if;
end if;
end process;
end behaviour;
|
mit
|
2b6a2b44467169b9918838d05068281a
| 0.505632 | 3.084942 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare6.vhd
| 1 | 4,444 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare6.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare6 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare6;
ARCHITECTURE SYN OF lpm_compare6 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "1000001011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "523"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 523 0 0 10 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
0d37e42244050fb26a853649c8219ca7
| 0.655716 | 3.697171 | false | false | false | false |
mitchsm/nvc
|
test/lower/attr1.vhd
| 4 | 503 |
entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
process is
variable x : integer := 0;
variable y : my_int;
variable z : integer := 1;
begin
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
assert integer'leftof(z) = 0;
assert integer'rightof(z) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
11e0a1d02adb67b55ef59a5dbdfe1930
| 0.572565 | 3.542254 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/dp_bank_sdp_v6.vhd
| 1 | 16,245 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : dp_bank_sdp_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-08-25 2.0 pvk Updated BRAM data input pin correctly when standard SDP mode is used.
-- Lower bits mapped to DIBDI in standard SDP. In Extra wide SDP
-- configuration, higher 32 bit mapped to DIBDI.
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity dp_bank_sdp_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_SDP_WIDE : integer;
C_RD_AWIDTH : integer;
C_RD_DWIDTH : integer;
C_WR_AWIDTH : integer;
C_WR_DWIDTH : integer);
port (
rst : in std_logic;
wr_clk : in std_logic;
wr_en : in std_logic;
wr_addr : in std_logic_vector(C_WR_AWIDTH-1 downto 0);
din : in std_logic_vector(C_WR_DWIDTH-1 downto 0);
rd_clk : in std_logic;
rd_en : in std_logic;
rd_addr : in std_logic_vector(C_RD_AWIDTH-1 downto 0);
dout : out std_logic_vector(C_RD_DWIDTH-1 downto 0));
end dp_bank_sdp_v6;
architecture rtl of dp_bank_sdp_v6 is
signal bram_din : std_logic_vector(63 downto 0);
signal bram_dout : std_logic_vector(63 downto 0);
signal bram_wr_addr : std_logic_vector(15 downto 0);
signal bram_rd_addr : std_logic_vector(15 downto 0);
signal bram_we : std_logic_vector(7 downto 0);
constant USE_RAMB36E1 : boolean := ((C_WR_DWIDTH = 64 and C_RD_DWIDTH <= 64) or
(C_RD_DWIDTH = 64 and C_WR_DWIDTH <= 64));
constant USE_RAMB18E1 : boolean := ((C_WR_DWIDTH = 32 and C_RD_DWIDTH <= 32) or
(C_RD_DWIDTH = 32 and C_WR_DWIDTH <= 32));
begin
PORT_64_GEN : if USE_RAMB36E1 generate
begin
process(wr_addr)
constant ADDR_LSB : integer := log2(C_WR_DWIDTH);
constant ADDR_MSB : integer := ADDR_LSB+C_WR_AWIDTH-1;
begin
bram_wr_addr <= (others => '0');
bram_wr_addr(ADDR_MSB downto ADDR_LSB) <= wr_addr;
end process;
process(rd_addr)
constant ADDR_LSB : integer := log2(C_RD_DWIDTH);
constant ADDR_MSB : integer := ADDR_LSB+C_RD_AWIDTH-1;
begin
bram_rd_addr <= (others => '0');
bram_rd_addr(ADDR_MSB downto ADDR_LSB) <= rd_addr;
end process;
SDP_EXTRA_WIDE_GEN : if C_SDP_WIDE = 1 generate
begin
bram_din(C_WR_DWIDTH-1 downto 0) <= din;
bram_din(63 downto C_WR_DWIDTH) <= (others => '0');
end generate SDP_EXTRA_WIDE_GEN;
SDP_STD_GEN : if C_SDP_WIDE = 0 generate
begin
bram_din(32+C_WR_DWIDTH-1 downto 32) <= din;
bram_din(C_WR_DWIDTH-1 downto 0) <= din;
bram_din(31 downto C_WR_DWIDTH) <= (others => '0');
bram_din(63 downto 32+C_WR_DWIDTH) <= (others => '0');
end generate SDP_STD_GEN;
-- process(din)
-- begin
-- bram_din <= (others => '0');
-- bram_din(C_WR_DWIDTH-1 downto 0) <= din;
-- end process;
dout <= bram_dout(C_RD_DWIDTH-1 downto 0);
-- Port A: read
-- Port B: write
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP", -- "SDP" or "TDP"
READ_WIDTH_A => C_RD_DWIDTH+(C_RD_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => 0, -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => 0, -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => C_WR_DWIDTH+(C_WR_DWIDTH/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din(31 downto 0), -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout(31 downto 0), -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_rd_addr, -- 16-bit input A port address/Read address input
CLKARDCLK => rd_clk, -- 1-bit input A port clock/Read clock input
ENARDEN => rd_en, -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => x"0", -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din(63 downto 32), -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout(63 downto 32), -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_wr_addr, -- 16-bit input B port address/Write address input
CLKBWRCLK => wr_clk, -- 1-bit input B port clock/Write clock input
ENBWREN => wr_en, -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
SIM_COLLISION_CHECK => "ALL",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => C_RD_DWIDTH+(C_RD_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => 0, -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
READ_WIDTH_B => 0, -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => C_WR_DWIDTH+(C_WR_DWIDTH/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST"
)
PORT MAP (
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DBITERR => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
DINADIN => bram_din(31 downto 0), -- 32-bit input A port data/LSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DOUTADOUT => bram_dout(31 downto 0), -- 32-bit output A port data/LSB data output
DOUTPADOUTP => open,
ADDRARDADDR => bram_rd_addr(14 downto 0), -- 16-bit input A port address/Read address input
CLKARDCLK => rd_clk,
ENARDEN => rd_en, -- 1-bit input A port enable/Read enable input
ADDRENA => '0',
REGCEAREGCE => '1',
RSTRAMARSTRAM => rst,
RSTREGARSTREG => '0',
WEA => x"0", -- 4-bit input A port write enable input
DINBDIN => bram_din(63 downto 32), -- 32-bit input B port data/MSB data input
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
DOUTBDOUT => bram_dout(63 downto 32), -- 32-bit output B port data/MSB data output
DOUTPBDOUTP => open,
ADDRBWRADDR => bram_wr_addr(14 downto 0), -- 16-bit input B port address/Write address input
CLKBWRCLK => wr_clk,
ENBWREN => wr_en, -- 1-bit input B port enable/Write enable input
ADDRENB => '0',
ECCPIPECE => '0',
REGCEB => '1',
RSTRAMB => rst,
RSTREGB => '0',
SLEEP => '0',
WEBWE => x"FF" -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate PORT_64_GEN;
end rtl;
|
mit
|
2eb4549749ebca04f0f13aa17d209107
| 0.517267 | 4.018056 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/pad_pads_e-rtl-a.vhd
| 1 | 14,556 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:53:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-rtl-a.vhd,v 1.2 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: pad_pads_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of pad_pads_e
--
architecture rtl of pad_pads_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component w_data3
-- No Generated Generics
port (
-- Generated Port for Entity w_data3
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data3
);
end component;
-- ---------
component w_data2
-- No Generated Generics
port (
-- Generated Port for Entity w_data2
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data2
);
end component;
-- ---------
component w_pad_i
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_i
di : out std_ulogic -- data in from pad
-- End of Generated Port for Entity w_pad_i
);
end component;
-- ---------
component w_pad_o
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_o
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_pad_o
);
end component;
-- ---------
component w_disp
-- No Generated Generics
port (
-- Generated Port for Entity w_disp
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_disp
);
end component;
-- ---------
component w_osc
-- No Generated Generics
port (
-- Generated Port for Entity w_osc
pd : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
xo : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_osc
);
end component;
-- ---------
component w_pad_dire
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dire
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dire
);
end component;
-- ---------
component w_pad_dir
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dir
di : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dir
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_1 : std_ulogic;
signal mix_logic0_0 : std_ulogic;
-- __I_NODRV_I signal clki2c : std_ulogic;
signal clki3c : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal pad_dir_di : std_ulogic;
-- __I_OUT_OPEN signal pad_dir_di38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_do38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_en38 : std_ulogic;
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_1 <= '1';
mix_logic0_0 <= '0';
p_mix_pad_di_1_go <= pad_di_1; -- __I_O_BIT_PORT
p_mix_pad_di_12_go <= pad_di_12; -- __I_O_BIT_PORT
p_mix_pad_di_13_go <= pad_di_13; -- __I_O_BIT_PORT
p_mix_pad_di_14_go <= pad_di_14; -- __I_O_BIT_PORT
p_mix_pad_di_15_go <= pad_di_15; -- __I_O_BIT_PORT
p_mix_pad_di_16_go <= pad_di_16; -- __I_O_BIT_PORT
p_mix_pad_di_17_go <= pad_di_17; -- __I_O_BIT_PORT
p_mix_pad_di_18_go <= pad_di_18; -- __I_O_BIT_PORT
p_mix_pad_di_31_go <= pad_di_31; -- __I_O_BIT_PORT
p_mix_pad_di_32_go <= pad_di_32; -- __I_O_BIT_PORT
p_mix_pad_di_33_go <= pad_di_33; -- __I_O_BIT_PORT
p_mix_pad_di_34_go <= pad_di_34; -- __I_O_BIT_PORT
p_mix_pad_di_39_go <= pad_di_39; -- __I_O_BIT_PORT
p_mix_pad_di_40_go <= pad_di_40; -- __I_O_BIT_PORT
pad_do_12 <= p_mix_pad_do_12_gi; -- __I_I_BIT_PORT
pad_do_13 <= p_mix_pad_do_13_gi; -- __I_I_BIT_PORT
pad_do_14 <= p_mix_pad_do_14_gi; -- __I_I_BIT_PORT
pad_do_15 <= p_mix_pad_do_15_gi; -- __I_I_BIT_PORT
pad_do_16 <= p_mix_pad_do_16_gi; -- __I_I_BIT_PORT
pad_do_17 <= p_mix_pad_do_17_gi; -- __I_I_BIT_PORT
pad_do_18 <= p_mix_pad_do_18_gi; -- __I_I_BIT_PORT
pad_do_2 <= p_mix_pad_do_2_gi; -- __I_I_BIT_PORT
pad_do_31 <= p_mix_pad_do_31_gi; -- __I_I_BIT_PORT
pad_do_32 <= p_mix_pad_do_32_gi; -- __I_I_BIT_PORT
pad_do_35 <= p_mix_pad_do_35_gi; -- __I_I_BIT_PORT
pad_do_36 <= p_mix_pad_do_36_gi; -- __I_I_BIT_PORT
pad_do_39 <= p_mix_pad_do_39_gi; -- __I_I_BIT_PORT
pad_do_40 <= p_mix_pad_do_40_gi; -- __I_I_BIT_PORT
pad_en_12 <= p_mix_pad_en_12_gi; -- __I_I_BIT_PORT
pad_en_13 <= p_mix_pad_en_13_gi; -- __I_I_BIT_PORT
pad_en_14 <= p_mix_pad_en_14_gi; -- __I_I_BIT_PORT
pad_en_15 <= p_mix_pad_en_15_gi; -- __I_I_BIT_PORT
pad_en_16 <= p_mix_pad_en_16_gi; -- __I_I_BIT_PORT
pad_en_17 <= p_mix_pad_en_17_gi; -- __I_I_BIT_PORT
pad_en_18 <= p_mix_pad_en_18_gi; -- __I_I_BIT_PORT
pad_en_2 <= p_mix_pad_en_2_gi; -- __I_I_BIT_PORT
pad_en_31 <= p_mix_pad_en_31_gi; -- __I_I_BIT_PORT
pad_en_32 <= p_mix_pad_en_32_gi; -- __I_I_BIT_PORT
pad_en_35 <= p_mix_pad_en_35_gi; -- __I_I_BIT_PORT
pad_en_36 <= p_mix_pad_en_36_gi; -- __I_I_BIT_PORT
pad_en_39 <= p_mix_pad_en_39_gi; -- __I_I_BIT_PORT
pad_en_40 <= p_mix_pad_en_40_gi; -- __I_I_BIT_PORT
pad_pu_31 <= p_mix_pad_pu_31_gi; -- __I_I_BIT_PORT
pad_pu_32 <= p_mix_pad_pu_32_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for data_10_pad
data_10_pad: w_data3
port map (
di => pad_di_32, -- data in from pad
do => pad_do_32, -- data out to pad
en => pad_en_32, -- pad output enable
pu => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for data_10_pad
-- Generated Instance Port Map for data_9_pad
data_9_pad: w_data2
port map (
di => pad_di_31, -- data in from pad
do => pad_do_31, -- data out to pad
en => pad_en_31, -- pad output enable
pu => pad_pu_31 -- pull-up control
);
-- End of Generated Instance Port Map for data_9_pad
-- Generated Instance Port Map for data_i1_pad
data_i1_pad: w_pad_i
port map (
di => pad_di_1 -- data in from pad
);
-- End of Generated Instance Port Map for data_i1_pad
-- Generated Instance Port Map for data_i33_pad
data_i33_pad: w_pad_i
port map (
di => pad_di_33 -- data in from pad
);
-- End of Generated Instance Port Map for data_i33_pad
-- Generated Instance Port Map for data_i34_pad
data_i34_pad: w_pad_i
port map (
di => pad_di_34 -- data in from pad
);
-- End of Generated Instance Port Map for data_i34_pad
-- Generated Instance Port Map for data_o1_pad
data_o1_pad: w_pad_o
port map (
do => pad_do_2, -- data out to pad
en => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for data_o1_pad
-- Generated Instance Port Map for data_o35_pad
data_o35_pad: w_pad_o
port map (
do => pad_do_35, -- data out to pad
en => pad_en_35 -- pad output enable
);
-- End of Generated Instance Port Map for data_o35_pad
-- Generated Instance Port Map for data_o36_pad
data_o36_pad: w_pad_o
port map (
do => pad_do_36, -- data out to pad
en => pad_en_36 -- pad output enable
);
-- End of Generated Instance Port Map for data_o36_pad
-- Generated Instance Port Map for disp_10_pad
disp_10_pad: w_disp
port map (
di => pad_di_40, -- data in from pad
do => pad_do_40, -- data out to pad
en => pad_en_40 -- pad output enable
);
-- End of Generated Instance Port Map for disp_10_pad
-- Generated Instance Port Map for disp_2_pad
disp_2_pad: w_disp
port map (
di => pad_di_12, -- data in from pad
do => pad_do_12, -- data out to pad
en => pad_en_12 -- pad output enable
);
-- End of Generated Instance Port Map for disp_2_pad
-- Generated Instance Port Map for disp_3_pad
disp_3_pad: w_disp
port map (
di => pad_di_13, -- data in from pad
do => pad_do_13, -- data out to pad
en => pad_en_13 -- pad output enable
);
-- End of Generated Instance Port Map for disp_3_pad
-- Generated Instance Port Map for disp_4_pad
disp_4_pad: w_disp
port map (
di => pad_di_14, -- data in from pad
do => pad_do_14, -- data out to pad
en => pad_en_14 -- pad output enable
);
-- End of Generated Instance Port Map for disp_4_pad
-- Generated Instance Port Map for disp_5_pad
disp_5_pad: w_disp
port map (
di => pad_di_15, -- data in from pad
do => pad_do_15, -- data out to pad
en => pad_en_15 -- pad output enable
);
-- End of Generated Instance Port Map for disp_5_pad
-- Generated Instance Port Map for disp_6_pad
disp_6_pad: w_disp
port map (
di => pad_di_16, -- data in from pad
do => pad_do_16, -- data out to pad
en => pad_en_16 -- pad output enable
);
-- End of Generated Instance Port Map for disp_6_pad
-- Generated Instance Port Map for disp_7_pad
disp_7_pad: w_disp
port map (
di => pad_di_17, -- data in from pad
do => pad_do_17, -- data out to pad
en => pad_en_17 -- pad output enable
);
-- End of Generated Instance Port Map for disp_7_pad
-- Generated Instance Port Map for disp_8_pad
disp_8_pad: w_disp
port map (
di => pad_di_18, -- data in from pad
do => pad_do_18, -- data out to pad
en => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for disp_8_pad
-- Generated Instance Port Map for disp_9_pad
disp_9_pad: w_disp
port map (
di => pad_di_39, -- data in from pad
do => pad_do_39, -- data out to pad
en => pad_en_39 -- pad output enable
);
-- End of Generated Instance Port Map for disp_9_pad
-- Generated Instance Port Map for osc_1_pad
osc_1_pad: w_osc
port map (
pd => mix_logic1_0,
-- __I_NODRV_I xo => __nodrv__/clki2c
);
-- End of Generated Instance Port Map for osc_1_pad
-- Generated Instance Port Map for osc_2_pad
osc_2_pad: w_osc
port map (
pd => mix_logic1_1,
xo => clki3c
);
-- End of Generated Instance Port Map for osc_2_pad
-- Generated Instance Port Map for osc_3_pad
osc_3_pad: w_osc
port map (
pd => mix_logic0_0,
xo => clki3c
);
-- End of Generated Instance Port Map for osc_3_pad
-- Generated Instance Port Map for pad_dire_pad
pad_dire_pad: w_pad_dire
port map (
di => open, -- __I_OUT_OPEN
-- __I_NODRV_I -- __I_NODRV_I do => __nodrv__/pad_dir_en38/pad_dir_do38,
-- __I_NODRV_I en => __nodrv__/pad_dir_en38
);
-- End of Generated Instance Port Map for pad_dire_pad
-- Generated Instance Port Map for pad_dirli_pad
pad_dirli_pad: w_pad_dir
port map (
di => open -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for pad_dirli_pad
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
7eb0989fdfcb311f3fb96b8b544e470e
| 0.605867 | 2.474668 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/blk_mem_gen_outputMem_ste/example_design/bmg_wrapper.vhd
| 1 | 10,219 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_outputMem_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_outputMem_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
gpl-2.0
|
50c155f903b0e6793d533481cd7aa737
| 0.492612 | 3.838843 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_a_e-rtl-a.vhd
| 1 | 5,527 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_1 : out std_ulogic; -- Use internally test1
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_o : out std_ulogic_vector(10 downto 3);
port_o02 : out std_ulogic_vector(10 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_ab_1 : in std_ulogic; -- Use internally test1
port_i : in std_ulogic_vector(10 downto 3);
port_i02 : in std_ulogic_vector(10 downto 1)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_2 : in std_ulogic_vector(4 downto 0); -- Bus with hole in the middle
port_3 : in std_ulogic_vector(3 downto 0) -- Bus combining o.k.
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_port_offset_01 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02b : std_ulogic_vector(1 downto 0);
signal test1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal test2 : std_ulogic_vector(4 downto 0);
signal test3 : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_test1_go <= test1; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_1 => test1, -- Use internally test1
port_2 => test2(0), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(0), -- Bus combining o.k.
port_o => s_port_offset_01,
port_o02(1 downto 0) => s_port_offset_02b, -- __W_PORT
port_o02(10 downto 3) => s_port_offset_02 -- __W_PORT
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_2 => test2(1), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(1), -- Bus combining o.k.
port_ab_1 => test1, -- Use internally test1
port_i => s_port_offset_01,
port_i02(10 downto 3) => s_port_offset_02, -- __W_PORT
port_i02(2 downto 1) => s_port_offset_02b -- __W_PORT
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_2 => test2(3), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(2) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_2 => test2(4), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(3) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_2 => test2, -- Bus with hole in the middleNeeds input to be happy
port_3 => test3 -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
b280fe115fa0a07df1964dc3cd519d02
| 0.626741 | 2.977909 | false | true | false | false |
mitchsm/nvc
|
test/regress/issue29.vhd
| 5 | 769 |
entity sub is
generic (
width : integer );
port (
x : in bit_vector(width - 1 downto 0);
y : in bit_vector;
z : out bit_vector(width - 1 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y after 1 us;
end architecture;
-------------------------------------------------------------------------------
entity issue29 is
end entity;
architecture rtl of issue29 is
signal z : bit_vector(7 downto 0);
begin
sub_i: entity work.sub
generic map (
width => 8 )
port map (
x => X"ab",
y => X"cd",
z => z );
process is
begin
wait for 2 us;
assert z = "10001001";
wait;
end process;
end architecture;
|
gpl-3.0
|
0a2a6eec76cba485da251a0c1c579675
| 0.46814 | 4.134409 | false | false | false | false |
blutsvente/MIX
|
test/results/autoopen/inst_t_e-rtl-a.vhd
| 1 | 3,925 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jul 6 05:51:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_s_aio17_gc : inout std_ulogic;
p_mix_s_ao11_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao3_go : out std_ulogic;
s_ai14 : in std_ulogic_vector(7 downto 0);
s_ai16 : out std_ulogic_vector(7 downto 0);
s_ai6 : in std_ulogic;
s_ai8 : out std_ulogic;
s_aio18 : inout std_ulogic;
s_aio19 : inout std_ulogic;
s_ao1 : out std_ulogic;
s_ao12 : out std_ulogic_vector(7 downto 0);
s_ao13 : out std_ulogic_vector(7 downto 0);
s_ao4 : out std_ulogic;
s_ao5 : out std_ulogic;
s_ao9 : in std_ulogic_vector(7 downto 0);
s_outname : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_e_e
-- No Generated Generics
-- Generated Generics for Entity inst_e_e
-- End of Generated Generics for Entity inst_e_e
port (
-- Generated Port for Entity inst_e_e
p_mix_s_eo3_go : out std_ulogic;
s_eo1 : out std_ulogic;
s_eo2 : out std_ulogic;
s_eo4 : out std_ulogic;
s_eo5 : out std_ulogic;
s_outname : in std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Generated Signal List
--
-- __I_OUT_OPEN signal s_ao1 : std_ulogic;
-- __I_OUT_OPEN signal s_ao12 : std_ulogic_vector(7 downto 0);
-- __I_OUT_OPEN signal s_ao4 : std_ulogic;
-- __I_NODRV_I signal s_ao9 : std_ulogic_vector(7 downto 0);
-- __I_OUT_OPEN signal s_eo1 : std_ulogic;
-- __I_OUT_OPEN signal s_eo2 : std_ulogic;
-- __I_OUT_OPEN signal s_eo4 : std_ulogic;
signal s_outname : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_s_aio17_gc => s_aio17,
p_mix_s_ao11_go => s_ao11,
p_mix_s_ao3_go => s_ao3,
s_ai14 => s_ai14,
s_ai16 => s_ai16,
s_ai6 => s_ai6,
s_ai8 => s_ai8,
s_aio18 => s_aio18,
s_aio19 => s_aio19,
s_ao1 => open, -- __I_OUT_OPEN
s_ao12 => open, -- __I_OUT_OPEN
s_ao13 => s_ao13,
s_ao4 => open, -- __I_OUT_OPEN
s_ao5 => s_ao5,
-- __I_NODRV_I s_ao9 => __nodrv__/s_ao9,
s_outname => s_outname
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_s_eo3_go => s_eo3,
s_eo1 => open, -- __I_OUT_OPEN
s_eo2 => open, -- __I_OUT_OPEN
s_eo4 => open, -- __I_OUT_OPEN
s_eo5 => s_eo5,
s_outname => s_outname
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
8ae7a78f054aaddb7753e68640c32be3
| 0.581146 | 2.583937 | false | false | false | false |
mitchsm/nvc
|
test/elab/elab3.vhd
| 5 | 1,328 |
package p is
function log2(x : in integer) return integer;
end package;
package body p is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
entity sub is
generic ( W : integer );
end entity;
use work.p.all;
architecture test of sub is
constant B : integer := log2(W);
signal s : bit_vector(B - 1 downto 0);
constant C : bit_vector(log2(B) to 1) := (others => '0');
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
begin
s : entity work.sub
generic map ( 10 );
end architecture;
-------------------------------------------------------------------------------
use work.p.all;
entity top2 is
end entity;
architecture test of top2 is
constant W : integer := 10;
constant B : integer := log2(W);
signal s : bit_vector(B - 1 downto 0);
begin
end architecture;
|
gpl-3.0
|
960de00447092fda03928a430205181e
| 0.464608 | 4.229299 | false | false | false | false |
mitchsm/nvc
|
test/regress/array3.vhd
| 5 | 530 |
entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
|
gpl-3.0
|
66e6e9f6a50e9075faf5f0c50332e372
| 0.469811 | 2.99435 | false | false | false | false |
mitchsm/nvc
|
lib/synopsys/std_logic_textio.vhd
| 5 | 18,668 |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
gpl-3.0
|
766683af7d76a62e0431fcd888102400
| 0.600654 | 2.86319 | false | false | false | false |
blutsvente/MIX
|
test/results/macro/splice/inst_splice_e_s-rtl-a.vhd
| 1 | 35,427 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_splice_e_s
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:03:31 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_splice_e_s-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: inst_splice_e_s-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_splice_e_s
--
architecture rtl of inst_splice_e_s is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_splice_3_0_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_0_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_0 : out std_ulogic -- Splice signal connector up 3, 0
-- End of Generated Port for Entity inst_splice_3_0_e_s
);
end component;
-- ---------
component inst_splice_3_1_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_1_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_1 : out std_ulogic -- Splice signal connector up 3, 1
-- End of Generated Port for Entity inst_splice_3_1_e_s
);
end component;
-- ---------
component inst_splice_3_10_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_10_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 10 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_10 : out std_ulogic -- Splice signal connector up 3, 10
-- End of Generated Port for Entity inst_splice_3_10_e_s
);
end component;
-- ---------
component inst_splice_3_11_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_11_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 11 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_11 : out std_ulogic -- Splice signal connector up 3, 11
-- End of Generated Port for Entity inst_splice_3_11_e_s
);
end component;
-- ---------
component inst_splice_3_12_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_12_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 12 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_12 : out std_ulogic -- Splice signal connector up 3, 12
-- End of Generated Port for Entity inst_splice_3_12_e_s
);
end component;
-- ---------
component inst_splice_3_13_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_13_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 13 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_13 : out std_ulogic -- Splice signal connector up 3, 13
-- End of Generated Port for Entity inst_splice_3_13_e_s
);
end component;
-- ---------
component inst_splice_3_14_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_14_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 14 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_14 : out std_ulogic -- Splice signal connector up 3, 14
-- End of Generated Port for Entity inst_splice_3_14_e_s
);
end component;
-- ---------
component inst_splice_3_15_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_15_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 15 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_15 : out std_ulogic -- Splice signal connector up 3, 15
-- End of Generated Port for Entity inst_splice_3_15_e_s
);
end component;
-- ---------
component inst_splice_3_2_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_2_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_2 : out std_ulogic -- Splice signal connector up 3, 2
-- End of Generated Port for Entity inst_splice_3_2_e_s
);
end component;
-- ---------
component inst_splice_3_3_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_3_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_3 : out std_ulogic -- Splice signal connector up 3, 3
-- End of Generated Port for Entity inst_splice_3_3_e_s
);
end component;
-- ---------
component inst_splice_3_4_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_4_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 4 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_4 : out std_ulogic -- Splice signal connector up 3, 4
-- End of Generated Port for Entity inst_splice_3_4_e_s
);
end component;
-- ---------
component inst_splice_3_5_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_5_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 5 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_5 : out std_ulogic -- Splice signal connector up 3, 5
-- End of Generated Port for Entity inst_splice_3_5_e_s
);
end component;
-- ---------
component inst_splice_3_6_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_6_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 6 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_6 : out std_ulogic -- Splice signal connector up 3, 6
-- End of Generated Port for Entity inst_splice_3_6_e_s
);
end component;
-- ---------
component inst_splice_3_7_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_7_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 7 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_7 : out std_ulogic -- Splice signal connector up 3, 7
-- End of Generated Port for Entity inst_splice_3_7_e_s
);
end component;
-- ---------
component inst_splice_3_8_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_8_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 8 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_8 : out std_ulogic -- Splice signal connector up 3, 8
-- End of Generated Port for Entity inst_splice_3_8_e_s
);
end component;
-- ---------
component inst_splice_3_9_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_9_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 9 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_9 : out std_ulogic -- Splice signal connector up 3, 9
-- End of Generated Port for Entity inst_splice_3_9_e_s
);
end component;
-- ---------
component inst_splice_4_0_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_0_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 0 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_0_e_s
);
end component;
-- ---------
component inst_splice_4_1_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_1_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 1 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_1_e_s
);
end component;
-- ---------
component inst_splice_4_10_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_10_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 10 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 10 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_10_e_s
);
end component;
-- ---------
component inst_splice_4_11_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_11_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 11 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 11 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_11_e_s
);
end component;
-- ---------
component inst_splice_4_12_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_12_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 12 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 12 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_12_e_s
);
end component;
-- ---------
component inst_splice_4_13_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_13_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 13 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 13 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_13_e_s
);
end component;
-- ---------
component inst_splice_4_14_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_14_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 14 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 14 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_14_e_s
);
end component;
-- ---------
component inst_splice_4_15_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_15_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 15 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 15 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_15_e_s
);
end component;
-- ---------
component inst_splice_4_2_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_2_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 2 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_2_e_s
);
end component;
-- ---------
component inst_splice_4_3_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_3_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 3 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_3_e_s
);
end component;
-- ---------
component inst_splice_4_4_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_4_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 4 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 4 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_4_e_s
);
end component;
-- ---------
component inst_splice_4_5_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_5_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 5 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 5 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_5_e_s
);
end component;
-- ---------
component inst_splice_4_6_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_6_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 6 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 6 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_6_e_s
);
end component;
-- ---------
component inst_splice_4_7_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_7_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 7 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 7 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_7_e_s
);
end component;
-- ---------
component inst_splice_4_8_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_8_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 8 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 8 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_8_e_s
);
end component;
-- ---------
component inst_splice_4_9_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_9_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 9 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 9 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_9_e_s
);
end component;
-- ---------
component inst_spbit_e_s -- common entitiy
-- No Generated Generics
port (
-- Generated Port for Entity inst_spbit_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 5, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_5 : in std_ulogic -- Splice signal connector in 5, 3 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_spbit_e_s
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_splice_3 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_4 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_5 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_join_4 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_join_5 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
s_splice_3 <= p_mix_s_splice_3_gi; -- __I_I_BUS_PORT
p_mix_s_splice_3_0_go <= s_splice_3_0; -- __I_O_BIT_PORT
p_mix_s_splice_3_1_go <= s_splice_3_1; -- __I_O_BIT_PORT
p_mix_s_splice_3_10_go <= s_splice_3_10; -- __I_O_BIT_PORT
p_mix_s_splice_3_11_go <= s_splice_3_11; -- __I_O_BIT_PORT
p_mix_s_splice_3_12_go <= s_splice_3_12; -- __I_O_BIT_PORT
p_mix_s_splice_3_13_go <= s_splice_3_13; -- __I_O_BIT_PORT
p_mix_s_splice_3_14_go <= s_splice_3_14; -- __I_O_BIT_PORT
p_mix_s_splice_3_15_go <= s_splice_3_15; -- __I_O_BIT_PORT
p_mix_s_splice_3_2_go <= s_splice_3_2; -- __I_O_BIT_PORT
p_mix_s_splice_3_3_go <= s_splice_3_3; -- __I_O_BIT_PORT
p_mix_s_splice_3_4_go <= s_splice_3_4; -- __I_O_BIT_PORT
p_mix_s_splice_3_5_go <= s_splice_3_5; -- __I_O_BIT_PORT
p_mix_s_splice_3_6_go <= s_splice_3_6; -- __I_O_BIT_PORT
p_mix_s_splice_3_7_go <= s_splice_3_7; -- __I_O_BIT_PORT
p_mix_s_splice_3_8_go <= s_splice_3_8; -- __I_O_BIT_PORT
p_mix_s_splice_3_9_go <= s_splice_3_9; -- __I_O_BIT_PORT
s_splice_4 <= p_mix_s_splice_4_gi; -- __I_I_BUS_PORT
s_splice_5 <= p_mix_s_splice_5_gi; -- __I_I_BUS_PORT
p_mix_s_splice_join_4_go <= s_splice_join_4; -- __I_O_BUS_PORT
p_mix_s_splice_join_5_go <= s_splice_join_5; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_splice_3_0
inst_splice_3_0: inst_splice_3_0_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(0), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_0 => s_splice_3_0 -- Splice signal connector up 3, 0
);
-- End of Generated Instance Port Map for inst_splice_3_0
-- Generated Instance Port Map for inst_splice_3_1
inst_splice_3_1: inst_splice_3_1_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(1), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_1 => s_splice_3_1 -- Splice signal connector up 3, 1
);
-- End of Generated Instance Port Map for inst_splice_3_1
-- Generated Instance Port Map for inst_splice_3_10
inst_splice_3_10: inst_splice_3_10_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(10), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_10 => s_splice_3_10 -- Splice signal connector up 3, 10
);
-- End of Generated Instance Port Map for inst_splice_3_10
-- Generated Instance Port Map for inst_splice_3_11
inst_splice_3_11: inst_splice_3_11_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(11), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_11 => s_splice_3_11 -- Splice signal connector up 3, 11
);
-- End of Generated Instance Port Map for inst_splice_3_11
-- Generated Instance Port Map for inst_splice_3_12
inst_splice_3_12: inst_splice_3_12_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(12), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_12 => s_splice_3_12 -- Splice signal connector up 3, 12
);
-- End of Generated Instance Port Map for inst_splice_3_12
-- Generated Instance Port Map for inst_splice_3_13
inst_splice_3_13: inst_splice_3_13_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(13), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_13 => s_splice_3_13 -- Splice signal connector up 3, 13
);
-- End of Generated Instance Port Map for inst_splice_3_13
-- Generated Instance Port Map for inst_splice_3_14
inst_splice_3_14: inst_splice_3_14_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(14), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_14 => s_splice_3_14 -- Splice signal connector up 3, 14
);
-- End of Generated Instance Port Map for inst_splice_3_14
-- Generated Instance Port Map for inst_splice_3_15
inst_splice_3_15: inst_splice_3_15_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(15), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_15 => s_splice_3_15 -- Splice signal connector up 3, 15
);
-- End of Generated Instance Port Map for inst_splice_3_15
-- Generated Instance Port Map for inst_splice_3_2
inst_splice_3_2: inst_splice_3_2_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(2), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_2 => s_splice_3_2 -- Splice signal connector up 3, 2
);
-- End of Generated Instance Port Map for inst_splice_3_2
-- Generated Instance Port Map for inst_splice_3_3
inst_splice_3_3: inst_splice_3_3_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(3), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_3 => s_splice_3_3 -- Splice signal connector up 3, 3
);
-- End of Generated Instance Port Map for inst_splice_3_3
-- Generated Instance Port Map for inst_splice_3_4
inst_splice_3_4: inst_splice_3_4_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(4), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_4 => s_splice_3_4 -- Splice signal connector up 3, 4
);
-- End of Generated Instance Port Map for inst_splice_3_4
-- Generated Instance Port Map for inst_splice_3_5
inst_splice_3_5: inst_splice_3_5_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(5), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_5 => s_splice_3_5 -- Splice signal connector up 3, 5
);
-- End of Generated Instance Port Map for inst_splice_3_5
-- Generated Instance Port Map for inst_splice_3_6
inst_splice_3_6: inst_splice_3_6_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(6), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_6 => s_splice_3_6 -- Splice signal connector up 3, 6
);
-- End of Generated Instance Port Map for inst_splice_3_6
-- Generated Instance Port Map for inst_splice_3_7
inst_splice_3_7: inst_splice_3_7_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(7), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_7 => s_splice_3_7 -- Splice signal connector up 3, 7
);
-- End of Generated Instance Port Map for inst_splice_3_7
-- Generated Instance Port Map for inst_splice_3_8
inst_splice_3_8: inst_splice_3_8_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(8), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_8 => s_splice_3_8 -- Splice signal connector up 3, 8
);
-- End of Generated Instance Port Map for inst_splice_3_8
-- Generated Instance Port Map for inst_splice_3_9
inst_splice_3_9: inst_splice_3_9_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(9), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_9 => s_splice_3_9 -- Splice signal connector up 3, 9
);
-- End of Generated Instance Port Map for inst_splice_3_9
-- Generated Instance Port Map for inst_splice_4_0
inst_splice_4_0: inst_splice_4_0_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(0), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(0) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_0
-- Generated Instance Port Map for inst_splice_4_1
inst_splice_4_1: inst_splice_4_1_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(1), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(1) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_1
-- Generated Instance Port Map for inst_splice_4_10
inst_splice_4_10: inst_splice_4_10_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(10), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(10) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_10
-- Generated Instance Port Map for inst_splice_4_11
inst_splice_4_11: inst_splice_4_11_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(11), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(11) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_11
-- Generated Instance Port Map for inst_splice_4_12
inst_splice_4_12: inst_splice_4_12_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(12), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(12) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_12
-- Generated Instance Port Map for inst_splice_4_13
inst_splice_4_13: inst_splice_4_13_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(13), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(13) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_13
-- Generated Instance Port Map for inst_splice_4_14
inst_splice_4_14: inst_splice_4_14_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(14), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(14) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_14
-- Generated Instance Port Map for inst_splice_4_15
inst_splice_4_15: inst_splice_4_15_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(15), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(15) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_15
-- Generated Instance Port Map for inst_splice_4_2
inst_splice_4_2: inst_splice_4_2_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(2), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(2) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_2
-- Generated Instance Port Map for inst_splice_4_3
inst_splice_4_3: inst_splice_4_3_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(3), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(3) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_3
-- Generated Instance Port Map for inst_splice_4_4
inst_splice_4_4: inst_splice_4_4_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(4), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(4) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_4
-- Generated Instance Port Map for inst_splice_4_5
inst_splice_4_5: inst_splice_4_5_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(5), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(5) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_5
-- Generated Instance Port Map for inst_splice_4_6
inst_splice_4_6: inst_splice_4_6_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(6), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(6) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_6
-- Generated Instance Port Map for inst_splice_4_7
inst_splice_4_7: inst_splice_4_7_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(7), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(7) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_7
-- Generated Instance Port Map for inst_splice_4_8
inst_splice_4_8: inst_splice_4_8_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(8), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(8) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_8
-- Generated Instance Port Map for inst_splice_4_9
inst_splice_4_9: inst_splice_4_9_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(9), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(9) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_9
-- Generated Instance Port Map for inst_splice_5_0
inst_splice_5_0: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(0), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(0) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_0
-- Generated Instance Port Map for inst_splice_5_1
inst_splice_5_1: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(1), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(1) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_1
-- Generated Instance Port Map for inst_splice_5_2
inst_splice_5_2: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(2), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(2) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_2
-- Generated Instance Port Map for inst_splice_5_3
inst_splice_5_3: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(3), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(3) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_3
-- Generated Instance Port Map for inst_splice_5_4
inst_splice_5_4: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(4), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(4) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_4
-- Generated Instance Port Map for inst_splice_5_5
inst_splice_5_5: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(5), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(5) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_5
-- Generated Instance Port Map for inst_splice_5_6
inst_splice_5_6: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(6), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(6) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_6
-- Generated Instance Port Map for inst_splice_5_7
inst_splice_5_7: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(7), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(7) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_7
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
5c2ff191e867c727a30b3b7754ec96d1
| 0.670421 | 2.904805 | false | false | false | false |
mitchsm/nvc
|
test/sem/varinit.vhd
| 4 | 1,350 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity computation is
end entity;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
begin
end architecture;
|
gpl-3.0
|
1ada43c761f8046a7076d3a39e57cbfa
| 0.624444 | 3.901734 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter1.vhd
| 1 | 4,451 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter1 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END lpm_counter1;
ARCHITECTURE SYN OF lpm_counter1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(10 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 2000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 11
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "2000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "2000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 11 0 OUTPUT NODEFVAL "q[10..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 11 0 @q 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
bcdd93652fd4879346f48954d5f5b85a
| 0.652662 | 3.696844 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_1_0/synth/zc702_proc_sys_reset_1_0.vhd
| 1 | 6,659 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_1_0;
ARCHITECTURE zc702_proc_sys_reset_1_0_arch OF zc702_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_proc_sys_reset_1_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_proc_sys_reset_1_0_arch : ARCHITECTURE IS "zc702_proc_sys_reset_1_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_proc_sys_reset_1_0_arch: ARCHITECTURE IS "zc702_proc_sys_reset_1_0,proc_sys_reset,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_1_0_arch;
|
mit
|
07734998f118389fef2f6fa5f38856d6
| 0.71317 | 3.439566 | false | false | false | false |
mitchsm/nvc
|
test/regress/access4.vhd
| 4 | 533 |
entity access4 is
end entity;
architecture test of access4 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
p(1 to 3) := (1, 2, 3);
assert p(1 to 3) = (1, 2, 3);
assert p(2) = 2;
p.all(4 to 6) := (4, 5, 6);
assert p.all(4) = 4;
assert p'length = 10;
assert p.all'low = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
c297a36f705ad0a87751f1287c017bb4
| 0.525328 | 3.098837 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/inst_ea_e-rtl-a.vhd
| 1 | 19,634 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-a.vhd,v 1.4 2006/06/22 07:20:00 wig Exp $
-- $Date: 2006/06/22 07:20:00 $
-- $Log: inst_ea_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/22 07:20:00 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ea_e
--
architecture rtl of inst_ea_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eaa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eaa_e
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0); -- CBUSinterface
mbist_clut_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_fifo_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
unsplice_a1_no3 : in std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : in std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : in std_ulogic_vector(100 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : in std_ulogic_vector(97 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : in std_ulogic_vector(99 downto 2); -- connect mid 100 bits
unsplice_bad_a : in std_ulogic_vector(1 downto 0);
unsplice_bad_b : in std_ulogic_vector(3 downto 0); -- # conflict
video_p_0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widemerge_a1_p : in std_ulogic_vector(31 downto 0);
widesig_p : in std_ulogic_vector(30 downto 0);
widesig_p_0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_10 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_11 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_12 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_13 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_14 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_15 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_16 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_17 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_18 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_19 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_20 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_21 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_22 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_23 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_24 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_25 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_26 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_27 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_28 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_29 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_3 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_30 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_31 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_4 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_5 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_6 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_7 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_8 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_9 : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_eaa_e
);
end component;
-- ---------
component inst_eab_e
-- No Generated Generics
-- Generated Generics for Entity inst_eab_e
-- End of Generated Generics for Entity inst_eab_e
port (
-- Generated Port for Entity inst_eab_e
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CBUSinterface
v_select : in std_ulogic_vector(5 downto 0); -- VPUinterface
video_p_1 : in std_ulogic
-- End of Generated Port for Entity inst_eab_e
);
end component;
-- ---------
component inst_eac_e
-- No Generated Generics
-- Generated Generics for Entity inst_eac_e
-- End of Generated Generics for Entity inst_eac_e
port (
-- Generated Port for Entity inst_eac_e
adp_bist_fail : out std_ulogic;
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CBUSinterface
cp_lcmd : in std_ulogic_vector(6 downto 0); -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2 : in std_ulogic_vector(6 downto 0); -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p : in std_ulogic_vector(6 downto 0); -- Signal name != port name
cpu_bist_fail : out std_ulogic;
cvi_sbist_fail0 : in std_ulogic;
cvi_sbist_fail1 : in std_ulogic;
ema_bist_fail : out std_ulogic;
ga_sbist_fail0 : in std_ulogic;
ga_sbist_fail1 : in std_ulogic;
ifu_bist_fail : out std_ulogic;
mcu_bist_fail : out std_ulogic;
pdu_bist_fail0 : out std_ulogic;
pdu_bist_fail1 : out std_ulogic;
tsd_bist_fail : out std_ulogic;
video_p_2 : in std_ulogic
-- End of Generated Port for Entity inst_eac_e
);
end component;
-- ---------
component inst_ead_e
-- No Generated Generics
-- Generated Generics for Entity inst_ead_e
-- End of Generated Generics for Entity inst_ead_e
port (
-- Generated Port for Entity inst_ead_e
video_p_3 : in std_ulogic
-- End of Generated Port for Entity inst_ead_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_bus_0 : std_ulogic_vector(5 downto 0);
signal mix_logic0_bus_1 : std_ulogic_vector(5 downto 0);
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd_2 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
constant cp_lcmd_2_tolow_c : std_ulogic_vector(5 downto 0) := ( others => '0' );
signal cp_lcmd_2_tolow : std_ulogic_vector(5 downto 0);
signal cp_lcmd_3 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widemerge_a1 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_19 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_20 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_21 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_22 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_23 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_24 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_25 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_26 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_28 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_29 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_30 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_2 <= '0';
mix_logic0_bus_0 <= ( others => '0' );
mix_logic0_bus_1 <= ( others => '0' );
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
cp_lcmd(6) <= p_mix_cp_lcmd_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
cp_lcmd_2(6) <= p_mix_cp_lcmd_2_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
cp_lcmd_2_tolow <= cp_lcmd_2_tolow_c;
cp_lcmd_3(6) <= p_mix_cp_lcmd_3_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
tmi_sbist_fail(11 downto 10) <= p_mix_tmi_sbist_fail_11_10_gi(1 downto 0); -- __I_I_SLICE_PORT
p_mix_tmi_sbist_fail_9_0_go(9 downto 0) <= tmi_sbist_fail(9 downto 0); -- __I_O_SLICE_PORT
unsplice_a1_no3(125 downto 0) <= p_mix_unsplice_a1_no3_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a1_no3(127) <= p_mix_unsplice_a1_no3_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
widemerge_a1 <= p_mix_widemerge_a1_31_0_gi; -- __I_I_BUS_PORT
widesig <= p_mix_widesig_31_0_gi; -- __I_I_BUS_PORT
widesig_r_0 <= p_mix_widesig_r_0_gi; -- __I_I_BIT_PORT
widesig_r_1 <= p_mix_widesig_r_1_gi; -- __I_I_BIT_PORT
widesig_r_10 <= p_mix_widesig_r_10_gi; -- __I_I_BIT_PORT
widesig_r_11 <= p_mix_widesig_r_11_gi; -- __I_I_BIT_PORT
widesig_r_12 <= p_mix_widesig_r_12_gi; -- __I_I_BIT_PORT
widesig_r_13 <= p_mix_widesig_r_13_gi; -- __I_I_BIT_PORT
widesig_r_14 <= p_mix_widesig_r_14_gi; -- __I_I_BIT_PORT
widesig_r_15 <= p_mix_widesig_r_15_gi; -- __I_I_BIT_PORT
widesig_r_16 <= p_mix_widesig_r_16_gi; -- __I_I_BIT_PORT
widesig_r_17 <= p_mix_widesig_r_17_gi; -- __I_I_BIT_PORT
widesig_r_18 <= p_mix_widesig_r_18_gi; -- __I_I_BIT_PORT
widesig_r_19 <= p_mix_widesig_r_19_gi; -- __I_I_BIT_PORT
widesig_r_2 <= p_mix_widesig_r_2_gi; -- __I_I_BIT_PORT
widesig_r_20 <= p_mix_widesig_r_20_gi; -- __I_I_BIT_PORT
widesig_r_21 <= p_mix_widesig_r_21_gi; -- __I_I_BIT_PORT
widesig_r_22 <= p_mix_widesig_r_22_gi; -- __I_I_BIT_PORT
widesig_r_23 <= p_mix_widesig_r_23_gi; -- __I_I_BIT_PORT
widesig_r_24 <= p_mix_widesig_r_24_gi; -- __I_I_BIT_PORT
widesig_r_25 <= p_mix_widesig_r_25_gi; -- __I_I_BIT_PORT
widesig_r_26 <= p_mix_widesig_r_26_gi; -- __I_I_BIT_PORT
widesig_r_27 <= p_mix_widesig_r_27_gi; -- __I_I_BIT_PORT
widesig_r_28 <= p_mix_widesig_r_28_gi; -- __I_I_BIT_PORT
widesig_r_29 <= p_mix_widesig_r_29_gi; -- __I_I_BIT_PORT
widesig_r_3 <= p_mix_widesig_r_3_gi; -- __I_I_BIT_PORT
widesig_r_30 <= p_mix_widesig_r_30_gi; -- __I_I_BIT_PORT
widesig_r_4 <= p_mix_widesig_r_4_gi; -- __I_I_BIT_PORT
widesig_r_5 <= p_mix_widesig_r_5_gi; -- __I_I_BIT_PORT
widesig_r_6 <= p_mix_widesig_r_6_gi; -- __I_I_BIT_PORT
widesig_r_7 <= p_mix_widesig_r_7_gi; -- __I_I_BIT_PORT
widesig_r_8 <= p_mix_widesig_r_8_gi; -- __I_I_BIT_PORT
widesig_r_9 <= p_mix_widesig_r_9_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eaa
inst_eaa: inst_eaa_e
port map (
-- __E_PRINTCONN unsplice_bad_a => unsplice_bad_a
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_clut_fail_o => tmi_sbist_fail(8),
mbist_fifo_fail_o => tmi_sbist_fail(9),
unsplice_a1_no3(1 downto 0) => unsplice_a1_no3(1 downto 0), -- leaves 3 unconnected
unsplice_a1_no3(127 downto 4) => unsplice_a1_no3(125 downto 2), -- leaves 3 unconnected
unsplice_a1_no3(2) => unsplice_a1_no3(127), -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
unsplice_bad_b(1 downto 0) => unsplice_bad_b(1 downto 0), -- # conflict
unsplice_bad_b(3 downto 2) => unsplice_bad_b(1 downto 0), -- # conflict
video_p_0 => video_i(0),
widemerge_a1_p => widemerge_a1,
widesig_p(0) => widesig_r_0, -- __I_BIT_TO_BUSPORT
widesig_p(1) => widesig_r_1, -- __I_BIT_TO_BUSPORT
widesig_p(10) => widesig_r_10, -- __I_BIT_TO_BUSPORT
widesig_p(11) => widesig_r_11, -- __I_BIT_TO_BUSPORT
widesig_p(12) => widesig_r_12, -- __I_BIT_TO_BUSPORT
widesig_p(13) => widesig_r_13, -- __I_BIT_TO_BUSPORT
widesig_p(14) => widesig_r_14, -- __I_BIT_TO_BUSPORT
widesig_p(15) => widesig_r_15, -- __I_BIT_TO_BUSPORT
widesig_p(16) => widesig_r_16, -- __I_BIT_TO_BUSPORT
widesig_p(17) => widesig_r_17, -- __I_BIT_TO_BUSPORT
widesig_p(18) => widesig_r_18, -- __I_BIT_TO_BUSPORT
widesig_p(19) => widesig_r_19, -- __I_BIT_TO_BUSPORT
widesig_p(2) => widesig_r_2, -- __I_BIT_TO_BUSPORT
widesig_p(20) => widesig_r_20, -- __I_BIT_TO_BUSPORT
widesig_p(21) => widesig_r_21, -- __I_BIT_TO_BUSPORT
widesig_p(22) => widesig_r_22, -- __I_BIT_TO_BUSPORT
widesig_p(23) => widesig_r_23, -- __I_BIT_TO_BUSPORT
widesig_p(24) => widesig_r_24, -- __I_BIT_TO_BUSPORT
widesig_p(25) => widesig_r_25, -- __I_BIT_TO_BUSPORT
widesig_p(26) => widesig_r_26, -- __I_BIT_TO_BUSPORT
widesig_p(27) => widesig_r_27, -- __I_BIT_TO_BUSPORT
widesig_p(28) => widesig_r_28, -- __I_BIT_TO_BUSPORT
widesig_p(29) => widesig_r_29, -- __I_BIT_TO_BUSPORT
widesig_p(3) => widesig_r_3, -- __I_BIT_TO_BUSPORT
widesig_p(30) => widesig_r_30, -- __I_BIT_TO_BUSPORT
widesig_p(4) => widesig_r_4, -- __I_BIT_TO_BUSPORT
widesig_p(5) => widesig_r_5, -- __I_BIT_TO_BUSPORT
widesig_p(6) => widesig_r_6, -- __I_BIT_TO_BUSPORT
widesig_p(7) => widesig_r_7, -- __I_BIT_TO_BUSPORT
widesig_p(8) => widesig_r_8, -- __I_BIT_TO_BUSPORT
widesig_p(9) => widesig_r_9, -- __I_BIT_TO_BUSPORT
widesig_p_0 => widesig(0),
widesig_p_1 => widesig(1),
widesig_p_10 => widesig(10),
widesig_p_11 => widesig(11),
widesig_p_12 => widesig(12),
widesig_p_13 => widesig(13),
widesig_p_14 => widesig(14),
widesig_p_15 => widesig(15),
widesig_p_16 => widesig(16),
widesig_p_17 => widesig(17),
widesig_p_18 => widesig(18),
widesig_p_19 => widesig(19),
widesig_p_2 => widesig(2),
widesig_p_20 => widesig(20),
widesig_p_21 => widesig(21),
widesig_p_22 => widesig(22),
widesig_p_23 => widesig(23),
widesig_p_24 => widesig(24),
widesig_p_25 => widesig(25),
widesig_p_26 => widesig(26),
widesig_p_27 => widesig(27),
widesig_p_28 => widesig(28),
widesig_p_29 => widesig(29),
widesig_p_3 => widesig(3),
widesig_p_30 => widesig(30),
widesig_p_31 => widesig(31),
widesig_p_4 => widesig(4),
widesig_p_5 => widesig(5),
widesig_p_6 => widesig(6),
widesig_p_7 => widesig(7),
widesig_p_8 => widesig(8),
widesig_p_9 => widesig(9)
);
-- End of Generated Instance Port Map for inst_eaa
-- Generated Instance Port Map for inst_eab
inst_eab: inst_eab_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select(0) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(1) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(2) => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
v_select(3) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(4) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(5) => v_select(5), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
video_p_1 => video_i(1)
);
-- End of Generated Instance Port Map for inst_eab
-- Generated Instance Port Map for inst_eac
inst_eac: inst_eac_e
port map (
adp_bist_fail => tmi_sbist_fail(0),
c_addr => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
cp_lcmd(5 downto 0) => mix_logic0_bus_0, -- __W_PORT
cp_lcmd(6) => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2(5 downto 0) => cp_lcmd_2_tolow, -- __W_PORT
cp_lcmd_2(6) => cp_lcmd_2(6), -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p(5 downto 0) => mix_logic0_bus_1, -- __W_PORT
cp_lcmd_p(6) => cp_lcmd_3(6), -- Signal name != port name
cpu_bist_fail => tmi_sbist_fail(1),
cvi_sbist_fail0 => tmi_sbist_fail(10),
cvi_sbist_fail1 => tmi_sbist_fail(11),
ema_bist_fail => tmi_sbist_fail(7),
ga_sbist_fail0 => tmi_sbist_fail(8),
ga_sbist_fail1 => tmi_sbist_fail(9),
ifu_bist_fail => tmi_sbist_fail(6),
mcu_bist_fail => tmi_sbist_fail(2),
pdu_bist_fail0 => tmi_sbist_fail(3),
pdu_bist_fail1 => tmi_sbist_fail(4),
tsd_bist_fail => tmi_sbist_fail(5),
video_p_2 => video_i(2)
);
-- End of Generated Instance Port Map for inst_eac
-- Generated Instance Port Map for inst_ead
inst_ead: inst_ead_e
port map (
video_p_3 => video_i(3)
);
-- End of Generated Instance Port Map for inst_ead
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
908b8597e39d9b35b993ffe681871e00
| 0.639197 | 2.45425 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/asymmetric_dp_bank_v6.vhd
| 1 | 35,840 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : asymmetric_dp_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
-- Assumption: Port A is always wider
entity asymmetric_dp_bank_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_PRINT_INFO : boolean := false;
C_BANK_AWIDTH_A : integer;
C_BANK_DWIDTH_A : integer;
C_BANK_AWIDTH_B : integer;
C_BANK_DWIDTH_B : integer);
port (
rst : in std_logic;
clk_a : in std_logic;
ce_a : in std_logic;
we_a : in std_logic;
addr_a : in std_logic_vector(C_BANK_AWIDTH_A-1 downto 0);
din_a : in std_logic_vector(C_BANK_DWIDTH_A-1 downto 0);
dout_a : out std_logic_vector(C_BANK_DWIDTH_A-1 downto 0);
clk_b : in std_logic;
ce_b : in std_logic;
we_b : in std_logic;
addr_b : in std_logic_vector(C_BANK_AWIDTH_B-1 downto 0);
din_b : in std_logic_vector(C_BANK_DWIDTH_B-1 downto 0);
dout_b : out std_logic_vector(C_BANK_DWIDTH_B-1 downto 0));
end asymmetric_dp_bank_v6;
architecture rtl of asymmetric_dp_bank_v6 is
constant MAX_BRAM_AWIDTH : integer := 15; -- 32Kx1
constant MIN_BRAM_AWIDTH : integer := 10; -- 1Kx32
constant MAX_BRAM_DWIDTH : integer := 32; -- 1Kx32
constant MIN_BRAM_DWIDTH : integer := 1; -- 32Kx1
constant DATA_RATIO : integer := C_BANK_DWIDTH_A/C_BANK_DWIDTH_B;
function calc_bram_dwidth(bank_awidth : natural; bank_dwidth : natural) return integer is
variable dwidth : integer;
begin
if(bank_awidth > MAX_BRAM_AWIDTH) then
-- If required address bitwidth is bigger than possible bitwidth, then we
-- have to increase depth. In this case, the BRAMs are configured x1.
dwidth := 1;
else
-- bitwidth for data bus is calculated using the following expression:
dwidth := 2**(MAX_BRAM_AWIDTH-bank_awidth);
-- assuming that we do not go above max possible bitwidth:
if(dwidth > MAX_BRAM_DWIDTH) then
dwidth := MAX_BRAM_DWIDTH;
end if;
-- But, if it goes above the width of the bank, we limit to such width
if(dwidth > bank_dwidth) then
dwidth := bank_dwidth;
end if;
if(dwidth*DATA_RATIO > MAX_BRAM_DWIDTH) then
dwidth := MAX_BRAM_DWIDTH/DATA_RATIO;
end if;
end if;
return dwidth;
end function calc_bram_dwidth;
-- Dimensioning of bank according to narrow port
constant BRAM_AWIDTH_B : integer := min_size(C_BANK_AWIDTH_B, MAX_BRAM_AWIDTH);
constant BRAM_DWIDTH_B : integer := calc_bram_dwidth(C_BANK_AWIDTH_B, C_BANK_DWIDTH_B);
constant N_BRAM : integer := div_round_up(C_BANK_DWIDTH_B, BRAM_DWIDTH_B);
constant BRAM_AWIDTH_A : integer := BRAM_AWIDTH_B-log2(DATA_RATIO);
constant BRAM_DWIDTH_A : integer := BRAM_DWIDTH_B*DATA_RATIO;
constant COL_SIZE : integer := 2**(C_BANK_AWIDTH_B-BRAM_AWIDTH_B);
begin
NO_DEPTH_EXPANSION_GEN : if (C_BANK_AWIDTH_B <= MAX_BRAM_AWIDTH) generate
signal bram_addr_a : std_logic_vector(15 downto 0);
signal bram_addr_b : std_logic_vector(15 downto 0);
begin
process(addr_a)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_A);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_A-1;
begin
bram_addr_a <= (others => '0');
bram_addr_a(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_a;
end process;
process(addr_b)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_B);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_B-1;
begin
bram_addr_b <= (others => '0');
bram_addr_b(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_b;
end process;
MEM_BANK_GEN : for i in 0 to N_BRAM-1 generate
signal bram_din_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_a : std_logic_vector(3 downto 0);
signal bram_din_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_b : std_logic_vector(7 downto 0);
begin
-- In the input dus (wide), BRAM i gives support to slice i of each of
-- the DATA_RATIO subwords.
process(din_a)
begin
bram_din_a <= (others => '1');
for k in 0 to DATA_RATIO-1 loop
-- from each subwordk, we take slice i
bram_din_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k) <=
din_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k);
end loop;
end process;
DOUT_A_GEN : for k in 0 to DATA_RATIO-1 generate
begin
dout_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k) <=
bram_dout_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k);
end generate DOUT_A_GEN;
-- narrow port (B), we group the slices:
process(din_b)
begin
bram_din_b <= (others => '0');
bram_din_b(BRAM_DWIDTH_B-1 downto 0) <= din_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i);
end process;
dout_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i) <= bram_dout_b(BRAM_DWIDTH_B-1 downto 0);
-- No support for byte-enable we signals
bram_we_a <= (others => we_a);
bram_we_b <= (others => we_b);
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP", -- "SDP" or "TDP"
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din_a, -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout_a, -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_addr_a, -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a, -- 1-bit input A port clock/Read clock input
ENARDEN => ce_a, -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => bram_we_a, -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din_b, -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout_b, -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_addr_b, -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b, -- 1-bit input B port clock/Write clock input
ENBWREN => ce_b, -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
--WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
WEBWE => bram_we_b); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
SIM_COLLISION_CHECK => "ALL",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72,
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST"
)
PORT MAP (
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DBITERR => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
DINADIN => bram_din_a, -- 32-bit input A port data/LSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DOUTADOUT => bram_dout_a, -- 32-bit output A port data/LSB data output
DOUTPADOUTP => open,
ADDRARDADDR => bram_addr_a(14 downto 0), -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a,
ENARDEN => ce_a, -- 1-bit input A port enable/Read enable input
ADDRENA => '0',
REGCEAREGCE => '1',
RSTRAMARSTRAM => rst,
RSTREGARSTREG => '0',
WEA => bram_we_a, -- 4-bit input A port write enable input
DINBDIN => bram_din_b, -- 32-bit input B port data/MSB data input
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
DOUTBDOUT => bram_dout_b, -- 32-bit output B port data/MSB data output
DOUTPBDOUTP => open,
ADDRBWRADDR => bram_addr_b(14 downto 0), -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b,
ENBWREN => ce_b, -- 1-bit input B port enable/Write enable input
ADDRENB => '0',
ECCPIPECE => '0',
REGCEB => '1',
RSTRAMB => rst,
RSTREGB => '0',
SLEEP => '0',
WEBWE => bram_we_b -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate MEM_BANK_GEN;
end generate NO_DEPTH_EXPANSION_GEN;
DEPTH_EXPANSION_GEN : if (C_BANK_AWIDTH_B > MAX_BRAM_AWIDTH) generate
signal bram_addr_a : std_logic_vector(15 downto 0);
signal bram_addr_b : std_logic_vector(15 downto 0);
constant WORD_AWIDTH : integer := log2(COL_SIZE);
constant BRAM_SEL_A_MSB : integer := C_BANK_AWIDTH_A-1;
constant BRAM_SEL_A_LSB : integer := BRAM_SEL_A_MSB-(WORD_AWIDTH-1);
constant BRAM_SEL_B_MSB : integer := C_BANK_AWIDTH_B-1;
constant BRAM_SEL_B_LSB : integer := BRAM_SEL_B_MSB-(WORD_AWIDTH-1);
signal bram_ce_a : std_logic_vector(COL_SIZE-1 downto 0);
signal bram_ce_b : std_logic_vector(COL_SIZE-1 downto 0);
signal bram_sel_addr_a : std_logic_vector(WORD_AWIDTH-1 downto 0);
signal bram_sel_addr_b : std_logic_vector(WORD_AWIDTH-1 downto 0);
begin
-- Use the WORD_AWIDTH MS bits to select the BRAM inside the column
process(addr_a, ce_a)
begin
bram_ce_a <= (others => '0');
if (ce_a = '1') then
for i in 0 to COL_SIZE-1 loop
if (unsigned(addr_a(BRAM_SEL_A_MSB downto BRAM_SEL_A_LSB)) = i) then
bram_ce_a(i) <= '1';
end if;
end loop;
end if;
end process;
process(addr_b, ce_b)
begin
bram_ce_b <= (others => '0');
if (ce_b = '1') then
for i in 0 to COL_SIZE-1 loop
if (unsigned(addr_b(BRAM_SEL_B_MSB downto BRAM_SEL_B_LSB)) = i) then
bram_ce_b(i) <= '1';
end if;
end loop;
end if;
end process;
-- this section of bits has to be registered to generate the selection
-- signal for the mux's of output datapath
process(clk_a)
begin
if (clk_a'event and clk_a = '1') then
if (ce_a = '1') then
bram_sel_addr_a <= addr_a(BRAM_SEL_A_MSB downto BRAM_SEL_A_LSB);
end if;
end if;
end process;
process(clk_b)
begin
if (clk_b'event and clk_b = '1') then
if (ce_b = '1') then
bram_sel_addr_b <= addr_b(BRAM_SEL_B_MSB downto BRAM_SEL_B_LSB);
end if;
end if;
end process;
-- In this case, given that it is depth increase we use all width of BRAM
-- address bus of wide port
process(addr_b)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_B);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_B-1;
constant ADDR_LSB : integer := 0;
constant ADDR_MSB : integer := MAX_BRAM_AWIDTH-1;
begin
bram_addr_b <= (others => '0');
bram_addr_b(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_b(ADDR_MSB downto ADDR_LSB);
end process;
-- and, in the narrow port, it's the same but reducing the width log2(DATA_RATIO):
process(addr_a)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_A);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_A-1;
-- same as wide port minus log2(DATA_RATIO):
constant ADDR_LSB : integer := 0;
constant ADDR_MSB : integer := (MAX_BRAM_AWIDTH-log2(DATA_RATIO))-1;
begin
bram_addr_a <= (others => '0');
bram_addr_a(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_a(ADDR_MSB downto ADDR_LSB);
end process;
MEM_BANK_GEN : for i in 0 to N_BRAM-1 generate
signal bram_din_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_a : std_logic_vector(3 downto 0);
signal bram_din_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_b : std_logic_vector(7 downto 0);
-- These superbusses represent group data busses at the output of BRAMs
-- in same column
signal col_dout_a : std_logic_vector(COL_SIZE*BRAM_DWIDTH_A-1 downto 0);
signal col_dout_b : std_logic_vector(COL_SIZE*BRAM_DWIDTH_B-1 downto 0);
-- this is for the output mux
signal mux_dout_a : std_logic_vector(BRAM_DWIDTH_A-1 downto 0);
signal mux_dout_b : std_logic_vector(BRAM_DWIDTH_B-1 downto 0);
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
begin
-- In the input port of wide bus, BRAM i gives support to slide i of each
-- of DATA_RATIO subwords
process(din_a)
begin
bram_din_a <= (others => '1');
for k in 0 to DATA_RATIO-1 loop
-- from each subword k, we take slice i
bram_din_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k) <=
din_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k);
end loop;
end process;
-- in the narrow port(B), we group the slices:
process(din_b)
begin
bram_din_b <= (others => '0');
bram_din_b(BRAM_DWIDTH_B-1 downto 0) <= din_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i);
end process;
-- mux's in the output data busses in the same column
process(col_dout_a, bram_sel_addr_a)
begin
mux_dout_a <= (others => '0');
for k in 0 to COL_SIZE-1 loop
if (unsigned(bram_sel_addr_a) = k) then
mux_dout_a <= col_dout_a(BRAM_DWIDTH_A*(k+1)-1 downto BRAM_DWIDTH_A*k);
end if;
end loop;
end process;
process(col_dout_b, bram_sel_addr_b)
begin
mux_dout_b <= (others => '0');
for k in 0 to COL_SIZE-1 loop
if (unsigned(bram_sel_addr_b) = k) then
mux_dout_b <= col_dout_b(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k);
end if;
end loop;
end process;
-- For the output datapath, we apply the same criterio that in the input
-- datapath
-- For the wide port, we apply interleave with the output of the mux
DOUT_A_GEN : for k in 0 to DATA_RATIO-1 generate
begin
dout_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k) <=
mux_dout_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k);
end generate DOUT_A_GEN;
-- for the narrow port, we directly take the slice
dout_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i) <= mux_dout_b(BRAM_DWIDTH_B-1 downto 0);
-- No byte-enable for we signals
bram_we_a <= (others => we_a);
bram_we_b <= (others => we_b);
BRAM_COL_GEN : for k in 0 to COL_SIZE-1 generate
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
begin
-- This superbus groups the output datapaths
col_dout_a(BRAM_DWIDTH_A*(k+1)-1 downto BRAM_DWIDTH_A*k) <= bram_dout_a(BRAM_DWIDTH_A-1 downto 0);
col_dout_b(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k) <= bram_dout_b(BRAM_DWIDTH_B-1 downto 0);
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP", -- "SDP" or "TDP"
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din_a, -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout_a, -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_addr_a, -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a, -- 1-bit input A port clock/Read clock input
ENARDEN => bram_ce_a(k), -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => bram_we_a, -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din_b, -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout_b, -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_addr_b, -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b, -- 1-bit input B port clock/Write clock input
ENBWREN => bram_ce_b(k), -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
--WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
WEBWE => bram_we_b); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
SIM_COLLISION_CHECK => "ALL",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72,
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST"
)
PORT MAP (
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DBITERR => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
DINADIN => bram_din_a, -- 32-bit input A port data/LSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DOUTADOUT => bram_dout_a, -- 32-bit output A port data/LSB data output
DOUTPADOUTP => open,
ADDRARDADDR => bram_addr_a(14 downto 0), -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a,
ENARDEN => bram_ce_a(k), -- 1-bit input A port enable/Read enable input
ADDRENA => '0',
REGCEAREGCE => '1',
RSTRAMARSTRAM => rst,
RSTREGARSTREG => '0',
WEA => bram_we_a, -- 4-bit input A port write enable input
DINBDIN => bram_din_b, -- 32-bit input B port data/MSB data input
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
DOUTBDOUT => bram_dout_b, -- 32-bit output B port data/MSB data output
DOUTPBDOUTP => open,
ADDRBWRADDR => bram_addr_b(14 downto 0), -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b,
ENBWREN => bram_ce_b(k), -- 1-bit input B port enable/Write enable input
ADDRENB => '0',
ECCPIPECE => '0',
REGCEB => '1',
RSTRAMB => rst,
RSTREGB => '0',
SLEEP => '0',
WEBWE => bram_we_b -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate BRAM_COL_GEN;
end generate MEM_BANK_GEN;
end generate DEPTH_EXPANSION_GEN;
end rtl;
|
mit
|
e4f56ef6af94ac62d29ac0c4674dfda1
| 0.525781 | 3.787382 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/ddrv4-rtl-a.vhd
| 1 | 5,580 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ddrv4
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-a.vhd,v 1.1 2004/04/06 10:44:19 wig Exp $
-- $Date: 2004/04/06 10:44:19 $
-- $Log: ddrv4-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:44:19 wig
-- Adding result/padio
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ddrv --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_time : in std_ulogic_vector(3 downto 0);
current_time : in std_ulogic_vector(3 downto 0);
display : out std_ulogic_vector(6 downto 0);
key_buffer : in std_ulogic_vector(3 downto 0);
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f --
-- No Generated Generics
port (
-- Generated Port for Entity and_f
out_p : out std_ulogic;
y : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_display_ls_hr_go <= display_ls_hr; -- __I_O_BUS_PORT
p_mix_display_ls_min_go <= display_ls_min; -- __I_O_BUS_PORT
p_mix_display_ms_hr_go <= display_ms_hr; -- __I_O_BUS_PORT
p_mix_display_ms_min_go <= display_ms_min; -- __I_O_BUS_PORT
p_mix_sound_alarm_go <= sound_alarm; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
out_p => sound_alarm,
y => alarm -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3e620856202de3caa15d4b35d7e12be0
| 0.640143 | 3.105175 | false | false | false | false |
blutsvente/MIX
|
test/results/padio2/pads_westsouth-struct-a.vhd
| 1 | 35,568 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_westsouth
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_westsouth-struct-a.vhd,v 1.6 2007/03/05 15:29:26 wig Exp $
-- $Date: 2007/03/05 15:29:26 $
-- $Log: pads_westsouth-struct-a.vhd,v $
-- Revision 1.6 2007/03/05 15:29:26 wig
-- Updated testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pads_westsouth
--
architecture struct of pads_westsouth is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc
-- No Generated Generics
port (
-- Generated Port for Entity ioc
bypass : in std_ulogic_vector(1 downto 0);
clk : in std_ulogic_vector(1 downto 0);
clockdr_i : in std_ulogic;
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(1 downto 0);
en : in std_ulogic_vector(1 downto 0);
enq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
iddq : in std_ulogic_vector(1 downto 0);
mode_1_i : in std_ulogic;
mode_2_i : in std_ulogic;
mode_3_i : in std_ulogic;
mux_sel_p : in std_ulogic_vector(1 downto 0);
oe : in std_ulogic_vector(1 downto 0);
pad : inout std_ulogic;
pd : in std_ulogic_vector(1 downto 0);
res_n : in std_ulogic;
scan_en_i : in std_ulogic;
scan_i : in std_ulogic;
scan_o : out std_ulogic;
serial_input_i : in std_ulogic;
serial_output_o : out std_ulogic;
shiftdr_i : in std_ulogic;
tck_i : in std_ulogic;
tenq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
updatedr_i : in std_ulogic
-- End of Generated Port for Entity ioc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_18 : std_ulogic;
signal mix_logic1_19 : std_ulogic;
signal mix_logic1_20 : std_ulogic;
signal mix_logic1_21 : std_ulogic;
signal mix_logic1_22 : std_ulogic;
signal mix_logic1_23 : std_ulogic;
signal mix_logic1_24 : std_ulogic;
signal mix_logic1_25 : std_ulogic;
signal mix_logic1_26 : std_ulogic;
signal mix_logic1_27 : std_ulogic;
signal mix_logic1_28 : std_ulogic;
signal mix_logic1_29 : std_ulogic;
signal mix_logic1_30 : std_ulogic;
signal mix_logic1_31 : std_ulogic;
signal mix_logic1_32 : std_ulogic;
signal mix_logic1_33 : std_ulogic;
signal mix_logic1_34 : std_ulogic;
signal mix_logic1_35 : std_ulogic;
signal mix_logic1_36 : std_ulogic;
signal mix_logic1_37 : std_ulogic;
signal mix_logic1_38 : std_ulogic;
signal mix_logic1_39 : std_ulogic;
signal mix_logic1_40 : std_ulogic;
signal mix_logic1_41 : std_ulogic;
signal mix_logic1_42 : std_ulogic;
signal mix_logic1_43 : std_ulogic;
signal mix_logic1_44 : std_ulogic;
signal mix_logic1_45 : std_ulogic;
signal mix_logic1_46 : std_ulogic;
signal mix_logic1_47 : std_ulogic;
signal mix_logic1_66 : std_ulogic;
signal mix_logic1_67 : std_ulogic;
signal mix_logic1_68 : std_ulogic;
signal mix_logic1_69 : std_ulogic;
signal mix_logic1_70 : std_ulogic;
signal mix_logic1_71 : std_ulogic;
signal mix_logic1_72 : std_ulogic;
signal mix_logic1_73 : std_ulogic;
signal mix_logic1_74 : std_ulogic;
signal mix_logic1_75 : std_ulogic;
signal mix_logic1_76 : std_ulogic;
signal mix_logic1_77 : std_ulogic;
signal mix_logic1_78 : std_ulogic;
signal mix_logic1_79 : std_ulogic;
signal mix_logic1_80 : std_ulogic;
signal mix_logic1_81 : std_ulogic;
signal mix_logic1_82 : std_ulogic;
signal mix_logic1_83 : std_ulogic;
signal mix_logic1_84 : std_ulogic;
signal mix_logic1_85 : std_ulogic;
signal mix_logic1_86 : std_ulogic;
signal mix_logic1_87 : std_ulogic;
signal mix_logic1_88 : std_ulogic;
signal mix_logic1_89 : std_ulogic;
signal mix_logic1_90 : std_ulogic;
signal mix_logic1_91 : std_ulogic;
signal mix_logic1_92 : std_ulogic;
signal mix_logic1_93 : std_ulogic;
signal mix_logic1_94 : std_ulogic;
signal mix_logic1_95 : std_ulogic;
signal mix_logic0_10 : std_ulogic;
signal mix_logic0_11 : std_ulogic;
signal mix_logic0_12 : std_ulogic;
signal mix_logic0_13 : std_ulogic;
signal mix_logic0_14 : std_ulogic;
signal mix_logic0_15 : std_ulogic;
signal mix_logic0_22 : std_ulogic;
signal mix_logic0_23 : std_ulogic;
signal mix_logic0_24 : std_ulogic;
signal mix_logic0_25 : std_ulogic;
signal mix_logic0_26 : std_ulogic;
signal mix_logic0_27 : std_ulogic;
signal mix_logic0_28 : std_ulogic;
signal mix_logic0_29 : std_ulogic;
signal mix_logic0_30 : std_ulogic;
signal mix_logic0_31 : std_ulogic;
signal mix_logic0_33 : std_ulogic;
signal mix_logic0_36 : std_ulogic;
signal mix_logic0_38 : std_ulogic;
signal mix_logic0_40 : std_ulogic;
signal mix_logic0_42 : std_ulogic;
signal mix_logic0_44 : std_ulogic;
signal mix_logic0_46 : std_ulogic;
signal mix_logic0_47 : std_ulogic;
signal mix_logic0_48 : std_ulogic;
signal mix_logic0_49 : std_ulogic;
signal mix_logic0_51 : std_ulogic;
signal mix_logic0_52 : std_ulogic;
signal mix_logic0_54 : std_ulogic;
signal mix_logic0_57 : std_ulogic;
signal mix_logic0_58 : std_ulogic;
signal mix_logic0_59 : std_ulogic;
signal mix_logic0_6 : std_ulogic;
signal mix_logic0_60 : std_ulogic;
signal mix_logic0_62 : std_ulogic;
signal mix_logic0_64 : std_ulogic;
signal mix_logic0_65 : std_ulogic;
signal mix_logic0_7 : std_ulogic;
signal mix_logic0_8 : std_ulogic;
signal mix_logic0_9 : std_ulogic;
signal clkf81 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal clockdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal dbo_o : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal default : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_1_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_2_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_3_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pmux_sel_por : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal res_f81_n : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_byp_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_iddq_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_sio_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_in_db2o_0 : std_ulogic;
signal s_in_db2o_1 : std_ulogic;
signal s_in_db2o_2 : std_ulogic;
signal s_in_db2o_3 : std_ulogic;
signal s_in_db2o_4 : std_ulogic;
signal s_in_db2o_5 : std_ulogic;
signal s_in_db2o_6 : std_ulogic;
signal s_in_db2o_7 : std_ulogic;
signal s_in_db2o_8 : std_ulogic;
signal s_in_db2o_9 : std_ulogic;
signal s_in_dbo_0 : std_ulogic;
signal s_in_dbo_1 : std_ulogic;
signal s_in_dbo_2 : std_ulogic;
signal s_in_dbo_3 : std_ulogic;
signal s_in_dbo_4 : std_ulogic;
signal s_in_dbo_5 : std_ulogic;
signal s_in_dbo_6 : std_ulogic;
signal s_in_dbo_7 : std_ulogic;
signal s_in_dbo_8 : std_ulogic;
signal s_in_dbo_9 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_0 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_1 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_2 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_3 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_4 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_5 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_6 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_7 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_8 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_9 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_0 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_1 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_2 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_3 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_4 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_5 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_6 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_7 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_8 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_9 : std_ulogic;
signal scan_en_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal shiftdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tck_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal updatedr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal varclk_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_18 <= '1';
mix_logic1_19 <= '1';
mix_logic1_20 <= '1';
mix_logic1_21 <= '1';
mix_logic1_22 <= '1';
mix_logic1_23 <= '1';
mix_logic1_24 <= '1';
mix_logic1_25 <= '1';
mix_logic1_26 <= '1';
mix_logic1_27 <= '1';
mix_logic1_28 <= '1';
mix_logic1_29 <= '1';
mix_logic1_30 <= '1';
mix_logic1_31 <= '1';
mix_logic1_32 <= '1';
mix_logic1_33 <= '1';
mix_logic1_34 <= '1';
mix_logic1_35 <= '1';
mix_logic1_36 <= '1';
mix_logic1_37 <= '1';
mix_logic1_38 <= '1';
mix_logic1_39 <= '1';
mix_logic1_40 <= '1';
mix_logic1_41 <= '1';
mix_logic1_42 <= '1';
mix_logic1_43 <= '1';
mix_logic1_44 <= '1';
mix_logic1_45 <= '1';
mix_logic1_46 <= '1';
mix_logic1_47 <= '1';
mix_logic1_66 <= '1';
mix_logic1_67 <= '1';
mix_logic1_68 <= '1';
mix_logic1_69 <= '1';
mix_logic1_70 <= '1';
mix_logic1_71 <= '1';
mix_logic1_72 <= '1';
mix_logic1_73 <= '1';
mix_logic1_74 <= '1';
mix_logic1_75 <= '1';
mix_logic1_76 <= '1';
mix_logic1_77 <= '1';
mix_logic1_78 <= '1';
mix_logic1_79 <= '1';
mix_logic1_80 <= '1';
mix_logic1_81 <= '1';
mix_logic1_82 <= '1';
mix_logic1_83 <= '1';
mix_logic1_84 <= '1';
mix_logic1_85 <= '1';
mix_logic1_86 <= '1';
mix_logic1_87 <= '1';
mix_logic1_88 <= '1';
mix_logic1_89 <= '1';
mix_logic1_90 <= '1';
mix_logic1_91 <= '1';
mix_logic1_92 <= '1';
mix_logic1_93 <= '1';
mix_logic1_94 <= '1';
mix_logic1_95 <= '1';
mix_logic0_10 <= '0';
mix_logic0_11 <= '0';
mix_logic0_12 <= '0';
mix_logic0_13 <= '0';
mix_logic0_14 <= '0';
mix_logic0_15 <= '0';
mix_logic0_22 <= '0';
mix_logic0_23 <= '0';
mix_logic0_24 <= '0';
mix_logic0_25 <= '0';
mix_logic0_26 <= '0';
mix_logic0_27 <= '0';
mix_logic0_28 <= '0';
mix_logic0_29 <= '0';
mix_logic0_30 <= '0';
mix_logic0_31 <= '0';
mix_logic0_33 <= '0';
mix_logic0_36 <= '0';
mix_logic0_38 <= '0';
mix_logic0_40 <= '0';
mix_logic0_42 <= '0';
mix_logic0_44 <= '0';
mix_logic0_46 <= '0';
mix_logic0_47 <= '0';
mix_logic0_48 <= '0';
mix_logic0_49 <= '0';
mix_logic0_51 <= '0';
mix_logic0_52 <= '0';
mix_logic0_54 <= '0';
mix_logic0_57 <= '0';
mix_logic0_58 <= '0';
mix_logic0_59 <= '0';
mix_logic0_6 <= '0';
mix_logic0_60 <= '0';
mix_logic0_62 <= '0';
mix_logic0_64 <= '0';
mix_logic0_65 <= '0';
mix_logic0_7 <= '0';
mix_logic0_8 <= '0';
mix_logic0_9 <= '0';
clkf81 <= clkf81_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
clockdr_i <= clockdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
dbo_o_9_0_go(9 downto 0) <= dbo_o(9 downto 0); -- __I_O_SLICE_PORT
default <= default_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_1_i <= mode_1_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_2_i <= mode_2_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_3_i <= mode_3_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
pmux_sel_por <= pmux_sel_por_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
res_f81_n <= res_f81_n_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_byp_i <= rgbout_byp_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_iddq_i <= rgbout_iddq_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_sio_i <= rgbout_sio_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
scan_en_i <= scan_en_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
shiftdr_i <= shiftdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
tck_i <= tck_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
updatedr_i <= updatedr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
varclk_i <= varclk_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_db2o_0
ioc_db2o_0: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_68, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(0), -- padout (X2)
do(0) => db2o_i(0), -- padin (X2)
do(1) => mix_logic1_66, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_22, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_67, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_0, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_36,
scan_o => open,
serial_input_i => s_in_db2o_0,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_0
-- Generated Instance Port Map for ioc_db2o_1
ioc_db2o_1: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_71, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(1), -- padout (X2)
do(0) => db2o_i(1), -- padin (X2)
do(1) => mix_logic1_69, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_23, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_70, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_1, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_62,
scan_o => open,
serial_input_i => s_in_db2o_1,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_1
-- Generated Instance Port Map for ioc_db2o_2
ioc_db2o_2: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_74, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(2), -- padout (X2)
do(0) => db2o_i(2), -- padin (X2)
do(1) => mix_logic1_72, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_24, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_73, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_2, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_47,
scan_o => open,
serial_input_i => s_in_db2o_2,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_2
-- Generated Instance Port Map for ioc_db2o_3
ioc_db2o_3: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_77, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(3), -- padout (X2)
do(0) => db2o_i(3), -- padin (X2)
do(1) => mix_logic1_75, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_25, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_76, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_3, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_42,
scan_o => open,
serial_input_i => s_in_db2o_3,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_3
-- Generated Instance Port Map for ioc_db2o_4
ioc_db2o_4: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_80, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(4), -- padout (X2)
do(0) => db2o_i(4), -- padin (X2)
do(1) => mix_logic1_78, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_26, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_79, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_4, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_51,
scan_o => open,
serial_input_i => s_in_db2o_4,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_4
-- Generated Instance Port Map for ioc_db2o_5
ioc_db2o_5: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_83, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(5), -- padout (X2)
do(0) => db2o_i(5), -- padin (X2)
do(1) => mix_logic1_81, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_27, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_82, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_5, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_65,
scan_o => open,
serial_input_i => s_in_db2o_5,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_5
-- Generated Instance Port Map for ioc_db2o_6
ioc_db2o_6: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_86, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(6), -- padout (X2)
do(0) => db2o_i(6), -- padin (X2)
do(1) => mix_logic1_84, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_28, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_85, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_6, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_52,
scan_o => open,
serial_input_i => s_in_db2o_6,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_6
-- Generated Instance Port Map for ioc_db2o_7
ioc_db2o_7: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_89, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(7), -- padout (X2)
do(0) => db2o_i(7), -- padin (X2)
do(1) => mix_logic1_87, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_29, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_88, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_7, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_49,
scan_o => open,
serial_input_i => s_in_db2o_7,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_7
-- Generated Instance Port Map for ioc_db2o_8
ioc_db2o_8: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_92, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(8), -- padout (X2)
do(0) => db2o_i(8), -- padin (X2)
do(1) => mix_logic1_90, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_30, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_91, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_8, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_58,
scan_o => open,
serial_input_i => s_in_db2o_8,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_8
-- Generated Instance Port Map for ioc_db2o_9
ioc_db2o_9: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_95, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(9), -- padout (X2)
do(0) => db2o_i(9), -- padin (X2)
do(1) => mix_logic1_93, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_31, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_94, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_9, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_59,
scan_o => open,
serial_input_i => s_in_db2o_9,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_9
-- Generated Instance Port Map for ioc_dbo_0
ioc_dbo_0: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_20, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(0), -- padout
do(0) => dbo_i(0), -- padin (X2)
do(1) => mix_logic1_18, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_6, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_19, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_0, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_54,
scan_o => open,
serial_input_i => s_in_dbo_0,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_0
-- Generated Instance Port Map for ioc_dbo_1
ioc_dbo_1: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_23, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(1), -- padout
do(0) => dbo_i(1), -- padin (X2)
do(1) => mix_logic1_21, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_7, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_22, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_1, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_60,
scan_o => open,
serial_input_i => s_in_dbo_1,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_1
-- Generated Instance Port Map for ioc_dbo_2
ioc_dbo_2: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_26, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(2), -- padout
do(0) => dbo_i(2), -- padin (X2)
do(1) => mix_logic1_24, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_8, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_25, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_2, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_33,
scan_o => open,
serial_input_i => s_in_dbo_2,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_2
-- Generated Instance Port Map for ioc_dbo_3
ioc_dbo_3: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_29, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(3), -- padout
do(0) => dbo_i(3), -- padin (X2)
do(1) => mix_logic1_27, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_9, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_28, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_3, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_44,
scan_o => open,
serial_input_i => s_in_dbo_3,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_3
-- Generated Instance Port Map for ioc_dbo_4
ioc_dbo_4: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_32, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(4), -- padout
do(0) => dbo_i(4), -- padin (X2)
do(1) => mix_logic1_30, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_10, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_31, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_4, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_57,
scan_o => open,
serial_input_i => s_in_dbo_4,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_4
-- Generated Instance Port Map for ioc_dbo_5
ioc_dbo_5: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_35, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(5), -- padout
do(0) => dbo_i(5), -- padin (X2)
do(1) => mix_logic1_33, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_11, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_34, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_5, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_40,
scan_o => open,
serial_input_i => s_in_dbo_5,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_5
-- Generated Instance Port Map for ioc_dbo_6
ioc_dbo_6: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_38, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(6), -- padout
do(0) => dbo_i(6), -- padin (X2)
do(1) => mix_logic1_36, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_12, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_37, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_6, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_46,
scan_o => open,
serial_input_i => s_in_dbo_6,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_6
-- Generated Instance Port Map for ioc_dbo_7
ioc_dbo_7: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_41, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(7), -- padout
do(0) => dbo_i(7), -- padin (X2)
do(1) => mix_logic1_39, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_13, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_40, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_7, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_64,
scan_o => open,
serial_input_i => s_in_dbo_7,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_7
-- Generated Instance Port Map for ioc_dbo_8
ioc_dbo_8: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_44, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(8), -- padout
do(0) => dbo_i(8), -- padin (X2)
do(1) => mix_logic1_42, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_14, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_43, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_8, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_48,
scan_o => open,
serial_input_i => s_in_dbo_8,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_8
-- Generated Instance Port Map for ioc_dbo_9
ioc_dbo_9: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_47, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(9), -- padout
do(0) => dbo_i(9), -- padin (X2)
do(1) => mix_logic1_45, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_15, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_46, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_9, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_38,
scan_o => open,
serial_input_i => s_in_dbo_9,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_9
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
59b3e7f03200cc95248c4d8972dfed05
| 0.573971 | 2.234452 | false | false | false | false |
mitchsm/nvc
|
test/regress/real2.vhd
| 5 | 488 |
entity real2 is
end entity;
architecture test of real2 is
type real_vec is array (integer range <>) of real;
type real_rec is record
x, y : real;
end record;
begin
process is
variable a, b : real_vec(1 to 3);
variable r : real_rec;
begin
a := (1.0, 1.2, 3.4);
b := (0.9, 0.2, 4.1);
assert b < a;
r.x := 2.0;
r.y := 3.0;
assert r = (2.0, 3.0);
wait;
end process;
end architecture;
|
gpl-3.0
|
19ebe78bb2ee43fb3961d12c36914b85
| 0.497951 | 3.069182 | false | false | false | false |
mitchsm/nvc
|
test/regress/record1.vhd
| 5 | 744 |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
constant k : r1 := (62, 75);
begin
process is
variable a : r1;
variable b : r1 := (1, 2);
variable c : r1 := (x => 10, y => 2);
variable d : r1 := (others => 99);
begin
assert a.x = integer'left;
assert (b.x = 1) and (b.y = 2);
assert (c.x / c.y) = 5;
assert (d.x = 99) and (d.y = 99);
a.x := 5;
assert a.x = 5;
a := b;
assert (a.x = 1) and (a.y = 2);
a := k;
assert (a.x = k.x) and (a.y = k.y);
assert a = k;
assert a /= b;
wait;
end process;
end architecture;
|
gpl-3.0
|
7d8e4978a8840c339b5c42faffc373ba
| 0.444892 | 3.02439 | false | false | false | false |
mitchsm/nvc
|
test/regress/concat2.vhd
| 5 | 787 |
entity concat2 is
end entity;
architecture test of concat2 is
type int_array is array (integer range <>) of integer;
-- Dummy argument is to prevent constant folding;
function get_array(dummy : in integer) return int_array is
begin
return (1, 2, 3);
end function;
function pad(a : in int_array; dummy : in integer) return int_array is
begin
return (0, 0) & a;
end function;
begin
process is
variable x : int_array(0 to 3);
variable d : integer;
begin
x := get_array(d) & ( 0 => 4 );
assert x = (1, 2, 3, 4);
x := get_array(d) & ( 6 => 8 );
assert x = (1, 2, 3, 8);
x := pad((1, 2), d);
assert x = (0, 0, 1, 2);
wait;
end process;
end architecture;
|
gpl-3.0
|
dbc5a18733dd6bce3ed87c4a5e051677
| 0.542567 | 3.451754 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/ioblock3_e-rtl-a.vhd
| 1 | 10,726 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock3_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:52:30 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-rtl-a.vhd,v 1.4 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: ioblock3_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock3_e
--
architecture rtl of ioblock3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc_r_iou
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_iou
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
p_pu : out std_ulogic; -- pull-up control
pu : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ioc_r_iou
);
end component;
-- ---------
component ioc_g_i
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
p_di : in std_ulogic; -- data in from pad
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
component ioc_r_io3
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io3
do : in std_ulogic_vector(3 downto 0);
en : in std_ulogic_vector(3 downto 0);
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io3
);
end component;
-- ---------
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal ioseldi_0 : std_ulogic;
-- __I_NODRV_I signal ioseldi_1 : std_ulogic;
signal ioseldi_2 : std_ulogic;
signal ioseldi_3 : std_ulogic;
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_data_10
ioc_data_10: ioc_r_iou
port map (
di => d9_di(1), -- d9io
do => d9_do(1), -- d9io
en => d9_en(1), -- d9io
p_di => pad_di_32, -- data in from pad
p_do => pad_do_32, -- data out to pad
p_en => pad_en_32, -- pad output enable
p_pu => pad_pu_32, -- pull-up control
pu => d9_pu(1) -- d9io
);
-- End of Generated Instance Port Map for ioc_data_10
-- Generated Instance Port Map for ioc_data_9
ioc_data_9: ioc_r_iou
port map (
di => d9_di(0), -- d9io
do => d9_do(0), -- d9io
en => d9_en(0), -- d9io
p_di => pad_di_31, -- data in from pad
p_do => pad_do_31, -- data out to pad
p_en => pad_en_31, -- pad output enable
p_pu => pad_pu_31, -- pull-up control
pu => d9_pu(0) -- d9io
);
-- End of Generated Instance Port Map for ioc_data_9
-- Generated Instance Port Map for ioc_data_i33
ioc_data_i33: ioc_g_i
port map (
di => data_i33, -- io data
p_di => pad_di_33, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_data_i33
-- Generated Instance Port Map for ioc_data_i34
ioc_data_i34: ioc_g_i
port map (
di => data_i34, -- io data
p_di => pad_di_34, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_data_i34
-- Generated Instance Port Map for ioc_data_o35
ioc_data_o35: ioc_g_o
port map (
do => data_o35, -- io data
p_do => pad_do_35, -- data out to pad
p_en => pad_en_35, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_data_o35
-- Generated Instance Port Map for ioc_data_o36
ioc_data_o36: ioc_g_o
port map (
do => data_o36, -- io data
p_do => pad_do_36, -- data out to pad
p_en => pad_en_36, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_data_o36
-- Generated Instance Port Map for ioc_disp_10
ioc_disp_10: ioc_r_io3
port map (
do(0) => display_ls(1),
do(1) => display_ls(3),
do(2) => display_ls(5),
do(3) => display_ls(7),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_40, -- data in from pad
p_do => pad_do_40, -- data out to pad
p_en => pad_en_40, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
sel(1) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_disp_10
-- Generated Instance Port Map for ioc_disp_9
ioc_disp_9: ioc_r_io3
port map (
do(0) => display_ls(0),
do(1) => display_ls(2),
do(2) => display_ls(4),
do(3) => display_ls(6),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_39, -- data in from pad
p_do => pad_do_39, -- data out to pad
p_en => pad_en_39, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
-- __I_NODRV_I sel(1) => __nodrv__/ioseldi_1, -- __I_BIT_TO_BUSPORT
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_disp_9
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
36f0956e02374fea700463417a914e34
| 0.594537 | 2.393662 | false | false | false | false |
mitchsm/nvc
|
test/regress/range1.vhd
| 5 | 1,872 |
package index is
subtype myRange is natural range 7 downto 0;
constant my_range: bit_vector (myRange) := (others => '0');
function "+" (l: bit_vector; stride: natural) return bit_vector;
end package;
package body index is
function "+" (l: bit_vector;
stride: natural) return bit_vector is
variable retval: bit_vector(
l'LEFT + l'LENGTH * stride
downto
l'RIGHT + l'LENGTH * stride );
begin
-- report "stride = " & INTEGER'IMAGE(stride);
-- report "retval'LEFT = " & INTEGER'IMAGE(retval'LEFT);
-- report "retval'RIGHT = " & INTEGER'IMAGE(retval'RIGHT);
return retval;
end function;
end package body;
-------------------------------------------------------------------------------
use work.index.all;
entity range1 is
end entity;
architecture foo of range1 is
signal big_range: bit_vector (63 downto 0) := x"feedfacedeadbeef";
signal little_range: bit_vector (myRange);
function to_string(inp: bit_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: bit_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(bit'IMAGE(input_str(i)));
end loop;
-- report "image_str = " & image_str;
return image_str;
end;
begin
STIMULUS:
process
begin
wait for 1 ns;
for stride in myRange loop
report "stride = " & INTEGER'IMAGE(stride);
little_range <= big_range( "+"(my_range, stride)'RANGE );
wait for 1 ns;
end loop;
wait;
end process;
MONITOR:
process (little_range)
begin
report "little_range = " & to_string (little_range);
end process;
end architecture;
|
gpl-3.0
|
a7b3aefd40b74a8b280f3c9e3f77b1ba
| 0.558761 | 4 | false | false | false | false |
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