repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
mitchsm/nvc
|
test/sem/generics.vhd
| 4 | 2,489 |
entity bot is
generic ( N : integer );
port ( o : out integer );
end entity;
architecture a of bot is
begin
process is
begin
o <= N;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
signal x : integer;
begin
bot0: entity work.bot -- OK
generic map ( N => 5 )
port map ( o => x );
bot1: entity work.bot -- OK
generic map ( 5 )
port map ( o => x );
bot3: entity work.bot -- Missing N
port map ( o => x );
bot4: entity work.bot -- Too many generics
generic map ( 1, 2 )
port map ( o => x );
end architecture;
-------------------------------------------------------------------------------
entity bad is
generic (
X : integer;
Y : integer := X + 1 ); -- X not visible
port (
p : in integer := X );
end entity;
-------------------------------------------------------------------------------
entity class is
generic (
constant X : integer; -- OK
signal Y : integer ); -- Error
end entity;
-------------------------------------------------------------------------------
package p is
component c is
generic ( X : integer ); -- OK
port ( p : in integer range 1 to X; -- OK
q : in integer range 1 to Y ); -- Error
end component;
end package;
-------------------------------------------------------------------------------
entity static is
generic ( X : integer );
end entity;
architecture a of static is
constant k : integer := X + 1;
signal s : bit_vector(1 to 3);
alias sx : bit is s(X);
alias sx1 : bit is s(X + 1);
alias sx2 : bit_vector is s(k to 3);
function f(x : bit_vector) return integer;
component c is
generic (
x : bit_vector(2 downto 0) );
end component;
component d is
generic (
t : time );
end component;
begin
i1: entity work.bot
generic map (
N => f("100") )
port map (
o => open );
i2: component c
generic map ( x => "00" & '1' ); -- OK
i3: component c
generic map ( x => "00" & sx ); -- Error
i4: component d
generic map ( t => 100 ns ); -- OK
end architecture;
|
gpl-3.0
|
ed4e810fa8cd3983bdca6c7142397be2
| 0.414624 | 4.444643 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/PC_Register.vhd
| 2 | 1,347 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:15 11/22/2013
-- Design Name:
-- Module Name: PC_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC_Register is
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_OR_NOT : in STD_LOGIC := WRITE_PC_YES;
CLK : in STD_LOGIC);
end PC_Register;
architecture Behavioral of PC_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
-- update pc value at up edge
if (WRITE_OR_NOT = WRITE_PC_YES) then
PC_OUT <= PC_IN;
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
15c644017088844fee0984f884fd7882
| 0.585004 | 3.650407 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/sfl.vhd
| 1 | 3,130 |
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: sfl.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sfl IS
PORT
(
noe_in : IN STD_LOGIC
);
END sfl;
ARCHITECTURE SYN OF sfl IS
COMPONENT altserial_flash_loader
GENERIC (
enable_quad_spi_support : NATURAL;
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_quad_spi_support => 0,
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Cyclone III",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
8ec06edf903613c516236fe5942d9a7d
| 0.639936 | 3.9125 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue227.vhd
| 4 | 1,196 |
entity issue227 is
end entity issue227;
use std.textio.all;
architecture test of issue227 is
procedure proc(
delay : time := 0 ns;
a,b : integer := 1) is
begin
wait for delay;
write(OUTPUT, integer'image(a) & integer'image(b) & LF);
end procedure proc;
function func(a,b : integer := 1) return integer is
begin
return 10*a+b;
end function func;
begin
proc; -- all unassociated
proc(1 ns, 2, b => open); -- named OPEN
proc(2 ns, open, b => 2); -- positional OPEN
proc(3 ns, a => 2); -- one unassociated
process
begin
wait for 4 ns;
proc; -- all unassociated
proc(0 ns, 2, b => open); -- named OPEN
proc(0 ns, open, b => 2); -- positional OPEN
proc(0 ns, a => 2); -- one unassociated
write(OUTPUT, integer'image(func) & LF);
write(OUTPUT, integer'image(func(a => 2, b => open)) & LF);
write(OUTPUT, integer'image(func(open, b => 2)) & LF);
write(OUTPUT, integer'image(func(a => 2)) & LF);
wait;
end process;
end architecture test;
|
gpl-3.0
|
6b51b85a2a1c2e1825597435b8cba578
| 0.524247 | 3.7375 | false | false | false | false |
mitchsm/nvc
|
test/regress/array1.vhd
| 4 | 634 |
entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),
( 4, 5, 6 ),
( 7, 8, 9 ) );
begin
report integer'image(m(1, 3));
report integer'image(m(2, 2));
assert m(2, 2) = 5;
assert m(3, 1) = 7;
report integer'image(c(1, 0));
assert c(1, 0) = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
86c674b3ac2bbb4036b66e58436208c2
| 0.476341 | 3.234694 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/axis_accelerator_adapter.vhd
| 1 | 102,902 |
-------------------------------------------------------------------------------
-- axis_accelerator_adpater.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2013] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Title : AXI4-Stream Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : axis_accelerator_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This is the Accelerator Adapter top-level module. It is
-- implemented as a wrapper that uses buses for all input/output arguments.
-- This top-level module supports up-to eight input/output arguments.
-- Then, it instantiates the "xd_adapter_core", which is a completely
-- parametrizable module.
-------------------------------------------------------------------------------
-- Structure:
--
-- axis_accelerator_adapter.vhd
-- xd_adapter_pkg.vhd
-- axis_accelerator_adapter_core.vhd
-- |-- axi_lite_adapter
-- |-- cdc_sync.vhd
-- |-- xd_input_args_module.vhd
-- |-- xd_s2m_adapter.vhd
-- |-- xd_s2m_converter.vhd
-- |-- xd_s2m_memory_dc.vhd
-- |-- xd_iarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_output_args_module.vhd
-- |-- cdc_sync.vhd
-- |-- xd_m2s_adapter.vhd
-- |-- xd_m2s_converter.vhd
-- |-- xd_m2s_memory_dc.vhd
-- |-- arg_mem_bank.vhd
-- |-- asymmetric_dp_bank_v6.vhd
-- |-- symmetric_dp_bank_v6.vhd
-- |-- dp_bank_sdp_v6.vhd
-- |-- oarg_columnized_mem_bank.vhd
-- |-- srl_fifo_32_wt.vhd
-- |-- xd_oarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_sync_module.vhd
-- |-- cdc_sync.vhd
-- |-- sync_ap_status.vhd
-- |-- async_fifo_dist_wt.vhd
-- |-- xd_input_scalars_module.vhd
-- |-- xd_input_scalars_fifo.vhd
-- |-- xd_output_scalars_module.vhd
-- |-- xd_output_scalars_fifo.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "aclk","clk_div#", "clk_#x"
-- reset signals: "rst", "aresetn","rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- History:
-- ~~~~~~
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-01-31 1.0 pankajk removed perf mon ports, all ports in lower case
-- 2013-05-10 1.1 pankajk Seperated scalar port and brought those to top
-- entity
-- 2013-07-22 2.0 pankajk New scalar ports (*.vld, *.ack) and parameter
-- scalar_mode added to support accelerator IP
-- interface ap_none, ap_hs, ap_vld
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter_core;
entity axis_accelerator_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7"; -- Xilinx FPGA family
--
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
--
C_AP_ADAPTER_ID : integer range 0 to 15 :=1;
C_N_INPUT_ARGS : integer := 2;
C_N_OUTPUT_ARGS : integer := 1;
C_ENABLE_STREAM_CLK : integer := 0;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_S_AXIS_HAS_TSTRB : integer := 0;
C_S_AXIS_HAS_TKEEP : integer := 0;
--
C_S_AXIS_TDATA_WIDTH : integer := 64;
C_S_AXIS_TUSER_WIDTH : integer := 8;
C_S_AXIS_TID_WIDTH : integer := 4;
C_S_AXIS_TDEST_WIDTH : integer := 8;
--
C_AP_IARG_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_IARG_MB_DEPTH : std_logic_vector := X"0000000400000004000000040000000400000004000000040000000400000004";
C_AP_IARG_WIDTH : std_logic_vector := X"0000002000000020000000200000002000000020000000200000002000000020";
C_AP_IARG_N_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_DIM_1 : std_logic_vector := X"0000040000000400000004000000040000000400000004000000040000000400";
C_AP_IARG_DIM_2 : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_FORMAT_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_IARG_FORMAT_FACTOR : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_FORMAT_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
--
C_AP_IARG_0_DWIDTH : integer := 32;
C_AP_IARG_1_DWIDTH : integer := 32;
C_AP_IARG_2_DWIDTH : integer := 32;
C_AP_IARG_3_DWIDTH : integer := 32;
C_AP_IARG_4_DWIDTH : integer := 32;
C_AP_IARG_5_DWIDTH : integer := 32;
C_AP_IARG_6_DWIDTH : integer := 32;
C_AP_IARG_7_DWIDTH : integer := 32;
--
C_M_AXIS_TDATA_WIDTH : integer := 64;
C_M_AXIS_TUSER_WIDTH : integer := 8;
C_M_AXIS_TID_WIDTH : integer := 4;
C_M_AXIS_TDEST_WIDTH : integer := 8;
--
C_AP_OARG_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_OARG_MB_DEPTH : std_logic_vector := X"0000000400000004000000040000000400000004000000040000000400000004";
C_AP_OARG_WIDTH : std_logic_vector := X"0000002000000020000000200000002000000020000000200000002000000020";
C_AP_OARG_N_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_DIM : std_logic_vector := X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008";
C_AP_OARG_DIM_1 : std_logic_vector := X"0000040000000400000004000000040000000400000004000000080000000008";
C_AP_OARG_DIM_2 : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_FORMAT_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_OARG_FORMAT_FACTOR : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_FORMAT_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
--
C_AP_OARG_0_DWIDTH : integer := 32;
C_AP_OARG_1_DWIDTH : integer := 32;
C_AP_OARG_2_DWIDTH : integer := 32;
C_AP_OARG_3_DWIDTH : integer := 32;
C_AP_OARG_4_DWIDTH : integer := 32;
C_AP_OARG_5_DWIDTH : integer := 32;
C_AP_OARG_6_DWIDTH : integer := 32;
C_AP_OARG_7_DWIDTH : integer := 32;
--
C_INPUT_SCALAR_0_WIDTH : integer := 0;
C_INPUT_SCALAR_1_WIDTH : integer := 0;
C_INPUT_SCALAR_2_WIDTH : integer := 0;
C_INPUT_SCALAR_3_WIDTH : integer := 0;
C_INPUT_SCALAR_4_WIDTH : integer := 0;
C_INPUT_SCALAR_5_WIDTH : integer := 0;
C_INPUT_SCALAR_6_WIDTH : integer := 0;
C_INPUT_SCALAR_7_WIDTH : integer := 0;
C_INPUT_SCALAR_8_WIDTH : integer := 0;
C_INPUT_SCALAR_9_WIDTH : integer := 0;
C_INPUT_SCALAR_10_WIDTH : integer := 0;
C_INPUT_SCALAR_11_WIDTH : integer := 0;
C_INPUT_SCALAR_12_WIDTH : integer := 0;
C_INPUT_SCALAR_13_WIDTH : integer := 0;
C_INPUT_SCALAR_14_WIDTH : integer := 0;
C_INPUT_SCALAR_15_WIDTH : integer := 0;
C_OUTPUT_SCALAR_0_WIDTH : integer := 0;
C_OUTPUT_SCALAR_1_WIDTH : integer := 0;
C_OUTPUT_SCALAR_2_WIDTH : integer := 0;
C_OUTPUT_SCALAR_3_WIDTH : integer := 0;
C_OUTPUT_SCALAR_4_WIDTH : integer := 0;
C_OUTPUT_SCALAR_5_WIDTH : integer := 0;
C_OUTPUT_SCALAR_6_WIDTH : integer := 0;
C_OUTPUT_SCALAR_7_WIDTH : integer := 0;
C_OUTPUT_SCALAR_8_WIDTH : integer := 0;
C_OUTPUT_SCALAR_9_WIDTH : integer := 0;
C_OUTPUT_SCALAR_10_WIDTH : integer := 0;
C_OUTPUT_SCALAR_11_WIDTH : integer := 0;
C_OUTPUT_SCALAR_12_WIDTH : integer := 0;
C_OUTPUT_SCALAR_13_WIDTH : integer := 0;
C_OUTPUT_SCALAR_14_WIDTH : integer := 0;
C_OUTPUT_SCALAR_15_WIDTH : integer := 0;
C_N_INOUT_SCALARS : integer := 0;
C_N_INPUT_SCALARS : integer := 0;
C_INPUT_SCALAR_DWIDTH : std_logic_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020";
C_AP_ISCALAR_DOUT_WIDTH : integer := 32;
C_INPUT_SCALAR_MODE : std_logic_vector(63 downto 0) := X"0000000000000000";
--
C_N_OUTPUT_SCALARS : integer := 0;
C_OUTPUT_SCALAR_DWIDTH : std_logic_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020";
C_AP_OSCALAR_DIN_WIDTH : integer := 32;
C_AP_ISCALAR_IO_DOUT_WIDTH : integer := 32;
C_AP_OSCALAR_IO_DIN_WIDTH : integer := 32;
C_OUTPUT_SCALAR_MODE : std_logic_vector(63 downto 0) := X"0000000000000000";
C_NONE : integer := 2);
port (
-------------------------------
-- AXI4-Lite Slave Interface --
-------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
----------------------------------------------
-- AXI4-Stream slave interface clock reset
----------------------------------------------
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
----------------------------------------------
-- AXI4-Stream master interface clock reset
----------------------------------------------
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
----------------------------------------------
-- Accelerator clock --
----------------------------------------------
aclk : in std_logic;
-------------------------------
-- AXI4-Stream Slave Interface --
-------------------------------
s_axis_0_aclk : in std_logic;
s_axis_0_aresetn : in std_logic;
s_axis_0_tvalid : in std_logic;
s_axis_0_tready : out std_logic;
s_axis_0_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_0_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_0_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_0_tlast : in std_logic;
s_axis_0_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_0_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_0_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_1_aclk : in std_logic;
s_axis_1_aresetn : in std_logic;
s_axis_1_tvalid : in std_logic;
s_axis_1_tready : out std_logic;
s_axis_1_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_1_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_1_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_1_tlast : in std_logic;
s_axis_1_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_1_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_1_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_2_aclk : in std_logic;
s_axis_2_aresetn : in std_logic;
s_axis_2_tvalid : in std_logic;
s_axis_2_tready : out std_logic;
s_axis_2_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_2_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_2_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_2_tlast : in std_logic;
s_axis_2_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_2_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_2_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_3_aclk : in std_logic;
s_axis_3_aresetn : in std_logic;
s_axis_3_tvalid : in std_logic;
s_axis_3_tready : out std_logic;
s_axis_3_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_3_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_3_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_3_tlast : in std_logic;
s_axis_3_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_3_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_3_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_4_aclk : in std_logic;
s_axis_4_aresetn : in std_logic;
s_axis_4_tvalid : in std_logic;
s_axis_4_tready : out std_logic;
s_axis_4_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_4_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_4_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_4_tlast : in std_logic;
s_axis_4_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_4_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_4_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_5_aclk : in std_logic;
s_axis_5_aresetn : in std_logic;
s_axis_5_tvalid : in std_logic;
s_axis_5_tready : out std_logic;
s_axis_5_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_5_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_5_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_5_tlast : in std_logic;
s_axis_5_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_5_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_5_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_6_aclk : in std_logic;
s_axis_6_aresetn : in std_logic;
s_axis_6_tvalid : in std_logic;
s_axis_6_tready : out std_logic;
s_axis_6_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_6_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_6_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_6_tlast : in std_logic;
s_axis_6_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_6_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_6_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_7_aclk : in std_logic;
s_axis_7_aresetn : in std_logic;
s_axis_7_tvalid : in std_logic;
s_axis_7_tready : out std_logic;
s_axis_7_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_7_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_7_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_7_tlast : in std_logic;
s_axis_7_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_7_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_7_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
------------------------------------------
-- Accelerator Port input arguments (BRAM)
------------------------------------------
ap_iarg_0_clk : in std_logic;
ap_iarg_0_rst : in std_logic;
ap_iarg_0_addr : in std_logic_vector(31 downto 0);
ap_iarg_0_ce : in std_logic;
ap_iarg_0_we : in std_logic_vector(C_AP_IARG_0_DWIDTH/8-1 downto 0);
ap_iarg_0_din : in std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
ap_iarg_0_dout : out std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
---
ap_iarg_1_clk : in std_logic;
ap_iarg_1_rst : in std_logic;
ap_iarg_1_addr : in std_logic_vector(31 downto 0);
ap_iarg_1_ce : in std_logic;
ap_iarg_1_we : in std_logic_vector(C_AP_IARG_1_DWIDTH/8-1 downto 0);
ap_iarg_1_din : in std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
ap_iarg_1_dout : out std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
---
ap_iarg_2_clk : in std_logic;
ap_iarg_2_rst : in std_logic;
ap_iarg_2_addr : in std_logic_vector(31 downto 0);
ap_iarg_2_ce : in std_logic;
ap_iarg_2_we : in std_logic_vector(C_AP_IARG_2_DWIDTH/8-1 downto 0);
ap_iarg_2_din : in std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
ap_iarg_2_dout : out std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
---
ap_iarg_3_clk : in std_logic;
ap_iarg_3_rst : in std_logic;
ap_iarg_3_addr : in std_logic_vector(31 downto 0);
ap_iarg_3_ce : in std_logic;
ap_iarg_3_we : in std_logic_vector(C_AP_IARG_3_DWIDTH/8-1 downto 0);
ap_iarg_3_din : in std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
ap_iarg_3_dout : out std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
---
ap_iarg_4_clk : in std_logic;
ap_iarg_4_rst : in std_logic;
ap_iarg_4_addr : in std_logic_vector(31 downto 0);
ap_iarg_4_ce : in std_logic;
ap_iarg_4_we : in std_logic_vector(C_AP_IARG_4_DWIDTH/8-1 downto 0);
ap_iarg_4_din : in std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
ap_iarg_4_dout : out std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
---
ap_iarg_5_clk : in std_logic;
ap_iarg_5_rst : in std_logic;
ap_iarg_5_addr : in std_logic_vector(31 downto 0);
ap_iarg_5_ce : in std_logic;
ap_iarg_5_we : in std_logic_vector(C_AP_IARG_5_DWIDTH/8-1 downto 0);
ap_iarg_5_din : in std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
ap_iarg_5_dout : out std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
---
ap_iarg_6_clk : in std_logic;
ap_iarg_6_rst : in std_logic;
ap_iarg_6_addr : in std_logic_vector(31 downto 0);
ap_iarg_6_ce : in std_logic;
ap_iarg_6_we : in std_logic_vector(C_AP_IARG_6_DWIDTH/8-1 downto 0);
ap_iarg_6_din : in std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
ap_iarg_6_dout : out std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
---
ap_iarg_7_clk : in std_logic;
ap_iarg_7_rst : in std_logic;
ap_iarg_7_addr : in std_logic_vector(31 downto 0);
ap_iarg_7_ce : in std_logic;
ap_iarg_7_we : in std_logic_vector(C_AP_IARG_7_DWIDTH/8-1 downto 0);
ap_iarg_7_din : in std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
ap_iarg_7_dout : out std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
---------------------------------------------
-- Accelerator Port input arguments (FIFO) --
---------------------------------------------
ap_fifo_iarg_0_dout : out std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
ap_fifo_iarg_0_read : in std_logic;
ap_fifo_iarg_0_empty_n : out std_logic;
ap_fifo_iarg_1_dout : out std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
ap_fifo_iarg_1_read : in std_logic;
ap_fifo_iarg_1_empty_n : out std_logic;
ap_fifo_iarg_2_dout : out std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
ap_fifo_iarg_2_read : in std_logic;
ap_fifo_iarg_2_empty_n : out std_logic;
ap_fifo_iarg_3_dout : out std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
ap_fifo_iarg_3_read : in std_logic;
ap_fifo_iarg_3_empty_n : out std_logic;
ap_fifo_iarg_4_dout : out std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
ap_fifo_iarg_4_read : in std_logic;
ap_fifo_iarg_4_empty_n : out std_logic;
ap_fifo_iarg_5_dout : out std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
ap_fifo_iarg_5_read : in std_logic;
ap_fifo_iarg_5_empty_n : out std_logic;
ap_fifo_iarg_6_dout : out std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
ap_fifo_iarg_6_read : in std_logic;
ap_fifo_iarg_6_empty_n : out std_logic;
ap_fifo_iarg_7_dout : out std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
ap_fifo_iarg_7_read : in std_logic;
ap_fifo_iarg_7_empty_n : out std_logic;
-------------------------------
--* AXI4-Stream Slave Interface* --
-- Output Arguments
-------------------------------
m_axis_0_aclk : in std_logic;
m_axis_0_aresetn : in std_logic;
m_axis_0_tvalid : out std_logic;
m_axis_0_tready : in std_logic;
m_axis_0_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_0_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_0_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_0_tlast : out std_logic;
m_axis_0_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_0_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_0_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_1_aclk : in std_logic;
m_axis_1_aresetn : in std_logic;
m_axis_1_tvalid : out std_logic;
m_axis_1_tready : in std_logic;
m_axis_1_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_1_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_1_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_1_tlast : out std_logic;
m_axis_1_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_1_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_1_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_2_aclk : in std_logic;
m_axis_2_aresetn : in std_logic;
m_axis_2_tvalid : out std_logic;
m_axis_2_tready : in std_logic;
m_axis_2_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_2_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_2_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_2_tlast : out std_logic;
m_axis_2_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_2_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_2_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_3_aclk : in std_logic;
m_axis_3_aresetn : in std_logic;
m_axis_3_tvalid : out std_logic;
m_axis_3_tready : in std_logic;
m_axis_3_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_3_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_3_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_3_tlast : out std_logic;
m_axis_3_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_3_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_3_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_4_aclk : in std_logic;
m_axis_4_aresetn : in std_logic;
m_axis_4_tvalid : out std_logic;
m_axis_4_tready : in std_logic;
m_axis_4_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_4_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_4_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_4_tlast : out std_logic;
m_axis_4_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_4_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_4_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_5_aclk : in std_logic;
m_axis_5_aresetn : in std_logic;
m_axis_5_tvalid : out std_logic;
m_axis_5_tready : in std_logic;
m_axis_5_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_5_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_5_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_5_tlast : out std_logic;
m_axis_5_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_5_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_5_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_6_aclk : in std_logic;
m_axis_6_aresetn : in std_logic;
m_axis_6_tvalid : out std_logic;
m_axis_6_tready : in std_logic;
m_axis_6_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_6_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_6_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_6_tlast : out std_logic;
m_axis_6_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_6_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_6_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_7_aclk : in std_logic;
m_axis_7_aresetn : in std_logic;
m_axis_7_tvalid : out std_logic;
m_axis_7_tready : in std_logic;
m_axis_7_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_7_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_7_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_7_tlast : out std_logic;
m_axis_7_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_7_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_7_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
----------------------------------------------
-- Accelerator Port output arguments (BRAM) --
----------------------------------------------
--- AP output arguments
ap_oarg_0_clk : in std_logic;
ap_oarg_0_rst : in std_logic;
ap_oarg_0_addr : in std_logic_vector(31 downto 0);
ap_oarg_0_ce : in std_logic;
ap_oarg_0_we : in std_logic_vector(C_AP_OARG_0_DWIDTH/8-1 downto 0);
ap_oarg_0_din : in std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
ap_oarg_0_dout : out std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
---
ap_oarg_1_clk : in std_logic;
ap_oarg_1_rst : in std_logic;
ap_oarg_1_addr : in std_logic_vector(31 downto 0);
ap_oarg_1_ce : in std_logic;
ap_oarg_1_we : in std_logic_vector(C_AP_OARG_1_DWIDTH/8-1 downto 0);
ap_oarg_1_din : in std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
ap_oarg_1_dout : out std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
---
ap_oarg_2_clk : in std_logic;
ap_oarg_2_rst : in std_logic;
ap_oarg_2_addr : in std_logic_vector(31 downto 0);
ap_oarg_2_ce : in std_logic;
ap_oarg_2_we : in std_logic_vector(C_AP_OARG_2_DWIDTH/8-1 downto 0);
ap_oarg_2_din : in std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
ap_oarg_2_dout : out std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
---
ap_oarg_3_clk : in std_logic;
ap_oarg_3_rst : in std_logic;
ap_oarg_3_addr : in std_logic_vector(31 downto 0);
ap_oarg_3_ce : in std_logic;
ap_oarg_3_we : in std_logic_vector(C_AP_OARG_3_DWIDTH/8-1 downto 0);
ap_oarg_3_din : in std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
ap_oarg_3_dout : out std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
---
ap_oarg_4_clk : in std_logic;
ap_oarg_4_rst : in std_logic;
ap_oarg_4_addr : in std_logic_vector(31 downto 0);
ap_oarg_4_ce : in std_logic;
ap_oarg_4_we : in std_logic_vector(C_AP_OARG_4_DWIDTH/8-1 downto 0);
ap_oarg_4_din : in std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
ap_oarg_4_dout : out std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
---
ap_oarg_5_clk : in std_logic;
ap_oarg_5_rst : in std_logic;
ap_oarg_5_addr : in std_logic_vector(31 downto 0);
ap_oarg_5_ce : in std_logic;
ap_oarg_5_we : in std_logic_vector(C_AP_OARG_5_DWIDTH/8-1 downto 0);
ap_oarg_5_din : in std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
ap_oarg_5_dout : out std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
---
ap_oarg_6_clk : in std_logic;
ap_oarg_6_rst : in std_logic;
ap_oarg_6_addr : in std_logic_vector(31 downto 0);
ap_oarg_6_ce : in std_logic;
ap_oarg_6_we : in std_logic_vector(C_AP_OARG_6_DWIDTH/8-1 downto 0);
ap_oarg_6_din : in std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
ap_oarg_6_dout : out std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
---
ap_oarg_7_clk : in std_logic;
ap_oarg_7_rst : in std_logic;
ap_oarg_7_addr : in std_logic_vector(31 downto 0);
ap_oarg_7_ce : in std_logic;
ap_oarg_7_we : in std_logic_vector(C_AP_OARG_7_DWIDTH/8-1 downto 0);
ap_oarg_7_din : in std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
ap_oarg_7_dout : out std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
----------------------------------------------
-- Accelerator Port output arguments (FIFO) --
----------------------------------------------
ap_fifo_oarg_0_din : in std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
ap_fifo_oarg_0_write : in std_logic;
ap_fifo_oarg_0_full_n : out std_logic;
ap_fifo_oarg_1_din : in std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
ap_fifo_oarg_1_write : in std_logic;
ap_fifo_oarg_1_full_n : out std_logic;
ap_fifo_oarg_2_din : in std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
ap_fifo_oarg_2_write : in std_logic;
ap_fifo_oarg_2_full_n : out std_logic;
ap_fifo_oarg_3_din : in std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
ap_fifo_oarg_3_write : in std_logic;
ap_fifo_oarg_3_full_n : out std_logic;
ap_fifo_oarg_4_din : in std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
ap_fifo_oarg_4_write : in std_logic;
ap_fifo_oarg_4_full_n : out std_logic;
ap_fifo_oarg_5_din : in std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
ap_fifo_oarg_5_write : in std_logic;
ap_fifo_oarg_5_full_n : out std_logic;
ap_fifo_oarg_6_din : in std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
ap_fifo_oarg_6_write : in std_logic;
ap_fifo_oarg_6_full_n : out std_logic;
ap_fifo_oarg_7_din : in std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
ap_fifo_oarg_7_write : in std_logic;
ap_fifo_oarg_7_full_n : out std_logic;
----------------------------------------------
-- Accelerator Control Interface --
----------------------------------------------
ap_start : out std_logic;
ap_ready : in std_logic;
ap_done : in std_logic;
ap_continue : out std_logic;
ap_idle : in std_logic;
aresetn : out std_logic;
----------------------------------------------
-- Accelerator Input Scalar Interface --
----------------------------------------------
ap_iscalar_0_dout : out std_logic_vector(C_INPUT_SCALAR_0_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_1_dout : out std_logic_vector(C_INPUT_SCALAR_1_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_2_dout : out std_logic_vector(C_INPUT_SCALAR_2_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_3_dout : out std_logic_vector(C_INPUT_SCALAR_3_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_4_dout : out std_logic_vector(C_INPUT_SCALAR_4_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_5_dout : out std_logic_vector(C_INPUT_SCALAR_5_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_6_dout : out std_logic_vector(C_INPUT_SCALAR_6_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_7_dout : out std_logic_vector(C_INPUT_SCALAR_7_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_8_dout : out std_logic_vector(C_INPUT_SCALAR_8_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_9_dout : out std_logic_vector(C_INPUT_SCALAR_9_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_10_dout : out std_logic_vector(C_INPUT_SCALAR_10_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_11_dout : out std_logic_vector(C_INPUT_SCALAR_11_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_12_dout : out std_logic_vector(C_INPUT_SCALAR_12_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_13_dout : out std_logic_vector(C_INPUT_SCALAR_13_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_14_dout : out std_logic_vector(C_INPUT_SCALAR_14_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_15_dout : out std_logic_vector(C_INPUT_SCALAR_15_WIDTH-1 downto 0) := (others=>'0');
-- Inpput scalar Valid signals (valid for AP_HS & AP_VLD modes)
ap_iscalar_0_vld : out std_logic;
ap_iscalar_1_vld : out std_logic;
ap_iscalar_2_vld : out std_logic;
ap_iscalar_3_vld : out std_logic;
ap_iscalar_4_vld : out std_logic;
ap_iscalar_5_vld : out std_logic;
ap_iscalar_6_vld : out std_logic;
ap_iscalar_7_vld : out std_logic;
ap_iscalar_8_vld : out std_logic;
ap_iscalar_9_vld : out std_logic;
ap_iscalar_10_vld : out std_logic;
ap_iscalar_11_vld : out std_logic;
ap_iscalar_12_vld : out std_logic;
ap_iscalar_13_vld : out std_logic;
ap_iscalar_14_vld : out std_logic;
ap_iscalar_15_vld : out std_logic;
-- Input Scalar ack - (valid for AP_HS mode)
ap_iscalar_0_ack : in std_logic;
ap_iscalar_1_ack : in std_logic;
ap_iscalar_2_ack : in std_logic;
ap_iscalar_3_ack : in std_logic;
ap_iscalar_4_ack : in std_logic;
ap_iscalar_5_ack : in std_logic;
ap_iscalar_6_ack : in std_logic;
ap_iscalar_7_ack : in std_logic;
ap_iscalar_8_ack : in std_logic;
ap_iscalar_9_ack : in std_logic;
ap_iscalar_10_ack : in std_logic;
ap_iscalar_11_ack : in std_logic;
ap_iscalar_12_ack : in std_logic;
ap_iscalar_13_ack : in std_logic;
ap_iscalar_14_ack : in std_logic;
ap_iscalar_15_ack : in std_logic;
----------------------------------------------
-- Accelerator Output Scalar Interface --
----------------------------------------------
ap_oscalar_0_din : in std_logic_vector(C_OUTPUT_SCALAR_0_WIDTH-1 downto 0);
ap_oscalar_1_din : in std_logic_vector(C_OUTPUT_SCALAR_1_WIDTH-1 downto 0);
ap_oscalar_2_din : in std_logic_vector(C_OUTPUT_SCALAR_2_WIDTH-1 downto 0);
ap_oscalar_3_din : in std_logic_vector(C_OUTPUT_SCALAR_3_WIDTH-1 downto 0);
ap_oscalar_4_din : in std_logic_vector(C_OUTPUT_SCALAR_4_WIDTH-1 downto 0);
ap_oscalar_5_din : in std_logic_vector(C_OUTPUT_SCALAR_5_WIDTH-1 downto 0);
ap_oscalar_6_din : in std_logic_vector(C_OUTPUT_SCALAR_6_WIDTH-1 downto 0);
ap_oscalar_7_din : in std_logic_vector(C_OUTPUT_SCALAR_7_WIDTH-1 downto 0);
ap_oscalar_8_din : in std_logic_vector(C_OUTPUT_SCALAR_8_WIDTH-1 downto 0);
ap_oscalar_9_din : in std_logic_vector(C_OUTPUT_SCALAR_9_WIDTH-1 downto 0);
ap_oscalar_10_din : in std_logic_vector(C_OUTPUT_SCALAR_10_WIDTH-1 downto 0);
ap_oscalar_11_din : in std_logic_vector(C_OUTPUT_SCALAR_11_WIDTH-1 downto 0);
ap_oscalar_12_din : in std_logic_vector(C_OUTPUT_SCALAR_12_WIDTH-1 downto 0);
ap_oscalar_13_din : in std_logic_vector(C_OUTPUT_SCALAR_13_WIDTH-1 downto 0);
ap_oscalar_14_din : in std_logic_vector(C_OUTPUT_SCALAR_14_WIDTH-1 downto 0);
ap_oscalar_15_din : in std_logic_vector(C_OUTPUT_SCALAR_15_WIDTH-1 downto 0);
-- Output scalar Valid signals (valid for AP_HS & AP_VLD modes)
ap_oscalar_0_vld : in std_logic;
ap_oscalar_1_vld : in std_logic;
ap_oscalar_2_vld : in std_logic;
ap_oscalar_3_vld : in std_logic;
ap_oscalar_4_vld : in std_logic;
ap_oscalar_5_vld : in std_logic;
ap_oscalar_6_vld : in std_logic;
ap_oscalar_7_vld : in std_logic;
ap_oscalar_8_vld : in std_logic;
ap_oscalar_9_vld : in std_logic;
ap_oscalar_10_vld : in std_logic;
ap_oscalar_11_vld : in std_logic;
ap_oscalar_12_vld : in std_logic;
ap_oscalar_13_vld : in std_logic;
ap_oscalar_14_vld : in std_logic;
ap_oscalar_15_vld : in std_logic;
-- Output Scalar ack - (valid for AP_HS mode)
ap_oscalar_0_ack : out std_logic;
ap_oscalar_1_ack : out std_logic;
ap_oscalar_2_ack : out std_logic;
ap_oscalar_3_ack : out std_logic;
ap_oscalar_4_ack : out std_logic;
ap_oscalar_5_ack : out std_logic;
ap_oscalar_6_ack : out std_logic;
ap_oscalar_7_ack : out std_logic;
ap_oscalar_8_ack : out std_logic;
ap_oscalar_9_ack : out std_logic;
ap_oscalar_10_ack : out std_logic;
ap_oscalar_11_ack : out std_logic;
ap_oscalar_12_ack : out std_logic;
ap_oscalar_13_ack : out std_logic;
ap_oscalar_14_ack : out std_logic;
ap_oscalar_15_ack : out std_logic;
---
interrupt : out std_logic);
end entity;
architecture rtl of axis_accelerator_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
-- Constant declaration
constant C_S_AXIS_TSTRB_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_S_AXIS_TKEEP_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TSTRB_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TKEEP_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_MAX_SCALAR_DWIDTH : integer := 32;
constant C_MAX_ARG_DWIDTH : integer := 1024;
constant C_MAX_ARG_SWIDTH : integer := 16; -- Strobe width
constant C_MAX_ARG_AWIDTH : integer := 16;
constant C_MAX_ARG_N_DIM : integer := 4;
constant C_MAX_MB_DEPTH : integer := 8;
constant C_MAX_N_IARGS : integer := 8;
constant C_MAX_N_OARGS : integer := 8;
constant C_MAX_N_ISCALARS : integer := 8;
constant C_MAX_N_OSCALARS : integer := 8;
constant C_MAX_N_IOSCALARS : integer := 8;
constant C_MTBF_STAGES : integer := 4;
-------------------------
-- Scaler Data Width
-------------------------
-- GENERIC GROUPING: INPUT ARGUMENTS:
function calc_iarg_dwidth return std_logic_vector is
variable value : std_logic_vector(C_MAX_N_IARGS*32-1 downto 0) := (others => '0');
begin
value(32*(0+1)-1 downto 32*0) := int2lv(C_AP_IARG_0_DWIDTH);
value(32*(1+1)-1 downto 32*1) := int2lv(C_AP_IARG_1_DWIDTH);
value(32*(2+1)-1 downto 32*2) := int2lv(C_AP_IARG_2_DWIDTH);
value(32*(3+1)-1 downto 32*3) := int2lv(C_AP_IARG_3_DWIDTH);
value(32*(4+1)-1 downto 32*4) := int2lv(C_AP_IARG_4_DWIDTH);
value(32*(5+1)-1 downto 32*5) := int2lv(C_AP_IARG_5_DWIDTH);
value(32*(6+1)-1 downto 32*6) := int2lv(C_AP_IARG_6_DWIDTH);
value(32*(7+1)-1 downto 32*7) := int2lv(C_AP_IARG_7_DWIDTH);
return value;
end function calc_iarg_dwidth;
---------------------------------------------------------
-- GENERIC GROUPING: OUTPUT ARGUMENTS
function calc_oarg_dwidth return std_logic_vector is
variable value : std_logic_vector(C_MAX_N_OARGS*32-1 downto 0) := (others => '0');
begin
value(32*(0+1)-1 downto 32*0) := int2lv(C_AP_OARG_0_DWIDTH);
value(32*(1+1)-1 downto 32*1) := int2lv(C_AP_OARG_1_DWIDTH);
value(32*(2+1)-1 downto 32*2) := int2lv(C_AP_OARG_2_DWIDTH);
value(32*(3+1)-1 downto 32*3) := int2lv(C_AP_OARG_3_DWIDTH);
value(32*(4+1)-1 downto 32*4) := int2lv(C_AP_OARG_4_DWIDTH);
value(32*(5+1)-1 downto 32*5) := int2lv(C_AP_OARG_5_DWIDTH);
value(32*(6+1)-1 downto 32*6) := int2lv(C_AP_OARG_6_DWIDTH);
value(32*(7+1)-1 downto 32*7) := int2lv(C_AP_OARG_7_DWIDTH);
return value;
end function calc_oarg_dwidth;
-------------------------
-- BRAM PRIMITIVE TYPE
-- 7_SERIES : RAMB36E1, ULRASCALE : RAMB36E2
-------------------------
function calc_bram_type return string is
begin
if (C_FAMILY = "virtexu" or C_FAMILY = "kintexu" or C_FAMILY = "artixu" or C_FAMILY = "virtexuplus" or C_FAMILY = "kintexuplus" or C_FAMILY = "zynquplus") then
return "ULTRASCALE";
else
return "7_SERIES";
end if ;
end function calc_bram_type;
constant BRAM_PRIMITIVE_TYPE : string := calc_bram_type;
constant C_AP_OARG_DWIDTH : std_logic_vector(C_MAX_N_OARGS*32-1 downto 0) := calc_oarg_dwidth;
constant C_AP_IARG_DWIDTH : std_logic_vector(C_MAX_N_IARGS*32-1 downto 0) := calc_iarg_dwidth;
-- SUPERBUSSES DECLARATION:
signal s_axis_aclk_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_aresetn_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tvalid : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tready : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tdata : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDATA_WIDTH-1 downto 0);
signal s_axis_tstrb : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TSTRB_WIDTH-1 downto 0);
signal s_axis_tkeep : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TKEEP_WIDTH-1 downto 0);
signal s_axis_tlast : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tid : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TID_WIDTH-1 downto 0);
signal s_axis_tdest : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDEST_WIDTH-1 downto 0);
signal s_axis_tuser : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TUSER_WIDTH-1 downto 0);
signal m_axis_aclk_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_aresetn_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tvalid : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tready : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tdata : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal m_axis_tstrb : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TSTRB_WIDTH-1 downto 0);
signal m_axis_tkeep : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TKEEP_WIDTH-1 downto 0);
signal m_axis_tlast : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tid : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TID_WIDTH-1 downto 0);
signal m_axis_tdest : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
signal m_axis_tuser : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TUSER_WIDTH-1 downto 0);
signal ap_iarg_addr : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_AWIDTH-1 downto 0);
signal ap_iarg_ce : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_iarg_we : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_iarg_din : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_iarg_dout : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_oarg_addr : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_AWIDTH-1 downto 0);
signal ap_oarg_ce : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_oarg_we : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_oarg_din : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_oarg_dout : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
-------------------------------------------------------
constant AP_IARG_0_OFFSET : integer := log2(C_AP_IARG_0_DWIDTH/8);
constant AP_IARG_1_OFFSET : integer := log2(C_AP_IARG_1_DWIDTH/8);
constant AP_IARG_2_OFFSET : integer := log2(C_AP_IARG_2_DWIDTH/8);
constant AP_IARG_3_OFFSET : integer := log2(C_AP_IARG_3_DWIDTH/8);
constant AP_IARG_4_OFFSET : integer := log2(C_AP_IARG_4_DWIDTH/8);
constant AP_IARG_5_OFFSET : integer := log2(C_AP_IARG_5_DWIDTH/8);
constant AP_IARG_6_OFFSET : integer := log2(C_AP_IARG_6_DWIDTH/8);
constant AP_IARG_7_OFFSET : integer := log2(C_AP_IARG_7_DWIDTH/8);
constant AP_OARG_0_OFFSET : integer := log2(C_AP_OARG_0_DWIDTH/8);
constant AP_OARG_1_OFFSET : integer := log2(C_AP_OARG_1_DWIDTH/8);
constant AP_OARG_2_OFFSET : integer := log2(C_AP_OARG_2_DWIDTH/8);
constant AP_OARG_3_OFFSET : integer := log2(C_AP_OARG_3_DWIDTH/8);
constant AP_OARG_4_OFFSET : integer := log2(C_AP_OARG_4_DWIDTH/8);
constant AP_OARG_5_OFFSET : integer := log2(C_AP_OARG_5_DWIDTH/8);
constant AP_OARG_6_OFFSET : integer := log2(C_AP_OARG_6_DWIDTH/8);
constant AP_OARG_7_OFFSET : integer := log2(C_AP_OARG_7_DWIDTH/8);
-------------------------------------------------
signal ap_fifo_iarg_dout : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_fifo_iarg_read : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_fifo_iarg_empty_n : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_fifo_oarg_din : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_fifo_oarg_write : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_fifo_oarg_full_n : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-------------------------------------------------
-- Scaler signals
signal ap_iscalar_dout_i : std_logic_vector(511 downto 0);
signal ap_oscalar_din_i : std_logic_vector(511 downto 0);
signal ap_oscalar_din_int : std_logic_vector(C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
signal ap_ioscalar_din_int : std_logic_vector(C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0);
signal ap_oscalar_vld_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal ap_iscalar_vld_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal ap_oscalar_ack_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal ap_iscalar_ack_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal zeros1 : std_logic_vector(256-C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
signal zeros256 : std_logic_vector(255 downto 0);
begin
zeros1 <= (others => '0');
zeros256 <= (others => '0');
----------------------------------------------
-- Scalar signals assignments
----------------------------------------------
ap_oscalar_vld_i <= ap_oscalar_15_vld & ap_oscalar_14_vld & ap_oscalar_13_vld &
ap_oscalar_12_vld & ap_oscalar_11_vld & ap_oscalar_10_vld &
ap_oscalar_9_vld & ap_oscalar_8_vld & ap_oscalar_7_vld &
ap_oscalar_6_vld & ap_oscalar_5_vld & ap_oscalar_4_vld &
ap_oscalar_3_vld & ap_oscalar_2_vld & ap_oscalar_1_vld &
ap_oscalar_0_vld;
ap_iscalar_ack_i <= ap_iscalar_15_ack & ap_iscalar_14_ack & ap_iscalar_13_ack &
ap_iscalar_12_ack & ap_iscalar_11_ack & ap_iscalar_10_ack &
ap_iscalar_9_ack & ap_iscalar_8_ack & ap_iscalar_7_ack &
ap_iscalar_6_ack & ap_iscalar_5_ack & ap_iscalar_4_ack &
ap_iscalar_3_ack & ap_iscalar_2_ack & ap_iscalar_1_ack &
ap_iscalar_0_ack;
-- Output scalar ack generation
ap_oscalar_0_ack <= ap_oscalar_ack_i(0);
ap_oscalar_1_ack <= ap_oscalar_ack_i(1);
ap_oscalar_2_ack <= ap_oscalar_ack_i(2);
ap_oscalar_3_ack <= ap_oscalar_ack_i(3);
ap_oscalar_4_ack <= ap_oscalar_ack_i(4);
ap_oscalar_5_ack <= ap_oscalar_ack_i(5);
ap_oscalar_6_ack <= ap_oscalar_ack_i(6);
ap_oscalar_7_ack <= ap_oscalar_ack_i(7);
ap_oscalar_8_ack <= ap_oscalar_ack_i(8);
ap_oscalar_9_ack <= ap_oscalar_ack_i(9);
ap_oscalar_10_ack <= ap_oscalar_ack_i(10);
ap_oscalar_11_ack <= ap_oscalar_ack_i(11);
ap_oscalar_12_ack <= ap_oscalar_ack_i(12);
ap_oscalar_13_ack <= ap_oscalar_ack_i(13);
ap_oscalar_14_ack <= ap_oscalar_ack_i(14);
ap_oscalar_15_ack <= ap_oscalar_ack_i(15);
-- input scalar valid generation
ap_iscalar_0_vld <= ap_iscalar_vld_i(0);
ap_iscalar_1_vld <= ap_iscalar_vld_i(1);
ap_iscalar_2_vld <= ap_iscalar_vld_i(2);
ap_iscalar_3_vld <= ap_iscalar_vld_i(3);
ap_iscalar_4_vld <= ap_iscalar_vld_i(4);
ap_iscalar_5_vld <= ap_iscalar_vld_i(5);
ap_iscalar_6_vld <= ap_iscalar_vld_i(6);
ap_iscalar_7_vld <= ap_iscalar_vld_i(7);
ap_iscalar_8_vld <= ap_iscalar_vld_i(8);
ap_iscalar_9_vld <= ap_iscalar_vld_i(9);
ap_iscalar_10_vld <= ap_iscalar_vld_i(10);
ap_iscalar_11_vld <= ap_iscalar_vld_i(11);
ap_iscalar_12_vld <= ap_iscalar_vld_i(12);
ap_iscalar_13_vld <= ap_iscalar_vld_i(13);
ap_iscalar_14_vld <= ap_iscalar_vld_i(14);
ap_iscalar_15_vld <= ap_iscalar_vld_i(15);
----------------------------------------------
-- Output Scalar signals assignments
----------------------------------------------
OSCALER_0_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_int <= (others=>'0');
end generate OSCALER_0_GEN;
OSCALER_1_GEN : if (C_N_OUTPUT_SCALARS = 1) generate
begin
ap_oscalar_din_int <= ap_oscalar_0_din;
end generate OSCALER_1_GEN;
OSCALER_2_GEN : if (C_N_OUTPUT_SCALARS = 2) generate
begin
ap_oscalar_din_int <= ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_2_GEN;
OSCALER_3_GEN : if (C_N_OUTPUT_SCALARS = 3) generate
begin
ap_oscalar_din_int <= ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_3_GEN;
OSCALER_4_GEN : if (C_N_OUTPUT_SCALARS = 4) generate
begin
ap_oscalar_din_int <= ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_4_GEN;
OSCALER_5_GEN : if (C_N_OUTPUT_SCALARS = 5) generate
begin
ap_oscalar_din_int <= ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_5_GEN;
OSCALER_6_GEN : if (C_N_OUTPUT_SCALARS = 6) generate
begin
ap_oscalar_din_int <= ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_6_GEN;
OSCALER_7_GEN : if (C_N_OUTPUT_SCALARS = 7) generate
begin
ap_oscalar_din_int <= ap_oscalar_6_din & ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_7_GEN;
OSCALER_8_GEN : if (C_N_OUTPUT_SCALARS = 8) generate
begin
ap_oscalar_din_int <= ap_oscalar_7_din & ap_oscalar_6_din & ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_8_GEN;
IOSCALER_0_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
ap_ioscalar_din_int <= (others=>'0');
end generate IOSCALER_0_GEN;
OSCALER_9_GEN : if (C_N_INOUT_SCALARS = 1) generate
begin
ap_ioscalar_din_int <= ap_oscalar_8_din;
end generate OSCALER_9_GEN;
OSCALER_10_GEN : if (C_N_INOUT_SCALARS = 2) generate
begin
ap_ioscalar_din_int <= ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_10_GEN;
OSCALER_11_GEN : if (C_N_INOUT_SCALARS = 3) generate
begin
ap_ioscalar_din_int <= ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_11_GEN;
OSCALER_12_GEN : if (C_N_INOUT_SCALARS = 4) generate
begin
ap_ioscalar_din_int <= ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_12_GEN;
OSCALER_13_GEN : if (C_N_INOUT_SCALARS = 5) generate
begin
ap_ioscalar_din_int <= ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_13_GEN;
OSCALER_14_GEN : if (C_N_INOUT_SCALARS = 6) generate
begin
ap_ioscalar_din_int <= ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_14_GEN;
OSCALER_15_GEN : if (C_N_INOUT_SCALARS = 7) generate
begin
ap_ioscalar_din_int <= ap_oscalar_14_din & ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_15_GEN;
OSCALER_16_GEN : if (C_N_INOUT_SCALARS = 8) generate
begin
ap_ioscalar_din_int <= ap_oscalar_15_din & ap_oscalar_14_din & ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_16_GEN;
OSCALER_GEN_1 : if (C_N_INOUT_SCALARS > 0 and C_N_OUTPUT_SCALARS > 0) generate
begin
ap_oscalar_din_i(256+C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0) <= ap_ioscalar_din_int & zeros1 & ap_oscalar_din_int;
OSCALER_ZERO_GEN_1 : if (C_AP_OSCALAR_IO_DIN_WIDTH < 256 ) generate
ap_oscalar_din_i(511 downto 256+C_AP_OSCALAR_IO_DIN_WIDTH) <= (others =>'0') ;
end generate OSCALER_ZERO_GEN_1;
end generate OSCALER_GEN_1;
OSCALER_GEN_2 : if (C_N_INOUT_SCALARS = 0 and C_N_OUTPUT_SCALARS > 0) generate
begin
ap_oscalar_din_i(C_AP_OSCALAR_DIN_WIDTH-1 downto 0) <= ap_oscalar_din_int;
ap_oscalar_din_i(511 downto C_AP_OSCALAR_DIN_WIDTH) <= (others => '0');
end generate OSCALER_GEN_2;
OSCALER_GEN_3 : if (C_N_INOUT_SCALARS > 0 and C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_i(256+C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0) <= ap_ioscalar_din_int & zeros256 ;
OSCALER_ZERO_GEN_3 : if (C_AP_OSCALAR_IO_DIN_WIDTH < 256 ) generate
ap_oscalar_din_i(511 downto 256+C_AP_OSCALAR_IO_DIN_WIDTH) <= (others =>'0') ;
end generate OSCALER_ZERO_GEN_3;
end generate OSCALER_GEN_3;
OSCALER_GEN_4 : if (C_N_INOUT_SCALARS = 0 and C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_i <= (others => '0');
end generate OSCALER_GEN_4;
----------------------------------------------
-- Input Scalar signals assignments
----------------------------------------------
ISCALER_1_GEN : if (C_N_INPUT_SCALARS > 0) generate
begin
ap_iscalar_0_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 0)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 0)));
end generate ISCALER_1_GEN;
ISCALER_2_GEN : if (C_N_INPUT_SCALARS > 1) generate
begin
ap_iscalar_1_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 1)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 1)));
end generate ISCALER_2_GEN;
ISCALER_3_GEN : if (C_N_INPUT_SCALARS > 2) generate
begin
ap_iscalar_2_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 2)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 2)));
end generate ISCALER_3_GEN;
ISCALER_4_GEN : if (C_N_INPUT_SCALARS > 3) generate
begin
ap_iscalar_3_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 3)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 3)));
end generate ISCALER_4_GEN;
ISCALER_5_GEN : if (C_N_INPUT_SCALARS > 4) generate
begin
ap_iscalar_4_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 4)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 4)));
end generate ISCALER_5_GEN;
ISCALER_6_GEN : if (C_N_INPUT_SCALARS > 5) generate
begin
ap_iscalar_5_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 5)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 5)));
end generate ISCALER_6_GEN;
ISCALER_7_GEN : if (C_N_INPUT_SCALARS > 6) generate
begin
ap_iscalar_6_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 6)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 6)));
end generate ISCALER_7_GEN;
ISCALER_8_GEN : if (C_N_INPUT_SCALARS > 7) generate
begin
ap_iscalar_7_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 7)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 7)));
end generate ISCALER_8_GEN;
ISCALER_9_GEN : if (C_N_INOUT_SCALARS > 0) generate
begin
ap_iscalar_8_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 8)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 8)));
end generate ISCALER_9_GEN;
ISCALER_10_GEN : if (C_N_INOUT_SCALARS > 1) generate
begin
ap_iscalar_9_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 9)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 9)));
end generate ISCALER_10_GEN;
ISCALER_11_GEN : if (C_N_INOUT_SCALARS > 2) generate
begin
ap_iscalar_10_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 10)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 10)));
end generate ISCALER_11_GEN;
ISCALER_12_GEN : if (C_N_INOUT_SCALARS > 3) generate
begin
ap_iscalar_11_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 11)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 11)));
end generate ISCALER_12_GEN;
ISCALER_13_GEN : if (C_N_INOUT_SCALARS > 4) generate
begin
ap_iscalar_12_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 12)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 12)));
end generate ISCALER_13_GEN;
ISCALER_14_GEN : if (C_N_INOUT_SCALARS > 5) generate
begin
ap_iscalar_13_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 13)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 13)));
end generate ISCALER_14_GEN;
ISCALER_15_GEN : if (C_N_INOUT_SCALARS > 6) generate
begin
ap_iscalar_14_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 14)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 14)));
end generate ISCALER_15_GEN;
ISCALER_16_GEN : if (C_N_INOUT_SCALARS > 7) generate
begin
ap_iscalar_15_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 15)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 15)));
end generate ISCALER_16_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- Single stremaing clock and reset port exposed to user. Asynchronous clocks between the
-- different streaming channel not supported
-----------------------------------------------------------------------------------------
SINGLE_CLK_RST_GEN : if (C_ENABLE_STREAM_CLK = 0) generate
s_axis_aclk_i(0) <= s_axis_aclk;
s_axis_aclk_i(1) <= s_axis_aclk;
s_axis_aclk_i(2) <= s_axis_aclk;
s_axis_aclk_i(3) <= s_axis_aclk;
s_axis_aclk_i(4) <= s_axis_aclk;
s_axis_aclk_i(5) <= s_axis_aclk;
s_axis_aclk_i(6) <= s_axis_aclk;
s_axis_aclk_i(7) <= s_axis_aclk;
s_axis_aresetn_i(0) <= s_axis_aresetn;
s_axis_aresetn_i(1) <= s_axis_aresetn;
s_axis_aresetn_i(2) <= s_axis_aresetn;
s_axis_aresetn_i(3) <= s_axis_aresetn;
s_axis_aresetn_i(4) <= s_axis_aresetn;
s_axis_aresetn_i(5) <= s_axis_aresetn;
s_axis_aresetn_i(6) <= s_axis_aresetn;
s_axis_aresetn_i(7) <= s_axis_aresetn;
m_axis_aclk_i(0) <= m_axis_aclk;
m_axis_aclk_i(1) <= m_axis_aclk;
m_axis_aclk_i(2) <= m_axis_aclk;
m_axis_aclk_i(3) <= m_axis_aclk;
m_axis_aclk_i(4) <= m_axis_aclk;
m_axis_aclk_i(5) <= m_axis_aclk;
m_axis_aclk_i(6) <= m_axis_aclk;
m_axis_aclk_i(7) <= m_axis_aclk;
m_axis_aresetn_i(0) <= m_axis_aresetn;
m_axis_aresetn_i(1) <= m_axis_aresetn;
m_axis_aresetn_i(2) <= m_axis_aresetn;
m_axis_aresetn_i(3) <= m_axis_aresetn;
m_axis_aresetn_i(4) <= m_axis_aresetn;
m_axis_aresetn_i(5) <= m_axis_aresetn;
m_axis_aresetn_i(6) <= m_axis_aresetn;
m_axis_aresetn_i(7) <= m_axis_aresetn;
end generate SINGLE_CLK_RST_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- Asynchronous clocks between the different streaming channel supported
-----------------------------------------------------------------------------------------
ASYNC_CLK_RST_GEN : if (C_ENABLE_STREAM_CLK = 1) generate
s_axis_aclk_i(0) <= s_axis_0_aclk;
s_axis_aclk_i(1) <= s_axis_1_aclk;
s_axis_aclk_i(2) <= s_axis_2_aclk;
s_axis_aclk_i(3) <= s_axis_3_aclk;
s_axis_aclk_i(4) <= s_axis_4_aclk;
s_axis_aclk_i(5) <= s_axis_5_aclk;
s_axis_aclk_i(6) <= s_axis_6_aclk;
s_axis_aclk_i(7) <= s_axis_7_aclk;
s_axis_aresetn_i(0) <= s_axis_0_aresetn;
s_axis_aresetn_i(1) <= s_axis_1_aresetn;
s_axis_aresetn_i(2) <= s_axis_2_aresetn;
s_axis_aresetn_i(3) <= s_axis_3_aresetn;
s_axis_aresetn_i(4) <= s_axis_4_aresetn;
s_axis_aresetn_i(5) <= s_axis_5_aresetn;
s_axis_aresetn_i(6) <= s_axis_6_aresetn;
s_axis_aresetn_i(7) <= s_axis_7_aresetn;
m_axis_aclk_i(0) <= m_axis_0_aclk;
m_axis_aclk_i(1) <= m_axis_1_aclk;
m_axis_aclk_i(2) <= m_axis_2_aclk;
m_axis_aclk_i(3) <= m_axis_3_aclk;
m_axis_aclk_i(4) <= m_axis_4_aclk;
m_axis_aclk_i(5) <= m_axis_5_aclk;
m_axis_aclk_i(6) <= m_axis_6_aclk;
m_axis_aclk_i(7) <= m_axis_7_aclk;
m_axis_aresetn_i(0) <= m_axis_0_aresetn;
m_axis_aresetn_i(1) <= m_axis_1_aresetn;
m_axis_aresetn_i(2) <= m_axis_2_aresetn;
m_axis_aresetn_i(3) <= m_axis_3_aresetn;
m_axis_aresetn_i(4) <= m_axis_4_aresetn;
m_axis_aresetn_i(5) <= m_axis_5_aresetn;
m_axis_aresetn_i(6) <= m_axis_6_aresetn;
m_axis_aresetn_i(7) <= m_axis_7_aresetn;
end generate ASYNC_CLK_RST_GEN;
-------------------------------------------------------------------------------------------------
-- Assiging default value '1' when TSTRB and TKEEP signals are not present in the Input stream.
-- When Input stream STROBE and KEEP are available, no need to drive default values.
-- This is work around to resolve the Vivado wrapper issue which does not drive default input '1'
-- properly when signla widht is less than 4 bits.
-------------------------------------------------------------------------------------------------
EN_TSTRB_GEN : if (C_S_AXIS_HAS_TSTRB = 1) generate
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(0+1)-1 downto C_S_AXIS_TSTRB_WIDTH*0) <= s_axis_0_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(1+1)-1 downto C_S_AXIS_TSTRB_WIDTH*1) <= s_axis_1_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(2+1)-1 downto C_S_AXIS_TSTRB_WIDTH*2) <= s_axis_2_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(3+1)-1 downto C_S_AXIS_TSTRB_WIDTH*3) <= s_axis_3_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(4+1)-1 downto C_S_AXIS_TSTRB_WIDTH*4) <= s_axis_4_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(5+1)-1 downto C_S_AXIS_TSTRB_WIDTH*5) <= s_axis_5_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(6+1)-1 downto C_S_AXIS_TSTRB_WIDTH*6) <= s_axis_6_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(7+1)-1 downto C_S_AXIS_TSTRB_WIDTH*7) <= s_axis_7_tstrb;
end generate EN_TSTRB_GEN;
NO_TSTRB_GEN : if (C_S_AXIS_HAS_TSTRB = 0) generate
s_axis_tstrb <= (others => '1') ;
end generate NO_TSTRB_GEN;
-- TKEEP generation
EN_TKEEP_GEN : if (C_S_AXIS_HAS_TKEEP = 1) generate
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(0+1)-1 downto C_S_AXIS_TKEEP_WIDTH*0) <= s_axis_0_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(1+1)-1 downto C_S_AXIS_TKEEP_WIDTH*1) <= s_axis_1_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(2+1)-1 downto C_S_AXIS_TKEEP_WIDTH*2) <= s_axis_2_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(3+1)-1 downto C_S_AXIS_TKEEP_WIDTH*3) <= s_axis_3_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(4+1)-1 downto C_S_AXIS_TKEEP_WIDTH*4) <= s_axis_4_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(5+1)-1 downto C_S_AXIS_TKEEP_WIDTH*5) <= s_axis_5_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(6+1)-1 downto C_S_AXIS_TKEEP_WIDTH*6) <= s_axis_6_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(7+1)-1 downto C_S_AXIS_TKEEP_WIDTH*7) <= s_axis_7_tkeep;
end generate EN_TKEEP_GEN;
NO_TKEEP_GEN : if (C_S_AXIS_HAS_TKEEP = 0) generate
s_axis_tkeep <= (others => '1') ;
end generate NO_TKEEP_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- SUPERBUSES BUILDING: SLAVE AXI STREAMS (INPUT ARGUMENTS):
-- NOTE FOR SIMULATION: This concatenation inserts a delta delay for clocks signals. In
-- the case of input signals causality is preserved becouse another delta delay is
-- inserted during their concatenation. For input signals, there is no problem
-----------------------------------------------------------------------------------------
--AXI4-Stream slave interface TVALID generation
s_axis_tvalid(0) <= s_axis_0_tvalid;
s_axis_tvalid(1) <= s_axis_1_tvalid;
s_axis_tvalid(2) <= s_axis_2_tvalid;
s_axis_tvalid(3) <= s_axis_3_tvalid;
s_axis_tvalid(4) <= s_axis_4_tvalid;
s_axis_tvalid(5) <= s_axis_5_tvalid;
s_axis_tvalid(6) <= s_axis_6_tvalid;
s_axis_tvalid(7) <= s_axis_7_tvalid;
--AXI4-Stream slave interface TREADY generation
s_axis_0_tready <= s_axis_tready(0);
s_axis_1_tready <= s_axis_tready(1);
s_axis_2_tready <= s_axis_tready(2);
s_axis_3_tready <= s_axis_tready(3);
s_axis_4_tready <= s_axis_tready(4);
s_axis_5_tready <= s_axis_tready(5);
s_axis_6_tready <= s_axis_tready(6);
s_axis_7_tready <= s_axis_tready(7);
--AXI4-Stream slave interface TDATA generation
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(0+1)-1 downto C_S_AXIS_TDATA_WIDTH*0) <= s_axis_0_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(1+1)-1 downto C_S_AXIS_TDATA_WIDTH*1) <= s_axis_1_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(2+1)-1 downto C_S_AXIS_TDATA_WIDTH*2) <= s_axis_2_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(3+1)-1 downto C_S_AXIS_TDATA_WIDTH*3) <= s_axis_3_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(4+1)-1 downto C_S_AXIS_TDATA_WIDTH*4) <= s_axis_4_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(5+1)-1 downto C_S_AXIS_TDATA_WIDTH*5) <= s_axis_5_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(6+1)-1 downto C_S_AXIS_TDATA_WIDTH*6) <= s_axis_6_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(7+1)-1 downto C_S_AXIS_TDATA_WIDTH*7) <= s_axis_7_tdata;
--AXI4-Stream slave interface TLAST generation
s_axis_tlast(0) <= s_axis_0_tlast;
s_axis_tlast(1) <= s_axis_1_tlast;
s_axis_tlast(2) <= s_axis_2_tlast;
s_axis_tlast(3) <= s_axis_3_tlast;
s_axis_tlast(4) <= s_axis_4_tlast;
s_axis_tlast(5) <= s_axis_5_tlast;
s_axis_tlast(6) <= s_axis_6_tlast;
s_axis_tlast(7) <= s_axis_7_tlast;
--AXI4-Stream slave interface TID generation
s_axis_tid(C_S_AXIS_TID_WIDTH*(0+1)-1 downto C_S_AXIS_TID_WIDTH*0) <= s_axis_0_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(1+1)-1 downto C_S_AXIS_TID_WIDTH*1) <= s_axis_1_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(2+1)-1 downto C_S_AXIS_TID_WIDTH*2) <= s_axis_2_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(3+1)-1 downto C_S_AXIS_TID_WIDTH*3) <= s_axis_3_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(4+1)-1 downto C_S_AXIS_TID_WIDTH*4) <= s_axis_4_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(5+1)-1 downto C_S_AXIS_TID_WIDTH*5) <= s_axis_5_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(6+1)-1 downto C_S_AXIS_TID_WIDTH*6) <= s_axis_6_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(7+1)-1 downto C_S_AXIS_TID_WIDTH*7) <= s_axis_7_tid;
--AXI4-Stream slave interface TDEST generation
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(0+1)-1 downto C_S_AXIS_TDEST_WIDTH*0) <= s_axis_0_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(1+1)-1 downto C_S_AXIS_TDEST_WIDTH*1) <= s_axis_1_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(2+1)-1 downto C_S_AXIS_TDEST_WIDTH*2) <= s_axis_2_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(3+1)-1 downto C_S_AXIS_TDEST_WIDTH*3) <= s_axis_3_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(4+1)-1 downto C_S_AXIS_TDEST_WIDTH*4) <= s_axis_4_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(5+1)-1 downto C_S_AXIS_TDEST_WIDTH*5) <= s_axis_5_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(6+1)-1 downto C_S_AXIS_TDEST_WIDTH*6) <= s_axis_6_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(7+1)-1 downto C_S_AXIS_TDEST_WIDTH*7) <= s_axis_7_tdest;
--AXI4-Stream slave interface TUSER generation
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(0+1)-1 downto C_S_AXIS_TUSER_WIDTH*0) <= s_axis_0_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(1+1)-1 downto C_S_AXIS_TUSER_WIDTH*1) <= s_axis_1_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(2+1)-1 downto C_S_AXIS_TUSER_WIDTH*2) <= s_axis_2_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(3+1)-1 downto C_S_AXIS_TUSER_WIDTH*3) <= s_axis_3_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(4+1)-1 downto C_S_AXIS_TUSER_WIDTH*4) <= s_axis_4_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(5+1)-1 downto C_S_AXIS_TUSER_WIDTH*5) <= s_axis_5_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(6+1)-1 downto C_S_AXIS_TUSER_WIDTH*6) <= s_axis_6_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(7+1)-1 downto C_S_AXIS_TUSER_WIDTH*7) <= s_axis_7_tuser;
-----------------------------------------------------------------------------------------
-- Accelerator Input Argument interface signal Generation
-- SUPERBUSES BUILDING: AP INPUT ARGUMENTS:
-----------------------------------------------------------------------------------------
-- Input Argument BRAM interface addr generation
ap_iarg_addr(C_MAX_ARG_AWIDTH*(0+1)-1 downto C_MAX_ARG_AWIDTH*0) <= ap_iarg_0_addr(C_MAX_ARG_AWIDTH+AP_IARG_0_OFFSET-1 downto AP_IARG_0_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(1+1)-1 downto C_MAX_ARG_AWIDTH*1) <= ap_iarg_1_addr(C_MAX_ARG_AWIDTH+AP_IARG_1_OFFSET-1 downto AP_IARG_1_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(2+1)-1 downto C_MAX_ARG_AWIDTH*2) <= ap_iarg_2_addr(C_MAX_ARG_AWIDTH+AP_IARG_2_OFFSET-1 downto AP_IARG_2_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(3+1)-1 downto C_MAX_ARG_AWIDTH*3) <= ap_iarg_3_addr(C_MAX_ARG_AWIDTH+AP_IARG_3_OFFSET-1 downto AP_IARG_3_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(4+1)-1 downto C_MAX_ARG_AWIDTH*4) <= ap_iarg_4_addr(C_MAX_ARG_AWIDTH+AP_IARG_4_OFFSET-1 downto AP_IARG_4_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(5+1)-1 downto C_MAX_ARG_AWIDTH*5) <= ap_iarg_5_addr(C_MAX_ARG_AWIDTH+AP_IARG_5_OFFSET-1 downto AP_IARG_5_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(6+1)-1 downto C_MAX_ARG_AWIDTH*6) <= ap_iarg_6_addr(C_MAX_ARG_AWIDTH+AP_IARG_6_OFFSET-1 downto AP_IARG_6_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(7+1)-1 downto C_MAX_ARG_AWIDTH*7) <= ap_iarg_7_addr(C_MAX_ARG_AWIDTH+AP_IARG_7_OFFSET-1 downto AP_IARG_7_OFFSET);
-- Input Argument BRAM interface ce generation
ap_iarg_ce(0) <= ap_iarg_0_ce;
ap_iarg_ce(1) <= ap_iarg_1_ce;
ap_iarg_ce(2) <= ap_iarg_2_ce;
ap_iarg_ce(3) <= ap_iarg_3_ce;
ap_iarg_ce(4) <= ap_iarg_4_ce;
ap_iarg_ce(5) <= ap_iarg_5_ce;
ap_iarg_ce(6) <= ap_iarg_6_ce;
ap_iarg_ce(7) <= ap_iarg_7_ce;
-- Input Argument BRAM interface we generation
ap_iarg_we(0) <= ap_iarg_0_we(0);
ap_iarg_we(1) <= ap_iarg_1_we(0);
ap_iarg_we(2) <= ap_iarg_2_we(0);
ap_iarg_we(3) <= ap_iarg_3_we(0);
ap_iarg_we(4) <= ap_iarg_4_we(0);
ap_iarg_we(5) <= ap_iarg_5_we(0);
ap_iarg_we(6) <= ap_iarg_6_we(0);
ap_iarg_we(7) <= ap_iarg_7_we(0);
-- Input Argument BRAM interface din generation
ap_iarg_din(C_MAX_ARG_DWIDTH*(0+1)-1 downto C_MAX_ARG_DWIDTH*0) <= ext_lv(ap_iarg_0_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(1+1)-1 downto C_MAX_ARG_DWIDTH*1) <= ext_lv(ap_iarg_1_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(2+1)-1 downto C_MAX_ARG_DWIDTH*2) <= ext_lv(ap_iarg_2_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(3+1)-1 downto C_MAX_ARG_DWIDTH*3) <= ext_lv(ap_iarg_3_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(4+1)-1 downto C_MAX_ARG_DWIDTH*4) <= ext_lv(ap_iarg_4_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(5+1)-1 downto C_MAX_ARG_DWIDTH*5) <= ext_lv(ap_iarg_5_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(6+1)-1 downto C_MAX_ARG_DWIDTH*6) <= ext_lv(ap_iarg_6_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(7+1)-1 downto C_MAX_ARG_DWIDTH*7) <= ext_lv(ap_iarg_7_din, C_MAX_ARG_DWIDTH);
-- Input Argument BRAM interface dout generation
ap_iarg_0_dout <= ap_iarg_dout(C_AP_IARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_iarg_1_dout <= ap_iarg_dout(C_AP_IARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_iarg_2_dout <= ap_iarg_dout(C_AP_IARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_iarg_3_dout <= ap_iarg_dout(C_AP_IARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_iarg_4_dout <= ap_iarg_dout(C_AP_IARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_iarg_5_dout <= ap_iarg_dout(C_AP_IARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_iarg_6_dout <= ap_iarg_dout(C_AP_IARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_iarg_7_dout <= ap_iarg_dout(C_AP_IARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Input Argument FIFO interface dout generation
ap_fifo_iarg_0_dout <= ap_fifo_iarg_dout(C_AP_IARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_fifo_iarg_1_dout <= ap_fifo_iarg_dout(C_AP_IARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_fifo_iarg_2_dout <= ap_fifo_iarg_dout(C_AP_IARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_fifo_iarg_3_dout <= ap_fifo_iarg_dout(C_AP_IARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_fifo_iarg_4_dout <= ap_fifo_iarg_dout(C_AP_IARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_fifo_iarg_5_dout <= ap_fifo_iarg_dout(C_AP_IARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_fifo_iarg_6_dout <= ap_fifo_iarg_dout(C_AP_IARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_fifo_iarg_7_dout <= ap_fifo_iarg_dout(C_AP_IARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Input Argument FIFO interface read generation
ap_fifo_iarg_read(0) <= ap_fifo_iarg_0_read;
ap_fifo_iarg_read(1) <= ap_fifo_iarg_1_read;
ap_fifo_iarg_read(2) <= ap_fifo_iarg_2_read;
ap_fifo_iarg_read(3) <= ap_fifo_iarg_3_read;
ap_fifo_iarg_read(4) <= ap_fifo_iarg_4_read;
ap_fifo_iarg_read(5) <= ap_fifo_iarg_5_read;
ap_fifo_iarg_read(6) <= ap_fifo_iarg_6_read;
ap_fifo_iarg_read(7) <= ap_fifo_iarg_7_read;
-- Input Argument FIFO interface empty generation
ap_fifo_iarg_0_empty_n <= ap_fifo_iarg_empty_n(0);
ap_fifo_iarg_1_empty_n <= ap_fifo_iarg_empty_n(1);
ap_fifo_iarg_2_empty_n <= ap_fifo_iarg_empty_n(2);
ap_fifo_iarg_3_empty_n <= ap_fifo_iarg_empty_n(3);
ap_fifo_iarg_4_empty_n <= ap_fifo_iarg_empty_n(4);
ap_fifo_iarg_5_empty_n <= ap_fifo_iarg_empty_n(5);
ap_fifo_iarg_6_empty_n <= ap_fifo_iarg_empty_n(6);
ap_fifo_iarg_7_empty_n <= ap_fifo_iarg_empty_n(7);
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- SUPERBUSES BUILDING: MASTER AXI STREAMS (OUTPUT ARGUMENTS):
-- NOTE FOR SIMULATION: This concatenation inserts a delta delay for clocks signals. In
-- the case of input signals causality is preserved becouse another delta delay is
-- inserted during their concatenation. For input signals, there is no problem
-----------------------------------------------------------------------------------------
--AXI4-Stream master interface TVALID generation
m_axis_0_tvalid <= m_axis_tvalid(0);
m_axis_1_tvalid <= m_axis_tvalid(1);
m_axis_2_tvalid <= m_axis_tvalid(2);
m_axis_3_tvalid <= m_axis_tvalid(3);
m_axis_4_tvalid <= m_axis_tvalid(4);
m_axis_5_tvalid <= m_axis_tvalid(5);
m_axis_6_tvalid <= m_axis_tvalid(6);
m_axis_7_tvalid <= m_axis_tvalid(7);
--AXI4-Stream master interface TREADY generation
m_axis_tready(0) <= m_axis_0_tready;
m_axis_tready(1) <= m_axis_1_tready;
m_axis_tready(2) <= m_axis_2_tready;
m_axis_tready(3) <= m_axis_3_tready;
m_axis_tready(4) <= m_axis_4_tready;
m_axis_tready(5) <= m_axis_5_tready;
m_axis_tready(6) <= m_axis_6_tready;
m_axis_tready(7) <= m_axis_7_tready;
--AXI4-Stream master interface TDATA generation
m_axis_0_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(0+1)-1 downto C_M_AXIS_TDATA_WIDTH*0);
m_axis_1_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(1+1)-1 downto C_M_AXIS_TDATA_WIDTH*1);
m_axis_2_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(2+1)-1 downto C_M_AXIS_TDATA_WIDTH*2);
m_axis_3_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(3+1)-1 downto C_M_AXIS_TDATA_WIDTH*3);
m_axis_4_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(4+1)-1 downto C_M_AXIS_TDATA_WIDTH*4);
m_axis_5_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(5+1)-1 downto C_M_AXIS_TDATA_WIDTH*5);
m_axis_6_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(6+1)-1 downto C_M_AXIS_TDATA_WIDTH*6);
m_axis_7_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(7+1)-1 downto C_M_AXIS_TDATA_WIDTH*7);
--AXI4-Stream master interface TSTRB generation
m_axis_0_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(0+1)-1 downto C_M_AXIS_TSTRB_WIDTH*0);
m_axis_1_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(1+1)-1 downto C_M_AXIS_TSTRB_WIDTH*1);
m_axis_2_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(2+1)-1 downto C_M_AXIS_TSTRB_WIDTH*2);
m_axis_3_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(3+1)-1 downto C_M_AXIS_TSTRB_WIDTH*3);
m_axis_4_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(4+1)-1 downto C_M_AXIS_TSTRB_WIDTH*4);
m_axis_5_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(5+1)-1 downto C_M_AXIS_TSTRB_WIDTH*5);
m_axis_6_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(6+1)-1 downto C_M_AXIS_TSTRB_WIDTH*6);
m_axis_7_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(7+1)-1 downto C_M_AXIS_TSTRB_WIDTH*7);
--AXI4-Stream master interface TKEEP generation
m_axis_0_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(0+1)-1 downto C_M_AXIS_TKEEP_WIDTH*0);
m_axis_1_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(1+1)-1 downto C_M_AXIS_TKEEP_WIDTH*1);
m_axis_2_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(2+1)-1 downto C_M_AXIS_TKEEP_WIDTH*2);
m_axis_3_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(3+1)-1 downto C_M_AXIS_TKEEP_WIDTH*3);
m_axis_4_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(4+1)-1 downto C_M_AXIS_TKEEP_WIDTH*4);
m_axis_5_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(5+1)-1 downto C_M_AXIS_TKEEP_WIDTH*5);
m_axis_6_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(6+1)-1 downto C_M_AXIS_TKEEP_WIDTH*6);
m_axis_7_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(7+1)-1 downto C_M_AXIS_TKEEP_WIDTH*7);
--AXI4-Stream master interface TLAST generation
m_axis_0_tlast <= m_axis_tlast(0);
m_axis_1_tlast <= m_axis_tlast(1);
m_axis_2_tlast <= m_axis_tlast(2);
m_axis_3_tlast <= m_axis_tlast(3);
m_axis_4_tlast <= m_axis_tlast(4);
m_axis_5_tlast <= m_axis_tlast(5);
m_axis_6_tlast <= m_axis_tlast(6);
m_axis_7_tlast <= m_axis_tlast(7);
--AXI4-Stream master interface TID generation
m_axis_0_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(0+1)-1 downto C_M_AXIS_TID_WIDTH*0);
m_axis_1_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(1+1)-1 downto C_M_AXIS_TID_WIDTH*1);
m_axis_2_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(2+1)-1 downto C_M_AXIS_TID_WIDTH*2);
m_axis_3_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(3+1)-1 downto C_M_AXIS_TID_WIDTH*3);
m_axis_4_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(4+1)-1 downto C_M_AXIS_TID_WIDTH*4);
m_axis_5_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(5+1)-1 downto C_M_AXIS_TID_WIDTH*5);
m_axis_6_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(6+1)-1 downto C_M_AXIS_TID_WIDTH*6);
m_axis_7_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(7+1)-1 downto C_M_AXIS_TID_WIDTH*7);
--AXI4-Stream master interface TDEST generation
m_axis_0_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(0+1)-1 downto C_M_AXIS_TDEST_WIDTH*0);
m_axis_1_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(1+1)-1 downto C_M_AXIS_TDEST_WIDTH*1);
m_axis_2_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(2+1)-1 downto C_M_AXIS_TDEST_WIDTH*2);
m_axis_3_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(3+1)-1 downto C_M_AXIS_TDEST_WIDTH*3);
m_axis_4_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(4+1)-1 downto C_M_AXIS_TDEST_WIDTH*4);
m_axis_5_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(5+1)-1 downto C_M_AXIS_TDEST_WIDTH*5);
m_axis_6_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(6+1)-1 downto C_M_AXIS_TDEST_WIDTH*6);
m_axis_7_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(7+1)-1 downto C_M_AXIS_TDEST_WIDTH*7);
--AXI4-Stream master interface TKEEP generation
m_axis_0_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(0+1)-1 downto C_M_AXIS_TUSER_WIDTH*0);
m_axis_1_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(1+1)-1 downto C_M_AXIS_TUSER_WIDTH*1);
m_axis_2_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(2+1)-1 downto C_M_AXIS_TUSER_WIDTH*2);
m_axis_3_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(3+1)-1 downto C_M_AXIS_TUSER_WIDTH*3);
m_axis_4_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(4+1)-1 downto C_M_AXIS_TUSER_WIDTH*4);
m_axis_5_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(5+1)-1 downto C_M_AXIS_TUSER_WIDTH*5);
m_axis_6_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(6+1)-1 downto C_M_AXIS_TUSER_WIDTH*6);
m_axis_7_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(7+1)-1 downto C_M_AXIS_TUSER_WIDTH*7);
-----------------------------------------------------------------------------------------
-- Accelerator Output Argument interface signal Generation
-- SUPERBUSES BUILDING: AP Output ARGUMENTS:
-----------------------------------------------------------------------------------------
-- Output Argument BRAM interface addr generation
ap_oarg_addr(C_MAX_ARG_AWIDTH*(0+1)-1 downto C_MAX_ARG_AWIDTH*0) <= ap_oarg_0_addr(C_MAX_ARG_AWIDTH+AP_OARG_0_OFFSET-1 downto AP_OARG_0_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(1+1)-1 downto C_MAX_ARG_AWIDTH*1) <= ap_oarg_1_addr(C_MAX_ARG_AWIDTH+AP_OARG_1_OFFSET-1 downto AP_OARG_1_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(2+1)-1 downto C_MAX_ARG_AWIDTH*2) <= ap_oarg_2_addr(C_MAX_ARG_AWIDTH+AP_OARG_2_OFFSET-1 downto AP_OARG_2_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(3+1)-1 downto C_MAX_ARG_AWIDTH*3) <= ap_oarg_3_addr(C_MAX_ARG_AWIDTH+AP_OARG_3_OFFSET-1 downto AP_OARG_3_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(4+1)-1 downto C_MAX_ARG_AWIDTH*4) <= ap_oarg_4_addr(C_MAX_ARG_AWIDTH+AP_OARG_4_OFFSET-1 downto AP_OARG_4_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(5+1)-1 downto C_MAX_ARG_AWIDTH*5) <= ap_oarg_5_addr(C_MAX_ARG_AWIDTH+AP_OARG_5_OFFSET-1 downto AP_OARG_5_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(6+1)-1 downto C_MAX_ARG_AWIDTH*6) <= ap_oarg_6_addr(C_MAX_ARG_AWIDTH+AP_OARG_6_OFFSET-1 downto AP_OARG_6_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(7+1)-1 downto C_MAX_ARG_AWIDTH*7) <= ap_oarg_7_addr(C_MAX_ARG_AWIDTH+AP_OARG_7_OFFSET-1 downto AP_OARG_7_OFFSET);
-- Output Argument BRAM interface ce generation
ap_oarg_ce(0) <= ap_oarg_0_ce;
ap_oarg_ce(1) <= ap_oarg_1_ce;
ap_oarg_ce(2) <= ap_oarg_2_ce;
ap_oarg_ce(3) <= ap_oarg_3_ce;
ap_oarg_ce(4) <= ap_oarg_4_ce;
ap_oarg_ce(5) <= ap_oarg_5_ce;
ap_oarg_ce(6) <= ap_oarg_6_ce;
ap_oarg_ce(7) <= ap_oarg_7_ce;
-- Output Argument BRAM interface we generation
ap_oarg_we(0) <= ap_oarg_0_we(0);
ap_oarg_we(1) <= ap_oarg_1_we(0);
ap_oarg_we(2) <= ap_oarg_2_we(0);
ap_oarg_we(3) <= ap_oarg_3_we(0);
ap_oarg_we(4) <= ap_oarg_4_we(0);
ap_oarg_we(5) <= ap_oarg_5_we(0);
ap_oarg_we(6) <= ap_oarg_6_we(0);
ap_oarg_we(7) <= ap_oarg_7_we(0);
-- Output Argument BRAM interface din generation
ap_oarg_din(C_MAX_ARG_DWIDTH*(0+1)-1 downto C_MAX_ARG_DWIDTH*0) <= ext_lv(ap_oarg_0_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(1+1)-1 downto C_MAX_ARG_DWIDTH*1) <= ext_lv(ap_oarg_1_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(2+1)-1 downto C_MAX_ARG_DWIDTH*2) <= ext_lv(ap_oarg_2_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(3+1)-1 downto C_MAX_ARG_DWIDTH*3) <= ext_lv(ap_oarg_3_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(4+1)-1 downto C_MAX_ARG_DWIDTH*4) <= ext_lv(ap_oarg_4_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(5+1)-1 downto C_MAX_ARG_DWIDTH*5) <= ext_lv(ap_oarg_5_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(6+1)-1 downto C_MAX_ARG_DWIDTH*6) <= ext_lv(ap_oarg_6_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(7+1)-1 downto C_MAX_ARG_DWIDTH*7) <= ext_lv(ap_oarg_7_din, C_MAX_ARG_DWIDTH);
-- Output Argument BRAM interface dout generation
ap_oarg_0_dout <= ap_oarg_dout(C_AP_OARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_oarg_1_dout <= ap_oarg_dout(C_AP_OARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_oarg_2_dout <= ap_oarg_dout(C_AP_OARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_oarg_3_dout <= ap_oarg_dout(C_AP_OARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_oarg_4_dout <= ap_oarg_dout(C_AP_OARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_oarg_5_dout <= ap_oarg_dout(C_AP_OARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_oarg_6_dout <= ap_oarg_dout(C_AP_OARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_oarg_7_dout <= ap_oarg_dout(C_AP_OARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Output Argument FIFO interface din generation
ap_fifo_oarg_din(C_AP_OARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0) <= ap_fifo_oarg_0_din;
ap_fifo_oarg_din(C_AP_OARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1) <= ap_fifo_oarg_1_din;
ap_fifo_oarg_din(C_AP_OARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2) <= ap_fifo_oarg_2_din;
ap_fifo_oarg_din(C_AP_OARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3) <= ap_fifo_oarg_3_din;
ap_fifo_oarg_din(C_AP_OARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4) <= ap_fifo_oarg_4_din;
ap_fifo_oarg_din(C_AP_OARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5) <= ap_fifo_oarg_5_din;
ap_fifo_oarg_din(C_AP_OARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6) <= ap_fifo_oarg_6_din;
ap_fifo_oarg_din(C_AP_OARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7) <= ap_fifo_oarg_7_din;
-- Assining unused bits in the vector to default value to reduce synthesis warnings.
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_AP_OARG_0_DWIDTH+C_MAX_ARG_DWIDTH*0) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_AP_OARG_1_DWIDTH+C_MAX_ARG_DWIDTH*1) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_AP_OARG_2_DWIDTH+C_MAX_ARG_DWIDTH*2) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_AP_OARG_3_DWIDTH+C_MAX_ARG_DWIDTH*3) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_AP_OARG_4_DWIDTH+C_MAX_ARG_DWIDTH*4) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_AP_OARG_5_DWIDTH+C_MAX_ARG_DWIDTH*5) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_AP_OARG_6_DWIDTH+C_MAX_ARG_DWIDTH*6) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_AP_OARG_7_DWIDTH+C_MAX_ARG_DWIDTH*7) <= (others => '0');
-- Output Argument FIFO interface fifo_write generation
ap_fifo_oarg_write(0) <= ap_fifo_oarg_0_write;
ap_fifo_oarg_write(1) <= ap_fifo_oarg_1_write;
ap_fifo_oarg_write(2) <= ap_fifo_oarg_2_write;
ap_fifo_oarg_write(3) <= ap_fifo_oarg_3_write;
ap_fifo_oarg_write(4) <= ap_fifo_oarg_4_write;
ap_fifo_oarg_write(5) <= ap_fifo_oarg_5_write;
ap_fifo_oarg_write(6) <= ap_fifo_oarg_6_write;
ap_fifo_oarg_write(7) <= ap_fifo_oarg_7_write;
-- Output Argument FIFO interface fifo_full generation
ap_fifo_oarg_0_full_n <= ap_fifo_oarg_full_n(0);
ap_fifo_oarg_1_full_n <= ap_fifo_oarg_full_n(1);
ap_fifo_oarg_2_full_n <= ap_fifo_oarg_full_n(2);
ap_fifo_oarg_3_full_n <= ap_fifo_oarg_full_n(3);
ap_fifo_oarg_4_full_n <= ap_fifo_oarg_full_n(4);
ap_fifo_oarg_5_full_n <= ap_fifo_oarg_full_n(5);
ap_fifo_oarg_6_full_n <= ap_fifo_oarg_full_n(6);
ap_fifo_oarg_7_full_n <= ap_fifo_oarg_full_n(7);
--------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
-- XD_ADAPTER_CORE_I : Adapter core logic
-----------------------------------------------------------------------------------------
XD_ADAPTER_CORE_I : entity axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter_core
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => BRAM_PRIMITIVE_TYPE,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MTBF_STAGES => C_MTBF_STAGES,
--
C_AP_ADAPTER_ID => C_AP_ADAPTER_ID,
C_MAX_SCALAR_DWIDTH => C_MAX_SCALAR_DWIDTH,
C_MAX_ARG_DWIDTH => C_MAX_ARG_DWIDTH,
C_MAX_ARG_AWIDTH => C_MAX_ARG_AWIDTH,
C_MAX_ARG_N_DIM => C_MAX_ARG_N_DIM,
C_MAX_MB_DEPTH => C_MAX_MB_DEPTH,
C_MAX_N_IARGS => C_MAX_N_IARGS,
C_MAX_N_OARGS => C_MAX_N_OARGS,
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS,
C_MAX_N_IOSCALARS => C_MAX_N_IOSCALARS,
--
C_N_INPUT_ARGS => C_N_INPUT_ARGS,
C_N_OUTPUT_ARGS => C_N_OUTPUT_ARGS,
--
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_TUSER_WIDTH,
C_S_AXIS_TID_WIDTH => C_S_AXIS_TID_WIDTH,
C_S_AXIS_TDEST_WIDTH => C_S_AXIS_TDEST_WIDTH,
--
C_AP_IARG_TYPE => C_AP_IARG_TYPE,
C_AP_IARG_DWIDTH => C_AP_IARG_DWIDTH,
C_AP_IARG_MB_DEPTH => C_AP_IARG_MB_DEPTH,
--
C_AP_IARG_WIDTH => C_AP_IARG_WIDTH,
C_AP_IARG_N_DIM => C_AP_IARG_N_DIM,
C_AP_IARG_DIM_1 => C_AP_IARG_DIM_1,
C_AP_IARG_DIM_2 => C_AP_IARG_DIM_2,
C_AP_IARG_FORMAT_TYPE => C_AP_IARG_FORMAT_TYPE,
C_AP_IARG_FORMAT_FACTOR => C_AP_IARG_FORMAT_FACTOR,
C_AP_IARG_FORMAT_DIM => C_AP_IARG_FORMAT_DIM,
--
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
--
C_AP_OARG_TYPE => C_AP_OARG_TYPE,
C_AP_OARG_DWIDTH => C_AP_OARG_DWIDTH,
C_AP_OARG_MB_DEPTH => C_AP_OARG_MB_DEPTH,
--
C_AP_OARG_WIDTH => C_AP_OARG_WIDTH,
C_AP_OARG_N_DIM => C_AP_OARG_N_DIM,
C_AP_OARG_DIM => C_AP_OARG_DIM,
C_AP_OARG_DIM_1 => C_AP_OARG_DIM_1,
C_AP_OARG_DIM_2 => C_AP_OARG_DIM_2,
C_AP_OARG_FORMAT_TYPE => C_AP_OARG_FORMAT_TYPE,
C_AP_OARG_FORMAT_FACTOR => C_AP_OARG_FORMAT_FACTOR,
C_AP_OARG_FORMAT_DIM => C_AP_OARG_FORMAT_DIM,
--
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_INPUT_SCALAR_DWIDTH => C_INPUT_SCALAR_DWIDTH,
C_AP_ISCALAR_DOUT_WIDTH => C_AP_ISCALAR_DOUT_WIDTH,
C_INPUT_SCALAR_MODE => C_INPUT_SCALAR_MODE,
--
C_OUTPUT_SCALAR_MODE => C_OUTPUT_SCALAR_MODE,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS,
C_OUTPUT_SCALAR_DWIDTH => C_OUTPUT_SCALAR_DWIDTH,
C_AP_OSCALAR_DIN_WIDTH => C_AP_OSCALAR_DIN_WIDTH,
C_AP_ISCALAR_IO_DOUT_WIDTH => C_AP_ISCALAR_IO_DOUT_WIDTH,
C_AP_OSCALAR_IO_DIN_WIDTH => C_AP_OSCALAR_IO_DIN_WIDTH)
port map (
-- SLAVE AXI LITE:
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
--- Slave AXI streams (input arguments)
s_axis_aclk => s_axis_aclk_i,
s_axis_aresetn => s_axis_aresetn_i,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => s_axis_tstrb,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => s_axis_tid,
s_axis_tdest => s_axis_tdest,
s_axis_tuser => s_axis_tuser,
--- AP input arguments
ap_iarg_addr => ap_iarg_addr,
ap_iarg_ce => ap_iarg_ce,
ap_iarg_we => ap_iarg_we,
ap_iarg_din => ap_iarg_din,
ap_iarg_dout => ap_iarg_dout,
---
ap_fifo_iarg_dout => ap_fifo_iarg_dout,
ap_fifo_iarg_read => ap_fifo_iarg_read,
ap_fifo_iarg_empty_n => ap_fifo_iarg_empty_n,
--- Master AXI streams (output arguments)
m_axis_aclk => m_axis_aclk_i,
m_axis_aresetn => m_axis_aresetn_i,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tstrb => m_axis_tstrb,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tid => m_axis_tid,
m_axis_tdest => m_axis_tdest,
m_axis_tuser => m_axis_tuser,
--- AP output arguments
ap_oarg_addr => ap_oarg_addr,
ap_oarg_ce => ap_oarg_ce,
ap_oarg_we => ap_oarg_we,
ap_oarg_din => ap_oarg_din,
ap_oarg_dout => ap_oarg_dout,
---
ap_fifo_oarg_din => ap_fifo_oarg_din,
ap_fifo_oarg_write => ap_fifo_oarg_write,
ap_fifo_oarg_full_n => ap_fifo_oarg_full_n,
---
ap_clk => aclk,
ap_rst => aresetn,
-- AP control handshaking:
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
---
ap_iscalar_dout => ap_iscalar_dout_i,
ap_oscalar_din => ap_oscalar_din_i,
ap_oscalar_vld => ap_oscalar_vld_i,
ap_oscalar_ack => ap_oscalar_ack_i,
ap_iscalar_vld => ap_iscalar_vld_i,
ap_iscalar_ack => ap_iscalar_ack_i,
---
interrupt => interrupt);
end rtl;
|
mit
|
bff3b9ee0624f9320d3a57ce5b0fd84a
| 0.587812 | 2.82496 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare5.vhd
| 1 | 4,450 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare5.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare5 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare5;
ARCHITECTURE SYN OF lpm_compare5 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "0000101011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "43"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 43 0 0 10 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
de12479cebf060d21a2702893860cb88
| 0.65618 | 3.702163 | false | false | false | false |
mitchsm/nvc
|
test/regress/concat5.vhd
| 5 | 631 |
entity concat5 is
end entity;
architecture test of concat5 is
function count_as(x : string) return integer is
variable r : integer := 0;
begin
for i in 1 to x'length loop
if x(i) = 'a' then
r := r + 1;
end if;
end loop;
return r;
end function;
begin
process is
variable x : string(1 to 3) := "aba";
begin
assert count_as(x & "baa") = 4;
assert count_as("baa" & x) = 4;
assert count_as("baa" & 'a') = 3;
assert count_as(('b', 'a', 'a') & x) = 4;
wait;
end process;
end architecture;
|
gpl-3.0
|
c76f04166feb3a4a6c70c081b481f23f
| 0.497623 | 3.486188 | false | false | false | false |
mitchsm/nvc
|
test/regress/signal4.vhd
| 5 | 728 |
entity signal4 is
end entity;
architecture test of signal4 is
signal s : bit_vector(3 downto 0) := (1 => '1', others => '0');
begin
process is
variable v : bit_vector(3 downto 0) := (others => '1');
begin
assert s(0) = '0';
assert s(1) = '1';
assert v(1) = '1';
v(2) := s(3);
assert v(2) = '0';
s(0) <= v(3);
assert s(0) = '0';
wait for 1 ns;
assert v(3) = '1';
assert s(0) = v(3);
assert v = ( '1', '0', '1', '1' );
s <= v;
assert s = ( '0', '0', '1', '1' ) report "one";
wait for 1 ns;
assert s = ( '1', '0', '1', '1' ) report "two";
wait;
end process;
end architecture;
|
gpl-3.0
|
978bb59b1c56557305f352418a6a3ef4
| 0.425824 | 2.923695 | false | false | false | false |
mitchsm/nvc
|
test/regress/shared1.vhd
| 5 | 750 |
package p is
shared variable pglobal : integer := 2;
end package;
-------------------------------------------------------------------------------
entity shared1 is
end entity;
use work.p.all;
architecture test of shared1 is
shared variable global : integer := 5;
procedure check_it(constant expect : in integer) is
begin
assert global = expect;
end procedure;
procedure set_it(constant set : in integer) is
begin
global := set;
end procedure;
begin
process is
begin
assert global = 5;
global := 6;
check_it(6);
set_it(7);
assert global = 7;
assert pglobal = 2;
pglobal := 51;
wait;
end process;
end architecture;
|
gpl-3.0
|
d2b7b2d8622247fba4b689b761710569
| 0.526667 | 4.385965 | false | false | false | false |
mitchsm/nvc
|
test/lower/choice1.vhd
| 2 | 390 |
entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when others =>
x := 5;
end case;
wait;
end process;
end architecture;
|
gpl-3.0
|
3ae23ac4a2f83e18472dd2ae86c51114
| 0.441026 | 4.382022 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue163.vhd
| 5 | 1,281 |
package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
9b1a25bf2a0d8991410d887946b96f10
| 0.58548 | 3.745614 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/async_fifo_dist_wt.vhd
| 1 | 9,838 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : async_fifo_dist_wt.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity async_fifo_dist_wt is
generic (
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
DEPTH : integer := 31;
WIDTH : integer := 16);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_clk : in std_logic;
wr_rst : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic);
end async_fifo_dist_wt;
architecture rtl of async_fifo_dist_wt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH);
constant ADDR_BITS : integer := log2(FIFO_DEPTH);
signal rd_addr : unsigned(ADDR_BITS-1 downto 0);
signal wr_addr : unsigned(ADDR_BITS-1 downto 0);
-- Following signals have gray values
signal wr_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal din_rdy_i : std_logic;
signal empty_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "distributed";
signal mem_dout : std_logic_vector(WIDTH-1 downto 0);
begin
---------------------------------------------------------
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
-- From all gray signals, only next_rd_cnt and next_wr_cnt are counters. all
-- the rest are registers. It's simpler to use a binary counter and then use
-- a table to transfor to gray. Given that the address counter is initialized
-- to zero, signal next_XX_cnt will load code gray(0) after first increment.
-- Hence, it should be initialized to gray(N-1). that is, the initial values
-- will be:
-- * next_XX_cnt = gray(N-1)
-- * XX_cnt = gray(N-2)
-- * prev_XX_cnt = gray(N-3)
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
next_rd_cnt <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
rd_cnt <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
prev_rd_cnt <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_cnt <= rd_cnt;
rd_cnt <= next_rd_cnt;
next_rd_cnt <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
next_wr_cnt <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
wr_cnt <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_cnt <= next_wr_cnt;
next_wr_cnt <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
-----------------------------------------------------------------
-- Flag FULL:
-- 1.- move to full condition (not din_rdy) when there is an efective
-- write next_wr_cnt = prev_rd_cnt
-- 2.- stay in full condition (not din_rdy) while this condition is true:
-- next_wr_cnt = rd_cnt
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if((not(din_rdy_i) or fifo_we) = '1') then
if(din_rdy_i = '1') then
if (next_wr_cnt = prev_rd_cnt) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
else
if (wr_cnt = prev_rd_cnt) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
-- Flag EMPTY:
-- 1.- move to empty condition when there is read (next_rd_cnt = wr_cnt)
-- 2.- stay in empty condition while the two pointers are the same (wr_cnt = rd_cnt)
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if((empty_i or fifo_re) = '1') then
if(empty_i = '0') then
if(next_rd_cnt = wr_cnt) then
empty_i <= '1';
else
empty_i <= '0';
end if;
else
if(rd_cnt = wr_cnt) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
-----------------------------------------------------------------------
-- memory modeling (XST to infer)
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
end rtl;
|
mit
|
bba57c42b426e804cf7d07b5dd72bbb3
| 0.556922 | 3.645054 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue185.vhd
| 5 | 1,259 |
entity issue185 is
end entity;
architecture a of issue185 is
type record_t is record
field : natural;
end record;
procedure proc_rec(constant value : in record_t := (field => 0)) is
begin
report integer'image(value.field);
wait for 0 ns;
report integer'image(value.field);
end procedure;
procedure proc_integer(constant value : in integer := 0) is
begin
report integer'image(value);
wait for 0 ns;
report integer'image(value);
end procedure;
procedure proc_string(constant value : in string := "hello") is
begin
report value;
wait for 0 ns;
report value;
end procedure;
procedure proc_bit_vector(constant value : in bit_vector := "0") is
begin
report bit'image(value(0));
wait for 0 ns;
report bit'image(value(0));
end procedure;
begin
main : process
begin
report "record parameter does not work";
proc_rec;
proc_rec(value => (field => 1));
report "integer parameter works";
proc_integer;
proc_integer(value => 1);
report "string parameter works";
proc_string;
proc_string(value => "foobar");
report "bit_vector parameter works";
proc_bit_vector;
proc_bit_vector(value => "1");
wait;
end process;
end architecture;
|
gpl-3.0
|
8eb6494f06d9837300c3d1cb3893c33d
| 0.658459 | 3.780781 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_eb_e-rtl-a.vhd
| 1 | 4,367 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:24 wig Exp $
-- $Date: 2004/04/06 10:50:24 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:24 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eba_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eba_e
mbist_aci_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_vcd_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_eba_e
);
end component;
-- ---------
component inst_ebb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebb_e
mbist_sum_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
req_select_o : out std_ulogic_vector(5 downto 0);
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_ebb_e
);
end component;
-- ---------
component inst_ebc_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
port (
-- Generated Port for Entity inst_ebc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ebc_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
p_mix_tmi_sbist_fail_12_10_go(2 downto 0) <= tmi_sbist_fail(12 downto 10); -- __I_O_SLICE_PORT
p_mix_v_select_5_0_go <= v_select; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
port map (
mbist_aci_fail_o => tmi_sbist_fail(10),
mbist_vcd_fail_o => tmi_sbist_fail(11),
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
port map (
mbist_sum_fail_o => tmi_sbist_fail(12),
req_select_o => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
4fccad42f66b60e1f45d4e1c282df5a5
| 0.633845 | 3.123748 | false | false | false | false |
blutsvente/MIX
|
Resources/Examples/a_clk_20030129/a_clk-a.vhd
| 1 | 24,544 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for __COMMON__ of __COMMON__
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 10:43:20 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl a_clk.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Revision: 1.3 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of A_CLK
--
architecture rtl of A_CLK is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component PADS
-- No Generated Generics
port (
-- Generated Port for Entity PADS
p_mix_pad_conn_1_2_go : out std_ulogic;
p_mix_pad_conn_2_3_go : out std_ulogic;
p_mix_pad_conn_3_4_go : out std_ulogic;
p_mix_pad_conn_4_5_go : out std_ulogic;
p_mix_pad_conn_5_6_go : out std_ulogic;
p_mix_pad_conn_6_7_go : out std_ulogic;
p_mix_pad_conn_7_8_go : out std_ulogic;
p_mix_pad_conn_8_9_go : out std_ulogic;
p_mix_pad_conn_9_10_go : out std_ulogic
-- End of Generated Port for Entity PADS
);
end component;
-- ---------
component a_fsm
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
alarm_in_u : in std_ulogic;
clk : in std_ulogic;
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic;
wire_high_bit : in std_ulogic; -- Wire bit to high
wire_high_bus : in std_ulogic_vector(3 downto 0); -- Ground wire_low port
wire_low_bus : in std_ulogic_vector(3 downto 0) -- Ground wire_low port
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component alreg
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic -- The Reset
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4
-- No Generated Generics
port (
-- Generated Port for Entity count4
clk : in std_ulogic;
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic;
reset : in std_ulogic -- The Reset
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
display_ls_hr : out std_ulogic_vector(6 downto 0);
display_ls_min : out std_ulogic_vector(6 downto 0);
display_ms_hr : out std_ulogic_vector(6 downto 0);
display_ms_min : out std_ulogic_vector(6 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_sound_alarm_test1_go : out std_ulogic;
reset : in std_ulogic; -- The Reset
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad
-- No Generated Generics
port (
-- Generated Port for Entity keypad
clk : in std_ulogic;
columns : in std_ulogic_vector(2 downto 0);
reset : in std_ulogic; -- The Reset
rows : out std_ulogic_vector(3 downto 0) -- Keypad Output
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
clk : in std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
reset : in std_ulogic; -- The Reset
rows : in std_ulogic_vector(3 downto 0); -- Keypad Output
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen
-- No Generated Generics
port (
-- Generated Port for Entity timegen
clk : in std_ulogic;
one_minute : out std_ulogic;
one_second : out std_ulogic;
reset : in std_ulogic; -- The Reset
stopwatch : in std_ulogic -- Driven by reset
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_bus_1 : std_ulogic_vector(3 downto 0);
signal mix_logic0_bus_1 : std_ulogic_vector(3 downto 0);
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm_test1 : std_ulogic;
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_bus_1 <= ( others => '1' );
mix_logic0_bus_1 <= ( others => '0' );
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for PADS
PADS: PADS
port map (
p_mix_pad_conn_1_2_go => pad_conn_1_2,
p_mix_pad_conn_2_3_go => pad_conn_2_3,
p_mix_pad_conn_3_4_go => pad_conn_3_4,
p_mix_pad_conn_4_5_go => pad_conn_4_5,
p_mix_pad_conn_5_6_go => pad_conn_5_6,
p_mix_pad_conn_6_7_go => pad_conn_6_7,
p_mix_pad_conn_7_8_go => pad_conn_7_8,
p_mix_pad_conn_8_9_go => pad_conn_8_9,
p_mix_pad_conn_9_10_go => pad_conn_9_10
);
-- End of Generated Instance Port Map for PADS
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
alarm_in_u => sound_alarm_test1, -- Use internally test1
clk => clk, -- The ClockThe d_Clk (X4)
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset, -- The Reset (X10)
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button,
wire_high_bit => mix_logic1_0, -- Wire bit to high
wire_high_bus => mix_logic1_bus_1, -- Ground wire_low port
wire_low_bus => mix_logic0_bus_1 -- Ground wire_low port
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
clk => clk, -- The ClockThe d_Clk (X4)
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute,
reset => reset -- The Reset (X10)
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
clk => clk, -- The ClockThe d_Clk (X4)
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
display_ls_hr => display_ls_hr, -- Display storage buffer 2 ls_hr
display_ls_min => display_ls_min, -- Display storage buffer 0 ls_min
display_ms_hr => display_ms_hr, -- Display storage buffer 3 ms_hr
display_ms_min => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_sound_alarm_test1_go => sound_alarm_test1, -- Use internally test1
reset => reset, -- The Reset (X10)
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
sound_alarm => sound_alarm
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
clk => clk, -- The ClockThe d_Clk (X4)
columns => columns,
reset => reset, -- The Reset (X10)
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
clk => clk, -- The ClockThe d_Clk (X4)
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
reset => reset, -- The Reset (X10)
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
clk => clk, -- The ClockThe d_Clk (X4)
one_minute => one_minute,
one_second => one_sec_pulse,
reset => reset, -- The Reset (X10)
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
-- Start of Generated Architecture rtl of PADS
--
architecture rtl of PADS is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component padcell
-- No Generated Generics
port (
-- Generated Port for Entity padcell
EI : in std_ulogic;
EO : out std_ulogic
-- End of Generated Port for Entity padcell
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal pad_conn_1_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_2_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_3_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_4_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_5_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_6_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_7_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_8_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_conn_9_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
p_mix_pad_conn_1_2_go <= pad_conn_1_2; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_2_3_go <= pad_conn_2_3; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_3_4_go <= pad_conn_3_4; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_4_5_go <= pad_conn_4_5; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_5_6_go <= pad_conn_5_6; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_6_7_go <= pad_conn_6_7; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_7_8_go <= pad_conn_7_8; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_8_9_go <= pad_conn_8_9; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_pad_conn_9_10_go <= pad_conn_9_10; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for Pad_1
Pad_1: padcell
port map (
EI => mix_logic0_0, -- Ground EI of Pad1
EO => pad_conn_1_2
);
-- End of Generated Instance Port Map for Pad_1
-- Generated Instance Port Map for Pad_10
Pad_10: padcell
port map (
EI => pad_conn_9_10
);
-- End of Generated Instance Port Map for Pad_10
-- Generated Instance Port Map for Pad_2
Pad_2: padcell
port map (
EI => pad_conn_1_2,
EO => pad_conn_2_3
);
-- End of Generated Instance Port Map for Pad_2
-- Generated Instance Port Map for Pad_3
Pad_3: padcell
port map (
EI => pad_conn_2_3,
EO => pad_conn_3_4
);
-- End of Generated Instance Port Map for Pad_3
-- Generated Instance Port Map for Pad_4
Pad_4: padcell
port map (
EI => pad_conn_3_4,
EO => pad_conn_4_5
);
-- End of Generated Instance Port Map for Pad_4
-- Generated Instance Port Map for Pad_5
Pad_5: padcell
port map (
EI => pad_conn_4_5,
EO => pad_conn_5_6
);
-- End of Generated Instance Port Map for Pad_5
-- Generated Instance Port Map for Pad_6
Pad_6: padcell
port map (
EI => pad_conn_5_6,
EO => pad_conn_6_7
);
-- End of Generated Instance Port Map for Pad_6
-- Generated Instance Port Map for Pad_7
Pad_7: padcell
port map (
EI => pad_conn_6_7,
EO => pad_conn_7_8
);
-- End of Generated Instance Port Map for Pad_7
-- Generated Instance Port Map for Pad_8
Pad_8: padcell
port map (
EI => pad_conn_7_8,
EO => pad_conn_8_9
);
-- End of Generated Instance Port Map for Pad_8
-- Generated Instance Port Map for Pad_9
Pad_9: padcell
port map (
EI => pad_conn_8_9,
EO => pad_conn_9_10
);
-- End of Generated Instance Port Map for Pad_9
end rtl;
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ddrv
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_in : in std_ulogic; -- Use internally test1
alarm_time : in std_ulogic_vector(3 downto 0); -- Display storage buffer 1 ms_min
clk : in std_ulogic; -- The d_Clk
current_time : in std_ulogic_vector(3 downto 0); -- Display storage buffer 1 ms_min
display : out std_ulogic_vector(6 downto 0); -- Display storage buffer 1 ms_min
key_buffer : in std_ulogic_vector(3 downto 0); -- Display storage buffer 1 ms_min
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- Display storage buffer 1 ms_min __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f
-- No Generated Generics
port (
-- Generated Port for Entity and_f
clk : in std_ulogic;
mix_key_out : out std_ulogic;
out_2 : out std_ulogic; -- Use internally test1
reset : in std_ulogic; -- The Reset
y : in std_ulogic_vector(3 downto 0) -- Display storage buffer 3 ms_hr
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal sound_alarm_test1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_sound_alarm_test1_go <= sound_alarm_test1; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_in => sound_alarm_test1, -- Use internally test1
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
clk => clk, -- The ClockThe d_Clk (X4)
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
clk => clk, -- The ClockThe d_Clk (X4)
mix_key_out => sound_alarm,
out_2 => sound_alarm_test1, -- Use internally test1
reset => reset, -- The Reset (X10)
y(0) => alarm(0), -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
y(1) => alarm(0), -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
y(2) => alarm(0), -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
y(3) => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
4d5ddd4e2991d084cd011cd8b1712195
| 0.643171 | 2.736537 | false | false | false | false |
mitchsm/nvc
|
test/regress/case2.vhd
| 4 | 1,534 |
entity case2 is
end entity;
architecture test of case2 is
function toint4(b : bit_vector(3 downto 0)) return integer is
begin
case b is
when X"0" => return 0;
when X"1" => return 1;
when X"2" => return 2;
when X"3" => return 3;
when X"4" => return 4;
when X"5" => return 5;
when X"6" => return 6;
when X"7" => return 7;
when X"8" => return 8;
when X"9" => return 9;
when X"a" => return 10;
when X"b" => return 11;
when X"c" => return 12;
when X"d" => return 13;
when X"e" => return 14;
when X"f" => return 15;
end case;
end function;
function toint3(b : bit_vector(3 downto 0)) return integer is
begin
case b is
when X"0" => return 0;
when X"1" => return 1;
when X"2" => return 2;
when X"3" => return 3;
when X"4" => return 4;
when X"5" => return 5;
when X"6" => return 6;
when X"7" => return 7;
when others => return -1;
end case;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
begin
assert toint4(X"4") = 4;
b := X"a";
assert toint4(b) = 10;
assert toint4(X"f") = 15;
assert toint3(X"5") = 5;
assert toint3(X"c") = -1;
wait;
end process;
end architecture;
|
gpl-3.0
|
54d0618415cf667340138a80a326fd62
| 0.449153 | 3.592506 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_e_e-rtl-a.vhd
| 1 | 10,896 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:55 wig Exp $
-- $Date: 2004/04/06 10:49:55 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:55 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
egi_scani : in std_ulogic_vector(10 downto 0);
egi_scano : out std_ulogic_vector(10 downto 0);
p_mix_cp_laddr_31_1_gi : in std_ulogic_vector(30 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_gpio_int_4_0_go : out std_ulogic_vector(4 downto 0);
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_tmu_dac_reset_go : out std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eb_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0);
p_mix_v_select_5_0_go : out std_ulogic_vector(5 downto 0);
vclkl27 : in std_ulogic;
vio_scani : in std_ulogic_vector(30 downto 0);
vio_scano : out std_ulogic_vector(30 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end component;
-- ---------
component inst_ec_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ec_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_v_select_5_0_gi : in std_ulogic_vector(5 downto 0);
tpm_scani : in std_ulogic_vector(12 downto 0);
tpm_scano : out std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ec_e
);
end component;
-- ---------
component inst_ed_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ed_e
p_mix_acg_systime_init_30_0_gi : in std_ulogic_vector(30 downto 0);
p_mix_cgs_ramclk_go : out std_ulogic;
p_mix_gpio_int_2_0_gi : in std_ulogic_vector(2 downto 0);
p_mix_itm_scani_0_0_gi : in std_ulogic;
p_mix_nreset_go : out std_ulogic;
p_mix_nreset_s_go : out std_ulogic;
p_mix_tmi_scano_0_0_go : out std_ulogic;
p_mix_vclkl27_go : out std_ulogic
-- End of Generated Port for Entity inst_ed_e
);
end component;
-- ---------
component inst_ee_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ee_e
cgs_ramclk : in std_ulogic;
itm_scani : out std_ulogic_vector(70 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic;
si_vclkx2 : in std_ulogic;
tmi_sbist_fail : in std_ulogic_vector(12 downto 0);
tmi_scano : in std_ulogic_vector(70 downto 0)
-- End of Generated Port for Entity inst_ee_e
);
end component;
-- ---------
component inst_ef_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ef_e
cp_laddro : out std_ulogic_vector(31 downto 0);
cp_lcmd : out std_ulogic_vector(6 downto 0);
cpu_scani : in std_ulogic_vector(7 downto 0);
cpu_scano : out std_ulogic_vector(7 downto 0);
int23 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int24 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int25 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int26 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
int27 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nreset : in std_ulogic;
nreset_s : in std_ulogic;
tap_reset_n : in std_ulogic;
tap_reset_n_o : out std_ulogic
-- End of Generated Port for Entity inst_ef_e
);
end component;
-- ---------
component inst_eg_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eg_e
acg_systime_init : out std_ulogic_vector(30 downto 0);
adp_scani : in std_ulogic_vector(6 downto 0);
adp_scano : out std_ulogic_vector(6 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_eg_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0);
signal s_int_cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal cp_laddr : std_ulogic_vector(31 downto 0);
signal cp_lcmd : std_ulogic_vector(6 downto 0);
signal gpio_int : std_ulogic_vector(4 downto 0);
signal itm_scani : std_ulogic_vector(70 downto 0);
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic;
signal tap_reset_n_o : std_ulogic;
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0);
signal tmi_scano : std_ulogic_vector(70 downto 0);
signal v_select : std_ulogic_vector(5 downto 0);
signal s_int_vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
cgs_ramclk <= s_int_cgs_ramclk; -- __I_O_BIT_PORT
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
vclkl27 <= s_int_vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
egi_scani => itm_scani(31 downto 21),
egi_scano => tmi_scano(31 downto 21),
p_mix_cp_laddr_31_1_gi => cp_laddr(31 downto 1), -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
p_mix_cp_lcmd_6_6_gi => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
p_mix_gpio_int_4_0_go => gpio_int, -- GPIOWakeUPSignalsInterruptinputs
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_11_10_gi => tmi_sbist_fail(11 downto 10),
p_mix_tmi_sbist_fail_9_0_go => tmi_sbist_fail(9 downto 0),
p_mix_tmu_dac_reset_go => tmu_dac_reset, -- CADCTestModeRGBADAC
p_mix_v_select_2_2_gi => v_select(2), -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
p_mix_v_select_5_5_gi => v_select(5) -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_12_10_go => tmi_sbist_fail(12 downto 10),
p_mix_v_select_5_0_go => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
vclkl27 => s_int_vclkl27, -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
vio_scani => itm_scani(70 downto 40),
vio_scano => tmi_scano(70 downto 40)
);
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_v_select_5_0_gi => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
tpm_scani => itm_scani(20 downto 8),
tpm_scano => tmi_scano(20 downto 8)
);
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
port map (
p_mix_acg_systime_init_30_0_gi => acg_systime_init, -- ADPinterfaceScan
p_mix_cgs_ramclk_go => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
p_mix_gpio_int_2_0_gi => gpio_int(2 downto 0), -- GPIOWakeUPSignalsInterruptinputs
p_mix_itm_scani_0_0_gi => itm_scani(0),
p_mix_nreset_go => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_go => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_scano_0_0_go => tmi_scano(0),
p_mix_vclkl27_go => s_int_vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
port map (
cgs_ramclk => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
itm_scani => itm_scani,
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
si_vclkx2 => si_vclkx2, -- DigitalVideoPort
tmi_sbist_fail => tmi_sbist_fail,
tmi_scano => tmi_scano
);
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
port map (
cp_laddro => cp_laddr, -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
cp_lcmd => cp_lcmd, -- GuestBusLBC(memorymappedI/O)Interface
cpu_scani => itm_scani(39 downto 32),
cpu_scano => tmi_scano(39 downto 32),
int23 => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
int24 => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
int25 => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
int26 => gpio_int(3), -- GPIOWakeUPSignalsInterruptinputs
int27 => gpio_int(4), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
tap_reset_n => tap_reset_n_o, -- RESETports
tap_reset_n_o => tap_reset_n_o -- RESETports
);
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
adp_scani => itm_scani(7 downto 1),
adp_scano => tmi_scano(7 downto 1),
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
898c0fd0a1c8fc3f59e4b94095335ae8
| 0.661344 | 2.91805 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/pad_pads_e-rtl-a.vhd
| 1 | 14,556 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:52:30 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-rtl-a.vhd,v 1.4 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: pad_pads_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of pad_pads_e
--
architecture rtl of pad_pads_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component w_data3
-- No Generated Generics
port (
-- Generated Port for Entity w_data3
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data3
);
end component;
-- ---------
component w_data2
-- No Generated Generics
port (
-- Generated Port for Entity w_data2
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data2
);
end component;
-- ---------
component w_pad_i
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_i
di : out std_ulogic -- data in from pad
-- End of Generated Port for Entity w_pad_i
);
end component;
-- ---------
component w_pad_o
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_o
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_pad_o
);
end component;
-- ---------
component w_disp
-- No Generated Generics
port (
-- Generated Port for Entity w_disp
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_disp
);
end component;
-- ---------
component w_osc
-- No Generated Generics
port (
-- Generated Port for Entity w_osc
pd : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
xo : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_osc
);
end component;
-- ---------
component w_pad_dire
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dire
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dire
);
end component;
-- ---------
component w_pad_dir
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dir
di : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dir
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_1 : std_ulogic;
signal mix_logic0_0 : std_ulogic;
-- __I_NODRV_I signal clki2c : std_ulogic;
signal clki3c : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal pad_dir_di : std_ulogic;
-- __I_OUT_OPEN signal pad_dir_di38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_do38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_en38 : std_ulogic;
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_1 <= '1';
mix_logic0_0 <= '0';
p_mix_pad_di_1_go <= pad_di_1; -- __I_O_BIT_PORT
p_mix_pad_di_12_go <= pad_di_12; -- __I_O_BIT_PORT
p_mix_pad_di_13_go <= pad_di_13; -- __I_O_BIT_PORT
p_mix_pad_di_14_go <= pad_di_14; -- __I_O_BIT_PORT
p_mix_pad_di_15_go <= pad_di_15; -- __I_O_BIT_PORT
p_mix_pad_di_16_go <= pad_di_16; -- __I_O_BIT_PORT
p_mix_pad_di_17_go <= pad_di_17; -- __I_O_BIT_PORT
p_mix_pad_di_18_go <= pad_di_18; -- __I_O_BIT_PORT
p_mix_pad_di_31_go <= pad_di_31; -- __I_O_BIT_PORT
p_mix_pad_di_32_go <= pad_di_32; -- __I_O_BIT_PORT
p_mix_pad_di_33_go <= pad_di_33; -- __I_O_BIT_PORT
p_mix_pad_di_34_go <= pad_di_34; -- __I_O_BIT_PORT
p_mix_pad_di_39_go <= pad_di_39; -- __I_O_BIT_PORT
p_mix_pad_di_40_go <= pad_di_40; -- __I_O_BIT_PORT
pad_do_12 <= p_mix_pad_do_12_gi; -- __I_I_BIT_PORT
pad_do_13 <= p_mix_pad_do_13_gi; -- __I_I_BIT_PORT
pad_do_14 <= p_mix_pad_do_14_gi; -- __I_I_BIT_PORT
pad_do_15 <= p_mix_pad_do_15_gi; -- __I_I_BIT_PORT
pad_do_16 <= p_mix_pad_do_16_gi; -- __I_I_BIT_PORT
pad_do_17 <= p_mix_pad_do_17_gi; -- __I_I_BIT_PORT
pad_do_18 <= p_mix_pad_do_18_gi; -- __I_I_BIT_PORT
pad_do_2 <= p_mix_pad_do_2_gi; -- __I_I_BIT_PORT
pad_do_31 <= p_mix_pad_do_31_gi; -- __I_I_BIT_PORT
pad_do_32 <= p_mix_pad_do_32_gi; -- __I_I_BIT_PORT
pad_do_35 <= p_mix_pad_do_35_gi; -- __I_I_BIT_PORT
pad_do_36 <= p_mix_pad_do_36_gi; -- __I_I_BIT_PORT
pad_do_39 <= p_mix_pad_do_39_gi; -- __I_I_BIT_PORT
pad_do_40 <= p_mix_pad_do_40_gi; -- __I_I_BIT_PORT
pad_en_12 <= p_mix_pad_en_12_gi; -- __I_I_BIT_PORT
pad_en_13 <= p_mix_pad_en_13_gi; -- __I_I_BIT_PORT
pad_en_14 <= p_mix_pad_en_14_gi; -- __I_I_BIT_PORT
pad_en_15 <= p_mix_pad_en_15_gi; -- __I_I_BIT_PORT
pad_en_16 <= p_mix_pad_en_16_gi; -- __I_I_BIT_PORT
pad_en_17 <= p_mix_pad_en_17_gi; -- __I_I_BIT_PORT
pad_en_18 <= p_mix_pad_en_18_gi; -- __I_I_BIT_PORT
pad_en_2 <= p_mix_pad_en_2_gi; -- __I_I_BIT_PORT
pad_en_31 <= p_mix_pad_en_31_gi; -- __I_I_BIT_PORT
pad_en_32 <= p_mix_pad_en_32_gi; -- __I_I_BIT_PORT
pad_en_35 <= p_mix_pad_en_35_gi; -- __I_I_BIT_PORT
pad_en_36 <= p_mix_pad_en_36_gi; -- __I_I_BIT_PORT
pad_en_39 <= p_mix_pad_en_39_gi; -- __I_I_BIT_PORT
pad_en_40 <= p_mix_pad_en_40_gi; -- __I_I_BIT_PORT
pad_pu_31 <= p_mix_pad_pu_31_gi; -- __I_I_BIT_PORT
pad_pu_32 <= p_mix_pad_pu_32_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for data_10_pad
data_10_pad: w_data3
port map (
di => pad_di_32, -- data in from pad
do => pad_do_32, -- data out to pad
en => pad_en_32, -- pad output enable
pu => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for data_10_pad
-- Generated Instance Port Map for data_9_pad
data_9_pad: w_data2
port map (
di => pad_di_31, -- data in from pad
do => pad_do_31, -- data out to pad
en => pad_en_31, -- pad output enable
pu => pad_pu_31 -- pull-up control
);
-- End of Generated Instance Port Map for data_9_pad
-- Generated Instance Port Map for data_i1_pad
data_i1_pad: w_pad_i
port map (
di => pad_di_1 -- data in from pad
);
-- End of Generated Instance Port Map for data_i1_pad
-- Generated Instance Port Map for data_i33_pad
data_i33_pad: w_pad_i
port map (
di => pad_di_33 -- data in from pad
);
-- End of Generated Instance Port Map for data_i33_pad
-- Generated Instance Port Map for data_i34_pad
data_i34_pad: w_pad_i
port map (
di => pad_di_34 -- data in from pad
);
-- End of Generated Instance Port Map for data_i34_pad
-- Generated Instance Port Map for data_o1_pad
data_o1_pad: w_pad_o
port map (
do => pad_do_2, -- data out to pad
en => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for data_o1_pad
-- Generated Instance Port Map for data_o35_pad
data_o35_pad: w_pad_o
port map (
do => pad_do_35, -- data out to pad
en => pad_en_35 -- pad output enable
);
-- End of Generated Instance Port Map for data_o35_pad
-- Generated Instance Port Map for data_o36_pad
data_o36_pad: w_pad_o
port map (
do => pad_do_36, -- data out to pad
en => pad_en_36 -- pad output enable
);
-- End of Generated Instance Port Map for data_o36_pad
-- Generated Instance Port Map for disp_10_pad
disp_10_pad: w_disp
port map (
di => pad_di_40, -- data in from pad
do => pad_do_40, -- data out to pad
en => pad_en_40 -- pad output enable
);
-- End of Generated Instance Port Map for disp_10_pad
-- Generated Instance Port Map for disp_2_pad
disp_2_pad: w_disp
port map (
di => pad_di_12, -- data in from pad
do => pad_do_12, -- data out to pad
en => pad_en_12 -- pad output enable
);
-- End of Generated Instance Port Map for disp_2_pad
-- Generated Instance Port Map for disp_3_pad
disp_3_pad: w_disp
port map (
di => pad_di_13, -- data in from pad
do => pad_do_13, -- data out to pad
en => pad_en_13 -- pad output enable
);
-- End of Generated Instance Port Map for disp_3_pad
-- Generated Instance Port Map for disp_4_pad
disp_4_pad: w_disp
port map (
di => pad_di_14, -- data in from pad
do => pad_do_14, -- data out to pad
en => pad_en_14 -- pad output enable
);
-- End of Generated Instance Port Map for disp_4_pad
-- Generated Instance Port Map for disp_5_pad
disp_5_pad: w_disp
port map (
di => pad_di_15, -- data in from pad
do => pad_do_15, -- data out to pad
en => pad_en_15 -- pad output enable
);
-- End of Generated Instance Port Map for disp_5_pad
-- Generated Instance Port Map for disp_6_pad
disp_6_pad: w_disp
port map (
di => pad_di_16, -- data in from pad
do => pad_do_16, -- data out to pad
en => pad_en_16 -- pad output enable
);
-- End of Generated Instance Port Map for disp_6_pad
-- Generated Instance Port Map for disp_7_pad
disp_7_pad: w_disp
port map (
di => pad_di_17, -- data in from pad
do => pad_do_17, -- data out to pad
en => pad_en_17 -- pad output enable
);
-- End of Generated Instance Port Map for disp_7_pad
-- Generated Instance Port Map for disp_8_pad
disp_8_pad: w_disp
port map (
di => pad_di_18, -- data in from pad
do => pad_do_18, -- data out to pad
en => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for disp_8_pad
-- Generated Instance Port Map for disp_9_pad
disp_9_pad: w_disp
port map (
di => pad_di_39, -- data in from pad
do => pad_do_39, -- data out to pad
en => pad_en_39 -- pad output enable
);
-- End of Generated Instance Port Map for disp_9_pad
-- Generated Instance Port Map for osc_1_pad
osc_1_pad: w_osc
port map (
pd => mix_logic1_0,
-- __I_NODRV_I xo => __nodrv__/clki2c
);
-- End of Generated Instance Port Map for osc_1_pad
-- Generated Instance Port Map for osc_2_pad
osc_2_pad: w_osc
port map (
pd => mix_logic1_1,
xo => clki3c
);
-- End of Generated Instance Port Map for osc_2_pad
-- Generated Instance Port Map for osc_3_pad
osc_3_pad: w_osc
port map (
pd => mix_logic0_0,
xo => clki3c
);
-- End of Generated Instance Port Map for osc_3_pad
-- Generated Instance Port Map for pad_dire_pad
pad_dire_pad: w_pad_dire
port map (
di => open, -- __I_OUT_OPEN
-- __I_NODRV_I -- __I_NODRV_I do => __nodrv__/pad_dir_en38/pad_dir_do38,
-- __I_NODRV_I en => __nodrv__/pad_dir_en38
);
-- End of Generated Instance Port Map for pad_dire_pad
-- Generated Instance Port Map for pad_dirli_pad
pad_dirli_pad: w_pad_dir
port map (
di => open -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for pad_dirli_pad
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
fdd78af7b141ec0eca49bd9a3efee3b3
| 0.605867 | 2.474668 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/alu.vhd
| 2 | 2,336 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:42:01 11/19/2013
-- Design Name:
-- Module Name: alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
op : in STD_LOGIC_VECTOR(3 downto 0);
zf : out STD_LOGIC;
sf : out STD_LOGIC;
c : out STD_LOGIC_VECTOR(15 downto 0)
);
end alu;
architecture Behavioral of alu is
begin
process (a, b, op)
variable res : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
begin
case op is
when ALU_ADD =>
res := a + b;
when ALU_SUB =>
res := a - b;
when ALU_AND =>
res := a and b;
when ALU_OR =>
res := a or b;
when ALU_XOR =>
res := a xor b;
when ALU_NOT =>
res := not(a);
when ALU_SLL =>
res := to_stdlogicvector(to_bitvector(a) sll conv_integer(b));
when ALU_SRL =>
res := to_stdlogicvector(to_bitvector(a) srl conv_integer(b));
when ALU_SLA =>
res := to_stdlogicvector(to_bitvector(a) sla conv_integer(b));
when ALU_SRA =>
res := to_stdlogicvector(to_bitvector(a) sra conv_integer(b));
when ALU_ROL =>
res := to_stdlogicvector(to_bitvector(a) rol conv_integer(b));
when ALU_ROR =>
res := to_stdlogicvector(to_bitvector(a) ror conv_integer(b));
when ALU_NEG =>
res := ZERO - a;
when others =>
NULL;
end case;
c <= res;
if (res = ZERO) then
zf <= ZF_TRUE;
sf <= SF_FALSE;
elsif (conv_integer(res) < 0) then
zf <= ZF_FALSE;
sf <= SF_TRUE;
else
zf <= ZF_FALSE;
sf <= SF_FALSE;
end if;
end process;
end Behavioral;
|
apache-2.0
|
b403e5eccf14341b8434b813ba6e7e18
| 0.584332 | 3.161028 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/s2s_async_fifo_wt.vhd
| 1 | 61,617 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : s2s_async_fifo_wt.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity s2s_async_fifo_wt is
generic (
C_FAMILY : string := "virtex6";
C_MTBF_STAGES : integer := 31;
DEPTH : integer := 31;
WIDTH : integer := 16);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_clk : in std_logic;
wr_rst : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic);
end s2s_async_fifo_wt;
architecture rtl of s2s_async_fifo_wt is
constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH)+1;
constant ADDR_BITS : integer := log2(FIFO_DEPTH);
signal rd_addr : unsigned(ADDR_BITS-1 downto 0);
signal wr_addr : unsigned(ADDR_BITS-1 downto 0);
-- Following signals have gray values
signal wr_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_cnt_wr : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_cnt_rd : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_cnt_wr : std_logic_vector(ADDR_BITS-1 downto 0);
signal dummy_next_wr_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_cnt_rd : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_cnt_rd : std_logic_vector(ADDR_BITS-1 downto 0);
signal dummy_next_rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_cnt : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_cnt_wr : std_logic_vector(ADDR_BITS-1 downto 0);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal din_rdy_i : std_logic;
signal empty_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
signal full : std_logic;
signal empty : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
function calc_ram_style(is_unidir : natural) return boolean is
variable bram_style : boolean := false;
begin
return bram_style;
end function calc_ram_style;
constant USE_BRAM : boolean := (ADDR_BITS > 5);
-- pragma translate_off
signal dbg_ADDR_BITS : integer := ADDR_BITS;
-- pragma translate_on
constant C_EXTRA_SYNCS : integer := 1;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
-- From all gray signals, only next_rd_cnt and next_wr_cnt are counters. all
-- the rest are registers. It's simpler to use a binary counter and then use
-- a table to transfor to gray. Given that the address counter is initialized
-- to zero, signal next_XX_cnt will load code gray(0) after first increment.
-- Hence, it should be initialized to gray(N-1). that is, the initial values
-- will be:
-- * next_XX_cnt = gray(N-1)
-- * XX_cnt = gray(N-2)
-- * prev_XX_cnt = gray(N-3)
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
next_rd_cnt <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
rd_cnt <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
prev_rd_cnt <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_cnt <= rd_cnt;
rd_cnt <= next_rd_cnt;
next_rd_cnt <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
-- process(rd_clk, rd_rst)
-- begin
-- if(rd_rst = '1') then
-- wr_cnt_rd <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
-- dummy_next_wr_cnt<= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
-- elsif(rd_clk'event and rd_clk = '1') then
-- --if(fifo_we = '1') then
-- dummy_next_wr_cnt <= bin2gray(std_logic_vector(wr_addr));
-- wr_cnt_rd <= dummy_next_wr_cnt;
-- --end if;
-- end if;
-- end process;
--dummy_next_rd_cnt <= bin2gray(std_logic_vector(rd_addr));
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
next_wr_cnt <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
wr_cnt <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_cnt <= next_wr_cnt;
next_wr_cnt <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
-- process(wr_clk, wr_rst)
-- begin
-- if(wr_rst = '1') then
-- prev_rd_cnt_wr <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
-- dummy_next_rd_cnt<= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
-- elsif(rd_clk'event and rd_clk = '1') then
-- --if(fifo_re = '1') then
-- dummy_next_rd_cnt <= bin2gray(std_logic_vector(rd_addr ));
-- prev_rd_cnt_wr <= dummy_next_rd_cnt;
-- --end if;
-- end if;
-- end process;
--dummy_next_wr_cnt <= bin2gray(std_logic_vector(wr_addr));
-----------------------------------------------------------------
-- Flag FULL:
-- 1.- move to full condition (not din_rdy) when there is an efective
-- write next_wr_cnt = prev_rd_cnt
-- 2.- stay in full condition (not din_rdy) while this condition is true:
-- next_wr_cnt = rd_cnt
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if((not(din_rdy_i) or fifo_we) = '1') then
if(din_rdy_i = '1') then
if (next_wr_cnt = prev_rd_cnt) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
else
if (wr_cnt = prev_rd_cnt) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
-- Flag EMPTY:
-- 1.- move to empty condition when there is read (next_rd_cnt = wr_cnt)
-- 2.- stay in empty condition while the two pointers are the same (wr_cnt = rd_cnt)
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if((empty_i or fifo_re) = '1') then
if(empty_i = '0') then
if(next_rd_cnt = wr_cnt) then
empty_i <= '1';
else
empty_i <= '0';
end if;
else
if(rd_cnt = wr_cnt) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
-----------------------------------------------------------------------
-- memory modeling (XST to infer)
DIST_MEM_GEN : if not(USE_BRAM) generate
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "distributed";
signal mem_dout : std_logic_vector(WIDTH-1 downto 0);
begin
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
end generate DIST_MEM_GEN;
BRAM_MEM_GEN : if (USE_BRAM) generate
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "block";
begin
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem(to_integer(rd_addr));
end if;
end if;
end process;
end generate BRAM_MEM_GEN;
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate
begin
din_rdy <= not(full);
dout_vld <= not(empty);
DIST_MEM_GEN : if not(USE_BRAM) generate
begin
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADDR_BITS,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => WIDTH,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADDR_BITS,
C_RD_DEPTH => FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADDR_BITS,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
C_WR_DEPTH => FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADDR_BITS,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => din_vld,
rd_en => dout_rdy,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
end generate DIST_MEM_GEN;
BRAM_MEM_GEN : if (USE_BRAM) generate
begin
FIF_BMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADDR_BITS,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => WIDTH,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADDR_BITS,
C_RD_DEPTH => FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADDR_BITS,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
C_WR_DEPTH => FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADDR_BITS,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => din_vld,
rd_en => dout_rdy,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
end generate BRAM_MEM_GEN;
end generate NEW_INTRO;
end rtl;
|
mit
|
1a5aa6431d0a8936dcfe359136c5dbaf
| 0.477709 | 3.489664 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/ioblock0_e-rtl-a.vhd
| 1 | 4,983 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ioblock0_e-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock0_e
--
architecture rtl of ioblock0_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_g_i --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
p_di : in std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_6 <= p_mix_iosel_6_gi; -- __I_I_BIT_PORT
iosel_7 <= p_mix_iosel_7_gi; -- __I_I_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_data_i1
ioc_data_i1: ioc_g_i
port map (
di => data_i1, -- io data
p_di => pad_di_1, -- data in from pad
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(7) => iosel_7 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_data_i1
-- Generated Instance Port Map for ioc_data_o1
ioc_data_o1: ioc_g_o
port map (
do => data_o1, -- io data
p_do => pad_do_2, -- data out to pad
p_en => pad_en_2, -- pad output enable
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(7) => iosel_7 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_data_o1
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
a53b4d6f309c99565fdfd1231b83bcf2
| 0.579571 | 2.611635 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/sync_ap_status.vhd
| 1 | 5,231 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : sync_ap_status.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-08-25 2.0 pvk Changed reset polarity to active low
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
-- this is a synchronizer module for ap_start and ap_done (between accelerator
-- clock and AXI clock)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity sync_ap_status is
port (
rst : in std_logic;
ap_clk : in std_logic;
ap_flag : in std_logic;
axi_clk : in std_logic;
flag : out std_logic;
flag_clr : in std_logic);
end entity;
architecture rtl of sync_ap_status is
signal wr_cnt : std_logic;
signal rd_cnt : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal full_n : std_logic;
signal empty_n : std_logic;
begin
wr_en <= ap_flag and full_n;
process(ap_clk, rst)
begin
if(rst = '1') then
wr_cnt <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(wr_en = '1') then
wr_cnt <= not(wr_cnt);
end if;
end if;
end process;
rd_en <= flag_clr and empty_n;
process(axi_clk, rst)
begin
if(rst = '1') then
rd_cnt <= '0';
elsif(axi_clk'event and axi_clk = '1') then
if(rd_en = '1') then
rd_cnt <= not(rd_cnt);
end if;
end if;
end process;
process(ap_clk, rst)
begin
if(rst = '1') then
full_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(full_n = '1') then
full_n <= not(wr_en);
else
full_n <= not(wr_cnt xor rd_cnt);
end if;
end if;
end process;
process(axi_clk, rst)
begin
if(rst = '1') then
empty_n <= '0';
elsif(axi_clk'event and axi_clk = '1') then
if(empty_n = '1') then
empty_n <= not(rd_en);
else
empty_n <= (wr_cnt xor rd_cnt);
end if;
end if;
end process;
flag <= empty_n;
end rtl;
|
mit
|
35e23dca7bd8e6167e1b6bcb3565423c
| 0.573886 | 4.061335 | false | false | false | false |
mitchsm/nvc
|
test/expect.vhd
| 5 | 2,297 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic );
end entity;
architecture rtl of memory is
type ram_t is array (0 to 255) of std_logic_vector(WIDTH - 1 downto 0);
signal addr_r : unsigned(7 downto 0) := X"00";
signal ram : ram_t;
begin
reg: process (clk) is
begin
if rising_edge(clk) then
addr_r <= addr;
if we = '1' then
ram(to_integer(addr)) <= din;
end if;
end if;
end process;
dout <= ram(to_integer(addr_r));
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
end entity;
architecture test of top is
constant ITERS : integer := 1;
constant WIDTH : integer := 8;
signal clk : std_logic := '0';
signal addr : unsigned(7 downto 0) := X"00";
signal din : std_logic_vector(WIDTH - 1 downto 0);
signal dout : std_logic_vector(WIDTH - 1 downto 0);
signal we : std_logic := '0';
signal running : boolean := true;
begin
clk <= not clk after 5 ns when running else '0';
uut: entity work.memory
generic map (
WIDTH => WIDTH )
port map (
clk => clk,
addr => addr,
din => din,
dout => dout,
we => we );
stim: process is
begin
for j in 1 to ITERS loop
wait for 20 ns;
we <= '1';
for i in 0 to 255 loop
addr <= to_unsigned(i, 8);
din <= std_logic_vector(to_unsigned((i + j) mod 256, WIDTH));
wait for 10 ns;
end loop;
we <= '0';
for i in 0 to 255 loop
addr <= to_unsigned(i, 8);
wait for 10 ns;
assert dout = std_logic_vector(to_unsigned((i + j) mod 256, WIDTH));
end loop;
end loop;
end process;
end architecture;
|
gpl-3.0
|
a079e3852f50987392a3655ab1132668
| 0.502394 | 3.834725 | false | false | false | false |
mitchsm/nvc
|
test/sem/issue236.vhd
| 3 | 907 |
entity subent is
port (
a : in boolean := false;
b : in boolean;
c : inout string; -- unconstrained
d : out string(1 to 4)
);
end entity;
entity test is
end entity;
architecture a1 of test is
begin
e1: entity work.subent -- ok
port map (
-- a is an unassociated port of mode IN but has a default value
b => true,
c => "1234"
-- d is unassociated port of mode OUT but is constrained
);
e2: entity work.subent -- error
port map (
a => true,
-- b is not allowed to be unassociated
c => "1234"
);
end architecture;
architecture a2 of test is
begin
e2: entity work.subent -- error
port map (
a => true,
b => true
-- c is not allowed to be unassociated
);
end architecture;
|
gpl-3.0
|
9073f06f358a53d8f800159acf407bb9
| 0.510474 | 3.926407 | false | true | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/clk_x_pntrs.vhd
| 1 | 24,116 |
-------------------------------------------------------------------------------
-- $Id: clk_x_pntrs.vhd,v 1.1 2011/06/02 09:43:59 robertb Exp $
-- Title : Clock Crossing Logic
-- Project : FIFO Generator
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : clk_x_pntrs.vhd
-- Author : Xilinx
-------------------------------------------------------------------------------
--
-- Description: This module is used only for Asynchronous FIFOs to pass the
-- read pointer from RD_CLK domain to WR_CLK domain and the
-- write pointer from WR_CLK domain to RD_CLK domain.
-- In the process of passing the pointers from one clock domain to
-- another, registers might fall into meta-stable state. In order
-- to avoid this undesired situation, two-register-stage
-- synchronization logic is implemented after data is passed into
-- the different clock domain.
--
-- I. Functionality:
--
-- 1. Input binary write pointer is converted into gray code.
--
-- 2. The gray encoded write pointer is registered in the WR_CLK
-- domain. The content of these flops are guaranteed to contain
-- either the current value or the next value in the sequence,
-- since only one bit can change at a time. Therefore, using
-- gray code guarantees valid pointer values across clock
-- domains. For implementing these gray counters, it is more
-- efficient to implement a binary counter and then XOR the
-- outputs to create a gray code output than to build a gray
-- counter directly.
--
-- 3. It is then registered twice in the RD_CLK domain. As the
-- Gray-encoded counter values are passed across cross domains
-- from the WR_CLK domain to the RD_CLK domain, or vice-versa,
-- it is possible that the counter value may be in a state of
-- transition at the time that the flops latch in their data.
-- Since the counter value is gray-coded, only one bit will be
-- transitioning at any given time, and therefore it is expected
--- that only one flop is likely to be metastable. Under these
-- circumstances, it is acceptable for the metastable flop to
-- latch in either the old or the new value.
--
-- 4. In the RD_CLK domain, it is converted back to binary and
-- registered.
--
-- 5. Steps 1-4 are repeated for the read pointer (passed from
-- RD_CLK domain to WR_CLK domain)
--
--
-- II. Module I/O
-- Inputs: WR_CLK, RD_CLK, WR_RST, RD_RST,
-- RD_PNTR (C_RD_PNTR_WIDTH-1:0),
-- WR_PNTR (C_WR_PNTR_WIDTH-1:0)
--
-- Outputs: RD_PNTR_WR (C_RD_PNTR_WIDTH-1:0),
-- WR_PNTR_RW (C_WR_PNTR_WIDTH-1:0)
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
ENTITY clk_x_pntrs IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
---------------------------------------------------------------------------
C_HAS_RST : integer := 0;
C_RD_PNTR_WIDTH : integer := 4;
C_WR_PNTR_WIDTH : integer := 4;
C_MSGON_VAL : integer := 1;
C_SYNCHRONIZER_STAGE : integer := 2
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
-- Inputs
WR_CLK : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_RST : IN std_logic := '0';
WR_PNTR : IN std_logic_vector (C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_PNTR : IN std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
-- Outputs
WR_PNTR_RD : OUT std_logic_vector (C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_PNTR_WR : OUT std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0')
);
END clk_x_pntrs;
-------------------------------------------------------------------------------
-- Port Definitions:
-------------------------------------------------------------------------------
-- WR_PNTR_RD : Write Pointer synchronized to RD_CLK
-- RD_PNTR_WR : Read Pointer synchronized to WR_CLK
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF clk_x_pntrs IS
ATTRIBUTE DowngradeIPIdentifiedWarnings: STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF xilinx : ARCHITECTURE IS "yes";
-----------------------------------------------------------------------------
-- Internal Constants
-----------------------------------------------------------------------------
CONSTANT zeros_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT zeros_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
--CONSTANT MSGONATTR : string := int_2_strbool(C_MSGON_VAL);
-----------------------------------------------------------------------------
-- Internal Signals
-----------------------------------------------------------------------------
-- The following 6 signals are initialized to 0. Because they are gray coded
-- signals, the initial value "0" is actually the gray code for binary "0".
-- If they have to be initialized to a non-zero value, make sure to use the
-- bin2gray function.
SIGNAL wr_pntr_gc : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
SIGNAL rd_pntr_gc : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- SIGNAL wr_pntr_gc_asreg : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL rd_pntr_gc_asreg : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
SIGNAL wr_pntr_gc_asreg_last : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
SIGNAL rd_pntr_gc_asreg_last : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
SIGNAL wr_pntr_bin : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
SIGNAL rd_pntr_bin : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- Defined to connect data output of one FIFO to data input of another
TYPE wr_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
TYPE rd_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_q : wr_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL rd_q : rd_sync_array := (OTHERS => (OTHERS => '0'));
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
-- ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF wr_q : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_q : SIGNAL IS "true";
--
-- ATTRIBUTE msgon : STRING;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF wr_q : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_q : SIGNAL IS MSGONATTR;
-----------------------------------------------------------------------------
BEGIN --xilinx
-------------------------------------------------------------------------------
-- Asynchronous FIFO
--
-- Pass WR_PNTR from WR_CLK domain to RD_CLK domain
-------------------------------------------------------------------------------
--
--
-- STAGE 1 | STAGE 2 STAGE 3 STAGE 4
-- |
-- |
-- | wr_pntr_gc wr_pntr_gc
-- wr_pntr_gc _asreg _asreg_d1 wr_pntr_bin
-- +------+ | +------+ +------+ +------+
-- --\| bin2 |--------\| |----\| |----\| |----\
-- --/| gray |--------/| |----/| |----/| |----/
-- WR_PNTR | | | | | | | | | WR_PNTR_RD
-- +--|> a | | +-|> a | +-|> a | +-|> a |
-- | +------+ | | +------+ | +------+ | +------+
-- | ^ | | ^ | ^ | ^
-- | | | | | | | | |
-- | | | | +------|-----+------|-----+------- RD_RST
-- --+ | | | | |
-- WR_CLK | | +------------+------------+-------------- RD_CLK
-- | |
-- ---------+ |
-- WR_RST |
-- |
-- |
-- WR_CLK domain | RD_CLK domain
-- |
--
--
-- a = asynchronous reset of the register
-----------------------------------------------------------------------------
-- First stage of clock domain crossing
-- Clock binary to gray value of the write pointer in WR_CLK domain
-----------------------------------------------------------------------------
-- wr_pntr_gc is reset to 0. Because it is a gray coded signal the reset
-- value "0" is actually the gray code for binary "0". If it has to be
-- initialized to a non-zero value, make sure to use the bin2gray function.
pwgc : PROCESS (WR_CLK, WR_RST)
BEGIN
if (WR_RST='1') then
wr_pntr_gc <= zeros_wr;
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
wr_pntr_gc <= bin2gray(WR_PNTR) AFTER TFF;
END IF;
END PROCESS pwgc;
-- -----------------------------------------------------------------------------
-- -- Second and third stages of clock domain crossing
-- -- Clock gray value of the write pointer with RD_CLK
-- -----------------------------------------------------------------------------
-- -- wr_pntr_gc_asreg and wr_pntr_gc_asreg_last are reset to 0. Because they are
-- -- gray coded signals, the reset value "0" is actually the gray code for
-- -- binary "0". If they have to be initialized to a non-zero value, make sure
-- -- to use the bin2gray function.
--
-- -- rd_pntr_gc_asreg and rd_pntr_gc_asreg_last are reset to 0. Because they are
-- -- gray coded signals, the reset value "0" is actually the gray code for
-- -- binary "0". If they have to be initialized to a non-zero value, make sure
-- -- to use the bin2gray function.
--
-- g2stage_synch: IF (C_SYNCHRONIZER_STAGE = 2) GENERATE
-- SIGNAL wr_pntr_gc_asreg : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL rd_pntr_gc_asreg : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg : SIGNAL IS "true";
--
-- ATTRIBUTE msgon : STRING;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- BEGIN
-- pwx: PROCESS (RD_CLK, RD_RST)
-- BEGIN
-- if (RD_RST='1') then
-- wr_pntr_gc_asreg <= zeros_wr;
-- wr_pntr_gc_asreg_last <= zeros_wr;
-- ELSIF RD_CLK'event AND RD_CLK = '1' THEN
-- wr_pntr_gc_asreg <= wr_pntr_gc AFTER TFF;
-- wr_pntr_gc_asreg_last <= wr_pntr_gc_asreg AFTER TFF;
-- END IF;
-- END PROCESS pwx;
--
-- prx: PROCESS (WR_CLK, WR_RST)
-- BEGIN
-- if (WR_RST='1') then
-- rd_pntr_gc_asreg <= zeros_rd;
-- rd_pntr_gc_asreg_last <= zeros_rd;
-- ELSIF WR_CLK'event AND WR_CLK = '1' THEN
-- rd_pntr_gc_asreg <= rd_pntr_gc AFTER TFF;
-- rd_pntr_gc_asreg_last <= rd_pntr_gc_asreg AFTER TFF;
-- END IF;
-- END PROCESS prx;
-- END GENERATE g2stage_synch;
--
-- g3stage_synch: IF (C_SYNCHRONIZER_STAGE = 3) GENERATE
-- SIGNAL wr_pntr_gc_asreg : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL wr_pntr_gc_asreg_d1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL rd_pntr_gc_asreg : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- SIGNAL rd_pntr_gc_asreg_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg_d1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg_d1 : SIGNAL IS "true";
--
-- ATTRIBUTE msgon : STRING;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg_d1 : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg_d1 : SIGNAL IS MSGONATTR;
-- BEGIN
-- pwx: PROCESS (RD_CLK, RD_RST)
-- BEGIN
-- if (RD_RST='1') then
-- wr_pntr_gc_asreg <= zeros_wr;
-- wr_pntr_gc_asreg_d1 <= zeros_wr;
-- wr_pntr_gc_asreg_last <= zeros_wr;
-- ELSIF RD_CLK'event AND RD_CLK = '1' THEN
-- wr_pntr_gc_asreg <= wr_pntr_gc AFTER TFF;
-- wr_pntr_gc_asreg_d1 <= wr_pntr_gc_asreg AFTER TFF;
-- wr_pntr_gc_asreg_last <= wr_pntr_gc_asreg_d1 AFTER TFF;
-- END IF;
-- END PROCESS pwx;
--
-- prx: PROCESS (WR_CLK, WR_RST)
-- BEGIN
-- if (WR_RST='1') then
-- rd_pntr_gc_asreg <= zeros_rd;
-- rd_pntr_gc_asreg_d1 <= zeros_rd;
-- rd_pntr_gc_asreg_last <= zeros_rd;
-- ELSIF WR_CLK'event AND WR_CLK = '1' THEN
-- rd_pntr_gc_asreg <= rd_pntr_gc AFTER TFF;
-- rd_pntr_gc_asreg_d1 <= rd_pntr_gc_asreg AFTER TFF;
-- rd_pntr_gc_asreg_last <= rd_pntr_gc_asreg_d1 AFTER TFF;
-- END IF;
-- END PROCESS prx;
-- END GENERATE g3stage_synch;
--
-- g4stage_synch: IF (C_SYNCHRONIZER_STAGE = 4) GENERATE
-- SIGNAL wr_pntr_gc_asreg : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL wr_pntr_gc_asreg_d1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL wr_pntr_gc_asreg_d2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := zeros_wr;
-- SIGNAL rd_pntr_gc_asreg : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- SIGNAL rd_pntr_gc_asreg_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- SIGNAL rd_pntr_gc_asreg_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := zeros_rd;
-- ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg_d1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF wr_pntr_gc_asreg_d2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg_d1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rd_pntr_gc_asreg_d2 : SIGNAL IS "true";
--
-- ATTRIBUTE msgon : STRING;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg_d1 : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF wr_pntr_gc_asreg_d2 : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg_d1 : SIGNAL IS MSGONATTR;
-- ATTRIBUTE msgon OF rd_pntr_gc_asreg_d2 : SIGNAL IS MSGONATTR;
-- BEGIN
-- pwx: PROCESS (RD_CLK, RD_RST)
-- BEGIN
-- if (RD_RST='1') then
-- wr_pntr_gc_asreg <= zeros_wr;
-- wr_pntr_gc_asreg_d1 <= zeros_wr;
-- wr_pntr_gc_asreg_d2 <= zeros_wr;
-- wr_pntr_gc_asreg_last <= zeros_wr;
-- ELSIF RD_CLK'event AND RD_CLK = '1' THEN
-- wr_pntr_gc_asreg <= wr_pntr_gc AFTER TFF;
-- wr_pntr_gc_asreg_d1 <= wr_pntr_gc_asreg AFTER TFF;
-- wr_pntr_gc_asreg_d2 <= wr_pntr_gc_asreg_d1 AFTER TFF;
-- wr_pntr_gc_asreg_last <= wr_pntr_gc_asreg_d2 AFTER TFF;
-- END IF;
-- END PROCESS pwx;
--
-- prx: PROCESS (WR_CLK, WR_RST)
-- BEGIN
-- if (WR_RST='1') then
-- rd_pntr_gc_asreg <= zeros_rd;
-- rd_pntr_gc_asreg_d1 <= zeros_rd;
-- rd_pntr_gc_asreg_d2 <= zeros_rd;
-- rd_pntr_gc_asreg_last <= zeros_rd;
-- ELSIF WR_CLK'event AND WR_CLK = '1' THEN
-- rd_pntr_gc_asreg <= rd_pntr_gc AFTER TFF;
-- rd_pntr_gc_asreg_d1 <= rd_pntr_gc_asreg AFTER TFF;
-- rd_pntr_gc_asreg_d2 <= rd_pntr_gc_asreg_d1 AFTER TFF;
-- rd_pntr_gc_asreg_last <= rd_pntr_gc_asreg_d2 AFTER TFF;
-- END IF;
-- END PROCESS prx;
-- END GENERATE g4stage_synch;
gsync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
rd_stg_inst: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => C_HAS_RST,
C_WIDTH => C_WR_PNTR_WIDTH
)
PORT MAP (
RST => RD_RST,
CLK => RD_CLK,
D => wr_q(i-1),
Q => wr_q(i)
);
wr_stg_inst: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => C_HAS_RST,
C_WIDTH => C_RD_PNTR_WIDTH
)
PORT MAP (
RST => WR_RST,
CLK => WR_CLK,
D => rd_q(i-1),
Q => rd_q(i)
);
END GENERATE gsync_stage;
wr_q(0) <= wr_pntr_gc;
wr_pntr_gc_asreg_last <= wr_q(C_SYNCHRONIZER_STAGE);
rd_q(0) <= rd_pntr_gc;
rd_pntr_gc_asreg_last <= rd_q(C_SYNCHRONIZER_STAGE);
-- pwr_sync : PROCESS (RD_CLK, RD_RST)
-- BEGIN
-- if (RD_RST='1' AND C_HAS_RST = 1) then
-- wr_q <= (OTHERS => (OTHERS => '0'));
-- ELSIF (RD_CLK'event AND RD_CLK='1') THEN
-- FOR I IN 1 TO C_SYNCHRONIZER_STAGE LOOP
-- wr_q(i) <= wr_q(i-1);
-- END LOOP;
-- END IF;
-- END PROCESS pwr_sync;
--
-- prd_sync : PROCESS (WR_CLK, WR_RST)
-- BEGIN
-- if (WR_RST='1' AND C_HAS_RST = 1) then
-- rd_q <= (OTHERS => (OTHERS => '0'));
-- ELSIF (WR_CLK'event AND WR_CLK='1') THEN
-- FOR I IN 1 TO C_SYNCHRONIZER_STAGE LOOP
-- rd_q(i) <= rd_q(i-1);
-- END LOOP;
-- END IF;
-- END PROCESS prd_sync;
-----------------------------------------------------------------------------
-- Fourth stage of clock domain crossing
-- Clock gray to binary value of the write pointer in RD_CLK domain
-----------------------------------------------------------------------------
pwbin : PROCESS (RD_CLK, RD_RST)
BEGIN
if (RD_RST='1' AND C_HAS_RST = 1) then
wr_pntr_bin <= zeros_wr;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
wr_pntr_bin <= gray2bin(wr_pntr_gc_asreg_last) AFTER TFF;
END IF;
END PROCESS pwbin;
-----------------------------------------------------------------------------
-- Asynchronous FIFO
--
-- Pass RD_PNTR from RD_CLK domain to WR_CLK domain
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- First stage of clock domain crossing
-- Clock binary to gray value of the read pointer in RD_CLK domain
-----------------------------------------------------------------------------
-- rd_pntr_gc is reset to 0. Because it is a gray coded signal the reset
-- value "0" is actually the gray code for binary "0". If it has to be
-- initialized to a non-zero value, make sure to use the bin2gray function.
prgc : PROCESS (RD_CLK, RD_RST)
BEGIN
if (RD_RST='1' AND C_HAS_RST = 1) then
rd_pntr_gc <= zeros_rd;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
rd_pntr_gc <= bin2gray(RD_PNTR) AFTER TFF;
END IF;
END PROCESS prgc;
-----------------------------------------------------------------------------
-- Fourth stage of clock domain crossing
-- Clock gray to binary value of the read pointer in WR_CLK domain
-----------------------------------------------------------------------------
prbin : PROCESS (WR_CLK, WR_RST)
BEGIN
if (WR_RST='1' AND C_HAS_RST = 1) then
rd_pntr_bin <= zeros_rd;
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
rd_pntr_bin <= gray2bin(rd_pntr_gc_asreg_last ) AFTER TFF;
END IF;
END PROCESS prbin;
-- Connect the output ports
WR_PNTR_RD <= wr_pntr_bin;
RD_PNTR_WR <= rd_pntr_bin;
END xilinx;
|
mit
|
a77dbc637cb6429892bca731c0ca5d69
| 0.50651 | 3.689154 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue94.vhd
| 5 | 761 |
package pkg is
function func (dataw : integer; shiftw : integer)return bit_vector;
end pkg;
package body pkg is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
y_temp(1):=(others => '0');
return y_temp(0);
end func;
end pkg;
entity issue94 is
end entity;
use work.pkg.all;
architecture test of issue94 is
begin
process is
begin
assert func(4, 4) = "1111";
wait;
end process;
end architecture;
|
gpl-3.0
|
d334a1f04ce5106f5edcf23f8bcc50a8
| 0.626807 | 3.57277 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_s2m_adapter.vhd
| 1 | 12,386 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_s2m_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_s2m_converter;
use axis_accelerator_adapter_v2_1_6.xd_s2m_memory_dc;
use axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt;
entity xd_s2m_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7";
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_S_AXIS_TDATA_WIDTH : integer;
C_S_AXIS_TUSER_WIDTH : integer;
C_S_AXIS_TID_WIDTH : integer;
C_S_AXIS_TDEST_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer;
C_EXTRA_SYNCS : integer);
port (
-- Input streams
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TVALID : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TKEEP : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TID : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
dbg_stream_nwords : out std_logic_vector(15 downto 0);
dbg_buffer_nwords : out std_logic_vector(15 downto 0);
dbg_ap_start : in std_logic;
ap_clk : in std_logic;
ap_rst_sync : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
mb_arg_rdy : out std_logic;
mb_arg_done : in std_logic;
status_empty : out std_logic;
status_full : out std_logic;
status_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_s2m_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
signal axi_rst : std_logic;
signal axi_rst1 : std_logic;
signal axi_rst2 : std_logic;
function calc_axi_addr_width return integer is
variable addr_width : integer := 0;
begin
if (C_S_AXIS_TDATA_WIDTH > C_AP_ARG_DATA_WIDTH) then
addr_width := C_AP_ARG_ADDR_WIDTH-log2(C_S_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH);
else
addr_width := C_AP_ARG_ADDR_WIDTH+log2(C_AP_ARG_DATA_WIDTH/C_S_AXIS_TDATA_WIDTH);
end if;
return addr_width;
end function calc_axi_addr_width;
constant AXI_DATA_WIDTH : integer := C_S_AXIS_TDATA_WIDTH;
constant AXI_ADDR_WIDTH : integer := calc_axi_addr_width;
signal ap_rst_vec : std_logic_vector(0 downto 0);
-- signal ap_rst_sync : std_logic;
-- signal ap_rst_sync1 : std_logic;
signal axisn_rst : std_logic;
signal conv_addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
signal conv_ce : std_logic;
signal conv_we : std_logic;
signal conv_last : std_logic;
signal conv_rdy : std_logic;
signal conv_data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
-- Control for number of words receided in the stream
signal last_conv_addr_vld : std_logic;
signal stream_nwords : unsigned(AXI_ADDR_WIDTH downto 0);
signal stream_nwords_vld : std_logic;
signal buffer_nwords : std_logic_vector(AXI_ADDR_WIDTH downto 0);
signal buffer_nwords_vld : std_logic;
signal buffer_nwords_rdy : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi_rst1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync : SIGNAL IS "true";
begin
-- undriven ports
dbg_stream_nwords <= (others => '0');
dbg_buffer_nwords <= (others => '0');
-- core reset generation
-- prd1: PROCESS (S_AXIS_ACLK, ap_rst)
-- BEGIN
-- -- Register Stage #1
-- IF (ap_rst = '1') THEN
-- ap_rst_sync1 <= '1';
-- ap_rst_sync <= '1';
-- ELSIF (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') THEN
-- ap_rst_sync1 <= '0';
-- ap_rst_sync <= ap_rst_sync1;
-- END IF;
-- END PROCESS prd1;
axi_rst2 <= not(S_AXIS_ARESETN) or ap_rst_sync;
prd2: PROCESS (S_AXIS_ACLK, axi_rst2)
BEGIN
-- Register Stage #1
IF (axi_rst2 = '1') THEN
axi_rst1 <= '1';
axi_rst <= '1';
ELSIF (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') THEN
axi_rst1 <= '0';
axi_rst <= axi_rst1;
END IF;
END PROCESS prd2;
CONVERTER_I : entity axis_accelerator_adapter_v2_1_6.xd_s2m_converter
generic map (
C_FAMILY => C_FAMILY,
AXI_DATA_WIDTH => AXI_DATA_WIDTH,
AXI_ADDR_WIDTH => AXI_ADDR_WIDTH,
C_EXTRA_SYNCS => C_EXTRA_SYNCS)
port map (
axi_clk => S_AXIS_ACLK,
axi_rst => axi_rst,
axis_vld => S_AXIS_TVALID,
axis_rdy => S_AXIS_TREADY,
axis_last => S_AXIS_TLAST,
axis_keep => S_AXIS_TKEEP,
axis_data => S_AXIS_TDATA,
conv_addr => conv_addr,
conv_ce => conv_ce,
conv_we => conv_we,
conv_last => conv_last,
conv_rdy => conv_rdy,
conv_data => conv_data);
MEM_CTRL_I : entity axis_accelerator_adapter_v2_1_6.xd_s2m_memory_dc
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_BRAM_TYPE => C_BRAM_TYPE,
CONV_DATA_WIDTH => AXI_DATA_WIDTH,
CONV_ADDR_WIDTH => AXI_ADDR_WIDTH,
C_AP_ARG_WIDTH => C_AP_ARG_WIDTH,
C_AP_ARG_N_DIM => C_AP_ARG_N_DIM,
C_AP_ARG_DIM_1 => C_AP_ARG_DIM_1,
C_AP_ARG_DIM_2 => C_AP_ARG_DIM_2,
C_AP_ARG_FORMAT_TYPE => C_AP_ARG_FORMAT_TYPE,
C_AP_ARG_FORMAT_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_AP_ARG_FORMAT_DIM => C_AP_ARG_FORMAT_DIM,
C_AP_ARG_DATA_WIDTH => C_AP_ARG_DATA_WIDTH,
C_AP_ARG_ADDR_WIDTH => C_AP_ARG_ADDR_WIDTH,
C_MULTIBUFFER_DEPTH => C_MULTIBUFFER_DEPTH,
C_EXTRA_SYNCS => C_EXTRA_SYNCS)
port map (
clk => S_AXIS_ACLK,
rst => axi_rst,
conv_addr => conv_addr,
conv_ce => conv_ce,
conv_we => conv_we,
conv_last => conv_last,
conv_rdy => conv_rdy,
conv_data => conv_data,
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_arg_addr => ap_arg_addr,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout,
mb_arg_rdy => mb_arg_rdy,
mb_arg_done => mb_arg_done,
status_empty => status_empty,
status_full => status_full,
status_used => status_used);
---------------------------
-- The following logic is used for debugging purposes (provide number of
-- words received in the axi_stream. TODO: design not finished.
last_conv_addr_vld <= conv_ce and conv_rdy and conv_last;
process(S_AXIS_ACLK)
begin
if (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(last_conv_addr_vld = '1') then
stream_nwords <= unsigned('0' & conv_addr) + 1;
end if;
end if;
end process;
process(S_AXIS_ACLK, axi_rst)
begin
if (axi_rst = '1') then
stream_nwords_vld <= '0';
elsif (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
stream_nwords_vld <= last_conv_addr_vld;
end if;
end process;
NWORDS_FIFO_I : entity axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt
generic map (
C_FAMILY => C_FAMILY,
WIDTH => AXI_ADDR_WIDTH+1)
port map (
rst => axi_rst,
clk => S_AXIS_ACLK,
din => std_logic_vector(stream_nwords),
din_vld => stream_nwords_vld,
din_rdy => open,
dout => buffer_nwords,
dout_vld => buffer_nwords_vld,
dout_rdy => buffer_nwords_rdy);
buffer_nwords_rdy <= '0';
end rtl;
|
mit
|
f888b9c5077ae05f1debc32140ea4edc
| 0.575166 | 3.408365 | false | false | false | false |
mitchsm/nvc
|
test/wave/wave_test.vhd
| 4 | 2,005 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sub is
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;
architecture test of sub is
signal ctr : unsigned(3 to 18) := (others => '0');
signal ctr2 : unsigned(15 downto 0) := (others => '0');
begin
y <= x after 5 ns;
ctr <= ctr + 1 after 20 ns;
ctr2 <= ctr2 + 1 after 20 ns;
end architecture;
-------------------------------------------------------------------------------
package p is
signal s : bit;
end package;
-------------------------------------------------------------------------------
entity wave_test is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use work.p.all;
architecture test of wave_test is
signal x : std_logic_vector(7 downto 0) := X"AA";
signal y : std_logic_vector(7 downto 0);
signal z : std_logic := 'U';
signal o : std_logic := '0';
signal b : boolean;
signal m : string(1 to 3);
signal p : bit_vector(1 to 3);
signal q : bit_vector(3 downto 1);
signal t : delay_length;
type state is (INIT, ONE, TWO);
signal s : state;
begin
x <= not x after 50 ns;
z <= 'X' after 100 ns, -- Appears same as 'U'
'H' after 200 ns,
'Z' after 300 ns,
'L' after 400 ns,
'-' after 500 ns,
'1' after 600 ns;
a_block: block is
signal i : natural; -- No integer type in FST?
signal c : character;
begin
i <= i + 1 after 20 ns;
c <= m((i rem 3) + 1);
end block;
m <= "abc";
work.p.s <= '1';
b <= true;
s <= ONE after 60 ns, TWO after 150 ns;
sub_i: entity work.sub
port map ( x, y );
gen: for i in 1 to 3 generate
signal g : integer;
begin
end generate;
p(1) <= '1';
p(2) <= '1';
p(3) <= '0';
q(1) <= '1';
q(2) <= '1';
q(3) <= '0';
t <= 20 us after 1 ps;
end architecture;
|
gpl-3.0
|
43d5ebb5c0affd881b14ccb98075bf54
| 0.489776 | 3.341667 | false | false | false | false |
mitchsm/nvc
|
test/regress/implicit2.vhd
| 5 | 630 |
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = t1;
wait for 2 ns;
t0 := x'transaction;
report bit'image(t0);
assert t0 = not t1;
wait for 2 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = not t1;
wait;
end process;
end architecture;
|
gpl-3.0
|
5f9e8dcbc4c973b1ffcd4b4f1fc56fc0
| 0.536508 | 3.519553 | false | false | false | false |
mitchsm/nvc
|
test/regress/const2.vhd
| 4 | 1,322 |
package pack is
function foo(x : in integer) return real;
end package;
package body pack is
type real_vector is array (integer range <>) of real;
function get_results return real_vector is
begin
return ( 52.6, 16.7, 1.832, 0.623, 762.236 );
end function;
constant results : real_vector := get_results;
function foo(x : in integer) return real is
begin
return results(x);
end function;
type int_vector is array (integer range <>) of integer;
subtype int_vector4 is int_vector(1 to 4);
constant blah : int_vector4 := ( 0, 1, 6, 6 );
constant blah2 : int_vector4 := blah;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity const2 is
end entity;
architecture test of const2 is
function get_it return integer is
begin
return integer(foo(integer'left + 1));
end function;
function get_bits return bit_vector is
begin
return "110101";
end function;
constant some_bits : bit_vector := get_bits;
constant a_bit : bit := some_bits(2);
begin
process is
begin
assert get_it = 16;
assert some_bits(some_bits'right) = '1';
assert a_bit = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
a828178a2546083dccc67de3f88320c9
| 0.587746 | 3.888235 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/control.vhd
| 1 | 3,706 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.functions.all;
use work.psl.all;
use work.wed.all;
use work.control_package.all;
use work.cu_package.all;
use work.dma_package.all;
entity control is
port (
i : in control_in;
o : out control_out
);
end entity control;
architecture logic of control is
signal q, r : control_int;
signal ci : cu_in;
signal co : cu_out;
begin
comb : process(all)
variable v : control_int;
begin
----------------------------------------------------------------------------------------------------------------------- default assignments
v := r;
v.o.cd.read.valid := '0';
v.o.cd.write.request.valid := '0';
v.o.cd.write.data.valid := '0';
----------------------------------------------------------------------------------------------------------------------- control commands
if i.ha.val then
case i.ha.com is
when PCC_RESET =>
v.state := reset;
v.o.ca.reset := '1';
when PCC_START =>
v.state := wed;
v.o.ah.running := '1';
read_cacheline (v.o.cd.read, i.ha.ea);
when others =>
null;
end case;
end if;
----------------------------------------------------------------------------------------------------------------------- afu state machine
case r.state is
when idle =>
v.o.ah.done := '0';
when reset =>
v.state := idle;
v.o.ca.reset := '0';
v.o.ah.done := '1';
when wed =>
if i.dc.read.valid then
v.state := go;
wed_parse (i.dc.read.data, v.wed);
v.start := '1';
end if;
when go =>
v.start := '0';
if co.done then
write_byte (v.o.cd.write, i.ha.ea, slv(x"01"));
v.state := done;
else
v.o.cd.read := co.read;
v.o.cd.write := co.write;
end if;
when done =>
if i.dc.write.valid then
v.state := idle;
v.o.ah.running := '0';
v.o.ah.done := '1';
end if;
when others =>
null;
end case;
----------------------------------------------------------------------------------------------------------------------- outputs
-- drive input registers
q <= v;
-- output
ci.start <= r.start;
o <= r.o;
end process;
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(i.clk, r.o.ca.reset)
begin
if rising_edge(i.clk) then
if r.o.ca.reset then
control_reset(r);
else
r <= q;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------------------- cu
ci.wed <= q.wed;
ci.cr.clk <= i.clk;
ci.cr.rst <= r.o.ca.reset;
ci.id <= i.dc.id;
ci.read <= i.dc.read;
ci.write <= i.dc.write;
cu0 : entity work.cu port map (ci, co);
end architecture logic;
|
bsd-2-clause
|
44296ee47461cf7358a7295285f64f24
| 0.32191 | 4.525031 | false | false | false | false |
mitchsm/nvc
|
test/sem/attr.vhd
| 3 | 4,179 |
entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
signal i : int_vec(1 to 3);
attribute foo of i : signal is 6; -- OK
begin
process is
variable v : integer;
begin
v := x'foo; -- OK
report y'bar; -- OK
end process;
process is
begin
report z'foo; -- Error
end process;
process is
variable v : int_vec_ptr;
begin
assert v'length = 5;
assert v.all'length = 62;
end process;
process is
begin
report e'path_name; -- OK
report e'instance_name; -- OK
report a1'path_name; -- OK
report a1'instance_name; -- OK
end process;
process is
begin
assert i'event; -- OK
assert i(1)'event; -- OK
assert i(x)'event; -- OK
assert i'foo = 1; -- OK
assert i(1)'foo = 2; -- Error
end process;
end architecture;
architecture a2 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of z : signal is string'("boo"); -- Error
attribute bar of x : signal is 73; -- Error
attribute foo of q : signal is 71; -- Error
attribute foo of yah : label is 12; -- Ignored
begin
end architecture;
architecture a3 of e is
type int10_vec is array (integer range 1 to 10) of integer;
begin
process is
variable x : integer;
begin
assert int10_vec'low = 1; -- OK
assert int10_vec'high = 10; -- OK
assert int10_vec'left = 1; -- OK
assert int10_vec'right = 10; -- OK
assert int10_vec'low(1) = 1; -- OK
assert int10_vec'left(x) = 2; -- Error
end process;
end architecture;
package p is
function func(x : in integer) return integer;
end package;
package body p is
function func(x : in integer) return integer is
begin
report func'instance_name;
return x + 1;
end function;
end package body;
entity issue39 is
generic (
g : bit := '0'
);
begin
assert (g = '0' or g = '1')
report issue39'instance_name & "oops!"
severity failure;
end entity issue39;
architecture a4 of e is
begin
process is
begin
assert integer'image(0)(0) = '0'; -- OK
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
attribute b : integer;
attribute b of i : variable is 4;
begin
assert i'a(1) = '0'; -- OK
assert i'b(1) = 1; -- Error
end process;
process is
variable i : integer;
attribute a : boolean;
attribute a of i : signal is true; -- Error
begin
end process;
process is
variable x : integer;
begin
assert x'last_event = 0 ns; -- Error
end process;
process is
type bv_ptr is access bit_vector;
variable a : bv_ptr;
type r is record
x : integer;
end record;
variable b : r;
begin
a(a'range) := "110101"; -- OK
a(bit_vector'range) := "110101"; -- Error
a(b'range) := "101010"; -- Error
a(e'range) := "110101"; -- Error
end process;
process is
function func(x : integer) return bit_vector;
variable a : bit_vector(1 to 10);
begin
a(func(4)'range) := (others => '1'); -- OK
end process;
process is
type bvptr is access bit_vector;
variable b : bvptr;
begin
for i in b.all'range loop -- OK
end loop;
for i in b'range loop -- OK
end loop;
end process;
end architecture;
|
gpl-3.0
|
695bae04c96395900f05e4d07cc91554
| 0.522613 | 3.851613 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare9.vhd
| 1 | 4,435 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare9.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare9 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare9;
ARCHITECTURE SYN OF lpm_compare9 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "100011100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "284"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 284 0 0 9 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare9.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare9.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare9.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare9.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare9_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
ef7ccb13a2a75cae1c4f1e3f1cb1f801
| 0.655017 | 3.689684 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab4.vhd
| 5 | 740 |
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
gpl-3.0
|
7f9d797f12418b1ea97113fd898ddf9d
| 0.413514 | 3.874346 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/mix/inst_a_e-rtl-a.vhd
| 1 | 3,353 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_aa_e -- vhdl udc test for inst_aa_i
-- No Generated Generics
-- Generated Generics for Entity inst_aa_e
-- End of Generated Generics for Entity inst_aa_e
port (
-- Generated Port for Entity inst_aa_e
port_xa_i : in std_ulogic; -- tie to low to create port
port_xa_o : out std_ulogic -- signal test aa to ba
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e -- vhdl udc test for inst_ab_i
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
port_ab_i : in std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
udc: THIS GOES TO BODY of inst_a_i;
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
p_mix_signal_aa_ba_go <= signal_aa_ba; -- __I_O_BIT_PORT
signal_bb_ab <= p_mix_signal_bb_ab_gi; -- __I_I_BUS_PORT
--
-- Generated Instances and Port Mappings
--
udc: pre_inst_udc for VHDL goes into inst_a_i
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_aa_e -- vhdl udc test for inst_aa_i
port map (
port_xa_i => mix_logic0_0, -- tie to low to create port
port_xa_o => signal_aa_ba -- signal test aa to ba
);
-- End of Generated Instance Port Map for inst_aa_i
udc: post_inst_udc VHDL for inst_aa_i goes into inst_a_i
udc: pre_inst_udc for VHDL inst_ab_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab_e -- vhdl udc test for inst_ab_i
port map (
port_ab_i => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_ab_i
udc: post_inst_udc VHDL for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
5d9f455cb99a966ac6537fb11d252aaa
| 0.614375 | 2.9594 | false | true | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter11.vhd
| 1 | 4,161 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter11.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter11 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_counter11;
ARCHITECTURE SYN OF lpm_counter11 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 8
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
6bbc2a356b94b2548883815de9bd4a8b
| 0.652247 | 3.748649 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/arg_mem_bank_v6.vhd
| 1 | 9,868 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : arg_mem_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.asymmetric_dp_bank_v6;
use axis_accelerator_adapter_v2_1_6.symmetric_dp_bank_v6;
use axis_accelerator_adapter_v2_1_6.dp_bank_sdp_v6;
entity arg_mem_bank_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_PRINT_INFO : boolean := false;
C_IS_UNIDIR : integer range 0 to 1 := 0;
C_OPORT_AWIDTH : integer;
C_OPORT_DWIDTH : integer;
C_IPORT_AWIDTH : integer;
C_IPORT_DWIDTH : integer);
port (
rst : in std_logic;
oport_clk : in std_logic;
oport_ce : in std_logic;
oport_we : in std_logic;
oport_addr : in std_logic_vector(C_OPORT_AWIDTH-1 downto 0);
oport_din : in std_logic_vector(C_OPORT_DWIDTH-1 downto 0);
oport_dout : out std_logic_vector(C_OPORT_DWIDTH-1 downto 0);
iport_clk : in std_logic;
iport_ce : in std_logic;
iport_we : in std_logic;
iport_addr : in std_logic_vector(C_IPORT_AWIDTH-1 downto 0);
iport_din : in std_logic_vector(C_IPORT_DWIDTH-1 downto 0);
iport_dout : out std_logic_vector(C_IPORT_DWIDTH-1 downto 0));
end arg_mem_bank_v6;
architecture rtl of arg_mem_bank_v6 is
function calc_use_sdp(is_unidir : natural) return integer is
variable use_sdp : integer;
begin
if(C_IS_UNIDIR = 0) then
use_sdp := 0;
else
use_sdp := 0;
if(C_OPORT_DWIDTH = 64 and C_IPORT_DWIDTH <= 64 and C_OPORT_AWIDTH <= 9) then
-- SDP, WR port 64 bits
use_sdp := 1;
elsif(C_IPORT_DWIDTH = 64 and C_OPORT_DWIDTH <= 64 and C_IPORT_AWIDTH <= 9) then
-- SDP, RD port 64 bits
use_sdp := 1;
end if;
end if;
return use_sdp;
end function calc_use_sdp;
constant USE_SDP : integer := calc_use_sdp(C_IS_UNIDIR);
begin
WR_PORT_WIDER_GEN : if (C_IPORT_DWIDTH > C_OPORT_DWIDTH) generate
begin
USE_SDP_GEN : if (use_sdp /= 0) generate
begin
BANK_I : entity axis_accelerator_adapter_v2_1_6.dp_bank_sdp_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_SDP_WIDE => 1,
C_RD_AWIDTH => C_OPORT_AWIDTH,
C_RD_DWIDTH => C_OPORT_DWIDTH,
C_WR_AWIDTH => C_IPORT_AWIDTH,
C_WR_DWIDTH => C_IPORT_DWIDTH)
port map (
rst => rst,
rd_clk => oport_clk,
rd_en => oport_ce,
rd_addr => oport_addr,
dout => oport_dout,
wr_clk => iport_clk,
wr_en => iport_ce,
wr_addr => iport_addr,
din => iport_din);
iport_dout <= (others => '0');
end generate USE_SDP_GEN;
DONT_USE_SDP_GEN : if (use_sdp = 0) generate
begin
-- Port A is always the wider port
BANK_I : entity axis_accelerator_adapter_v2_1_6.asymmetric_dp_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_BANK_AWIDTH_A => C_IPORT_AWIDTH,
C_BANK_DWIDTH_A => C_IPORT_DWIDTH,
C_BANK_AWIDTH_B => C_OPORT_AWIDTH,
C_BANK_DWIDTH_B => C_OPORT_DWIDTH)
port map (
rst => rst,
clk_a => iport_clk,
ce_a => iport_ce,
we_a => iport_we,
addr_a => iport_addr,
din_a => iport_din,
dout_a => iport_dout,
clk_b => oport_clk,
ce_b => oport_ce,
we_b => oport_we,
addr_b => oport_addr,
din_b => oport_din,
dout_b => oport_dout);
end generate DONT_USE_SDP_GEN;
end generate WR_PORT_WIDER_GEN;
---------------------------------------------------------------------------------------
WR_PORT_NARROWER_GEN : if (C_IPORT_DWIDTH < C_OPORT_DWIDTH) generate
begin
USE_SDP_GEN : if (use_sdp /= 0) generate
begin
BANK_I : entity axis_accelerator_adapter_v2_1_6.dp_bank_sdp_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_SDP_WIDE => 0,
C_RD_AWIDTH => C_OPORT_AWIDTH,
C_RD_DWIDTH => C_OPORT_DWIDTH,
C_WR_AWIDTH => C_IPORT_AWIDTH,
C_WR_DWIDTH => C_IPORT_DWIDTH)
port map (
rst => rst,
rd_clk => oport_clk,
rd_en => oport_ce,
rd_addr => oport_addr,
dout => oport_dout,
wr_clk => iport_clk,
wr_en => iport_ce,
wr_addr => iport_addr,
din => iport_din);
iport_dout <= (others => '0');
end generate USE_SDP_GEN;
DONT_USE_SDP_GEN : if (use_sdp = 0) generate
begin
-- Port A is always the wider port
BANK_I : entity axis_accelerator_adapter_v2_1_6.asymmetric_dp_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_BANK_AWIDTH_B => C_IPORT_AWIDTH,
C_BANK_DWIDTH_B => C_IPORT_DWIDTH,
C_BANK_AWIDTH_A => C_OPORT_AWIDTH,
C_BANK_DWIDTH_A => C_OPORT_DWIDTH)
port map (
rst => rst,
clk_b => iport_clk,
ce_b => iport_ce,
we_b => iport_we,
addr_b => iport_addr,
din_b => iport_din,
dout_b => iport_dout,
clk_a => oport_clk,
ce_a => oport_ce,
we_a => oport_we,
addr_a => oport_addr,
din_a => oport_din,
dout_a => oport_dout);
end generate DONT_USE_SDP_GEN;
end generate WR_PORT_NARROWER_GEN;
SAME_WIDTH_GEN : if (C_OPORT_DWIDTH = C_IPORT_DWIDTH) generate
begin
BANK_I : entity axis_accelerator_adapter_v2_1_6.symmetric_dp_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_BANK_AWIDTH => C_OPORT_AWIDTH,
C_BANK_DWIDTH => C_OPORT_DWIDTH)
port map (
rst => rst,
clk_a => oport_clk,
ce_a => oport_ce,
we_a => oport_we,
addr_a => oport_addr,
din_a => oport_din,
dout_a => oport_dout,
clk_b => iport_clk,
ce_b => iport_ce,
we_b => iport_we,
addr_b => iport_addr,
din_b => iport_din,
dout_b => iport_dout);
end generate SAME_WIDTH_GEN;
end rtl;
|
mit
|
2c67287f5d1c9a677f212333c3b94804
| 0.541143 | 3.679344 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/mmio.vhd
| 1 | 3,465 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psl.all;
use work.mmio_package.all;
entity mmio is
port (
i : in mmio_in;
o : out mmio_out
);
end entity mmio;
architecture logic of mmio is
signal q, r : mmio_int;
begin
comb : process(all)
variable v : mmio_int;
begin
----------------------------------------------------------------------------------------------------------------------- default assignments
v := r;
v.reg := i.ac.data;
----------------------------------------------------------------------------------------------------------------------- parse inputs
v.cfg_read := i.ha.val and i.ha.cfg and i.ha.rnw;
v.cfg_write := i.ha.val and i.ha.cfg and not i.ha.rnw;
v.mmio_dw := i.ha.dw;
v.mmio_write := i.ha.val and not i.ha.cfg and not i.ha.rnw;
v.mmio_read := i.ha.val and not i.ha.cfg and i.ha.rnw;
----------------------------------------------------------------------------------------------------------------------- afu descriptor
-- register offset x'0 : reg_prog_model and num_of_processes
if i.ha.ad(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0) = 24x"0" then
v.cfg_data := AFUD_0;
-- register offset x'30' : per_process_psa_control
elsif i.ha.ad(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0) = 24x"c" then
v.cfg_data := AFUD_30;
else
v.cfg_data := (others => '0');
end if;
----------------------------------------------------------------------------------------------------------------------- write
if v.mmio_write then
case i.ha.ad is
-- debug data
when MMIO_REG_ADDRESS =>
v.reg := i.ha.data;
when others => null;
end case;
end if;
----------------------------------------------------------------------------------------------------------------------- read
-- afu descriptor double word
if r.cfg_read and r.mmio_dw then
v.mmio_rdata := v.cfg_data;
-- afu descriptor word
elsif r.cfg_read and i.ha.ad(0) then
v.mmio_rdata := v.cfg_data(PSL_WORD_WIDTH - 1 downto 0) & v.cfg_data(PSL_WORD_WIDTH - 1 downto 0);
-- afu descriptor other word
elsif r.cfg_read then
v.mmio_rdata := v.cfg_data(PSL_WORD_WIDTH - 1 downto 0) & v.cfg_data(PSL_WORD_WIDTH - 1 downto 0);
-- read register double word
elsif r.mmio_read and r.mmio_dw then
case i.ha.ad is
-- debug data
when MMIO_REG_ADDRESS =>
v.mmio_rdata := v.reg;
when others => null;
end case;
else
v.mmio_rdata := (others => '0');
end if;
----------------------------------------------------------------------------------------------------------------------- output
v.ack := r.cfg_read or r.cfg_write or r.mmio_read or r.mmio_write;
q <= v;
o.ah.ack <= r.ack;
o.ah.data <= r.mmio_rdata;
end process;
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(i.cr)
begin
if rising_edge(i.cr.clk) then
if i.cr.rst then
mmio_reset(r);
else
r <= q;
end if;
end if;
end process;
end architecture logic;
|
bsd-2-clause
|
caeb7679982411e3364a8f16e06d2363
| 0.403752 | 4.081272 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter0.vhd
| 1 | 4,268 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (16 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(16 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 72000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 17
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "72000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "17"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "72000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 17 0 OUTPUT NODEFVAL "q[16..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 17 0 @q 0 0 17 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
816eaab2f1f8230df336634533cdfbf2
| 0.653702 | 3.737303 | false | false | false | false |
mitchsm/nvc
|
test/regress/fact.vhd
| 5 | 899 |
entity fact_gen is
port (
question : in integer;
answer : out integer );
end entity;
architecture behav of fact_gen is
begin
process (question) is
variable tmp : integer;
begin
tmp := 1;
for i in 1 to question loop
tmp := tmp * i;
end loop;
answer <= tmp;
end process;
end architecture;
-------------------------------------------------------------------------------
entity fact is
end entity;
architecture test of fact is
signal question, answer : integer;
begin
uut: entity work.fact_gen
port map (
question => question,
answer => answer );
process is
begin
for i in 1 to 15 loop
question <= i;
wait on answer;
report integer'image(answer);
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
58590dd8f50e0722621a2727082d2c10
| 0.499444 | 4.731579 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_4_3/sim/zc702_proc_sys_reset_4_3.vhd
| 1 | 5,843 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_4_3 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_4_3;
ARCHITECTURE zc702_proc_sys_reset_4_3_arch OF zc702_proc_sys_reset_4_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_4_3_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_4_3_arch;
|
mit
|
99dd56f540ada47c3aa7e1b6bbd25ad1
| 0.706144 | 3.575887 | false | false | false | false |
mitchsm/nvc
|
test/simp/issue155.vhd
| 3 | 419 |
package issue155 is
type W_TYPE is record
A : integer;
B : integer;
C : integer;
end record;
constant W : W_TYPE := (A => 8, B => 4, C => 2);
signal A : bit_vector(W.A-1 downto 0);
signal B : bit_vector(W.B-1 downto 0);
signal C : bit_vector(W.C-1 downto 0);
constant V : W_TYPE := (1, 2, 3);
signal D : bit_vector(V.C-1 downto V.A);
end package;
|
gpl-3.0
|
87b8de3b9d743b6f5d5212be8bba5fe5
| 0.522673 | 2.93007 | false | false | false | false |
mitchsm/nvc
|
test/perf/bigram.vhd
| 5 | 3,098 |
package util is
function log2(x : in integer) return integer;
end package;
package body util is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity memory is
generic (
WIDTH : integer;
DEPTH : integer );
port (
clk : in std_logic;
addr : in unsigned(log2(DEPTH) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic );
end entity;
architecture rtl of memory is
type ram_t is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal addr_r : unsigned(log2(DEPTH) - 1 downto 0);
signal ram : ram_t;
begin
reg: process (clk) is
begin
if rising_edge(clk) then
addr_r <= addr;
if we = '1' then
ram(to_integer(addr)) <= din;
end if;
end if;
end process;
dout <= ram(to_integer(addr_r));
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity bigram is
end entity;
architecture test of bigram is
constant ITERS : integer := 100;
constant WIDTH : integer := 1024;
constant DEPTH : integer := 1024;
signal clk : std_logic := '0';
signal addr : unsigned(log2(DEPTH) - 1 downto 0);
signal din : std_logic_vector(WIDTH - 1 downto 0);
signal dout : std_logic_vector(WIDTH - 1 downto 0);
signal we : std_logic := '1';
signal running : boolean := true;
begin
clk <= not clk after 5 ns when running else '0';
uut: entity work.memory
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH )
port map (
clk => clk,
addr => addr,
din => din,
dout => dout,
we => we );
stim: process is
begin
for j in 1 to ITERS loop
wait for 20 ns;
we <= '1';
for i in 0 to DEPTH - 1 loop
addr <= to_unsigned(i, addr'length);
din <= std_logic_vector(to_unsigned((i + j) mod DEPTH, WIDTH));
wait for 10 ns;
end loop;
we <= '0';
for i in 0 to DEPTH - 1 loop
addr <= to_unsigned(i, addr'length);
wait for 10 ns;
assert dout = std_logic_vector(to_unsigned((i + j) mod DEPTH, WIDTH));
end loop;
end loop;
running <= false;
wait;
end process;
end architecture;
|
gpl-3.0
|
fb26642a0db4b4ad23d8010f2b58324c
| 0.494835 | 3.961637 | false | false | false | false |
mitchsm/nvc
|
lib/std/textio.vhd
| 3 | 14,567 |
--
-- TEXTIO package as defined by IEEE 1076-1993
--
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
procedure readline (file f: text; l: inout line);
procedure read (l : inout line;
value : out bit;
good : out boolean );
procedure read (l : inout line;
value : out bit );
procedure read (l : inout line;
value : out bit_vector;
good : out boolean );
procedure read (l : inout line;
value : out bit_vector );
procedure read (l : inout line;
value : out boolean;
good : out boolean );
procedure read (l : inout line;
value : out boolean );
procedure read (l : inout line;
value : out character;
good : out boolean );
procedure read (l : inout line;
value : out character );
procedure read (l : inout line;
value : out integer;
good : out boolean );
procedure read (l : inout line;
value : out integer );
procedure read (l : inout line;
value : out real;
good : out boolean );
procedure read (l : inout line;
value : out real );
procedure read (l : inout line;
value : out string;
good : out boolean );
procedure read (l : inout line;
value : out string );
procedure read (l : inout line;
value : out time;
good : out boolean );
procedure read (l : inout line;
value : out time );
procedure writeline (file f : text; l : inout line);
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 );
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns );
end package;
package body textio is
procedure grow (l : inout line;
extra : in natural;
old_size : out natural ) is
variable tmp : line;
begin
if l = null then
l := new string(1 to extra);
old_size := 0;
elsif extra > 0 then
old_size := l'length;
tmp := new string(1 to l'length + extra);
tmp(1 to l'length) := l.all;
deallocate(l);
l := tmp;
end if;
end procedure;
procedure shrink (l : inout line; size : in natural) is
variable tmp : line;
begin
assert l /= null;
assert size < l'length;
tmp := new string(1 to size);
tmp.all := l.all(1 to size);
deallocate(l);
l := tmp;
end procedure;
procedure consume (l : inout line; nchars : in natural) is
variable tmp : line;
begin
assert l /= null;
if nchars = l'length then
tmp := new string'("");
else
assert nchars <= l'length;
tmp := new string(1 to l'length - nchars);
tmp.all := l.all(1 + nchars to l'length);
end if;
deallocate(l);
l := tmp;
end procedure;
function max (a, b : integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
procedure read (l : inout line;
value : out bit;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out bit )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit read failed";
end procedure;
procedure read (l : inout line;
value : out bit_vector;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out bit_vector )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit_vector read failed";
end procedure;
procedure read (l : inout line;
value : out boolean;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out boolean )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "boolean read failed";
end procedure;
procedure read (l : inout line;
value : out character;
good : out boolean ) is
begin
if l'length > 0 then
value := l.all(1);
consume(l, 1);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out character )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "character read failed";
end procedure;
procedure read (l : inout line;
value : out integer;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out integer )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "integer read failed";
end procedure;
procedure read (l : inout line;
value : out real;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out real )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "real read failed";
end procedure;
procedure read (l : inout line;
value : out string;
good : out boolean ) is
begin
if value'length <= l'length then
value := l.all(1 to value'length);
consume(l, value'length);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out string )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "string read failed";
end procedure;
procedure read (l : inout line;
value : out time;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out time )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "time read failed";
end procedure;
procedure readline (file f: text; l: inout line) is
variable tmp : line;
variable ch : string(1 to 1);
variable used : natural;
variable got : integer;
begin
if l /= null then
deallocate(l);
end if;
tmp := new string(1 to 128);
loop
exit when endfile(f);
read(f, ch, got);
exit when got /= 1;
next when ch(1) = CR;
if ch(1) = LF then
exit;
else
if used = tmp'length then
grow(tmp, 128, used);
end if;
used := used + 1;
tmp(used) := ch(1);
end if;
end loop;
if used = 0 then
l := new string'("");
else
shrink(tmp, used);
l := tmp;
end if;
end procedure;
procedure writeline (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
l := new string'("");
end procedure;
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 )
is
variable orig : natural;
variable width : natural;
begin
width := max(value'length, field);
grow(l, width, orig);
if justified = left then
l(orig + 1 to orig + value'length) := value;
for i in orig + value'length + 1 to orig + width loop
l(i) := ' ';
end loop;
else
for i in orig + 1 to orig + width - value'length loop
l(i) := ' ';
end loop;
l(orig + 1 + width - value'length to orig + width) := value;
end if;
end procedure;
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, string'(1 => value), justified, field);
end procedure;
function bit_to_char (b : bit) return character is
type table_t is array (bit) of character;
constant table : table_t := ( '0' => '0',
'1' => '1' );
begin
return table(b);
end function;
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, bit_to_char(value), justified, field);
end procedure;
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 )
is
variable s : string(1 to value'length);
alias v : bit_vector(1 to value'length) is value;
begin
for i in s'range loop
s(i) := bit_to_char(v(i));
end loop;
write(l, s, justified, field);
end procedure;
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, boolean'image(value), justified, field);
end procedure;
function unit_string (unit : time) return string is
begin
-- Standard requires unit in lower case
if unit = fs then
return " fs";
elsif unit = ps then
return " ps";
elsif unit = ns then
return " ns";
elsif unit = us then
return " us";
elsif unit = ms then
return " ms";
elsif unit = sec then
return " sec";
elsif unit = min then
return " min";
elsif unit = hr then
return " hr";
else
report "invalid unit " & time'image(unit);
end if;
end function;
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns )
is
-- TODO: this overflows for large unit or value
constant value_fs : integer := value / fs;
constant unit_fs : integer := unit / fs;
begin
if (value_fs rem unit_fs) = 0 then
write(l, integer'image(value_fs / unit_fs) & unit_string(unit),
justified, field);
else
write(l, real'image(real(value_fs) / real(unit_fs)) &
unit_string(unit), justified, field);
end if;
end procedure;
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, integer'image(value), justified, field);
end procedure;
end package body;
|
gpl-3.0
|
e101b32a9305d8113a8c6e104c708d62
| 0.457747 | 4.749592 | false | false | false | false |
blutsvente/MIX
|
test/results/configuration/cmdline/ent_t-rtl-a.vhd
| 1 | 6,206 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
component ent_c
-- No Generated Generics
-- Generated Generics for Entity ent_c
-- End of Generated Generics for Entity ent_c
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: ent_c
;
-- End of Generated Instance Port Map for inst_c
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
ce7ffa4b61078f6cb5b3e423052c956c
| 0.638092 | 2.828624 | false | false | false | false |
mitchsm/nvc
|
test/sem/const.vhd
| 5 | 1,268 |
entity e is
end entity;
architecture a of e is
constant x : integer := 5;
function f_pure(n : in integer) return integer is
begin
return n + 1;
end function;
impure function f_impure return integer is
begin
return x;
end function;
signal s : integer;
begin
process is
variable v : integer;
begin
v := x; -- OK
x := v; -- Error
end process;
process is
constant c : integer; -- Error
begin
end process;
process is
constant c : integer := f_pure(5); -- OK
begin
end process;
process is
constant c : integer := f_impure; -- OK (LRM 93 7.4.2 note 2)
begin
end process;
end architecture;
-------------------------------------------------------------------------------
package p is
constant c : integer; -- OK
constant d : integer;
constant e : integer := c + 1; -- OK
constant f : integer;
end package;
package body p is
constant c : integer := 6; -- OK
constant c : integer := 6; -- Error
constant f : bit := '1'; -- Error
-- Missing definition for d
end package body;
|
gpl-3.0
|
dcc0f3b22f376511373057c62b30aa6b
| 0.48265 | 4.449123 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/connport/inst_ea_e-rtl-a.vhd
| 1 | 5,504 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-a.vhd,v 1.2 2006/06/22 07:20:00 wig Exp $
-- $Date: 2006/06/22 07:20:00 $
-- $Log: inst_ea_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:20:00 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ea_e
--
architecture rtl of inst_ea_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eaa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eaa_e
unsplice_a1 : in std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : in std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : in std_ulogic_vector(100 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : in std_ulogic_vector(97 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : in std_ulogic_vector(99 downto 2); -- connect mid 100 bits
unsplice_bad_a : in std_ulogic_vector(1 downto 0);
unsplice_bad_b : in std_ulogic_vector(3 downto 0) -- # conflict
-- End of Generated Port for Entity inst_eaa_e
);
end component;
-- ---------
component inst_eab_e
-- No Generated Generics
-- Generated Generics for Entity inst_eab_e
-- End of Generated Generics for Entity inst_eab_e
-- No Generated Port
end component;
-- ---------
component inst_eac_e
-- No Generated Generics
-- Generated Generics for Entity inst_eac_e
-- End of Generated Generics for Entity inst_eac_e
-- No Generated Port
end component;
-- ---------
component inst_ead_e
-- No Generated Generics
-- Generated Generics for Entity inst_ead_e
-- End of Generated Generics for Entity inst_ead_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal unsplice_a1 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
unsplice_a1(127) <= p_mix_unsplice_a1_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a1(125 downto 0) <= p_mix_unsplice_a1_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eaa
inst_eaa: inst_eaa_e
port map (
unsplice_a1(1 downto 0) => unsplice_a1(1 downto 0), -- leaves 3 unconnected
unsplice_a1(127 downto 4) => unsplice_a1(125 downto 2), -- leaves 3 unconnected
unsplice_a1(2) => unsplice_a1(127), -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
unsplice_bad_b(1 downto 0) => unsplice_bad_b(1 downto 0), -- # conflict
unsplice_bad_b(3 downto 2) => unsplice_bad_b(1 downto 0) -- # conflict
);
-- End of Generated Instance Port Map for inst_eaa
-- Generated Instance Port Map for inst_eab
inst_eab: inst_eab_e
;
-- End of Generated Instance Port Map for inst_eab
-- Generated Instance Port Map for inst_eac
inst_eac: inst_eac_e
;
-- End of Generated Instance Port Map for inst_eac
-- Generated Instance Port Map for inst_ead
inst_ead: inst_ead_e
;
-- End of Generated Instance Port Map for inst_ead
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
0cde969974555d52be5241933d59f50e
| 0.646802 | 2.988056 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/RAM1_Visitor.vhd
| 2 | 5,065 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM1_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: in std_logic_vector(15 downto 0);
TSRE: in std_logic;
TBRE: in std_logic;
---output
RAM1_Enable: out std_logic := '1';
RAM1_ReadEnable: out std_logic := '1';
RAM1_WriteEnable: out std_logic := '1';
SPort_WriteEnable:out std_logic := '1';
SPort_ReadEnable: out std_logic := '1';
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
end RAM1_Visitor;
architecture behavior of RAM1_Visitor is
signal tempMemData:std_logic_vector(15 downto 0);
signal tempMemDataSrc: std_logic_vector(1 downto 0);
signal tempRAM1_Enable :std_logic;
signal tempSPort_WriteEnable:std_logic;
signal tempSPort_ReadEnable:std_logic;
signal tempRAM1_ReadEnable:std_logic;
signal tempRAM1_WriteEnable:std_logic;
begin
process(DMemData,EXandMEM_AluRes,DataReady,TSRE, TBRE)
variable temp:std_logic_vector(15 downto 0);
begin
if EXandMEM_AluRes = COM_STATUS_ADDR then
temp:= "0000000000000001";
temp(0):= TSRE and TBRE;
temp(1):= DataReady;
tempMemData <= temp;
elsif EXandMEM_AluRes = COM_DATA_ADDR then
tempMemData <= DMemData;--AcqPortData;
else
tempMemData <= DMemData;--AcqMemoryData;
end if;
end process;
process(EXandMEM_AluRes, DMemReadWrite)
begin
if DMemReadWrite = MEM_READ then
if (EXandMEM_AluRes = COM_DATA_ADDR) then
tempMemDataSrc <= "00"; ------port
elsif (EXandMEM_AluRes = COM_STATUS_ADDR) then
tempMemDataSrc <= "11"; -- port status
elsif EXandMEM_AluRes < DATA_MEM_BEGIN then
tempMemDataSrc <="01"; ---------RAM2
else
tempMemDataSrc <="10"; ---------RAM1
end if;
elsif DMemReadWrite = MEM_WRITE then
if (EXandMEM_AluRes = COM_DATA_ADDR) then
tempMemDataSrc <= "00"; ------port data
elsif (EXandMEM_AluRes = COM_STATUS_ADDR) then
tempMemDataSrc <= "11"; -- port status
elsif EXandMEM_AluRes < DATA_MEM_BEGIN then
tempMemDataSrc <="01"; ---------RAM2
else
tempMemDataSrc <="10"; ---------RAM1
end if;
else
tempMemDataSrc <= "10";
end if;
end process;
process(EXandMEM_AluRes, DMemReadWrite, tempMemDataSrc, writeData, tempMemData)
begin
if DMemReadWrite = MEM_READ then
if tempMemDataSrc = "00" then
DMemData <= "ZZZZZZZZZZZZZZZZ";
DMemAddr <= EXandMEM_AluRes;
elsif tempMemDataSrc = "11" then
DMemData <= tempMemData;
DMemAddr <= EXandMEM_AluRes;
elsif tempMemDataSrc = "10" then
DMemData <= "ZZZZZZZZZZZZZZZZ";
DMemAddr <= EXandMEM_AluRes;
elsif tempMemDataSrc = "01" then
DMemData <= "ZZZZZZZZZZZZZZZZ";
DMemAddr <= EXandMEM_AluRes;
else
DMemData <= "ZZZZZZZZZZZZZZZZ";
end if;
elsif DMemReadWrite = MEM_WRITE then
if tempMemDataSrc = "00" then
DMemData <= writeData;
DMemAddr <= EXandMEM_AluRes;
elsif tempMemDataSrc = "10" then
DMemData <= writeData;
DMemAddr <= EXandMEM_AluRes;
elsif tempMemDataSrc = "01" then
DMemData <= writeData;
DMemAddr <= EXandMEM_AluRes;
else
DMemData <= "ZZZZZZZZZZZZZZZZ";
end if;
else
DMemData <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
RAM1_Enable <=tempRAM1_Enable;
SPort_WriteEnable <= tempSPort_WriteEnable;
SPort_ReadEnable <= tempSPort_ReadEnable;
RAM1_ReadEnable <= tempRAM1_ReadEnable;
RAM1_WriteEnable <= tempRAM1_WriteEnable;
process(clk, EXandMEM_AluRes, DMemReadWrite, tempMemDataSrc)
begin
if clk = '0' then
if EXandMEM_AluRes = COM_DATA_ADDR then
tempRAM1_Enable <= '1';
tempRAM1_ReadEnable <= '1';
tempRAM1_WriteEnable <= '1';
if DMemReadWrite = MEM_READ then
tempSport_ReadEnable <= '0';
tempSport_WriteEnable <= '1';
elsif DMemReadWrite = MEM_WRITE then
tempSport_ReadEnable <= '1';
tempSport_WriteEnable <= '0';
else
tempSport_ReadEnable <= '1';
tempSport_WriteEnable <= '1';
end if;
elsif tempMemDataSrc = "10" then ---------------------RAM1
tempRAM1_Enable <= '0';
tempSPort_WriteEnable <= '1';
tempSPort_ReadEnable <= '1';
if DMemReadWrite = MEM_READ then
tempRAM1_ReadEnable <= '0';
tempRAM1_WriteEnable <= '1';
elsif DMemReadWrite = MEM_WRITE then
tempRAM1_ReadEnable <= '1';
tempRAM1_WriteEnable <= '0';
else
tempRAM1_ReadEnable <= '1';
tempRAM1_WriteEnable <= '1';
end if;
else
tempRAM1_Enable <= '1';
tempSPort_WriteEnable <= '1';
tempSPort_ReadEnable <= '1';
tempRAM1_ReadEnable <= '1';
tempRAM1_WriteEnable <= '1';
end if;
elsif clk = '1' then
tempRAM1_Enable <= '1';
tempSPort_WriteEnable <= '1';
tempSPort_ReadEnable <= '1';
tempRAM1_ReadEnable <= '1';
tempRAM1_WriteEnable <= '1';
end if;
end process;
end behavior;
|
apache-2.0
|
0bdf07304f86f82f0d27321d96c504e5
| 0.654294 | 3.497928 | false | false | false | false |
mitchsm/nvc
|
test/sem/func.vhd
| 4 | 6,787 |
package func is
function sum(x, y, z : in integer) return integer;
function invalid(x : out integer) return integer; -- Error
type uenum is (A, B, C);
type uenum_vector is array (integer range <>) of uenum;
function resolved(v : uenum_vector) return uenum;
subtype enum is resolved uenum;
subtype enum_ab is resolved uenum range A to B;
function resolved2(v : uenum) return uenum;
subtype enum_bad1 is resolved2 uenum; -- Error
function resolved3(v : uenum; x : integer) return uenum;
subtype enum_bad2 is resolved3 uenum; -- Error
subtype enum_bad3 is uenum uenum; -- Error
function default(x : in uenum := 6) return uenum; -- Error
function foo return integer is -- Error
begin
return 4;
end function;
end package;
package body bad is -- Error
end package body;
package body func is
function sum(x, y, z : in integer) return integer is
begin
return x + y; -- OK
end function;
function test1(x : integer) return integer is
begin
return A; -- Wrong return type
end function;
function test2(x : out integer) return integer is -- Invalid mode
begin
return 0;
end function;
function test3(x : integer) return integer is
begin
null; -- Missing return statement
end function;
function foo(x, y, z : in integer) return integer;
function foo(x, y, z : in integer) return integer; -- Duplicate
function test4(x : uenum_vector) return uenum is
begin
return x(x'low);
end function;
function test5(x, y : uenum) return uenum is
type uenum2d is array (uenum, uenum) of uenum;
constant table : uenum2d :=
( ( A, A, A ),
( A, B, C ),
( A, C, B ) );
begin
return table(x, y);
end function;
function test6(x : uenum_vector) return uenum_vector is
variable tmp : uenum_vector(1 to x'length);
begin
for i in tmp'range loop
tmp(i) := A;
end loop;
return tmp;
end function;
function test7(x : uenum_vector) return uenum_vector is
subtype rtype is uenum_vector(x'length downto 0);
variable r : rtype;
begin
return r;
end function;
function test8(x : uenum) return uenum_vector is
begin
return test7((1 to 3 => x));
end function;
function default2(y : in integer := 6) return integer is
begin
return y * 2;
end function;
function test9 return integer is
begin
return default2;
end function;
function test10(k : in integer) return integer is
variable v : integer;
variable u : uenum;
begin
v := sum(x => 4, 1); -- Error
v := sum(1, x => 4, x => 4); -- Error
v := sum(1, y => k, z => 4); -- OK
u := resolved3(A, x => 4); -- OK
u := resolved3(x => 3, v => B); -- OK
return v;
end function;
function test11(constant c : in bit) return bit; -- OK
function test12(variable v : in bit) return bit; -- Error
type ft is file of bit;
function test13(file f : ft) return bit; -- OK
function test14(signal s : bit) return bit; -- OK
procedure modify(variable b : inout bit) is
begin
b := '1';
end procedure;
function test15(file f : ft) return bit is
variable b : bit;
begin
read(f, b); -- OK
return b;
end function;
function test16(x : in bit) return bit is
begin
modify(x); -- Error
return x;
end function;
impure function test17(x : in bit) return bit is
begin
if now = 10 ns then
return '1';
else
return '0';
end if;
end function;
function test18(x : in bit) return bit is
begin
return not test17(x); -- Error, test18 not impure
end function;
type int_ptr is access integer;
function test19(x : in int_ptr) return integer; -- Error
function recur(x : in integer) return integer is
begin
if x = 0 then
return 1;
else
return x * recur(x - 1);
end if;
end function;
function test20(x : integer := 5; y : real) return integer is
variable k : integer;
begin
k := test20(6.5); -- Error
k := test20(5); -- Error
k := test20(y => 7); -- Error
return k;
end function;
function test21a(x : string) return integer;
function test21a(x : bit_vector) return integer;
function test21 return integer is
begin
return test21a(';' & LF); -- OK
end function;
function test22a(x : integer) return integer is
begin
return x + 1;
end function;
function test22a(x : integer) return real is
begin
return real(x) + 1.0;
end function;
function test22 return integer is
begin
assert test22a(1) = 2;
assert test22a(1) = 2.0;
return 1;
end function;
impure function test23 return integer is
variable x : integer;
impure function sub(y : in integer) return integer is
begin
return x + y;
end function;
begin
x := 5;
return sub(2);
end function;
function test24f(x : integer; r : real := 1.0) return integer;
function test24f(y : integer; b : boolean := true) return integer;
function test24 return integer is
begin
return test24f(x => 1) + test24f(y => 2);
end function;
end package body;
package func2 is
procedure test25(constant x : integer);
end package;
package body func2 is
procedure test25(variable x : integer) is -- Error
begin
end procedure;
function test26(signal x : integer) return integer;
function test26(x : integer) return integer is -- Error
begin
return 1;
end function;
end package body;
package func3 is
end package;
package body func3 is
-- default class should be treated identically to constant class
-- (ie, this should not produce an error)
function issue182(bitv : bit_vector) return integer is
function nested_fun return integer is
begin
return bitv'length;
end function;
begin
return nested_fun;
end function;
function issue123(signal x : integer) return integer is
function nested return integer is
begin
return x + 1; -- Error
end function;
begin
return nested;
end function;
end package body;
|
gpl-3.0
|
d1fa8d69a4744d8d4b55541ddce9ebe8
| 0.572123 | 4.05194 | false | true | false | false |
mitchsm/nvc
|
test/simp/ffold.vhd
| 3 | 2,029 |
package pack is
function add4(x : in integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
signal s1 : integer := add1(5);
signal s2 : integer := add4(1);
signal s3 : integer := log2(11);
signal s4 : integer := log2(integer(real'(5.5)));
signal s5 : integer := case1(1);
signal s6 : integer := case1(7);
signal s7 : integer := adddef;
signal s8 : boolean := chain2("foo", "hello");
begin
end architecture;
|
gpl-3.0
|
e0c9d81a2325dd9c47b03e35413c9301
| 0.502711 | 4.090726 | false | false | false | false |
mitchsm/nvc
|
test/regress/block1.vhd
| 5 | 591 |
entity block1 is
end entity;
architecture test of block1 is
signal u, v, w: integer;
begin
process is
begin
u <= 1;
wait for 1 ns;
u <= 2;
wait;
end process;
a: block is
signal x : integer;
begin
x <= u + 2;
v <= x;
end block;
b: block is
signal x : integer;
begin
x <= v + 6;
w <= x;
end block;
process is
begin
wait for 1 ns;
assert w = 9;
wait for 1 ns;
assert w = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
231bf420bdf73396cce7fcdee3bb3abd
| 0.460237 | 3.788462 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd
| 6 | 22,296 |
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_8;
use proc_sys_reset_v5_0_8.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_8.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_8.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_8.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_8.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
mit
|
dbaac5455378b2f4416b0342a5cef2c0
| 0.446044 | 4.194131 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/Controller.vhd
| 2 | 11,694 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:02:20 11/22/2013
-- Design Name:
-- Module Name: Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Controller is
Port (
INST_CODE : in STD_LOGIC_VECTOR(4 downto 0);
INST_RS : in STD_LOGIC_VECTOR(2 downto 0);
INST_RT : in STD_LOGIC_VECTOR(2 downto 0);
INST_RD : in STD_LOGIC_VECTOR(2 downto 0);
INST_FUNC : in STD_LOGIC_VECTOR(1 downto 0);
ALU_OP : out STD_LOGIC_VECTOR (3 downto 0) := ALU_NULL;
ALU_A_SRC : out STD_LOGIC_VECTOR (2 downto 0) := ALU_A_SRC_ZERO;
ALU_B_SRC : out STD_LOGIC_VECTOR (1 downto 0) := ALU_B_SRC_ZERO;
WRITE_REGS_DEST : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_DM_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0) := WRITE_DM_DATA_SRC_Z;
WRITE_RA_OR_NOT : out STD_LOGIC := WRITE_RA_NO;
WRITE_IH_OR_NOT : out STD_LOGIC := WRITE_IH_NO;
WRITE_T_OR_NOT : out STD_LOGIC := WRITE_T_NO;
WRITE_SP_OR_NOT : out STD_LOGIC := WRITE_SP_NO;
WRITE_T_SRC : out STD_LOGIC;
DATA_MEM_READ_WRITE : out STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
REGS_WRITE_OR_NOT : out STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0)
);
end Controller;
architecture Behavioral of Controller is
begin
process (INST_CODE, INST_RS, INST_RT, INST_RD, INST_FUNC)
variable inst_rd_func : std_logic_vector(4 downto 0);
variable cmd : MY_CMD;
begin
cmd := get_cmd(ALU_NULL, ALU_A_SRC_ZERO, ALU_B_SRC_ZERO, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
inst_rd_func(4 downto 2) := INST_RD;
inst_rd_func(1 downto 0) := INST_FUNC;
case INST_CODE is
when INST_CODE_ADDSP3 =>
--ADDPS3 //[rs] = sp + imm
cmd := get_cmd(ALU_ADD, ALU_A_SRC_SP, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_NOP =>
--NOP //null
NULL;
when INST_CODE_B =>
--B //pc = pc + imm
NULL;
when INST_CODE_BEQZ =>
--BEQZ //if (a == 0) pc = pc + imm
NULL;
when INST_CODE_BNEZ =>
--BEQZ //if (a != 0) pc = pc + imm
NULL;
when INST_CODE_SLL_SRA =>
case INST_FUNC is
when INST_FUNC_SLL =>
--SLL //[rs] = A sll imm
cmd := get_cmd(ALU_SLL, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_FUNC_SRA =>
--SRA //[rs] = A sra imm
cmd := get_cmd(ALU_SRA, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when others =>
NULL;
end case;
when INST_CODE_ADDIU3 =>
--ADDIU3 //[rt] = A + imm
cmd := get_cmd(ALU_ADD, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RT,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_ADDIU =>
--ADDIU //[rs] = A + imm
cmd := get_cmd(ALU_ADD, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_ADDSP_BTEQZ_MTSP =>
case INST_RS is
when INST_RS_ADDSP =>
--ADDSP //sp = sp + imm
cmd := get_cmd(ALU_ADD, ALU_A_SRC_SP, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_YES, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_RS_BTEQZ =>
--BETQZ //if (T == 0) pc = pc + imm
NULL;
when INST_RS_MTSP =>
--MTSP //SP = 0 + B
cmd := get_cmd(ALU_ADD, ALU_A_SRC_ZERO, ALU_B_SRC_B, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_YES, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when others =>
NULL;
end case;
when INST_CODE_LI =>
--LI //[rs] = 0 + imm
cmd := get_cmd(ALU_ADD, ALU_A_SRC_ZERO, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_CMPI =>
--CMPI //if (A - imm == 0) T = 0; else t = 1;
cmd := get_cmd(ALU_SUB, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_YES, T_SRC_IS_NOT_ZF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_LW_SP =>
--LW_SP //[rs] = MEM[SP+imm]
cmd := get_cmd(ALU_ADD, ALU_A_SRC_SP, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_READ, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_DM_DATA);
when INST_CODE_LW =>
--LW //[rt] = MEM[A+imm]
cmd := get_cmd(ALU_ADD, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RT,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_READ, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_DM_DATA);
when INST_CODE_SW_SP =>
--SW_SP //MEM[SP+imm] = A
cmd := get_cmd(ALU_ADD, ALU_A_SRC_SP, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_WRITE, WRITE_DM_DATA_SRC_A,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_SW =>
--SW //MEM[A+imm] = B
cmd := get_cmd(ALU_ADD, ALU_A_SRC_A, ALU_B_SRC_IMM, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_WRITE, WRITE_DM_DATA_SRC_B,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_CODE_ADDU_SUBU =>
case INST_FUNC is
when INST_FUNC_ADDU =>
--ADDU //[rd] = A + B
cmd := get_cmd(ALU_ADD, ALU_A_SRC_A, ALU_B_SRC_B, WRITE_REGS_DEST_RD,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_FUNC_SUBU =>
--SUBU //[rd] = A - B
cmd := get_cmd(ALU_SUB, ALU_A_SRC_A, ALU_B_SRC_B, WRITE_REGS_DEST_RD,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when others =>
NULL;
end case;
when INST_CODE_AND_TO_SLT =>
case inst_rd_func is
when INST_RD_FUNC_AND =>
--AND //[rs] = A and B
cmd := get_cmd(ALU_AND, ALU_A_SRC_A, ALU_B_SRC_B, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_RD_FUNC_CMP =>
--CMP //if (A - B == 0) T = 0; else T = 1;
cmd := get_cmd(ALU_SUB, ALU_A_SRC_A, ALU_B_SRC_B, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_YES, T_SRC_IS_NOT_ZF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_RD_FUNC_JALR_JR_MFPC =>
case INST_RT is
when INST_RT_JALR =>
--JALR //PC = A; RA = PC;
cmd := get_cmd(ALU_NULL, ALU_A_SRC_ZERO, ALU_B_SRC_ZERO, WRITE_REGS_DEST_RS,
WRITE_RA_YES, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_RT_JR =>
--JR //PC = A
NULL;
when INST_RT_MFPC =>
--MFPC //[rs] = PC
--CHANGE HERE
cmd := get_cmd(ALU_ADD, ALU_A_SRC_PC, ALU_B_SRC_ZERO, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_PC_REG);
when others =>
NULL;
end case;
when INST_RD_FUNC_NEG =>
--NEG //[rs] = -A
cmd := get_cmd(ALU_NEG, ALU_A_SRC_A, ALU_B_SRC_ZERO, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_RD_FUNC_OR =>
--OR //[rs] = A or B
cmd := get_cmd(ALU_OR, ALU_A_SRC_A, ALU_B_SRC_B, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_ALU_RESULT);
when INST_RD_FUNC_SLT =>
--SLT //if (A - B < 0) T = 1; else T = 0;
cmd := get_cmd(ALU_SUB, ALU_A_SRC_A, ALU_B_SRC_B, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_YES, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when others =>
NULL;
end case;
when INST_CODE_MFIH_MTIH =>
case INST_FUNC is
when INST_FUNC_MFIH =>
--MFIH //[rs] = IH
--CHANGE HERE
cmd := get_cmd(ALU_ADD, ALU_A_SRC_IH, ALU_B_SRC_ZERO, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_NO, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SRC_Z,
WRITE_REGS_YES, REGS_WRITE_DATA_SRC_IH_REG);
when INST_FUNC_MTIH =>
--MTIH //IH = A + 0
cmd := get_cmd(ALU_ADD, ALU_A_SRC_A, ALU_B_SRC_ZERO, WRITE_REGS_DEST_RS,
WRITE_RA_NO, WRITE_IH_YES, WRITE_SP_NO, WRITE_T_NO, T_SRC_IS_SF,
MEM_NONE, WRITE_DM_DATA_SrC_Z,
WRITE_REGS_NO, REGS_WRITE_DATA_SRC_ALU_RESULT);
when others =>
NULL;
end case;
when others =>
NULL;
end case;
ALU_OP <= cmd.ALU_OP;
ALU_A_SRC <= cmd.ALU_A_SRC;
ALU_B_SRC <= cmd.ALU_B_SRC;
WRITE_REGS_DEST <= cmd.WRITE_REGS_DEST;
WRITE_RA_OR_NOT <= cmd.WRITE_RA_OR_NOT;
WRITE_IH_OR_NOT <= cmd.WRITE_IH_OR_NOT;
WRITE_SP_OR_NOT <= cmd.WRITE_SP_OR_NOT;
WRITE_T_OR_NOT <= cmd.WRITE_T_OR_NOT;
WRITE_T_SRC <= cmd.WRITE_T_SRC;
DATA_MEM_READ_WRITE <= cmd.DATA_MEM_READ_WRITE;
WRITE_DM_DATA_SRC <= cmd.WRITE_DM_DATA_SRC;
REGS_WRITE_OR_NOT <= cmd.REGS_WRITE_OR_NOT;
REGS_WRITE_DATA_SRC <= cmd.REGS_WRITE_DATA_SRC;
end process;
end Behavioral;
|
apache-2.0
|
3c0b35272ae11de4e3cd5b743163ff31
| 0.573884 | 2.53721 | false | false | false | false |
mitchsm/nvc
|
test/regress/signal12.vhd
| 5 | 585 |
entity signal12 is
end entity;
architecture test of signal12 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
signal a : bit_vector(7 downto 0);
signal b : byte_vec(1 to 3);
begin
assign: b <= (others => a);
process is
begin
a <= X"01";
wait for 1 ns;
assert b(1) = X"01";
assert b(2) = X"01";
assert b(3) = X"01";
a <= X"f0";
wait for 1 ns;
assert b(1) = X"f0";
assert b(2) = X"f0";
assert b(3) = X"f0";
wait;
end process;
end architecture;
|
gpl-3.0
|
0519dc841febdf893d7860ed15d4d0ae
| 0.512821 | 3.145161 | false | false | false | false |
DacHt/CU_Droptest
|
hdl/WOLF_CONTROLLER.vhd
| 1 | 10,369 |
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: WOLF_CONTROLLER.vhd
-- File history:
-- v0.1: 2017-04-15: Initial verision for drop test only
--
-- Description:
-- Controller for the REXUS - WOLF exeriment. Handles the statemachine and status communication.
--
-- Backup version:
-- 2017-05-28: D.R: Initial version, light led at 5 sec, turn off led at 10 sec.
-- 2017-06-14: D.R: Droptest version
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity WOLF_CONTROLLER is
port (
---------------------------------------------------
-- Inputs --
---------------------------------------------------
mclk : IN std_logic; -- Main clock
clk_1hz : IN std_logic; -- 1 Hz clock
reset : IN std_logic; -- Reset (when 1)
--UART
uart_data_in : IN std_logic_vector(7 downto 0);
uart_txrdy : IN std_logic;
uart_rxrdy : IN std_logic;
---------------------------------------------------
-- Outputs --
---------------------------------------------------
--Cutter
cutter_en : OUT std_logic; -- Cutter Enable (0=Off, 1=On)
cutter_pwm_duty : OUT std_logic_vector(7 downto 0); -- Cutter PWM duty cycle (100% = 255, 0% = 0)
--UART
uart_data_out : OUT std_logic_vector(7 downto 0);
uart_wen : OUT std_logic;
uart_oen : OUT std_logic;
uart_baud_val : OUT std_logic_vector(12 downto 0);
uart_baud_val_frac: OUT std_logic_vector(2 downto 0) := "000";
--LED
led1 : OUT std_logic;
led2 : OUT std_logic
);
end WOLF_CONTROLLER;
architecture architecture_WOLF_CONTROLLER of WOLF_CONTROLLER is
--####################### Constants #####################################
--Cutter
constant sec_cutter_enable : integer := 2; -- Seconds cutter should be enabled
constant sec_to_cutter_enable : integer := 2; -- Seconds from ejection to enable cutter.
constant cutter_duty : integer := 50; -- Cutter PWM duty cycle, controls current through heating filament(255 => More current, 0 => Less current)
--Uart
constant uart_baud_val_int : integer := 212; -- baudval = (mclk / (16 * baudrate)) - 1; set for 9600 baud
--####################### Signals #####################################
----------------------------------------------------------------------------------------------------------------------
-- Control signals |Comments --
----------------------------------------------------------------------------------------------------------------------
--uart
signal uart_data_buffer_in : std_logic_vector(7 downto 0) :=(others => '0');
signal uart_ready : std_logic := '0';
signal main_uart_transmit_flag : std_logic := '0';
signal main_uart_data_out : std_logic_vector(7 downto 0) :=(others => '0');
--Misson counter
signal sec_since_res : unsigned(12 downto 0) := (others => '0'); -- Variable to keep track of seconds since reset
-----------------------------------------------------------------------------------------------------------------------
-- State Machine Signals |Comments --
-----------------------------------------------------------------------------------------------------------------------
type main_state is (START, IDLE, CUTTER_ENABLE, CUTTER_DISABLE, SLEEP);
signal main_current_state : main_state;
signal main_next_state : main_state := START;
type uart_state is (START, IDLE, RECEIVE, RESPONSE, TRANSMIT);
signal uart_current_state : uart_state;
signal uart_next_state : uart_state := START;
--################# Architecture Body ###########################
begin
-----------------------------------------------------------------
-- Signal/Port mapping --
-----------------------------------------------------------------
cutter_pwm_duty <= std_logic_vector(to_unsigned(cutter_duty, cutter_pwm_duty'length));
uart_baud_val <= std_logic_vector(to_unsigned(uart_baud_val_int, uart_baud_val'length));
-----------------------------------------------------------------
-- Mission counter --
-- Description: --
-- Keeps track of seconds since reset, counts up to --
-- 2^12 = 4096 seconds (68,3 min) and then overflows back to 0.--
-----------------------------------------------------------------
mission_counter: process(clk_1hz, reset)
begin
if ( reset = '1' ) then
sec_since_res <= (others => '0');
else
if ( rising_edge(clk_1hz) ) then
sec_since_res <= sec_since_res + 1;
end if;
end if;
end process;
-----------------------------------------------------------------
-- Uart State Machine --
-- Description: --
-- Uart state machine --
-----------------------------------------------------------------
uart_state_machine : process(mclk, reset)
begin
if(reset = '1') then
uart_next_state <= START;
uart_data_out <= (others => '0');
uart_wen <= '1';
uart_oen <= '1';
uart_ready <= '0';
else
if(rising_edge(mclk)) then
uart_current_state <= uart_next_state;
case uart_current_state is
when START =>
uart_data_out <= (others => '0');
uart_wen <= '1';
uart_oen <= '1';
uart_ready <= '0';
uart_next_state <= IDLE;
when IDLE => -- Wait for receving command
uart_ready <= '1';
if(uart_rxrdy = '1') then
uart_ready <= '0';
uart_next_state <= RECEIVE;
elsif(main_uart_transmit_flag='1') then
uart_ready <= '0';
uart_data_out <= main_uart_data_out;
uart_next_state <= TRANSMIT;
else
uart_next_state <= uart_current_state;
end if;
when RECEIVE => -- Recevie the byte
uart_data_buffer_in <= uart_data_in;
uart_oen <= '0';
uart_next_state <= RESPONSE;
when RESPONSE =>
uart_data_out <= uart_data_buffer_in;
uart_next_state <= TRANSMIT;
when TRANSMIT =>
if(uart_txrdy = '1') then
uart_wen <= '0';
uart_next_state <= START;
else
uart_next_state <= uart_current_state;
end if;
end case;
end if;
end if;
end process uart_state_machine;
-----------------------------------------------------------------
-- Main State Machine --
-- Description: --
-- Main state machine of the WOLF mission controller --
-----------------------------------------------------------------
main_state_machine : process(mclk, reset)
begin
if(reset = '1') then
cutter_en <= '0';
main_uart_transmit_flag <= '0';
main_uart_data_out <= x"00";
main_next_state <= START;
elsif(rising_edge(mclk)) then
main_current_state <= main_next_state;
case main_current_state is
-- Starting state
when START =>
cutter_en <= '0';
main_uart_transmit_flag <= '0';
if(uart_ready = '1') then
main_next_state <= IDLE;
main_uart_data_out <= x"01";
main_uart_transmit_flag <= '1';
end if;
-- IDLE state
when IDLE =>
main_uart_transmit_flag <= '0';
-- Enable cutter after "sec_to_cutter_enable" from reset
if (sec_since_res >= To_unsigned(sec_to_cutter_enable, sec_since_res'length)) then
if(uart_ready = '1') then
main_next_state <= CUTTER_ENABLE;
main_uart_data_out <= x"02";
main_uart_transmit_flag <= '1';
end if;
else
main_next_state <= main_current_state;
end if;
-- Enable cutter
when CUTTER_ENABLE =>
main_uart_transmit_flag <= '0';
if(uart_ready = '1') then
cutter_en <= '1';
main_uart_data_out <= x"03";
main_uart_transmit_flag <= '1';
main_next_state <= CUTTER_DISABLE;
end if;
--Disable cutter
when CUTTER_DISABLE =>
-- Disable cutter after "sec_cutter_enable"
main_uart_transmit_flag <= '0';
if (sec_since_res >= To_unsigned((sec_to_cutter_enable + sec_cutter_enable), sec_since_res'length)) then
if(uart_ready = '1') then
cutter_en <= '0';
main_uart_data_out <= x"04";
main_uart_transmit_flag <= '1';
main_next_state <= SLEEP;
end if;
else
main_next_state <= main_current_state;
end if;
-- SLEEP state, do nothing
when SLEEP =>
main_uart_transmit_flag <= '0';
end case;
end if;
end process main_state_machine;
end architecture_WOLF_CONTROLLER;
|
mit
|
5df2f6a73fed81cd3958fda343a993ba
| 0.405246 | 4.721767 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_counter1.vhd
| 2 | 4,443 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter1 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_counter1;
ARCHITECTURE SYN OF lpm_counter1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(8 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 272,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 9
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "272"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "272"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
9c14bca810bcd9a8cb2b41a67fee75ef
| 0.651812 | 3.687137 | false | false | false | false |
mitchsm/nvc
|
test/regress/ieee3.vhd
| 5 | 561 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ieee3 is
end entity;
architecture test of ieee3 is
begin
process is
variable x, y, z: unsigned(7 downto 0);
begin
x := to_unsigned(3, 8);
y := to_unsigned(5, 8);
assert y > x;
assert y >= x;
assert x <= y;
assert x < y;
assert to_integer(x) = 3;
assert (x + y) = 8;
assert (y - x) = 2;
assert (x * y) = 15;
assert (y / x) = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
c0d08e2ddf567635cf5fca019f883aa6
| 0.511586 | 3.224138 | false | false | false | false |
mitchsm/nvc
|
test/regress/operator1.vhd
| 5 | 481 |
entity operator1 is
end entity;
architecture test of operator1 is
type t is (A, B);
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
begin
process is
variable x, y : t;
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
wait;
end process;
end architecture;
|
gpl-3.0
|
5b5f19e81429d7ca69dfbf9e9986b109
| 0.463617 | 3.728682 | false | false | false | false |
mitchsm/nvc
|
test/sem/real.vhd
| 3 | 758 |
entity e is
end entity;
architecture a of e is
signal x : real := 1.234; -- OK
type my_real is range 0.0 to 1.0; -- OK
begin
process is
variable v : my_real;
begin
x <= x + 6.1215; -- OK
x <= v; -- Error
end process;
process is
variable i : integer;
begin
i := integer(x); -- OK
x <= real(i); -- OK
x <= real(5); -- OK
x <= real(bit'('1')); -- Error
end process;
process is
variable x : real;
begin
x := real'left; -- OK
x := real'right; -- OK
end process;
end architecture;
|
gpl-3.0
|
f12c3f2fb1308c232559afd3928eac94
| 0.387863 | 4.142077 | false | false | false | false |
mitchsm/nvc
|
test/regress/driver2.vhd
| 5 | 429 |
entity driver2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver2 is
signal x : std_logic;
begin
x <= 'H';
p1: process is
begin
x <= 'Z';
wait for 1 ns;
assert x = 'H';
x <= '0';
wait for 1 ns;
assert x = '0';
x <= 'Z';
wait for 1 ns;
assert x = 'H';
wait;
end process;
end architecture;
|
gpl-3.0
|
a6d9562ec33e04719d862164fddf9d14
| 0.491841 | 3.377953 | false | false | false | false |
mitchsm/nvc
|
test/sem/integer.vhd
| 4 | 1,456 |
entity b is
end entity;
architecture a of b is
type my_int1 is range 0 to 10;
type my_int2 is range -20 to 30;
signal x : my_int1 := 2;
begin
process is
variable z : my_int1;
begin
z := x;
end process;
process is
variable y : my_int2;
begin
-- Should generate error as my_int1 and my_int2 incompatible
y := x;
end process;
process is
subtype my_int2_sub is my_int2 range 0 to 10;
variable yy : my_int2_sub;
begin
yy := 6; -- OK
-- Should fail even though the range is the same
yy := x;
end process;
process is
-- Base type is undefined
subtype bad is nothing range 1 to 2;
begin
end process;
process is
subtype my_int2_same is my_int2;
subtype another_one is my_int2_same range 0 to 10;
variable yyy : another_one;
variable foo : my_int2 range 0 to 10;
begin
yyy := foo; -- OK
yyy := foo * 2; -- OK
yyy := 5 * (2 + 4) / 2; -- OK
yyy := (yyy + 5) * x + 2; -- Cannot convert my_int1 to my_int2
end process;
process is
variable b : my_int2 := my_int2'left;
begin
b := my_int2'low;
b := my_int2'high;
b := my_int2'right;
b := my_int2'cake; -- Error
end process;
end architecture;
|
gpl-3.0
|
0dcee95925547e1571d5519220fb51a3
| 0.504121 | 3.649123 | false | false | false | false |
mitchsm/nvc
|
test/regress/record10.vhd
| 5 | 654 |
entity record10 is
end entity;
architecture test of record10 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
x : integer;
y : bit_vector(1 to 3);
end record;
begin
process is
variable r1 : rec1;
variable r2 : rec2;
variable a, b : integer;
variable c : bit_vector(1 to 3);
begin
a := 1;
b := 2;
r1 := rec1'(x => a, y => b);
assert r1.x = 1;
assert r1.y = 2;
r2 := rec2'(x => a, y => c);
assert r2.x = 1;
assert r2.y = "000";
wait;
end process;
end architecture;
|
gpl-3.0
|
06b47e691d1c6b798803d5cc5024511a
| 0.481651 | 3.336735 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare0.vhd
| 2 | 4,444 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "0000101001";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "41"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 41 0 0 10 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
6ed1a04ad4df850b25bf2dbee4a64e93
| 0.655941 | 3.70025 | false | false | false | false |
mitchsm/nvc
|
test/regress/alias7.vhd
| 5 | 649 |
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
assert ctr = 0;
x <= X"3f";
wait for 1 ns;
assert ctr = 0;
x <= X"80";
wait for 1 ns;
assert ctr = 1;
x <= X"00";
wait for 1 ns;
assert ctr = 1;
x <= X"ff";
wait for 1 ns;
assert ctr = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
872b1a4a488dffd97e8f751cd45f9975
| 0.469954 | 3.625698 | false | false | false | false |
mitchsm/nvc
|
test/regress/operator5.vhd
| 5 | 819 |
package pack is
type int_vec2 is array (integer range <>) of integer;
type int_vec is array (integer range <>) of integer;
function "<"(a, b : int_vec) return boolean;
end package;
package body pack is
function "<"(a, b : int_vec) return boolean is
begin
return false;
end function;
end package body;
entity operator5 is
end entity;
use work.pack.all;
architecture test of operator5 is
function ">="(a, b : int_vec) return boolean is
begin
return false;
end function;
begin
process is
variable x, y : int_vec(1 to 3);
begin
x := (1, 2, 3);
y := (4, 5, 6);
assert not (y >= x);
assert (int_vec2(y) >= int_vec2(x));
assert not (y < x) and not (x < y);
wait;
end process;
end architecture;
|
gpl-3.0
|
389f30c159c5a37ab58a0fbf687145e2
| 0.577534 | 3.5 | false | false | false | false |
mitchsm/nvc
|
test/lower/slice1.vhd
| 4 | 671 |
entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v(2 to 3) = ( 7, 4 );
wait for 1 ns;
x <= ( 1, 2, 3, 4 );
x(1 to 2) <= ( 6, 7 );
assert x(2 to 3) = ( 7, 4 );
wait for 1 ns;
u := ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
|
gpl-3.0
|
b927df42e74972e0d40cd72bef2954f9
| 0.460507 | 3.12093 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/pad_pads_e-rtl-a.vhd
| 1 | 13,174 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 16:54:04 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-rtl-a.vhd,v 1.3 2006/07/10 07:30:08 wig Exp $
-- $Date: 2006/07/10 07:30:08 $
-- $Log: pad_pads_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/10 07:30:08 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of pad_pads_e
--
architecture rtl of pad_pads_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component w_pad_i
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_i
di : out std_ulogic -- data in from pad
-- End of Generated Port for Entity w_pad_i
);
end component;
-- ---------
component w_disp
-- No Generated Generics
port (
-- Generated Port for Entity w_disp
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_disp
);
end component;
-- ---------
component w_pad_o
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_o
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_pad_o
);
end component;
-- ---------
component w_data2
-- No Generated Generics
port (
-- Generated Port for Entity w_data2
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data2
);
end component;
-- ---------
component w_data3
-- No Generated Generics
port (
-- Generated Port for Entity w_data3
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data3
);
end component;
-- ---------
component w_pad_dir
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dir
di : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dir
);
end component;
-- ---------
component w_pad_dire
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dire
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dire
);
end component;
-- ---------
--
-- Generated Signal List
--
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal pad_dir_di : std_ulogic;
-- __I_OUT_OPEN signal pad_dir_di38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_do38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_en38 : std_ulogic;
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_pad_di_1_go <= pad_di_1; -- __I_O_BIT_PORT
p_mix_pad_di_12_go <= pad_di_12; -- __I_O_BIT_PORT
p_mix_pad_di_13_go <= pad_di_13; -- __I_O_BIT_PORT
p_mix_pad_di_14_go <= pad_di_14; -- __I_O_BIT_PORT
p_mix_pad_di_15_go <= pad_di_15; -- __I_O_BIT_PORT
p_mix_pad_di_16_go <= pad_di_16; -- __I_O_BIT_PORT
p_mix_pad_di_17_go <= pad_di_17; -- __I_O_BIT_PORT
p_mix_pad_di_18_go <= pad_di_18; -- __I_O_BIT_PORT
p_mix_pad_di_31_go <= pad_di_31; -- __I_O_BIT_PORT
p_mix_pad_di_32_go <= pad_di_32; -- __I_O_BIT_PORT
p_mix_pad_di_33_go <= pad_di_33; -- __I_O_BIT_PORT
p_mix_pad_di_34_go <= pad_di_34; -- __I_O_BIT_PORT
p_mix_pad_di_39_go <= pad_di_39; -- __I_O_BIT_PORT
p_mix_pad_di_40_go <= pad_di_40; -- __I_O_BIT_PORT
pad_do_12 <= p_mix_pad_do_12_gi; -- __I_I_BIT_PORT
pad_do_13 <= p_mix_pad_do_13_gi; -- __I_I_BIT_PORT
pad_do_14 <= p_mix_pad_do_14_gi; -- __I_I_BIT_PORT
pad_do_15 <= p_mix_pad_do_15_gi; -- __I_I_BIT_PORT
pad_do_16 <= p_mix_pad_do_16_gi; -- __I_I_BIT_PORT
pad_do_17 <= p_mix_pad_do_17_gi; -- __I_I_BIT_PORT
pad_do_18 <= p_mix_pad_do_18_gi; -- __I_I_BIT_PORT
pad_do_2 <= p_mix_pad_do_2_gi; -- __I_I_BIT_PORT
pad_do_31 <= p_mix_pad_do_31_gi; -- __I_I_BIT_PORT
pad_do_32 <= p_mix_pad_do_32_gi; -- __I_I_BIT_PORT
pad_do_35 <= p_mix_pad_do_35_gi; -- __I_I_BIT_PORT
pad_do_36 <= p_mix_pad_do_36_gi; -- __I_I_BIT_PORT
pad_do_39 <= p_mix_pad_do_39_gi; -- __I_I_BIT_PORT
pad_do_40 <= p_mix_pad_do_40_gi; -- __I_I_BIT_PORT
pad_en_12 <= p_mix_pad_en_12_gi; -- __I_I_BIT_PORT
pad_en_13 <= p_mix_pad_en_13_gi; -- __I_I_BIT_PORT
pad_en_14 <= p_mix_pad_en_14_gi; -- __I_I_BIT_PORT
pad_en_15 <= p_mix_pad_en_15_gi; -- __I_I_BIT_PORT
pad_en_16 <= p_mix_pad_en_16_gi; -- __I_I_BIT_PORT
pad_en_17 <= p_mix_pad_en_17_gi; -- __I_I_BIT_PORT
pad_en_18 <= p_mix_pad_en_18_gi; -- __I_I_BIT_PORT
pad_en_2 <= p_mix_pad_en_2_gi; -- __I_I_BIT_PORT
pad_en_31 <= p_mix_pad_en_31_gi; -- __I_I_BIT_PORT
pad_en_32 <= p_mix_pad_en_32_gi; -- __I_I_BIT_PORT
pad_en_35 <= p_mix_pad_en_35_gi; -- __I_I_BIT_PORT
pad_en_36 <= p_mix_pad_en_36_gi; -- __I_I_BIT_PORT
pad_en_39 <= p_mix_pad_en_39_gi; -- __I_I_BIT_PORT
pad_en_40 <= p_mix_pad_en_40_gi; -- __I_I_BIT_PORT
pad_pu_31 <= p_mix_pad_pu_31_gi; -- __I_I_BIT_PORT
pad_pu_32 <= p_mix_pad_pu_32_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for pad_1
pad_1: w_pad_i
port map (
di => pad_di_1 -- data in from pad
);
-- End of Generated Instance Port Map for pad_1
-- Generated Instance Port Map for pad_12
pad_12: w_disp
port map (
di => pad_di_12, -- data in from pad
do => pad_do_12, -- data out to pad
en => pad_en_12 -- pad output enable
);
-- End of Generated Instance Port Map for pad_12
-- Generated Instance Port Map for pad_13
pad_13: w_disp
port map (
di => pad_di_13, -- data in from pad
do => pad_do_13, -- data out to pad
en => pad_en_13 -- pad output enable
);
-- End of Generated Instance Port Map for pad_13
-- Generated Instance Port Map for pad_14
pad_14: w_disp
port map (
di => pad_di_14, -- data in from pad
do => pad_do_14, -- data out to pad
en => pad_en_14 -- pad output enable
);
-- End of Generated Instance Port Map for pad_14
-- Generated Instance Port Map for pad_15
pad_15: w_disp
port map (
di => pad_di_15, -- data in from pad
do => pad_do_15, -- data out to pad
en => pad_en_15 -- pad output enable
);
-- End of Generated Instance Port Map for pad_15
-- Generated Instance Port Map for pad_16
pad_16: w_disp
port map (
di => pad_di_16, -- data in from pad
do => pad_do_16, -- data out to pad
en => pad_en_16 -- pad output enable
);
-- End of Generated Instance Port Map for pad_16
-- Generated Instance Port Map for pad_17
pad_17: w_disp
port map (
di => pad_di_17, -- data in from pad
do => pad_do_17, -- data out to pad
en => pad_en_17 -- pad output enable
);
-- End of Generated Instance Port Map for pad_17
-- Generated Instance Port Map for pad_18
pad_18: w_disp
port map (
di => pad_di_18, -- data in from pad
do => pad_do_18, -- data out to pad
en => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for pad_18
-- Generated Instance Port Map for pad_2
pad_2: w_pad_o
port map (
do => pad_do_2, -- data out to pad
en => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for pad_2
-- Generated Instance Port Map for pad_31
pad_31: w_data2
port map (
di => pad_di_31, -- data in from pad
do => pad_do_31, -- data out to pad
en => pad_en_31, -- pad output enable
pu => pad_pu_31 -- pull-up control
);
-- End of Generated Instance Port Map for pad_31
-- Generated Instance Port Map for pad_32
pad_32: w_data3
port map (
di => pad_di_32, -- data in from pad
do => pad_do_32, -- data out to pad
en => pad_en_32, -- pad output enable
pu => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_32
-- Generated Instance Port Map for pad_33
pad_33: w_pad_i
port map (
di => pad_di_33 -- data in from pad
);
-- End of Generated Instance Port Map for pad_33
-- Generated Instance Port Map for pad_34
pad_34: w_pad_i
port map (
di => pad_di_34 -- data in from pad
);
-- End of Generated Instance Port Map for pad_34
-- Generated Instance Port Map for pad_35
pad_35: w_pad_o
port map (
do => pad_do_35, -- data out to pad
en => pad_en_35 -- pad output enable
);
-- End of Generated Instance Port Map for pad_35
-- Generated Instance Port Map for pad_36
pad_36: w_pad_o
port map (
do => pad_do_36, -- data out to pad
en => pad_en_36 -- pad output enable
);
-- End of Generated Instance Port Map for pad_36
-- Generated Instance Port Map for pad_37
pad_37: w_pad_dir
port map (
di => open -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for pad_37
-- Generated Instance Port Map for pad_38
pad_38: w_pad_dire
port map (
di => open, -- __I_OUT_OPEN
-- __I_NODRV_I -- __I_NODRV_I do => __nodrv__/pad_dir_en38/pad_dir_do38,
-- __I_NODRV_I en => __nodrv__/pad_dir_en38
);
-- End of Generated Instance Port Map for pad_38
-- Generated Instance Port Map for pad_39
pad_39: w_disp
port map (
di => pad_di_39, -- data in from pad
do => pad_do_39, -- data out to pad
en => pad_en_39 -- pad output enable
);
-- End of Generated Instance Port Map for pad_39
-- Generated Instance Port Map for pad_40
pad_40: w_disp
port map (
di => pad_di_40, -- data in from pad
do => pad_do_40, -- data out to pad
en => pad_en_40 -- pad output enable
);
-- End of Generated Instance Port Map for pad_40
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
a9a97c59884fdc64ac6d61d546f8e949
| 0.600729 | 2.472598 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_3_2/synth/zc702_proc_sys_reset_3_2.vhd
| 1 | 6,659 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_3_2 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_3_2;
ARCHITECTURE zc702_proc_sys_reset_3_2_arch OF zc702_proc_sys_reset_3_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_3_2_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_proc_sys_reset_3_2_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_proc_sys_reset_3_2_arch : ARCHITECTURE IS "zc702_proc_sys_reset_3_2,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_proc_sys_reset_3_2_arch: ARCHITECTURE IS "zc702_proc_sys_reset_3_2,proc_sys_reset,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_3_2_arch;
|
mit
|
c0d1b4b40dd21e74409a689fcdcd7763
| 0.71317 | 3.439566 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/ios_e-rtl-a.vhd
| 1 | 20,327 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-rtl-a.vhd,v 1.2 2005/07/19 07:13:15 wig Exp $
-- $Date: 2005/07/19 07:13:15 $
-- $Log: ios_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:15 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ios_e
--
architecture rtl of ios_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioblock0_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_go : out std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end component;
-- ---------
component ioblock1_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock1_e
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic
-- End of Generated Port for Entity ioblock1_e
);
end component;
-- ---------
component ioblock2_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ioblock3_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock3_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ioblock3_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_out_2 : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioblock_0
ioblock_0: ioblock0_e
port map (
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_nand_out_2_go => nand_out_2, -- Links ...
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_en_2_go => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_0
-- Generated Instance Port Map for ioblock_1
ioblock_1: ioblock1_e
port map (
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_nand_out_2_gi => nand_out_2, -- Links ...
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_1
-- Generated Instance Port Map for ioblock_2
ioblock_2: ioblock2_e
;
-- End of Generated Instance Port Map for ioblock_2
-- Generated Instance Port Map for ioblock_3
ioblock_3: ioblock3_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ioblock_3
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
d2f756d7292e45b99dfd134326232eb8
| 0.6055 | 2.249806 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/fifo.vhd
| 1 | 7,424 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: fifo.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END fifo;
ARCHITECTURE SYN OF fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(23 DOWNTO 0);
wrusedw <= sub_wire2(8 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 24,
lpm_widthu => 9,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
wrusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "24"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "24"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
3861f135cc7f2f708ef4a7da0fbcc5fe
| 0.665275 | 3.528517 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/blk_mem_gen_inputMem_ste/example_design/blk_mem_gen_inputMem_top.vhd
| 1 | 5,013 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_inputMem_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_inputMem_top;
ARCHITECTURE xilinx OF blk_mem_gen_inputMem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_inputMem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_inputMem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-2.0
|
830fcfdbd80237b30a713514cde0d20e
| 0.561141 | 4.578082 | false | false | false | false |
mitchsm/nvc
|
test/regress/proc9.vhd
| 4 | 416 |
entity proc9 is
end entity;
architecture test of proc9 is
procedure foo (x : in integer; y : out bit_vector) is
constant c : bit_vector(1 to x) := (others => '1');
begin
wait;
y := c;
end procedure;
begin
process is
variable b : bit_vector(1 to 5);
begin
foo(5, b);
assert b = (1 to 5 => '1');
wait;
end process;
end architecture;
|
gpl-3.0
|
f748990ae5bcd32aff02bad242475322
| 0.536058 | 3.525424 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/MUX_3.vhd
| 2 | 1,485 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:36 11/21/2013
-- Design Name:
-- Module Name: MUX_3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_3 is
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (1 downto 0) := "00";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
end MUX_3;
architecture Behavioral of MUX_3 is
begin
process(SRC_1, SRC_2, SRC_3, SELEC)
begin
case SELEC is
when "00" =>
OUTPUT <= SRC_1;
when "01" =>
OUTPUT <= SRC_2;
when "10" =>
OUTPUT <= SRC_3;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
|
apache-2.0
|
a0351b0d7f9277e77e23bed9ca52a170
| 0.56431 | 3.527316 | false | false | false | false |
mitchsm/nvc
|
test/regress/alias3.vhd
| 5 | 763 |
entity alias3 is
end entity;
architecture test of alias3 is
type int_array is array (integer range <>) of integer;
function cut(x : int_array; low, high: integer) return int_array is
alias a : int_array(1 to x'length) is x;
begin
return a(low to high);
end function;
signal s : int_array(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable x : int_array(1 to 5) := (1, 2, 3, 4, 5);
variable y : int_array(4 downto 0) := (4, 3, 2, 1, 0);
alias sa : int_array(4 downto 0) is x;
begin
assert x(2 to 4) = (2, 3, 4);
assert sa(3 downto 1) = (2, 3, 4);
assert cut(x, 2, 3) = (2, 3);
assert cut(y, 1, 2) = (4, 3);
wait;
end process;
end architecture;
|
gpl-3.0
|
0beaa4004cea6015a17dbaff9d2b13ed
| 0.541284 | 3.01581 | false | false | false | false |
mitchsm/nvc
|
test/regress/array2.vhd
| 5 | 505 |
entity array2 is
end entity;
architecture test of array2 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
begin
process is
variable a : int_array_Nx4(1 to 4);
variable b : int_array(1 to 4);
begin
a(1)(2) := 2;
assert a(1)(2) = 2;
a := ( others => ( 1, 2, 3, 4 ) );
b := a(1);
assert b = ( 1, 2, 3, 4);
wait;
end process;
end architecture;
|
gpl-3.0
|
ad3f4b938220d62cadfe4da1181571fd
| 0.532673 | 3.216561 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab7.vhd
| 5 | 1,242 |
entity sub2 is
generic (
VALUE : integer );
port (
x : out integer );
end entity;
architecture test of sub2 is
begin
x <= VALUE;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
generic (
ENABLE : boolean );
port (
y : out integer );
end entity;
architecture test of sub1 is
begin
value7_g: if ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 7 )
port map ( x => y );
end generate;
value5_g: if not ENABLE generate
sub: entity work.sub2
generic map ( VALUE => 5 )
port map ( x => y );
end generate;
end architecture;
-------------------------------------------------------------------------------
entity elab7 is
end entity;
architecture test of elab7 is
signal a, b : integer;
begin
sa: entity work.sub1
generic map ( ENABLE => true )
port map ( y => a );
sb: entity work.sub1
generic map ( ENABLE => false )
port map ( y => b );
process is
begin
wait for 1 ns;
assert a = 7;
assert b = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
6a10abf387ae6d3736e965c6536e03b7
| 0.472625 | 4.451613 | false | false | false | false |
mitchsm/nvc
|
test/regress/agg6.vhd
| 5 | 556 |
entity agg6 is
end entity;
architecture test of agg6 is
type int_vec is array (natural range <>) of integer;
type int_vec4x2 is array (1 to 4) of int_vec(1 to 2);
begin
process is
variable a : int_vec4x2;
variable b : int_vec(1 to 8);
begin
b := (1, 2, 3, 4, 5, 6, 7, 8);
a := int_vec4x2'(b(1 to 2), b(3 to 4), b(5 to 6), b(7 to 8));
assert a(1) = (1, 2);
assert a(2) = (3, 4);
assert a(3) = (5, 6);
assert a(4) = (7, 8);
wait;
end process;
end architecture;
|
gpl-3.0
|
cf6d45f4a960fab525582a560cc71e97
| 0.508993 | 2.78 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_mux1.vhd
| 1 | 4,505 |
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux1.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux1 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_mux1;
ARCHITECTURE SYN OF lpm_mux1 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
sub_wire3 <= data0x(7 DOWNTO 0);
result <= sub_wire0(7 DOWNTO 0);
sub_wire1 <= data1x(7 DOWNTO 0);
sub_wire2(1, 0) <= sub_wire1(0);
sub_wire2(1, 1) <= sub_wire1(1);
sub_wire2(1, 2) <= sub_wire1(2);
sub_wire2(1, 3) <= sub_wire1(3);
sub_wire2(1, 4) <= sub_wire1(4);
sub_wire2(1, 5) <= sub_wire1(5);
sub_wire2(1, 6) <= sub_wire1(6);
sub_wire2(1, 7) <= sub_wire1(7);
sub_wire2(0, 0) <= sub_wire3(0);
sub_wire2(0, 1) <= sub_wire3(1);
sub_wire2(0, 2) <= sub_wire3(2);
sub_wire2(0, 3) <= sub_wire3(3);
sub_wire2(0, 4) <= sub_wire3(4);
sub_wire2(0, 5) <= sub_wire3(5);
sub_wire2(0, 6) <= sub_wire3(6);
sub_wire2(0, 7) <= sub_wire3(7);
sub_wire4 <= sel;
sub_wire5(0) <= sub_wire4;
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_MUX",
lpm_width => 8,
lpm_widths => 1
)
PORT MAP (
data => sub_wire2,
sel => sub_wire5,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
0d7ad1550ffd8e448603b52e65f684c8
| 0.620422 | 3.104755 | false | false | false | false |
mitchsm/nvc
|
test/regress/access7.vhd
| 4 | 905 |
entity access7 is
end entity;
architecture test of access7 is
type int_ptr is access integer;
type int_ptr_ptr is access int_ptr;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr(x : out int_ptr_ptr) is
begin
x := new int_ptr;
end procedure;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array(1 to 3);
end procedure;
begin
process is
variable pp : int_ptr_ptr;
variable pa : int_ptr_array_ptr;
begin
alloc_ptr(pp);
assert pp.all = null;
pp.all := new integer'(4);
assert pp.all.all = 4;
alloc_ptr_array(pa);
assert pa.all = (null, null, null);
pa(1) := new integer'(6);
assert pa(1).all = 6;
wait;
end process;
end architecture;
|
gpl-3.0
|
12ba607fb4c71baac0514ef5b5b3d60f
| 0.58674 | 3.42803 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3.vhd
| 1 | 21,293 |
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13632)
`protect data_block
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`protect end_protected
|
mit
|
d282a2da8f22acb0f22c58a2f1df1f96
| 0.938994 | 1.884503 | false | false | false | false |
mitchsm/nvc
|
test/sem/issue224.vhd
| 3 | 1,057 |
entity test is
end entity test;
architecture test of test is
-- next line should fail to compile because it's not legal to assign a default value to a signal parameter
procedure proc(signal a : integer := 1) is
begin
end procedure proc;
begin
end architecture test;
architecture test2 of test is
procedure proc(signal a : integer) is
begin
end procedure proc;
begin
-- next line should also fail to compile because it's not legal to have no actual or an OPEN actual
proc(a => open);
end architecture test2;
architecture test3 of test is
procedure proc(
variable a : in integer := 1;
variable a : out integer := 1
) is
begin
end procedure proc;
begin
end architecture test3;
architecture test4 of test is
procedure proc(
variable a : in integer := 1;
variable a : inout integer := 1
) is
begin
end procedure proc;
begin
end architecture test4;
entity test2 is
port (
a : linkage boolean := false -- error
);
end entity test2;
|
gpl-3.0
|
7a0b762e7b4ea6824f8395c67c5506bf
| 0.664144 | 4.194444 | false | true | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/ram.vhd
| 1 | 6,664 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
address : in unsigned(depth - 1 downto 0);
data_in : in std_logic_vector(width - 1 downto 0);
data_out : out std_logic_vector(width - 1 downto 0)
);
end ram;
architecture logic of ram is
type mem_type is array ((2 ** depth) - 1 downto 0) of std_logic_vector(width - 1 downto 0);
begin
-- read new data
w_r : if wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
if put then
mem(idx(address)) := data_in;
end if;
data_out <= mem(idx(address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
data_out <= mem(idx(address));
if put then
mem(idx(address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram_unsigned is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
address : in unsigned(depth - 1 downto 0);
data_in : in unsigned(width - 1 downto 0);
data_out : out unsigned(width - 1 downto 0)
);
end ram_unsigned;
architecture logic of ram_unsigned is
type mem_type is array ((2 ** depth) - 1 downto 0) of unsigned(width - 1 downto 0);
begin
-- read new data
w_r : if wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
if put then
mem(idx(address)) := data_in;
end if;
data_out <= mem(idx(address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
data_out <= mem(idx(address));
if put then
mem(idx(address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram_dual is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
write_address : in unsigned(depth - 1 downto 0);
data_in : in std_logic_vector(width - 1 downto 0);
read_address : in unsigned(depth - 1 downto 0);
data_out : out std_logic_vector(width - 1 downto 0)
);
end ram_dual;
architecture logic of ram_dual is
type mem_type is array ((2 ** depth) - 1 downto 0) of std_logic_vector(width - 1 downto 0);
shared variable mem : mem_type := (others => (others => '0'));
begin
-- read new data
w_r : if wr generate
process(clk)
begin
if rising_edge(clk) then
if put then
mem(idx(write_address)) := data_in;
end if;
data_out <= mem(idx(read_address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
begin
if rising_edge(clk) then
data_out <= mem(idx(read_address));
if put then
mem(idx(write_address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram_dual_unsigned is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
write_address : in unsigned(depth - 1 downto 0);
data_in : in unsigned(width - 1 downto 0);
read_address : in unsigned(depth - 1 downto 0);
data_out : out unsigned(width - 1 downto 0)
);
end ram_dual_unsigned;
architecture logic of ram_dual_unsigned is
type mem_type is array ((2 ** depth) - 1 downto 0) of unsigned(width - 1 downto 0);
shared variable mem : mem_type := (others => (others => '0'));
begin
-- read new data
w_r : if wr generate
process(clk)
begin
if rising_edge(clk) then
if put then
mem(idx(write_address)) := data_in;
end if;
data_out <= mem(idx(read_address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
begin
if rising_edge(clk) then
data_out <= mem(idx(read_address));
if put then
mem(idx(write_address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
|
bsd-2-clause
|
0211cfafe608c9f93c9063c1c66840d0
| 0.453782 | 4.128872 | false | false | false | false |
blutsvente/MIX
|
Resources/Examples/a_clk_20030129/ddrv4_struct-a.vhd
| 1 | 4,930 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for ddrv4_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template
--
-- Generator: mix_0.pl /mix/0.1, [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
--
--
-- Start of Generated Architecture ddrv4_struct
--
architecture ddrv4_struct of ddrv4 is
--
-- Components
--
-- Generated Components
component ddrv
port (
-- generated
alarm_in : in std_ulogic;
alarm_time : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time : in std_ulogic_vector(3 downto 0);
display : out std_ulogic_vector(6 downto 0);
key_buffer : in std_ulogic_vector(3 downto 0);
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic_vector(3 downto 0)
-- end of generated port
);
end component;
-- ---------
component and_f
port (
-- generated
clk : in std_ulogic;
out : out std_ulogic;
out_2 : out std_ulogic;
reset : in std_ulogic;
y : in std_ulogic_vector(3 downto 0)
-- end of generated port
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signals
--
signal alarm : std_ulogic_vector(3 downto 0);
signal alarm_time_ls_hr : std_ulogic_vector(3 downto 0);
signal alarm_time_ls_min : std_ulogic_vector(3 downto 0);
signal alarm_time_ms_hr : std_ulogic_vector(3 downto 0);
signal alarm_time_ms_min : std_ulogic_vector(3 downto 0);
signal clk : std_ulogic;
signal current_time_ls_hr : std_ulogic_vector(3 downto 0);
signal current_time_ls_min : std_ulogic_vector(3 downto 0);
signal current_time_ms_hr : std_ulogic_vector(3 downto 0);
signal current_time_ms_min : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0);
signal display_ls_min : std_ulogic_vector(6 downto 0);
signal display_ms_hr : std_ulogic_vector(6 downto 0);
signal display_ms_min : std_ulogic_vector(6 downto 0);
signal key_buffer_0 : std_ulogic_vector(3 downto 0);
signal key_buffer_1 : std_ulogic_vector(3 downto 0);
signal key_buffer_2 : std_ulogic_vector(3 downto 0);
signal key_buffer_3 : std_ulogic_vector(3 downto 0);
signal reset : std_ulogic;
signal show_a : std_ulogic;
signal show_new_time : std_ulogic;
signal sound_alarm : std_ulogic;
signal sound_alarm_test1 : std_ulogic;
--
-- End of Generated Signals
--
-- %CONSTANTS%
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv PORT MAP(
alarm_time => alarm_time_ls_hr,
clk => clk,
current_time => current_time_ls_hr,
key_buffer => key_buffer_2,
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm,
display => display_ls_hr
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv PORT MAP(
alarm_time => alarm_time_ls_min,
clk => clk,
current_time => current_time_ls_min,
key_buffer => key_buffer_0,
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm,
display => display_ls_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv PORT MAP(
alarm_time => alarm_time_ms_hr,
clk => clk,
current_time => current_time_ms_hr,
key_buffer => key_buffer_3,
show_a => show_a,
show_new_time => show_new_time,
alarm_in => sound_alarm_test1,
sound_alarm => alarm,
display => display_ms_hr
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv PORT MAP(
alarm_time => alarm_time_ms_min,
clk => clk,
current_time => current_time_ms_min,
key_buffer => key_buffer_1,
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm,
display => display_ms_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_and_f
u_and_f: and_f PORT MAP(
y => alarm,
clk => clk,
reset => reset,
out => sound_alarm,
out_2 => sound_alarm_test1
);
-- End of Generated Instance Port Map
end ddrv4_struct;
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
bfafae53ee490122e838cb435afb6dfe
| 0.583367 | 3.041333 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare3.vhd
| 2 | 4,435 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare3.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare3 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare3;
ARCHITECTURE SYN OF lpm_compare3 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "000001010";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "10"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 10 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
91204d90cb601ba2bf57bc11cab884db
| 0.655242 | 3.692756 | false | false | false | false |
mitchsm/nvc
|
test/regress/func17.vhd
| 5 | 477 |
entity func17 is
end entity;
architecture test of func17 is
function func(x : bit_vector) return bit_vector is
variable y : bit_vector(1 to x'length) := x;
begin
y(1 + x'length / 2) := '1'; -- Would corrupt X
return y;
end function;
begin
process is
variable b : bit_vector(1 to 3);
begin
b := "101";
assert func(b) = "111";
assert b = "101";
wait;
end process;
end architecture;
|
gpl-3.0
|
2ed8d04337c3640de742c476544b72e3
| 0.549266 | 3.533333 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/fifo.vhd
| 1 | 4,528 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
entity fifo is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0';
fd : natural := 1
);
port (
cr : in cr_in;
put : in std_logic;
data_in : in std_logic_vector(width - 1 downto 0);
pull : in std_logic;
data_out : out std_logic_vector(width - 1 downto 0);
empty : out std_logic;
full : out std_logic
);
end fifo;
architecture logic of fifo is
type fifo_int is record
put_address : unsigned(depth downto 0);
pull_address : unsigned(depth downto 0);
empty : std_logic;
full : std_logic;
end record;
signal q, r : fifo_int;
begin
comb : process(all)
variable v : fifo_int;
begin
v := r;
v.put_address := r.put_address + u(put);
v.pull_address := r.pull_address + u(pull);
v.empty := is_empty(v.put_address, v.pull_address);
v.full := is_full(v.put_address + fd, v.pull_address) or is_full(v.put_address + fd + 1, v.pull_address);
empty <= r.empty;
full <= r.full;
q <= v;
end process comb;
ram : entity work.ram_dual generic map (width, depth, wr)
port map (
clk => cr.clk,
put => put,
write_address => r.put_address(depth - 1 downto 0),
data_in => data_in,
read_address => q.pull_address(depth - 1 downto 0),
data_out => data_out
);
reg : process(cr)
begin
if rising_edge(cr.clk) then
if cr.rst then
r.put_address <= (others => '0');
r.pull_address <= (others => '0');
r.empty <= '1';
r.full <= '0';
else
r <= q;
end if;
end if;
end process;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
entity fifo_unsigned is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0';
fd : natural := 1
);
port (
cr : in cr_in;
put : in std_logic;
data_in : in unsigned(width - 1 downto 0);
pull : in std_logic;
data_out : out unsigned(width - 1 downto 0);
empty : out std_logic;
full : out std_logic
);
end fifo_unsigned;
architecture logic of fifo_unsigned is
type fifo_int is record
put_address : unsigned(depth downto 0);
pull_address : unsigned(depth downto 0);
empty : std_logic;
full : std_logic;
end record;
signal q, r : fifo_int;
begin
comb : process(all)
variable v : fifo_int;
begin
v := r;
v.put_address := r.put_address + u(put);
v.pull_address := r.pull_address + u(pull);
v.empty := is_empty(v.put_address, v.pull_address);
v.full := is_full(v.put_address + fd, v.pull_address) or is_full(v.put_address + fd + 1, v.pull_address);
empty <= r.empty;
full <= r.full;
q <= v;
end process comb;
ram : entity work.ram_dual_unsigned generic map (width, depth, wr)
port map (
clk => cr.clk,
put => put,
write_address => r.put_address(depth - 1 downto 0),
data_in => data_in,
read_address => q.pull_address(depth - 1 downto 0),
data_out => data_out
);
reg : process(cr)
begin
if rising_edge(cr.clk) then
if cr.rst then
r.put_address <= (others => '0');
r.pull_address <= (others => '0');
r.empty <= '1';
r.full <= '0';
else
r <= q;
end if;
end if;
end process;
end architecture logic;
|
bsd-2-clause
|
d632b1eed155288e00c4be14b6416a63
| 0.45053 | 3.71757 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/dma.vhd
| 1 | 23,418 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
use work.dma_package.all;
entity dma is
port (
i : in dma_in;
o : out dma_out
);
end entity dma;
architecture logic of dma is
signal q, r : dma_int;
signal re : dma_ext;
alias write : std_logic is i.r.tag(PSL_TAG_WIDTH - 1);
alias tag : unsigned(DMA_TAG_WIDTH - 1 downto 0) is i.r.tag(DMA_TAG_WIDTH - 1 downto 0);
begin
comb : process(all)
variable v : dma_int;
begin
----------------------------------------------------------------------------------------------------------------------- default assignments
v := r;
v.read := '0';
v.read_touch := '0';
v.write := '0';
v.write_touch := '0';
v.o.dc.read.valid := '0';
v.o.dc.write.valid := '0';
v.id := r.id + u(i.cd.read.valid or i.cd.write.request.valid);
v.read_credits := r.read_credits + u(i.r.valid and not(write));
v.write_credits := r.write_credits + u(i.r.valid and write);
v.rt.available := not is_full(r.rt.tag, r.rb.pull_address);
v.wt.available := not is_full(r.wt.tag, r.wb.pull_address);
v.rse.engine(r.rse.pull_engine).touch.count := r.rse.engine(r.rse.pull_engine).touch.count + u(r.read and not(r.read_touch));
v.wse.engine(r.wse.pull_engine).touch.count := r.wse.engine(r.wse.pull_engine).touch.count + u(r.write and not(r.write_touch));
if i.b.rad(0) then
v.o.b.rdata := re.wb.data(1023 downto 512);
else
v.o.b.rdata := re.wb.data(511 downto 0);
end if;
----------------------------------------------------------------------------------------------------------------------- select read/write
if l(r.rse.active_count > 0 and r.wse.active_count > 0 and v.read_credits > 0 and v.write_credits > 0) and v.rt.available and v.wt.available then
v.read := not(DMA_WRITE_PRIORITY);
v.write := DMA_WRITE_PRIORITY;
elsif v.rt.available and l(r.rse.active_count > 0 and v.read_credits > 0) then
v.read := '1';
elsif v.wt.available and l(r.wse.active_count > 0 and v.write_credits > 0) then
v.write := '1';
end if;
if v.read then
v.o.c.tag := "0" & r.rt.tag(DMA_TAG_WIDTH - 1 downto 0);
else
v.o.c.tag := "1" & r.wt.tag(DMA_TAG_WIDTH - 1 downto 0);
end if;
v.o.c.valid := v.read or v.write;
v.read_credits := v.read_credits - u(v.read);
v.write_credits := v.write_credits - u(v.write);
v.rt.tag := r.rt.tag + u(v.read);
v.wt.tag := r.wt.tag + u(v.write);
----------------------------------------------------------------------------------------------------------------------- move requests to stream engines
for stream in 0 to DMA_READ_ENGINES - 1 loop
if not(re.rq(stream).empty) and r.rse.free(stream) then
v.rse.free(stream) := '0';
v.rse.ready(stream) := '1';
v.rse.engine(stream).hold := (others => '0');
v.rse.engine(stream).touch.touch := '0';
v.rse.engine(stream).touch.count := (others => '0');
v.rse.engine(stream).touch.address := re.rq(stream).request.address + PSL_PAGESIZE;
v.rse.engine(stream).request := re.rq(stream).request;
end if;
end loop;
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
if not(re.wq(stream).empty) and r.wse.free(stream) then
v.wse.free(stream) := '0';
v.wse.ready(stream) := '1';
v.wse.engine(stream).hold := (others => '0');
v.wse.engine(stream).touch.touch := '0';
v.wse.engine(stream).touch.count := (others => '0');
v.wse.engine(stream).touch.address := re.wq(stream).request.address + PSL_PAGESIZE;
v.wse.engine(stream).request := re.wq(stream).request;
end if;
end loop;
----------------------------------------------------------------------------------------------------------------------- select stream engine
for stream in 0 to DMA_READ_ENGINES - 1 loop
if r.rse.ready(stream) and not(r.rse.free(stream)) then
v.rse.pull_engine := stream;
end if;
end loop;
v.rse.pull_stream := (others => '0');
v.rse.pull_stream(v.rse.pull_engine) := '1';
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
if r.wse.ready(stream) and not(r.wse.free(stream)) and not(re.wqb(stream).empty) then
v.wse.pull_engine := stream;
end if;
end loop;
v.wse.pull_stream := (others => '0');
v.wse.pull_stream(v.wse.pull_engine) := '1';
v.wqb(v.wse.pull_engine) := v.wqb(v.wse.pull_engine) - u(v.write and not(v.write_touch));
----------------------------------------------------------------------------------------------------------------------- generate commands
if v.read then
if DMA_READ_TOUCH and l(r.rse.engine(v.rse.pull_engine).touch.count = DMA_TOUCH_COUNT and r.rse.engine(v.rse.pull_engine).request.size + DMA_TOUCH_COUNT > PSL_PAGESIZE)
and not(r.rse.engine(v.rse.pull_engine).touch.touch)
then
v.o.c.com := PCO_TOUCH_I;
v.o.c.ea := r.rse.engine(v.rse.pull_engine).touch.address;
v.read_touch := '1';
v.rse.engine(v.rse.pull_engine).touch.touch := '1';
v.rse.engine(v.rse.pull_engine).touch.address := r.rse.engine(v.rse.pull_engine).touch.address + PSL_PAGESIZE;
else
v.read_touch := '0';
v.rse.engine(v.rse.pull_engine).touch.touch := '0';
v.o.c.ea := r.rse.engine(v.rse.pull_engine).request.address;
if r.rse.engine(v.rse.pull_engine).request.size < PSL_CACHELINE_BYTES then
v.o.c.size := r.rse.engine(v.rse.pull_engine).request.size(PSL_SIZE_WIDTH - 1 downto 0);
v.o.c.com := PCO_READ_PNA;
else
v.o.c.size := PSL_CACHELINE_BYTES_OUT;
v.o.c.com := PCO_READ_CL_NA;
end if;
v.rse.free(v.rse.pull_engine) := l(r.rse.engine(v.rse.pull_engine).request.size <= PSL_CACHELINE_BYTES);
v.rse.active_count := v.rse.active_count - u(l(r.rse.engine(v.rse.pull_engine).request.size <= PSL_CACHELINE_BYTES));
v.rse.engine(v.rse.pull_engine).request.size := r.rse.engine(v.rse.pull_engine).request.size - PSL_CACHELINE_BYTES;
v.rse.engine(v.rse.pull_engine).request.address := r.rse.engine(v.rse.pull_engine).request.address + PSL_CACHELINE_BYTES;
v.rse.ready(v.rse.pull_engine) := not(v.rse.free(v.rse.pull_engine) or l(r.rse.active_count > 1));
end if;
end if;
if v.write then
if DMA_WRITE_TOUCH and l(r.wse.engine(v.wse.pull_engine).touch.count = DMA_TOUCH_COUNT and r.wse.engine(v.wse.pull_engine).request.size + DMA_TOUCH_COUNT > PSL_PAGESIZE)
and not(r.wse.engine(v.wse.pull_engine).touch.touch)
then
v.o.c.com := PCO_TOUCH_I;
v.o.c.ea := r.wse.engine(v.wse.pull_engine).touch.address;
v.write_touch := '1';
v.wse.engine(v.wse.pull_engine).touch.touch := '1';
v.wse.engine(v.wse.pull_engine).touch.address := r.wse.engine(v.wse.pull_engine).touch.address + PSL_PAGESIZE;
else
v.write_touch := '0';
v.wse.engine(v.wse.pull_engine).touch.touch := '0';
v.o.c.ea := r.wse.engine(v.wse.pull_engine).request.address;
v.o.c.com := PCO_WRITE_NA;
if r.wse.engine(v.wse.pull_engine).request.size <= PSL_CACHELINE_BYTES then
v.o.c.size := r.wse.engine(v.wse.pull_engine).request.size(PSL_SIZE_WIDTH - 1 downto 0);
v.wse.free(v.wse.pull_engine) := '1';
v.wse.active_count := v.wse.active_count - 1;
else
v.o.c.size := PSL_CACHELINE_BYTES_OUT;
end if;
v.wse.engine(v.wse.pull_engine).request.size := r.wse.engine(v.wse.pull_engine).request.size - PSL_CACHELINE_BYTES;
v.wse.engine(v.wse.pull_engine).request.address := r.wse.engine(v.wse.pull_engine).request.address + PSL_CACHELINE_BYTES;
v.wse.ready(v.wse.pull_engine) := not(v.wse.free(v.wse.pull_engine) or l(r.wse.active_count > 1));
end if;
end if;
v.rse.active_count := u(ones(not(v.rse.free)), v.rse.active_count'length);
v.wse.active_count := (others => '0');
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
v.wqb(stream) := v.wqb(stream) + u(i.cd.write.data.valid and i.cd.write.data.stream(stream));
v.wse.active_count := v.wse.active_count + u(l(v.wqb(stream) > 0) and not(v.wse.free(stream)));
end loop;
for stream in 0 to DMA_READ_ENGINES - 1 loop
if not(v.rse.pull_stream(stream)) then
if not(v.rse.free(stream)) and not(v.rse.ready(stream)) then
v.rse.engine(stream).hold := r.rse.engine(stream).hold + u(v.read and not(v.rse.free(stream)));
if v.rse.engine(stream).hold >= v.rse.active_count - 1 then
v.rse.ready(stream) := '1';
v.rse.engine(stream).hold := (others => '0');
end if;
end if;
end if;
end loop;
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
if stream /= v.wse.pull_engine then
if not(v.wse.free(stream)) and not(v.wse.ready(stream)) then
v.wse.engine(stream).hold := r.wse.engine(stream).hold + u(v.write);
if v.wse.engine(stream).hold >= v.wse.active_count - 1 then
v.wse.ready(stream) := '1';
v.wse.engine(stream).hold := (others => '0');
end if;
end if;
end if;
end loop;
--------------------------------------------------------------------------------------------------------------------- handle responses
if i.r.valid and not(write) and
l((i.r.tag < r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.rb.put_flip = r.rb.pull_flip) or
(i.r.tag >= r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.rb.put_flip /= r.rb.pull_flip))
then
v.rb.put_flip := not r.rb.put_flip;
end if;
if i.r.valid and write and
l((tag < r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.wb.put_flip = r.wb.pull_flip) or
(tag >= r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.wb.put_flip /= r.wb.pull_flip))
then
v.wb.put_flip := not r.wb.put_flip;
end if;
if i.r.valid then
if write then
v.wb.status(idx(tag)) := v.wb.put_flip;
else
v.rb.status(idx(tag)) := v.rb.put_flip;
end if;
end if;
if r.rb.status(idx(r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0))) = r.rb.pull_flip then
v.o.dc.read.valid := not re.rh.touch;
v.rb.pull_address := r.rb.pull_address + 1;
if r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0) = (DMA_TAG_WIDTH - 1 downto 0 => '1') then
v.rb.pull_flip := not r.rb.pull_flip;
end if;
elsif r.wb.status(idx(r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0))) = r.wb.pull_flip then
v.o.dc.write.valid := not re.wh.touch;
v.wb.pull_address := r.wb.pull_address + 1;
if r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0) = (DMA_TAG_WIDTH - 1 downto 0 => '1') then
v.wb.pull_flip := not r.wb.pull_flip;
end if;
end if;
----------------------------------------------------------------------------------------------------------------------- outputs
q <= v;
o <= r.o;
o.dc.id <= q.id;
o.dc.read.id <= re.rh.id;
o.dc.read.stream <= slv(re.rh.stream);
o.dc.read.data <= re.rb.data1 & re.rb.data0;
for stream in 0 to DMA_READ_ENGINES - 1 loop
o.dc.read.full(stream) <= re.rq(stream).full;
end loop;
o.dc.write.id <= re.wh.id;
o.dc.write.stream <= slv(re.wh.stream);
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
o.dc.write.full(stream) <= re.wq(stream).full or l(r.wqb(stream) >= (2**DMA_WRITE_QUEUE_DEPTH - 4));
end loop;
end process comb;
----------------------------------------------------------------------------------------------------------------------- read queues
rqs : for stream in 0 to DMA_READ_ENGINES - 1 generate
rq : entity work.fifo_unsigned generic map (DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH, DMA_WRITE_QUEUE_DEPTH, '1', 1)
port map (
cr => i.cr,
put => i.cd.read.valid and i.cd.read.stream(stream),
data_in => r.id & i.cd.read.address & i.cd.read.size,
pull => not(re.rq(stream).empty) and r.rse.free(stream),
data_out => re.rq(stream).data,
empty => re.rq(stream).empty,
full => re.rq(stream).full
);
re.rq(stream).request.id <= re.rq(stream).data(DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH);
re.rq(stream).request.address <= re.rq(stream).data(PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto DMA_SIZE_WIDTH);
re.rq(stream).request.size <= re.rq(stream).data(DMA_SIZE_WIDTH - 1 downto 0);
end generate rqs;
----------------------------------------------------------------------------------------------------------------------- write queues + buffers
wqs : for stream in 0 to DMA_WRITE_ENGINES - 1 generate
wq : entity work.fifo_unsigned generic map (DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH, DMA_WRITE_QUEUE_DEPTH, '1', 1)
port map (
cr => i.cr,
put => i.cd.write.request.valid and i.cd.write.request.stream(stream),
data_in => r.id & i.cd.write.request.address & i.cd.write.request.size,
pull => not(re.wq(stream).empty) and r.wse.free(stream),
data_out => re.wq(stream).data,
empty => re.wq(stream).empty,
full => re.wq(stream).full
);
re.wq(stream).request.id <= re.wq(stream).data(DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH);
re.wq(stream).request.address <= re.wq(stream).data(PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto DMA_SIZE_WIDTH);
re.wq(stream).request.size <= re.wq(stream).data(DMA_SIZE_WIDTH - 1 downto 0);
wqb : entity work.fifo generic map (DMA_DATA_WIDTH, DMA_WRITE_BUFFER_DEPTH, '0', 1)
port map (
cr => i.cr,
put => i.cd.write.data.valid and i.cd.write.data.stream(stream),
data_in => endian_swap(i.cd.write.data.data),
pull => r.write and not(r.write_touch) and r.wse.pull_stream(stream),
data_out => re.wqb(stream).data,
empty => re.wqb(stream).empty,
full => re.wqb(stream).full
);
end generate wqs;
----------------------------------------------------------------------------------------------------------------------- write buffer
wb : entity work.ram_dual generic map (DMA_DATA_WIDTH, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => r.write,
write_address => r.o.c.tag(DMA_TAG_WIDTH - 1 downto 0),
data_in => re.wqb(r.wse.pull_engine).data,
read_address => i.b.rtag(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.wb.data
);
----------------------------------------------------------------------------------------------------------------------- read buffer
rb0 : entity work.ram_dual generic map (PSL_DATA_WIDTH, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => i.b.wvalid and not(i.b.wad(0)),
write_address => i.b.wtag(DMA_TAG_WIDTH - 1 downto 0),
data_in => endian_swap(i.b.wdata),
read_address => r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.rb.data0
);
rb1 : entity work.ram_dual generic map (PSL_DATA_WIDTH, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => i.b.wvalid and i.b.wad(0),
write_address => i.b.wtag(DMA_TAG_WIDTH - 1 downto 0),
data_in => endian_swap(i.b.wdata),
read_address => r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.rb.data1
);
----------------------------------------------------------------------------------------------------------------------- command history
rh : entity work.ram_dual_unsigned generic map (DMA_ID_WIDTH + DMA_READ_ENGINES + 1, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => r.read,
write_address => r.o.c.tag(DMA_TAG_WIDTH - 1 downto 0),
data_in => r.rse.engine(r.rse.pull_engine).request.id & u(r.rse.pull_stream) & r.rse.engine(r.rse.pull_engine).touch.touch,
read_address => r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.rh.data
);
re.rh.id <= re.rh.data(DMA_ID_WIDTH + DMA_READ_ENGINES downto DMA_READ_ENGINES + 1);
re.rh.stream <= re.rh.data(DMA_READ_ENGINES downto 1);
re.rh.touch <= re.rh.data(0);
wh : entity work.ram_dual_unsigned generic map (DMA_ID_WIDTH + DMA_WRITE_ENGINES + 1, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => r.write,
write_address => r.o.c.tag(DMA_TAG_WIDTH - 1 downto 0),
data_in => r.wse.engine(r.wse.pull_engine).request.id & u(r.wse.pull_stream) & r.wse.engine(r.wse.pull_engine).touch.touch,
read_address => r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.wh.data
);
re.wh.id <= re.wh.data(DMA_ID_WIDTH + DMA_WRITE_ENGINES downto DMA_WRITE_ENGINES + 1);
re.wh.stream <= re.wh.data(DMA_WRITE_ENGINES downto 1);
re.wh.touch <= re.wh.data(0);
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(i.cr)
begin
if rising_edge(i.cr.clk) then
if i.cr.rst then
dma_reset(r);
else
r <= q;
end if;
end if;
end process;
end architecture logic;
|
bsd-2-clause
|
14018701e274205a00fec29d73d14e12
| 0.406012 | 4.066331 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare2.vhd
| 2 | 4,438 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare2.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare2 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare2;
ARCHITECTURE SYN OF lpm_compare2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "1000001011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "523"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 523 0 0 10 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
50f209e03fd1a0acad7a49dd1a82f0cb
| 0.655475 | 3.695254 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/IF_ID_Register.vhd
| 2 | 2,840 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:48:24 11/21/2013
-- Design Name:
-- Module Name: IF_ID_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IF_ID_Register is
Port ( NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_PC_OR_NOT : in STD_LOGIC := WRITE_PC_YES;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
CLK : in STD_LOGIC;
INST_IN : in STD_LOGIC_VECTOR (15 downto 0) := NOP_INST;
WRITE_IR_OR_NOT : in STD_LOGIC := WRITE_IR_YES;
WRITE_IR_SRC_SELEC : in STD_LOGIC := WRITE_IR_SRC_SELEC_ORIGIN;
INST_OUT_CODE : out STD_LOGIC_VECTOR(4 downto 0) := NOP_INST(15 downto 11);
INST_OUT_RS : out STD_LOGIC_VECTOR(2 downto 0) := NOP_INST(10 downto 8);
INST_OUT_RT : out STD_LOGIC_VECTOR(2 downto 0) := NOP_INST(7 downto 5);
INST_OUT_RD : out STD_LOGIC_VECTOR(2 downto 0) := NOP_INST(4 downto 2);
INST_OUT_FUNC : out STD_LOGIC_VECTOR(1 downto 0) := NOP_INST(1 downto 0)
);
end IF_ID_Register;
architecture Behavioral of IF_ID_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
-- update value at up edge
if (WRITE_PC_OR_NOT = WRITE_PC_YES) then
NEW_PC_OUT <= NEW_PC_IN;
end if;
if (WRITE_IR_OR_NOT = WRITE_IR_YES ) then
case WRITE_IR_SRC_SELEC is
when WRITE_IR_SRC_SELEC_ORIGIN =>
INST_OUT_CODE <= INST_IN(15 downto 11);
INST_OUT_RS <= INST_IN(10 downto 8);
INST_OUT_RT <= INST_IN(7 downto 5);
INST_OUT_RD <= INST_IN(4 downto 2);
INST_OUT_FUNC <= INST_IN(1 downto 0);
when WRITE_IR_SRC_SELEC_NOP =>
INST_OUT_CODE <= NOP_INST(15 downto 11);
INST_OUT_RS <= NOP_INST(10 downto 8);
INST_OUT_RT <= NOP_INST(7 downto 5);
INST_OUT_RD <= NOP_INST(4 downto 2);
INST_OUT_FUNC <= NOP_INST(1 downto 0);
when others =>
INST_OUT_CODE <= INST_IN(15 downto 11);
INST_OUT_RS <= INST_IN(10 downto 8);
INST_OUT_RT <= INST_IN(7 downto 5);
INST_OUT_RD <= INST_IN(4 downto 2);
INST_OUT_FUNC <= INST_IN(1 downto 0);
end case;
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
892f58e70b1d481b12dd28453b767df8
| 0.586972 | 3.131202 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramstates.vhd
| 1 | 12,373 |
----------------------------------------------------------------------------
--
-- Oscilloscope VRAM State Machine
--
-- This is an implementation of a VRAM State machine for a digital scope in
-- VHDL. There are three inputs to the system, one selects the trigger
-- slope and the other two determine the relationship between the trigger
-- level and the signal level. The only output is a trigger signal which
-- indicates a trigger event has occurred.
--
-- The file contains multiple architectures for a Moore state machine
-- implementation to demonstrate the different ways of building a state
-- machine.
--
--
-- Revision History:
-- 2014/02/23 Albert Gural Created file and updated with VRAM
-- state machine.
-- 2014/06/07 Albert Gural Added idle states to improve r/w speeds.
--
----------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
--
-- Oscilloscope VRAM entity declaration
--
entity ScopeVRAM is
port (
clk : in std_logic; -- clock input
reset : in std_logic; -- reset to idle state (active low)
cs : in std_logic; -- whether CPU is requesting R/W (active low)
rw : in std_logic; -- whether CPU is requesting R or W
srt : in std_logic; -- display requesting serial row transfer
RAS : out std_logic; -- row address select output
CAS : out std_logic; -- col address select output
TRG : out std_logic; -- trigger output (active low)
WE : out std_logic; -- write enable output (active low)
AS : out std_logic_vector(1 downto 0); -- address select
-- 00 = low 9 bits
-- 01 = high 9 bits
-- 10 = row transfer
-- 11 = col transfer (0)
ACK : out std_logic; -- send acknowledge back to display driver
BUSY : out std_logic -- busy signal to CPU for read/write
);
end ScopeVRAM;
--
-- Oscilloscope VRAM Moore State Machine
-- State Assignment Architecture
--
-- This architecture just shows the basic state machine syntax when the state
-- assignments are made manually. This is useful for minimizing output
-- decoding logic and avoiding glitches in the output (due to the decoding
-- logic).
--
architecture assign_statebits of ScopeVRAM is
subtype states is std_logic_vector(12 downto 0); -- state type
-- define the actual states as constants
-- bits: [RAS][CAS][TRG][WE][AS<2>][ACK][BUSY]
-- [type <000 IDLE, 010 READ, 011 WRITE, 100 REFRESH, 101 TRANSFER>]
-- [number <00, 01, ...>]
constant IDLE : states := "1111011100000"; -- idle (can accept R/W)
constant IDLE2 : states := "1111011100001"; -- idle (can accept R/W)
constant IDLE3 : states := "1111011100010"; -- idle (can accept R/W)
constant IDLE4 : states := "1111011100011"; -- idle (can accept R/W, srt, refresh)
constant READ1 : states := "1111011101000"; -- read cycle
constant READ2 : states := "0111011101000"; -- read cycle
constant READ3 : states := "0101001101000"; -- read cycle
constant READ4 : states := "0001001101000"; -- read cycle
constant READ5 : states := "0001001101001"; -- read cycle
constant READ6 : states := "0001001001010"; -- read cycle
constant READ7 : states := "1111001101000"; -- read cycle
constant READ8 : states := "1111001101001"; -- read cycle
constant READ9 : states := "1111001101010"; -- read cycle
constant WRITE1 : states := "0111011101100"; -- write cycle
constant WRITE2 : states := "0110001101100"; -- write cycle
constant WRITE3 : states := "0010001101100"; -- write cycle
constant WRITE4 : states := "0010001001101"; -- write cycle
constant WRITE5 : states := "1111001101100"; -- write cycle
constant WRITE6 : states := "1111001101101"; -- write cycle
constant WRITE7 : states := "1111001101110"; -- write cycle
constant TRANSFER1 : states := "1101101110100"; -- transfer cycle
constant TRANSFER2 : states := "0101101110100"; -- transfer cycle
constant TRANSFER3 : states := "0111111110100"; -- transfer cycle
constant TRANSFER4 : states := "0011111110100"; -- transfer cycle
constant TRANSFER5 : states := "1111010110100"; -- transfer cycle
constant TRANSFER6 : states := "1111011110100"; -- transfer cycle
constant REFRESH1 : states := "1111001110000"; -- refresh cycle
constant REFRESH2 : states := "1111001110001"; -- refresh cycle
constant REFRESH3 : states := "1011001110000"; -- refresh cycle
constant REFRESH4 : states := "0011001110000"; -- refresh cycle
constant REFRESH5 : states := "0011001110001"; -- refresh cycle
constant REFRESH6 : states := "0011001110010"; -- refresh cycle
constant REFRESH7 : states := "1111001110010"; -- refresh cycle
constant REFRESH8 : states := "1111001110011"; -- refresh cycle
signal CurrentState : states; -- current state
signal NextState : states; -- next state
begin
-- the output is always the high bit of the state encoding
RAS <= CurrentState(12);
CAS <= CurrentState(11);
TRG <= CurrentState(10);
WE <= CurrentState(9);
AS <= CurrentState(8 downto 7);
ACK <= CurrentState(6);
BUSY <= CurrentState(5);
-- compute the next state (function of current state and inputs)
transition: process (reset, cs, rw, srt, CurrentState)
begin
case CurrentState is -- do the state transition/output
when IDLE => -- in idle state, do transition
if (cs = '0' and rw = '1') then
NextState <= READ1; -- start read cycle
elsif (cs = '0' and rw = '0') then
NextState <= WRITE1; -- start write cycle
else
NextState <= IDLE2; -- start refresh cycle
end if;
when IDLE2 => -- in idle state, do transition
if (cs = '0' and rw = '1') then
NextState <= READ1; -- start read cycle
elsif (cs = '0' and rw = '0') then
NextState <= WRITE1; -- start write cycle
else
NextState <= IDLE3; -- start refresh cycle
end if;
when IDLE3 => -- in idle state, do transition
if (cs = '0' and rw = '1') then
NextState <= READ1; -- start read cycle
elsif (cs = '0' and rw = '0') then
NextState <= WRITE1; -- start write cycle
else
NextState <= IDLE4; -- start refresh cycle
end if;
when IDLE4 => -- in idle state, do transition
if (cs = '0' and rw = '1') then
NextState <= READ1; -- start read cycle
elsif (cs = '0' and rw = '0') then
NextState <= WRITE1; -- start write cycle
elsif (srt = '1') then
NextState <= TRANSFER1; -- start serial row transfer
else
NextState <= REFRESH1; -- start refresh cycle
end if;
when READ1 => -- read cycle
NextState <= READ2; -- go to next part of read cycle
when READ2 => -- read cycle
NextState <= READ3; -- go to next part of read cycle
when READ3 => -- read cycle
NextState <= READ4; -- go to next part of read cycle
when READ4 => -- read cycle
NextState <= READ5; -- go to next part of read cycle
when READ5 => -- read cycle
NextState <= READ6; -- go to next part of read cycle
when READ6 => -- read cycle
NextState <= READ7; -- go to next part of read cycle
when READ7 => -- read cycle
NextState <= READ8; -- go to next part of read cycle
when READ8 => -- read cycle
NextState <= READ9; -- go to next part of read cycle
when READ9 => -- read cycle
NextState <= IDLE; -- go back to idle
when WRITE1 => -- write cycle
NextState <= WRITE2; -- go to next part of write cycle
when WRITE2 => -- write cycle
NextState <= WRITE3; -- go to next part of write cycle
when WRITE3 => -- write cycle
NextState <= WRITE4; -- go to next part of write cycle
when WRITE4 => -- write cycle
NextState <= WRITE5; -- go to next part of write cycle
when WRITE5 => -- write cycle
NextState <= WRITE6; -- go to next part of write cycle
when WRITE6 => -- write cycle
NextState <= WRITE7; -- go to next part of write cycle
when WRITE7 => -- write cycle
NextState <= IDLE; -- go back to idle
when TRANSFER1 => -- transfer cycle
NextState <= TRANSFER2; -- go to next part of transfer cycle
when TRANSFER2 => -- transfer cycle
NextState <= TRANSFER3; -- go to next part of transfer cycle
when TRANSFER3 => -- transfer cycle
NextState <= TRANSFER4; -- go to next part of transfer cycle
when TRANSFER4 => -- transfer cycle
NextState <= TRANSFER5; -- go to next part of transfer cycle
when TRANSFER5 => -- transfer cycle
NextState <= TRANSFER6; -- go to next part of transfer cycle
when TRANSFER6 => -- transfer cycle
NextState <= IDLE; -- go back to idle
when REFRESH1 => -- refresh cycle
NextState <= REFRESH2; -- go to next part of refresh cycle
when REFRESH2 => -- refresh cycle
NextState <= REFRESH3; -- go to next part of refresh cycle
when REFRESH3 => -- refresh cycle
NextState <= REFRESH4; -- go to next part of refresh cycle
when REFRESH4 => -- refresh cycle
NextState <= REFRESH5; -- go to next part of refresh cycle
when REFRESH5 => -- refresh cycle
NextState <= REFRESH6; -- go to next part of refresh cycle
when REFRESH6 => -- refresh cycle
NextState <= REFRESH7; -- go to next part of refresh cycle
when REFRESH7 => -- refresh cycle
NextState <= REFRESH8; -- go to next part of refresh cycle
when REFRESH8 => -- refresh cycle
NextState <= IDLE; -- go back to idle
when others => -- default
NextState <= IDLE; -- go back to idle
end case;
if reset = '1' then -- reset overrides everything
NextState <= IDLE; -- go to idle on reset
end if;
end process transition;
-- storage of current state (loads the next state on the clock)
process (clk)
begin
if clk = '1' then -- only change on rising edge of clock
CurrentState <= NextState; -- save the new state information
end if;
end process;
end assign_statebits;
|
mit
|
93439cef58dee35cf0949f34bd74a946
| 0.515235 | 4.688518 | false | false | false | false |
blutsvente/MIX
|
test/results/macro/splice/inst_t_e-rtl-a.vhd
| 1 | 15,896 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:03:31 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
s_splice_1 : out std_ulogic_vector(3 downto 0);
s_splice_2 : out std_ulogic_vector(2 downto 0);
s_splice_3 : out std_ulogic_vector(15 downto 0);
s_splice_4 : out std_ulogic_vector(15 downto 0);
s_splice_5 : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_splice_1 : in std_ulogic_vector(3 downto 0); -- Splice signal connector up 1, 1Splice signal connector up 1, 0Splice signal connector up 1, 2S...
p_splice_2 : in std_ulogic_vector(2 downto 0); -- Splice signal connector up 2, 1Splice signal connector up 2, 0Splice signal connector up 2, 2
p_splice_3 : in std_ulogic_vector(15 downto 0); -- Splice signal connector up 3, 14Splice signal connector up 3, 3Splice signal connector up 3, 6...
p_splice_4 : in std_ulogic_vector(15 downto 0); -- Splice signal connector up, joined 4, 0
p_splice_5 : in std_ulogic_vector(7 downto 0) -- Splice signal connector up, joined 5, 0
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_splice_e_s -- splice box
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_e_s
p_mix_s_splice_3_0_go : out std_ulogic;
p_mix_s_splice_3_10_go : out std_ulogic;
p_mix_s_splice_3_11_go : out std_ulogic;
p_mix_s_splice_3_12_go : out std_ulogic;
p_mix_s_splice_3_13_go : out std_ulogic;
p_mix_s_splice_3_14_go : out std_ulogic;
p_mix_s_splice_3_15_go : out std_ulogic;
p_mix_s_splice_3_1_go : out std_ulogic;
p_mix_s_splice_3_2_go : out std_ulogic;
p_mix_s_splice_3_3_go : out std_ulogic;
p_mix_s_splice_3_4_go : out std_ulogic;
p_mix_s_splice_3_5_go : out std_ulogic;
p_mix_s_splice_3_6_go : out std_ulogic;
p_mix_s_splice_3_7_go : out std_ulogic;
p_mix_s_splice_3_8_go : out std_ulogic;
p_mix_s_splice_3_9_go : out std_ulogic;
p_mix_s_splice_3_gi : in std_ulogic_vector(15 downto 0);
p_mix_s_splice_4_gi : in std_ulogic_vector(15 downto 0);
p_mix_s_splice_5_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_splice_join_4_go : out std_ulogic_vector(15 downto 0);
p_mix_s_splice_join_5_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_splice_e_s
);
end component;
-- ---------
component inst_splice_1_0_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_0_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_0 : out std_ulogic -- Splice signal connector up 1, 0
-- End of Generated Port for Entity inst_splice_1_0_e_s
);
end component;
-- ---------
component inst_splice_1_1_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_1_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_1 : out std_ulogic -- Splice signal connector up 1, 1
-- End of Generated Port for Entity inst_splice_1_1_e_s
);
end component;
-- ---------
component inst_splice_1_2_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_2_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_2 : out std_ulogic -- Splice signal connector up 1, 2
-- End of Generated Port for Entity inst_splice_1_2_e_s
);
end component;
-- ---------
component inst_splice_1_3_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_1_3_e_s
s_splice_1 : in std_ulogic; -- Splice signal connector in: 1, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_1_3 : out std_ulogic -- Splice signal connector up 1, 3
-- End of Generated Port for Entity inst_splice_1_3_e_s
);
end component;
-- ---------
component inst_splice_2_0_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_2_0_e_s
s_splice_2 : in std_ulogic; -- Splice signal connector in: 2, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_2_0 : out std_ulogic -- Splice signal connector up 2, 0
-- End of Generated Port for Entity inst_splice_2_0_e_s
);
end component;
-- ---------
component inst_splice_2_1_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_2_1_e_s
s_splice_2 : in std_ulogic; -- Splice signal connector in: 2, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_2_1 : out std_ulogic -- Splice signal connector up 2, 1
-- End of Generated Port for Entity inst_splice_2_1_e_s
);
end component;
-- ---------
component inst_splice_2_2_e_s
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_2_2_e_s
s_splice_2 : in std_ulogic; -- Splice signal connector in: 2, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_2_2 : out std_ulogic -- Splice signal connector up 2, 2
-- End of Generated Port for Entity inst_splice_2_2_e_s
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_splice_1 : std_ulogic_vector(3 downto 0);
signal s_splice_1_0 : std_ulogic;
signal s_splice_1_1 : std_ulogic;
signal s_splice_1_2 : std_ulogic;
signal s_splice_1_3 : std_ulogic;
signal s_splice_2 : std_ulogic_vector(2 downto 0);
signal s_splice_2_0 : std_ulogic;
signal s_splice_2_1 : std_ulogic;
signal s_splice_2_2 : std_ulogic;
signal s_splice_3 : std_ulogic_vector(15 downto 0);
signal s_splice_3_0 : std_ulogic;
signal s_splice_3_1 : std_ulogic;
signal s_splice_3_10 : std_ulogic;
signal s_splice_3_11 : std_ulogic;
signal s_splice_3_12 : std_ulogic;
signal s_splice_3_13 : std_ulogic;
signal s_splice_3_14 : std_ulogic;
signal s_splice_3_15 : std_ulogic;
signal s_splice_3_2 : std_ulogic;
signal s_splice_3_3 : std_ulogic;
signal s_splice_3_4 : std_ulogic;
signal s_splice_3_5 : std_ulogic;
signal s_splice_3_6 : std_ulogic;
signal s_splice_3_7 : std_ulogic;
signal s_splice_3_8 : std_ulogic;
signal s_splice_3_9 : std_ulogic;
signal s_splice_4 : std_ulogic_vector(15 downto 0);
signal s_splice_5 : std_ulogic_vector(7 downto 0);
signal s_splice_join_4 : std_ulogic_vector(15 downto 0);
signal s_splice_join_5 : std_ulogic_vector(7 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
s_splice_1 => s_splice_1, -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_2 => s_splice_2, -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_3 => s_splice_3, -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_4 => s_splice_4, -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
s_splice_5 => s_splice_5 -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
p_splice_1(0) => s_splice_1_0, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 0
p_splice_1(1) => s_splice_1_1, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 1
p_splice_1(2) => s_splice_1_2, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 2
p_splice_1(3) => s_splice_1_3, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 1, 3
p_splice_2(0) => s_splice_2_0, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 2, 0
p_splice_2(1) => s_splice_2_1, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 2, 1
p_splice_2(2) => s_splice_2_2, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 2, 2
p_splice_3(0) => s_splice_3_0, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 0
p_splice_3(1) => s_splice_3_1, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 1
p_splice_3(10) => s_splice_3_10, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 10
p_splice_3(11) => s_splice_3_11, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 11
p_splice_3(12) => s_splice_3_12, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 12
p_splice_3(13) => s_splice_3_13, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 13
p_splice_3(14) => s_splice_3_14, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 14
p_splice_3(15) => s_splice_3_15, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 15
p_splice_3(2) => s_splice_3_2, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 2
p_splice_3(3) => s_splice_3_3, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 3
p_splice_3(4) => s_splice_3_4, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 4
p_splice_3(5) => s_splice_3_5, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 5
p_splice_3(6) => s_splice_3_6, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 6
p_splice_3(7) => s_splice_3_7, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 7
p_splice_3(8) => s_splice_3_8, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 8
p_splice_3(9) => s_splice_3_9, -- __I_BIT_TO_BUSPORT -- Splice signal connector up 3, 9
p_splice_4 => s_splice_join_4, -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
p_splice_5 => s_splice_join_5 -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_splice
inst_splice: inst_splice_e_s -- splice box
port map (
p_mix_s_splice_3_0_go => s_splice_3_0, -- Splice signal connector up 3, 0
p_mix_s_splice_3_10_go => s_splice_3_10, -- Splice signal connector up 3, 10
p_mix_s_splice_3_11_go => s_splice_3_11, -- Splice signal connector up 3, 11
p_mix_s_splice_3_12_go => s_splice_3_12, -- Splice signal connector up 3, 12
p_mix_s_splice_3_13_go => s_splice_3_13, -- Splice signal connector up 3, 13
p_mix_s_splice_3_14_go => s_splice_3_14, -- Splice signal connector up 3, 14
p_mix_s_splice_3_15_go => s_splice_3_15, -- Splice signal connector up 3, 15
p_mix_s_splice_3_1_go => s_splice_3_1, -- Splice signal connector up 3, 1
p_mix_s_splice_3_2_go => s_splice_3_2, -- Splice signal connector up 3, 2
p_mix_s_splice_3_3_go => s_splice_3_3, -- Splice signal connector up 3, 3
p_mix_s_splice_3_4_go => s_splice_3_4, -- Splice signal connector up 3, 4
p_mix_s_splice_3_5_go => s_splice_3_5, -- Splice signal connector up 3, 5
p_mix_s_splice_3_6_go => s_splice_3_6, -- Splice signal connector up 3, 6
p_mix_s_splice_3_7_go => s_splice_3_7, -- Splice signal connector up 3, 7
p_mix_s_splice_3_8_go => s_splice_3_8, -- Splice signal connector up 3, 8
p_mix_s_splice_3_9_go => s_splice_3_9, -- Splice signal connector up 3, 9
p_mix_s_splice_3_gi => s_splice_3, -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
p_mix_s_splice_4_gi => s_splice_4, -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
p_mix_s_splice_5_gi => s_splice_5, -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
p_mix_s_splice_join_4_go => s_splice_join_4, -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
p_mix_s_splice_join_5_go => s_splice_join_5 -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
);
-- End of Generated Instance Port Map for inst_splice
-- Generated Instance Port Map for inst_splice_1_0
inst_splice_1_0: inst_splice_1_0_e_s
port map (
s_splice_1 => s_splice_1(0), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_0 => s_splice_1_0 -- Splice signal connector up 1, 0
);
-- End of Generated Instance Port Map for inst_splice_1_0
-- Generated Instance Port Map for inst_splice_1_1
inst_splice_1_1: inst_splice_1_1_e_s
port map (
s_splice_1 => s_splice_1(1), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_1 => s_splice_1_1 -- Splice signal connector up 1, 1
);
-- End of Generated Instance Port Map for inst_splice_1_1
-- Generated Instance Port Map for inst_splice_1_2
inst_splice_1_2: inst_splice_1_2_e_s
port map (
s_splice_1 => s_splice_1(2), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_2 => s_splice_1_2 -- Splice signal connector up 1, 2
);
-- End of Generated Instance Port Map for inst_splice_1_2
-- Generated Instance Port Map for inst_splice_1_3
inst_splice_1_3: inst_splice_1_3_e_s
port map (
s_splice_1 => s_splice_1(3), -- Splice signal connector in: 1, 0Splice signal connector in: 1, 1Splice signal connector in: 1,...
s_splice_1_3 => s_splice_1_3 -- Splice signal connector up 1, 3
);
-- End of Generated Instance Port Map for inst_splice_1_3
-- Generated Instance Port Map for inst_splice_2_0
inst_splice_2_0: inst_splice_2_0_e_s
port map (
s_splice_2 => s_splice_2(0), -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_2_0 => s_splice_2_0 -- Splice signal connector up 2, 0
);
-- End of Generated Instance Port Map for inst_splice_2_0
-- Generated Instance Port Map for inst_splice_2_1
inst_splice_2_1: inst_splice_2_1_e_s
port map (
s_splice_2 => s_splice_2(1), -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_2_1 => s_splice_2_1 -- Splice signal connector up 2, 1
);
-- End of Generated Instance Port Map for inst_splice_2_1
-- Generated Instance Port Map for inst_splice_2_2
inst_splice_2_2: inst_splice_2_2_e_s
port map (
s_splice_2 => s_splice_2(2), -- Splice signal connector in: 2, 0Splice signal connector in: 2, 1Splice signal connector in: 2,...
s_splice_2_2 => s_splice_2_2 -- Splice signal connector up 2, 2
);
-- End of Generated Instance Port Map for inst_splice_2_2
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
9335d12eec9163f4121abf329eae31e7
| 0.650793 | 2.720055 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter5.vhd
| 1 | 4,437 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter5.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter5 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_counter5;
ARCHITECTURE SYN OF lpm_counter5 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(8 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 272,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 9
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "272"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "272"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
17f757ce64f1ae8b36e9f8c91412071c
| 0.651566 | 3.685216 | false | false | false | false |
mitchsm/nvc
|
test/regress/attr6.vhd
| 4 | 895 |
entity attr6 is
end entity;
architecture test of attr6 is
signal x : integer := 5;
signal y : bit_vector(0 to 3);
begin
process is
begin
assert x'last_event = time'high;
x <= 0;
assert x'last_value = x;
assert x'last_value = 5;
wait for 1 ns;
assert x'last_value = 5;
assert x'last_event = 1 ns;
x <= 2;
wait for 1 ns;
assert x = 2;
assert x'last_value = 0;
assert x'last_event = 1 ns;
assert y'last_value = y;
y <= ( '0', '1', '0', '1' );
wait for 1 ns;
assert y'last_value = ( '0', '0', '0', '0' );
y(1) <= '1';
wait for 1 ns;
assert y'last_value = ( '0', '0', '0', '0' );
y(1) <= '0';
wait for 1 ns;
assert y'last_value = ( '0', '1', '0', '0' );
wait;
end process;
end architecture;
|
gpl-3.0
|
1fef68524cea951349e3891d5fbe0a87
| 0.458101 | 3.118467 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/ioblock0_e-rtl-a.vhd
| 1 | 5,326 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock0_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-rtl-a.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ioblock0_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock0_e
--
architecture rtl of ioblock0_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_g_i --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_di : in std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
constant nand_out_0_c : std_ulogic := '0';
signal nand_out_0 : std_ulogic;
signal nand_out_1 : std_ulogic;
signal nand_out_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
nand_out_0 <= nand_out_0_c;
p_mix_nand_out_2_go <= nand_out_2; -- __I_O_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_g_i_1
ioc_g_i_1: ioc_g_i
port map (
di => data_i1, -- io data
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_0, -- Links ...
nand_out => nand_out_1, -- Links ...
p_di => pad_di_1, -- data in from pad
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_g_i_1
-- Generated Instance Port Map for ioc_g_o_2
ioc_g_o_2: ioc_g_o
port map (
do => data_o1, -- io data
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_1, -- Links ...
nand_out => nand_out_2, -- Links ...
p_do => pad_do_2, -- data out to pad
p_en => pad_en_2, -- pad output enable
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_g_o_2
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
643b2f274b54a2a9b1657b409d1815db
| 0.578858 | 2.590467 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_input_scalars_module.vhd
| 1 | 16,206 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_input_scalars_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_input_scalars_fifo;
entity xd_input_scalars_module is
generic (
-- System generics:
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MAX_N_ISCALARS : integer;
C_N_INPUT_SCALARS : integer;
C_N_INOUT_SCALARS : integer;
C_INPUT_SCALAR_DWIDTH : std_logic_vector;
C_AP_ISCALAR_DOUT_WIDTH : integer;
C_NONE : integer := 2);
port (
clk : in std_logic;
rst : in std_logic;
iscalar_rst : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
iscalar_din : in std_logic_vector(31 downto 0);
iscalar_we : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_empty : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_full : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_used : out std_logic_vector(C_MAX_N_ISCALARS*4-1 downto 0);
--- AP input scalars
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_rst_s_axi_aclk : in std_logic;
ap_iscalar_rdy : out std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
ap_iscalar_done : in std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
ap_iscalar_dout : out std_logic_vector(C_AP_ISCALAR_DOUT_WIDTH-1 downto 0));
end entity;
architecture rtl of xd_input_scalars_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
signal status_iscalar_used_i : std_logic_vector(C_MAX_N_ISCALARS*4-1 downto 0);
signal status_iscalar_empty_i : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
signal ap_iscalar_rdy_i : std_logic_vector(C_MAX_N_ISCALARS-1 downto 0);
begin
INPUT_SCALARS_GEN : for i in 0 to C_MAX_N_ISCALARS-1 generate
begin
ACTIVE_GEN : if (i < C_N_INPUT_SCALARS) generate
constant ISCALAR_DWIDTH : integer := get_int_element(C_INPUT_SCALAR_DWIDTH, i);
constant ISCALAR_LSB : integer := get_compact_LSB(C_INPUT_SCALAR_DWIDTH, i);
constant ISCALAR_MSB : integer := get_compact_MSB(C_INPUT_SCALAR_DWIDTH, i);
signal dout_i : std_logic_vector(ISCALAR_DWIDTH-1 downto 0);
signal empty : std_logic;
signal fifo_rst_reg : std_logic;
begin
-- fifo_rst <= ap_rst_s_axi_aclk or iscalar_rst(i);
process(clk, ap_rst_s_axi_aclk)
begin
if(ap_rst_s_axi_aclk = '1') then
fifo_rst_reg <= '1';
elsif(clk'event and clk = '1') then
fifo_rst_reg <= iscalar_rst(i);
end if;
end process;
-- Input scalars must show a behaviour equal to the input arguments in
-- the sense that written data by the processor must be inmediatelly
-- available for the accelerator. So a write-through FIFO is used.
FIFO_I : entity axis_accelerator_adapter_v2_1_6.xd_input_scalars_fifo
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
WIDTH => ISCALAR_DWIDTH)
port map (
din => iscalar_din(ISCALAR_DWIDTH-1 downto 0),
din_vld => iscalar_we(i),
din_rdy => open,
wr_used => status_iscalar_used_i(4*(i+1)-1 downto 4*i),
wr_empty => status_iscalar_empty_i(i),
wr_full => status_iscalar_full(i),
wr_clk => clk,
dout => dout_i,
dout_vld => ap_iscalar_rdy_i(i),
dout_rdy => ap_iscalar_done(i),
rd_clk => ap_clk,
rst => fifo_rst_reg);
ap_iscalar_dout(ISCALAR_MSB downto ISCALAR_LSB) <= dout_i;
EN_SYNC_GEN_ISCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_ISCALAR_STATUS_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => '0',
prmry_vect_in => status_iscalar_used_i(4*(i+1)-1 downto 4*i),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => open,
scndry_vect_out => status_iscalar_used(4*(i+1)-1 downto 4*i)
);
XD_ISCALAR_EMPTY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_ISCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => status_iscalar_empty_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => status_iscalar_empty(i),
scndry_vect_out => open
);
XD_ISCALAR_RDY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_ISCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => ap_iscalar_rdy_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => ap_iscalar_rdy(i),
scndry_vect_out => open
);
end generate EN_SYNC_GEN_ISCALAR;
NO_SYNC_GEN_ISCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_iscalar_empty(i) <= status_iscalar_empty_i(i);
ap_iscalar_rdy(i) <= ap_iscalar_rdy_i(i);
status_iscalar_used(4*(i+1)-1 downto 4*i) <= status_iscalar_used_i(4*(i+1)-1 downto 4*i);
end generate NO_SYNC_GEN_ISCALAR;
end generate ACTIVE_GEN;
INACTIVE_GEN : if (i > C_N_INPUT_SCALARS-1 and i < 8) generate
constant ISCALAR_DWIDTH : integer := get_int_element(C_INPUT_SCALAR_DWIDTH, i);
constant ISCALAR_LSB : integer := get_compact_LSB(C_INPUT_SCALAR_DWIDTH, i);
constant ISCALAR_MSB : integer := get_compact_MSB(C_INPUT_SCALAR_DWIDTH, i);
begin
--ap_iscalar_dout(ISCALAR_MSB downto ISCALAR_LSB) <= (others => '0');
status_iscalar_empty(i) <= '0';
status_iscalar_full(i) <= '0';
status_iscalar_used(4*(i+1)-1 downto 4*i) <= (others => '0');
-- A non used input scalar is always ready:
ap_iscalar_rdy(i) <= '1';
end generate INACTIVE_GEN;
--Pankaj
INOUT_ACTIVE_GEN : if (i > 7 and i < C_N_INOUT_SCALARS) generate
constant ISCALAR_DWIDTH : integer := get_int_element(C_INPUT_SCALAR_DWIDTH, i);
constant ISCALAR_LSB : integer := get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, i);
constant ISCALAR_MSB : integer := get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, i);
signal dout_i : std_logic_vector(ISCALAR_DWIDTH-1 downto 0);
signal empty : std_logic;
signal fifo_rst_reg : std_logic;
begin
-- fifo_rst <= ap_rst_s_axi_aclk or iscalar_rst(i);
process(clk, ap_rst_s_axi_aclk)
begin
if(ap_rst_s_axi_aclk = '1') then
fifo_rst_reg <= '1';
elsif(clk'event and clk = '1') then
fifo_rst_reg <= iscalar_rst(i);
end if;
end process;
-- Input scalars must show a behaviour equal to the input arguments in
-- the sense that written data by the processor must be inmediatelly
-- available for the accelerator. So a write-through FIFO is used.
FIFO_I : entity axis_accelerator_adapter_v2_1_6.xd_input_scalars_fifo
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
WIDTH => ISCALAR_DWIDTH)
port map (
din => iscalar_din(ISCALAR_DWIDTH-1 downto 0),
din_vld => iscalar_we(i),
din_rdy => open,
wr_used => status_iscalar_used_i(4*(i+1)-1 downto 4*i),
wr_empty => status_iscalar_empty_i(i),
wr_full => status_iscalar_full(i),
wr_clk => clk,
dout => dout_i,
dout_vld => ap_iscalar_rdy_i(i),
dout_rdy => ap_iscalar_done(i),
rd_clk => ap_clk,
rst => fifo_rst_reg);
ap_iscalar_dout(ISCALAR_MSB downto ISCALAR_LSB) <= dout_i;
EN_SYNC_GEN_ISCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_ISCALAR_STATUS_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => '0',
prmry_vect_in => status_iscalar_used_i(4*(i+1)-1 downto 4*i),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => open,
scndry_vect_out => status_iscalar_used(4*(i+1)-1 downto 4*i)
);
XD_ISCALAR_EMPTY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_ISCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => status_iscalar_empty_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => status_iscalar_empty(i),
scndry_vect_out => open
);
XD_ISCALAR_RDY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_ISCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => ap_iscalar_rdy_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => ap_iscalar_rdy(i),
scndry_vect_out => open
);
end generate EN_SYNC_GEN_ISCALAR;
NO_SYNC_GEN_ISCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_iscalar_empty(i) <= status_iscalar_empty_i(i);
ap_iscalar_rdy(i) <= ap_iscalar_rdy_i(i);
status_iscalar_used(4*(i+1)-1 downto 4*i) <= status_iscalar_used_i(4*(i+1)-1 downto 4*i);
end generate NO_SYNC_GEN_ISCALAR;
end generate INOUT_ACTIVE_GEN;
INOUT_INACTIVE_GEN : if (i > C_N_INOUT_SCALARS-1) generate
begin
status_iscalar_empty(i) <= '0';
status_iscalar_full(i) <= '0';
status_iscalar_used(4*(i+1)-1 downto 4*i) <= (others => '0');
-- A non used input scalar is always ready:
ap_iscalar_rdy(i) <= '1';
end generate INOUT_INACTIVE_GEN;
---
end generate INPUT_SCALARS_GEN;
NO_INPUT_SCALAR_GEN : if (C_N_INPUT_SCALARS = 0 and (C_N_INOUT_SCALARS-8) = 0) generate
begin
ap_iscalar_dout <= (others => '0');
end generate NO_INPUT_SCALAR_GEN;
end rtl;
|
mit
|
2dedfcb45dd30b163565b8fc9025df05
| 0.522091 | 3.786449 | false | false | false | false |
blutsvente/MIX
|
test/results/verilog/mixed/ent_t-rtl-a.vhd
| 1 | 5,688 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.6 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.6 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
-- Generated Generics for Entity ent_a
-- End of Generated Generics for Entity ent_a
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
d9122c32e210d09787ef2735cb1cb733
| 0.631505 | 2.80197 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue262.vhd
| 3 | 2,817 |
package textio is
type line is access string;
end package;
use work.textio.all;
package PKG is
procedure SCAN(
variable TEXT_LINE : inout LINE;
TEXT_END : in integer;
START_POS : in integer;
FOUND : out boolean;
FOUND_LEN : out integer
);
end package;
use work.textio.all;
package body PKG is
procedure SCAN(
variable TEXT_LINE : inout LINE;
TEXT_END : in integer;
START_POS : in integer;
FOUND : out boolean;
FOUND_LEN : out integer
) is
variable len : integer;
variable char : character;
begin
len := 1;
for pos in START_POS+1 to text_end loop
char := text_line(pos);
case char is
when NUL|SOH|STX|ETX|EOT|ENQ|ACK|BEL|
BS |HT |LF |VT |FF |CR |SO |SI |
DLE|DC1|DC2|DC3|DC4|NAK|SYN|ETB|
CAN|EM |SUB|ESC|FSP|GSP|RSP|USP|DEL =>
exit;
when '['|']'|'{'|'}'|',' =>
for prev_pos in pos-1 downto START_POS loop
exit when (text_line(prev_pos) /= ' ');
len := len - 1;
end loop;
exit;
when ':'=>
for prev_pos in pos-1 downto START_POS loop
exit when (text_line(prev_pos) /= ' ');
len := len - 1;
end loop;
exit;
when '#' =>
for prev_pos in pos-1 downto START_POS loop
exit when (text_line(prev_pos) /= ' ');
len := len - 1;
end loop;
exit;
when others => null;
end case;
len := len + 1;
end loop;
FOUND := TRUE;
FOUND_LEN := len;
end procedure;
end package body;
use work.textio.all;
library WORK;
use WORK.PKG.all;
entity issue262 is
end issue262;
architecture MODEL of issue262 is
begin
process
variable text_line : LINE;
variable text_end : integer;
variable found : boolean;
variable found_len : integer;
begin
--write(text_line, string'("{A:1}"));
text_line := new string'("{A:1}");
text_end := 4;
SCAN(text_line, text_end, 1, found, found_len);
report boolean'image(found);
report integer'image(found_len);
assert found;
assert found_len = 2;
wait;
end process;
end MODEL;
|
gpl-3.0
|
98698c929858cbb6401dc3964da6def0
| 0.433795 | 4.24247 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter8.vhd
| 1 | 4,152 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter8.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter8 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_counter8;
ARCHITECTURE SYN OF lpm_counter8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 8
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter8.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
61c55baa7a7dab7155e5025865c89fa2
| 0.651493 | 3.740541 | false | false | false | false |
blutsvente/MIX
|
test/results/intra/instance/ent_t-rtl-a.vhd
| 1 | 6,064 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Thu Oct 13 08:24:14 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.2 2006/01/19 09:18:58 wig Exp $
-- $Date: 2006/01/19 09:18:58 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.2 2006/01/19 09:18:58 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a
generic (
generic_15 : integer := 4660; -- Parameter for genericGeneric
);
port (
-- Generated Port for Entity ent_a
const_p_19 : in std_ulogic_vector(15 downto 0); -- Constant on inst_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
constant const_19_c : std_ulogic_vector(15 downto 0) := "0000110000011001"; -- __I_ConvConstant: 0xc19
signal const_19 : std_ulogic_vector(15 downto 0);
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
const_19 <= const_19_c;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
generic map (
generic_15 => 17185
)
port map (
const_p_19 => const_19, -- Constant on inst_a
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
bef4e1f08d2d9e7e2ae87f0daeaba390
| 0.629288 | 2.802218 | false | false | false | false |
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