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spoorcc/realtimestagram
|
src/lookup_table.vhd
| 2 | 3,913 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--! \class lookup_table
--! \brief returns a value from a pre generated lookup table
--!
--! \dot
--! digraph lookup_table{
--!
--! graph [rankdir=LR, splines=ortho, sep=5];
--! edge [penwidth=2.2, arrowsize=.5]
--! node [height=0.25, width=0.25, style=filled, fontname=sans]
--!
--! /* single or multibit registers */
--! subgraph registers{
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, headport=w, tailport=e]
--! clk rst enable pixel_i pixel_o
--! }
--!
--! subgraph cluster_0 {
--!
--! color=gray100;
--! label=lookup_table;
--! fontcolor=black;
--! fontname=sans;
--!
--! lut [label="lut", height=2, shape=box, fillcolor=gray96, fontcolor=black, tailport=e]
--! and0 [label="&", shape=circle, fillcolor=white, fontcolor=black, fixedsize=true]
--! }
--!
--! clk -> and0
--! enable -> and0
--! rst -> and0 [arrowhead=odot, arrowsize=0.6]
--! and0 -> lut
--! pixel_i -> lut -> pixel_o
--!
--!}
--! \enddot
--!
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.curves_pkg.all;
--============================================================================--
--!
--!
--!
--!
entity lookup_table is
generic (
wordsize: integer; --! input image wordsize in bits
lut: array_pixel --! pre generated lookup table
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_o: out std_logic_vector((wordsize-1) downto 0) --! the output pixel
);
end entity;
--============================================================================--
architecture behavioural of lookup_table is
-- signal declarations
signal lut_value_s: std_logic_vector((wordsize-1) downto 0);
begin
--! \brief clocked process that outputs LUT-value on each rising edge if enable is true
--! \param[in] clk clock
--! \param[in] rst asynchronous reset
curve_adjustment : process(clk, rst)
begin
if rst = '1' then
lut_value_s <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
lut_value_s <= lut(to_integer(unsigned(pixel_i)));
pixel_o <= lut_value_s;
else
pixel_o <= (others => '0');
end if; -- end if enable = '1'
end if; -- end if rst = '1'
end process;
end architecture;
--============================================================================--
|
gpl-2.0
|
b5ef2ba01120cd6c15449abd104aa390
| 0.495017 | 4.239437 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/pcu_tb.vhd
| 1 | 2,364 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity pcu_tb is
end pcu_tb;
architecture Behavior of pcu_tb is
constant I_clk_period : time := 10 ns;
signal I_clk, I_reset : std_logic := '0';
signal I_en: std_logic := '1';
signal I_op: pcuops_t;
signal I_data, O_data, O_trapret: std_logic_vector(XLEN-1 downto 0);
begin
-- instantiate unit under test
uut: entity work.pcu port map(
I_clk => I_clk,
I_en => I_en,
I_reset => I_reset,
I_op => I_op,
I_data => I_data,
O_data => O_data,
O_trapret => O_trapret
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- test setting the program counter
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
-- test entering and returning from a trap
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
I_data <= X"BEEFCAFE";
I_op <= PCU_ENTERTRAP;
wait until falling_edge(I_clk);
assert O_data = TRAP_VECTOR report "wrong value" severity failure;
I_op <= PCU_RETTRAP;
wait until falling_edge(I_clk);
assert O_data = X"BEEFCAFE" report "wrong value" severity failure;
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
assert O_trapret = X"BEEFCAFE" report "wrong value" severity failure;
-- test entering and returning from an interrupt
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
I_data <= X"BEEFCAFE";
I_op <= PCU_ENTERINT;
wait until falling_edge(I_clk);
assert O_data = INTERRUPT_VECTOR report "wrong value" severity failure;
I_op <= PCU_RETINT;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
cd3bb250a8c69e05b3b6c1e5049d6547
| 0.673435 | 2.886447 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/BancoDeRegistros.vhd
| 1 | 2,998 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:44:15 11/21/2012
-- Design Name:
-- Module Name: BancoDeRegistros - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BancoDeRegistros is
--generic( P: integer:=32; -- ancho de palabra
--N: integer:=32; -- nº de palabras
--tam_addr: integer:=5); -- ancho dirección
port( Clock: in std_logic;
Reg_Write: in std_logic;
RA: in std_logic_vector(4 downto 0);
RB: in std_logic_vector(4 downto 0);
RW: in std_logic_vector(4 downto 0);
busW: in std_logic_vector(31 downto 0);
busA: out std_logic_vector(31 downto 0);
busB: out std_logic_vector(31 downto 0)
);
end BancoDeRegistros;
architecture Behavioral of BancoDeRegistros is
type br_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal tmp: br_type:=(
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000111",
"00000000000000000000000000000001",
"00000000000000000000000000000110",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000001111");
begin
-- Lectura asíncrona
busA <= tmp(conv_integer(RA));
busB <= tmp(conv_integer(RB));
-- Escritura
process(Clock, Reg_Write)
begin
if (Clock'event and Clock='1') then
if Reg_Write='1' then
tmp(conv_integer(RW)) <= busW;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
8451e475c4e9c444fe57b09189803c74
| 0.716811 | 4.42836 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2/Hex4Digs_2_SSeg.vhd
| 1 | 3,014 |
--------------------------------------------------
-- Module Name: Hex4Digs_2_SSeg - behavioral --
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity Hex4Digs_2_SSeg is
Port ( clock : in std_logic; -- Input clock
inclk : in std_logic; -- Inc clock
sw0 : in std_logic; -- Switch to control clock
incr : in std_logic_vector (3 downto 0); -- Increment digits
anodes : out std_logic_vector (3 downto 0); -- Anodes for display
cathodes : out std_logic_vector (7 downto 0)); -- Cathodes for segments
end Hex4Digs_2_SSeg;
architecture behavioral of Hex4Digs_2_SSeg is
signal clk : std_logic;
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
constant TC1KHz : integer := 15; -- TC for 1 KHz clock
signal clk5Hz : std_logic := '0'; -- 5 Hz clock
signal clk1KHz : std_logic := '0'; -- 1 KHz clock
signal dsel : std_logic_vector (1 downto 0) := "00"; -- Display select
signal hx0, hx1, hx2, hx3 : std_logic_vector (3 downto 0) := "0000"; -- Hex digits
signal sg0, sg1, sg2, sg3 : std_logic_vector (7 downto 0) := "11111111"; -- Segments
begin
-- Get 1 KHz, 16 Hz, and 5 Hz clocks
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
c1KHz: CDiv port map (clock, TC1KHz, clk1KHz);
-- Get 4 Hex digits and assign their segments
dig0: Hex2SSeg port map (hx0, sg0);
dig1: Hex2SSeg port map (hx1, sg1);
dig2: Hex2SSeg port map (hx2, sg2);
dig3: Hex2SSeg port map (hx3, sg3);
process (sw0, clk1KHz, clk5Hz) -- control clocks
begin
if (sw0 = '0') then
clk <= clk1KHz;
else
clk <= clk5Hz;
end if;
end process;
process (inclk)
begin
if rising_edge(inclk) then
if (incr(0) = '1') then hx0 <= hx0 + 1; end if;
if (incr(1) = '1') then hx1 <= hx1 + 1; end if;
if (incr(2) = '1') then hx2 <= hx2 + 1; end if;
if (incr(3) = '1') then hx3 <= hx3 + 1; end if;
end if;
end process;
-- cathodes <= sg0 when dsel = "00" else
-- sg1 when dsel = "01" else
-- sg2 when dsel = "10" else
-- sg3;
process (clk) -- choose output display with dsel
begin
if rising_edge(clk) then
case dsel is
when "00" =>
cathodes <= sg3;
anodes <= "0111";
when "01" =>
cathodes <= sg2;
anodes <= "1011";
when "10" =>
cathodes <= sg1;
anodes <= "1101";
when others =>
cathodes <= sg0;
anodes <= "1110";
end case;
dsel <= dsel + 1;
end if;
end process;
end behavioral;
|
gpl-3.0
|
10965aa47d13d0fd7cb81d96444eb819
| 0.492701 | 3.592372 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AddSubNDemo.vhd
| 1 | 586 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AddSubNDemo is
port( SW : in std_logic_vector(17 downto 0);
KEY : in std_logic;
LEDR : out std_logic_vector(13 downto 0));
end AddSubNDemo;
architecture Shell of AddSubNDemo is
begin
AddSubNDemo: entity work.MultiAddSub(Structural)
port map(op0 => SW(3 downto 0),
op1 => SW(7 downto 4),
op2 => SW(12 downto 8),
op3 => SW(17 downto 13),
sub => KEY,
cout0=>LEDR(4),
cout1=>LEDR(13),
res0=>LEDR(3 downto 0),
res1=>LEDR(12 downto 8));
end Shell;
|
gpl-2.0
|
2a9d05b6930766b7643076ae8ada3253
| 0.629693 | 2.777251 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2/cntr_tb.vhd
| 1 | 2,776 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:43:14 02/20/2013
-- Design Name:
-- Module Name: /home/jmurray/Desktop/UTK/Spring2013/ECE351/HW/HW3-VDemo/cntr/cntr_tb.vhd
-- Project Name: cntr
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Hex4Digs_2_SSeg
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cntr_tb IS
END cntr_tb;
ARCHITECTURE behavior OF cntr_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Hex4Digs_2_SSeg
PORT(
clock : IN std_logic;
inclk : IN std_logic;
sw0 : IN std_logic;
incr : IN std_logic_vector(3 downto 0);
anodes : OUT std_logic_vector(3 downto 0);
cathodes : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal inclk : std_logic := '0';
signal sw0 : std_logic := '0';
signal incr : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal anodes : std_logic_vector(3 downto 0);
signal cathodes : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clock_period : time := 20 ns;
constant inclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Hex4Digs_2_SSeg PORT MAP (
clock => clock,
inclk => inclk,
sw0 => sw0,
incr => incr,
anodes => anodes,
cathodes => cathodes
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
inclk_process :process
begin
inclk <= '0';
wait for inclk_period/2;
inclk <= '1';
wait for inclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
1ecc960c149c07def85c4e0419994ca5
| 0.592939 | 3.813187 | false | true | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/control.vhd
| 1 | 7,931 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:03:44 11/22/2012
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
port(instruction: in std_logic_vector(5 downto 0);
estado: in ESTADOS;
sig_estado: out ESTADOS;
RegDst, RegWrite, MemWrite, MemRead, MemtoReg, PcWriteCond0, PcWriteCond1, PcWriteCond2,
ALUOp0, ALUOp1, ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, PcWrite:out std_logic);
end control;
architecture Behavioral of control is
begin
process(instruction, estado)
begin
if(estado = WB) then sig_estado <= F;
end if;
if(estado = F) then
RegDst <= '0';
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0';
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '1';
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '0';
ALUA <= '0';
ALUB1 <= '0';
ALUB0 <= '1';
PcSrc1 <= '0';
PcSrc0 <= '0';
sig_estado <= ID;
elsif(estado = ID) then
RegDst <= '0'; -- valor indeterminado, solo lee
RegWrite <= '0'; -- lee de registro
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0';
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '0';
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '0';
ALUA <= '0';
ALUB1 <= '1';
ALUB0 <= '1';
PcSrc1 <= '0';
PcSrc0 <= '0';
sig_estado <= EX;
else
-- tipo R
if instruction = "000000" then
RegDst <= '1';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0';
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '0';
ALUOp2 <= '0';
ALUOp1 <= '1';
ALUOp0 <= '0';
ALUA <= '1';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '0'; -- indeterminado
PcSrc0 <= '0'; -- indeterminado
if(estado = EX) then
sig_estado <= WB;
end if;
if(estado=WB) then
RegWrite <= '1';
else
RegWrite <= '0';
end if;
-- lw
elsif instruction = "100011" then
RegDst <= '0';
MemWrite <= '0';
MemRead <= '1';
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '0';
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '0';
ALUA <= '1';
ALUB1 <= '1';
ALUB0 <= '0';
PcSrc1 <= '0'; -- indeterminado
PcSrc0 <= '0'; -- indeterminado
if (estado = EX) then
sig_estado <= MEM;
RegWrite <= '0';
MemtoReg <= '0';
elsif (estado = MEM) then
sig_estado <= WB;
RegWrite <= '0';
MemtoReg <= '0';
else
MemtoReg <= '1';
RegWrite <= '1';
end if;
-- sw
elsif instruction = "101011" then
RegDst <= '0'; -- indeterminado
RegWrite <= '0';
MemRead <= '0';
MemtoReg <= '0'; -- indeterminado
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '0';
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '0';
ALUA <= '1';
ALUB1 <= '1';
ALUB0 <= '0';
PcSrc1 <= '0'; -- indeterminado
PcSrc0 <= '0'; -- indeterminado
if (estado = EX) then
sig_estado <= MEM;
MemWrite <= '0';
elsif (estado = MEM) then
sig_estado <= F;
MemWrite <= '1';
else
MemWrite <= '0';
end if;
-- beq
elsif instruction = "000100" then
RegDst <= '0'; -- indeterminado
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0'; -- indeterminado
PcWriteCond2 <= '1';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0'; -- bit de salto
PcWrite <= '0'; -- indeterminado
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '1';
ALUA <= '1';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '0';
PcSrc0 <= '1';
sig_estado <= F;
-- bne
elsif instruction = "000101" then
RegDst <= '0'; -- indeterminado
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0'; -- indeterminado
PcWriteCond2 <= '1';
PcWriteCond1 <= '0';
PCWriteCond0 <= '1'; -- bit de salto
PcWrite <= '0'; -- indeterminado
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '1';
ALUA <= '1';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '0';
PcSrc0 <= '1';
sig_estado <= F;
-- bgt
elsif instruction = "000110" then
RegDst <= '0'; -- indeterminado
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0'; -- indeterminado
PcWriteCond2 <= '1';
PcWriteCond1 <= '1';
PCWriteCond0 <= '0'; -- bit de salto
PcWrite <= '0'; -- indeterminado
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '1';
ALUA <= '1';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '0';
PcSrc0 <= '1';
sig_estado <= F;
-- blt
elsif instruction = "000111" then
RegDst <= '0'; -- indeterminado
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0'; -- indeterminado
PcWriteCond2 <= '1';
PcWriteCond1 <= '1';
PCWriteCond0 <= '1'; -- bit de salto
PcWrite <= '0'; -- indeterminado
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '1';
ALUA <= '1';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '0';
PcSrc0 <= '1';
sig_estado <= F;
-- jump
elsif instruction = "111111" then--inventado
RegDst <= '0'; -- indeterminado
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0'; -- indeterminado
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0'; -- bit de salto
PcWrite <= '1';
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '1';
ALUA <= '1';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '1';
PcSrc0 <= '1';
sig_estado <= F;
-- addi, subi, andi, ori
elsif (instruction="010000" or instruction="010001" or instruction="010010" or instruction="010011") then
RegDst <= '0';
RegWrite <= '1';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0';
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '0';
ALUA <= '1';
ALUB1 <= '1';
ALUB0 <= '0';
PcSrc1 <= '0'; -- indeterminado
PcSrc0 <= '0'; -- indeterminado
if(estado=WB) then
RegWrite <= '1';
else
RegWrite <= '0';
end if;
if instruction="010000" then -- addi
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '0';
elsif instruction="010001" then --subi
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '1';
elsif instruction="010010" then --andi
ALUOp2 <= '1';
ALUOp1 <= '0';
ALUOp0 <= '0';
else --ori
ALUOp2 <= '1';
ALUOp1 <= '0';
ALUOp0 <= '1';
end if;
if(estado = EX) then
sig_estado <= WB;
end if;
else
RegDst <= '0';
RegWrite <= '0';
MemWrite <= '0';
MemRead <= '0';
MemtoReg <= '0';
PcWriteCond2 <= '0';
PcWriteCond1 <= '0';
PCWriteCond0 <= '0';
PcWrite <= '0';
ALUOp2 <= '0';
ALUOp1 <= '0';
ALUOp0 <= '0';
ALUA <= '0';
ALUB1 <= '0';
ALUB0 <= '0';
PcSrc1 <= '0';
PcSrc0 <= '0';
sig_estado <= F;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
2dea32f9f7289ffafe8057fe92f90f06
| 0.491111 | 3.042194 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/MultiAddSub.vhd
| 1 | 775 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity MultiAddSub is
port( op0, op1 : in std_logic_vector(3 downto 0);
op2, op3 : in std_logic_vector(4 downto 0);
cout0, cout1:out std_logic;
res0 : out std_logic_vector(3 downto 0);
res1 : out std_logic_vector(4 downto 0);
sub : in std_logic);
end MultiAddSub;
architecture Structural of MultiAddSub is
begin
AddSub4: entity work.AddSubN(Behavioral)
generic map(n => 4)
port map(op0 => op0,
op1 => op1,
sub => sub,
cout=> cout0,
res => res0);
AddSub5: entity work.AddSubN(Behavioral)
generic map(n => 5)
port map(op0 => op2,
op1 => op3,
cout => cout1,
res => res1,
sub => sub);
end Structural;
|
gpl-2.0
|
fffab660b41047a679efb1de24231496
| 0.607742 | 2.748227 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AluNex5.vhd
| 1 | 923 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ALUN is
generic(N : natural := 8);
port( a, b : in std_logic_vector(N-1 downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector(N-1 downto 0);
r2 : out std_logic_vector(N-1 downto 0));
end ALUN;
architecture Behavioral of ALUN is
signal s_a, s_b, s_r : unsigned(N-1 downto 0);
signal s_m : unsigned((2*N)-1 downto 0);
begin
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= (s_a + s_b) when "000",
(s_a - s_b) when "001",
s_m(N-1 downto 0) when "010",
(s_a / s_b) when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m((2*N)-1 downto 4)) when (op = "010") else
(others => '0');
r2 <= r;
end Behavioral;
|
gpl-2.0
|
ab33a8bf669a2affdcd695caa4186b5c
| 0.562297 | 2.29602 | false | false | false | false |
vinodpa/openPowerlink-FPGA
|
Examples/ipcore/xilinx/openmac/src/ipif_master_handler.vhd
| 3 | 11,156 |
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ipif_master_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
m_burstcount_width_g : integer := 4
);
port(
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_byteenable : in std_logic_vector(3 downto 0);
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_writedata : in std_logic_vector(31 downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_readdata : out std_logic_vector(31 downto 0);
m_waitrequest : out std_logic := '1';
m_readdatavalid : out std_logic := '0';
m_clk : out std_logic
);
end ipif_master_handler;
architecture rtl of ipif_master_handler is
signal clk, rst : std_logic;
--signals for requesting transfers
signal m_write_s, m_read_s, m_wrd_en_n : std_logic;
signal m_write_l, m_read_l : std_logic;
signal m_write_rise, m_read_rise : std_logic;
signal m_write_fall, m_read_fall : std_logic;
signal mst_write_req, mst_write_req_next : std_logic;
signal mst_read_req, mst_read_req_next : std_logic;
--what if master wants to req new transfer, but previous is not yet completed (= no Mst_Cmplt pulse!!!)
signal mst_done : std_logic;
--signals for the transfer
type tran_t is (idle, sof, tran, eof, seof, wait4cmplt); --seof = start/end of frame (single beat)
signal wr_tran, wr_tran_next : tran_t;
signal rd_tran : tran_t;
--avoid preset of FFs
signal MAC_DMA2Bus_MstRd_dst_rdy : std_logic;
begin
--some assignments..
m_clk <= MAC_DMA_CLK;
clk <= MAC_DMA_CLK;
rst <= MAC_DMA_Rst;
mst_done <= Bus2MAC_DMA_Mst_Cmplt;
m_write_s <= m_write and not m_wrd_en_n; --NOTE: write/read enable is low-active!
m_read_s <= m_read and not m_wrd_en_n; --NOTE: write/read enable is low-active!
--reserved
MAC_DMA2Bus_Mst_Lock <= '0';
MAC_DMA2Bus_Mst_Reset <= '0';
--delay some signals..
del_proc : process(clk, rst)
begin
if rst = '1' then
m_write_l <= '0'; m_read_l <= '0';
m_wrd_en_n <= '0'; --is low-active to avoid preset of FF
elsif rising_edge(clk) then
m_write_l <= m_write_s; m_read_l <= m_read_s;
if mst_done = '1' then
m_wrd_en_n <= '0';
elsif m_write_fall = '1' or m_read_fall = '1' then
m_wrd_en_n <= '1'; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
m_write_rise <= '1' when m_write_l = '0' and m_write_s = '1' else '0';
m_read_rise <= '1' when m_read_l = '0' and m_read_s = '1' else '0';
m_write_fall <= '1' when m_write_l = '1' and m_write_s = '0' else '0';
m_read_fall <= '1' when m_read_l = '1' and m_read_s = '0' else '0';
--generate req qualifiers
req_proc : process(clk, rst)
begin
if rst = '1' then
mst_write_req <= '0'; mst_read_req <= '0';
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
elsif rising_edge(clk) then
mst_write_req <= mst_write_req_next; mst_read_req <= mst_read_req_next;
if m_read_s = '1' then
MAC_DMA2Bus_MstRd_dst_rdy <= '1';
elsif rd_tran = eof and Bus2MAC_DMA_MstRd_src_rdy_n = '0' then
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
end if;
end if;
end process;
MAC_DMA2Bus_MstRd_dst_rdy_n <= not MAC_DMA2Bus_MstRd_dst_rdy;
mst_write_req_next <= '0' when mst_write_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_write_req = '0' and m_write_rise = '1' else
mst_write_req;
mst_read_req_next <= '0' when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_read_req = '0' and m_read_rise = '1' else
mst_read_req;
MAC_DMA2Bus_MstRd_Req <= mst_read_req;
MAC_DMA2Bus_MstWr_Req <= mst_write_req;
MAC_DMA2Bus_Mst_Type <= '0' when m_burstcount < 2 else --single beat
mst_read_req or mst_write_req; --we are talking about bursts..
--assign address, byteenable and burst size
comb_addrZeroPad : process(m_address)
begin
for i in MAC_DMA2Bus_Mst_Addr'range loop
if i <= m_address'high then
MAC_DMA2Bus_Mst_Addr(i) <= m_address(i);
else
MAC_DMA2Bus_Mst_Addr(i) <= '0'; --zero padding
end if;
end loop;
end process;
--MAC_DMA2Bus_Mst_Addr <= m_address;
MAC_DMA2Bus_Mst_BE <= "1111";
MAC_DMA2Bus_Mst_Length <= conv_std_logic_vector(conv_integer(m_burstcount),
MAC_DMA2Bus_Mst_Length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(clk, rst)
begin
if rst = '1' then
wr_tran <= idle;
elsif rising_edge(clk) then
wr_tran <= wr_tran_next;
end if;
end process;
--generate fsm for write and read transfers
wr_tran_next <=
seof when wr_tran = idle and mst_write_req_next = '1' and (m_burstcount <= 1 or m_burstcount'length = 1) else
sof when wr_tran = idle and mst_write_req_next = '1' and m_burstcount'length > 1 else
eof when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount = 2 and m_burstcount'length > 1 else
tran when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
eof when wr_tran = tran and m_burstcounter <= 2 and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
wait4cmplt when (wr_tran = eof or wr_tran = seof) and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
idle when wr_tran = wait4cmplt and mst_done = '1' else
wr_tran;
rd_tran <=
seof when Bus2MAC_DMA_MstRd_sof_n = '0' and Bus2MAC_DMA_MstRd_eof_n = '0' else
sof when Bus2MAC_DMA_MstRd_sof_n = '0' else
eof when Bus2MAC_DMA_MstRd_eof_n = '0' else
tran when Bus2MAC_DMA_MstRd_src_rdy_n = '0' else
idle;
--set write qualifiers
MAC_DMA2Bus_MstWr_sof_n <= '0' when wr_tran = sof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_eof_n <= '0' when wr_tran = eof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_src_rdy_n <= '0' when wr_tran /= idle and wr_tran /= wait4cmplt else '1';
MAC_DMA2Bus_MstWr_src_dsc_n <= '1'; --no support
MAC_DMA2Bus_MstWr_rem <= (others => '0'); --no support
--set read qualifiers
MAC_DMA2Bus_MstRd_dst_dsc_n <= '1'; --no support
--connect ipif with avalon
m_waitrequest <= --waitrequest if not ready or no write active
not m_write when Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
not m_read when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else '1';
m_readdatavalid <= not Bus2MAC_DMA_MstRd_src_rdy_n;
MAC_DMA2Bus_MstWr_d <= m_writedata;
m_readdata <= Bus2MAC_DMA_MstRd_d;
end rtl;
|
gpl-2.0
|
60f5d8073c80f6bac92f6a4351f28f90
| 0.595823 | 3.193816 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/mouse_displayer.vhd
| 1 | 14,317 |
------------------------------------------------------------------------
-- mouse_displayer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the implementation of a mouse cursor.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Mouse position is received from the mouse_controller, horizontal and
-- vertical counters are received from vga_module and if the counters
-- are inside the mouse cursor bounds, then the mouse is sent to the
-- screen instead of the received pixels. The mouse cursor is 16x16
-- pixels and used 2 colors: white and black. For the color encoding
-- 2 bits are used to be able to use transparency. The cursor is stored
-- in a distributed ram memory 256x2bits in dimension. If the current
-- pixel of the mouse is "00" then output color is black, if "01" then
-- white and if "10" or "11" then the pixel is perfectly transparent
-- and the input colors are output. This way, the mouse will not be a
-- 16x16 square and will have an arrow shape.
-- Memory address is composed from the difference of the vga counters
-- and mouse position. xdiff is the difference on 4 bits (because cursor
-- is 16 pixels width) between the horizontal vga counter and the xpos
-- of the mouse. ydiff is the difference on 4 bits (because cursor
-- has 16 pixels in height) between the vertical vga counter and the
-- ypos of the mouse. By concatenating ydiff and xidff (in this order)
-- the memory address of the current pixel is obtained.
-- Distributed memory is forced by the attributes, because the block
-- rams are entirely used for storing images.
-- If blank input from the vga_module is active, this means that current
-- pixel is not inside visible screen and color outputs are set to black
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal (100MHz)
-- pixel_clk - input pin, from pixel_clock_switcher, the clock used
-- - by the vga_controller for the currently used
-- - resolution, generated by a dcm. 25MHz for 640x480
-- - and 40MHz for 800x600. This clock is used to read
-- - pixels from memory and output data on color outputs.
-- xpos - input pin, 10 bits, from mouse_controller
-- - the x position of the mouse relative to the upper
-- - left corner
-- ypos - input pin, 10 bits, from mouse_controller
-- - the y position of the mouse relative to the upper
-- - left corner
-- hcount - input pin, 11 bits, from vga_module
-- - the horizontal counter from the vga_controller
-- - tells the horizontal position of the current pixel
-- - on the screen from left to right.
-- vcount - input pin, 11 bits, from vga_module
-- - the vertical counter from the vga_controller
-- - tells the vertical position of the currentl pixel
-- - on the screen from top to bottom.
-- blank - input pin, from vga_module
-- - if active, current pixel is not in visible area,
-- - and color outputs should be set on 0.
-- red_in - input pin, 4 bits, from effects_layer
-- - red channel input of the image to be displayed
-- green_in - input pin, 4 bits, from effects_layer
-- - green channel input of the image to be displayed
-- blue_in - input pin, 4 bits, from effects_layer
-- - blue channel input of the image to be displayed
-- red_out - output pin, 4 bits, to vga hardware module.
-- - red output channel
-- green_out - output pin, 4 bits, to vga hardware module.
-- - green output channel
-- blue_out - output pin, 4 bits, to vga hardware module.
-- - blue output channel
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- simulation library
library unisim;
use unisim.vcomponents.all;
-- the mouse_displayer entity declaration
-- read above for behavioral description and port definitions.
entity mouse_displayer is
port (
clk : in std_logic;
pixel_clk: in std_logic;
xpos : in std_logic_vector(9 downto 0);
ypos : in std_logic_vector(9 downto 0);
hcount : in std_logic_vector(10 downto 0);
vcount : in std_logic_vector(10 downto 0);
blank : in std_logic;
click : in std_logic;
red_in : in std_logic_vector(2 downto 0);
green_in : in std_logic_vector(2 downto 0);
blue_in : in std_logic_vector(2 downto 1);
red_out : out std_logic_vector(2 downto 0);
green_out: out std_logic_vector(2 downto 0);
blue_out : out std_logic_vector(2 downto 1)
);
-- force synthesizer to extract distributed ram for the
-- displayrom signal, and not a block ram, because the block ram
-- is entirely used to store the image.
attribute rom_extract : string;
attribute rom_extract of mouse_displayer: entity is "yes";
attribute rom_style : string;
attribute rom_style of mouse_displayer: entity is "distributed";
end mouse_displayer;
architecture Behavioral of mouse_displayer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
type displayrom is array(0 to 255) of std_logic_vector(1 downto 0);
-- the memory that holds the cursor.
-- 00 - black
-- 01 - white
-- 1x - transparent
constant mouserom: displayrom := (
"00","00","11","11","11","11","11","11","11","11","11","11","11","11","11","11",
"00","01","00","11","11","11","11","11","11","11","11","11","11","11","11","11",
"00","01","01","00","11","11","11","11","11","11","11","11","11","11","11","11",
"00","01","01","01","00","11","11","11","11","11","11","11","11","11","11","11",
"00","01","01","01","01","00","11","11","11","11","11","11","11","11","11","11",
"00","01","01","01","01","01","00","11","11","11","11","11","11","11","11","11",
"00","01","01","01","01","01","01","00","11","11","11","11","11","11","11","11",
"00","01","01","01","01","01","01","01","00","11","11","11","11","11","11","11",
"00","01","01","01","01","01","00","00","00","00","11","11","11","11","11","11",
"00","01","01","01","01","01","00","11","11","11","11","11","11","11","11","11",
"00","01","00","00","01","01","00","11","11","11","11","11","11","11","11","11",
"00","00","11","11","00","01","01","00","11","11","11","11","11","11","11","11",
"00","11","11","11","00","01","01","00","11","11","11","11","11","11","11","11",
"11","11","11","11","11","00","01","01","00","11","11","11","11","11","11","11",
"11","11","11","11","11","00","01","01","00","11","11","11","11","11","11","11",
"11","11","11","11","11","11","00","00","11","11","11","11","11","11","11","11"
);
constant clickrom: displayrom := (
"00","00","00","00","11","11","11","11","11","11","11","11","00","00","00","00",
"00","01","01","01","00","11","11","11","11","11","11","00","01","01","01","00",
"00","01","01","01","01","00","11","11","11","11","00","01","01","01","01","00",
"00","01","01","01","01","01","00","11","11","00","01","01","01","01","01","00",
"11","00","01","01","01","01","01","00","00","01","01","01","01","01","00","11",
"11","11","00","01","01","01","01","01","01","01","01","01","01","00","11","11",
"11","11","11","00","01","01","01","01","01","01","01","01","00","11","11","11",
"11","11","11","11","00","01","01","01","01","01","01","00","11","11","11","11",
"11","11","11","11","00","01","01","01","01","01","01","00","11","11","11","11",
"11","11","11","00","01","01","01","01","01","01","01","01","00","11","11","11",
"11","11","00","01","01","01","01","01","01","01","01","01","01","00","11","11",
"11","00","01","01","01","01","01","00","00","01","01","01","01","01","00","11",
"00","01","01","01","01","01","00","11","11","00","01","01","01","01","01","00",
"00","01","01","01","01","00","11","11","11","11","00","01","01","01","01","00",
"00","01","01","01","00","11","11","11","11","11","11","00","01","01","01","00",
"00","00","00","00","11","11","11","11","11","11","11","11","00","00","00","00"
);
-- width and height of cursor.
constant OFFSET: std_logic_vector(4 downto 0) := "10000"; -- 16
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- pixel from the display memory, representing currently displayed
-- pixel of the cursor, if the cursor is being display at this point
signal mousepixel: std_logic_vector(1 downto 0) := (others => '0');
signal clickpixel: std_logic_vector(1 downto 0) := (others => '0');
-- when high, enables displaying of the cursor, and reading the
-- cursor memory.
signal enable_mouse_display: std_logic := '0';
-- difference in range 0-15 between the vga counters and mouse position
signal xdiff: std_logic_vector(3 downto 0) := (others => '0');
signal ydiff: std_logic_vector(3 downto 0) := (others => '0');
begin
-- compute xdiff
x_diff: process(clk)
variable temp_diff: std_logic_vector(10 downto 0) := (others => '0');
begin
if rising_edge(clk) then
temp_diff := hcount - ('0' & xpos);
xdiff <= temp_diff(3 downto 0);
end if;
end process x_diff;
-- compute ydiff
y_diff: process(clk)
variable temp_diff: std_logic_vector(10 downto 0) := (others => '0');
begin
if rising_edge(clk) then
temp_diff := vcount - ('0' & ypos);
ydiff <= temp_diff(3 downto 0);
end if;
end process y_diff;
-- read pixel from memory at address obtained by concatenation of
-- ydiff and xdiff
mousepixel <= mouserom(conv_integer(ydiff & xdiff)) when rising_edge(pixel_clk);
clickpixel <= clickrom(conv_integer(ydiff & xdiff)) when rising_edge(pixel_clk);
-- set enable_mouse_display high if vga counters inside cursor block
enable_mouse: process(pixel_clk)
begin
if rising_edge(pixel_clk) then
if(hcount >= xpos and hcount < (xpos + OFFSET) and
vcount >= ypos and vcount < (ypos + OFFSET))
then
enable_mouse_display <= '1';
else
enable_mouse_display <= '0';
end if;
end if;
end process enable_mouse;
-- if cursor display is enabled, then, according to pixel
-- value, set the output color channels.
process(pixel_clk)
begin
if rising_edge(pixel_clk) then
-- if in visible screen
if blank = '0' then
-- in display is enabled
if enable_mouse_display = '1' then
if click = '1' then
-- white pixel of click
if(clickpixel = "01") then
red_out <= (others => '1');
green_out <= (others => '1');
blue_out <= (others => '1');
-- black pixel of click
elsif clickpixel = "00" then
red_out <= (others => '0');
green_out <= (others => '0');
blue_out <= (others => '0');
-- transparent pixel of click
-- let input pass to output
else
red_out <= red_in;
green_out <= green_in;
blue_out <= blue_in;
end if;
else
-- white pixel of cursor
if(mousepixel = "01") then
red_out <= (others => '1');
green_out <= (others => '1');
blue_out <= (others => '1');
-- black pixel of cursor
elsif mousepixel = "00" then
red_out <= (others => '0');
green_out <= (others => '0');
blue_out <= (others => '0');
-- transparent pixel of cursor
-- let input pass to output
else
red_out <= red_in;
green_out <= green_in;
blue_out <= blue_in;
end if;
end if;
-- cursor display is not enabled
-- let input pass to output.
else
red_out <= red_in;
green_out <= green_in;
blue_out <= blue_in;
end if;
-- not in visible screen, black outputs.
else
red_out <= (others => '0');
green_out <= (others => '0');
blue_out <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
ed61b64159eb1593f712d0f70b11e255
| 0.477474 | 3.950607 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/spi/spiromram_wb8.vhd
| 1 | 4,621 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spiromram_wb8 is
generic(
ADDRLEN: integer := 12
);
port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_I: in std_logic_vector(7 downto 0);
RST_I: in std_logic;
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- SPI signal lines
I_spi_miso: in std_logic := '0';
O_spi_sel: out std_logic := '1';
O_spi_clk: out std_logic := '0';
O_spi_mosi: out std_logic := '0'
);
end spiromram_wb8;
architecture Behavioral of spiromram_wb8 is
type store_t is array(0 to (2**ADDRLEN)-1) of std_logic_vector(7 downto 0);
signal ram: store_t := (others => X"00");
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
signal tx_data, rx_data: std_logic_vector(7 downto 0) := X"00";
signal tx_start: boolean := false;
signal spi_busy: boolean := true;
begin
spimaster_instance: entity work.spimaster port map(
I_clk => CLK_I,
I_tx_data => tx_data,
I_tx_start => tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => rx_data,
O_busy => spi_busy
);
process(CLK_I)
type ctrlstates is (RESET, FILLRAM1, FILLRAM2, IDLE, READ1, READ2, READ3, READ4, READ5, READ6, READ7, TX1, TX2);
variable state, retstate: ctrlstates := RESET;
variable ack: std_logic := '0';
variable addr: std_logic_vector(23 downto 0) := X"000000";
variable init: std_logic := '1';
variable initaddr: std_logic_vector(ADDRLEN-1 downto 0);
begin
if rising_edge(CLK_I) then
ack := '0';
O_spi_sel <= '0'; -- select device
if RST_I = '1' then
state := RESET;
end if;
case state is
when RESET =>
O_spi_sel <= '1'; -- deselect device
init := '1';
initaddr := (others => '0');
state := FILLRAM1;
when FILLRAM1 =>
addr := (others => '0');
addr(ADDRLEN-1 downto 0) := initaddr;
state := READ1;
when FILLRAM2 =>
O_spi_sel <= '1'; -- deselect device
ram(to_integer(unsigned(initaddr))) <= rx_data;
-- increase address counter
initaddr := std_logic_vector((unsigned(initaddr) + 1));
if unsigned(initaddr) = 0 then
-- init address wrapped back to zero, we're finished
init := '0';
state := IDLE;
else
-- fetch next byte to initialize RAM
state := FILLRAM1;
end if;
when IDLE =>
O_spi_sel <= '1'; -- deselect device
if ADR_I(24) = '0' then
---------------
-- access RAM
---------------
if STB_I = '1' then
if(WE_I = '1') then
ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0)))) <= DAT_I;
else
DAT_O <= ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0))));
end if;
ack := '1';
end if;
else
--------------
-- access ROM
--------------
if not spi_busy and STB_I = '1' then
addr := ADR_I(23 downto 0);
state := READ1;
end if;
end if;
when READ1 =>
-- start reading SPI ROM by submitting the READ opcode
tx_data <= X"03";
state := TX1;
retstate := READ2;
when READ2 =>
-- transmit first part of the address
tx_data <= addr(23 downto 16);
state := TX1;
retstate := READ3;
when READ3 =>
-- transmit second part of the address
tx_data <= addr(15 downto 8);
state := TX1;
retstate := READ4;
when READ4 =>
-- transmit third part of the address
tx_data <= addr(7 downto 0);
state := TX1;
retstate := READ5;
when READ5 =>
-- read byte from SPI ROM (transmitted data doesn't matter)
tx_data <= X"00";
state := TX1;
retstate := READ6;
when READ6 =>
-- output read data and ACK
ack := '1';
DAT_O <= rx_data;
state := READ7;
when READ7 =>
if init = '0' then
state := IDLE;
else
state := FILLRAM2;
end if;
when TX1 =>
-- signal beginning of transmission
tx_start <= true;
-- wait for ack that transmission is in progress
if spi_busy then
state := TX2;
end if;
when TX2 =>
tx_start <= false;
-- wait until transmission has ended
if not spi_busy then
state := retstate;
end if;
end case;
end if;
ACK_O <= ack and STB_I and (not init);
end process;
end Behavioral;
|
mit
|
113b984c4c203fbe20c0fc0a6c0a0b5d
| 0.560485 | 3.05218 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 1/fase1.vhd
| 1 | 1,082 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity fase1 is
port( KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(0 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0));
end fase1;
architecture Structural of fase1 is
signal s_binOut : unsigned(6 downto 0);
signal decOut_1, decOut_2 : std_logic_vector(3 downto 0);
begin
cliente_seguinte_core: entity work.cliente_seguinte(Behavioral)
port map(clienseg => KEY(0),
reset => SW(0),
unsigned(binOut) => s_binOut);
Bin2BCD_core: entity work.Bin2BCDDecoder(Behavioral)
port map(inBin => std_logic_vector(s_binOut),
outBCD => decOut_1,
outBCD2 => decOut_2);
Bin7Seg_core1: entity work.bin7Seg(Behavioral)
port map( binInput => decOut_1,
decOut_n => HEX7);
Bin7Seg_core2: entity work.bin7Seg(Behavioral)
port map( binInput => decOut_2,
decOut_n => HEX6);
end Structural;
|
gpl-2.0
|
5a1dc48eb76371413c742ee49d8fa477
| 0.609982 | 3.005556 | false | false | false | false |
spoorcc/realtimestagram
|
src/sepia.vhd
| 2 | 7,590 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--! \class sepia
--! \brief Creates a sepia image
--!
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--============================================================================--
--!
--!
--!
--!
entity sepia is
generic (
wordsize: integer; --! input image wordsize in bits
image_width: integer; --! width of input image
image_height: integer --! height of input image
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_red_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
threshold: in std_logic_vector((wordsize-1) downto 0); --! Amount of sepia effect
pixel_red_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_o: out std_logic_vector((wordsize-1) downto 0) --! the input pixel
);
end entity;
--============================================================================--
architecture behavioural of sepia is
constant max_value : integer := 2**wordsize - 1;
signal red_0 : integer range 0 to max_value;
signal green_0 : integer range 0 to max_value;
signal blue_0 : integer range 0 to max_value;
signal r_g_max : integer range 0 to max_value;
signal b_delay : integer range 0 to max_value;
signal intensity : integer range 0 to max_value;
signal th_delay_d0 : integer range 0 to max_value;
signal th_delay_d1 : integer range 0 to max_value;
signal th_diff_6 : integer range 0 to max_value/6;
signal th_d6_delay : integer range 0 to max_value/6;
signal th_d6_times7 : integer range 0 to (max_value/6)*7;
signal max_min_th : integer range 0 to max_value;
signal tone : integer range 0 to max_value / 7;
signal red_o_int : integer range 0 to max_value;
signal green_o_int : integer range 0 to max_value;
signal blue_o_int : integer range 0 to max_value;
begin
sepia_process : process(clk, rst)
variable red_i_int : integer range 0 to max_value := 0;
variable green_i_int : integer range 0 to max_value := 0;
variable blue_i_int : integer range 0 to max_value := 0;
variable threshold_i_int : integer range 0 to max_value := 0;
variable red_o_int_d0 : integer range 0 to max_value := 0;
variable green_o_int_d0 : integer range 0 to max_value := 0;
variable blue_o_int_d0 : integer range 0 to max_value := 0;
begin
if rst = '1' then
pixel_red_o <= (others => '0');
pixel_green_o <= (others => '0');
pixel_blue_o <= (others => '0');
r_g_max <= 0;
b_delay <= 0;
intensity <= 0;
th_delay_d0 <= 0;
th_delay_d1 <= 0;
th_diff_6 <= 0;
th_d6_delay <= 0;
th_d6_times7 <= 0;
max_min_th <= 0;
tone <= 0;
red_o_int <= 0;
green_o_int <= 0;
blue_o_int <= 0;
red_o_int_d0 := 0;
green_o_int_d0 := 0;
blue_o_int_d0 := 0;
elsif rising_edge(clk) then
if enable = '1' then
red_i_int := to_integer(unsigned(pixel_red_i));
green_i_int := to_integer(unsigned(pixel_green_i));
blue_i_int := to_integer(unsigned(pixel_blue_i));
-- Convert to gray, by finding largest value
if red_i_int >= green_i_int then
r_g_max <= red_i_int;
else
r_g_max <= green_i_int;
end if;
b_delay <= blue_i_int;
if r_g_max >= b_delay then
intensity <= r_g_max;
else
intensity <= b_delay;
end if;
-- Calculate threshold
threshold_i_int := to_integer(unsigned(threshold));
th_diff_6 <= threshold_i_int / 6;
th_d6_delay <= th_diff_6;
th_d6_times7 <= th_diff_6 * 7;
th_delay_d0 <= threshold_i_int;
th_delay_d1 <= th_delay_d0;
max_min_th <= max_value - th_delay_d0;
-- Calculate red pixel
if intensity > th_delay_d1 then
red_o_int <= max_value;
else
red_o_int <= intensity + max_min_th;
end if;
-- Calculate green pixel
if intensity > th_d6_times7 then
green_o_int <= max_value;
else
green_o_int <= intensity + max_value - th_d6_times7;
end if;
-- Calculate blue pixel
if intensity < th_d6_delay then
blue_o_int <= 0;
else
blue_o_int <= intensity - th_d6_delay;
end if;
-- Check ranges
tone <= th_delay_d1 / 7;
red_o_int_d0 := red_o_int;
if green_o_int < tone then
green_o_int_d0 := tone;
else
green_o_int_d0 := green_o_int;
end if;
if blue_o_int < tone then
blue_o_int_d0 := tone;
else
blue_o_int_d0 := blue_o_int;
end if;
pixel_red_o <= std_logic_vector(to_unsigned(red_o_int_d0, wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(green_o_int_d0, wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(blue_o_int_d0, wordsize));
else
pixel_red_o <= (others => '0');
pixel_green_o <= (others => '0');
pixel_blue_o <= (others => '0');
end if; -- end if enable = '1'
end if; -- end if rst = '1'
end process;
end architecture;
--============================================================================--
|
gpl-2.0
|
b56ca12eb2ba9ab13619e7673c0c7598
| 0.476285 | 4.007392 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 9/Parte II/Ram1_Demo.vhd
| 1 | 524 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram1_Demo is
port( SW : in std_logic_vector(12 downto 0);
KEY: in std_logic_vector(0 downto 0);
LEDG: out std_logic_vector(7 downto 0));
end Ram1_Demo;
architecture Behavioral of Ram1_Demo is
begin
ram_16_8: entity work.Ram_16_8(Behavioral)
port map(clk => KEY(0),
writeEnable => SW(0),
address => SW(4 downto 1),
writeData => SW(12 downto 5),
readData => LEDG(7 downto 0));
end Behavioral;
|
gpl-2.0
|
14607918ac7bcc4eca802b7ea5f5f879
| 0.641221 | 2.895028 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 7/Parte 2(TPC)/DrinksFSM.vhd
| 1 | 2,541 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity DrinksFSM is
port( C : in std_logic;
V : in std_logic;
reset : in std_logic;
clk : in std_logic;
drink : out std_logic;
m_money : out std_logic_vector(3 downto 0);
c_money : out std_logic_vector(3 downto 0));
end DrinksFSM;
architecture Behavioral of DrinksFSM is
type Tstate is (S0,S1,S2,S3,S4,S5, S6, S7, S8, S9, S10, S11);
signal pState, nState : Tstate;
signal sm_money : unsigned(3 downto 0);
signal sc_money : unsigned(3 downto 0);
signal s_reset : std_logic;
begin
m_money <= std_logic_vector(sm_money);
c_money <= std_logic_vector(sc_money);
clk_proc: process(clk, reset)
begin
if(reset = '1') then
pState <= S0;
elsif(rising_edge(clk)) then
pState <= nState;
end if;
end process;
comb_process: process(pState, C, V)
begin
drink <= '0';
sc_money <= "0000";
case pState is
when S0 =>
sm_money <= "0000";
if(C='1') then
nState <= S6;
elsif(V='1') then
nState <= S1;
else
nState <= S0;
end if;
when S1 =>
sm_money <= "0010";
if(C='1') then
nState <= S7;
elsif(V='1') then
nState <= S2;
else
nState <= S1;
end if;
when S2 =>
sm_money <= "0100";
if(C='1') then
nState <= S8;
elsif(V='1') then
nState <= S3;
else
nState <= S2;
end if;
when S3 =>
sm_money <= "0110";
if(C='1') then
nState <= S10;
elsif(V='1') then
nState <= S4;
else
nState <= S3;
end if;
when S4 =>
sm_money <= "1000";
if(C='1') then
nState <= S11;
elsif(V='1') then
nState <= S5;
else
nState <= S4;
end if;
when S5 =>
sm_money <= "0000";
sc_money <= "0001";
nState <= S5;
drink <= '1';
when S6 =>
sm_money <= "0101";
if(C='1') then
nState <= S5;
elsif(V='1') then
nState <= S7;
else
nState <= S6;
end if;
when S7 =>
sm_money <= "0111";
if(C='1') then
nState <= S9;
elsif(V='1') then
nState <= S8;
else
nState <= S7;
end if;
when S8 =>
sm_money <= "1001";
nState <= S8;
drink <= '1';
when S9 =>
sm_money <= "0010";
sc_money <= "0001";
nState <= S9;
drink <= '1';
when S10=>
sm_money <= "0001";
sc_money <= "0001";
nState <= S10;
drink <= '1';
when S11=>
sm_money <= "0010";
sc_money <= "0001";
nState <= S11;
drink <= '1';
end case;
end process;
end Behavioral;
|
gpl-2.0
|
b531e0a9f13a1bbed59f62e3d95d80e0
| 0.520268 | 2.525845 | false | false | false | false |
miree/vhdl_cores
|
tdc/fifo.vhd
| 1 | 1,986 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
depth : integer;
bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
push_i, pop_i : in std_logic;
full_o, empty_o : out std_logic;
d_i : in std_logic_vector ( bit_width-1 downto 0 );
q_o : out std_logic_vector ( bit_width-1 downto 0 )
);
end entity;
architecture rtl of fifo is
-- calculate the number of words from
-- the depth (which is like the address width)
constant number_of_words : integer := 2**depth;
-- define data type of the storage array
type fifo_data_array is array ( 0 to number_of_words-1)
of std_logic_vector ( bit_width-1 downto 0);
-- define the storage array
signal fifo_data : fifo_data_array;
-- read and write index pointers
-- give them one bit more then needed to quickly check for overflow
-- by looking at the most significant bit (tip from Matthias Kreider)
signal w_idx : unsigned ( depth downto 0 );
signal r_idx : unsigned ( depth downto 0 );
begin
main: process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then -- reset is active high
-- force reset state
w_idx <= (others => '0');
r_idx <= (others => '0');
else
-- normal operation:
-- writing
if push_i = '1' then
fifo_data(to_integer(w_idx(depth-1 downto 0))) <= d_i;
w_idx <= w_idx + 1;
end if;
-- reading
if pop_i = '1' then
r_idx <= r_idx + 1;
end if;
end if;
end if;
end process;
q_o <= fifo_data(to_integer(r_idx(depth-1 downto 0)));
full_o <= r_idx(depth) xor w_idx(depth) when (r_idx(depth-1 downto 0) = w_idx(depth-1 downto 0)) else '0';
empty_o <= not (r_idx(depth) xor w_idx(depth)) when (r_idx(depth-1 downto 0) = w_idx(depth-1 downto 0)) else '0';
end architecture;
|
mit
|
c601ad40434d3b4f9903b928c30b2279
| 0.577543 | 3.261084 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/DoubleFifo.vhd
| 2 | 7,973 |
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
end if;
end process;
p_mux2_data : process(RST)
begin
if CLK'event and CLK = '1' then
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
p_mux3_data : process(CLK)
begin
if CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
else
data_out <= fifo2_q;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
a9ace65a53e75c6343fd06d83c4d980c
| 0.360717 | 5.420122 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 6/Parte 4/SeqShiftUnitTb.vhd
| 1 | 1,276 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqShiftUnitTb is
end SeqShiftUnitTb;
architecture Stimulus of SeqShiftUnitTb is
signal s_clk, s_siLeft, s_siRight, s_loadEn, s_rotate, s_dirLeft, s_shArith : std_logic;
signal s_dataIn, s_dataOut : std_logic_vector(7 downto 0);
begin
s_dataIn <= "10101010";
seqshiftunit_core: entity work.SeqShiftUnit(RTL)
port map(clk => s_clk,
siLeft => s_siLeft,
siRight => s_siRight,
loadEn => s_loadEn,
rotate => s_rotate,
dirLeft => s_dirLeft,
shArith => s_shArith,
dataIn => s_dataIn,
dataOut => s_dataOut);
clk_proc: process
begin
s_clk <= '0';
wait for 50 ns;
s_clk <= '1';
wait for 50 ns;
end process;
stim_proc: process
begin
s_siLeft <= '1';
s_siRight <= '1';
s_loadEn <= '1';
s_rotate <= '0';
s_dirLeft <= '0';
s_shArith <= '0';
wait for 100 ns;
s_loadEn <= '0';
s_rotate <= '1';
wait for 100 ns;
s_dirLeft <= '1';
wait for 100 ns;
s_rotate <= '0';
s_shArith <= '1';
s_dirLeft <= '1';
wait for 100 ns;
s_dirLeft <= '0';
wait for 100 ns;
s_shArith <= '0';
wait for 100 ns;
s_dirLeft <= '1';
wait for 100 ns;
end process;
end Stimulus;
|
gpl-2.0
|
56be997348ec6cbfe1ec6b2bb79d6f82
| 0.562696 | 2.714894 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 2/Bin2BCDDecoder.vhd
| 2 | 1,145 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin2BCDDecoder is
port( inBin : in std_logic_vector (6 downto 0);
outBCD: out std_logic_vector(3 downto 0);
outBCD2:out std_logic_vector(3 downto 0));
end Bin2BCDDecoder;
architecture Behavioral of Bin2BCDDecoder is
signal n,l,m : natural;
begin
n <= to_integer(unsigned(inBin));
outBCD2 <= "0000" when n<10 else
"0001" when n<20 else
"0010" when n<30 else
"0011" when n<40 else
"0100" when n<50 else
"0101" when n<60 else
"0110" when n<70 else
"0111" when n<80 else
"1000" when n<90 else
"1001";
l <= 0 when n<10 else
10 when n<20 else
20 when n<30 else
30 when n<40 else
40 when n<50 else
50 when n<60 else
60 when n<70 else
70 when n<80 else
80 when n<90 else
90;
m <= n-l;
outBCD <= "0000" when m=0 else
"0001" when m=1 else
"0010" when m=2 else
"0011" when m=3 else
"0100" when m=4 else
"0101" when m=5 else
"0110" when m=6 else
"0111" when m=7 else
"1000" when m=8 else
"1001";
end Behavioral;
|
gpl-2.0
|
0e7bb9ea61b44e3e96ac598d25687564
| 0.601747 | 2.739234 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/MDCT.vhd
| 2 | 8,291 |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
-- Company : None
--
--------------------------------------------------------------------------------
--
-- File : MDCT.VHD
-- Created : Sat Feb 25 16:12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Discrete Cosine Transform - chip top level (w/ memories)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library WORK;
use WORK.MDCT_PKG.all;
entity MDCT is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
odv1 : out STD_LOGIC;
dcto1 : out std_logic_vector(OP_W-1 downto 0)
);
end MDCT;
architecture RTL of MDCT is
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal romedatao_s : T_ROM1DATAO;
signal romodatao_s : T_ROM1DATAO;
signal romeaddro_s : T_ROM1ADDRO;
signal romoaddro_s : T_ROM1ADDRO;
signal rome2datao_s : T_ROM2DATAO;
signal romo2datao_s : T_ROM2DATAO;
signal rome2addro_s : T_ROM2ADDRO;
signal romo2addro_s : T_ROM2ADDRO;
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
begin
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : entity work.DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao => romedatao_s,
romodatao => romodatao_s,
odv => odv1,
dcto => dcto1,
romeaddro => romeaddro_s,
romoaddro => romoaddro_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
wmemsel => wmemsel_s
);
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : entity work.DCT2D
port map(
clk => clk,
rst => rst,
romedatao => rome2datao_s,
romodatao => romo2datao_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro => rome2addro_s,
romoaddro => romo2addro_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe1_s,
clk => clk,
q => ramdatao1_s
);
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe2_s,
clk => clk,
q => ramdatao2_s
);
-- double buffer switch
ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0';
ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0';
ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : entity work.DBUFCTL
port map(
clk => clk,
rst => rst,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
dataready => dataready_s
);
------------------------------
-- 1st stage ROMs
------------------------------
G_ROM_ST1 : for i in 0 to 8 generate
U1_ROME : entity work.ROME
port map(
addr => romeaddro_s(i),
clk => clk,
datao => romedatao_s(i)
);
U1_ROMO : entity work.ROMO
port map(
addr => romoaddro_s(i),
clk => clk,
datao => romodatao_s(i)
);
end generate G_ROM_ST1;
------------------------------
-- 2nd stage ROMs
------------------------------
G_ROM_ST2 : for i in 0 to 10 generate
U2_ROME : entity work.ROME
port map(
addr => rome2addro_s(i),
clk => clk,
datao => rome2datao_s(i)
);
U2_ROMO : entity work.ROMO
port map(
addr => romo2addro_s(i),
clk => clk,
datao => romo2datao_s(i)
);
end generate G_ROM_ST2;
end RTL;
|
bsd-2-clause
|
2c9766ebb1f9010733b171fb54d740b1
| 0.447835 | 4.345388 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/vga_mouse.vhd
| 1 | 8,281 |
--------------------------------------------
-- Module Name: vga_mouse - behavioral --
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.vga_mouse_pkg.all;
entity vga_mouse is
port (
sclk : in std_logic; -- system clk (100 MHz)
rst : in std_logic; -- global reset
resolution : in std_logic; -- switch to control 640x480 and 800x600 resolutions
pos_sw : in std_logic; -- switch to control data on SSEG display
bgsw : in std_logic_vector(2 downto 0);
ps2_clk : inout std_logic; -- PS/2 clk line for mouse
ps2_data : inout std_logic; -- PS/2 data line for mouse
left : out std_logic; -- mouse left button
middle : out std_logic; -- mouse middle button
right : out std_logic; -- mouse right button
busyev : out std_logic; -- indicate activity (busy or new_event)
zposled : out std_logic; -- indicate activity (zpos if applicable)
anodes : out std_logic_vector(3 downto 0); -- displays
cathodes : out std_logic_vector(6 downto 0); -- segments
-- hs, hcount, vs, vcount and blank are muxed by the resolution switch
-- and are the outputs of the corresponding resolution submodule
-- that are fed to the mouse display module and output to VGA
hsync : out std_logic; -- horizontal sync pulse to VGA
vsync : out std_logic; -- vertical sync pulse to VGA
vga_red : out std_logic_vector(2 downto 0); -- red to VGA
vga_green : out std_logic_vector(2 downto 0); -- green to VGA
vga_blue : out std_logic_vector(2 downto 1) -- blue to VGA
);
end vga_mouse;
architecture behavioral of vga_mouse is
constant tc1khz : integer := 15; -- Time constant for 1 KHz clock
signal clk1khz : std_logic := '0'; -- 1 KHz clock
signal clk_25mhz : std_logic; -- for 640x480 resolution from dividing system clk
signal clk_40mhz : std_logic; -- for 800x600 resolution from DCM
signal clk : std_logic; -- system clk output from DCM
signal cnt : std_logic_vector(1 downto 0) := "00"; -- counter to divide system clk
signal switch : std_logic := '0'; -- high for one clk period when resolution changes
signal lastres : std_logic; -- value of switch last clock edge
signal new_event : std_logic; -- high for one clk period after a packet from mouse is processed
signal busy : std_logic; -- indicates ps/2 activity
signal xpos : std_logic_vector(9 downto 0); -- output xpos from mouse ref to vga decoder
signal ypos : std_logic_vector(9 downto 0); -- output ypos from mouse ref to vga decoder
signal zpos : std_logic_vector(3 downto 0); -- z-wheel data (if applicable)
signal click : std_logic;
signal l, m, r : std_logic;
signal dispos : std_logic_vector(9 downto 0); -- either the X or Y pos data of the mouse
signal dsel : std_logic_vector(1 downto 0); -- used to cycle through SSEG displays
signal sg0, sg1, sg2 : std_logic_vector(6 downto 0) := "0000000"; -- mouse x/y diff segments
signal pos_segs : std_logic_vector(6 downto 0); -- position indicator
constant xpos_segs : std_logic_vector(6 downto 0) := "0001001"; -- 'X'
constant ypos_segs : std_logic_vector(6 downto 0) := "0011001"; -- 'Y'
-- Convert 2 or 4 bit data to hex for SSEG display
function hex_segs (binvec : std_logic_vector) return std_logic_vector is
variable decvec : std_logic_vector(3 downto 0) := "0000";
variable segments : std_logic_vector(6 downto 0);
begin
if (binvec'length = 2) then
decvec(1 downto 0) := binvec;
else
decvec := binvec;
end if;
case decvec is
when "0000" => segments := "1000000"; -- 0
when "0001" => segments := "1111001"; -- 1
when "0010" => segments := "0100100"; -- 2
when "0011" => segments := "0110000"; -- 3
when "0100" => segments := "0011001"; -- 4
when "0101" => segments := "0010010"; -- 5
when "0110" => segments := "0000010"; -- 6
when "0111" => segments := "1111000"; -- 7
when "1000" => segments := "0000000"; -- 8
when "1001" => segments := "0010000"; -- 9
when "1010" => segments := "0001000"; -- A
when "1011" => segments := "0000011"; -- b
when "1100" => segments := "1000110"; -- C
when "1101" => segments := "0100001"; -- d
when "1110" => segments := "0000110"; -- E
when "1111" => segments := "0001110"; -- F
when others => segments := "1111111"; -- OFF
end case;
return segments;
end hex_segs;
begin
-- 40 MHz clcok from DCM for 800x600 resolution
c40MHz: dcm_40mhz
port map (
clkin_in => sclk,
clkdv_out => clk_40mhz,
clk0_out => clk
);
-- Decode mouse data to vga signals
vga: vgacomp
port map (
clk => clk,
clk_25 => clk_25mhz,
clk_40 => clk_40mhz,
rst => rst,
resolution => resolution,
click => click,
bgsw => bgsw,
xpos => xpos,
ypos => ypos,
hsync => hsync,
vsync => vsync,
red => vga_red,
green => vga_green,
blue => vga_blue
);
-- Interface and controller for PS2 mouse
mouse: mousecomp
port map (
clk => clk,
resolution => resolution,
rst => rst,
switch => switch,
left => l,
middle => m,
new_event => new_event,
right => r,
busy => busy,
xpos => xpos,
ypos => ypos,
zpos => zpos,
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
-- 1 KHz clock for SSEG display
cdiv1k: cdiv
port map (
clk => clk,
tcvl => tc1khz,
cout => clk1khz
);
-- Output activity to LEDs for monitoring
busyev <= busy or new_event;
zposled <= zpos(3) or zpos(2) or zpos(1) or zpos(0);
-- Set click signal excitation for the mouse displayer
click <= l or m or r;
-- Output mouse clicks to LEDs
left <= l;
middle <= m;
right <= r;
-- 25 MHz clock (divide system clock by 4)
process(clk, cnt)
begin
if rising_edge(clk) then
if cnt = "00" then
clk_25mhz <= '1';
else
clk_25mhz <= '0';
end if;
cnt <= cnt + '1';
end if;
end process;
-- Generate switch pulse if resolution is changed
process(clk, resolution)
begin
if rising_edge(clk) then
if resolution /= lastres then
switch <= '1';
else
switch <= '0';
end if;
lastres <= resolution;
end if;
end process;
-- Display mouse position on SSEG display
process(pos_sw, xpos, ypos)
begin
case pos_sw is
when '0' => dispos <= xpos; pos_segs <= xpos_segs;
when others => dispos <= ypos; pos_segs <= ypos_segs;
end case;
end process;
process(dispos)
begin
sg0 <= hex_segs(dispos(3 downto 0));
sg1 <= hex_segs(dispos(7 downto 4));
sg2 <= hex_segs(dispos(9 downto 8));
end process;
process(clk1khz)
begin
if rising_edge(clk1khz) then
case dsel is
when "00" => anodes <= "1110"; cathodes <= sg0;
when "01" => anodes <= "1101"; cathodes <= sg1;
when "10" => anodes <= "1011"; cathodes <= sg2;
when others => anodes <= "0111"; cathodes <= pos_segs;
end case;
dsel <= dsel + 1;
end if;
end process;
end behavioral;
|
gpl-3.0
|
5a6c9dc39909474b9c7b92c43bb829cb
| 0.521676 | 4.031646 | false | false | false | false |
miree/vhdl_cores
|
uart/uart_wbp_components.vhd
| 1 | 28,463 |
-- Components that can be used to build a bidirectional
-- UART-wishbone bridge between FPGA and host system
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wbta_pkg is
constant c_wbp_adr_width : integer := 32;
constant c_wbp_dat_width : integer := 32;
subtype t_wbp_adr is
std_logic_vector(c_wbp_adr_width-1 downto 0);
subtype t_wbp_dat is
std_logic_vector(c_wbp_dat_width-1 downto 0);
subtype t_wbp_sel is
std_logic_vector((c_wbp_adr_width/8)-1 downto 0);
type t_wbp_transaction_request is record
stall_timeout : unsigned(31 downto 0); -- wait at most so long for stall to go down before ending the strobe
cyc : std_logic;
adr : t_wbp_adr;
sel : t_wbp_sel;
we : std_logic;
dat : t_wbp_dat;
end record;
constant c_wbp_transaction_init : t_wbp_transaction_request := (stall_timeout=>(others => '0'), cyc=>'0',we=>'0',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
type t_wbta_request is record
dat : t_wbp_transaction_request;
stb : std_logic;
stall : std_logic;
end record;
constant c_wbta_request_init : t_wbta_request := (c_wbp_transaction_init, '0', '0');
type t_wbp_transaction_response is record
sel : t_wbp_sel;
dat : t_wbp_dat;
we : std_logic;
ack : std_logic;
err : std_logic;
rty : std_logic;
stall_timeout : std_logic; -- this is '1' when the strobe was stalled for too long
end record;
constant c_wbp_transaction_response_init : t_wbp_transaction_response := (sel=>(others=>'0'),dat=>(others=>'0'),we=>'0',ack=>'0',err=>'0',rty=>'0',stall_timeout=>'0');
type t_wbta_response is record
dat : t_wbp_transaction_response;
stb : std_logic;
stall : std_logic;
end record;
constant c_wbta_response_init : t_wbta_response := (c_wbp_transaction_response_init, '0', '0');
type t_wbp_response is record
dat : t_wbp_dat;
ack : std_logic;
err : std_logic;
rty : std_logic;
end record;
constant c_wbp_response_init : t_wbp_response := (dat=>(others => '0'), others => '0');
type t_configuration is record
host_sends_write_response : std_logic;
fpga_sends_write_response : std_logic;
end record;
constant c_configuration_init : t_configuration := (host_sends_write_response=>'1', fpga_sends_write_response=>'1');
subtype t_byte_idx is integer range 0 to 3;
type t_byte_select is record
idx : t_byte_idx;
mask: std_logic_vector(3 downto 0);
end record;
constant c_byte_select_zero : t_byte_select := (0,(others => '0'));
function next_byte_select(byte : t_byte_select) return t_byte_select;
function init_byte_select(init_mask : std_logic_vector(3 downto 0)) return t_byte_select;
subtype t_adr_block_idx is integer range 0 to 4;
type t_adr_blocks is array (0 to 4) of std_logic_vector(5 downto 0);
type t_adr_packing is record
idx : t_adr_block_idx;
mask : std_logic_vector(0 to 4);
blocks : t_adr_blocks;
end record;
constant c_adr_packing_init : t_adr_packing := (0, (others => '0'), (others => (others => '0')));
function init_adr_packing_write(adr : std_logic_vector(31 downto 0)) return t_adr_packing;
function init_adr_packing_read(adr : std_logic_vector(31 downto 0)) return t_adr_packing;
function adr_packing_more_adr_blocks(adr_packing : t_adr_packing) return boolean;
end package;
package body wbta_pkg is
-- shift-right a bit-mask until a '1' is at maks(0).
-- increase idx by how many bits were shifted.
function next_byte_select(byte : t_byte_select) return t_byte_select is
begin
if byte.mask(1) = '1' then return (byte.idx + 1, "0" & byte.mask(3 downto 1));
elsif byte.mask(2) = '1' then return (byte.idx + 2, "00" & byte.mask(3 downto 2));
elsif byte.mask(3) = '1' then return (byte.idx + 3, "000" & byte.mask(3));
else return c_byte_select_zero;
end if;
end function;
function init_byte_select(init_mask : std_logic_vector(3 downto 0)) return t_byte_select is
variable start_byte : t_byte_select := (0, init_mask);
begin
if init_mask(0) = '1' then return start_byte;
else return next_byte_select(start_byte);
end if;
end function;
function init_adr_packing_write(adr : std_logic_vector(31 downto 0)) return t_adr_packing is
variable result : t_adr_packing := c_adr_packing_init;
begin
for i in 0 to 3 loop
result.blocks(i) := adr(9+6*i downto 4+6*i);
end loop;
result.blocks(4)(5 downto 0) := "00" & adr(31 downto 28);
for i in 0 to 4 loop
if result.blocks(i) = "000000" then
result.mask(i) := '0';
else
result.mask(i) := '1';
end if;
end loop;
result.idx := 0;
return result;
end function;
function init_adr_packing_read(adr : std_logic_vector(31 downto 0)) return t_adr_packing is
variable result : t_adr_packing := c_adr_packing_init;
begin
for i in 0 to 4 loop
result.blocks(i) := adr(7+6*i downto 2+6*i);
end loop;
for i in 0 to 4 loop
if result.blocks(i) = "000000" then
result.mask(i) := '0';
else
result.mask(i) := '1';
end if;
end loop;
result.idx := 0;
return result;
end function;
function adr_packing_more_adr_blocks(adr_packing : t_adr_packing) return boolean is
begin
if adr_packing.idx = 4 then
return false;
end if;
return unsigned(adr_packing.mask(adr_packing.idx to 4)) /= 0;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbta_pkg.all;
-- a module that handles one pipelined wishbone strobe
-- it takes strobe requests an delivers the response
entity wbta_wbp_master is
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- this interface takes a strobe request
tract_i : in t_wbp_transaction_request;
stb_i : in std_logic;
stall_o : out std_logic;
-- this interface delivers the strobe response
tract_o : out t_wbp_transaction_response;
stb_o : out std_logic;
stall_i : in std_logic;
-- configuration if a response to write strobes is expected
config_write_response_i : in std_logic;
-- a normal wishbone master
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_adr_o : out std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_o : out std_logic_vector( 3 downto 0);
wb_stall_i : in std_logic;
wb_ack_i : in std_logic;
wb_err_i : in std_logic;
wb_rty_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0));
end entity;
architecture rtl of wbta_wbp_master is
signal stall_out : std_logic := '0';
signal tract_out : t_wbp_transaction_response := c_wbp_transaction_response_init;
signal stb_out : std_logic := '0';
signal stall_timeout_count : unsigned(31 downto 0) := (others => '0');
signal stall_timeout_active: boolean := false;
signal wb_cyc_out : std_logic := '0';
signal wb_stb_out : std_logic := '0';
signal wb_we_out : std_logic := '0';
signal wb_adr_out : std_logic_vector(31 downto 0) := (others => '0');
signal wb_dat_out : std_logic_vector(31 downto 0) := (others => '0');
signal wb_sel_out : std_logic_vector( 3 downto 0) := (others => '0');
signal keep_cycle : std_logic := '0';
type t_state is (s_idle, s_wait_for_ack, s_send_response);
signal state : t_state := s_idle;
begin
stall_o <= stall_out;
tract_o <= tract_out;
stb_o <= stb_out;
wb_cyc_o <= wb_cyc_out;
wb_stb_o <= wb_stb_out;
wb_we_o <= wb_we_out;
wb_adr_o <= wb_adr_out;
wb_dat_o <= wb_dat_out;
wb_sel_o <= wb_sel_out;
stall_out <= '0' when state = s_idle else '1';
process
begin
wait until rising_edge(clk_i);
if rst_i = '1' then
tract_out <= c_wbp_transaction_response_init;
stb_out <= '0';
stall_timeout_count <= (others => '0');
stall_timeout_active <= false;
wb_cyc_out <= '0';
wb_stb_out <= '0';
wb_we_out <= '0';
wb_adr_out <= (others => '0');
wb_dat_out <= (others => '0');
wb_sel_out <= (others => '0');
state <= s_idle;
keep_cycle <= '0';
else
case state is
when s_idle =>
if stb_i = '1' then
stall_timeout_active <= tract_i.stall_timeout /= 0;
stall_timeout_count <= tract_i.stall_timeout;
wb_cyc_out <= '1';
wb_stb_out <= '1';
wb_adr_out <= tract_i.adr;
wb_dat_out <= tract_i.dat;
wb_sel_out <= tract_i.sel;
tract_out.sel <= tract_i.sel;
wb_we_out <= tract_i.we;
tract_out.we <= tract_i.we;
keep_cycle <= tract_i.cyc;
state <= s_wait_for_ack;
end if;
when s_wait_for_ack =>
if wb_stall_i = '0' then
wb_stb_out <= '0';
elsif stall_timeout_active then
stall_timeout_count <= stall_timeout_count - 1;
end if;
tract_out.dat <= wb_dat_i;
tract_out.ack <= wb_ack_i;
tract_out.err <= wb_err_i;
tract_out.rty <= wb_rty_i;
tract_out.stall_timeout <= stall_timeout_count(31);
if wb_ack_i = '1' or wb_err_i = '1' or wb_rty_i = '1' or
(stall_timeout_active and stall_timeout_count(31) = '1') then
if keep_cycle = '0' then
wb_cyc_out <= '0';
end if;
if config_write_response_i = '1' or wb_we_out = '0' then
stb_out <= '1';
state <= s_send_response;
else
state <= s_idle;
end if;
end if;
when s_send_response =>
if stall_i = '0' then
stb_out <= '0';
state <= s_idle;
end if;
end case;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbta_pkg.all;
-- Transfrom incoming bytes into wishbone transactions
-- Internal state: registers for adr,dat,sel and
-- the state of the state-machine
entity uart_wbta is
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- uart receiver interface
rx_dat_i : in std_logic_vector(7 downto 0);
rx_stb_i : in std_logic;
rx_stall_o : out std_logic;
-- wishbone transaction interface
wbta_dat_o : out t_wbp_transaction_request;
wbta_stb_o : out std_logic;
wbta_stall_i : in std_logic;
-- response interface from host to wishbone slave interface (wb_uart)
config_o : out t_configuration;
stb_resp_o : out t_wbp_response;
-- general purpose output bits
gpo_bits_o : out std_logic_vector(31 downto 0);
-- this reset can be initiated by the host
bridge_reset_o : out std_logic
);
end entity;
architecture rtl of uart_wbta is
signal wb_dat : std_logic_vector(31 downto 0) := (others => '0');
signal wb_adr : std_logic_vector(31 downto 0) := (others => '0');
signal wb_sel : std_logic_vector( 3 downto 0) := (others => '0');
signal stall_timeout : std_logic_vector(31 downto 0) := (others => '0');
signal gpo_bits : std_logic_vector(31 downto 0) := (others => '0');
type t_state is (s_idle, s_receive, s_stb);
signal state : t_state := s_idle;
type t_command is (command_config, -- command code 0
command_set_sel, -- command code 1
command_set_dat, -- command code 2
command_set_adr, -- command code 3
command_write_stb, -- command code 4
command_read_stb, -- command code 5
command_set_timeout, -- command code 6
command_slave_ack, -- command code 7
command_slave_err, -- command code 8
command_slave_rty, -- command code 9
command_set_gpo, -- command code 10
command_reset, -- command code 11
command_invalid);
-- type conversion function to t_command
function to_t_command (encoding : std_logic_vector) return t_command is
begin
for cmd in t_command'left to t_command'right loop
if to_integer(unsigned(encoding)) = t_command'pos(cmd) then
return cmd;
end if;
end loop;
return command_invalid;
end function;
signal command : t_command := command_invalid;
signal mask : std_logic_vector(3 downto 0) := (others => '0');
procedure start_receive(signal init_mask : in std_logic_vector(3 downto 0); signal byte : out t_byte_select; signal new_state : out t_state) is
begin
if init_mask /= "0000" then
byte <= init_byte_select(init_mask);
new_state <= s_receive;
end if;
end procedure;
signal byte_select : t_byte_select := c_byte_select_zero;
signal wbta_we_out : std_logic := '0';
signal wbta_stb_out : std_logic := '0';
type t_receive_type is (receive_adr, receive_dat, receive_timeout, receive_gpo_bits);
signal receive_type : t_receive_type;
signal delta_adr : signed(2 downto 0) := (others => '0'); -- this changes the address after stb to optimize successive strobes with increasing address
signal config_out : t_configuration := c_configuration_init;
signal stb_resp_out : t_wbp_response := c_wbp_response_init;
signal gpo_bits_out : std_logic_vector(31 downto 0) := (others => '0');
signal bridge_reset_out : std_logic := '0';
signal reset_just_happened : std_logic := '0';
begin
-- we can only take rx_data in s_idle or s_receive state
rx_stall_o <= '0' when state = s_idle or state = s_receive
else '1';
-- wishbone transaction output signals
wbta_dat_o.adr <= wb_adr;
wbta_dat_o.sel <= wb_sel;
wbta_dat_o.dat <= wb_dat;
wbta_dat_o.cyc <= mask(3); -- this is the bit that controls cyc after stb response (ack,err,rty, or timeout)
wbta_dat_o.we <= wbta_we_out;
wbta_dat_o.stall_timeout <= unsigned(stall_timeout);
wbta_stb_o <= wbta_stb_out;
config_o <= config_out;
stb_resp_o <= stb_resp_out;
gpo_bits_o <= gpo_bits_out;
bridge_reset_o <= bridge_reset_out;
-- the incoming byte consists of a
-- 4-bit mask in the most significant half
-- and a 4-bit command in the least significant half.
mask <= rx_dat_i(7 downto 4);
command <= to_t_command(rx_dat_i(3 downto 0)) when rx_stb_i = '1' and state = s_idle
else command_invalid;
process
begin
wait until rising_edge(clk_i);
if rst_i = '1' then
reset_just_happened <= '1';
end if;
stb_resp_out <= c_wbp_response_init;
bridge_reset_out <= '0';
case state is
when s_idle =>
gpo_bits_out <= gpo_bits;
if rx_stb_i = '1' then
case command is
when command_config =>
reset_just_happened <= '0';
config_out.host_sends_write_response <= mask(0);
config_out.fpga_sends_write_response <= mask(1);
when command_set_sel =>
reset_just_happened <= '0';
wb_sel <= mask;
when command_set_dat =>
reset_just_happened <= '0';
receive_type <= receive_dat;
start_receive(mask, byte_select, state);
when command_set_adr =>
reset_just_happened <= '0';
receive_type <= receive_adr;
start_receive(mask, byte_select, state);
when command_set_timeout =>
reset_just_happened <= '0';
receive_type <= receive_timeout;
start_receive(mask, byte_select, state);
when command_write_stb =>
reset_just_happened <= '0';
wbta_stb_out <= '1';
wbta_we_out <= '1';
delta_adr <= signed(mask(2 downto 0));
state <= s_stb;
when command_read_stb =>
reset_just_happened <= '0';
wbta_stb_out <= '1';
wbta_we_out <= '0';
delta_adr <= signed(mask(2 downto 0));
state <= s_stb;
when command_slave_ack =>
reset_just_happened <= '0';
stb_resp_out.ack <= '1';
stb_resp_out.dat <= wb_dat;
when command_slave_err =>
reset_just_happened <= '0';
stb_resp_out.err <= '1';
stb_resp_out.dat <= wb_dat;
when command_slave_rty =>
reset_just_happened <= '0';
stb_resp_out.rty <= '1';
stb_resp_out.dat <= wb_dat;
when command_set_gpo =>
reset_just_happened <= '0';
receive_type <= receive_gpo_bits;
start_receive(mask, byte_select, state);
when command_reset =>
reset_just_happened <= '1';
if reset_just_happened = '0' then
bridge_reset_out <= '1';
wb_dat <= (others => '0');
wb_adr <= (others => '0');
wb_sel <= (others => '0');
stall_timeout <= (others => '0');
gpo_bits <= (others => '0');
state <= s_idle;
end if;
when others =>
end case;
end if;
when s_receive =>
if rx_stb_i = '1' then
if receive_type = receive_dat then -- distinguish between data and address settings
wb_dat((byte_select.idx+1)*8-1 downto byte_select.idx*8) <= rx_dat_i;
elsif receive_type = receive_adr then
wb_adr((byte_select.idx+1)*8-1 downto byte_select.idx*8) <= rx_dat_i;
elsif receive_type = receive_timeout then
stall_timeout((byte_select.idx+1)*8-1 downto byte_select.idx*8) <= rx_dat_i;
elsif receive_type = receive_gpo_bits then
gpo_bits((byte_select.idx+1)*8-1 downto byte_select.idx*8) <= rx_dat_i;
end if;
-- handle the shifting of the byte-select-bitfield and detect end condition
byte_select <= next_byte_select(byte_select);
if byte_select.mask(3 downto 1) = "000" then
state <= s_idle;
end if;
end if;
when s_stb =>
if wbta_stall_i = '0' then
wbta_stb_out <= '0';
wb_adr <= std_logic_vector(signed(wb_adr) + 4*to_integer(delta_adr));
state <= s_idle;
end if;
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbta_pkg.all;
-- Transfrom incoming wishbone transaction responses
-- into a byte stream that can be digested by uart transmitter
entity wbta_uart is
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- uart receiver interface
tx_dat_o : out std_logic_vector(7 downto 0);
tx_stb_o : out std_logic;
tx_stall_i : in std_logic;
-- wishbone transaction interface
wbta_dat_i : in t_wbp_transaction_response;
wbta_stb_i : in std_logic;
wbta_stall_o : out std_logic
);
end entity;
architecture rtl of wbta_uart is
function response_type(ack, err, rty, stall_timeout : std_logic) return std_logic_vector is
begin
if ack = '1' then return "001"; -- 1
elsif err = '1' then return "010"; -- 2
elsif rty = '1' then return "011"; -- 3
elsif stall_timeout = '1' then return "100"; -- 4
else return "000";
end if;
end function;
type t_state is (s_idle, s_write_header, s_read_header, s_read_data);
signal state : t_state := s_idle;
--signal wbta_stall_out : std_logic := '0';
signal tx_dat_out : std_logic_vector( 7 downto 0) := (others => '0');
signal tx_stb_out : std_logic := '0';
signal wb_dat : t_wbp_dat := (others => '0');
signal wb_sel : t_wbp_dat := (others => '0');
signal byte_select : t_byte_select := c_byte_select_zero;
begin
wbta_stall_o <= '0' when state = s_idle else '1';
tx_dat_o <= tx_dat_out;
tx_stb_o <= tx_stb_out;
process
variable byte_select_next : t_byte_select;
begin
wait until rising_edge(clk_i);
if rst_i = '1' then
state <= s_idle;
tx_dat_out <= (others => '0');
tx_stb_out <= '0';
wb_dat <= (others => '0');
wb_sel <= (others => '0');
byte_select <= c_byte_select_zero;
else
case state is
when s_idle =>
if wbta_stb_i = '1' then
wb_dat <= wbta_dat_i.dat;
tx_stb_out <= '1';
if wbta_dat_i.we = '1' then
tx_dat_out <= '1' & "000" & '0' & response_type(wbta_dat_i.ack, wbta_dat_i.err, wbta_dat_i.rty, wbta_dat_i.stall_timeout);
state <= s_write_header;
else
tx_dat_out <= '1' & response_type(wbta_dat_i.ack, wbta_dat_i.err, wbta_dat_i.rty, wbta_dat_i.stall_timeout) & wbta_dat_i.dat(31) & wbta_dat_i.dat(23) & wbta_dat_i.dat(15) & wbta_dat_i.dat(7);
state <= s_read_header;
end if;
end if;
when s_write_header =>
if tx_stall_i = '0' then
tx_stb_out <= '0';
state <= s_idle;
end if;
when s_read_header =>
if tx_stall_i = '0' then
byte_select_next := init_byte_select(wbta_dat_i.sel);
byte_select <= byte_select_next;
tx_dat_out <= '0' & wb_dat((byte_select_next.idx+1)*8-2 downto byte_select_next.idx*8);
if byte_select_next.mask = "0000" then
tx_stb_out <= '0';
state <= s_idle;
else
state <= s_read_data;
end if;
end if;
when s_read_data =>
if tx_stall_i = '0' then
byte_select_next := next_byte_select(byte_select);
if byte_select_next.mask = "0000" then
tx_stb_out <= '0';
state <= s_idle;
end if;
byte_select <= byte_select_next;
tx_dat_out <= '0' & wb_dat((byte_select_next.idx+1)*8-2 downto byte_select_next.idx*8);
end if;
end case;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbta_pkg.all;
-- A wishbone slave interface with read and write capability
entity wb_uart is
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- separate bridge reset from host that is used to get the state machine out of s_wait_for_host_response
bridge_reset_i : in std_logic;
-- host response
config_write_response_i : in std_logic;
stb_resp_i : in t_wbp_response;
-- uart transmitter interface
tx_dat_o : out std_logic_vector(7 downto 0);
tx_stb_o : out std_logic;
tx_stall_i : in std_logic;
-- wishbone slave interface
dat_i : in std_logic_vector(31 downto 0);
adr_i : in std_logic_vector(31 downto 0);
sel_i : in std_logic_vector( 3 downto 0);
cyc_i : in std_logic;
stb_i : in std_logic;
we_i : in std_logic;
stall_o : out std_logic;
ack_o : out std_logic;
rty_o : out std_logic;
err_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of wb_uart is
signal tx_dat_out : std_logic_vector(7 downto 0) := (others => '0');
signal tx_stb_out : std_logic := '0';
signal wbp_resp_out : t_wbp_response := c_wbp_response_init;
signal wb_dat : std_logic_vector(31 downto 0) := (others => '0');
signal wb_adr : std_logic_vector(31 downto 0) := (others => '0');
signal wb_sel : std_logic_vector( 3 downto 0) := (others => '0');
signal wb_we : std_logic := '0';
signal adr_packing : t_adr_packing := c_adr_packing_init;
type t_state is (s_idle,
s_write_header, s_adr, s_finish_read_adr,
s_prepare_write_data, s_write_data,
s_wait_for_host_response
);
signal state : t_state := s_idle;
signal byte_select : t_byte_select := c_byte_select_zero;
signal lowest_adr_bit_read : integer := 0;
-- The slave produces two types of headers (type field 5 or 7)
-- Type 5 is a slave write access, causing the wb-write callback function on the host to be called
-- Type 7 is a slave read access, causing the wb-read callback funciton on the host to be called
-- A variable number of bytes can follow a type 5 header, depending on the sel-bits and the length of the address
-- header type 5 "1 101 ssss" "00aadddd" "0ddddddd" "0ddddddd" "0ddddddd" "0ddddddd"
-- header type 5 "1 101 ssss" "01aadddd" "00aaaaaa" "0ddddddd" "0ddddddd" "0ddddddd" "0ddddddd"
-- ........................
-- header type 5 "1 101 ssss" "01aadddd" "01aaaaaa" "01aaaaaa" "01aaaaaa" "01aaaaaa" "00--aaaa" "0ddddddd" "0ddddddd" "0ddddddd" "0ddddddd"
-- / \ \\ / \
-- / adr bit 2 \ adr bit 4 adr bit 31 adr bit 26
-- adr bit 3 adr bit 5
--
-- not yet implmeneted fast write (writes with sel = "1111" and without address) response type 6 header "1 110 dddd" "0ddddddd" "0ddddddd" "0ddddddd" "0ddddddd"
-- slave reads
-- header type 7 "1 111 ssss" "00aaaaaa"
-- ...
-- header type 7 "1 111 ssss" "01aaaaaa" "01aaaaaa" "01aaaaaa" "01aaaaaa" "00aaaaaa"
begin
tx_dat_o <= tx_dat_out;
tx_stb_o <= tx_stb_out;
stall_o <= '0' when state = s_idle else '1';
ack_o <= wbp_resp_out.ack;
rty_o <= wbp_resp_out.rty;
err_o <= wbp_resp_out.err;
dat_o <= wbp_resp_out.dat;
process
variable byte_select_next : t_byte_select;
begin
wait until rising_edge(clk_i);
if rst_i = '1' then
tx_dat_out <= (others => '0');
tx_stb_out <= '0';
wbp_resp_out <= c_wbp_response_init;
wb_dat <= (others => '0');
wb_adr <= (others => '0');
wb_sel <= (others => '0');
wb_we <= '0';
state <= s_idle;
byte_select <= c_byte_select_zero;
lowest_adr_bit_read <= 0;
else
wbp_resp_out <= c_wbp_response_init;
case state is
when s_idle =>
if cyc_i = '1' and stb_i = '1' then
if we_i = '1' then
wb_dat <= dat_i;
wb_adr <= adr_i;
wb_sel <= sel_i;
wb_we <= '1';
wbp_resp_out.ack <= not config_write_response_i; -- don't ack if a write response from the host is expected
tx_stb_out <= '1';
tx_dat_out <= "1101" & sel_i;
adr_packing <= init_adr_packing_write(adr_i);
state <= s_write_header;
else
wb_adr <= adr_i;
wb_sel <= sel_i;
wb_we <= '0';
wbp_resp_out.ack <= '0';
tx_stb_out <= '1';
tx_dat_out <= "1111" & sel_i;
adr_packing <= init_adr_packing_read(adr_i);
state <= s_adr;
end if;
else
tx_stb_out <= '0';
end if;
when s_write_header =>
if tx_stall_i = '0' then
if adr_packing_more_adr_blocks(adr_packing) then
tx_dat_out <= '0' & '1' & wb_adr(3 downto 2) & wb_dat(31) & wb_dat(23) & wb_dat(15) & wb_dat(7);
state <= s_adr;
else
tx_dat_out <= '0' & '0' & wb_adr(3 downto 2) & wb_dat(31) & wb_dat(23) & wb_dat(15) & wb_dat(7);
state <= s_prepare_write_data;
end if;
end if;
when s_adr =>
if tx_stall_i = '0' then
if adr_packing_more_adr_blocks(adr_packing) then
adr_packing.idx <= adr_packing.idx + 1;
tx_dat_out <= '0' & '1' & adr_packing.blocks(adr_packing.idx);
else
tx_dat_out <= '0' & '0' & adr_packing.blocks(adr_packing.idx);
if wb_we = '1' then
state <= s_prepare_write_data;
else
state <= s_finish_read_adr;
end if;
end if;
end if;
when s_finish_read_adr =>
if tx_stall_i = '0' then
state <= s_wait_for_host_response;
end if;
when s_prepare_write_data =>
if tx_stall_i = '0' then
byte_select_next := init_byte_select(wb_sel);
byte_select <= byte_select_next;
tx_dat_out <= '0' & wb_dat((byte_select_next.idx+1)*8-2 downto byte_select_next.idx*8);
if byte_select_next.mask = "0000" then
tx_stb_out <= '0';
if config_write_response_i = '1' then
state <= s_wait_for_host_response;
else
state <= s_idle;
end if;
else
state <= s_write_data;
end if;
end if;
when s_write_data =>
if tx_stall_i = '0' then
byte_select_next := next_byte_select(byte_select);
byte_select <= byte_select_next;
tx_dat_out <= '0' & wb_dat((byte_select_next.idx+1)*8-2 downto byte_select_next.idx*8);
if byte_select_next.mask = "0000" then
tx_stb_out <= '0';
if config_write_response_i = '1' then
state <= s_wait_for_host_response;
else
state <= s_idle;
end if;
end if;
end if;
when s_wait_for_host_response =>
tx_stb_out <= '0';
if bridge_reset_i = '1' then
wbp_resp_out <= c_wbp_response_init;
state <= s_idle;
else
if stb_resp_i.ack = '1' or stb_resp_i.err = '1' or stb_resp_i.rty = '1' then
wbp_resp_out <= stb_resp_i;
state <= s_idle;
end if;
end if;
end case;
end if;
end process;
end architecture;
|
mit
|
5c59a96bc26a6b9c5e11f6911fad7a1a
| 0.584267 | 2.942216 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/vga_controller_800_60.vhd
| 1 | 8,565 |
------------------------------------------------------------------------
-- vga_controller_800_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic to generate the synchronization signals,
-- horizontal and vertical pixel counter and video disable signal
-- for the 800x600@60Hz resolution.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web regarding the
-- vga video timings:
-- http://www.epanorama.net/documents/pc/vga_timing.html
-- This module generates the video synch pulses for the monitor to
-- enter 800x600@60Hz resolution state. It also provides horizontal
-- and vertical counters for the currently displayed pixel and a blank
-- signal that is active when the pixel is not inside the visible screen
-- and the color outputs should be reset to 0.
-- timing diagram for the horizontal synch signal (HS)
-- 0 840 968 1056 (pixels)
-- _________________________|------|_________________
-- timing diagram for the vertical synch signal (VS)
-- 0 601 605 628 (lines)
-- __________________________________|------|________
-- The blank signal is delayed one pixel clock period (25ns) from where
-- the pixel leaves the visible screen, according to the counters, to
-- account for the pixel pipeline delay. This delay happens because
-- it takes time from when the counters indicate current pixel should
-- be displayed to when the color data actually arrives at the monitor
-- pins (memory read delays, synchronization delays).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- rst - global reset signal
-- pixel_clk - input pin, from dcm_40MHz
-- - the clock signal generated by a DCM that has
-- - a frequency of 40MHz.
-- HS - output pin, to monitor
-- - horizontal synch pulse
-- VS - output pin, to monitor
-- - vertical synch pulse
-- hcount - output pin, 11 bits, to clients
-- - horizontal count of the currently displayed
-- - pixel (even if not in visible area)
-- vcount - output pin, 11 bits, to clients
-- - vertical count of the currently active video
-- - line (even if not in visible area)
-- blank - output pin, to clients
-- - active when pixel is not in visible area.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the vga_controller_800_60 entity declaration
-- read above for behavioral description and port definitions.
entity vga_controller_800_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
hcount : out std_logic_vector(10 downto 0);
vcount : out std_logic_vector(10 downto 0);
blank : out std_logic
);
end vga_controller_800_60;
architecture Behavioral of vga_controller_800_60 is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "10000100000"; -- 1056
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01001110100"; -- 628
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01101001000"; -- 840
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01111001000"; -- 968
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "01001011000"; -- 600
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "01001011001"; -- 601
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "01001011101"; -- 605
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
-- output horizontal and vertical counters
hcount <= hcounter;
vcount <= vcounter;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
else
hcounter <= hcounter + 1;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 128 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 4 video lines
-- = 4*HMAX = 4224 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
end Behavioral;
|
gpl-3.0
|
3812df7bdaa26e6616ea2cdb77864052
| 0.526328 | 4.693151 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/mem.vhd
| 1 | 4,400 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity mem is
Port(
-- wired to CPU core
I_clk: in std_logic;
I_en: in std_logic;
I_op: in std_logic_vector(2 downto 0); -- memory opcodes
I_iaddr: in std_logic_vector(31 downto 0); -- instruction address, provided by PCU
I_daddr: in std_logic_vector(31 downto 0); -- data address, provided by ALU
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
I_mem_imem: in std_logic := '0'; -- denotes if instruction memory is accessed (signal from control unit)
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic := '0';
-- wired to outside world, RAM, devices etc.
O_memen: out std_logic := '0';
O_memaddr: out std_logic_vector(31 downto 0);
O_memdata: out std_logic_vector(31 downto 0);
I_memdata: in std_logic_vector(31 downto 0);
O_memwrite: out std_logic := '0';
I_membusy: in std_logic := '0'
);
end mem;
architecture Behavioral of mem is
type control_states is (IDLE, READW, READH, READB, WRITEW, WRITEH1, WRITEH2, WRITEB1, WRITEB2);
signal state: control_states := IDLE;
signal buf: std_logic_vector(31 downto 0) := X"00000000";
begin
process(I_clk)
begin
if rising_edge(I_clk) and I_en = '1' then
case state is
when IDLE =>
case I_op is
when MEMOP_READW =>
O_memwrite <= '0';
O_memen <= '1';
O_busy <= '1';
if I_mem_imem = '1' then
-- read from instruction memory
O_memaddr <= I_iaddr;
else
-- read from data memory/devices
O_memaddr <= I_daddr;
end if;
state <= READW;
when MEMOP_READH =>
O_memwrite <= '0';
O_memen <= '1';
O_busy <= '1';
O_memaddr <= I_daddr;
state <= READH;
when MEMOP_READB =>
O_memwrite <= '0';
O_memen <= '1';
O_busy <= '1';
O_memaddr <= I_daddr;
state <= READB;
when MEMOP_WRITEW =>
-- visible endianess of this architecture is little endian!
O_memdata <= I_data(7 downto 0) & I_data(15 downto 8) & I_data(23 downto 16) & I_data(31 downto 24);
O_memwrite <= '1';
O_memen <= '1';
O_busy <= '1';
O_memaddr <= I_daddr;
state <= WRITEW;
when MEMOP_WRITEH =>
O_busy <= '1';
O_memwrite <= '0';
O_memen <= '1';
O_memaddr <= I_daddr;
state <= WRITEH1;
when MEMOP_WRITEB =>
O_busy <= '1';
O_memwrite <= '0';
O_memen <= '1';
O_memaddr <= I_daddr;
state <= WRITEB1;
when others =>
-- FIXME: Support the other mem ops!
null;
end case;
when READW =>
if I_membusy = '0' then
O_memen <= '0';
O_busy <= '0';
O_data <= I_memdata(7 downto 0) & I_memdata(15 downto 8) & I_memdata(23 downto 16) & I_memdata(31 downto 24);
state <= IDLE;
end if;
when READH =>
if I_membusy = '0' then
O_memen <= '0';
O_busy <= '0';
O_data <= std_logic_vector(resize(signed(I_memdata(23 downto 16) & I_memdata(31 downto 24)), O_data'length));
state <= IDLE;
end if;
when READB =>
if I_membusy = '0' then
O_memen <= '0';
O_busy <= '0';
O_data <= std_logic_vector(resize(signed(I_memdata(31 downto 24)), O_data'length));
state <= IDLE;
end if;
when WRITEW =>
if I_membusy = '0' then
O_memen <= '0';
O_memwrite <= '0';
O_busy <= '0';
state <= IDLE;
end if;
when WRITEH1 =>
if I_membusy = '0' then
-- combine new word and write to memory
O_memdata <= I_data(7 downto 0) & I_data(15 downto 8) & I_memdata(15 downto 0);
O_memwrite <= '1';
state <= WRITEH2;
end if;
when WRITEH2 =>
if I_membusy = '0' then
O_memwrite <= '0';
O_busy <= '0';
state <= IDLE;
end if;
when WRITEB1 =>
if I_membusy = '0' then
-- combine new word and write to memory
O_memdata <= I_data(7 downto 0) & I_memdata(23 downto 0);
O_memwrite <= '1';
state <= WRITEB2;
end if;
when WRITEB2 =>
if I_membusy = '0' then
O_memwrite <= '0';
O_busy <= '0';
state <= IDLE;
end if;
end case;
end if;
end process;
end Behavioral;
|
mit
|
eaa199bcdff329547cf436d7329ce9bf
| 0.538409 | 2.974983 | false | false | false | false |
miree/vhdl_cores
|
tdc/delayline.vhd
| 1 | 1,450 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delayline is
generic (
length : integer
);
port ( clk_i : in std_logic;
rst_i : in std_logic;
async_i : in std_logic;
line_o : out std_logic_vector(length-1 downto 0);
signal_o : out std_logic
);
end entity;
architecture rtl of delayline is
signal delay_line : std_logic_vector(length downto 0);
signal line_buffer_snap : std_logic_vector(length downto 0);
signal line_buffer : std_logic_vector(length downto 0);
signal edge_buffer : std_logic_vector(length-1 downto 0);
attribute KEEP : string;
attribute KEEP of delay_line : signal is "true";
begin
process(clk_i) is
begin
if rising_edge(clk_i) then
line_buffer_snap <= delay_line;
for i in edge_buffer'range loop
edge_buffer(i) <= (not line_buffer_snap(i+1) xor line_buffer_snap(i));
end loop;
line_buffer <= line_buffer_snap;
if unsigned(edge_buffer) /= 0 then
line_o <= line_buffer(length downto 1);
signal_o <= '1';
else
line_o <= (others => '0');
signal_o <= '0';
end if;
end if;
end process;
process (delay_line, async_i)
begin
for i in delay_line'range loop
if i = delay_line'left then
delay_line(i) <= async_i;
else
delay_line(i) <= not delay_line(i+1) after 330 ps;
end if;
end loop;
end process;
end architecture;
|
mit
|
9bb711dc6c21eb8359eca23225732b32
| 0.618621 | 2.941176 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2/HexDigSSegCntrl.vhd
| 1 | 2,821 |
-----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;
sws : in std_logic_vector (2 downto 0);
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0));
end HexDigSSegCntrl;
architecture control of HexDigSSegCntrl is
signal cntr : std_logic_vector (3 downto 0);
signal sw0 : std_logic;
signal csws : std_logic_vector (1 downto 0);
signal en : std_logic;
signal clk : std_logic;
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
constant TC16Hz : integer := 42; -- TC for 16 Hz clock
constant TC30Hz : integer := 36; -- TC for 30 Hz clock
constant TC312Hz : integer := 20; -- TC for 312 Hz clock
signal clk5Hz : std_logic := '0'; -- 5Hz clock
signal clk16Hz : std_logic := '0'; -- 16Hz clock
signal clk30Hz : std_logic := '0'; -- 30Hz clock
signal clk312Hz : std_logic := '0'; -- 312Hz clock
signal c0, c1, c2, c3 : integer range 0 to 15;
begin
sw0 <= sws(0);
csws(0) <= sws(1);
csws(1) <= sws(2);
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
c16Hz: CDiv port map (clock, TC16Hz, clk16Hz);
c30Hz: CDiv port map (clock, TC30Hz, clk30Hz);
c312Hz: CDiv port map (clock, TC312Hz, clk312Hz);
HexDs: Hex4Digs_2_SSeg port map (clock, clk, sw0, cntr, anodes, cathodes);
process (csws, clk5Hz, clk16Hz, clk30Hz, clk312Hz) -- control clocks
begin
case csws is
when "00" =>
clk <= clk5Hz;
when "01" =>
clk <= clk16Hz;
when "10" =>
clk <= clk30Hz;
when others =>
clk <= clk312Hz;
end case;
end process;
process (clk)
begin
if rising_edge(clk) then
en <= not en;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
c0 <= c0 + 1;
cntr(0) <= '1';
if (c0 = 15) then
c1 <= c1 + 1;
cntr(1) <= '1';
if (c1 = 15) then
c2 <= c2 + 1;
cntr(2) <= '1';
if (c2 = 15) then
c3 <= c3 + 1;
cntr(3) <= '1';
end if;
end if;
end if;
else
cntr <= "0000";
end if;
end if;
end process;
end control;
|
gpl-3.0
|
d78cda6e0619910dc607e5d881ddb072
| 0.47111 | 3.668401 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/simu_banco.vhd
| 2 | 3,136 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:11:41 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/simu_banco.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: BancoDeRegistros
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY simu_banco IS
END simu_banco;
ARCHITECTURE behavior OF simu_banco IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BancoDeRegistros
PORT(
Clock : IN std_logic;
Reg_Write : IN std_logic;
RA : IN std_logic_vector(4 downto 0);
RB : IN std_logic_vector(4 downto 0);
RW : IN std_logic_vector(4 downto 0);
busW : IN std_logic_vector(31 downto 0);
busA : OUT std_logic_vector(31 downto 0);
busB : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal Reg_Write : std_logic := '0';
signal RA : std_logic_vector(4 downto 0) := (others => '0');
signal RB : std_logic_vector(4 downto 0) := (others => '0');
signal RW : std_logic_vector(4 downto 0) := (others => '0');
signal busW : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal busA : std_logic_vector(31 downto 0);
signal busB : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BancoDeRegistros PORT MAP (
Clock => Clock,
Reg_Write => Reg_Write,
RA => RA,
RB => RB,
RW => RW,
busW => busW,
busA => busA,
busB => busB
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reg_write<='1';
wait for 100 ns;
RA<="00000";
RB<="00001";
RW<="00010";
busW<=X"FFFFFFFF";
wait for 100 ns;
RA<="00010";
RB<="00011";
RW<="00011";
busW<=X"AAAAAAAA";
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
1a15959fd323b9d6c8870163dc1c521b
| 0.555166 | 3.82906 | false | true | false | false |
spoorcc/realtimestagram
|
src/hsv2rgb_testsets_tb.vhd
| 2 | 2,522 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
entity hsv2rgb_testsets_tb is
end entity;
architecture all_tests of hsv2rgb_testsets_tb is
component hsv2rgb_tb is
generic (
input_file: string; --! Input file of test
output_file: string --! Output file of test
);
end component;
begin
Lenna: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_lenna.pnm",
output_file => "tst/output/hsv2rgb_lenna.pnm"
);
windmill: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_windmill.pnm",
output_file => "tst/output/hsv2rgb_windmill.pnm"
);
danger_zone: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_danger_zone.pnm",
output_file => "tst/output/hsv2rgb_danger_zone.pnm"
);
amersfoort: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_amersfoort.pnm",
output_file => "tst/output/hsv2rgb_amersfoort.pnm"
);
rainbow: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_rainbow.pnm",
output_file => "tst/output/hsv2rgb_rainbow.pnm"
);
hue_gradient: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_hue_gradient.pnm",
output_file => "tst/output/hsv2rgb_hue_gradient.pnm"
);
sat_gradient: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_sat_gradient.pnm",
output_file => "tst/output/hsv2rgb_sat_gradient.pnm"
);
val_gradient: hsv2rgb_tb
generic map(
input_file => "tst/output/rgb2hsv_val_gradient.pnm",
output_file => "tst/output/hsv2rgb_val_gradient.pnm"
);
end architecture;
|
gpl-2.0
|
813bbd47f5ca0cca3156bdf6d24ed026
| 0.615385 | 3.671033 | false | true | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/Mux2_1Demo.vhd
| 2 | 547 |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux2_1Demo is
port( SW : in STD_LOGIC_VECTOR(3 downto 0);
KEY : in STD_LOGIC_VECTOR(3 downto 2);
LEDR : out STD_LOGIC_VECTOR(0 downto 0));
end Mux2_1Demo;
Architecture Shell of Mux2_1Demo is
begin
system_core: entity work.Mux2_1(BehavProcess)
port map( dataln(0) => SW(0),
dataln(1) => SW(1),
dataln(2) => SW(2),
dataln(3) => SW(3),
sel(1) => KEY(3),
sel(0) => KEY(2),
dataOut => LEDR(0));
end Shell;
|
gpl-2.0
|
8a7299bcb69dc3e17ed4eca17d23ad8e
| 0.553931 | 2.629808 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 7/Parte 2(TPC)/DrinksMachine.vhd
| 1 | 1,512 |
library IEEE;
use IEEE.std_logic_1164.all;
entity DrinksMachine is
port( CLOCK_50 : in std_logic;
SW : in std_logic_vector(2 downto 0);
KEY : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(0 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0));
end DrinksMachine;
architecture Shell of DrinksMachine is
signal clk50Mhz, s_clk : std_logic;
signal sm_money, sc_money : std_logic_vector(3 downto 0);
signal s_hex6, s_hex7, s_hex5 : std_logic_vector(6 downto 0);
begin
clk50MHz <= CLOCK_50;
sw_debounce : entity WORK.DebounceUnit(Behavioral)
generic map(clkFrekHz => 50000,
blindmSec => 100,
inPol => '0',
outPol => '1')
port map(reset => SW(0),
refClk => clk50MHz,
dirtyIn => KEY(0),
pulsedOut => s_clk);
drink_core : entity work.DrinksFSM(Behavioral)
port map(C => SW(2),
V => SW(1),
reset => SW(0),
clk => s_clk,
drink => LEDG(0),
m_money => sm_money,
c_money => sc_money);
hex7_seg_dec : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => sc_money,
decOut_n => s_hex7);
hex6_seg_dec : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => sm_money,
decOut_n => s_hex6);
hex5_seg_dec : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => "0000",
decOut_n => s_hex5);
HEX7 <= s_hex7;
HEX6 <= s_hex6;
HEX5 <= s_hex5;
end Shell;
|
gpl-2.0
|
abe12853205dd37477d04ae4e0c36176
| 0.621032 | 2.554054 | false | false | false | false |
spoorcc/realtimestagram
|
src/sepia_tb.vhd
| 2 | 6,717 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
use work.config_const_pkg.all;
--======================================================================================--
entity sepia_tb is
generic (
input_file: string := "tst/input/amersfoort.pnm"; --! Input file of test
output_file: string := "tst/output/sepia_amersfoort.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight; --! Height of input image
sepia_threshold: integer := (255 * 50) / 100
);
end entity;
--======================================================================================--
architecture structural of sepia_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 4
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component sepia is
generic (
wordsize: integer := const_wordsize; --! input image wordsize in bits
image_width: integer := image_width; --! width of input image
image_height: integer := image_height --! height of input image
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_red_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
threshold: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_red_o: out std_logic_vector((wordsize-1) downto 0); --! the output pixel
pixel_green_o: out std_logic_vector((wordsize-1) downto 0); --! the output pixel
pixel_blue_o: out std_logic_vector((wordsize-1) downto 0) --! the output pixel
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal threshold_in: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: sepia
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_red_i => red_pixel_from_file,
pixel_green_i => green_pixel_from_file,
pixel_blue_i => blue_pixel_from_file,
threshold => threshold_in,
pixel_red_o => red_pixel_to_file,
pixel_green_o => green_pixel_to_file,
pixel_blue_o => blue_pixel_to_file
);
threshold_in <= std_logic_vector(to_unsigned(sepia_threshold, const_wordsize));
end architecture;
|
gpl-2.0
|
18428fb9f95dee29e85b9d3e495c70a1
| 0.507518 | 4.216573 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 8/TrafficLights/TrafficLightsFSM.vhd
| 1 | 3,987 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TrafficLightsFSM is
port(reset : in std_logic;
clk : in std_logic;
intermit : in std_logic;
newTime : out std_logic;
timeVal : out std_logic_vector(7 downto 0);
timeExp : in std_logic;
yBlink : out std_logic;
red1 : out std_logic;
yellow1 : out std_logic;
green1 : out std_logic;
red2 : out std_logic;
yellow2 : out std_logic;
green2 : out std_logic);
end TrafficLightsFSM;
architecture Behavioral of TrafficLightsFSM is
constant RED_TIME : std_logic_vector(7 downto 0) := "00000100"; -- 4 s
constant YELLOW_TIME : std_logic_vector(7 downto 0) := "00000011"; -- 3 s
constant GREEN1_TIME : std_logic_vector(7 downto 0) := "00001110"; -- 14 s
constant GREEN2_TIME : std_logic_vector(7 downto 0) := "00001100"; -- 10 s
constant INTERMIT_MIN_TIME : std_logic_vector(7 downto 0) := "00000110"; -- 6 s
type TState is (TInit, TIntermit,
TRed1, TYellow1, TGreen1,
TRed2, TYellow2, TGreen2);
signal s_currentState, s_nextState : TState := TInit;
signal s_stateChanged : std_logic := '1';
begin
sync_proc : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
s_currentState <= TInit;
s_stateChanged <= '1';
else
if (s_currentState /= s_nextState) then
s_stateChanged <= '1';
else
s_stateChanged <= '0';
end if;
s_currentState <= s_nextState;
end if;
end if;
end process;
newTime <= s_stateChanged;
comb_proc : process(s_currentState, intermit, timeExp)
begin
case (s_currentState) is
when TInit =>
red1 <= '0';
yellow1 <= '0';
green1 <= '0';
red2 <= '0';
yellow2 <= '0';
green2 <= '0';
yBlink <= '0';
timeVal <= (others => '-');
s_nextState <= TIntermit;
when TIntermit =>
red1 <= '0';
yellow1 <= '1';
green1 <= '0';
red2 <= '0';
yellow2 <= '1';
green2 <= '0';
yBlink <= '1';
timeVal <= INTERMIT_MIN_TIME;
if ((intermit = '0') and (timeExp = '1')) then
s_nextState <= TRed1;
else
s_nextState <= TIntermit;
end if;
when TRed1 =>
red1 <= '1';
yellow1 <= '0';
green1 <= '0';
red2 <= '1';
yellow2 <= '0';
green2 <= '0';
yBlink <= '0';
timeVal <= RED_TIME;
if (timeExp = '1') then
if (intermit = '1') then
s_nextState <= TIntermit;
else
s_nextState <= TGreen2;
end if;
else
s_nextState <= TRed1;
end if;
when TYellow1 =>
red1 <= '0';
yellow1 <= '1';
green1 <= '0';
red2 <= '1';
yellow2 <= '0';
green2 <= '0';
yBlink <= '0';
timeVal <= YELLOW_TIME;
if (timeExp = '1') then
s_nextState <= TRed1;
else
s_nextState <= TYellow1;
end if;
when TGreen1 =>
red1 <= '0';
yellow1 <= '0';
green1 <= '1';
red2 <= '1';
yellow2 <= '0';
green2 <= '0';
yBlink <= '0';
timeVal <= GREEN1_TIME;
if (intermit = '1') or (timeExp = '1') then
s_nextState <= TYellow1;
else
s_nextState <= TGreen1;
end if;
when TRed2 =>
red1 <= '1';
yellow1 <= '0';
green1 <= '0';
red2 <= '1';
yellow2 <= '0';
green2 <= '0';
yBlink <= '0';
timeVal <= RED_TIME;
if (timeExp = '1') then
if (intermit = '1') then
s_nextState <= TIntermit;
else
s_nextState <= TGreen1;
end if;
else
s_nextState <= TRed2;
end if;
when TYellow2 =>
red1 <= '1';
yellow1 <= '0';
green1 <= '0';
red2 <= '0';
yellow2 <= '1';
green2 <= '0';
yBlink <= '0';
timeVal <= YELLOW_TIME;
if (timeExp = '1') then
s_nextState <= TRed2;
else
s_nextState <= TYellow2;
end if;
when TGreen2 =>
red1 <= '1';
yellow1 <= '0';
green1 <= '0';
red2 <= '0';
yellow2 <= '0';
green2 <= '1';
yBlink <= '0';
timeVal <= GREEN2_TIME;
if (intermit = '1') or (timeExp = '1') then
s_nextState <= TYellow2;
else
s_nextState <= TGreen2;
end if;
end case;
end process;
end Behavioral;
|
gpl-2.0
|
3e0a869492551363ef051e299d4be5a2
| 0.548784 | 2.575581 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 7/Parte 1/ControlUnit.vhd
| 1 | 1,711 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ControlUnit is
port(reset : in std_logic;
clk : in std_logic;
statop : in std_logic;
laprst : in std_logic;
cntReset : out std_logic;
cntEnable : out std_logic;
regEnable : out std_logic);
end ControlUnit;
architecture Behavioral of ControlUnit is
type TState is (TCleared, TStarted, TStopped, TLapView);
signal s_currentState, s_nextState : TState;
begin
sync_proc : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
s_currentState <= TCleared;
else
s_currentState <= s_nextState;
end if;
end if;
end process;
comb_proc : process(s_currentState, statop, laprst)
begin
case (s_currentState) is
when TCleared =>
cntReset <= '1';
cntEnable <= '1';
regEnable <= '1';
if (statop = '1') then
s_nextState <= TStarted;
else
s_nextState <= TCleared;
end if;
when TStarted =>
cntReset <= '0';
cntEnable <= '1';
regEnable <= '1';
if (statop = '1') then
s_nextState <= TStopped;
elsif (laprst = '1') then
s_nextState <= TLapView;
else
s_nextState <= TStarted;
end if;
when TStopped =>
cntReset <= '0';
cntEnable <= '0';
regEnable <= '1';
if (statop = '1') then
s_nextState <= TStarted;
elsif (laprst = '1') then
s_nextState <= TCleared;
else
s_nextState <= TStopped;
end if;
when TLapView =>
cntReset <= '0';
cntEnable <= '1';
regEnable <= '0';
if (laprst = '1') then
s_nextState <= TStarted;
elsif(statop='1') then
regEnable <= '1';
s_nextState <= TCleared;
else
s_nextState <= TLapView;
end if;
end case;
end process;
end Behavioral;
|
gpl-2.0
|
9c17680538c1921e35c0f5e65e69b2fd
| 0.604325 | 2.929795 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/MemoriaDeDatos.vhd
| 1 | 3,406 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoriaDeDatos is
--generic( P: integer:=32; -- ancho de palabra 32 bits
-- N: integer:=32; -- nº de palabras 32 de 32
--M: integer:= 64; -- grupos de 4 palabras (2^32 / 4)=1073741824
--tam_addr: integer:=5); -- ancho dirección 2^5=32
port( Clock: in std_logic;
ADDR, write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0);
DW: in std_logic_vector(31 downto 0);
R, W: in std_logic;
reg0: out std_logic_vector(31 downto 0);
reg1: out std_logic_vector(31 downto 0);
reg2: out std_logic_vector(31 downto 0);
reg3: out std_logic_vector(31 downto 0)
);
end MemoriaDeDatos;
architecture Behavioral of MemoriaDeDatos is
type mem_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal tmp_mem: mem_type:=(
"00000000000000010000000000100000",--suma
"00000000010000110000000000100000",
"00000000100001010000000000100000",
"00000000110001110000000000100000",
"00000001000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100010",--resta
"00000000000000010000000000100010",
"00000000000000010000000000100010",
"00000000000000010000000000100101",--or
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100100",--and
"00010000000000000000000000000011",--beq
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000");
begin
--registros
reg0 <= tmp_mem(conv_integer(0));
reg1 <= tmp_mem(conv_integer(1));
reg2 <= tmp_mem(conv_integer(2));
reg3 <= tmp_mem(conv_integer(3));
-- Lectura
process(Clock)
begin
if (Clock'event and Clock='1') then
if(R = '1') then
DR <= tmp_mem(conv_integer(ADDR));
else
DR <= (DR' range => 'Z');
end if;
end if;
end process;
-- Escritura
process(Clock)
begin
if (Clock'event and Clock='1') then
if(W = '1') then
tmp_mem(conv_integer(write_addr))<= DW;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
855fc0cbb5afb3348198fd14d8fb47c6
| 0.709043 | 4.083933 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/AC_CR_ROM.vhd
| 2 | 31,473 |
-------------------------------------------------------------------------------
-- File Name : AC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_CR_ROM
--
-- Content : AC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_CR_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_CR_ROM : process(CLK)
begin
if CLK'event and CLK = '1' then
case rom_addr is
when X"00" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"01" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"02" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"03" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"04" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11000", VLC_AC'length);
when X"05" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11001", VLC_AC'length);
when X"06" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111000", VLC_AC'length);
when X"07" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"08" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110100", VLC_AC'length);
when X"09" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"0A" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when X"11" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"12" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111001", VLC_AC'length);
when X"13" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11110110", VLC_AC'length);
when X"14" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110101", VLC_AC'length);
when X"15" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"16" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"17" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when X"18" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"19" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"1A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when X"21" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"22" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11110111", VLC_AC'length);
when X"23" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"24" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"25" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000010", VLC_AC'length);
when X"26" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"27" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"28" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when X"29" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"2A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when X"31" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"32" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"33" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"34" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"35" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"36" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"37" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"38" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"39" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when X"3A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when X"41" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"42" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"43" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"44" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"45" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"46" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"47" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"48" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"49" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when X"4A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when X"51" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"52" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"53" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"54" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"55" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"56" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"57" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"58" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"59" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when X"5A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when X"61" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"62" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"63" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"64" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"65" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"66" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"67" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"68" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"69" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when X"6A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when X"71" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"72" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"73" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"74" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"75" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"76" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"77" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"78" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"79" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when X"7A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when X"81" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"82" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"83" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"84" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"85" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"86" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"87" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"88" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when X"89" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"8A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when X"91" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"92" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"93" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"94" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"95" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"96" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"97" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"98" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when X"99" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"9A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when X"A1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"A2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"A3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"A4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"A5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"A6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"A7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"A8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when X"A9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"AA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when X"B1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"B2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"B3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"B4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"B5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"B6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"B7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"B8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when X"B9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"BA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when X"C1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"C2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"C3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"C4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"C5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"C6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"C7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"C8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when X"C9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"CA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when X"D1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"D2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"D3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"D4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"D5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"D6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"D7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"D8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when X"D9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"DA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when X"E1" =>
VLC_AC_size <= to_unsigned(14, VLC_AC_size'length);
VLC_AC <= resize("11111111100000", VLC_AC'length);
when X"E2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"E3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"E4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"E5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"E6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"E7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"E8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"E9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when X"EA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when X"F0" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"F1" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000011", VLC_AC'length);
when X"F2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"F3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"F4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"F5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"F6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"F7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"F8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"F9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"FA" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
eb39d149271f6967940a53c9879fecfc
| 0.464493 | 3.880764 | false | false | false | false |
vinodpa/openPowerlink-FPGA
|
Examples/ipcore/common/openmac/src/openMAC_DMAmaster.vhd
| 3 | 21,294 |
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
sync6 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_rd_len,
dataSrc => dma_new_rd_len,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
if toggle = '1' then
rx_wr_req_s <= '1';
end if;
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
|
gpl-2.0
|
aa873136bc095a6ec73daf793819110d
| 0.560017 | 3.100917 | false | false | false | false |
spoorcc/realtimestagram
|
src/hsv2rgb_tb.vhd
| 2 | 6,075 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
--======================================================================================--
entity hsv2rgb_tb is
generic (
input_file: string := "tst/output/rgb2hsv_smpte_bars.pnm"; --! Input file of test
output_file: string := "tst/output/hsv2rgb_output.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight --! Height of input image
);
end entity;
--======================================================================================--
architecture structural of hsv2rgb_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 5
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component hsv2rgb is
generic (
wordsize: integer := 8 --! input image wordsize in bits
);
port (
-- inputs
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_hue_i: in std_logic_vector;
pixel_sat_i: in std_logic_vector;
pixel_val_i: in std_logic_vector;
-- outputs
pixel_red_o: out std_logic_vector;
pixel_green_o: out std_logic_vector;
pixel_blue_o: out std_logic_vector
);
end component;
for device_under_test : hsv2rgb use entity work.hsv2rgb(bailey);
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: hsv2rgb
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_hue_i => red_pixel_from_file,
pixel_sat_i => green_pixel_from_file,
pixel_val_i => blue_pixel_from_file,
pixel_red_o => red_pixel_to_file,
pixel_green_o => green_pixel_to_file,
pixel_blue_o => blue_pixel_to_file
);
end architecture;
|
gpl-2.0
|
52000714715885115ab30a0881e499e0
| 0.489877 | 4.233449 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/ISAintfc.vhd
| 1 | 16,022 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : ISAintfc.vhf
-- /___/ /\ Timestamp : 01/05/2006 10:51:23
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w ISAintfc.sch ISAintfc.vhf
--Design Name: ISAintfc
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD_MXILINX_ISAintfc is
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end FD_MXILINX_ISAintfc;
architecture BEHAVIORAL of FD_MXILINX_ISAintfc is
attribute BOX_TYPE : string ;
signal XLXN_4 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component FDCP
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
begin
I_36_43 : GND
port map (G=>XLXN_4);
U0 : FDCP
port map (C=>C,
CLR=>XLXN_4,
D=>D,
PRE=>XLXN_4,
Q=>Q);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity D3_8E_MXILINX_ISAintfc is
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end D3_8E_MXILINX_ISAintfc;
architecture BEHAVIORAL of D3_8E_MXILINX_ISAintfc is
attribute BOX_TYPE : string ;
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
begin
I_36_30 : AND4
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D7);
I_36_31 : AND4B1
port map (I0=>A0,
I1=>A2,
I2=>A1,
I3=>E,
O=>D6);
I_36_32 : AND4B1
port map (I0=>A1,
I1=>A2,
I2=>A0,
I3=>E,
O=>D5);
I_36_33 : AND4B2
port map (I0=>A1,
I1=>A0,
I2=>A2,
I3=>E,
O=>D4);
I_36_34 : AND4B1
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>E,
O=>D3);
I_36_35 : AND4B2
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>E,
O=>D2);
I_36_36 : AND4B2
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D1);
I_36_37 : AND4B3
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD4CE_MXILINX_ISAintfc is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end FD4CE_MXILINX_ISAintfc;
architecture BEHAVIORAL of FD4CE_MXILINX_ISAintfc is
attribute BOX_TYPE : string ;
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
U0 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D0,
Q=>Q0);
U1 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D1,
Q=>Q1);
U2 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D2,
Q=>Q2);
U3 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D3,
Q=>Q3);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity ISAintfc is
port ( BRDSELO : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
IORN : in std_logic;
IOWN : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
SA3 : in std_logic;
SA4 : in std_logic;
PLLOUT : in std_logic;
A2DDATA : out std_logic;
A2DSTAT : out std_logic;
D2A0 : out std_logic;
D2A1 : out std_logic;
D2A2 : out std_logic;
FIFO : out std_logic;
FIFOSTAT : out std_logic;
IOCS16N : out std_logic;
I2CSCL : out std_logic;
LBSD3 : out std_logic;
SIOR : out std_logic;
SIORN : out std_logic;
SIORW : out std_logic;
SIOW : out std_logic;
SIOWN : out std_logic;
SYSCTL : out std_logic;
BSD : inout std_logic_vector (15 downto 0);
I2CSDA : inout std_logic);
end ISAintfc;
architecture BEHAVIORAL of ISAintfc is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal BRDSELI : std_logic;
signal FSEL : std_logic;
signal XLXN_157 : std_logic;
signal XLXN_158 : std_logic;
signal XLXN_159 : std_logic;
signal XLXN_161 : std_logic;
signal XLXN_206 : std_logic;
signal XLXN_210 : std_logic;
signal XLXN_212 : std_logic;
signal XLXN_214 : std_logic;
signal XLXN_216 : std_logic;
signal XLXN_221 : std_logic;
signal XLXN_222 : std_logic;
signal XLXN_370 : std_logic;
-- signal XLXN_223a : std_logic;
-- signal XLXN_223b : std_logic;
-- signal XLXN_223c : std_logic;
-- signal XLXN_223d : std_logic;
-- signal XLXN_223e : std_logic;
-- signal XLXN_223f : std_logic;
signal XLXN_225 : std_logic;
signal XLXN_229 : std_logic;
signal XLXN_230 : std_logic;
signal XLXN_231 : std_logic;
signal XLXN_232 : std_logic;
signal A2DSTAT_DUMMY : std_logic;
signal A2DDATA_DUMMY : std_logic;
signal SIOWN_DUMMY : std_logic;
signal SIOR_DUMMY : std_logic;
signal SIORN_DUMMY : std_logic;
signal SIOW_DUMMY : std_logic;
signal SIORW_DUMMY : std_logic;
signal D2A2_DUMMY : std_logic;
-- signal MY_SIORW : std_logic;
-- signal cnt : std_logic_vector(1 downto 0):="00";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component FD4CE_MXILINX_ISAintfc
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic);
end component;
component D3_8E_MXILINX_ISAintfc
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end component;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component NAND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
component NOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NOR2 : component is "BLACK_BOX";
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
component AND5
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component FD_MXILINX_ISAintfc
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of XLXI_60 : label is "XLXI_60_0";
attribute HU_SET of XLXI_61 : label is "XLXI_61_1";
attribute HU_SET of XLXI_102 : label is "XLXI_102_2";
attribute HU_SET of XLXI_103 : label is "XLXI_103_3";
begin
A2DSTAT <= A2DSTAT_DUMMY;
A2DDATA <= A2DDATA_DUMMY;
SIOR <= SIOR_DUMMY;
SIORN <= SIORN_DUMMY;
SIOW <= SIOW_DUMMY;
SIOWN <= SIOWN_DUMMY;
D2A2 <= D2A2_DUMMY;
XLXI_30 : INV
port map (I=>SIOW_DUMMY,
O=>SIOWN_DUMMY);
XLXI_143 : VCC
port map (P=>XLXN_370);
XLXI_60 : FD4CE_MXILINX_ISAintfc
port map (C=>SIOWN_DUMMY,
CE=>FSEL,
CLR=>XLXN_210,
D0=>BSD(0),
D1=>BSD(1),
D2=>BSD(2),
D3=>BSD(3),
Q0=>XLXN_157,
Q1=>XLXN_158,
Q2=>XLXN_159,
Q3=>LBSD3);
XLXI_61 : D3_8E_MXILINX_ISAintfc
port map (A0=>XLXN_157,
A1=>XLXN_158,
A2=>XLXN_159,
E=>XLXN_206,
D0=>FIFO,
D1=>A2DSTAT_DUMMY,
D2=>A2DDATA_DUMMY,
D3=>D2A0,
D4=>D2A1,
D5=>D2A2_DUMMY,
D6=>SYSCTL,
D7=>FIFOSTAT);
XLXI_63 : GND
port map (G=>XLXN_210);
XLXI_66 : NAND2
port map (I0=>SIORN_DUMMY,
I1=>SIOWN_DUMMY,
O=>SIORW);
XLXI_69 : INV
port map (I=>SIOR_DUMMY,
O=>SIORN_DUMMY);
XLXI_75 : NOR2
port map (I0=>IOWN,
I1=>BRDSELO,
O=>SIOW_DUMMY);
XLXI_76 : NOR2
port map (I0=>IORN,
I1=>BRDSELO,
O=>SIOR_DUMMY);
XLXI_80 : BUFE
port map (E=>BRDSELI,
I=>XLXN_161,
O=>IOCS16N);
XLXI_81 : INV
port map (I=>BRDSELO,
O=>BRDSELI);
XLXI_82 : GND
port map (G=>XLXN_161);
XLXI_89 : INV
port map (I=>XLXN_229,
O=>XLXN_232);
XLXI_90 : INV
port map (I=>FSEL,
O=>XLXN_206);
XLXI_91 : AND2
port map (I0=>XLXN_232,
I1=>XLXN_221,
O=>XLXN_231);
XLXI_92 : AND5
port map (I0=>BRDSELI,
I1=>SA3,
I2=>SA2,
I3=>SA1,
I4=>SA0, --Uncomment for Viper
-- I4=>SA4, --Uncomment for Vulcan
O=>FSEL);
XLXI_93 : AND2
-- port map (I0=>FIFOCTL(1),
-- I1=>A2DSTAT_DUMMY,
-- port map (I0=>FIFOCTL(7),
-- I1=>D2A2_DUMMY,
port map (I0=>A2DDATA_DUMMY,
I1=>A2DDATA_DUMMY,
O=>XLXN_230);
XLXI_94 : AND2
port map (I0=>SIOR_DUMMY,
I1=>XLXN_230,
O=>XLXN_229);
XLXI_95 : NAND2
port map (I0=>SIOW_DUMMY,
I1=>XLXN_230,
O=>XLXN_216);
XLXI_96 : INV
port map (I=>BSD(0),
O=>XLXN_212);
XLXI_97 : INV
port map (I=>BSD(1),
O=>XLXN_214);
XLXI_98 : INV
port map (I=>XLXN_221,
O=>XLXN_222);
XLXI_99 : INV
port map (I=>XLXN_225,
O=>I2CSCL);
XLXI_100 : BUFE
port map (E=>XLXN_229,
I=>I2CSDA,
O=>BSD(0));
XLXI_101 : BUFE
port map (E=>XLXN_231,
I=>XLXN_222,
O=>I2CSDA);
XLXI_102 : FD_MXILINX_ISAintfc
port map (C=>XLXN_216,
D=>XLXN_212,
Q=>XLXN_221);
XLXI_103 : FD_MXILINX_ISAintfc
port map (C=>XLXN_216,
D=>XLXN_214,
Q=>XLXN_225);
-- delay: process(pllout,FSEL)
-- begin
-- if FSEL = '1' then
-- cnt <= "00";
-- elsif cnt = "00" and FSEL = '0' then
-- cnt <= "01";
-- elsif cnt = "01" and FSEL = '0' then
-- cnt <= "10";
-- else
-- cnt <= cnt;
-- end if;
-- end process delay;
end BEHAVIORAL;
|
gpl-2.0
|
18f75311f30b31100e26b6f13f57ec92
| 0.454875 | 3.458981 | false | false | false | false |
jpcofr/PDUAMaude
|
PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/banco.vhdl
| 1 | 2,589 |
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: BANCO **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- Banco de registros
-- reset_n HR (Habilitador)
-- _|___|_
-- clk -->| PC |
-- | SP |
-- | DPTR |
-- | A |--> BUSB
-- BUSC -->| VI |--> BUSA
-- | CTE1 |
-- | ACC |
-- |_______|
-- | |
-- SC SB
-- Selector de destino Selector de Origen
-- reg <--BUSC BUSB <-- reg
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity banco is
Port ( CLK : in std_logic;
RESET_n: in std_logic;
HR : in std_logic;
SC,SB : in std_logic_vector(2 downto 0);
BUSC : in std_logic_vector(7 downto 0);
BUSA,BUSB : out std_logic_vector(7 downto 0)
);
end banco;
architecture Behavioral of banco is
SIGNAL PC,SP,DPTR,A,VI,TEMP,CTE1,ACC : std_logic_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '0') then
if RESET_n = '0' then
PC <= "00000000";
SP <= "10000000"; -- Primera posición de RAM
DPTR <= "00000000";
A <= "00000000";
VI <= "00000010"; -- Vector de Interrupcion
TEMP <= "00000000";
CTE1 <= "11111111"; -- Constante Menos 1 (Compl. a 2)
ACC <= "00000000";
elsif HR = '1' then
case SC is
when "000" => PC <= BUSC;
when "001" => SP <= BUSC;
when "010" => DPTR <= BUSC;
when "011" => A <= BUSC;
-- when "100" => B <= BUSC; -- B es constante (vector de Int)
when "101" => TEMP <= BUSC;
-- when "110" => CTE 1 -- Es constante (menos 1)
when "111" => ACC <= BUSC;
when others => CTE1 <= "11111111";
end case;
end if;
end if;
end process;
process(SB,PC,SP,DPTR,A,VI,TEMP,ACC)
begin
case SB is
when "000" => BUSB <= PC;
when "001" => BUSB <= SP;
when "010" => BUSB <= DPTR;
when "011" => BUSB <= A;
when "100" => BUSB <= VI;
when "101" => BUSB <= TEMP;
when "110" => BUSB <= CTE1;
when "111" => BUSB <= ACC;
when others=> BUSB <= ACC;
end case;
end process;
BUSA <= ACC;
end Behavioral;
|
mit
|
4c08de16ee085b3b839eab4f239034e9
| 0.439938 | 3.212159 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/bus_wb8_tb.vhd
| 1 | 4,670 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_wb8_tb is
end bus_wb8_tb;
architecture Behavior of bus_wb8_tb is
component bus_wb8
Port(
I_en: in std_logic;
I_op: in busops_t; -- memory opcodes
I_addr: in std_logic_vector(31 downto 0); -- address
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic := '0';
-- wired to outside world, RAM, devices etc.
-- naming of signals taken from Wishbone B4 spec
CLK_I: in std_logic := '0';
ACK_I: in std_logic := '0';
DAT_I: in std_logic_vector(7 downto 0);
RST_I: in std_logic := '0';
ADR_O: out std_logic_vector(31 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
CYC_O: out std_logic := '0';
STB_O: out std_logic := '0';
WE_O: out std_logic := '0'
);
end component;
signal I_en: std_logic;
signal I_op: busops_t; -- memory opcodes
signal I_addr: std_logic_vector(31 downto 0); -- address
signal I_data: std_logic_vector(31 downto 0); -- data to be stored on write ops
signal O_data: std_logic_vector(31 downto 0);
signal O_busy: std_logic := '0';
signal O_clk: std_logic := '0';
signal O_reset: std_logic := '0';
signal CLK_I: std_logic := '0';
signal ACK_I: std_logic := '0';
signal DAT_I: std_logic_vector(7 downto 0);
signal RST_I: std_logic := '0';
signal ADR_O: std_logic_vector(31 downto 0);
signal DAT_O: std_logic_vector(7 downto 0);
signal CYC_O: std_logic := '0';
signal STB_O: std_logic := '0';
signal WE_O: std_logic := '0';
constant I_clk_period : time := 10 ns;
begin
uut: bus_wb8 port map(
I_en => I_en,
I_op => I_op,
I_addr => I_addr,
I_data => I_data,
O_data => O_data,
O_busy => O_busy,
CLK_I => CLK_I,
ACK_I => ACK_I,
DAT_I => DAT_I,
RST_I => RST_I,
ADR_O => ADR_O,
DAT_O => DAT_O,
CYC_O => CYC_O,
STB_O => STB_O,
WE_O => WE_O
);
proc_clock: process
begin
CLK_I <= '0';
wait for I_clk_period/2;
CLK_I <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- test read of words
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READW;
DAT_I <= X"CC";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"CCCCCCCC" report "wrong data read" severity failure;
I_en <= '0';
-- test read of half words and sign extension (here: sign set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READH;
DAT_I <= X"CC";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"FFFFCCCC" report "wrong data read" severity failure;
I_en <= '0';
-- test read of half words and sign extension (here sign not set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READH;
DAT_I <= X"0F";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"00000F0F" report "wrong data read" severity failure;
I_en <= '0';
-- test read of byte and sign extension (here: sign set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READB;
DAT_I <= X"CC";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"FFFFFFCC" report "wrong data read" severity failure;
I_en <= '0';
-- test read of byte and sign extension (here sign not set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READB;
DAT_I <= X"0F";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"0000000F" report "wrong data read" severity failure;
I_en <= '0';
-- test writing a word
wait until falling_edge(CLK_I);
I_en <= '1';
I_data <= X"CAFEBABE";
I_addr <= X"CAFE0000";
I_op <= BUS_WRITEW;
ACK_I <= '1';
wait until falling_edge(O_busy);
assert DAT_O = X"CA" report "wrong data written" severity failure;
I_en <= '0';
-- test writing a half word
wait until falling_edge(CLK_I);
I_en <= '1';
I_data <= X"CAFEBABE";
I_addr <= X"CAFE0000";
I_op <= BUS_WRITEH;
ACK_I <= '1';
wait until falling_edge(O_busy);
assert DAT_O = X"BA" report "wrong data written" severity failure;
I_en <= '0';
-- test writing a byte
wait until falling_edge(CLK_I);
I_en <= '1';
I_data <= X"CAFEBABE";
I_addr <= X"CAFE0000";
I_op <= BUS_WRITEB;
ACK_I <= '1';
wait until falling_edge(O_busy);
assert DAT_O = X"BE" report "wrong data written" severity failure;
I_en <= '0';
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
eccb2964aed082f69f377d7618be07b6
| 0.610064 | 2.573003 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Counter9999.vhd
| 1 | 1,886 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter9999 is
port( clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count0 : out std_logic_vector(3 downto 0);
count1 : out std_logic_vector(3 downto 0);
count2 : out std_logic_vector(3 downto 0);
count3 : out std_logic_vector(3 downto 0));
end Counter9999;
-- Contador com enable e reset, de 0 a 9999.
-- Necessário para gerar número pseudo-aleatório.
architecture Behavioral of Counter9999 is
signal s_count0, s_count1, s_count2, s_count3 : unsigned (3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(not(s_count0(0)='0') and not(s_count0(0)='1')) then
s_count0 <= (others => '0');
s_count1 <= (others => '0');
s_count2 <= (others => '0');
s_count3 <= (others => '0');
elsif(reset='1') then
s_count0 <= (others => '0');
s_count1 <= (others => '0');
s_count2 <= (others => '0');
s_count3 <= (others => '0');
elsif (enable = '0') then
s_count0 <= s_count0;
s_count1 <= s_count1;
s_count2 <= s_count2;
s_count3 <= s_count3;
else
if (s_count0="1001") then
s_count0 <= "0000";
if(s_count1 = "1001") then
s_count1 <= "0000";
if(s_count2 = "1001") then
s_count2 <= "0000";
if(s_count3 = "1001") then
s_count3 <= "0000";
else
s_count3 <= s_count3 + 1;
end if;
else
s_count2 <= s_count2 + 1;
end if;
else
s_count1 <= s_count1 + 1;
end if;
else
s_count0 <= s_count0 + 1;
end if;
end if;
end if;
end process;
count0 <= std_logic_vector(s_count0);
count1 <= std_logic_vector(s_count1);
count2 <= std_logic_vector(s_count2);
count3 <= std_logic_vector(s_count3);
end Behavioral;
|
gpl-2.0
|
a4bd317d4f457ca63452f74e9b0df61e
| 0.583643 | 2.608033 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AluDemoex5.vhd
| 1 | 1,485 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity AluDemoex5 is
port( SW : in std_logic_vector(17 downto 0);
LEDR: out std_logic_vector(7 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0));
end AluDemoex5;
architecture Structural of AluDemoex5 is
signal s, m, i1, i2, i3, i4 : std_logic_vector(3 downto 0);
begin
Alu4: entity work.AluN(Behavioral)
generic map(N => 4)
port map(a => SW(7 downto 4),
b => SW(3 downto 0),
op => SW(17 downto 15),
m => LEDR(7 downto 4),
r2 => s,
r => LEDR(3 downto 0),
m2 => m);
Bin2BCDm: entity work.Bin2BCD(Behavioral)
port map(inBin => m,
outBCD =>i1,
outBCD2=>i2);
Bin2BCDr: entity work.Bin2BCD(Behavioral)
port map(inBin => s,
outBCD => i3,
outBCD2=> i4);
Bin7SecDec: entity work.Bin7SecDec(Behavioral)
port map(binInput => i1,
decOut_n => HEX7(6 downto 0));
Bin7SecDec2: entity work.Bin7SecDec(Behavioral)
port map(binInput => i2,
decOut_n => HEX6(6 downto 0));
Bin7SecDec3: entity work.Bin7SecDec(Behavioral)
port map(binInput => i3,
decOut_n => HEX5(6 downto 0));
Bin7SecDec4: entity work.Bin7SecDec(Behavioral)
port map(binInput => i4,
decOut_n => HEX4(6 downto 0));
end Structural;
|
gpl-2.0
|
7e18480de363d618fcf94aef1abe292d
| 0.608754 | 2.817837 | false | false | false | false |
tejainece/VHDLExperiments
|
Multiply16Booth4/Multiply16Booth4.vhd
| 1 | 3,756 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:23 01/22/2014
-- Design Name:
-- Module Name: Multiply16Booth4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(31 downto 0));
end Multiply16Booth4;
architecture Behavioral of Multiply16Booth4 is
COMPONENT BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end COMPONENT;
COMPONENT BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end COMPONENT;
SIGNAL aTmp: STD_LOGIC_VECTOR(16 downto 0);
SIGNAL oTmp: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL prod0: STD_LOGIC_VECTOR(19 downto 0);
SIGNAL prod1: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod2: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod3: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod4: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod5: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod6: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod7: STD_LOGIC_VECTOR(17 downto 0);
begin
aTmp <= a & '0';
prod0(19 downto 17) <= (not prod0(16)) & prod0(16) & prod0(16);
prod1(18 downto 17) <= '1' & (not prod1(16));
prod2(18 downto 17) <= '1' & (not prod2(16));
prod3(18 downto 17) <= '1' & (not prod3(16));
prod4(18 downto 17) <= '1' & (not prod4(16));
prod5(18 downto 17) <= '1' & (not prod5(16));
prod6(18 downto 17) <= '1' & (not prod6(16));
prod7(17) <= not prod7(16);
prodgen0: BoothPartProdGen PORT MAP (
bin3 => aTmp(2 downto 0),
a => b,
product => prod0(16 downto 0)
);
prodgen1: BoothPartProdGen PORT MAP (
bin3 => aTmp(4 downto 2),
a => b,
product => prod1(16 downto 0)
);
prodgen2: BoothPartProdGen PORT MAP (
bin3 => aTmp(6 downto 4),
a => b,
product => prod2(16 downto 0)
);
prodgen3: BoothPartProdGen PORT MAP (
bin3 => aTmp(8 downto 6),
a => b,
product => prod3(16 downto 0)
);
prodgen4: BoothPartProdGen PORT MAP (
bin3 => aTmp(10 downto 8),
a => b,
product => prod4(16 downto 0)
);
prodgen5: BoothPartProdGen PORT MAP (
bin3 => aTmp(12 downto 10),
a => b,
product => prod5(16 downto 0)
);
prodgen6: BoothPartProdGen PORT MAP (
bin3 => aTmp(14 downto 12),
a => b,
product => prod6(16 downto 0)
);
prodgen7: BoothPartProdGen PORT MAP (
bin3 => aTmp(16 downto 14),
a => b,
product => prod7(16 downto 0)
);
output: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => oTmp
);
o <= oTmp(31 downto 0);
end Behavioral;
|
gpl-3.0
|
21a8a9e5df3e3bef24327587459ce73f
| 0.624334 | 3.048701 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 4/Parte III/CounterUpDown4.vhd
| 1 | 618 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterUpDown4 is
port( clk : in std_logic;
updown: in std_logic;
reset : in std_logic;
count : out std_logic_vector(3 downto 0));
end CounterUpDown4;
architecture Behavioral of CounterUpDown4 is
signal s_count : unsigned (3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
s_count <= (others => '0');
elsif (updown = '1') then
s_count <= s_count + 1;
else
s_count <= s_count - 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;
|
gpl-2.0
|
a71d045f8ce20f796a7bcaf079922897
| 0.656958 | 2.734513 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/spi/spirom_wb8.vhd
| 1 | 2,506 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spirom_wb8 is
Port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- SPI signal lines
I_spi_miso: in std_logic := '0';
O_spi_sel: out std_logic := '1';
O_spi_clk: out std_logic := '0';
O_spi_mosi: out std_logic := '0'
);
end spirom_wb8;
architecture Behavioral of spirom_wb8 is
signal tx_data, rx_data: std_logic_vector(7 downto 0) := X"00";
signal tx_start: boolean := false;
signal spi_busy: boolean := true;
begin
spimaster_instance: entity work.spimaster port map(
I_clk => CLK_I,
I_tx_data => tx_data,
I_tx_start => tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => rx_data,
O_busy => spi_busy
);
process(CLK_I)
type ctrlstates is (IDLE, OPCODE, ADDR1, ADDR2, ADDR3, READ1, READ2, WAITSTATE, TX1, TX2);
variable state, retstate: ctrlstates := IDLE;
variable doack: std_logic := '0';
begin
if rising_edge(CLK_I) then
doack := '0';
O_spi_sel <= '0'; -- select device
case state is
when IDLE =>
O_spi_sel <= '1'; -- deselect device
if not spi_busy and STB_I = '1' then
state := OPCODE;
end if;
when OPCODE =>
tx_data <= X"03";
state := TX1;
retstate := ADDR1;
when ADDR1 =>
tx_data <= ADR_I(23 downto 16);
state := TX1;
retstate := ADDR2;
when ADDR2 =>
tx_data <= ADR_I(15 downto 8);
state := TX1;
retstate := ADDR3;
when ADDR3 =>
tx_data <= ADR_I(7 downto 0);
state := TX1;
retstate := READ1;
when READ1 =>
tx_data <= X"00";
state := TX1;
retstate := READ2;
when READ2 =>
doack := '1';
state := WAITSTATE;
when WAITSTATE =>
state := IDLE;
when TX1 =>
-- signal beginning of transmission
tx_start <= true;
-- wait for ack that transmission is in progress
if spi_busy then
state := TX2;
end if;
when TX2 =>
tx_start <= false;
-- wait until transmission has ended
if not spi_busy then
state := retstate;
end if;
end case;
end if;
DAT_O <= rx_data;
ACK_O <= doack and STB_I;
end process;
end Behavioral;
|
mit
|
11a2185003d2beb5610dc2c12bf9f82b
| 0.57063 | 2.857469 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Debouncer.vhd
| 1 | 639 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Debouncer is
generic (N : positive);
port (clk : in std_logic;
dirty_In : in std_logic;
cleanOut : out std_logic);
end Debouncer;
-- Debouncer simples
architecture Behavioral of Debouncer is
signal s_dirty_In : std_logic_vector(N downto 1);
begin
process(clk, dirty_In)
begin
if(dirty_In='0') then
s_dirty_In <= (others => '0');
elsif(rising_edge(clk)) then
s_dirty_In <= '1' & s_dirty_In(N downto 2);
end if;
cleanOut <= s_dirty_In(N);
end process;
end Behavioral;
|
gpl-2.0
|
2b737f944f705f9d9b0b47401137a6b9
| 0.665102 | 2.827434 | false | false | false | false |
spoorcc/realtimestagram
|
src/sepia_testsets_tb.vhd
| 2 | 2,843 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
entity sepia_testsets_tb is
end entity;
architecture all_tests of sepia_testsets_tb is
constant threshold: integer := 220;
component sepia_tb is
generic (
input_file: string; --! Input file of test
output_file: string; --! Output file of test
sepia_threshold: integer
);
end component;
begin
Lenna: sepia_tb
generic map(
input_file => "tst/input/lenna.pnm",
output_file => "tst/output/sepia_lenna.pnm",
sepia_threshold => threshold
);
windmill: sepia_tb
generic map(
input_file => "tst/input/windmill.pnm",
output_file => "tst/output/sepia_windmill.pnm",
sepia_threshold => threshold
);
danger_zone: sepia_tb
generic map(
input_file => "tst/input/danger_zone.pnm",
output_file => "tst/output/sepia_danger_zone.pnm",
sepia_threshold => threshold
);
amersfoort: sepia_tb
generic map(
input_file => "tst/input/amersfoort.pnm",
output_file => "tst/output/sepia_amersfoort.pnm",
sepia_threshold => threshold
);
rainbow: sepia_tb
generic map(
input_file => "tst/input/rainbow.pnm",
output_file => "tst/output/sepia_rainbow.pnm",
sepia_threshold => threshold
);
hue_gradient: sepia_tb
generic map(
input_file => "tst/input/hue_gradient.pnm",
output_file => "tst/output/sepia_hue_gradient.pnm",
sepia_threshold => threshold
);
sat_gradient: sepia_tb
generic map(
input_file => "tst/input/sat_gradient.pnm",
output_file => "tst/output/sepia_sat_gradient.pnm",
sepia_threshold => threshold
);
val_gradient: sepia_tb
generic map(
input_file => "tst/input/val_gradient.pnm",
output_file => "tst/output/sepia_val_gradient.pnm",
sepia_threshold => threshold
);
end architecture;
|
gpl-2.0
|
742d98ec01a432d91212c15ce32009e2
| 0.591629 | 4.174743 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/checkEnd.vhd
| 1 | 2,334 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity checkEnd is
port( try0 : in std_logic_vector(3 downto 0);
try1 : in std_logic_vector(3 downto 0);
cert : in std_logic_vector(3 downto 0);
erra : in std_logic_vector(3 downto 0);
clock : in std_logic;
reset : in std_logic;
isBlink : out std_logic;
isend : out std_logic;
p : out std_logic_vector(3 downto 0);
n : out std_logic_vector(3 downto 0);
t1 : out std_logic_vector(3 downto 0);
t0 : out std_logic_vector(3 downto 0);
b_load : out std_logic);
end checkEnd;
-- Entidade que possui máquina de estados que faz atribuições essenciais para sinalização de saídas.
architecture Behavioral of checkEnd is
type Tstate is (S0, S1, S2, S3);
signal pState, nState : Tstate := S0;
signal s_p, s_n : std_logic_vector(3 downto 0) := "0000";
signal final_try1, final_try0 :std_logic_vector(3 downto 0);
signal load : std_logic;
begin
clk_proc:process(clock, reset)
begin
if(reset = '1') then
pState <= S0;
final_try0 <= (others => '0');
final_try1 <= (others => '0');
elsif(rising_edge(clock)) then
if(load = '1') then
final_try0 <= try0;
final_try1 <= try1;
end if;
pState <= nState;
end if;
end process;
compare_proc:process(pState, cert, erra, try0, try1)
begin
b_load <= '1';
load <= '1';
case pState is
when S0 =>
b_load <= '1';
isblink <= '0';
t1 <= "1111";
t0 <= "1111";
isend <= '0';
nState <= S3;
when S1 =>
isblink <= '1';
t1 <= final_try1;
t0 <= final_try0;
s_p <= "0100";
s_n <= "0000";
load <= '0';
isend <= '0';
b_load <= '0';
nState <= S1;
when S2 =>
s_p <= "0000";
s_n <= "0000";
isend <= '1';
isBlink <= '0';
t1 <= "1001";
t0 <= "1001";
nState <= S2;
when S3 =>
s_p <= cert;
s_n <= erra;
t1 <= "1111";
t0 <= "1111";
isend <= '0';
isblink <= '0';
if(s_p = "0100") then
t1 <= try1;
t0 <= try0;
isblink <= '1';
nState <= S1;
b_load <= '0';
load <= '1';
elsif(try1 = "1001" and try0 = "1001") then
nState <= S2;
else
nState <= S3;
end if;
when others =>
nState <= S0;
end case;
end process;
p <= s_p;
n <= s_n;
end Behavioral;
|
gpl-2.0
|
caae6173d0ca4f014930e7a1a1589f87
| 0.560137 | 2.460888 | false | false | false | false |
miree/vhdl_cores
|
tdc/delayline_tb.vhd
| 1 | 3,430 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delayline_tb is
end entity;
architecture simulation of delayline_tb is
constant clk_period : time := 20 ns;
-- generics for the device under test
--constant test_depth : integer := 7; -- delay length of 2^3
--constant test_bit_width : integer := 8;
-- signals to connect to fifo
signal clk : std_logic;
signal rst : std_logic;
signal async : std_logic;
signal line_result : std_logic_vector (63 downto 0) := (others => '0');
signal send_data : std_logic_vector (127 downto 0) := (others => '0');
signal edge_detected : std_logic;
signal pop : std_logic;
signal fifo_out : std_logic_vector (7 downto 0) := (others => '0');
signal full, empty : std_logic;
signal counter : unsigned (63 downto 0) := (others => '0');
begin
--fifo : entity work.fifo
-- generic map (
-- depth => 6,
-- bit_width => 64
-- )
-- port map (
-- clk_i => clk,
-- rst_i => rst,
-- push_i => edge_detected,
-- pop_i => pop,
-- full_o => full,
-- empty_o => empty,
-- d_i => line_result,
-- q_o => fifo_out
-- );
serial : entity work.serializer
generic map (
in_width => 2*64,
out_width => 8,
depth => 4
)
port map (
clk_i => clk,
rst_i => rst,
push_i => edge_detected,
pop_i => pop,
full_o => full,
empty_o => empty,
d_i => send_data,
q_o => fifo_out
);
send_data <= std_logic_vector(counter) & line_result;
-- instantiate device under test (dut)
dut : entity work.delayline
generic map (
length => 64
)
port map (
clk_i => clk,
rst_i => rst,
async_i => async,
line_o => line_result,
signal_o => edge_detected
);
count: process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
clk_gen: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
rst_initial: process
begin
rst <= '1';
wait for clk_period*20;
rst <= '0';
wait;
end process;
async_gen: process
begin
async <= '0';
wait for 403.4 ns;
async <= not async;
wait for 5.2 ns;
async <= not async;
wait for 201.1 ns;
async <= not async;
wait for 47.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 77.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 47.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 77.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 47.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait for 77.6 ns;
async <= not async;
wait for 7.6 ns;
async <= not async;
wait;
end process;
pop <= not empty;
--pop_gen: process
--begin
-- pop <= '0';
-- wait for 610 ns;
-- pop <= '1';
-- wait;
--end process;
end architecture;
|
mit
|
df8040d833fa3e0b7bfefe4b17e0dc88
| 0.52449 | 3.285441 | false | false | false | false |
miree/vhdl_cores
|
fifo/slow_read_fifo/guarded_fifo.vhd
| 1 | 4,913 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity guarded_fifo is
generic (
depth : integer;
bit_width : integer
);
port (
-- fast side interface
clk_fast_i : in std_logic;
rst_fast_i : in std_logic;
push_i : in std_logic;
full_o : out std_logic;
d_i : in std_logic_vector ( bit_width-1 downto 0 );
-- slow side interface
clk_i : in std_logic;
rst_i : in std_logic;
dack_i : in std_logic;
drdy_o : out std_logic;
q_o : out std_logic_vector ( bit_width-1 downto 0 )
);
end entity;
-- Take a non-guarded fifo and take control over the
-- push and pull lines and prevent illegal operations.
-- Forward the full and empty signals.
use work.fifo_pkg.all;
architecture rtl of guarded_fifo is
-- fast side signal
type fast_state_t is (s_idle, s_getting_data_pop, s_getting_data_nopop, s_getting_data_latch, s_providing_data, s_start_pop, s_unknown);
signal full, empty, push, pop : std_logic;
signal pop_request_sync, pop_request_sync_1 : std_logic;
signal q, fifo_out_data_fast : std_logic_vector ( bit_width-1 downto 0 );
signal data_ready : std_logic;
signal state, next_state : fast_state_t;
-- slow side signals
type slow_state_t is (s_block, s_noblock);
signal data_ready_sync, data_ready_sync_1 : std_logic;
signal data_ready_block : std_logic;
signal fifo_out_data_slow : std_logic_vector ( bit_width-1 downto 0 );
signal slow_state : slow_state_t;
begin
-- the fifo is located on the fast side
fifo : work.fifo_pkg.fifo
generic map (
depth => depth,
bit_width => bit_width
)
port map (
clk_i => clk_fast_i,
rst_i => rst_fast_i,
push_i => push,
pop_i => pop,
full_o => full,
empty_o => empty,
d_i => d_i,
q_o => q
);
-- fast side interface of this module can be forwarded directly to the fifo
full_o <= full;
push <= push_i and not full;
-- the fast side process has a state machine that manages popping data from the fifo if it is available
--
fast_side: process
begin
wait until rising_edge(clk_fast_i);
if rst_fast_i = '1' then
state <= s_idle;
next_state <= s_idle;
fifo_out_data_fast <= (others => 'U');
data_ready <= '0';
else
-- signal synchroinzation on the fast side (look at slow signals)
pop_request_sync_1 <= dack_i; -- data acknowledge => we make a pop request to the underlying fifo
pop_request_sync <= pop_request_sync_1;
fifo_out_data_fast <= fifo_out_data_fast;
-- managing state machine
case state is
when s_idle =>
if empty = '0' and pop_request_sync = '0' then
state <= s_getting_data_pop;
else
state <= s_idle;
end if;
-- create a single pulse to get next data
when s_getting_data_pop =>
if empty = '1' then
state <= s_idle;
else
pop <= '1';
state <= s_getting_data_nopop;
end if;
when s_getting_data_nopop =>
pop <= '0';
data_ready <= '1';
state <= s_getting_data_latch;
when s_getting_data_latch =>
state <= s_providing_data;
fifo_out_data_fast <= q;
data_ready <= '1';
when s_providing_data =>
if pop_request_sync = '1' then
state <= s_start_pop;
data_ready <= '0';
end if;
when s_start_pop =>
if pop_request_sync = '0' then
state <= s_idle;
end if;
when others => state <= s_unknown;
end case;
end if;
end process;
slow_side: process
begin
wait until rising_edge(clk_i);
if rst_i = '1' then
drdy_o <= '0';
data_ready_sync_1 <= '0';
data_ready_sync <= '0';
q_o <= (others => 'U');
data_ready_block <= '0';
slow_state <= s_noblock;
else
-- signal synchronization on the slow side (looking at fast signals)
data_ready_sync_1 <= data_ready;
data_ready_sync <= data_ready_sync_1;
drdy_o <= data_ready_sync and not data_ready_block;
if data_ready_sync = '1' then
q_o <= fifo_out_data_fast;
end if;
case slow_state is
when s_noblock =>
if dack_i = '1' then
slow_state <= s_block;
data_ready_block <= '1';
end if;
when s_block =>
if data_ready_sync = '1' and data_ready_sync_1 = '0' then
slow_state <= s_noblock;
data_ready_block <= '0';
end if;
end case;
end if;
end process;
end architecture;
|
mit
|
357c30a0d3c6791b056b2fb7545c94a3
| 0.537553 | 3.472085 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/MIPSX.vhd
| 2 | 1,980 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:14 12/14/2012
-- Design Name:
-- Module Name: MIPSX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MIPSX is
port (clk, reset : in std_logic;
sal: out std_logic_vector(31 downto 0)
);
end MIPSX;
architecture Behavioral of MIPSX is
signal Estado, Sig_Estado: Estados;
--Señales PC
signal tempPC: std_logic_vector(31 downto 0);
signal PC: std_logic_vector(31 downto 0);
signal loadPC: std_logic;
begin
sal<=PC;
Síncrono: process(clk, reset)
begin
if reset='1' then
Estado<=F;
elsif clk'event and clk ='1' then
Estado<=Sig_Estado;
if loadPC='1' then
PC<=tempPC;
end if;
end if;
end process Síncrono;
Combinacional:process(Estado)
begin
case Estado is
when F =>
loadPC<='1';
tempPC<=X"00000000";
Sig_Estado <= ID;
when ID =>
loadPC<='0';
tempPC<=X"00000001";
Sig_Estado <= EX;
when EX =>
loadPC<='0';
tempPC<=X"0000000B";
Sig_Estado <= MEM;
when MEM =>
loadPC<='1';
tempPC<=X"0000000A";
Sig_Estado <= WB;
when WB =>
loadPC<='1';
tempPC<=X"FFFFFFFF";
Sig_Estado <= F;
end case;
end process Combinacional;
end Behavioral;
|
gpl-2.0
|
ca66c8eb34d77d54b5f5802a4ca63a71
| 0.561111 | 3.461538 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/rgbctrl/rgbctrl_wb8.vhd
| 1 | 4,673 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
use work.rgbctrl_wb8_init.all;
entity rgbctrl_wb8 is
generic(
CLOCKFREQ: integer := (50 * 1000 * 1000) -- frequency (MHz)
);
-- signal naming according to Wishbone B4 spec
port(
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_I: in std_logic_vector(7 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- RGB control signal
O_rgb_ctrl: out std_logic
);
end rgbctrl_wb8;
architecture Behavioral of rgbctrl_wb8 is
signal ram: store_t := RAM_INIT;
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
constant TCL: integer := (1000 * 1000 * 1000) / CLOCKFREQ; -- time per clock interval (ns)
-- timing for ws8212b
constant T0H: integer := 400; -- high time for 0 bit (ns)
constant T0L: integer := 800; -- low time for 0 bit (ns)
constant T1H: integer := 800; -- high time for 1 bit (ns)
constant T1L: integer := 400; -- low time for 1 bit (ns)
constant RES: integer := 60000; -- reset time (ns)
constant T0H_CLKS: integer := T0H / TCL; -- clock cycles for 0 bit, high
constant T0L_CLKS: integer := T0L / TCL; -- clock cycles for 0 bit, low
constant T1H_CLKS: integer := T1H / TCL; -- clock cycles for 1 bit, high
constant T1L_CLKS: integer := T1L / TCL; -- clock cycles for 1 bit, low
constant RES_CLKS: integer := RES / TCL; -- clock cycles for reset, low
-- counter to keep track of byte address in RAM
signal next_rgb_addr: integer range 0 to ((2**ADDRLEN) - 1) := 0;
-- register to keep RGB-byte to be serialized
signal next_rgb_byte: std_logic_vector(7 downto 0) := X"00";
begin
-- process to generate RGB control signal
process(CLK_I)
-- clock counter for timing
variable clkcounter: integer range 0 to (RES_CLKS + 1) := 0;
-- variable for current byte
variable current_byte: std_logic_vector(7 downto 0) := X"00";
-- alias for current bit to be output
alias current_bit: std_logic is current_byte(7);
-- counter to keep track of number of output bits
variable bitcounter: integer range 0 to 7 := 0;
-- states for state machine
type states_t is (GETBYTE, OUT_RESET, SETUP_HIGH, OUT_HIGH, SETUP_LOW, OUT_LOW);
variable state: states_t := GETBYTE;
begin
if rising_edge(CLK_I) then
-- keep rgb control signal low by default
O_rgb_ctrl <= '0';
-- It's the final countdown... for timing
clkcounter := clkcounter - 1;
case state is
when GETBYTE =>
-- put byte read by the RAM process into our buffer
current_byte := next_rgb_byte;
if next_rgb_addr = 0 then
clkcounter := RES_CLKS;
state := OUT_RESET;
else
state := SETUP_HIGH;
end if;
next_rgb_addr <= next_rgb_addr + 1;
bitcounter := 0;
when OUT_RESET =>
if clkcounter = 0 then
-- done waiting!
state := SETUP_HIGH;
end if;
when SETUP_HIGH =>
-- determine length of high-output phase
if current_bit = '0' then
clkcounter := T0H_CLKS;
else
clkcounter := T1H_CLKS;
end if;
state := OUT_HIGH;
when OUT_HIGH =>
-- output HIGH!
O_rgb_ctrl <= '1';
if clkcounter = 0 then
-- done waiting, progress state machine!
state := SETUP_LOW;
end if;
when SETUP_LOW =>
-- determine length of low-output phase
if current_bit = '0' then
clkcounter := T0L_CLKS;
else
clkcounter := T1L_CLKS;
end if;
state := OUT_LOW;
when OUT_LOW =>
if clkcounter = 0 then
-- done waiting, progress!
-- shift current byte one bit position
current_byte := current_byte(6 downto 0) & '0';
if bitcounter = 7 then
-- byte finished, get next byte
state := GETBYTE;
else
-- output next bit of current byte
state := SETUP_HIGH;
end if;
bitcounter := bitcounter + 1;
end if;
end case;
end if;
end process;
-- process to access RAM
process(CLK_I, STB_I)
variable ack: std_logic := '0';
begin
if rising_edge(CLK_I) then
ack := '0';
if STB_I = '1' then
if(WE_I = '1') then
ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0)))) <= DAT_I;
else
DAT_O <= ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0))));
end if;
ack := '1';
end if;
-- read RGB-byte and store into a buffer for consumption by the other process
next_rgb_byte <= ram(next_rgb_addr);
end if;
ACK_O <= STB_I and ack;
end process;
end Behavioral;
|
mit
|
c5297fb4ab70d735959fd6c111026bfd
| 0.61866 | 3.134138 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/sys_toplevel.vhd
| 1 | 5,210 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity sys_toplevel is
Port(
I_clk: in std_logic;
I_en: in std_logic := '1';
I_reset: in std_logic := '0';
I_serial_rx: in std_logic;
O_addr: out std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_leds: out std_logic_vector(7 downto 0);
O_serial_tx: out std_logic;
O_busy: out std_logic
);
end sys_toplevel;
architecture Behavioral of sys_toplevel is
component arbiter
Port(
I_addr: in std_logic_vector(31 downto 0);
I_busy0, I_busy1, I_busy2, I_busy3: in std_logic;
I_data0, I_data1, I_data2, I_data3: in std_logic_vector(31 downto 0);
I_en: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0);
O_en0, O_en1, O_en2, O_en3: out std_logic
);
end component;
component arbiter_dummy
Port(
I_addr: in std_logic_vector(31 downto 0);
I_clk: in std_logic;
I_data: in std_logic_vector(31 downto 0);
I_en: in std_logic;
I_write: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0)
);
end component;
component cpu_toplevel
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_reset: in std_logic;
I_memdata: in std_logic_vector(XLEN-1 downto 0);
I_membusy: in std_logic;
O_memdata: out std_logic_vector(XLEN-1 downto 0);
O_memaddr: out std_logic_vector(XLEN-1 downto 0);
O_memen: out std_logic := '0';
O_memwrite: out std_logic := '0'
);
end component;
component leds
Port(
I_addr: in std_logic_vector(31 downto 0);
I_clk: in std_logic;
I_data: in std_logic_vector(31 downto 0);
I_en: in std_logic;
I_write: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0);
O_leds: out std_logic_vector(7 downto 0)
);
end component;
component ram
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_write: in std_logic;
I_addr: in std_logic_vector(XLEN-1 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_busy: out std_logic
);
end component;
component serial
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_addr: in std_logic_vector(31 downto 0);
I_data: in std_logic_vector(31 downto 0);
I_rx: in std_logic;
I_write: in std_logic;
O_tx: out std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0)
);
end component;
component wizpll
PORT(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
end component;
signal arb_busy, arb_en0, arb_en1, arb_en2, arb_en3: std_logic;
signal arb_data: std_logic_vector(XLEN-1 downto 0);
signal cpu_memdata: std_logic_vector(XLEN-1 downto 0);
signal cpu_memaddr: std_logic_vector(XLEN-1 downto 0);
signal cpu_memen: std_logic := '0';
signal cpu_memwrite: std_logic := '0';
signal dummy3_data: std_logic_vector(XLEN-1 downto 0);
signal dummy3_busy: std_logic;
signal inv_clk: std_logic;
signal inv_reset: std_logic;
signal led_busy: std_logic;
signal led_data: std_logic_vector(XLEN-1 downto 0);
signal pll_clk: std_logic;
signal ram_busy: std_logic := '0';
signal ram_data: std_logic_vector(XLEN-1 downto 0);
signal serial_busy: std_logic;
signal serial_data: std_logic_vector(XLEN-1 downto 0);
begin
arbiter_instance: arbiter port map(
I_addr => cpu_memaddr,
I_busy0 => ram_busy,
I_busy1 => led_busy,
I_busy2 => serial_busy,
I_busy3 => dummy3_busy,
I_data0 => ram_data,
I_data1 => led_data,
I_data2 => serial_data,
I_data3 => dummy3_data,
I_en => cpu_memen,
O_busy => arb_busy,
O_data => arb_data,
O_en0 => arb_en0,
O_en1 => arb_en1,
O_en2 => arb_en2,
O_en3 => arb_en3
);
cpu_instance: cpu_toplevel port map(
I_clk => pll_clk,
I_en => I_en,
I_reset => inv_reset,
I_memdata => arb_data,
I_membusy => arb_busy,
O_memdata => cpu_memdata,
O_memaddr => cpu_memaddr,
O_memen => cpu_memen,
O_memwrite => cpu_memwrite
);
-- I/O device 0
ram_instance: ram port map(
I_clk => inv_clk,
I_en => arb_en0,
I_write => cpu_memwrite,
I_addr => cpu_memaddr,
I_data => cpu_memdata,
O_data => ram_data,
O_busy => ram_busy
);
-- I/O device 1
leds_instance: leds port map(
I_clk => inv_clk,
I_en => arb_en1,
I_write => cpu_memwrite,
I_addr => cpu_memaddr,
I_data => cpu_memdata,
O_data => led_data,
O_busy => led_busy,
O_leds => O_leds
);
-- I/O device 2
serial_instance: serial port map(
I_clk => inv_clk,
I_en => arb_en2,
I_addr => cpu_memaddr,
I_data => cpu_memdata,
I_rx => I_serial_rx,
I_write => cpu_memwrite,
O_tx => O_serial_tx,
O_busy => serial_busy,
O_data => serial_data
);
-- I/O device 3
dummy3: arbiter_dummy port map(
I_addr => cpu_memaddr,
I_clk => inv_clk,
I_data => cpu_memdata,
I_en => arb_en3,
I_write => cpu_memwrite,
O_busy => dummy3_busy,
O_data => dummy3_data
);
pll_instance: wizpll port map(
inclk0 => I_clk,
c0 => pll_clk
);
inv_clk <= not pll_clk;
inv_reset <= not I_reset;
O_addr <= cpu_memaddr;
O_data <= cpu_memdata;
O_busy <= arb_busy;
end Behavioral;
|
mit
|
0c4915d2b3a0f7dbbfaa626e435d1c07
| 0.630134 | 2.485687 | false | false | false | false |
miree/vhdl_cores
|
tdc/serializer.vhd
| 1 | 1,807 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity serializer is
generic (
in_width : integer;
out_width : integer;
depth : integer
);
port (
clk_i , rst_i : in std_logic;
push_i, pop_i : in std_logic;
full_o, empty_o : out std_logic;
d_i : in std_logic_vector ( in_width-1 downto 0 );
q_o : out std_logic_vector ( out_width-1 downto 0 )
);
end entity;
architecture rtl of serializer is
signal pop : std_logic;
signal out_data : std_logic_vector ( in_width-1 downto 0 );
constant idx_max : integer := in_width/out_width-1;
constant idx_width : integer := integer(ceil(log2(real(idx_max+1))));
signal idx : unsigned ( idx_width-1 downto 0 ) := (others => '0');
begin
fifo: entity work.fifo
generic map (
depth => depth,
bit_width => in_width
)
port map (
clk_i => clk_i,
rst_i => rst_i,
push_i => push_i,
pop_i => pop,
full_o => full_o,
empty_o => empty_o,
d_i => d_i,
q_o => out_data
);
main : process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i = '1' then
idx <= (others => '0');
else
if pop_i = '1' then
if idx = idx_max then
idx <= (others => '0');
else
idx <= idx + 1;
end if;
end if;
end if;
end if;
end process;
--q_o <= out_data(out_width*(to_integer(idx)+1)-1 downto out_width*to_integer(idx));
q_o <= out_data(out_width*(idx_max+1-to_integer(idx))-1 downto out_width*(idx_max-to_integer(idx)));
pop <= '1' when pop_i = '1' and idx = idx_max else '0';
end architecture;
|
mit
|
d0f22f4ec08aa399c3a5a3f2d26626f0
| 0.530714 | 3.052365 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/rgmii_if.vhd
| 2 | 18,022 |
--------------------------------------------------------------------------------
-- File : rgmii_v2_0_if.vhd
-- Author : Xilinx Inc.
-- ------------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- ------------------------------------------------------------------------------
-- Description: This module creates a version 2.0 Reduced Gigabit Media
-- Independent Interface (RGMII v2.0) by instantiating
-- Input/Output buffers and Input/Output double data rate
-- (DDR) flip-flops as required.
--
-- This interface is used to connect the Ethernet MAC to
-- an external Ethernet PHY.
-- This module routes the rgmii_rxc from the phy chip
-- (via a bufg) onto the rx_clk line.
-- An IODELAY component is used to shift the input clock
-- to ensure that the set-up and hold times are observed.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the PHY IF design.
--------------------------------------------------------------------------------
entity rgmii_if is
port(
-- Synchronous resets
tx_reset : in std_logic;
rx_reset : in std_logic;
-- The following ports are the RGMII physical interface: these will be at
-- pins on the FPGA
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- The following signals are in the RGMII in-band status signals
link_status : out std_logic;
clock_speed : out std_logic_vector(1 downto 0);
duplex_status : out std_logic;
-- The following ports are the internal GMII connections from IOB logic
-- to the TEMAC core
txd_from_mac : in std_logic_vector(7 downto 0);
tx_en_from_mac : in std_logic;
tx_er_from_mac : in std_logic;
tx_clk : in std_logic;
crs_to_mac : out std_logic;
col_to_mac : out std_logic;
rxd_to_mac : out std_logic_vector(7 downto 0);
rx_dv_to_mac : out std_logic;
rx_er_to_mac : out std_logic;
-- Receiver clock for the MAC and Client Logic
rx_clk : out std_logic
);
end rgmii_if;
architecture PHY_IF of rgmii_if is
------------------------------------------------------------------------------
-- internal signals
------------------------------------------------------------------------------
signal not_tx_clk90 : std_logic; -- Inverted version of tx_clk90.
signal not_tx_clk : std_logic; -- Inverted version of tx_clk.
signal gmii_txd_rising : std_logic_vector(7 downto 0); -- gmii_txd signal registered on the rising edge of tx_clk.
signal gmii_tx_en_rising : std_logic; -- gmii_tx_en signal registered on the rising edge of tx_clk.
signal rgmii_tx_ctl_rising : std_logic; -- RGMII control signal registered on the rising edge of tx_clk.
signal gmii_txd_falling : std_logic_vector(3 downto 0); -- gmii_txd signal registered on the falling edge of tx_clk.
signal rgmii_tx_ctl_falling : std_logic; -- RGMII control signal registered on the falling edge of tx_clk.
signal rgmii_txc_odelay : std_logic; -- RGMII receiver clock ODDR output.
signal rgmii_tx_ctl_odelay : std_logic; -- RGMII control signal ODDR output.
signal rgmii_txd_odelay : std_logic_vector(3 downto 0); -- RGMII data ODDR output.
signal rgmii_tx_ctl_int : std_logic; -- Internal RGMII transmit control signal.
signal rgmii_rxd_delay : std_logic_vector(7 downto 0);
signal rgmii_rx_ctl_delay : std_logic;
signal rx_clk_inv : std_logic;
signal rgmii_rx_ctl_reg : std_logic; -- Internal RGMII receiver control signal.
signal gmii_rxd_reg_int : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal gmii_rx_dv_reg_int : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_dv_reg : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_er_reg : std_logic; -- gmii_rx_er registered in IOBs.
signal gmii_rxd_reg : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal inband_ce : std_logic; -- RGMII inband status registers clock enable
signal rx_clk_int : std_logic;
begin
-----------------------------------------------------------------------------
-- Route internal signals to output ports :
-----------------------------------------------------------------------------
rxd_to_mac <= gmii_rxd_reg;
rx_dv_to_mac <= gmii_rx_dv_reg;
rx_er_to_mac <= gmii_rx_er_reg;
-----------------------------------------------------------------------------
-- RGMII Transmitter Clock Management :
-----------------------------------------------------------------------------
-- Delay the transmitter clock relative to the data.
-- For 1 gig operation this delay is set to produce a 90 degree phase
-- shifted clock w.r.t. gtx_clk_bufg so that the clock edges are
-- centralised within the rgmii_txd[3:0] valid window.
-- Invert the clock locally at the ODDR primitive
not_tx_clk <= not(tx_clk);
-- Instantiate the Output DDR primitive
rgmii_txc_ddr : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => rgmii_txc_odelay,
C0 => tx_clk,
C1 => not_tx_clk,
CE => '1',
D0 => '1',
D1 => '0',
R => tx_reset,
S => '0'
);
-- Instantiate the Output Delay primitive (delay output by 2 ns)
delay_rgmii_tx_clk : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 30, -- 50 ps per tap 0-255 taps
DELAY_SRC => "ODATAIN"
)
port map (
BUSY => open,
DATAOUT => open,
DATAOUT2 => open,
DOUT => rgmii_txc,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => '0',
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => rgmii_txc_odelay,
RST => '0',
T => '0'
);
-----------------------------------------------------------------------------
-- RGMII Transmitter Logic :
-- drive TX signals through IOBs onto RGMII interface
-----------------------------------------------------------------------------
-- Encode rgmii ctl signal
rgmii_tx_ctl_int <= tx_en_from_mac xor tx_er_from_mac;
-- Instantiate Double Data Rate Output components.
-- Put data and control signals through ODELAY components to
-- provide similiar net delays to those seen on the clk signal.
gmii_txd_falling <= txd_from_mac(7 downto 4);
txdata_out_bus: for I in 3 downto 0 generate
begin
-- Instantiate the Output DDR primitive
rgmii_txd_out : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => rgmii_txd_odelay(I),
C0 => tx_clk,
C1 => not_tx_clk,
CE => '1',
D0 => txd_from_mac(I),
D1 => gmii_txd_falling(I),
R => tx_reset,
S => '0'
);
-- Instantiate the Output Delay primitive (delay output by 2 ns)
delay_rgmii_txd : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0, -- 50 ps per tap 0-255 taps
DELAY_SRC => "ODATAIN"
)
port map (
BUSY => open,
DATAOUT => open,
DATAOUT2 => open,
DOUT => rgmii_txd(I),
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => '0',
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => rgmii_txd_odelay(I),
RST => '0',
T => '0'
);
end generate;
-- Instantiate the Output DDR primitive
rgmii_tx_ctl_out : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => rgmii_tx_ctl_odelay,
C0 => tx_clk,
C1 => not_tx_clk,
CE => '1',
D0 => tx_en_from_mac,
D1 => rgmii_tx_ctl_int,
R => tx_reset,
S => '0'
);
-- Instantiate the Output Delay primitive (delay output by 2 ns)
delay_rgmii_tx_ctl : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0, -- 50 ps per tap 0-255 taps
DELAY_SRC => "ODATAIN"
)
port map (
BUSY => open,
DATAOUT => open,
DATAOUT2 => open,
DOUT => rgmii_tx_ctl,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => '0',
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => rgmii_tx_ctl_odelay,
RST => '0',
T => '0'
);
-----------------------------------------------------------------------------
-- RGMII Receiver Clock Logic
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- RGMII Receiver Clock Logic
-----------------------------------------------------------------------------
bufg_rgmii_rx_clk : BUFG
port map (
I => rgmii_rxc,
O => rx_clk_int
);
-- Assign the internal clock signal to the output port
rx_clk <= rx_clk_int;
rx_clk_inv <= not rx_clk_int;
-----------------------------------------------------------------------------
-- RGMII Receiver Logic : receive signals through IOBs from RGMII interface
-----------------------------------------------------------------------------
-- Instantiate Double Data Rate Input flip-flops.
-- DDR_CLK_EDGE attribute specifies output data alignment from IDDR component
rxdata_in_bus: for I in 3 downto 0 generate
delay_rgmii_rxd : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 40,
DELAY_SRC => "IDATAIN"
)
port map (
BUSY => open,
DATAOUT => rgmii_rxd_delay(I),
DATAOUT2 => open,
DOUT => open,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => rgmii_rxd(I),
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => '0',
RST => '0',
T => '1'
);
rgmii_rx_data_in : IDDR2
generic map (
DDR_ALIGNMENT => "C0"
)
port map (
Q0 => gmii_rxd_reg_int(I),
Q1 => gmii_rxd_reg_int(I+4),
C0 => rx_clk_int,
C1 => rx_clk_inv,
CE => '1',
D => rgmii_rxd_delay(I),
R => '0',
S => '0'
);
-- pipeline the bottom 4 bits
rxd_reg_pipe : process(rx_clk_int)
begin
if rx_clk_int'event and rx_clk_int ='1' then
gmii_rxd_reg(I) <= gmii_rxd_reg_int(I);
end if;
end process rxd_reg_pipe;
-- just pass the top 4 bits
gmii_rxd_reg(I+4) <= gmii_rxd_reg_int(I+4);
end generate;
delay_rgmii_rx_ctl : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 40,
DELAY_SRC => "IDATAIN"
)
port map (
BUSY => open,
DATAOUT => rgmii_rx_ctl_delay,
DATAOUT2 => open,
DOUT => open,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => rgmii_rx_ctl,
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => '0',
RST => '0',
T => '1'
);
rgmii_rx_ctl_in : IDDR2
generic map (
DDR_ALIGNMENT => "C0"
)
port map (
Q0 => gmii_rx_dv_reg_int,
Q1 => rgmii_rx_ctl_reg,
C0 => rx_clk_int,
C1 => rx_clk_inv,
CE => '1',
D => rgmii_rx_ctl_delay,
R => '0',
S => '0'
);
rxdv_reg_pipe : process(rx_clk_int)
begin
if rx_clk_int'event and rx_clk_int ='1' then
gmii_rx_dv_reg <= gmii_rx_dv_reg_int;
end if;
end process rxdv_reg_pipe;
-- Decode gmii_rx_er signal
gmii_rx_er_reg <= gmii_rx_dv_reg xor rgmii_rx_ctl_reg;
-----------------------------------------------------------------------------
-- RGMII Inband Status Registers :
-- extract the inband status from received rgmii data
-----------------------------------------------------------------------------
-- Enable inband status registers during Interframe Gap
inband_ce <= gmii_rx_dv_reg nor gmii_rx_er_reg;
reg_inband_status : process(rx_clk_int)
begin
if rx_clk_int'event and rx_clk_int ='1' then
if rx_reset = '1' then
link_status <= '0';
clock_speed(1 downto 0) <= "00";
duplex_status <= '0';
elsif inband_ce = '1' then
link_status <= gmii_rxd_reg(0);
clock_speed(1 downto 0) <= gmii_rxd_reg(2 downto 1);
duplex_status <= gmii_rxd_reg(3);
end if;
end if;
end process reg_inband_status;
-----------------------------------------------------------------------------
-- Create the GMII-style Collision and Carrier Sense signals from RGMII
-----------------------------------------------------------------------------
col_to_mac <= (tx_en_from_mac or tx_er_from_mac) and (gmii_rx_dv_reg or gmii_rx_er_reg);
crs_to_mac <= (tx_en_from_mac or tx_er_from_mac) or (gmii_rx_dv_reg or gmii_rx_er_reg);
end PHY_IF;
|
bsd-2-clause
|
73a64055acbdc7e59472d229d5e12a6c
| 0.455554 | 4.413911 | false | false | false | false |
marc0l92/RadioFM_FPGA
|
RadioFM_project/ipcore_dir/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.vhd
| 1 | 6,020 |
-- file: clk_wiz_v3_6_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clk_wiz_v3_6_exdes;
architecture xilinx of clk_wiz_v3_6_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clk_wiz_v3_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clk_wiz_v3_6
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int,
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
clkout_oddr : ODDR port map
(Q => CLK_OUT(1),
C => clk,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
|
gpl-3.0
|
cfb82f8b0df5d0bda3ebd900750ab193
| 0.594186 | 4 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part1/HexBtns.vhd
| 1 | 1,262 |
----------------------------------------
-- module name: hexbtns - btnpulse --
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexBtns is
port ( clk : in std_logic;
btns : in std_logic_vector (3 downto 0);
pulse : out std_logic_vector (3 downto 0));
end HexBtns;
architecture btnpulse of HexBtns is
signal bp0, bp1, bp2, bp3 : std_logic := '0'; -- Button debounce pulses
begin
-- Assign the debounce pulses to buttons
bdb0: debounce port map (clk, btns(0), bp0);
bdb1: debounce port map (clk, btns(1), bp1);
bdb2: debounce port map (clk, btns(2), bp2);
bdb3: debounce port map (clk, btns(3), bp3);
process (clk)
begin
if rising_edge(clk) then
if bp0 = '1' then pulse(0) <= '1';
else pulse(0) <= '0'; end if;
if bp1 = '1' then pulse(1) <= '1';
else pulse(1) <= '0'; end if;
if bp2 = '1' then pulse(2) <= '1';
else pulse(2) <= '0'; end if;
if bp3 = '1' then pulse(3) <= '1';
else pulse(3) <= '0'; end if;
end if;
end process;
end btnpulse;
|
gpl-3.0
|
ef62606e25beceeb63d3542f9fe09a46
| 0.487322 | 3.467033 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/sys_tb.vhd
| 1 | 1,535 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity sys_tb is
end sys_tb;
architecture Behavior of sys_tb is
component sys_toplevel
Port(
I_clk: in std_logic;
I_en: in std_logic := '1';
I_reset: in std_logic := '1'; -- gets inverted
I_serial_rx: in std_logic;
O_addr: out std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_leds: out std_logic_vector(7 downto 0);
O_serial_tx: out std_logic;
O_busy: out std_logic
);
end component;
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_en: std_logic := '1';
signal I_reset: std_logic := '0';
signal I_serial_rx: std_logic;
signal O_addr: std_logic_vector(XLEN-1 downto 0);
signal O_data: std_logic_vector(XLEN-1 downto 0);
signal O_leds: std_logic_vector(7 downto 0);
signal O_serial_tx: std_logic;
signal O_busy: std_logic;
begin
-- instantiate unit under test
uut: sys_toplevel port map(
I_clk => I_clk,
I_en => I_en,
I_reset => I_reset,
I_serial_rx => I_serial_rx,
O_addr => O_addr,
O_data => O_data,
O_leds => O_leds,
O_serial_tx => O_serial_tx,
O_busy => O_busy
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
I_en <= '1';
I_reset <= '1';
wait for 1000 * I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
110563931871da029ed580e230f31ec2
| 0.645603 | 2.562604 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part1/Debounce.vhd
| 1 | 825 |
--------------------------------------------
-- Module Name: debounce - clean_pulse --
--------------------------------------------
-- Button debounce circuit;
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT (
clk : IN STD_LOGIC; ---make it low frequency
key : IN STD_LOGIC; -- active low input
pulse : OUT STD_LOGIC);
END debounce;
ARCHITECTURE clean_pulse OF debounce IS
SIGNAL cnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
BEGIN
PROCESS (clk,key)
BEGIN
IF key = '1' THEN
cnt <= "00";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (cnt /= "11") THEN cnt <= cnt + 1; END IF;
END IF;
IF (cnt = "10") AND (key = '0') THEN pulse <= '1'; ELSE pulse <= '0'; END IF;
END PROCESS;
END clean_pulse;
|
gpl-3.0
|
af0af7759a9b9d60d92ab341899f089b
| 0.523636 | 3.618421 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/fifoio.vhd
| 1 | 11,248 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : fifoio.vhf
-- /___/ /\ Timestamp : 02/10/2006 14:47:24
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w fifoio.sch fifoio.vhf
--Design Name: fifoio
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD_MXILINX_fifoio is
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end FD_MXILINX_fifoio;
architecture BEHAVIORAL of FD_MXILINX_fifoio is
attribute BOX_TYPE : string ;
signal XLXN_4 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component FDCP
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
begin
I_36_43 : GND
port map (G=>XLXN_4);
U0 : FDCP
port map (C=>C,
CLR=>XLXN_4,
D=>D,
PRE=>XLXN_4,
Q=>Q);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity BUFE4_MXILINX_fifoio is
port ( E : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic);
end BUFE4_MXILINX_fifoio;
architecture BEHAVIORAL of BUFE4_MXILINX_fifoio is
attribute BOX_TYPE : string ;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
begin
I_36_37 : BUFE
port map (E=>E,
I=>I3,
O=>O3);
I_36_38 : BUFE
port map (E=>E,
I=>I2,
O=>O2);
I_36_39 : BUFE
port map (E=>E,
I=>I1,
O=>O1);
I_36_40 : BUFE
port map (E=>E,
I=>I0,
O=>O0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD8CE_MXILINX_fifoio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic_vector (7 downto 0);
Q : out std_logic_vector (7 downto 0));
end FD8CE_MXILINX_fifoio;
architecture BEHAVIORAL of FD8CE_MXILINX_fifoio is
attribute BOX_TYPE : string ;
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q0 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(0),
Q=>Q(0));
Q1 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(1),
Q=>Q(1));
Q2 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(2),
Q=>Q(2));
Q3 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(3),
Q=>Q(3));
Q4 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(4),
Q=>Q(4));
Q5 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(5),
Q=>Q(5));
Q6 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(6),
Q=>Q(6));
Q7 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(7),
Q=>Q(7));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity fifoio is
port ( A2DSYNC : in std_logic;
FIFO : in std_logic;
FIFOAFAE : in std_logic;
FIFOEMPTYN : in std_logic;
FIFOFULL : in std_logic;
FIFOHF : in std_logic;
FIFOSTAT : in std_logic;
ONEPPS : in std_logic;
PRESYNC : in std_logic;
SIOR : in std_logic;
SIOWN : in std_logic;
clk : in std_logic;
FIFOCLRN : out std_logic;
FIFOCTL : out std_logic_vector (7 downto 0);
FIFODAFN : out std_logic;
FIFOOE : out std_logic;
FIFOUNCK : out std_logic;
-- TEST43 : out std_logic;
BSD : inout std_logic_vector (15 downto 0));
end fifoio;
architecture BEHAVIORAL of fifoio is
attribute HU_SET : string ;
attribute BOX_TYPE : string ;
signal LLO : std_logic;
signal LL0 : std_logic;
signal LL1 : std_logic;
signal XLXN_10 : std_logic;
signal XLXN_30 : std_logic;
signal FIFOCTL_DUMMY : std_logic_vector (7 downto 0);
signal FIFOOE_DUMMY : std_logic;
signal FIFOOE_DELAY : std_logic;
signal PLL_DIV : std_logic;
component FD8CE_MXILINX_fifoio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic_vector (7 downto 0);
Q : out std_logic_vector (7 downto 0));
end component;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component BUFE4_MXILINX_fifoio
port ( E : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic);
end component;
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
component NOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
component FD_MXILINX_fifoio
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NOR2 : component is "BLACK_BOX";
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
attribute HU_SET of XLXI_4 : label is "XLXI_4_1";
attribute HU_SET of XLXI_19 : label is "XLXI_19_0";
attribute HU_SET of XLXI_29 : label is "XLXI_29_2";
attribute HU_SET of XLXI_37 : label is "XLXI_37_3";
attribute HU_SET of XLXI_38 : label is "XLXI_38_4";
begin
FIFOCTL(7 downto 0) <= FIFOCTL_DUMMY(7 downto 0);
FIFOOE <= FIFOOE_DUMMY;
XLXI_4 : FD8CE_MXILINX_fifoio
port map (C=>SIOWN,
CE=>FIFO,
CLR=>XLXN_10,
D(7 downto 0)=>BSD(7 downto 0),
Q(7 downto 0)=>FIFOCTL_DUMMY(7 downto 0));
XLXI_5 : GND
port map (G=>XLXN_10);
XLXI_17 : INV
port map (I=>FIFOCTL_DUMMY(5),
O=>FIFODAFN);
XLXI_19 : BUFE4_MXILINX_fifoio
port map (E=>XLXN_30,
I0=>FIFOHF,
I1=>FIFOAFAE,
I2=>FIFOEMPTYN,
I3=>FIFOFULL,
O0=>BSD(0),
O1=>BSD(1),
O2=>BSD(2),
O3=>BSD(3));
XLXI_20 : AND2
port map (I0=>FIFOSTAT,
I1=>SIOR,
O=>XLXN_30);
XLXI_23 : AND2
port map (I0=>SIOR,
I1=>FIFO,
O=>FIFOOE_DELAY);
XLXI_28 : INV
port map (I=>FIFOOE_DUMMY,
O=>FIFOUNCK);
XLXI_29 : BUFE4_MXILINX_fifoio
port map (E=>XLXN_30,
I0=>ONEPPS,
I1=>PRESYNC,
I2=>LL0,
I3=>LL0,
O0=>BSD(4),
O1=>BSD(5),
O2=>BSD(6),
O3=>BSD(7));
-- XLXI_31 : BUFE4_MXILINX_fifoio
-- port map (E=>XLXN_30,
-- I0=>A2DINT(1),
-- I1=>A2DINT(2),
-- I2=>A2DINT(3),
-- I3=>A2DINT(4),
-- O0=>BSD(8),
-- O1=>BSD(9),
-- O2=>BSD(10),
-- O3=>BSD(11));
-- XLXI_32 : BUFE4_MXILINX_fifoio
-- port map (E=>XLXN_30,
-- I0=>A2DINT(4),
-- I1=>A2DINT(5),
-- I2=>A2DINT(6),
-- I3=>A2DINT(7),
-- O0=>BSD(12),
-- O1=>BSD(13),
-- O2=>BSD(14),
-- O3=>BSD(15));
XLXI_33 : GND
port map (G=>LLO);
XLXI_34 : VCC
port map (P=>LL1);
XLXI_36 : NOR2
port map (I0=>A2DSYNC,
I1=>FIFOCTL_DUMMY(0),
O=>FIFOCLRN);
XLXI_37 : FD_MXILINX_fifoio
port map (C=>clk,
D=>FIFOOE_DELAY,
Q=>PLL_DIV);
XLXI_38 : FD_MXILINX_fifoio
port map (C=>clk,
D=>PLL_DIV,
Q=>FIFOOE_DUMMY);
end BEHAVIORAL;
|
gpl-2.0
|
014128c81e9a2569058672e740dfc539
| 0.455459 | 3.552748 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/arbiter/arbiter_wb8.vhd
| 1 | 1,104 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package arbiter_types is
constant ARB_DEVICES: integer := 8;
type arb_ACK_I_t is array(0 to ARB_DEVICES-1) of std_logic;
type arb_DAT_I_t is array(0 to ARB_DEVICES-1) of std_logic_vector(7 downto 0);
type arb_STB_O_t is array(0 to ARB_DEVICES-1) of std_logic;
end package;
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.arbiter_types.ALL;
entity arbiter_wb8 is
Port(
ADR_I: in std_logic_vector(31 downto 0);
ACK_I: in arb_ACK_I_t;
DAT_I: in arb_DAT_I_t;
STB_I: in std_logic := '0';
ACK_O: out std_logic := '0';
DAT_O: out std_logic_vector(7 downto 0);
STB_O: out arb_STB_O_t
);
end arbiter_wb8;
architecture Behavioral of arbiter_wb8 is
begin
process(ADR_I, STB_I, DAT_I, ACK_I)
variable device: integer range 0 to ARB_DEVICES-1;
begin
for i in 0 to ARB_DEVICES-1 loop
STB_O(i) <= '0';
end loop;
device := to_integer(unsigned(ADR_I(31 downto 28)));
STB_O(device) <= STB_I;
DAT_O <= DAT_I(device);
ACK_O <= ACK_I(device);
end process;
end Behavioral;
|
mit
|
fb9e383414c21bae64912f38bfac3406
| 0.673007 | 2.509091 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AddSubN.vhd
| 1 | 614 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity AddSubN is
generic(n : positive := 4);
port (op0 : in std_logic_vector(n-1 downto 0);
op1 : in std_logic_vector(n-1 downto 0);
sub : in std_logic;
cout : out std_logic;
res : out std_logic_vector(n-1 downto 0));
end AddSubN;
architecture Behavioral of AddSubN is
signal s_a, s_b, s_s : unsigned(n downto 0);
begin
s_a <= '0' & unsigned(op0);
s_b <= '0' & unsigned(op1);
s_s <= (s_a + s_b) when (sub='0') else
(s_a - s_b);
res <= std_logic_vector(s_s(n-1 downto 0));
cout<= std_logic(s_s(n));
end Behavioral;
|
gpl-2.0
|
da3164dce9464bda84644823cb4b5afe
| 0.625407 | 2.299625 | false | false | false | false |
spoorcc/realtimestagram
|
src/sigmoid_tb.vhd
| 2 | 4,015 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity sigmoid_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/sigmoid_output.pgm"; --! Output file of test
c_factor: real := 15.0 --! Amount of contrast adjustment
);
end entity;
--======================================================================================--
architecture structural of sigmoid_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 3
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
pixel_from_file: out std_logic_vector((wordsize-1) downto 0);
pixel_to_file: in std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
component lookup_table is
generic (
wordsize: integer := const_wordsize;
lut: array_pixel := create_sigmoid_lut(2**const_wordsize, c_factor)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
pixel_i: in std_logic_vector((wordsize-1) downto 0);
pixel_o: out std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: lookup_table
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
gpl-2.0
|
8463b991a1fb512b94e18a435f2a814b
| 0.465006 | 4.712441 | false | false | false | false |
rbaummer/UART
|
uart.vhd
| 1 | 9,043 |
--------------------------------------------------------------------------------
--
-- File: UART
-- Author: Rob Baummer
--
-- Description: A 8x oversampling UART operating from 9600 to 57600 baud. Uses
-- 1 start bit, 1 stop bit and no parity.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
entity uart is
generic (
--Frequency of System clock in Hz
clock_frequency : integer);
port (
--System interface
reset : in std_logic;
sys_clk : in std_logic;
--UART serial interface
DIN : in std_logic;
DOUT : out std_logic;
--Processor interface
proc_clk : in std_logic;
proc_addr : in std_logic_vector(1 downto 0);
proc_read : in std_logic;
proc_write : in std_logic;
proc_read_data : out std_logic_vector(7 downto 0);
proc_write_data : in std_logic_vector(7 downto 0)
);
end uart;
architecture behavorial of uart is
signal baud_enable : std_logic;
signal DIN_sync : std_logic;
signal baud_rate_sel : std_logic_vector(2 downto 0);
signal baud_en : std_logic;
signal baud_rate_reg : std_logic_vector(2 downto 0);
signal baud_rate_write : std_logic;
signal rx_byte : std_logic_vector(7 downto 0);
signal rx_valid : std_logic;
signal rx_full : std_logic;
signal rx_frame_error : std_logic;
signal baud_locked : std_logic;
signal baud_unlocked : std_logic;
signal rx_break : std_logic;
signal proc_rx_empty : std_logic;
signal proc_valid : std_logic;
signal proc_rx_read : std_logic;
signal proc_rx_data : std_logic_vector(7 downto 0);
signal rx_overflow : std_logic;
signal tx_read : std_logic;
signal tx_valid : std_logic;
signal tx_empty : std_logic;
signal tx_byte : std_logic_vector(7 downto 0);
signal proc_tx_full : std_logic;
signal proc_tx_write : std_logic;
signal uart_status : std_logic_vector(5 downto 0);
signal uart_status_sync : std_logic_vector(5 downto 0);
signal rx_enable_sync : std_logic;
signal baud_rate_reg_sync : std_logic_vector(2 downto 0);
signal baud_rate_write_sync : std_logic;
signal status_cs : std_logic;
signal control_cs : std_logic;
signal tx_cs : std_logic;
signal rx_cs : std_logic;
signal uart_control : std_logic_vector(4 downto 0);
signal status_clear : std_logic;
signal status_clear_sync : std_logic;
signal proc_reset : std_logic;
signal proc_reset_sync : std_logic;
signal uart_reset : std_logic;
begin
--UART reset, can be reset from global reset or by processor
uart_reset <= reset or proc_reset_sync;
--Synchronizer for DIN
d_sync : entity work.synchronizer
port map (
clk => sys_clk,
reset => reset,
I => DIN,
O => DIN_sync);
--Baud Rate Generator
br_gen : entity work.baud_clock_gen
generic map (
clock_frequency => clock_frequency)
port map (
reset => uart_reset,
sys_clk => sys_clk,
--baud rate selection
--000 - 57.6k
--001 - 38.4k
--010 - 19.2k
--011 - 14.4k
--100 - 9.6k
baud_rate_sel => baud_rate_sel,
--baud enable
baud_enable => baud_enable);
--Auto-Baud Rate Detection
--Requires known Byte 0x0D (return) to be transmitted
auto_br : entity work.uart_baud_rate_det
port map (
reset => uart_reset,
sys_clk => sys_clk,
--Processor override of auto baud rate detection
baud_rate_override => baud_rate_reg_sync,
baud_rate_write => baud_rate_write_sync,
--baud detection interface
rx_byte => rx_byte,
rx_valid => rx_valid,
rx_frame_error => rx_frame_error,
baud_rate_sel => baud_rate_sel,
baud_locked => baud_locked,
baud_unlocked => baud_unlocked);
----------------------------------------------------------------------------
-- UART Receiver --
----------------------------------------------------------------------------
--UART Receive Controller
rx : entity work.uart_rx
port map (
reset => uart_reset,
enable => rx_enable_sync,
sys_clk => sys_clk,
--UART serial interface
DIN => DIN_sync,
--Receiver Interface
baud_en => baud_enable,
rx_byte => rx_byte,
rx_valid => rx_valid,
rx_frame_error => rx_frame_error,
rx_break => rx_break);
--Receive FIFO
rx_fifo : entity work.mixed_clock_fifo_srambased
generic map (
N => 8,
L => 8)
port map (
reset => uart_reset,
--Read Interface to processor
read_clk => proc_clk,
read => proc_rx_read,
valid => proc_valid,
empty => proc_rx_empty,
read_data => proc_rx_data,
--Write Interface to Receiver
write_clk => sys_clk,
write => rx_valid,
full => rx_full,
write_data => rx_byte);
--Receiver overflow detection, sticky bit
--Receive FIFO overflows if it is full and another valid byte arrives at the
--receiver
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if uart_reset = '1' or status_clear_sync = '1' then
rx_overflow <= '0';
elsif rx_valid = '1' and rx_full = '1' then
rx_overflow <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- UART Transmitter --
----------------------------------------------------------------------------
--UART transmitter controller
tx : entity work.uart_tx
port map (
reset => uart_reset,
sys_clk => sys_clk,
--UART serial Interface
DOUT => DOUT,
--Transmitter interface
baud_en => baud_enable,
tx_fifo_empty => tx_empty,
tx_fifo_read => tx_read,
tx_byte => tx_byte,
tx_valid => tx_valid);
--Transmit FIFO
tx_fifo : entity work.mixed_clock_fifo_srambased
generic map (
N => 8,
L => 8)
port map (
reset => uart_reset,
--Read Interface to Transmitter
read_clk => sys_clk,
read => tx_read,
valid => tx_valid,
empty => tx_empty,
read_data => tx_byte,
--Write Interface to Processor
write_clk => proc_clk,
write => proc_tx_write,
full => proc_tx_full,
write_data => proc_write_data);
----------------------------------------------------------------------------
-- Control and Status Registers for Processor --
----------------------------------------------------------------------------
--uart status signals on sys_clk domain
uart_status <= baud_rate_sel & baud_unlocked & baud_locked & rx_overflow;
--status clear on proc_clk domain
status_clear <= status_cs and proc_read;
--synchronize sys_clk domain status signals to proc_clk domain
stat_sync : entity work.nbit_synchronizer
generic map (
N => 6)
port map (
clk => proc_clk,
reset => reset,
I => uart_status,
O => uart_status_sync);
clr_sync : entity work.synchronizer
port map (
clk => sys_clk,
reset => reset,
I => status_clear,
O => status_clear_sync);
--FIFO read/write signals
proc_rx_read <= proc_read and rx_cs;
proc_tx_write <= proc_write and tx_cs;
--synchronized control signals
cntrl0_sync : entity work.synchronizer
port map (
clk => sys_clk,
reset => reset,
I => uart_control(0),
O => rx_enable_sync);
cntrl31_sync : entity work.nbit_synchronizer
generic map (
N => 3)
port map (
clk => sys_clk,
reset => reset,
I => uart_control(3 downto 1),
O => baud_rate_reg_sync);
cntrl4_sync : entity work.synchronizer
port map (
clk => sys_clk,
reset => reset,
I => uart_control(4),
O => baud_rate_write_sync);
--Processor Read Data and Chip Selects
process (proc_addr, uart_status_sync, proc_rx_data, uart_control, proc_rx_empty, proc_tx_full)
begin
status_cs <= '0';
control_cs <= '0';
tx_cs <= '0';
rx_cs <= '0';
proc_read_data <= X"00";
case proc_addr(1 downto 0) is
--Status Register
when "00" =>
-- 7:5 | 4 | 3 | 2 | 1 | 0
--baud_rate | baud_unlock | baud_lock | rx_overflow | tx_full | rx_empty
proc_read_data <= uart_status_sync & proc_tx_full & proc_rx_empty;
status_cs <= '1';
--Control Register
when "01" =>
-- 7 | 6:5 | 4 | 3:1 | 0
-- reset| 00 | baud_write | baud_sel | rx_enable
proc_read_data(4 downto 0) <= uart_control;
control_cs <= '1';
--Transmit FIFO
when "10" =>
tx_cs <= '1';
--Receive FIFO
when "11" =>
proc_read_data <= proc_rx_data;
rx_cs <= '1';
when others =>
proc_read_data <= X"00";
end case;
end process;
--Control Register
--Control Register
-- 7:5 | 4 | 3:1 | 0
-- 000 | baud_write | baud_sel | rx_enable
process (proc_clk)
begin
if proc_clk = '1' and proc_clk'event then
if reset = '1' or proc_reset = '1' then
uart_control <= (others => '0');
elsif control_cs = '1' and proc_write = '1' then
uart_control <= proc_write_data(4 downto 0);
end if;
end if;
end process;
--Writing to bit 7 of control register generates a reset
proc_reset <= control_cs and proc_write_data(7);
rst_sync : entity work.synchronizer
port map (
clk => sys_clk,
reset => reset,
I => proc_reset,
O => proc_reset_sync);
end behavorial;
|
mit
|
91082b0e2e2d14757a32c4a1bc599521
| 0.589517 | 3.055068 | false | false | false | false |
rbaummer/UART
|
testbench/uart_tb_bfm_pkg.vhd
| 1 | 6,927 |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
--Test Bench Package for UART
--Provides procedures for the processor interface of the UART
package uart_tb_bfm_pkg is
--clock signals
constant proc_clk_period : time := 8 ns;
signal proc_clk : std_logic := '0';
--Register Addresses
signal status_addr : std_logic_vector(1 downto 0) := "00";
signal control_addr : std_logic_vector(1 downto 0) := "01";
signal tx_addr : std_logic_vector(1 downto 0) := "10";
signal rx_addr : std_logic_vector(1 downto 0) := "11";
--byte array for reading/writing
type byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
--processor interface to uart
type p_io is record
p_addr : std_logic_vector(1 downto 0);
p_read : std_logic;
p_write : std_logic;
p_read_data : std_logic_vector(7 downto 0);
p_write_data : std_logic_vector(7 downto 0);
end record;
--Procedure for Processor Read
procedure processor_read (
signal addr : in std_logic_vector(1 downto 0);
variable data : out std_logic_vector(7 downto 0);
signal p : inout p_io);
--Procedure for Processor Write
procedure processor_write (
signal addr : in std_logic_vector(1 downto 0);
variable data : in std_logic_vector(7 downto 0);
signal p : inout p_io);
--Procedure for reading UART RX Data
procedure processor_UART_read (
variable read_data : out byte_array;
signal p : inout p_io);
--Procedure for writing UART TX Data
procedure processor_UART_write (
variable write_data : in byte_array;
signal p : inout p_io);
--Initialize the UART simulation
--Set TX UART baud rate
--Enable RX UART
procedure UART_init (
constant baud_rate : in integer;
signal p0 : inout p_io;
signal p1 : inout p_io);
--Reset the UART via the processor
procedure UART_reset (
signal p : inout p_io);
--Compare the two input arrays and return true if they match
function compare_array (
array1 : byte_array;
array2 : byte_array) return boolean;
end uart_tb_bfm_pkg;
package body uart_tb_bfm_pkg is
--Procedure for Processor Read
procedure processor_read (
signal addr : in std_logic_vector(1 downto 0);
variable data : out std_logic_vector(7 downto 0);
signal p : inout p_io) is
begin
wait until proc_clk = '0';
p.p_addr <= addr;
p.p_read <= '1';
wait until proc_clk = '0';
p.p_read <= '0';
data := p.p_read_data;
end procedure;
--Procedure for Processor Write
procedure processor_write (
signal addr : in std_logic_vector(1 downto 0);
variable data : in std_logic_vector(7 downto 0);
signal p : inout p_io) is
begin
wait until proc_clk = '0';
p.p_addr <= addr;
p.p_write <= '1';
p.p_write_data <= data;
wait until proc_clk = '0';
p.p_write <= '0';
end procedure;
--Procedure for reading UART RX Data
procedure processor_UART_read (
variable read_data : out byte_array;
signal p : inout p_io) is
variable read_byte : std_logic_vector(7 downto 0);
variable rx_empty : std_logic := '1';
begin
for i in 0 to read_data'length-1 loop
--check RX status
processor_read(status_addr, read_byte, p);
rx_empty := read_byte(0);
--Poll status register until UART RX data is ready
while rx_empty = '1' loop
wait for 100 us;
--read status register
processor_read(status_addr, read_byte, p);
rx_empty := read_byte(0);
end loop;
--Read RX data
processor_read(rx_addr, read_byte, p);
--Save RX data
read_data(i) := read_byte;
end loop;
end procedure;
--Procedure for writing UART TX Data
procedure processor_UART_write (
variable write_data : in byte_array;
signal p : inout p_io) is
variable tx_full : std_logic := '0';
variable read_byte : std_logic_vector(7 downto 0);
begin
for i in 0 to write_data'length-1 loop
--Check TX full
processor_read(status_addr, read_byte, p);
tx_full := read_byte(1);
--Poll Status register if TX FIFO full is high
while tx_full = '1' loop
--read status register
processor_read(status_addr, read_byte, p);
tx_full := read_byte(1);
if tx_full = '1' then
wait for 1 us;
end if;
end loop;
--write next byte over UART
processor_write(tx_addr, write_data(i), p);
end loop;
end procedure;
--Initialize the UART simulation
--Set TX UART baud rate
--Enable RX UART
procedure UART_init (
constant baud_rate : in integer;
signal p0 : inout p_io;
signal p1 : inout p_io) is
variable baud : std_logic_vector(2 downto 0) := "000";
variable delay : time;
variable byte : std_logic_vector(7 downto 0) := X"00";
variable rx_empty : std_logic := '1';
variable sync_pattern : byte_array(0 to 1);
begin
--Select the baud rate
case baud_rate is
when 576 =>
baud := "000";
delay := 700 us;
when 384 =>
baud := "001";
delay := 1400 us;
when 192 =>
baud := "010";
delay := 2100 us;
when 144 =>
baud := "011";
delay := 2800 us;
when 96 =>
baud := "100";
delay := 4200 us;
when others =>
baud := "000";
delay := 700 us;
end case;
--TX UART Setup for processor 0
byte(4) := '1'; --baud_write
byte(3 downto 1) := baud; --baud_rate
processor_write(control_addr, byte, p0);
--RX UART Setup for processor 1
byte := X"01";
processor_write(control_addr, byte, p1);
--Send sync symbols (0x0D) for processor 0
sync_pattern := (X"0D", X"0D");
processor_UART_write(sync_pattern, p0);
--pause to allow receiver to resync to valid start bit
wait for delay;
sync_pattern := (X"0D", X"0D");
processor_UART_write(sync_pattern, p0);
--wait for sending sync pattern
wait for delay/2;
--test rx sync on processor 1
processor_read(status_addr, byte, p1);
if byte(7 downto 5) = baud and byte(3) = '1' then
report "UART RX Synced" severity note;
else
report "UART RX Failed to Sync" severity failure;
end if;
--Read sync symbols
processor_read(status_addr, byte, p1);
rx_empty := byte(0);
while rx_empty = '0' loop
--read sync character
processor_read(rx_addr, byte, p1);
--read status byte
processor_read(status_addr, byte, p1);
rx_empty := byte(0);
end loop;
report "UART INIT Finished" severity note;
end procedure;
--Reset UART via the processor
procedure UART_reset (
signal p : inout p_io) is
variable byte : std_logic_vector(7 downto 0);
begin
byte := X"80";
processor_write(control_addr, byte, p);
end procedure;
--Compare Array contents, return true if they match else false
function compare_array (
array1 : byte_array;
array2 : byte_array) return boolean is
begin
--Check array sizes match
if array1'length /= array2'length then
return false;
end if;
--Check array data
for i in 0 to array1'length-1 loop
if array1(i) /= array2(i) then
return false;
end if;
end loop;
return true;
end function;
end uart_tb_bfm_pkg;
|
mit
|
4727d28534a5917458352274dc0e2196
| 0.65353 | 3.03151 | false | false | false | false |
rbaummer/UART
|
uart_tx.vhd
| 1 | 5,128 |
--------------------------------------------------------------------------------
--
-- File: UART TX
-- Author: Rob Baummer
--
-- Description: A 8x oversampling UART transmitter from 9600 to 57600 baud. Uses
-- 1 start bit, 1 stop bit and no parity.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
entity uart_tx is
port (
--System Interface
reset : in std_logic;
sys_clk : in std_logic;
--UART serial interface
DOUT : out std_logic;
--Transmitter interface
baud_en : in std_logic;
tx_fifo_empty : in std_logic;
tx_fifo_read : out std_logic;
tx_byte : in std_logic_vector(7 downto 0);
tx_valid : in std_logic
);
end uart_tx;
architecture behavorial of uart_tx is
signal cnt_rst : std_logic;
signal cnt_en : std_logic;
signal cnt : std_logic_vector(2 downto 0);
signal bit_cnt_en : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal data_reg: std_logic_vector(7 downto 0);
signal send_start : std_logic;
signal send_stop : std_logic;
signal tx_fifo_read_i : std_logic;
signal tx_fifo_read_reg : std_logic;
signal shift : std_logic;
signal data_load : std_logic;
type statetype is (idle, start, data, stop);
signal cs, ns : statetype;
begin
--FIFO read signal
tx_fifo_read <= tx_fifo_read_i and not tx_fifo_read_reg;
--Sequential process for RX Statemachine
--Baud_en is used as an enable to allow state machine to operate at proper
--frequency
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
cs <= idle;
elsif baud_en = '1' then
cs <= ns;
end if;
end if;
end process;
--Next State Combinatorial process
process (cs, cnt, bit_cnt_en, bit_cnt, tx_fifo_empty)
begin
--default values for output signals
send_start <= '0';
send_stop <= '0';
tx_fifo_read_i <= '0';
cnt_rst <= '0';
cnt_en <= '0';
bit_cnt_en <= '0';
shift <= '0';
data_load <= '0';
case cs is
--wait for next byte to transmit
when idle =>
cnt_rst <= '1';
--idle transmit is high, if open collector output change to output
--high impedance during idle
send_stop <= '1';
--when the transmit fifo isn't empty
if tx_fifo_empty = '0' then
ns <= start;
else
ns <= idle;
end if;
--send start bit and read transmit byte
when start =>
send_start <= '1';
--read byte to send
tx_fifo_read_i <= '1';
--Using 8x baud counter from receiver so count 8 times
if cnt = "111" then
data_load <= '1';
ns <= data;
else
data_load <= '0';
ns <= start;
end if;
--send data bits
when data =>
--Using 8x baud counter from receiver so count 8 times
if cnt = "111" then
--shift out next serial bit
shift <= '1';
--increment bit counter
bit_cnt_en <= '1';
--if 8 bits sent, send stop bit
if bit_cnt = "111" then
ns <= stop;
else
ns <= data;
end if;
else
shift <= '0';
bit_cnt_en <= '0';
ns <= data;
end if;
--send stop bit
when stop =>
send_stop <= '1';
--Using 8x baud counter from receiver so count 8 times
if cnt = "111" then
if tx_fifo_empty = '0' then
ns <= start;
else
ns <= idle;
end if;
else
ns <= stop;
end if;
when others =>
ns <= idle;
end case;
end process;
--8x oversampling counter
--oversampling counter is used to determine optimal sampling time of asynchronous DIN
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or cnt_rst = '1' then
cnt <= "000";
--baud_en allows counter to operate at proper baud rate
elsif baud_en = '1' then
cnt <= cnt + "001";
end if;
end if;
end process;
--bit counter
--bit counter determines how many bits have been sent
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
bit_cnt <= "000";
--baud_en allows counter to operate at proper baud rate
elsif baud_en = '1' and bit_cnt_en = '1' then
bit_cnt <= bit_cnt + "001";
end if;
end if;
end process;
--shift register
--shift out the tx_byte serially
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
data_reg <= X"00";
--load in byte from transmit fifo
elsif data_load = '1' then
data_reg <= tx_byte;
--capture serial bit when commanded
elsif shift = '1' and baud_en = '1' then
data_reg <= '0' & data_reg(7 downto 1);
end if;
end if;
end process;
--TX Byte is sent LSB first
--send_start forces output to 0 for start bit
--send_stop muxes 1 to output for stop bit
DOUT <= data_reg(0) and not send_start when send_stop = '0' else '1';
--edge detection register for tx_read
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
tx_fifo_read_reg <= '0';
else
tx_fifo_read_reg <= tx_fifo_read_i;
end if;
end if;
end process;
end behavorial;
|
mit
|
1de7940da00666a69a6773b0ee5e53f6
| 0.598089 | 3.018246 | false | false | false | false |
spoorcc/realtimestagram
|
src/vignette_tb.vhd
| 2 | 5,131 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity vignette_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/vignette_output.pgm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight; --! Height of input image
vignette_x_c: real := 1.0; --! Strength of vignette in x direction
vignette_y_c: real := 1.0 --! Strength of vignette in y direction
);
end entity;
--======================================================================================--
architecture structural of vignette_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 4
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
pixel_from_file: out std_logic_vector;
pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component vignette is
generic (
wordsize: integer := const_wordsize;
width: integer := image_width;
height: integer := image_height;
lut_x: array_pixel := create_sine_lut(image_width, vignette_x_c);
lut_y: array_pixel := create_sine_lut(image_height, vignette_y_c)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
h_count: in std_logic_vector;
v_count: in std_logic_vector;
pixel_i: in std_logic_vector;
pixel_o: out std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: vignette
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
gpl-2.0
|
7fe0b07285e1ac03b30cf3650b57cb24
| 0.464822 | 4.573084 | false | false | false | false |
tejainece/VHDLExperiments
|
FloatingPointMul23/MyTypes.vhd
| 1 | 2,133 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package MyTypes is
subtype PairT is std_logic_vector(1 downto 0);
type PairArr is array (integer range <>) of PairT;
--type SumArr is array (o to num_sum) of std_logic_vector(1 downto 0);
function log2_ceil(N: integer) return positive;
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end MyTypes;
package body MyTypes is
function log2_ceil(N : integer) return positive is
begin
if (N <= 2) then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end MyTypes;
|
gpl-3.0
|
35725aae91a6c1c957bdcf0b52960c56
| 0.638537 | 3.104803 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/resetctrl/reset_ctrl.vhd
| 1 | 738 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity reset_ctrl is
port(
I_clk: in std_logic;
I_reset: in std_logic; -- input for "active high" reset signal
I_reset_inv: in std_logic; -- input for "active low" reset signal
O_reset: out std_logic -- reset output, "active high"
);
end reset_ctrl;
architecture Behavioral of reset_ctrl is
signal clockcounter: integer range 0 to 15 := 15;
begin
process(I_clk)
begin
if rising_edge(I_clk) then
O_reset <= '0';
if clockcounter /= 0 then
O_reset <= '1';
clockcounter <= clockcounter - 1;
end if;
if I_reset = '1' or I_reset_inv = '0' then
clockcounter <= 15;
end if;
end if;
end process;
end Behavioral;
|
mit
|
325986e3912921c40caf0106461c315b
| 0.647696 | 2.871595 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/a2dtiming.vhd
| 1 | 28,767 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : a2dtiming.vhf
-- /___/ /\ Timestamp : 02/10/2006 15:13:44
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w a2dtiming.sch a2dtiming.vhf
--Design Name: a2dtiming
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD_MXILINX_a2dtiming is
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end FD_MXILINX_a2dtiming;
architecture BEHAVIORAL of FD_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
signal XLXN_4 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component FDCP
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
begin
I_36_43 : GND
port map (G=>XLXN_4);
U0 : FDCP
port map (C=>C,
CLR=>XLXN_4,
D=>D,
PRE=>XLXN_4,
Q=>Q);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FDC_MXILINX_a2dtiming is
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end FDC_MXILINX_a2dtiming;
architecture BEHAVIORAL of FDC_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
signal XLXN_5 : std_logic;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component FDCP
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCP : component is "BLACK_BOX";
begin
I_36_55 : GND
port map (G=>XLXN_5);
U0 : FDCP
port map (C=>C,
CLR=>CLR,
D=>D,
PRE=>XLXN_5,
Q=>Q);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FTCE_MXILINX_a2dtiming is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end FTCE_MXILINX_a2dtiming;
architecture BEHAVIORAL of FTCE_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
signal TQ : std_logic;
signal Q_DUMMY : std_logic;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q <= Q_DUMMY;
I_36_32 : XOR2
port map (I0=>T,
I1=>Q_DUMMY,
O=>TQ);
I_36_35 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>TQ,
Q=>Q_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity CB8CE_MXILINX_a2dtiming is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q : out std_logic_vector (7 downto 0);
TC : out std_logic);
end CB8CE_MXILINX_a2dtiming;
architecture BEHAVIORAL of CB8CE_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal T2 : std_logic;
signal T3 : std_logic;
signal T4 : std_logic;
signal T5 : std_logic;
signal T6 : std_logic;
signal T7 : std_logic;
signal XLXN_1 : std_logic;
signal Q_DUMMY : std_logic_vector (7 downto 0);
signal TC_DUMMY : std_logic;
component AND5
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component FTCE_MXILINX_a2dtiming
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of Q0 : label is "Q0_6";
attribute HU_SET of Q1 : label is "Q1_7";
attribute HU_SET of Q2 : label is "Q2_3";
attribute HU_SET of Q3 : label is "Q3_4";
attribute HU_SET of Q4 : label is "Q4_5";
attribute HU_SET of Q5 : label is "Q5_2";
attribute HU_SET of Q6 : label is "Q6_1";
attribute HU_SET of Q7 : label is "Q7_0";
begin
Q(7 downto 0) <= Q_DUMMY(7 downto 0);
TC <= TC_DUMMY;
I_36_1 : AND5
port map (I0=>Q_DUMMY(7),
I1=>Q_DUMMY(6),
I2=>Q_DUMMY(5),
I3=>Q_DUMMY(4),
I4=>T4,
O=>TC_DUMMY);
I_36_2 : AND2
port map (I0=>Q_DUMMY(4),
I1=>T4,
O=>T5);
I_36_11 : AND3
port map (I0=>Q_DUMMY(5),
I1=>Q_DUMMY(4),
I2=>T4,
O=>T6);
I_36_15 : AND4
port map (I0=>Q_DUMMY(3),
I1=>Q_DUMMY(2),
I2=>Q_DUMMY(1),
I3=>Q_DUMMY(0),
O=>T4);
I_36_16 : VCC
port map (P=>XLXN_1);
I_36_24 : AND2
port map (I0=>Q_DUMMY(1),
I1=>Q_DUMMY(0),
O=>T2);
I_36_26 : AND3
port map (I0=>Q_DUMMY(2),
I1=>Q_DUMMY(1),
I2=>Q_DUMMY(0),
O=>T3);
I_36_28 : AND4
port map (I0=>Q_DUMMY(6),
I1=>Q_DUMMY(5),
I2=>Q_DUMMY(4),
I3=>T4,
O=>T7);
I_36_31 : AND2
port map (I0=>CE,
I1=>TC_DUMMY,
O=>CEO);
Q0 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>XLXN_1,
Q=>Q_DUMMY(0));
Q1 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>Q_DUMMY(0),
Q=>Q_DUMMY(1));
Q2 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T2,
Q=>Q_DUMMY(2));
Q3 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T3,
Q=>Q_DUMMY(3));
Q4 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T4,
Q=>Q_DUMMY(4));
Q5 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T5,
Q=>Q_DUMMY(5));
Q6 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T6,
Q=>Q_DUMMY(6));
Q7 : FTCE_MXILINX_a2dtiming
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T7,
Q=>Q_DUMMY(7));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity BUFE4_MXILINX_a2dtiming is
port ( E : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic);
end BUFE4_MXILINX_a2dtiming;
architecture BEHAVIORAL of BUFE4_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
begin
I_36_37 : BUFE
port map (E=>E,
I=>I3,
O=>O3);
I_36_38 : BUFE
port map (E=>E,
I=>I2,
O=>O2);
I_36_39 : BUFE
port map (E=>E,
I=>I1,
O=>O1);
I_36_40 : BUFE
port map (E=>E,
I=>I0,
O=>O0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity INV4_MXILINX_a2dtiming is
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic);
end INV4_MXILINX_a2dtiming;
architecture BEHAVIORAL of INV4_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
begin
I_36_37 : INV
port map (I=>I3,
O=>O3);
I_36_38 : INV
port map (I=>I2,
O=>O2);
I_36_39 : INV
port map (I=>I1,
O=>O1);
I_36_40 : INV
port map (I=>I0,
O=>O0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity D3_8E_MXILINX_a2dtiming is
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end D3_8E_MXILINX_a2dtiming;
architecture BEHAVIORAL of D3_8E_MXILINX_a2dtiming is
attribute BOX_TYPE : string ;
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
begin
I_36_30 : AND4
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D7);
I_36_31 : AND4B1
port map (I0=>A0,
I1=>A2,
I2=>A1,
I3=>E,
O=>D6);
I_36_32 : AND4B1
port map (I0=>A1,
I1=>A2,
I2=>A0,
I3=>E,
O=>D5);
I_36_33 : AND4B2
port map (I0=>A1,
I1=>A0,
I2=>A2,
I3=>E,
O=>D4);
I_36_34 : AND4B1
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>E,
O=>D3);
I_36_35 : AND4B2
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>E,
O=>D2);
I_36_36 : AND4B2
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D1);
I_36_37 : AND4B3
port map (I0=>A2,
I1=>A1,
I2=>A0,
I3=>E,
O=>D0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity a2dtiming is
port ( A2DINTRP : in std_logic;
A2DSTAT : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
LBSD3 : in std_logic;
ONEPPS : in std_logic;
PLLOUT : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
SA3 : in std_logic;
SIORW : in std_logic;
D2A0 : in std_logic;
A2DCLK : out std_logic;
A2DCS0N : out std_logic;
A2DCS1N : out std_logic;
A2DCS2N : out std_logic;
A2DCS3N : out std_logic;
A2DCS4N : out std_logic;
A2DCS5N : out std_logic;
A2DCS6N : out std_logic;
A2DCS7N : out std_logic;
A2DIOEBL : out std_logic;
A2DRS : out std_logic;
A2DRWN : out std_logic;
A2DSYNC : out std_logic;
FIFOLDCK : out std_logic;
IRQFF : out std_logic;
PRESYNC : out std_logic);
end a2dtiming;
architecture BEHAVIORAL of a2dtiming is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal ACTR : std_logic_vector (7 downto 0);
signal ADCLKEN : std_logic;
signal A2DCS : std_logic;
signal PRESYNCN : std_logic;
signal XLXN_17 : std_logic;
signal XLXN_18 : std_logic;
signal XLXN_19 : std_logic;
signal XLXN_29 : std_logic;
signal XLXN_30 : std_logic;
signal XLXN_31 : std_logic;
signal XLXN_32 : std_logic;
signal XLXN_33 : std_logic;
signal XLXN_34 : std_logic;
signal XLXN_35 : std_logic;
signal XLXN_36 : std_logic;
signal XLXN_128 : std_logic;
signal XLXN_155 : std_logic;
signal XLXN_223 : std_logic;
signal XLXN_229 : std_logic;
signal XLXN_230 : std_logic;
signal XLXN_271 : std_logic;
signal XLXN_317 : std_logic;
signal XLXN_335 : std_logic;
signal XLXN_340 : std_logic;
signal XLXN_347 : std_logic;
signal XLXN_364 : std_logic;
signal XLXN_370 : std_logic;
signal XLXN_394 : std_logic;
signal XLXN_399 : std_logic;
signal XLXN_401 : std_logic;
signal XLXN_402 : std_logic;
signal XLXN_403 : std_logic;
signal XLXN_404 : std_logic;
signal XLXN_405 : std_logic;
signal XLXN_446 : std_logic;
signal XLXN_455 : std_logic;
signal XLXN_468 : std_logic;
signal XLXN_469 : std_logic;
signal XLXN_472 : std_logic;
signal IRQFF_DUMMY : std_logic;
signal A2DSYNC_DUMMY : std_logic;
signal A2DCLK_DUMMY : std_logic;
signal A2DIOEBL_DUMMY : std_logic;
signal PRESYNC_DUMMY : std_logic;
signal A2DRS_DUMMY : std_logic;
-- signal A2DCS_Hold : std_logic;
-- signal disable : std_logic;
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
component BUFE4_MXILINX_a2dtiming
port ( E : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic);
end component;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component FDC_MXILINX_a2dtiming
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component D3_8E_MXILINX_a2dtiming
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic);
end component;
component INV4_MXILINX_a2dtiming
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic);
end component;
component NAND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component CB8CE_MXILINX_a2dtiming
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q : out std_logic_vector (7 downto 0);
TC : out std_logic);
end component;
component FD_MXILINX_a2dtiming
port ( C : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component AND3B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
component AND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
component NAND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of NAND3B1 : component is "BLACK_BOX";
attribute HU_SET of XLXI_6 : label is "XLXI_6_8";
attribute HU_SET of XLXI_63 : label is "XLXI_63_9";
attribute HU_SET of XLXI_93 : label is "XLXI_93_13";
attribute HU_SET of XLXI_99 : label is "XLXI_99_10";
attribute HU_SET of XLXI_100 : label is "XLXI_100_11";
attribute HU_SET of XLXI_101 : label is "XLXI_101_12";
attribute HU_SET of XLXI_127 : label is "XLXI_127_14";
attribute HU_SET of XLXI_131 : label is "XLXI_131_15";
attribute HU_SET of XLXI_138 : label is "XLXI_138_16";
attribute HU_SET of XLXI_141 : label is "XLXI_141_17";
attribute HU_SET of XLXI_181 : label is "XLXI_181_18";
attribute HU_SET of XLXI_185 : label is "XLXI_185_19";
begin
A2DCLK <= A2DCLK_DUMMY;
A2DIOEBL <= A2DIOEBL_DUMMY;
A2DRS <= A2DRS_DUMMY;
A2DSYNC <= A2DSYNC_DUMMY;
IRQFF <= IRQFF_DUMMY;
PRESYNC <= PRESYNC_DUMMY;
-- disable <= XLXN_401 and XLXN_128;
-- A2DCS_Hold <= (XLXN_401) OR (NOT ACTR(4));
-- XLXI_my : GND
-- port map (G=>disable);
XLXI_2 : INV
port map (I=>ACTR(4),
O=>XLXN_340);
XLXI_6 : BUFE4_MXILINX_a2dtiming
port map (E=>XLXN_128,
I0=>XLXN_394,
I1=>SA1,
I2=>SA2,
I3=>SA3,
O0=>XLXN_399,
O1=>XLXN_17,
O2=>XLXN_18,
O3=>XLXN_19);
XLXI_7 : BUFE
port map (E=>XLXN_128,
I=>XLXN_223,
O=>A2DCS);
XLXI_8 : BUFE
port map (E=>FIFOCTL(1),
I=>XLXN_347,
O=>A2DCS);
XLXI_37 : INV
port map (I=>FIFOCTL(1),
O=>XLXN_128);
XLXI_60 : AND2
port map (I0=>FIFOCTL(1),
I1=>IRQFF_DUMMY,
O=>XLXN_155);
XLXI_63 : FDC_MXILINX_a2dtiming
port map (C=>A2DINTRP,
CLR=>IRQFF_DUMMY,
D=>XLXN_317,
Q=>XLXN_335);
XLXI_91 : OR2
port map (I0=>A2DSTAT,
I1=>D2A0,
O=>A2DIOEBL_DUMMY);
XLXI_93 : FDC_MXILINX_a2dtiming
port map (C=>FIFOCTL(3),
CLR=>XLXN_229,
D=>FIFOCTL(2),
Q=>PRESYNC_DUMMY);
XLXI_94 : AND2
port map (I0=>XLXN_230,
I1=>FIFOCTL(4),
O=>XLXN_229);
XLXI_96 : INV
port map (I=>ONEPPS,
O=>XLXN_230);
XLXI_98 : AND2
port map (I0=>SIORW,
I1=>A2DIOEBL_DUMMY,
O=>XLXN_223);
XLXI_80 : INV
port map (I=>XLXN_401,
O=>XLXN_402);
XLXI_81 : INV
port map (I=>XLXN_402,
O=>XLXN_403);
XLXI_82 : INV
port map (I=>XLXN_403,
O=>XLXN_404);
XLXI_83 : INV
port map (I=>XLXN_404,
O=>XLXN_405);
XLXI_99 : D3_8E_MXILINX_a2dtiming
port map (A0=>XLXN_17,
A1=>XLXN_18,
A2=>XLXN_19,
-- E=>disable,
-- E=>XLXN_401,
E=>XLXN_405,
-- E=>A2DCS_Hold,
D0=>XLXN_29,
D1=>XLXN_30,
D2=>XLXN_31,
D3=>XLXN_32,
D4=>XLXN_33,
D5=>XLXN_34,
D6=>XLXN_35,
D7=>XLXN_36);
XLXI_100 : INV4_MXILINX_a2dtiming
port map (I0=>XLXN_32,
I1=>XLXN_31,
I2=>XLXN_30,
I3=>XLXN_29,
O0=>A2DCS3N,
O1=>A2DCS2N,
O2=>A2DCS1N,
O3=>A2DCS0N);
XLXI_101 : INV4_MXILINX_a2dtiming
port map (I0=>XLXN_36,
I1=>XLXN_35,
I2=>XLXN_34,
I3=>XLXN_33,
O0=>A2DCS7N,
O1=>A2DCS6N,
O2=>A2DCS5N,
O3=>A2DCS4N);
XLXI_116 : NAND2
port map (I0=>LBSD3,
I1=>A2DIOEBL_DUMMY,
O=>XLXN_271);
XLXI_117 : NAND2
port map (I0=>XLXN_271,
I1=>XLXN_128,
O=>A2DRWN);
XLXI_119 : VCC
port map (P=>XLXN_317);
XLXI_127 : BUFE4_MXILINX_a2dtiming
port map (E=>FIFOCTL(1),
I0=>ACTR(0),
I1=>ACTR(1),
I2=>ACTR(2),
I3=>ACTR(3),
O0=>XLXN_399,
O1=>XLXN_17,
O2=>XLXN_18,
O3=>XLXN_19);
XLXI_131 : CB8CE_MXILINX_a2dtiming
port map (C=>A2DCLK_DUMMY,
CE=>XLXN_340,
CLR=>XLXN_155,
CEO=>open,
Q(7 downto 0)=>ACTR(7 downto 0),
TC=>open);
XLXI_138 : FDC_MXILINX_a2dtiming
port map (C=>A2DCLK_DUMMY,
CLR=>XLXN_364,
D=>XLXN_335,
Q=>IRQFF_DUMMY);
XLXI_139 : INV
port map (I=>FIFOCTL(1),
O=>XLXN_364);
XLXI_141 : FD_MXILINX_a2dtiming
port map (C=>SIORW,
D=>XLXN_370,
Q=>ADCLKEN);
XLXI_143 : VCC
port map (P=>XLXN_370);
XLXI_144 : AND2
port map (I0=>ADCLKEN,
I1=>PLLOUT,
O=>A2DCLK_DUMMY);
XLXI_154 : AND2B1
port map (I0=>XLXN_446,
I1=>A2DCS,
O=>XLXN_401);
XLXI_155 : GND
port map (G=>XLXN_394);
XLXI_165 : BUFE
port map (E=>XLXN_128,
I=>A2DSTAT,
O=>A2DRS_DUMMY);
XLXI_166 : BUFE
port map (E=>FIFOCTL(1),
I=>XLXN_455,
O=>A2DRS_DUMMY);
XLXI_175 : AND2B1
port map (I0=>FIFOCTL(6),
I1=>XLXN_399,
-- I1=>A2DCS,
O=>XLXN_446);
XLXI_177 : AND2
port map (I0=>FIFOCTL(6),
I1=>XLXN_468,
O=>XLXN_455);
XLXI_180 : INV
port map (I=>ACTR(0),
O=>XLXN_468);
XLXI_181 : FDC_MXILINX_a2dtiming
port map (C=>PRESYNCN,
CLR=>A2DSYNC_DUMMY,
D=>XLXN_469,
Q=>XLXN_472);
XLXI_183 : VCC
port map (P=>XLXN_469);
XLXI_184 : INV
port map (I=>PRESYNC_DUMMY,
O=>PRESYNCN);
XLXI_185 : FD_MXILINX_a2dtiming
port map (C=>A2DCLK_DUMMY,
D=>XLXN_472,
Q=>A2DSYNC_DUMMY);
XLXI_187 : AND3B2
port map (I0=>A2DCLK_DUMMY,
I1=>IRQFF_DUMMY,
I2=>XLXN_340,
O=>XLXN_347);
XLXI_188 : NAND3B1
port map (I0=>XLXN_446,
I1=>A2DCS,
I2=>PRESYNCN,
O=>FIFOLDCK);
end BEHAVIORAL;
|
gpl-2.0
|
ecfc31e2ea53b33190cf610e1e758e0d
| 0.465325 | 3.403573 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/spi/spimaster_tb.vhd
| 1 | 1,438 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spimaster_tb is
end spimaster_tb;
architecture Behavior of spimaster_tb is
constant I_clk_period: time := 10 ns;
signal I_clk: std_logic := '0';
signal I_tx_data: std_logic_vector(7 downto 0) := X"00";
signal I_tx_start: boolean := false;
signal I_spi_miso: std_logic := '0';
signal O_spi_clk: std_logic := '0';
signal O_spi_mosi: std_logic := '0';
signal O_rx_data: std_logic_vector(7 downto 0) := X"00";
signal O_busy: boolean := false;
begin
-- instantiate unit under test
uut: entity work.spimaster port map(
I_clk => I_clk,
I_tx_data => I_tx_data,
I_tx_start => I_tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => O_rx_data,
O_busy => O_busy
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
stimuli: process
begin
wait until falling_edge(I_clk);
I_spi_miso <= '1';
I_tx_data <= "10101010";
I_tx_start <= true;
wait until O_busy = true;
I_tx_start <= false;
wait until O_busy = false;
I_tx_data <= X"00";
I_spi_miso <= '0';
I_tx_start <= true;
wait until O_busy = true;
I_tx_start <= false;
wait until O_busy = false;
wait for 10*I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end Behavior;
|
mit
|
86f5e1cf0e0679d82ef970cd96b6524f
| 0.625174 | 2.567857 | false | false | false | false |
miree/vhdl_cores
|
fifo/fifo_passive_out/testbench.vhd
| 2 | 3,978 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- package with component to test on this testbench
use work.fifo_pkg.all;
use work.guarded_fifo_pkg.all;
entity testbench is
end entity;
architecture simulation of testbench is
-- clock generation
constant clk_period : time := 5 ns;
-- signals to connect to fifo
constant depth : integer := 2; -- the number of fifo entries is 2**depth
constant bit_width : integer := 32; -- number of bits in each entry
signal clk, rst : std_logic;
signal d, q : std_logic_vector ( bit_width-1 downto 0 );
signal push, pop : std_logic;
signal full, empty : std_logic;
-- the value that is pushed to the fifo
signal ctr : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
-- the value that is expected to be read from the fifo (initialized with -1)
signal expected : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
begin
-- instantiate device under test (dut)
dut : work.guarded_fifo_pkg.guarded_fifo
generic map (
depth => depth ,
bit_width => bit_width
)
port map (
clk_i => clk,
rst_i => rst,
d_i => ctr,
q_o => q,
push_i => push,
pop_i => pop,
full_o => full,
empty_o => empty
);
clk_gen: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
rst_initial: process
begin
rst <= '1';
wait for clk_period*20;
rst <= '0';
wait;
end process;
p_read_write : process
begin
push <= '0';
pop <= '0';
--=============================
-- fill fifo
--=============================
--wait for clk_period*40.5;
wait until falling_edge(rst);
for i in 0 to 12 loop
-- convert an integer into std_logic_vector
-- i_slv := std_logic_vector(to_unsigned(i,8));
wait until rising_edge(clk);
d <= ctr;
push <= '1';
if to_integer(unsigned(ctr)) = 2 then
pop <= '1';
else
pop <= '0';
end if;
--push <= '0';
-- wait for clk_period*5;
end loop;
push <= '0';
--=============================
-- empty fifo
--=============================
wait for clk_period*40;
for i in 0 to 13 loop
pop <= '1';
wait for clk_period;
pop <= '0';
wait for clk_period*5;
-- expected := std_logic_vector(unsigned(expected) + 1);
-- typecasts can be avoided when using the library use ieee.std_logic_unsigned.all;
end loop;
for i in 0 to 12 loop
-- convert an integer into std_logic_vector
-- i_slv := std_logic_vector(to_unsigned(i,8));
wait until rising_edge(clk);
d <= ctr;
push <= '1';
--push <= '0';
-- wait for clk_period*5;
end loop;
push <= '0';
end process;
check: process
begin
wait until rising_edge(clk);
if empty = '0' and pop = '1' then
assert unsigned(q) = unsigned(expected)
report "We didn't get what we expect ("
& integer'image(to_integer(unsigned(q)))
& " /= "
& integer'image(to_integer(unsigned(expected)))
& ")";
end if;
end process;
-- this process increments the counter (that is the value which is written to the fifo)
-- only on rising clock edges when the acknowledge signal was sent back from the fifo, i.e.
-- if a value was successfully pushed into the fifo.
p_increment_ctr : process(clk)
begin
if rising_edge(clk) then
if full = '0' and push = '1' then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
end if;
end process;
p_increment_expected : process(clk)
begin
if rising_edge(clk) then
if empty = '0' and pop = '1' then
expected <= std_logic_vector(unsigned(expected) + 1);
end if;
end if;
end process;
end architecture;
|
mit
|
16bc2489b2311c6e7a49e7476394edae
| 0.551785 | 3.567713 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 5/Parte 2/SeqShiftUnit_Demo.vhd
| 1 | 859 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity SeqShiftUnit_Demo is
port( SW : in std_logic_vector(13 downto 0);
CLOCK_50 : in std_logic;
LEDR : out std_logic_vector(7 downto 0));
end SeqShiftUnit_Demo;
architecture Structural of SeqShiftUnit_Demo is
signal s_clk : std_logic;
begin
seqshiftunit: entity work.SeqShiftUnit(RTL)
port map(clk => s_clk,
dataIn => SW(7 downto 0),
siLeft => SW(8),
siRight => SW(9),
loadEn => SW(10),
rotate => SW(11),
dirLeft => SW(12),
shArith => SW(13),
dataOut =>LEDR(7 downto 0));
freqdivider: entity work.FreqDivider(Behavioral)
generic map(K => 50000000)
port map(clkIn => CLOCK_50,
clkOut => s_clk);
end Structural;
|
gpl-2.0
|
9756fda80acdbd93cb1022f13385e757
| 0.568102 | 3.316602 | false | false | false | false |
vinodpa/openPowerlink-FPGA
|
Examples/ipcore/xilinx/openmac/src/fifo_read.vhd
| 3 | 4,800 |
-------------------------------------------------------------------------------
-- read controller of the fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the read controler.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_read_ctrl is
generic(N: natural:=4);
port(
clkr, resetr: in std_logic;
w_ptr_in: in std_logic_vector(N downto 0);
rd: in std_logic;
r_empty: out std_logic;
r_full: out std_logic;
r_ptr_out: out std_logic_vector(N downto 0);
r_addr: out std_logic_vector(N-1 downto 0);
r_elements: out std_logic_vector(N-1 downto 0)
);
end fifo_read_ctrl;
architecture gray_arch of fifo_read_ctrl is
signal r_ptr_reg, r_ptr_next: std_logic_vector(N downto 0);
signal w_ptr_reg, w_ptr_next : std_logic_vector(N downto 0) := (others => '0');
signal gray1, bin, bin1: std_logic_vector(N downto 0);
signal raddr_all: std_logic_vector(N-1 downto 0);
signal raddr_msb,waddr_msb: std_logic;
signal empty_flag, full_flag: std_logic;
signal r_elements_wr, r_elements_rd, r_elements_diff : std_logic_vector(N downto 0);
signal r_elements_reg, r_elements_next : std_logic_vector(N-1 downto 0);
begin
-- register
process(clkr,resetr)
begin
if (resetr='1') then
r_ptr_reg <= (others=>'0');
--w_ptr_reg <= (others => '0');
r_elements_reg <= (others => '0');
elsif (clkr'event and clkr='1') then
r_ptr_reg <= r_ptr_next;
--w_ptr_reg <= w_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (N+1)-bit Gray counter
bin <= r_ptr_reg xor ('0' & bin(N downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor ('0' & bin1(N downto 1));
-- update read pointer
r_ptr_next <= gray1 when rd='1' and empty_flag='0' else
r_ptr_reg;
-- save write pointer
w_ptr_next <= w_ptr_in;
-- N-bit Gray counter
raddr_msb <= r_ptr_reg(N) xor r_ptr_reg(N-1);
raddr_all <= raddr_msb & r_ptr_reg(N-2 downto 0);
waddr_msb <= w_ptr_in(N) xor w_ptr_in(N-1);
-- check for FIFO read empty
empty_flag <=
'1' when w_ptr_in(N)=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- check for FIFO read full
full_flag <=
'1' when w_ptr_in(N)/=r_ptr_reg(N) and
w_ptr_in(N-2 downto 0)=r_ptr_reg(N-2 downto 0) and
raddr_msb = waddr_msb else
'0';
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= w_ptr_in xor ('0' & r_elements_rd(N downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
r_addr <= raddr_all;
r_ptr_out <= r_ptr_reg;
r_elements <= r_elements_reg;
r_empty <= empty_flag;
r_full <= full_flag;
end gray_arch;
|
gpl-2.0
|
e895329d64007c1f304ed1f920af5728
| 0.626875 | 3.480783 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/Constantes.vhd
| 1 | 9,678 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:05:59 01/09/2013
-- Design Name:
-- Module Name: Constantes - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Constantes is
port ( hcnt: in std_logic_vector(8 downto 0); -- horizontal pixel counter
vcnt: in std_logic_vector(9 downto 0);
tipo: in std_logic_vector(2 downto 0);
pintar: out std_logic;
pos_x:in std_logic_vector (8 downto 0);
pos_y: in std_logic_vector(9 downto 0)
);
end Constantes;
architecture Behavioral of Constantes is
signal Px: std_logic_vector(2 downto 0);
signal Py: std_logic_vector(3 downto 0);
begin
Px<=hcnt(2 downto 0);
Py<=vcnt(3 downto 0);
process(hcnt, vcnt)
begin
pintar<='0';
if hcnt >= pos_x and hcnt < pos_x + 8 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(II(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="010" then --STATE:
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="011" then --Registros:
if(R(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(M(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x +8 and hcnt < pos_x + 16 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(N(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
if(L(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="010" then --JUMPDIR:
if(T(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="011" then --Registros:
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x + 16 and hcnt < pos_x + 24 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
if(U(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="010" then --JUMPDIR:
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="011" then --Registros:
if(G(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(M(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x + 24 and hcnt < pos_x + 32 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(T(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
if(DOSPUNTOS(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="010" then --JUMPDIR:
if(T(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="011" then --Registros:
if(II(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x + 32 and hcnt < pos_x + 40 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(R(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="011" then --Registros:
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(R(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x +40 and hcnt < pos_x + 48 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(U(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="01" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
if(DOSPUNTOS(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="011" then --Registros:
if(T(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(II(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x +48 and hcnt < pos_x + 56 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(C(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
pintar<='0';
elsif tipo="011" then --Registros:
if(R(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x + 56 and hcnt < pos_x + 64 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(T(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
pintar<='0';
elsif tipo="011" then --Registros:
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
if(DOSPUNTOS(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x +64 and hcnt < pos_x + 72 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(II(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
pintar<='0';
elsif tipo="011" then --Registros:
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
pintar<='0';
end if;
end if;
end if;
if hcnt >= pos_x +72 and hcnt < pos_x + 80 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
pintar<='0';
elsif tipo="011" then --Registros:
if(DOSPUNTOS(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="100" then --Memoria:
pintar<='0';
end if;
end if;
end if;
if hcnt >= pos_x+80 and hcnt < pos_x + 88 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(N(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
pintar<='0';
elsif tipo="011" then --Registros:
pintar<='0';
elsif tipo="100" then --Memoria:
pintar<='0';
end if;
end if;
end if;
if hcnt >= pos_x+88 and hcnt < pos_x + 96 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if tipo="000" then --Instruction:
if(DOSPUNTOS(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif tipo="001" then --ALU:
pintar<='0';
elsif tipo="010" then --JUMPDIR:
pintar<='0';
elsif tipo="011" then --Registros:
pintar<='0';
elsif tipo="100" then --Memoria:
pintar<='0';
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
41e9cd88ec469c348b56a06c94a5fae0
| 0.576875 | 2.937178 | false | false | false | false |
tejainece/VHDLExperiments
|
BoothPartProdRed/BoothPartProdRed_tb.vhd
| 1 | 3,256 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:01 01/21/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/BoothPartProdRed/BoothPartProdRed_tb.vhd
-- Project Name: BoothPartProdRed
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: BoothPartProdRed
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY BoothPartProdRed_tb IS
END BoothPartProdRed_tb;
ARCHITECTURE behavior OF BoothPartProdRed_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BoothPartProdRed
PORT(
prod0 : IN std_logic_vector(19 downto 0);
prod1 : IN std_logic_vector(20 downto 2);
prod2 : IN std_logic_vector(22 downto 4);
prod3 : IN std_logic_vector(24 downto 6);
prod4 : IN std_logic_vector(26 downto 8);
prod5 : IN std_logic_vector(28 downto 10);
prod6 : IN std_logic_vector(30 downto 12);
prod7 : IN std_logic_vector(31 downto 14);
result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal prod0 : std_logic_vector(19 downto 0) := (others => '0');
signal prod1 : std_logic_vector(20 downto 2) := (others => '0');
signal prod2 : std_logic_vector(22 downto 4) := (others => '0');
signal prod3 : std_logic_vector(24 downto 6) := (others => '0');
signal prod4 : std_logic_vector(26 downto 8) := (others => '0');
signal prod5 : std_logic_vector(28 downto 10) := (others => '0');
signal prod6 : std_logic_vector(30 downto 12) := (others => '0');
signal prod7 : std_logic_vector(31 downto 14) := (others => '0');
--Outputs
signal result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
prod0 <= "11111111111111111111";
prod1 <= "1111111111111111111";
prod2 <= "0000000000000000001";
prod3 <= "1111111111111111111";
prod4 <= "0000000000000000001";
prod5 <= "0000000000000000001";
prod6 <= "0000000000000000001";
prod7 <= "000000000000000001";
wait for 100 ns;
wait for 100 ns;
wait;
end process;
END;
|
gpl-3.0
|
aeaa48d03c2c939ae8b06949c6cbf5fa
| 0.60688 | 3.885442 | false | true | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/tipos.vhd
| 2 | 6,885 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package tipos is
type ESTADOS is (F, ID, EX, MEM, WB);
type matrix is array(0 to 15) of std_logic_vector(0 to 7);
constant DOSPUNTOS: matrix:=(
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00011100",
"00011100",
"00011100",
"00000000",
"00000000",
"00000000",
"00011100",
"00011100",
"00011100",
"00000000"
);
constant VACIO: matrix:=(
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000"
);
constant CERO: matrix:=(
"00000000",
"01111110",
"01111110",
"01111110",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"01111110",
"01111110",
"01111110",
"00000000"
);
constant UNO: matrix:=(
"00000000",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"01111110",
"00000000"
);
constant A: matrix:=(
"00000000",
"00111100",
"00111100",
"01111110",
"01100110",
"01100110",
"01100110",
"01100110",
"01111110",
"01111110",
"01111110",
"01100110",
"01100110",
"01100110",
"01100110",
"00000000"
);
constant B: matrix:=(
"00000000",
"01111100",
"01111110",
"01100110",
"01100110",
"01100110",
"01100100",
"01111100",
"01111100",
"01100100",
"01100110",
"01100110",
"01100110",
"01111110",
"01111100",
"00000000"
);
constant C: matrix:=(
"00000000",
"00111110",
"01111110",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01111110",
"00111110",
"00000000"
);
constant E: matrix:=(
"00000000",
"01111110",
"01111110",
"01100000",
"01100000",
"01100000",
"01100000",
"01111110",
"01111110",
"01100000",
"01100000",
"01100000",
"01100000",
"01111110",
"01111110",
"00000000"
);
constant FF: matrix:=(
"00000000",
"01111110",
"01111110",
"01100000",
"01100000",
"01100000",
"01100000",
"01111100",
"01111100",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"00000000"
);
constant D: matrix:=(
"00000000",
"01110000",
"01111000",
"01101100",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01101100",
"01111000",
"01110000",
"00000000"
);
constant G: matrix:=(
"00000000",
"00111110",
"01111110",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01101110",
"01101110",
"01100110",
"01100110",
"01100110",
"01111110",
"00111100",
"00000000"
);
constant I: matrix:=(
"00000000",
"00011000",
"00011000",
"00000000",
"00000000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00000000"
);
constant II: matrix:=(
"00000000",
"01111110",
"01111110",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"01111110",
"01111110",
"00000000"
);
constant J: matrix:=(
"00000000",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"00000110",
"01100110",
"01100110",
"01100110",
"01111110",
"00111100",
"00000000"
);
constant L: matrix:=(
"00000000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100110",
"01100110",
"01100110",
"01111110",
"01111110",
"00000000"
);
constant N: matrix:=(
"00000000",
"01000010",
"01100010",
"01100010",
"01100010",
"01010010",
"01010010",
"01010010",
"01001010",
"01001010",
"01001010",
"01000110",
"01000110",
"01000110",
"01000010",
"00000000"
);
constant M: matrix:=(
"00000000",
"01000010",
"01100110",
"01100110",
"01100110",
"01011010",
"01011010",
"01011010",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"01000010",
"00000000"
);
--constant NN: matrix:=(
--"00000000",
--"00011000",
--"00100100",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"01000010",
--"00000000"
--);
constant O: matrix:=(
"00000000",
"00111100",
"01111110",
"01111110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01111110",
"01111110",
"00111100",
"00000000"
);
constant P: matrix:=(
"00000000",
"00111100",
"01111110",
"01100110",
"01100110",
"01100110",
"01100110",
"01111110",
"01111100",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"01100000",
"00000000"
);
constant Q: matrix:=(
"00000000",
"00111100",
"01111110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01111110",
"00111100",
"00001100",
"00000110",
"00000000"
);
constant R: matrix:=(--no me gusta
"00000000",
"00111100",
"01111110",
"01100110",
"01100110",
"01100110",
"01100100",
"01111100",
"01111100",
"01100100",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"00000000"
);
constant S: matrix:=(
"00000000",
"00111110",
"01111110",
"01100000",
"01100000",
"01100000",
"01100000",
"01111100",
"01111110",
"00000110",
"00000110",
"00000110",
"00000110",
"01111110",
"01111100",
"00000000"
);
constant T: matrix:=(
"00000000",
"01111110",
"01111110",
"01111110",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00011000",
"00000000"
);
constant U: matrix:=(
"00000000",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"01111110",
"01111110",
"00111100",
"00000000"
);
constant W: matrix:=(
"00000000",
"01000100",
"01000100",
"01000100",
"01000100",
"01000100",
"01000100",
"01000100",
"01000100",
"01010100",
"01010100",
"01010100",
"01111100",
"01111100",
"01101100",
"00000000"
);
constant X: matrix:=(
"00000000",
"01000010",
"01000010",
"01000010",
"00100100",
"00100100",
"00100100",
"00011000",
"00011000",
"00100100",
"00100100",
"00100100",
"01000010",
"01000010",
"01000010",
"00000000"
);
end tipos;
package body tipos is
end tipos;
|
gpl-2.0
|
8e13c6ef9bd0910831433bd451d0cc24
| 0.609586 | 2.670675 | false | false | false | false |
maikmerten/riscv-tomthumb
|
boards/de0-nano/vhdl/wizpll/wizpll_vga.vhd
| 1 | 14,872 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll_vga.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY wizpll_vga IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END wizpll_vga;
ARCHITECTURE SYN OF wizpll_vga IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2000,
clk0_duty_cycle => 50,
clk0_multiply_by => 1007,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=wizpll_vga",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "wizpll_vga.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2000"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
mit
|
abfaa7411902bd7f29c80c7318371f03
| 0.701049 | 3.377697 | false | false | false | false |
jpcofr/PDUAMaude
|
PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/RAM.vhdl
| 1 | 2,030 |
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: RAM **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por : MGH-DIMENDEZ-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- RAM (Buses de datos independientes in-out)
-- cs
-- _____|_
-- rw -->| |
-- dir(direccion)-->| |--> data_out
-- data_in -->|_______|
--
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM is
Port ( cs,rw : in std_logic;
dir : in std_logic_vector(2 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0));
end RAM;
architecture Behavioral of RAM is
type memoria is array (7 downto 0) of std_logic_vector(7 downto 0);
signal mem: memoria;
begin
process(cs,rw,dir,data_in)
begin
if cs = '1' then
if rw = '0' then -- Read
case dir is
when "000" => data_out <= mem(0);
when "001" => data_out <= mem(1);
when "010" => data_out <= mem(2);
when "011" => data_out <= mem(3);
when "100" => data_out <= mem(4);
when "101" => data_out <= mem(5);
when "110" => data_out <= mem(6);
when "111" => data_out <= mem(7);
when others => data_out <= (others => 'X');
end case;
else -- Write
case dir is
when "000" => mem(0) <= Data_in;
when "001" => mem(1) <= Data_in;
when "010" => mem(2) <= Data_in;
when "011" => mem(3) <= Data_in;
when "100" => mem(4) <= Data_in;
when "101" => mem(5) <= Data_in;
when "110" => mem(6) <= Data_in;
when "111" => mem(7) <= Data_in;
when others => mem(7) <= Data_in;
end case;
end if;
else data_out <= (others => 'Z');
end if;
end process;
end Behavioral;
|
mit
|
52a1f228745411fa8f2c68568a933604
| 0.453202 | 3.191824 | false | false | false | false |
marc0l92/RadioFM_FPGA
|
RadioFM_project/ps7_stub.vhd
| 1 | 36,385 |
----------------------------------------------------------------------------
-- ps7_stub.vhd
-- ZedBoard simple VHDL example
-- Version 1.0
--
-- Copyright (C) 2013 H.Poetzl
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation, either version
-- 2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity ps7_stub is
port (
i2c_sda_i : in std_ulogic;
i2c_sda_o : out std_ulogic;
i2c_sda_tn : out std_ulogic;
--
i2c_scl_i : in std_ulogic;
i2c_scl_o : out std_ulogic;
i2c_scl_tn : out std_ulogic
);
end entity ps7_stub;
architecture RTL of ps7_stub is
begin
PS7_inst : PS7
port map (
DMA0DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA0DAVALID => open, -- out std_ulogic;
DMA0DRREADY => open, -- out std_ulogic;
DMA0RSTN => open, -- out std_ulogic;
DMA1DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA1DAVALID => open, -- out std_ulogic;
DMA1DRREADY => open, -- out std_ulogic;
DMA1RSTN => open, -- out std_ulogic;
DMA2DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA2DAVALID => open, -- out std_ulogic;
DMA2DRREADY => open, -- out std_ulogic;
DMA2RSTN => open, -- out std_ulogic;
DMA3DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA3DAVALID => open, -- out std_ulogic;
DMA3DRREADY => open, -- out std_ulogic;
DMA3RSTN => open, -- out std_ulogic;
EMIOCAN0PHYTX => open, -- out std_ulogic;
EMIOCAN1PHYTX => open, -- out std_ulogic;
EMIOENET0GMIITXD => open, -- out std_logic_vector(7 downto 0);
EMIOENET0GMIITXEN => open, -- out std_ulogic;
EMIOENET0GMIITXER => open, -- out std_ulogic;
EMIOENET0MDIOMDC => open, -- out std_ulogic;
EMIOENET0MDIOO => open, -- out std_ulogic;
EMIOENET0MDIOTN => open, -- out std_ulogic;
EMIOENET0PTPDELAYREQRX => open, -- out std_ulogic;
EMIOENET0PTPDELAYREQTX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYREQRX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYREQTX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYRESPRX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYRESPTX => open, -- out std_ulogic;
EMIOENET0PTPSYNCFRAMERX => open, -- out std_ulogic;
EMIOENET0PTPSYNCFRAMETX => open, -- out std_ulogic;
EMIOENET0SOFRX => open, -- out std_ulogic;
EMIOENET0SOFTX => open, -- out std_ulogic;
EMIOENET1GMIITXD => open, -- out std_logic_vector(7 downto 0);
EMIOENET1GMIITXEN => open, -- out std_ulogic;
EMIOENET1GMIITXER => open, -- out std_ulogic;
EMIOENET1MDIOMDC => open, -- out std_ulogic;
EMIOENET1MDIOO => open, -- out std_ulogic;
EMIOENET1MDIOTN => open, -- out std_ulogic;
EMIOENET1PTPDELAYREQRX => open, -- out std_ulogic;
EMIOENET1PTPDELAYREQTX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYREQRX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYREQTX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYRESPRX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYRESPTX => open, -- out std_ulogic;
EMIOENET1PTPSYNCFRAMERX => open, -- out std_ulogic;
EMIOENET1PTPSYNCFRAMETX => open, -- out std_ulogic;
EMIOENET1SOFRX => open, -- out std_ulogic;
EMIOENET1SOFTX => open, -- out std_ulogic;
EMIOGPIOO => open, -- out std_logic_vector(63 downto 0);
EMIOGPIOTN => open, -- out std_logic_vector(63 downto 0);
EMIOI2C0SCLO => i2c_scl_o, -- out std_ulogic;
EMIOI2C0SCLTN => i2c_scl_tn, -- out std_ulogic;
EMIOI2C0SDAO => i2c_sda_o, -- out std_ulogic;
EMIOI2C0SDATN => i2c_sda_tn, -- out std_ulogic;
EMIOI2C1SCLO => open, -- out std_ulogic;
EMIOI2C1SCLTN => open, -- out std_ulogic;
EMIOI2C1SDAO => open, -- out std_ulogic;
EMIOI2C1SDATN => open, -- out std_ulogic;
EMIOPJTAGTDO => open, -- out std_ulogic;
EMIOPJTAGTDTN => open, -- out std_ulogic;
EMIOSDIO0BUSPOW => open, -- out std_ulogic;
EMIOSDIO0BUSVOLT => open, -- out std_logic_vector(2 downto 0);
EMIOSDIO0CLK => open, -- out std_ulogic;
EMIOSDIO0CMDO => open, -- out std_ulogic;
EMIOSDIO0CMDTN => open, -- out std_ulogic;
EMIOSDIO0DATAO => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO0DATATN => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO0LED => open, -- out std_ulogic;
EMIOSDIO1BUSPOW => open, -- out std_ulogic;
EMIOSDIO1BUSVOLT => open, -- out std_logic_vector(2 downto 0);
EMIOSDIO1CLK => open, -- out std_ulogic;
EMIOSDIO1CMDO => open, -- out std_ulogic;
EMIOSDIO1CMDTN => open, -- out std_ulogic;
EMIOSDIO1DATAO => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO1DATATN => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO1LED => open, -- out std_ulogic;
EMIOSPI0MO => open, -- out std_ulogic;
EMIOSPI0MOTN => open, -- out std_ulogic;
EMIOSPI0SCLKO => open, -- out std_ulogic;
EMIOSPI0SCLKTN => open, -- out std_ulogic;
EMIOSPI0SO => open, -- out std_ulogic;
EMIOSPI0SSNTN => open, -- out std_ulogic;
EMIOSPI0SSON => open, -- out std_logic_vector(2 downto 0);
EMIOSPI0STN => open, -- out std_ulogic;
EMIOSPI1MO => open, -- out std_ulogic;
EMIOSPI1MOTN => open, -- out std_ulogic;
EMIOSPI1SCLKO => open, -- out std_ulogic;
EMIOSPI1SCLKTN => open, -- out std_ulogic;
EMIOSPI1SO => open, -- out std_ulogic;
EMIOSPI1SSNTN => open, -- out std_ulogic;
EMIOSPI1SSON => open, -- out std_logic_vector(2 downto 0);
EMIOSPI1STN => open, -- out std_ulogic;
EMIOTRACECTL => open, -- out std_ulogic;
EMIOTRACEDATA => open, -- out std_logic_vector(31 downto 0);
EMIOTTC0WAVEO => open, -- out std_logic_vector(2 downto 0);
EMIOTTC1WAVEO => open, -- out std_logic_vector(2 downto 0);
EMIOUART0DTRN => open, -- out std_ulogic;
EMIOUART0RTSN => open, -- out std_ulogic;
EMIOUART0TX => open, -- out std_ulogic;
EMIOUART1DTRN => open, -- out std_ulogic;
EMIOUART1RTSN => open, -- out std_ulogic;
EMIOUART1TX => open, -- out std_ulogic;
EMIOUSB0PORTINDCTL => open, -- out std_logic_vector(1 downto 0);
EMIOUSB0VBUSPWRSELECT => open, -- out std_ulogic;
EMIOUSB1PORTINDCTL => open, -- out std_logic_vector(1 downto 0);
EMIOUSB1VBUSPWRSELECT => open, -- out std_ulogic;
EMIOWDTRSTO => open, -- out std_ulogic;
EVENTEVENTO => open, -- out std_ulogic;
EVENTSTANDBYWFE => open, -- out std_logic_vector(1 downto 0);
EVENTSTANDBYWFI => open, -- out std_logic_vector(1 downto 0);
FCLKCLK => open, -- out std_logic_vector(3 downto 0);
FCLKRESETN => open, -- out std_logic_vector(3 downto 0);
FTMTF2PTRIGACK => open, -- out std_logic_vector(3 downto 0);
FTMTP2FDEBUG => open, -- out std_logic_vector(31 downto 0);
FTMTP2FTRIG => open, -- out std_logic_vector(3 downto 0);
IRQP2F => open, -- out std_logic_vector(28 downto 0);
MAXIGP0ARADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP0ARBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARESETN => open, -- out std_ulogic;
MAXIGP0ARID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0ARLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP0ARQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARVALID => open, -- out std_ulogic;
MAXIGP0AWADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP0AWBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0AWLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP0AWQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWVALID => open, -- out std_ulogic;
MAXIGP0BREADY => open, -- out std_ulogic;
MAXIGP0RREADY => open, -- out std_ulogic;
MAXIGP0WDATA => open, -- out std_logic_vector(31 downto 0);
MAXIGP0WID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0WLAST => open, -- out std_ulogic;
MAXIGP0WSTRB => open, -- out std_logic_vector(3 downto 0);
MAXIGP0WVALID => open, -- out std_ulogic;
MAXIGP1ARADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP1ARBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARESETN => open, -- out std_ulogic;
MAXIGP1ARID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1ARLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP1ARQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARVALID => open, -- out std_ulogic;
MAXIGP1AWADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP1AWBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1AWLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP1AWQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWVALID => open, -- out std_ulogic;
MAXIGP1BREADY => open, -- out std_ulogic;
MAXIGP1RREADY => open, -- out std_ulogic;
MAXIGP1WDATA => open, -- out std_logic_vector(31 downto 0);
MAXIGP1WID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1WLAST => open, -- out std_ulogic;
MAXIGP1WSTRB => open, -- out std_logic_vector(3 downto 0);
MAXIGP1WVALID => open, -- out std_ulogic;
SAXIACPARESETN => open, -- out std_ulogic;
SAXIACPARREADY => open, -- out std_ulogic;
SAXIACPAWREADY => open, -- out std_ulogic;
SAXIACPBID => open, -- out std_logic_vector(2 downto 0);
SAXIACPBRESP => open, -- out std_logic_vector(1 downto 0);
SAXIACPBVALID => open, -- out std_ulogic;
SAXIACPRDATA => open, -- out std_logic_vector(63 downto 0);
SAXIACPRID => open, -- out std_logic_vector(2 downto 0);
SAXIACPRLAST => open, -- out std_ulogic;
SAXIACPRRESP => open, -- out std_logic_vector(1 downto 0);
SAXIACPRVALID => open, -- out std_ulogic;
SAXIACPWREADY => open, -- out std_ulogic;
SAXIGP0ARESETN => open, -- out std_ulogic;
SAXIGP0ARREADY => open, -- out std_ulogic;
SAXIGP0AWREADY => open, -- out std_ulogic;
SAXIGP0BID => open, -- out std_logic_vector(5 downto 0);
SAXIGP0BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP0BVALID => open, -- out std_ulogic;
SAXIGP0RDATA => open, -- out std_logic_vector(31 downto 0);
SAXIGP0RID => open, -- out std_logic_vector(5 downto 0);
SAXIGP0RLAST => open, -- out std_ulogic;
SAXIGP0RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP0RVALID => open, -- out std_ulogic;
SAXIGP0WREADY => open, -- out std_ulogic;
SAXIGP1ARESETN => open, -- out std_ulogic;
SAXIGP1ARREADY => open, -- out std_ulogic;
SAXIGP1AWREADY => open, -- out std_ulogic;
SAXIGP1BID => open, -- out std_logic_vector(5 downto 0);
SAXIGP1BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP1BVALID => open, -- out std_ulogic;
SAXIGP1RDATA => open, -- out std_logic_vector(31 downto 0);
SAXIGP1RID => open, -- out std_logic_vector(5 downto 0);
SAXIGP1RLAST => open, -- out std_ulogic;
SAXIGP1RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP1RVALID => open, -- out std_ulogic;
SAXIGP1WREADY => open, -- out std_ulogic;
SAXIHP0ARESETN => open, -- out std_ulogic;
SAXIHP0ARREADY => open, -- out std_ulogic;
SAXIHP0AWREADY => open, -- out std_ulogic;
SAXIHP0BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP0BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP0BVALID => open, -- out std_ulogic;
SAXIHP0RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP0RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP0RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP0RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP0RLAST => open, -- out std_ulogic;
SAXIHP0RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP0RVALID => open, -- out std_ulogic;
SAXIHP0WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP0WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP0WREADY => open, -- out std_ulogic;
SAXIHP1ARESETN => open, -- out std_ulogic;
SAXIHP1ARREADY => open, -- out std_ulogic;
SAXIHP1AWREADY => open, -- out std_ulogic;
SAXIHP1BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP1BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP1BVALID => open, -- out std_ulogic;
SAXIHP1RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP1RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP1RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP1RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP1RLAST => open, -- out std_ulogic;
SAXIHP1RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP1RVALID => open, -- out std_ulogic;
SAXIHP1WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP1WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP1WREADY => open, -- out std_ulogic;
SAXIHP2ARESETN => open, -- out std_ulogic;
SAXIHP2ARREADY => open, -- out std_ulogic;
SAXIHP2AWREADY => open, -- out std_ulogic;
SAXIHP2BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP2BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP2BVALID => open, -- out std_ulogic;
SAXIHP2RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP2RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP2RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP2RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP2RLAST => open, -- out std_ulogic;
SAXIHP2RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP2RVALID => open, -- out std_ulogic;
SAXIHP2WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP2WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP2WREADY => open, -- out std_ulogic;
SAXIHP3ARESETN => open, -- out std_ulogic;
SAXIHP3ARREADY => open, -- out std_ulogic;
SAXIHP3AWREADY => open, -- out std_ulogic;
SAXIHP3BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP3BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP3BVALID => open, -- out std_ulogic;
SAXIHP3RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP3RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP3RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP3RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP3RLAST => open, -- out std_ulogic;
SAXIHP3RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP3RVALID => open, -- out std_ulogic;
SAXIHP3WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP3WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP3WREADY => open, -- out std_ulogic;
DDRA => open, -- inout std_logic_vector(14 downto 0);
DDRBA => open, -- inout std_logic_vector(2 downto 0);
DDRCASB => open, -- inout std_ulogic;
DDRCKE => open, -- inout std_ulogic;
DDRCKN => open, -- inout std_ulogic;
DDRCKP => open, -- inout std_ulogic;
DDRCSB => open, -- inout std_ulogic;
DDRDM => open, -- inout std_logic_vector(3 downto 0);
DDRDQ => open, -- inout std_logic_vector(31 downto 0);
DDRDQSN => open, -- inout std_logic_vector(3 downto 0);
DDRDQSP => open, -- inout std_logic_vector(3 downto 0);
DDRDRSTB => open, -- inout std_ulogic;
DDRODT => open, -- inout std_ulogic;
DDRRASB => open, -- inout std_ulogic;
DDRVRN => open, -- inout std_ulogic;
DDRVRP => open, -- inout std_ulogic;
DDRWEB => open, -- inout std_ulogic;
MIO => open, -- inout std_logic_vector(53 downto 0);
PSCLK => open, -- inout std_ulogic;
PSPORB => open, -- inout std_ulogic;
PSSRSTB => open, -- inout std_ulogic;
DDRARB => (others => '0'), -- in std_logic_vector(3 downto 0);
DMA0ACLK => '0', -- in std_ulogic;
DMA0DAREADY => '0', -- in std_ulogic;
DMA0DRLAST => '0', -- in std_ulogic;
DMA0DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA0DRVALID => '0', -- in std_ulogic;
DMA1ACLK => '0', -- in std_ulogic;
DMA1DAREADY => '0', -- in std_ulogic;
DMA1DRLAST => '0', -- in std_ulogic;
DMA1DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA1DRVALID => '0', -- in std_ulogic;
DMA2ACLK => '0', -- in std_ulogic;
DMA2DAREADY => '0', -- in std_ulogic;
DMA2DRLAST => '0', -- in std_ulogic;
DMA2DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA2DRVALID => '0', -- in std_ulogic;
DMA3ACLK => '0', -- in std_ulogic;
DMA3DAREADY => '0', -- in std_ulogic;
DMA3DRLAST => '0', -- in std_ulogic;
DMA3DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA3DRVALID => '0', -- in std_ulogic;
EMIOCAN0PHYRX => '0', -- in std_ulogic;
EMIOCAN1PHYRX => '0', -- in std_ulogic;
EMIOENET0EXTINTIN => '0', -- in std_ulogic;
EMIOENET0GMIICOL => '0', -- in std_ulogic;
EMIOENET0GMIICRS => '0', -- in std_ulogic;
EMIOENET0GMIIRXCLK => '0', -- in std_ulogic;
EMIOENET0GMIIRXD => (others => '0'), -- in std_logic_vector(7 downto 0);
EMIOENET0GMIIRXDV => '0', -- in std_ulogic;
EMIOENET0GMIIRXER => '0', -- in std_ulogic;
EMIOENET0GMIITXCLK => '0', -- in std_ulogic;
EMIOENET0MDIOI => '0', -- in std_ulogic;
EMIOENET1EXTINTIN => '0', -- in std_ulogic;
EMIOENET1GMIICOL => '0', -- in std_ulogic;
EMIOENET1GMIICRS => '0', -- in std_ulogic;
EMIOENET1GMIIRXCLK => '0', -- in std_ulogic;
EMIOENET1GMIIRXD => (others => '0'), -- in std_logic_vector(7 downto 0);
EMIOENET1GMIIRXDV => '0', -- in std_ulogic;
EMIOENET1GMIIRXER => '0', -- in std_ulogic;
EMIOENET1GMIITXCLK => '0', -- in std_ulogic;
EMIOENET1MDIOI => '0', -- in std_ulogic;
EMIOGPIOI => (others => '0'), -- in std_logic_vector(63 downto 0);
EMIOI2C0SCLI => i2c_scl_i, -- in std_ulogic;
EMIOI2C0SDAI => i2c_sda_i, -- in std_ulogic;
EMIOI2C1SCLI => '0', -- in std_ulogic;
EMIOI2C1SDAI => '0', -- in std_ulogic;
EMIOPJTAGTCK => '0', -- in std_ulogic;
EMIOPJTAGTDI => '0', -- in std_ulogic;
EMIOPJTAGTMS => '0', -- in std_ulogic;
EMIOSDIO0CDN => '0', -- in std_ulogic;
EMIOSDIO0CLKFB => '0', -- in std_ulogic;
EMIOSDIO0CMDI => '0', -- in std_ulogic;
EMIOSDIO0DATAI => (others => '0'), -- in std_logic_vector(3 downto 0);
EMIOSDIO0WP => '0', -- in std_ulogic;
EMIOSDIO1CDN => '0', -- in std_ulogic;
EMIOSDIO1CLKFB => '0', -- in std_ulogic;
EMIOSDIO1CMDI => '0', -- in std_ulogic;
EMIOSDIO1DATAI => (others => '0'), -- in std_logic_vector(3 downto 0);
EMIOSDIO1WP => '0', -- in std_ulogic;
EMIOSPI0MI => '0', -- in std_ulogic;
EMIOSPI0SCLKI => '0', -- in std_ulogic;
EMIOSPI0SI => '0', -- in std_ulogic;
EMIOSPI0SSIN => '0', -- in std_ulogic;
EMIOSPI1MI => '0', -- in std_ulogic;
EMIOSPI1SCLKI => '0', -- in std_ulogic;
EMIOSPI1SI => '0', -- in std_ulogic;
EMIOSPI1SSIN => '0', -- in std_ulogic;
EMIOSRAMINTIN => '0', -- in std_ulogic;
EMIOTRACECLK => '0', -- in std_ulogic;
EMIOTTC0CLKI => (others => '0'), -- in std_logic_vector(2 downto 0);
EMIOTTC1CLKI => (others => '0'), -- in std_logic_vector(2 downto 0);
EMIOUART0CTSN => '0', -- in std_ulogic;
EMIOUART0DCDN => '0', -- in std_ulogic;
EMIOUART0DSRN => '0', -- in std_ulogic;
EMIOUART0RIN => '0', -- in std_ulogic;
EMIOUART0RX => '0', -- in std_ulogic;
EMIOUART1CTSN => '0', -- in std_ulogic;
EMIOUART1DCDN => '0', -- in std_ulogic;
EMIOUART1DSRN => '0', -- in std_ulogic;
EMIOUART1RIN => '0', -- in std_ulogic;
EMIOUART1RX => '0', -- in std_ulogic;
EMIOUSB0VBUSPWRFAULT => '0', -- in std_ulogic;
EMIOUSB1VBUSPWRFAULT => '0', -- in std_ulogic;
EMIOWDTCLKI => '0', -- in std_ulogic;
EVENTEVENTI => '0', -- in std_ulogic;
FCLKCLKTRIGN => (others => '0'), -- in std_logic_vector(3 downto 0);
FPGAIDLEN => '0', -- in std_ulogic;
FTMDTRACEINATID => (others => '0'), -- in std_logic_vector(3 downto 0);
FTMDTRACEINCLOCK => '0', -- in std_ulogic;
FTMDTRACEINDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
FTMDTRACEINVALID => '0', -- in std_ulogic;
FTMTF2PDEBUG => (others => '0'), -- in std_logic_vector(31 downto 0);
FTMTF2PTRIG => (others => '0'), -- in std_logic_vector(3 downto 0);
FTMTP2FTRIGACK => (others => '0'), -- in std_logic_vector(3 downto 0);
IRQF2P => (others => '0'), -- in std_logic_vector(19 downto 0);
MAXIGP0ACLK => '0', -- in std_ulogic;
MAXIGP0ARREADY => '0', -- in std_ulogic;
MAXIGP0AWREADY => '0', -- in std_ulogic;
MAXIGP0BID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP0BRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP0BVALID => '0', -- in std_ulogic;
MAXIGP0RDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
MAXIGP0RID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP0RLAST => '0', -- in std_ulogic;
MAXIGP0RRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP0RVALID => '0', -- in std_ulogic;
MAXIGP0WREADY => '0', -- in std_ulogic;
MAXIGP1ACLK => '0', -- in std_ulogic;
MAXIGP1ARREADY => '0', -- in std_ulogic;
MAXIGP1AWREADY => '0', -- in std_ulogic;
MAXIGP1BID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP1BRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP1BVALID => '0', -- in std_ulogic;
MAXIGP1RDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
MAXIGP1RID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP1RLAST => '0', -- in std_ulogic;
MAXIGP1RRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP1RVALID => '0', -- in std_ulogic;
MAXIGP1WREADY => '0', -- in std_ulogic;
SAXIACPACLK => '0', -- in std_ulogic;
SAXIACPARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIACPARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARUSER => (others => '0'), -- in std_logic_vector(4 downto 0);
SAXIACPARVALID => '0', -- in std_ulogic;
SAXIACPAWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIACPAWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPAWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPAWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWUSER => (others => '0'), -- in std_logic_vector(4 downto 0);
SAXIACPAWVALID => '0', -- in std_ulogic;
SAXIACPBREADY => '0', -- in std_ulogic;
SAXIACPRREADY => '0', -- in std_ulogic;
SAXIACPWDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIACPWID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPWLAST => '0', -- in std_ulogic;
SAXIACPWSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIACPWVALID => '0', -- in std_ulogic;
SAXIGP0ACLK => '0', -- in std_ulogic;
SAXIGP0ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP0ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARVALID => '0', -- in std_ulogic;
SAXIGP0AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP0AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWVALID => '0', -- in std_ulogic;
SAXIGP0BREADY => '0', -- in std_ulogic;
SAXIGP0RREADY => '0', -- in std_ulogic;
SAXIGP0WDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0WLAST => '0', -- in std_ulogic;
SAXIGP0WSTRB => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0WVALID => '0', -- in std_ulogic;
SAXIGP1ACLK => '0', -- in std_ulogic;
SAXIGP1ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP1ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARVALID => '0', -- in std_ulogic;
SAXIGP1AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP1AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWVALID => '0', -- in std_ulogic;
SAXIGP1BREADY => '0', -- in std_ulogic;
SAXIGP1RREADY => '0', -- in std_ulogic;
SAXIGP1WDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1WLAST => '0', -- in std_ulogic;
SAXIGP1WSTRB => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1WVALID => '0', -- in std_ulogic;
SAXIHP0ACLK => '0', -- in std_ulogic;
SAXIHP0ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP0ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP0ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARVALID => '0', -- in std_ulogic;
SAXIHP0AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP0AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP0AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWVALID => '0', -- in std_ulogic;
SAXIHP0BREADY => '0', -- in std_ulogic;
SAXIHP0RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP0RREADY => '0', -- in std_ulogic;
SAXIHP0WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP0WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0WLAST => '0', -- in std_ulogic;
SAXIHP0WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP0WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP0WVALID => '0', -- in std_ulogic;
SAXIHP1ACLK => '0', -- in std_ulogic;
SAXIHP1ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP1ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP1ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARVALID => '0', -- in std_ulogic;
SAXIHP1AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP1AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP1AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWVALID => '0', -- in std_ulogic;
SAXIHP1BREADY => '0', -- in std_ulogic;
SAXIHP1RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP1RREADY => '0', -- in std_ulogic;
SAXIHP1WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP1WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1WLAST => '0', -- in std_ulogic;
SAXIHP1WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP1WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP1WVALID => '0', -- in std_ulogic;
SAXIHP2ACLK => '0', -- in std_ulogic;
SAXIHP2ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP2ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP2ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARVALID => '0', -- in std_ulogic;
SAXIHP2AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP2AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP2AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWVALID => '0', -- in std_ulogic;
SAXIHP2BREADY => '0', -- in std_ulogic;
SAXIHP2RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP2RREADY => '0', -- in std_ulogic;
SAXIHP2WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP2WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2WLAST => '0', -- in std_ulogic;
SAXIHP2WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP2WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP2WVALID => '0', -- in std_ulogic;
SAXIHP3ACLK => '0', -- in std_ulogic;
SAXIHP3ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP3ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP3ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARVALID => '0', -- in std_ulogic;
SAXIHP3AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP3AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP3AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWVALID => '0', -- in std_ulogic;
SAXIHP3BREADY => '0', -- in std_ulogic;
SAXIHP3RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP3RREADY => '0', -- in std_ulogic;
SAXIHP3WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP3WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3WLAST => '0', -- in std_ulogic;
SAXIHP3WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP3WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP3WVALID => '0' -- in std_ulogic
);
end RTL;
|
gpl-3.0
|
3aab56f28d3b8808ef7929baa2b57eb5
| 0.611791 | 2.573743 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
CPU/Alu.vhd
| 1 | 959 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_lib.all;
entity alu is
port( a, b : in bit16;
sel : in t_alu;
c : out bit16);
end alu;
architecture rtl of alu is
begin
aluproc: process(a, b, sel)
begin
case sel is
when alupass =>
c <= a after 1 ns;
when andOp =>
c <= a and b after 1 ns;
when orOp =>
c <= a or b after 1 ns;
when xorOp =>
c <= a xor b after 1 ns;
when notOp =>
c <= not a after 1 ns;
when plus =>
c <= a + b after 1 ns;
when alusub =>
c <= a - b after 1 ns;
when inc =>
c <= a + "0000000000000001" after 1 ns;
when dec =>
c <= a - "0000000000000001" after 1 ns;
when zero =>
c <= "0000000000000000" after 1 ns;
when others =>
c <= "0000000000000000" after 1 ns;
end case;
end process;
end rtl;
|
gpl-3.0
|
56b104fa3eedbb19aaf568d58f398479
| 0.510949 | 3.400709 | false | false | false | false |
spoorcc/realtimestagram
|
src/hsv2rgb.vhd
| 2 | 8,695 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
--============================================================================--
--! \class hsv2rgb
--! \brief Creates Red Green and Blue channels from Hue Saturation Value inputs
--!
--! Calculation of RGB to HSV
--! ---------------
--! \f[I_{RGB} = \left\{\begin{matrix}
--! \{V,V-VS,V-VSH_{LSB}\}, & H_{MSB}=0 \\
--! \{V,V-VS(1-H_{LSB}),V-VS\}, & H_{MSB}=1 \\
--! \{V-VSH_{LSB},V,V-VS\}, & H_{MSB}=2 \\
--! \{V-VS,V,V-VS(1-H_{LSB})\}, & H_{MSB}=3 \\
--! \{V-VS,V-VSH_{LSB},V\}, & H_{MSB}=4 \\
--! \{V-VS(1-H_{LSB}),V-VS,V\}, & H_{MSB}=5
--! \end{matrix}\right.\f]
--!
entity hsv2rgb is
generic (
wordsize: integer := 8 --! input image wordsize in bits
);
port (
-- inputs
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
-- inputs
pixel_hue_i: in std_logic_vector((wordsize-1) downto 0); --! hue value of pixel
pixel_sat_i: in std_logic_vector((wordsize-1) downto 0); --! saturation of pixel
pixel_val_i: in std_logic_vector((wordsize-1) downto 0); --! value of pixel
pixel_red_o: out std_logic_vector((wordsize-1) downto 0); --! red output pixel
pixel_green_o: out std_logic_vector((wordsize-1) downto 0); --! green output pixel
pixel_blue_o: out std_logic_vector((wordsize-1) downto 0) --! blue output pixel
);
-- Types for radhakrishan architecture
type s_t_v_delay is array(0 to 2) of integer range 0 to 2**(wordsize*2);
type s_t_v_min_v_delay is array(0 to 3) of integer range 0 to 2**(wordsize*2);
type v_delay is array(0 to 5) of integer range 0 to 2**wordsize;
-- Types for bailey architecture
type val_delay is array(0 to 3) of integer range 0 to 2**wordsize;
type h_msb_delay is array(0 to 3) of integer range 0 to 6;
end entity;
--============================================================================--
architecture bailey of hsv2rgb is
constant degrees60: integer := integer(ceil(real(60)*real(256)/real(360)));
signal val_times_sat: integer range 0 to 2**(wordsize*2);
signal val_times_sat_d0: integer range 0 to 2**(wordsize*2);
signal val_min_valsat: integer range 0 to 2**(wordsize*2);
signal hue_lsb: integer range 0 to 2**wordsize;
signal hue_msb: h_msb_delay;
signal one_min_hue_lsb: integer range 0 to 2**wordsize;
signal valsat_t_hue_lsb: integer range 0 to 2**(wordsize*3);
signal val_min_vs_hlsb: integer range 0 to 2**(wordsize*3);
signal val_min_valsat_scaled: integer range 0 to 2**wordsize;
signal val_min_valsat_scaled_d0: integer range 0 to 2**wordsize;
signal val: val_delay;
begin
hsv2rgb : process(clk, rst)
variable hue_i_int : integer range 0 to 2**wordsize := 0;
variable sat_i_int : integer range 0 to 2**wordsize := 0;
variable val_i_int : integer range 0 to 2**wordsize := 0;
variable hue_msb_odd : integer range 0 to 1;
variable v_min_vs_hlsb_scaled : integer range 0 to 2**wordsize := 0;
begin
if rst = '1' then
val_times_sat <= 0;
val_times_sat_d0 <= 0;
val_min_valsat <= 0;
val_min_valsat_scaled <= 0;
val_min_valsat_scaled_d0 <= 0;
hue_lsb <= 0;
hue_msb <= (others => 0);
hue_msb_odd := 0;
one_min_hue_lsb <= 0;
valsat_t_hue_lsb <= 0;
val <= (others => 0);
elsif rising_edge(clk) then
if enable = '1' then
hue_i_int := to_integer(unsigned(pixel_hue_i));
sat_i_int := to_integer(unsigned(pixel_sat_i));
val_i_int := to_integer(unsigned(pixel_val_i));
val_times_sat <= val_i_int * sat_i_int;
val_times_sat_d0 <= val_times_sat;
val(0) <= val_i_int;
val(1 to 3) <= val(0 to 2);
val_min_valsat <= 2**wordsize * val(0) - val_times_sat;
hue_lsb <= (hue_i_int mod degrees60) * 6;
hue_msb(0) <= (hue_i_int / degrees60 + 1) mod 6;
hue_msb(1 to 3) <= hue_msb(0 to 2);
hue_msb_odd := hue_msb(0) mod 2;
if hue_msb_odd = 1 then
one_min_hue_lsb <= 2**wordsize - hue_lsb;
else
one_min_hue_lsb <= hue_lsb;
end if;
valsat_t_hue_lsb <= one_min_hue_lsb * val_times_sat_d0;
val_min_vs_hlsb <= val(2) * 2**(wordsize*2) - valsat_t_hue_lsb;
v_min_vs_hlsb_scaled := val_min_vs_hlsb / 2**(wordsize*2);
val_min_valsat_scaled <= val_min_valsat / 2**wordsize;
val_min_valsat_scaled_d0 <= val_min_valsat_scaled;
-- Mux output selection
output_mux: case hue_msb(3) is
when 0 =>
pixel_red_o <= std_logic_vector(to_unsigned(val(3), wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(val_min_valsat_scaled_d0, wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(v_min_vs_hlsb_scaled, wordsize));
when 1 =>
pixel_red_o <= std_logic_vector(to_unsigned(val(3), wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(v_min_vs_hlsb_scaled, wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(val_min_valsat_scaled_d0, wordsize));
when 2 =>
pixel_red_o <= std_logic_vector(to_unsigned(v_min_vs_hlsb_scaled, wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(val(3), wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(val_min_valsat_scaled_d0, wordsize));
when 3 =>
pixel_red_o <= std_logic_vector(to_unsigned(val_min_valsat_scaled_d0, wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(val(3), wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(v_min_vs_hlsb_scaled, wordsize));
when 4 =>
pixel_red_o <= std_logic_vector(to_unsigned(val_min_valsat_scaled_d0, wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(v_min_vs_hlsb_scaled, wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(val(3), wordsize));
when 5 =>
pixel_red_o <= std_logic_vector(to_unsigned(v_min_vs_hlsb_scaled, wordsize));
pixel_green_o <= std_logic_vector(to_unsigned(val_min_valsat_scaled_d0, wordsize));
pixel_blue_o <= std_logic_vector(to_unsigned(val(3), wordsize));
when others =>
pixel_red_o <= (others => '0');
pixel_green_o <= (others => '0');
pixel_blue_o <= (others => '0');
end case output_mux;
else
pixel_red_o <= (others => '0');
pixel_green_o <= (others => '0');
pixel_blue_o <= (others => '0');
end if; -- end if enable = '1'
end if; -- end if rst = '1'
end process;
end architecture;
--============================================================================--
|
gpl-2.0
|
c46c6a999f319639d33e11bff39497c7
| 0.512133 | 3.657972 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 3/fase3.vhd
| 1 | 2,650 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity fase3 is
port( KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(0 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(0 downto 0);
CLOCK_50:in std_logic);
end fase3;
architecture Structural of fase3 is
signal s_binOut, s_binOut2, s_binOut3 : unsigned(6 downto 0);
signal s_reset, s_clk : std_logic;
signal decOut_1, decOut_2, decOut_3, decOut_4 : std_logic_vector(3 downto 0);
begin
clock_core: entity work.FreqDivider(Behavioral)
generic map(K => 12500000)
port map(clkIn =>CLOCK_50,
clkOut=> s_clk);
cliente_seguinte_core: entity work.cliente_seguinte(Behavioral)
port map(clienseg => KEY(0),
reset => SW(0),
compareTo => std_logic_vector(s_binOut2),
resetOut => s_reset,
unsigned(binOut) => s_binOut);
cliente_em_fila_core: entity work.cliente_em_fila(Behavioral)
port map(client => KEY(1),
reset => s_reset,
unsigned(binOut2) => s_binOut2,
outLed => LEDR(0),
compareTo => std_logic_vector(s_binOut));
blink_core: entity work.blink(Behavioral)
port map(binIn =>std_logic_vector(s_binOut2),
std_logic_vector(binOut)=>s_binOut3,
clk => s_clk,
outLed => LEDG(0),
reset => s_reset);
Bin2BCD_cliente_seg_core: entity work.Bin2BCDDecoder(Behavioral)
port map(inBin => std_logic_vector(s_binOut),
outBCD => decOut_1,
outBCD2 => decOut_2);
Bin7Seg_core1: entity work.bin7Seg(Behavioral)
port map( binInput => decOut_1,
decOut_n => HEX6);
Bin7Seg_core2: entity work.bin7Seg(Behavioral)
port map( binInput => decOut_2,
decOut_n => HEX7);
Bin2BCD_cliente_fila_core: entity work.Bin2BCDDecoder(Behavioral)
port map(inBin => std_logic_vector(s_binOut3),
outBCD => decOut_3,
outBCD2 => decOut_4);
Bin7Seg_core3: entity work.bin7Seg(Behavioral)
port map( binInput => decOut_3,
decOut_n => HEX4);
Bin7Seg_core4: entity work.bin7Seg(Behavioral)
port map( binInput => decOut_4,
decOut_n => HEX5);
end Structural;
|
gpl-2.0
|
d73931b7e951a396c85653bb65825c64
| 0.57283 | 3.092182 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/BasicWatchWithBugs/Problema Inicial/BasicWatchCore.vhd
| 1 | 4,260 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatchCore is
port(reset : in std_logic;
clk : in std_logic;
mode : in std_logic;
hSet : in std_logic;
mSet : in std_logic;
hTens : out std_logic_vector(6 downto 0);
hUnits : out std_logic_vector(6 downto 0);
mTens : out std_logic_vector(6 downto 0);
mUnits : out std_logic_vector(6 downto 0);
sTens : out std_logic_vector(6 downto 0);
sUnits : out std_logic_vector(6 downto 0);
sTick : out std_logic);
end BasicWatchCore;
architecture RTL of BasicWatchCore is
signal s_clk1Hz, s_clkFast : std_logic;
signal s_clk : std_logic;
signal s_sReset : std_logic;
signal s_sUnitsBin, s_sTensBin : std_logic_vector(3 downto 0);
signal s_mUnitsBin, s_mTensBin : std_logic_vector(3 downto 0);
signal s_hUnitsBin, s_hTensBin : std_logic_vector(3 downto 0);
signal s_sUnitsTerm, s_sTensTerm : std_logic;
signal s_mUnitsTerm, s_mTensTerm : std_logic;
signal s_hUnitsTerm : std_logic;
signal s_sUnitsEnb, s_sTensEnb : std_logic;
signal s_mUnitsEnb, s_mTensEnb : std_logic;
signal s_hUnitsEnb, s_hTensEnb : std_logic;
begin
clk_div_1hz : entity work.ClkDividerN(RTL)
generic map(divFactor => 40000000)
port map(clkIn => clk,
clkOut => s_clk1Hz);
clk_div_fast : entity work.ClkDividerN(RTL)
generic map(divFactor => 12500000)
port map(clkIn => clk,
clkOut => s_clkFast);
s_clk <= s_clk1Hz when (mode = '0') else
s_clkFast;
sTick <= s_clk;
s_sReset <= reset or mode;
s_sUnitsEnb <= '1';
s_units_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 9)
port map(reset => s_sReset,
clk => s_clk,
enable => s_sUnitsEnb,
valOut => s_sUnitsBin,
termCnt => s_sUnitsTerm);
s_sTensEnb <= s_sUnitsTerm or reset;
s_tens_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 5)
port map(reset => s_sReset,
clk => s_clk,
enable => s_sTensEnb,
valOut => s_sTensBin,
termCnt => s_sTensTerm);
s_mUnitsEnb <= ((s_sTensTerm and s_sUnitsTerm) and not mode) or
reset or (mode and mSet);
m_units_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 9)
port map(reset => reset,
clk => s_clk,
enable => s_mUnitsEnb,
valOut => s_mUnitsBin,
termCnt => s_mUnitsTerm);
s_mTensEnb <= (s_mUnitsTerm and s_mUnitsEnb) or reset;
m_tens_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 5)
port map(reset => reset,
clk => s_clk,
enable => s_mTensEnb,
valOut => s_mTensBin,
termCnt => s_mTensTerm);
s_hUnitsEnb <= ((s_mTensTerm and s_mTensEnb) and not mode) or
reset or (mode and hSet);
h_units_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 9)
port map(reset => reset,
clk => s_clk,
enable => s_hUnitsEnb,
valOut => s_hUnitsBin,
termCnt => s_hUnitsTerm);
s_hTensEnb <= (s_hUnitsTerm and s_hUnitsEnb) or reset;
h_tens_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 2)
port map(reset => reset,
clk => s_clk,
enable => s_hTensEnb,
valOut => s_hTensBin,
termCnt => open);
s_units_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_sUnitsBin,
decOut_n => sUnits);
s_tens_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_sTensBin,
decOut_n => sTens);
m_units_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_mUnitsBin,
decOut_n => mUnits);
m_tens_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_mTensBin,
decOut_n => mTens);
h_units_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_hUnitsBin,
decOut_n => hUnits);
h_tens_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_hTensBin,
decOut_n => hTens);
end RTL;
|
gpl-2.0
|
eb35eaedd555184a3ad2ecbb0c11f8dd
| 0.58216 | 2.95423 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/DCT1D.vhd
| 2 | 14,667 |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
--**************************************************************
--**************************************************************
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwe_s : STD_LOGIC:='0';
signal wmemsel_reg : STD_LOGIC:='0';
signal stage2_reg : STD_LOGIC:='0';
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0):=(others=>'1');
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
--**************************************************************
--**************************************************************
signal even_not_odd : std_logic:='0';
signal even_not_odd_d1 : std_logic:='0';
signal even_not_odd_d2 : std_logic:='0';
signal even_not_odd_d3 : std_logic:='0';
signal ramwe_d1 : STD_LOGIC:='0';
signal ramwe_d2 : STD_LOGIC:='0';
signal ramwe_d3 : STD_LOGIC:='0';
signal ramwe_d4 : STD_LOGIC:='0';
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal wmemsel_d1 : STD_LOGIC:='0';
signal wmemsel_d2 : STD_LOGIC:='0';
signal wmemsel_d3 : STD_LOGIC:='0';
signal wmemsel_d4 : STD_LOGIC:='0';
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
begin
--**************************************************************
--**************************************************************
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
--**************************************************************
--**************************************************************
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif rising_edge(clk) then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
bsd-2-clause
|
d35ee945ece2f869ca2a68a7ebc186aa
| 0.452444 | 3.781129 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/Adder4.vhd
| 1 | 1,449 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity Adder4 is
port( a, b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end Adder4;
architecture Structural of Adder4 is
signal carryOut : std_logic_vector(2 downto 0);
begin
bit0: entity work.FullAdder(Behavioral)
port map(a => a(0),
b => b(0),
cin => cin,
s => s(0),
cout => carryOut(0));
bit1: entity work.FullAdder(Behavioral)
port map(a => a(1),
b => b(1),
cin => carryOut(0),
s => s(1),
cout => carryOut(1));
bit2: entity work.FullAdder(Behavioral)
port map(a => a(2),
b => b(2),
cin => carryOut(1),
s => s(2),
cout => carryOut(2));
bit3: entity work.FullAdder(Behavioral)
port map(a => a(3),
b => b(3),
cin => carryOut(2),
s => s(3),
cout => cout);
end Structural;
architecture Behavioral of Adder4 is
signal s_a, s_b, s_s : unsigned(4 downto 0);
begin
s_a <= '0' & unsigned(a);
s_b <= '0' & unsigned(b);
s_s <= s_a + s_b;
s <= std_logic_vector(s_s(3 downto 0));
cout <= s_s(4);
end Behavioral;
architecture Behavioral of AddSub4 is
signal s_a, s_b, s_s : unsigned(4 downto 0);
begin
s_a <= '0' & unsigned(a);
s_b <= '0' & unsigned(b);
s_s <= (s_a + s_b) when (sub = '0') else
(s_a - s_b);
s <= std_logic_vector(s_s(3 downto 0));
cout <= s_s(4);
end Behavioral;
|
gpl-2.0
|
ce7cc342f9e434c43369d43997def677
| 0.571429 | 2.50692 | false | false | false | false |
miree/vhdl_cores
|
wishbone/wbp_pkg.vhd
| 1 | 2,105 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Useful types for working with wishbone protocol, pipelined version as described
-- in the Wishbone B4 document: https://cdn.opencores.org/downloads/wbspec_b4.pdf
package wbp_pkg is
constant c_wbp_adr_width : integer := 32;
constant c_wbp_dat_width : integer := 32;
subtype t_wbp_adr is
std_logic_vector(c_wbp_adr_width-1 downto 0);
subtype t_wbp_dat is
std_logic_vector(c_wbp_dat_width-1 downto 0);
subtype t_wbp_sel is
std_logic_vector((c_wbp_adr_width/8)-1 downto 0);
type t_wbp_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wbp_adr;
sel : t_wbp_sel;
we : std_logic;
dat : t_wbp_dat;
end record t_wbp_master_out;
subtype t_wbp_slave_in is t_wbp_master_out;
type t_wbp_master_out_array is array(natural range<>) of t_wbp_master_out;
subtype t_wbp_slave_in_array is t_wbp_master_out_array;
type t_wbp_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
dat : t_wbp_dat;
end record t_wbp_slave_out;
subtype t_wbp_master_in is t_wbp_slave_out;
type t_wbp_master_in_array is array(natural range<>) of t_wbp_master_in;
subtype t_wbp_slave_out_array is t_wbp_master_in_array;
constant c_wbp_master_out_init : t_wbp_master_out := (cyc=>'0',stb=>'0',we=>'0',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
constant c_wbp_master_in_init : t_wbp_master_in := (ack=>'0',err=>'0',rty=>'0',stall=>'0',dat=>(others=>'-'));
constant c_wbp_slave_out_init : t_wbp_slave_out := (ack=>'0',err=>'0',rty=>'0',stall=>'0',dat=>(others=>'-'));
constant c_wbp_slave_in_init : t_wbp_slave_in := (cyc=>'0',stb=>'0',we=>'0',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
type t_wbp is record
mosi : t_wbp_master_out;
miso : t_wbp_master_in;
end record;
type t_wbp_array is array(natural range<>) of t_wbp;
constant c_wbp_init : t_wbp := (c_wbp_master_out_init, c_wbp_master_in_init);
end package;
package body wbp_pkg is
end package body;
|
mit
|
5586972bb8f8a195d1f62ce8d1f496ce
| 0.63943 | 2.875683 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-B/Hex2SSegController.vhd
| 1 | 1,010 |
----------------------------------------------
-- Module Name: ClockController - switch --
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity ClockController is
port ( clock : in std_logic;
sw0 : in std_logic;
clk : out std_logic);
end ClockController;
architecture switch of ClockController is
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
constant TC1KHz : integer := 15; -- TC for 1 KHz clock
signal clk5Hz : std_logic := '0'; -- 5 Hz clock
signal clk1KHz : std_logic := '0'; -- 1 KHz clock
begin
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
c1KHz: CDiv port map (clock, TC1KHz, clk1KHz);
-- use switch to select fast or slow clk
process (sw0)
begin
case sw0 is
when '0' =>
clk <= clk1KHz;
when others =>
clk <= clk5Hz;
end case;
end process;
end switch;
|
gpl-3.0
|
d25d8c23883ec64331206db055a89841
| 0.528713 | 3.825758 | false | false | false | false |
tejainece/VHDLExperiments
|
GoldschmidtDivider/GoldschmidtDiv_tb.vhd
| 1 | 2,909 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:51:11 01/20/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/GoldschmidtDiv/GoldschmidtDiv_tb.vhd
-- Project Name: GoldschmidtDiv
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: GoldschmidtDiv
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY GoldschmidtDiv_tb IS
END GoldschmidtDiv_tb;
ARCHITECTURE behavior OF GoldschmidtDiv_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT GoldschmidtDivider
GENERIC (m: natural := 20);
PORT(
N : IN std_logic_vector(15 downto 0);
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
clk : IN std_logic;
reset : IN std_logic;
start : IN std_logic;
done : OUT std_logic
);
END COMPONENT;
--Inputs
signal N : std_logic_vector(15 downto 0) := (others => '0');
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
signal done : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: GoldschmidtDivider GENERIC MAP (m => 20)
PORT MAP (
N => N,
D => D,
Q => Q,
clk => clk,
reset => reset,
start => start,
done => done
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period;
N(15 downto 8) <= "10000001";
N(7 downto 0) <= (OTHERS => '0');
D(15 downto 8) <= "00000111";
D(7 downto 0) <= (OTHERS => '0');
start <= '1';
wait for clk_period;
start <= '0';
wait for clk_period*100;
wait;
end process;
END;
|
gpl-3.0
|
0bbf5c7e32109130dbf4dffea778bb18
| 0.578206 | 3.758398 | false | true | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/ram/ram_wb8.vhd
| 1 | 1,031 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
use work.ram_wb8_init.all;
entity ram_wb8 is
-- signal naming according to Wishbone B4 spec
Port(
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_I: in std_logic_vector(7 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic
);
end ram_wb8;
architecture Behavioral of ram_wb8 is
signal ram: store_t := RAM_INIT;
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
begin
process(CLK_I, STB_I)
variable ack: std_logic := '0';
begin
if rising_edge(CLK_I) then
ack := '0';
if STB_I = '1' then
if(WE_I = '1') then
ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0)))) <= DAT_I;
else
DAT_O <= ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0))));
end if;
ack := '1';
end if;
end if;
ACK_O <= STB_I and ack;
end process;
end Behavioral;
|
mit
|
5e878f7a56a67a96200421a85fdb8953
| 0.644035 | 2.630102 | false | false | false | false |
tejainece/VHDLExperiments
|
BoothPartProdRed/BoothPartProdRed.vhd
| 1 | 7,894 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library WORK;
use WORK.MyWork.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end BoothPartProdRed;
architecture Behavioral of BoothPartProdRed is
COMPONENT HAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
END COMPONENT;
COMPONENT FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
COMPONENT Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
END COMPONENT;
SIGNAL tempS1: STD_LOGIC_VECTOR(24 downto 2);
SIGNAL tempC1: STD_LOGIC_VECTOR(23 downto 3);
SIGNAL ctemp1: STD_LOGIC_VECTOR(21 downto 7);
SIGNAL tempS2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempC2: STD_LOGIC_VECTOR(31 downto 11);
SIGNAL ctemp2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempS3: STD_LOGIC_VECTOR(31 downto 3);
SIGNAL tempC3: STD_LOGIC_VECTOR(32 downto 4);
SIGNAL ctemp3: STD_LOGIC_VECTOR(25 downto 12);
begin
result(1 downto 0) <= prod0(1 downto 0);
result(2) <= tempS1(2);
tempS2(9 downto 8) <= prod4(9 downto 8);
tempS1(24 downto 23) <= prod3(24 downto 23);
tempS2(31) <= prod7(31);
result(3) <= tempS3(3);
result(31 downto 4) <= std_logic_vector(unsigned(tempS3(31 downto 4)) + unsigned(tempC3(31 downto 4)));
mainfor: FOR index in 2 to 31 GENERATE
if1_2to3:IF index >= 2 and index <= 3 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_4to5:IF index >= 4 and index <= 5 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
c=>prod2(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_6:IF index = 6 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => '0',
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_7tp19:IF index >= 7 and index <= 19 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_20:IF index = 20 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_21:IF index = 21 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp1(index),
b=>prod2(index),
c=>prod3(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_22:IF index = 22 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod2(index),
b=>prod3(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_10to11:IF index >= 10 and index <= 11 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if1_12to13:IF index >= 12 and index <= 13 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
c=>prod6(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_14:IF index = 14 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => '0',
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_15to26:IF index >= 15 and index <= 26 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_27to28:IF index >= 27 and index <= 28 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_29:IF index = 29 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp2(index),
b=>prod6(index),
c=>prod7(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_30:IF index = 30 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod6(index),
b=>prod7(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if2_3to7:IF index >= 3 and index <= 7 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
if2_8to10:IF index >= 8 and index <= 10 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
c=>tempS2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_11:IF index = 11 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => '0',
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_12to23:IF index >= 12 and index <= 23 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_24:IF index = 24 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => '0',
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_25:IF index = 25 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp3(index),
b=>tempS2(index),
c=>tempC2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_26to31:IF index >= 26 and index <= 31 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS2(index),
b=>tempC2(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
END GENERATE;
end Behavioral;
|
gpl-3.0
|
0770c3687115e4987958bf1afc31ec05
| 0.560426 | 2.948823 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/States.vhd
| 1 | 4,252 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:50:49 01/11/2013
-- Design Name:
-- Module Name: Estados - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity States is
port ( hcnt: in std_logic_vector(8 downto 0); -- horizontal pixel counter
vcnt: in std_logic_vector(9 downto 0);
estado:in Estados;
pintar: out std_logic;
pos_x:in std_logic_vector (8 downto 0);
pos_y: in std_logic_vector(9 downto 0)
);
end States;
architecture Behavioral of States is
signal Px: std_logic_vector(2 downto 0);
signal Py: std_logic_vector(3 downto 0);
begin
Px<=hcnt(2 downto 0);
Py<=vcnt(3 downto 0);
process(hcnt, vcnt)
begin
pintar<='0';
if hcnt >= pos_x and hcnt < pos_x + 8 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if estado=F then --fetch
if(II(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=ID then --deco
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=EX then --exe
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=MEM then --mem
if(M(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=WB then --wb
if(W(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x +8 and hcnt < pos_x + 16 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if estado=F then --fetch
if(FF(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=ID then --deco
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=EX then --exe
if(X(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=MEM then --mem
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=WB then --wb
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;
end if;
end if;
if hcnt >= pos_x + 16 and hcnt < pos_x + 24 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if estado=F then --fetch
pintar<='0';
elsif estado=ID then --deco
if(C(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=EX then --exe
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=MEM then --mem
if(M(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=WB then --wb
pintar<='0';
end if;
end if;
end if;
if hcnt >= pos_x + 24 and hcnt < pos_x + 32 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if estado=F then --fetch
pintar<='0';
elsif estado=ID then --deco
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif estado=EX then --exe
pintar<='0';
elsif estado=MEM then --mem
pintar<='0';
elsif estado=WB then --wb
pintar<='0';
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
50b57eee91e1b590080a7d6de87c356e
| 0.5635 | 3.138007 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/d2aio.vhd
| 1 | 7,464 |
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity d2aio is
port ( AEN : in std_logic;
D2A0 : in std_logic;
D2A1 : in std_logic;
D2A2 : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
BRDSEL : in std_logic;
SIOW : in std_logic;
clk : in std_logic; -- 50 MHz
BSD : in std_logic_vector (15 downto 0);
D2ACAL : out std_logic_vector (4 downto 0);
SDIN : out std_logic;
CLKIN : out std_logic;
FSIN : out std_logic;
LDAC : out std_logic;
BRDSELO : out std_logic
);
end d2aio;
architecture BEHAVIORAL of d2aio is
signal d2a0_old2 : std_logic:='0';
signal d2a0_old1 : std_logic:='0';
signal d2a1_old2 : std_logic:='0';
signal d2a1_old1 : std_logic:='0';
-- signal d2a2_old2 : std_logic:='0';
-- signal d2a2_old1 : std_logic:='0';
signal data_old2 : std_logic:='0';
signal data_old1 : std_logic:='0';
signal flag: std_logic:='0';
signal fsin1: std_logic:='1';
signal fsin2: std_logic:='1';
signal shift_data : std_logic_vector(15 downto 0):=X"0000";
signal shift_count : std_logic_vector(4 downto 0):="00000";
signal clk_count : std_logic_vector(1 downto 0):="00";
-- signal cal: std_logic_vector(4 downto 0):="00000";
-- signal cal_snatch: std_logic_vector(4 downto 0):="00000";
-- signal cal_flag: std_logic:='0';
-- signal cal1: std_logic:='0';
-- signal cal2: std_logic:='0';
-- signal cal3: std_logic:='0';
-- signal cal4: std_logic:='0';
-- signal cal5: std_logic:='0';
signal snatch: std_logic_vector(4 downto 0):="00001";
signal state1: std_logic:='0';
signal state2: std_logic:='0';
signal state3: std_logic:='0';
signal sig_CLKIN: std_logic:='0';
signal data_index: integer:=0;
type state_value is (s1,s2);
signal state: state_value:=s1;
signal next_state: state_value;
attribute keep: string;
attribute keep of AEN: signal is "true";
begin
-- D2ACAL(4 downto 0) <= cal(4 downto 0);
D2ACAL(4 downto 0) <= snatch(4 downto 0);
-- D2ACAL(4 downto 0) <= "00001";
FSIN <= fsin1 and fsin2;
CLKIN <= sig_CLKIN;
select_card: process(BRDSEL,AEN)
begin
if BRDSEL = '0' and AEN = '0' then
BRDSELO <= '0';
else
BRDSELO <= '1';
end if;
end process select_card;
-- calproc: process(clk)
-- begin
-- if rising_edge(clk) then
-- if cal_flag = '1' then
-- cal <= cal_snatch;
-- cal_flag <= '0';
-- elsif snatch = "00001" and cal1 = '0' then
-- cal_snatch <= "00000";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal1 <= '1';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "00010" and cal2 = '0' then
-- cal_snatch <= "00011";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal2 <= '1';
-- cal1 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "00100" and cal3 = '0' then
-- cal_snatch <= "00101";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal3 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal4 <= '0';
-- cal5 <= '0';
-- elsif snatch = "01000" and cal4 = '0' then
-- cal_snatch <= "01001";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal4 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal5 <= '0';
-- elsif snatch = "10000" and cal5 = '0' then
-- cal_snatch <= "10001";
-- cal <= "00001";
-- cal_flag <= '1';
-- cal5 <= '1';
-- cal1 <= '0';
-- cal2 <= '0';
-- cal3 <= '0';
-- cal4 <= '0';
-- else
-- cal_snatch <= "00001";
-- cal <= "00001";
-- cal_flag <= '1';
---- cal1 <= '0';
---- cal2 <= '0';
---- cal3 <= '0';
---- cal4 <= '0';
---- cal5 <= '0';
-- end if;
-- end if;
-- end process calproc;
dacproc: process(clk)
begin
if rising_edge(clk) then
d2a0_old2 <= d2a0_old1;
d2a0_old1 <= D2A0;
d2a1_old2 <= d2a1_old1;
d2a1_old1 <= D2A1;
-- d2a2_old2 <= d2a2_old1;
-- d2a2_old1 <= D2A2;
data_old2 <= data_old1;
data_old1 <= SIOW;
if d2a0_old2 = '0' and d2a0_old1 ='1' then
state1 <= '1';
elsif BRDSEL = '0' and AEN = '0' and SA0 = '0' and SA1 = '0' and SA2 = '0' then
if data_old2 = '0' and data_old1 = '1' then
shift_data <= BSD;
state2 <= state1;
end if;
else
if state3 = '1' then
state1 <= '0';
state2 <= '0';
end if;
end if;
if d2a1_old2 = '0' and d2a1_old1 ='1' and flag = '0' then
fsin1 <= '0';
LDAC <= '1';
elsif d2a1_old2 = '1' and d2a1_old1 ='0' and flag = '0' then
flag <= '1';
fsin1 <= '1';
LDAC <= '1';
elsif d2a1_old2 = '0' and d2a1_old1 ='1' and flag = '1' then
LDAC <= '0';
fsin1 <= '1';
elsif d2a1_old2 = '1' and d2a1_old1 ='0' and flag = '1' then
flag <= '0';
LDAC <= '1';
fsin1 <= '1';
else
fsin1 <= '1';
LDAC <= '1';
end if;
end if;
end process dacproc;
busproc: process(clk)
begin
if rising_edge(clk) then
if D2A2 = '1' and (BRDSEL = '0' and AEN = '0' and SA0 = '0' and SA1 = '0' and SA2 = '0') then
if data_old2 = '0' and data_old1 = '1' then
snatch (4 downto 0) <= BSD(4 downto 0);
-- snatch (4 downto 0) <= BSD(15 downto 11);
end if;
else
snatch(4 downto 0) <= snatch(4 downto 0);
end if;
end if;
end process busproc;
states: process(clk)
begin
if falling_edge(clk) then
state <= next_state;
end if;
end process states;
machine: process(sig_CLKIN)
begin
if rising_edge(sig_CLKIN) then
case state is
when s1 => -- latch data
shift_count <= "00000";
data_index <= 0;
state3 <= '0';
fsin2 <= '1';
SDIN <= '0';
if state1 = '1' and state2 = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
if shift_count = "10000" then
state3 <= '1';
fsin2 <= '1';
SDIN <= '0';
shift_count <= "00000";
data_index <= 0;
next_state <= s1;
else
state3 <= '0';
fsin2 <= '0';
data_index <= data_index + 1;
SDIN <= shift_data(15 - data_index);
shift_count <= shift_count + 1;
next_state <= s2;
end if;
end case;
end if;
end process machine;
DAC_CLK: process(clk)
begin
if rising_edge (clk) then
if clk_count = "00" then
sig_CLKIN <= '1';
clk_count <= clk_count + 1;
elsif clk_count = "01" then
sig_CLKIN <= '1';
clk_count <= clk_count + 1;
elsif clk_count = "10" then
sig_CLKIN <= '0';
clk_count <= clk_count + 1;
elsif clk_count = "11" then
sig_CLKIN <= '0';
clk_count <= "00";
else
sig_CLKIN <= '0';
clk_count <= "00";
end if;
end if;
end process DAC_CLK;
end BEHAVIORAL;
|
gpl-2.0
|
288e9dfbbc4f8b160ea42bdd7e79939f
| 0.479502 | 2.923619 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/AluControl.vhd
| 2 | 1,768 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:13:04 11/28/2012
-- Design Name:
-- Module Name: AluControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AluControl is port (funct: in std_logic_vector(5 downto 0);
AluOp:in std_logic_vector(2 downto 0);
--AluOp(1) es 1
AluCtr: out std_logic_vector(1 downto 0));
end AluControl;
architecture Behavioral of AluControl is
begin
process(AluOp, funct)
begin-- tipo R
AluCtr<="00";
if AluOp = "010" then
if funct= "100000" then --suma
AluCtr<="10";
elsif funct= "100010" then --resta
AluCtr<="11";
elsif funct= "100100" then --and
AluCtr<="00";
elsif funct= "100101" then --or
AluCtr<="01";
end if;
-- beq,bne,bgt,blt,subi
elsif AluOp = "001" then --resta
AluCtr<="11";
-- lw, sw, addi
elsif AluOp = "000" then --suma
AluCtr<="10";
-- andi
elsif AluOp = "100" then
AluCtr<="00";
-- ori
elsif AluOp = "101" then
AluCtr<="01";
else
AluCtr<="10";
end if;
end process;
end Behavioral;
|
gpl-2.0
|
22c30db179432ce52d433c9c87e7aac2
| 0.554299 | 3.608163 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 5/Parte 2 (TPC)/CombShiftUnit_Demo.vhd
| 1 | 599 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CombShiftUnit_Demo is
port( SW : in std_logic_vector(17 downto 0);
KEY: in std_logic_vector(2 downto 0);
LEDR: out std_logic_vector(7 downto 0));
end CombShiftUnit_Demo;
architecture Structural of CombShiftUnit_Demo is
begin
CombShiftUnit: entity work.CombShiftUnit(Behavioral)
port map(dataIn => SW(7 downto 0),
rotate => KEY(0),
dirLeft=> KEY(1),
shArith=> Key(2),
shAmount=>SW(17 downto 15),
dataOut => LEDR(7 downto 0));
end Structural;
|
gpl-2.0
|
bf5b9ddfad4e39c952ed9a3de9f53486
| 0.644407 | 3.327778 | false | false | false | false |
rbaummer/UART
|
uart_baud_rate_det.vhd
| 1 | 6,066 |
--------------------------------------------------------------------------------
--
-- File: UART Baud Rate Detection
-- Author: Rob Baummer
--
-- Description: Uses known information about transmitted byte to automatically
-- determine the baud rate. Return Char 0x0D must be transmitted for auto rate
-- detection to work.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
entity uart_baud_rate_det is
port (
--System Interface
reset : in std_logic;
sys_clk : in std_logic;
--Processor override of auto detection
baud_rate_override : in std_logic_vector(2 downto 0);
baud_rate_write : in std_logic;
--Baud detection interface
rx_byte : in std_logic_vector(7 downto 0);
rx_valid : in std_logic;
rx_frame_error : in std_logic;
baud_rate_sel : out std_logic_vector(2 downto 0);
baud_locked : out std_logic;
baud_unlocked : out std_logic
);
end uart_baud_rate_det;
architecture behavorial of uart_baud_rate_det is
type statetype is (idle, detect, locked, unlocked);
signal cs, ns : statetype;
signal cnt : std_logic_vector(1 downto 0);
signal cnt_en : std_logic;
signal cnt_rst : std_logic;
signal baud_rate_reg : std_logic_vector(2 downto 0);
signal reset_baud : std_logic;
signal test_baud : std_logic;
signal det_57_6 : std_logic;
signal det_38_4 : std_logic;
signal det_19_2 : std_logic;
signal det_14_4 : std_logic;
signal det_09_6 : std_logic;
signal good_detect : std_logic;
signal set_baud : std_logic;
signal baud_rate_write_reg : std_logic;
signal baud_rate_write_i : std_logic;
begin
baud_rate_sel <= baud_rate_reg;
--sequential process for state machine
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
cs <= idle;
else
cs <= ns;
end if;
end if;
end process;
--combinatorial processor for state machine
process (cs, rx_byte, rx_valid, rx_frame_error, good_detect, baud_rate_write_i)
begin
--default values for control signals
reset_baud <= '0';
test_baud <= '0';
baud_locked <= '0';
baud_unlocked <= '0';
set_baud <= '0';
cnt_rst <= '0';
cnt_en <= '0';
case cs is
--wait for valid or invalid rx byte
when idle =>
--if processor sets baud rate
if baud_rate_write_i = '1' then
reset_baud <= '0';
ns <= locked;
--depending on transmitter baud the RX byte could have a frame error
elsif rx_valid = '1' or rx_frame_error = '1' then
reset_baud <= '0';
ns <= detect;
else
--reset baud rate to default 57.6k
reset_baud <= '1';
ns <= idle;
end if;
--Receiver defaults to highest baud rate (57.6k)
--Known transmitted character 0x0D will have different received value
--depending on transmitter baud rate
when detect =>
--if an expected character is detected
if good_detect = '1' then
cnt_en <= '0';
set_baud <= '1';
ns <= locked;
--if not count failure, attempt 3 times before giving up
else
cnt_en <= '1';
set_baud <= '0';
if cnt = "11" then
ns <= unlocked;
else
ns <= idle;
end if;
end if;
--known character detected, save baud rate
--if 3 frame errors occur in a row reset lock
when locked =>
baud_locked <= '1';
--reset counter on a valid byte
if rx_valid = '1' then
cnt_rst <= '1';
else
cnt_rst <= '0';
end if;
--increment frame error counter on frame error
if rx_frame_error = '1' then
cnt_en <= '1';
else
cnt_en <= '0';
end if;
--resync baudrate if 3 frame errors in a row have been received
if cnt = "11" then
ns <= idle;
else
ns <= locked;
end if;
--baud rate detection failed
when unlocked =>
baud_unlocked <= '1';
--if processor manually sets baud rate goto locked
if baud_rate_write_i = '1' then
ns <= locked;
else
ns <= unlocked;
end if;
when others =>
ns <= idle;
end case;
end process;
--Counter for attempts at baud rate detection and frame errors during locked
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or cnt_rst = '1' then
cnt <= "00";
--increment when commanded
elsif cnt_en = '1' then
cnt <= cnt + "01";
end if;
end if;
end process;
--Possible values of TX_Byte = 0x0D when sent at various baud rates
det_57_6 <= '1' when rx_byte = X"0D" else '0';
--due to 38.4 being 1.5x slower than 57.6 certain bits are unstable
det_38_4 <= '1' when rx_byte(7) = '0' and rx_byte(5) = '1' and rx_byte(4) = '1' and rx_byte(2) = '0' and rx_byte(1) = '1' else '0';
det_19_2 <= '1' when rx_byte = X"1C" else '0';
det_14_4 <= '1' when rx_byte = X"78" else '0';
det_09_6 <= '1' when rx_byte = X"E0" else '0';
good_detect <= det_57_6 or det_38_4 or det_19_2 or det_14_4 or det_09_6;
--Baud rate selection register
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or reset_baud = '1' then
baud_rate_reg <= "000";
--processor override for baud rate
elsif baud_rate_write_i = '1' then
baud_rate_reg <= baud_rate_override;
--Save detected baud rate
elsif set_baud = '1' then
if det_57_6 = '1' then
baud_rate_reg <= "000";
elsif det_38_4 = '1' then
baud_rate_reg <= "001";
elsif det_19_2 = '1' then
baud_rate_reg <= "010";
elsif det_14_4 = '1' then
baud_rate_reg <= "011";
elsif det_09_6 = '1' then
baud_rate_reg <= "100";
end if;
end if;
end if;
end process;
--edge detection register for baud rate write
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
baud_rate_write_reg <= '0';
else
baud_rate_write_reg <= baud_rate_write;
end if;
end if;
end process;
--edge detection for processor baud rate write
baud_rate_write_i <= baud_rate_write and not baud_rate_write_reg;
end behavorial;
|
mit
|
234db2a13fd1b26bf6d00aafc1e8acf2
| 0.606825 | 2.96771 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/Debouncer/CounterLoadUpDown4.vhd
| 3 | 847 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterLoadUpDown4 is
port( clk : in std_logic;
updown: in std_logic;
reset : in std_logic;
enable: in std_logic;
load : in std_logic;
dataIn: in std_logic_vector(3 downto 0);
count : out std_logic_vector(3 downto 0));
end CounterLoadUpDown4;
architecture Behavioral of CounterLoadUpDown4 is
signal s_count : unsigned (3 downto 0);
begin
process(clk, enable)
begin
if (enable = '1') then
s_count <= (others => '0');
elsif(rising_edge(clk)) then
if(reset='1') then
s_count <= (others => '0');
elsif(load='1') then
s_count <= unsigned(dataIn);
elsif (updown = '1') then
s_count <= s_count + 1;
else
s_count <= s_count - 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;
|
gpl-2.0
|
0ca1dc1af3e4a42260b01392689d7976
| 0.645809 | 2.7411 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/a2dstatio.vhd
| 1 | 12,561 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : a2dstatio.vhf
-- /___/ /\ Timestamp : 02/10/2006 14:47:29
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w a2dstatio.sch a2dstatio.vhf
--Design Name: a2dstatio
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FTCE_MXILINX_a2dstatio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end FTCE_MXILINX_a2dstatio;
architecture BEHAVIORAL of FTCE_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
signal TQ : std_logic;
signal Q_DUMMY : std_logic;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q <= Q_DUMMY;
I_36_32 : XOR2
port map (I0=>T,
I1=>Q_DUMMY,
O=>TQ);
I_36_35 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>TQ,
Q=>Q_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity CB4CE_MXILINX_a2dstatio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
TC : out std_logic);
end CB4CE_MXILINX_a2dstatio;
architecture BEHAVIORAL of CB4CE_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal T2 : std_logic;
signal T3 : std_logic;
signal XLXN_1 : std_logic;
signal Q0_DUMMY : std_logic;
signal Q1_DUMMY : std_logic;
signal Q2_DUMMY : std_logic;
signal Q3_DUMMY : std_logic;
signal TC_DUMMY : std_logic;
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component FTCE_MXILINX_a2dstatio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of U0 : label is "U0_0";
attribute HU_SET of U1 : label is "U1_1";
attribute HU_SET of U2 : label is "U2_2";
attribute HU_SET of U3 : label is "U3_3";
begin
Q0 <= Q0_DUMMY;
Q1 <= Q1_DUMMY;
Q2 <= Q2_DUMMY;
Q3 <= Q3_DUMMY;
TC <= TC_DUMMY;
I_36_31 : AND4
port map (I0=>Q3_DUMMY,
I1=>Q2_DUMMY,
I2=>Q1_DUMMY,
I3=>Q0_DUMMY,
O=>TC_DUMMY);
I_36_32 : AND3
port map (I0=>Q2_DUMMY,
I1=>Q1_DUMMY,
I2=>Q0_DUMMY,
O=>T3);
I_36_33 : AND2
port map (I0=>Q1_DUMMY,
I1=>Q0_DUMMY,
O=>T2);
I_36_58 : VCC
port map (P=>XLXN_1);
I_36_67 : AND2
port map (I0=>CE,
I1=>TC_DUMMY,
O=>CEO);
U0 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>XLXN_1,
Q=>Q0_DUMMY);
U1 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>Q0_DUMMY,
Q=>Q1_DUMMY);
U2 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T2,
Q=>Q2_DUMMY);
U3 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T3,
Q=>Q3_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity BUFE16_MXILINX_a2dstatio is
port ( E : in std_logic;
I : in std_logic_vector (15 downto 0);
O : out std_logic_vector (15 downto 0));
end BUFE16_MXILINX_a2dstatio;
architecture BEHAVIORAL of BUFE16_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
begin
I_36_30 : BUFE
port map (E=>E,
I=>I(8),
O=>O(8));
I_36_31 : BUFE
port map (E=>E,
I=>I(9),
O=>O(9));
I_36_32 : BUFE
port map (E=>E,
I=>I(10),
O=>O(10));
I_36_33 : BUFE
port map (E=>E,
I=>I(11),
O=>O(11));
I_36_34 : BUFE
port map (E=>E,
I=>I(15),
O=>O(15));
I_36_35 : BUFE
port map (E=>E,
I=>I(14),
O=>O(14));
I_36_36 : BUFE
port map (E=>E,
I=>I(13),
O=>O(13));
I_36_37 : BUFE
port map (E=>E,
I=>I(12),
O=>O(12));
I_36_38 : BUFE
port map (E=>E,
I=>I(6),
O=>O(6));
I_36_39 : BUFE
port map (E=>E,
I=>I(7),
O=>O(7));
I_36_40 : BUFE
port map (E=>E,
I=>I(0),
O=>O(0));
I_36_41 : BUFE
port map (E=>E,
I=>I(1),
O=>O(1));
I_36_42 : BUFE
port map (E=>E,
I=>I(2),
O=>O(2));
I_36_43 : BUFE
port map (E=>E,
I=>I(3),
O=>O(3));
I_36_44 : BUFE
port map (E=>E,
I=>I(4),
O=>O(4));
I_36_45 : BUFE
port map (E=>E,
I=>I(5),
O=>O(5));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity a2dstatio is
port ( A2DIOEBL : in std_logic;
PLLOUT : in std_logic;
SIOR : in std_logic;
SIOW : in std_logic;
A2DRS : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
PLLDBN : out std_logic;
-- TEST45 : out std_logic;
A2DBUS : inout std_logic_vector (15 downto 0);
BSD : inout std_logic_vector (15 downto 0));
end a2dstatio;
architecture BEHAVIORAL of a2dstatio is
attribute HU_SET : string ;
attribute BOX_TYPE : string ;
-- signal Latch_A2DBUS: std_logic_vector(15 downto 0);
signal XLXN_199 : std_logic;
signal XLXN_200 : std_logic;
signal XLXN_201 : std_logic;
signal XLXN_202 : std_logic;
signal XLXN_203 : std_logic;
signal XLXN_238 : std_logic;
signal XLXN_239 : std_logic;
signal my_data : std_logic_vector(15 downto 0);
-- component FD16_MXILINX_a2dstatio
-- port ( C : in std_logic;
-- D : in std_logic_vector (15 downto 0);
-- Q : out std_logic_vector (15 downto 0));
-- end component;
component BUFE16_MXILINX_a2dstatio
port ( E : in std_logic;
I : in std_logic_vector (15 downto 0);
O : out std_logic_vector (15 downto 0));
end component;
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component CB4CE_MXILINX_a2dstatio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
TC : out std_logic);
end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
attribute HU_SET of XLXI_17 : label is "XLXI_17_4";
attribute HU_SET of XLXI_84 : label is "XLXI_84_5";
attribute HU_SET of XLXI_160 : label is "XLXI_160_6";
attribute HU_SET of XLXI_166 : label is "XLXI_166_7";
begin
process(A2DRS)
begin
if A2DRS = '1' then
my_data <= X"AAAA";
else
my_data <= X"5555";
end if;
end process;
-- MY_XLXI : FD16_MXILINX_a2dstatio
-- port map (C=>PLLOUT,
-- D(15 downto 0)=>A2DBUS(15 downto 0),
-- Q(15 downto 0)=>Latch_A2DBUS(15 downto 0));
XLXI_17 : BUFE16_MXILINX_a2dstatio
port map (E=>XLXN_238,
-- I(15 downto 0)=>X"AAAA",
I(15 downto 0)=>A2DBUS(15 downto 0),
O(15 downto 0)=>BSD(15 downto 0));
XLXI_18 : AND2
port map (I0=>SIOR,
I1=>A2DIOEBL,
O=>XLXN_238);
XLXI_84 : BUFE16_MXILINX_a2dstatio
port map (E=>XLXN_239,
-- port map (E=>FIFOCTL(1),
-- I(15 downto 0)=>my_data(15 downto 0),
I(15 downto 0)=>BSD(15 downto 0),
O(15 downto 0)=>A2DBUS(15 downto 0));
XLXI_160 : CB4CE_MXILINX_a2dstatio
port map (C=>PLLOUT,
CE=>XLXN_200,
CLR=>XLXN_199,
CEO=>open,
Q0=>open,
Q1=>open,
Q2=>open,
Q3=>XLXN_203,
TC=>open);
XLXI_161 : VCC
port map (P=>XLXN_200);
XLXI_162 : GND
port map (G=>XLXN_199);
XLXI_164 : VCC
port map (P=>XLXN_201);
XLXI_165 : GND
port map (G=>XLXN_202);
XLXI_166 : CB4CE_MXILINX_a2dstatio
port map (C=>XLXN_203,
CE=>XLXN_201,
CLR=>XLXN_202,
CEO=>open,
Q0=>open,
Q1=>open,
Q2=>PLLDBN,
Q3=>open,
TC=>open);
-- XLXI_185 : BUF
-- port map (I=>XLXN_238,
-- O=>TEST45);
XLXI_186 : AND2
port map (I0=>A2DIOEBL,
I1=>SIOW,
O=>XLXN_239);
end BEHAVIORAL;
|
gpl-2.0
|
5681202131c94fc1c29331fd4bfcdd3d
| 0.471778 | 3.396701 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/Debouncer/Debouncer_Demo.vhd
| 1 | 755 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Debouncer_Demo is
port (CLOCK_50 : in std_logic;
KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(3 downto 0));
end Debouncer_Demo;
architecture Shell of Debouncer_Demo is
signal s_clk : std_logic;
begin
Deb_core: entity work.Debouncer(Behavioral)
generic map(N => 20)
port map(clk => CLOCK_50,
dirty_In => KEY(0),
cleanOut => s_clk);
Count_core: entity work.CounterLoadUpDown4(Behavioral)
port map(clk => s_clk,
updown=> SW(0),
reset => SW(1),
enable=> SW(2),
load => SW(3),
dataIn=> SW(7 downto 4),
count => LEDR(3 downto 0));
end Shell;
|
gpl-2.0
|
e94f646812da489d9fdf0e81f9809c55
| 0.601325 | 2.785978 | false | false | false | false |
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